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Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_175 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_307
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_175( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_307 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_77 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0)
node _source_ok_T = shr(io.in.a.bits.source, 5)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h13))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits = bits(_uncommonBits_T, 4, 0)
node _T_4 = shr(io.in.a.bits.source, 5)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<5>(0h13))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0)
node _T_24 = shr(io.in.a.bits.source, 5)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<5>(0h13))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h80000c0))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h101c0)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<32>(0h800000c0))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<29>(0h100001c0)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = or(_T_37, _T_42)
node _T_44 = and(_T_32, _T_43)
node _T_45 = or(UInt<1>(0h0), _T_44)
node _T_46 = and(_T_31, _T_45)
node _T_47 = asUInt(reset)
node _T_48 = eq(_T_47, UInt<1>(0h0))
when _T_48 :
node _T_49 = eq(_T_46, UInt<1>(0h0))
when _T_49 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_46, UInt<1>(0h1), "") : assert_2
node _T_50 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_51 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_52 = and(_T_50, _T_51)
node _T_53 = or(UInt<1>(0h0), _T_52)
node _T_54 = xor(io.in.a.bits.address, UInt<28>(0h80000c0))
node _T_55 = cvt(_T_54)
node _T_56 = and(_T_55, asSInt(UInt<17>(0h101c0)))
node _T_57 = asSInt(_T_56)
node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0)))
node _T_59 = xor(io.in.a.bits.address, UInt<32>(0h800000c0))
node _T_60 = cvt(_T_59)
node _T_61 = and(_T_60, asSInt(UInt<29>(0h100001c0)))
node _T_62 = asSInt(_T_61)
node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0)))
node _T_64 = or(_T_58, _T_63)
node _T_65 = and(_T_53, _T_64)
node _T_66 = or(UInt<1>(0h0), _T_65)
node _T_67 = and(UInt<1>(0h0), _T_66)
node _T_68 = asUInt(reset)
node _T_69 = eq(_T_68, UInt<1>(0h0))
when _T_69 :
node _T_70 = eq(_T_67, UInt<1>(0h0))
when _T_70 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_67, UInt<1>(0h1), "") : assert_3
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_74 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_74, UInt<1>(0h1), "") : assert_5
node _T_78 = asUInt(reset)
node _T_79 = eq(_T_78, UInt<1>(0h0))
when _T_79 :
node _T_80 = eq(is_aligned, UInt<1>(0h0))
when _T_80 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_81 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(_T_81, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_81, UInt<1>(0h1), "") : assert_7
node _T_85 = not(io.in.a.bits.mask)
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = asUInt(reset)
node _T_88 = eq(_T_87, UInt<1>(0h0))
when _T_88 :
node _T_89 = eq(_T_86, UInt<1>(0h0))
when _T_89 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_86, UInt<1>(0h1), "") : assert_8
node _T_90 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_91 = asUInt(reset)
node _T_92 = eq(_T_91, UInt<1>(0h0))
when _T_92 :
node _T_93 = eq(_T_90, UInt<1>(0h0))
when _T_93 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_90, UInt<1>(0h1), "") : assert_9
node _T_94 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_94 :
node _T_95 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_96 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_97 = and(_T_95, _T_96)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0)
node _T_98 = shr(io.in.a.bits.source, 5)
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_101 = and(_T_99, _T_100)
node _T_102 = leq(uncommonBits_2, UInt<5>(0h13))
node _T_103 = and(_T_101, _T_102)
node _T_104 = and(_T_97, _T_103)
node _T_105 = or(UInt<1>(0h0), _T_104)
node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_107 = xor(io.in.a.bits.address, UInt<28>(0h80000c0))
node _T_108 = cvt(_T_107)
node _T_109 = and(_T_108, asSInt(UInt<17>(0h101c0)))
node _T_110 = asSInt(_T_109)
node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0)))
node _T_112 = xor(io.in.a.bits.address, UInt<32>(0h800000c0))
node _T_113 = cvt(_T_112)
node _T_114 = and(_T_113, asSInt(UInt<29>(0h100001c0)))
node _T_115 = asSInt(_T_114)
node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = or(_T_111, _T_116)
node _T_118 = and(_T_106, _T_117)
node _T_119 = or(UInt<1>(0h0), _T_118)
node _T_120 = and(_T_105, _T_119)
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_T_120, UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_120, UInt<1>(0h1), "") : assert_10
node _T_124 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_125 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_126 = and(_T_124, _T_125)
node _T_127 = or(UInt<1>(0h0), _T_126)
node _T_128 = xor(io.in.a.bits.address, UInt<28>(0h80000c0))
node _T_129 = cvt(_T_128)
node _T_130 = and(_T_129, asSInt(UInt<17>(0h101c0)))
node _T_131 = asSInt(_T_130)
node _T_132 = eq(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = xor(io.in.a.bits.address, UInt<32>(0h800000c0))
node _T_134 = cvt(_T_133)
node _T_135 = and(_T_134, asSInt(UInt<29>(0h100001c0)))
node _T_136 = asSInt(_T_135)
node _T_137 = eq(_T_136, asSInt(UInt<1>(0h0)))
node _T_138 = or(_T_132, _T_137)
node _T_139 = and(_T_127, _T_138)
node _T_140 = or(UInt<1>(0h0), _T_139)
node _T_141 = and(UInt<1>(0h0), _T_140)
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_141, UInt<1>(0h1), "") : assert_11
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_148 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_148, UInt<1>(0h1), "") : assert_13
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(is_aligned, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_155 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_155, UInt<1>(0h1), "") : assert_15
node _T_159 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_159, UInt<1>(0h1), "") : assert_16
node _T_163 = not(io.in.a.bits.mask)
node _T_164 = eq(_T_163, UInt<1>(0h0))
node _T_165 = asUInt(reset)
node _T_166 = eq(_T_165, UInt<1>(0h0))
when _T_166 :
node _T_167 = eq(_T_164, UInt<1>(0h0))
when _T_167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_164, UInt<1>(0h1), "") : assert_17
node _T_168 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_169 = asUInt(reset)
node _T_170 = eq(_T_169, UInt<1>(0h0))
when _T_170 :
node _T_171 = eq(_T_168, UInt<1>(0h0))
when _T_171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_168, UInt<1>(0h1), "") : assert_18
node _T_172 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_172 :
node _T_173 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_174 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_175 = and(_T_173, _T_174)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0)
node _T_176 = shr(io.in.a.bits.source, 5)
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_179 = and(_T_177, _T_178)
node _T_180 = leq(uncommonBits_3, UInt<5>(0h13))
node _T_181 = and(_T_179, _T_180)
node _T_182 = and(_T_175, _T_181)
node _T_183 = or(UInt<1>(0h0), _T_182)
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_183, UInt<1>(0h1), "") : assert_19
node _T_187 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_188 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_189 = and(_T_187, _T_188)
node _T_190 = or(UInt<1>(0h0), _T_189)
node _T_191 = xor(io.in.a.bits.address, UInt<28>(0h80000c0))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<17>(0h101c0)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<32>(0h800000c0))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<29>(0h100001c0)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = or(_T_195, _T_200)
node _T_202 = and(_T_190, _T_201)
node _T_203 = or(UInt<1>(0h0), _T_202)
node _T_204 = asUInt(reset)
node _T_205 = eq(_T_204, UInt<1>(0h0))
when _T_205 :
node _T_206 = eq(_T_203, UInt<1>(0h0))
when _T_206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_203, UInt<1>(0h1), "") : assert_20
node _T_207 = asUInt(reset)
node _T_208 = eq(_T_207, UInt<1>(0h0))
when _T_208 :
node _T_209 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_210 = asUInt(reset)
node _T_211 = eq(_T_210, UInt<1>(0h0))
when _T_211 :
node _T_212 = eq(is_aligned, UInt<1>(0h0))
when _T_212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_213 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_214 = asUInt(reset)
node _T_215 = eq(_T_214, UInt<1>(0h0))
when _T_215 :
node _T_216 = eq(_T_213, UInt<1>(0h0))
when _T_216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_213, UInt<1>(0h1), "") : assert_23
node _T_217 = eq(io.in.a.bits.mask, mask)
node _T_218 = asUInt(reset)
node _T_219 = eq(_T_218, UInt<1>(0h0))
when _T_219 :
node _T_220 = eq(_T_217, UInt<1>(0h0))
when _T_220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_217, UInt<1>(0h1), "") : assert_24
node _T_221 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_T_221, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_221, UInt<1>(0h1), "") : assert_25
node _T_225 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_225 :
node _T_226 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_227 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_228 = and(_T_226, _T_227)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0)
node _T_229 = shr(io.in.a.bits.source, 5)
node _T_230 = eq(_T_229, UInt<1>(0h0))
node _T_231 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_232 = and(_T_230, _T_231)
node _T_233 = leq(uncommonBits_4, UInt<5>(0h13))
node _T_234 = and(_T_232, _T_233)
node _T_235 = and(_T_228, _T_234)
node _T_236 = or(UInt<1>(0h0), _T_235)
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_239 = and(_T_237, _T_238)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h80000c0))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<17>(0h101c0)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h800000c0))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<29>(0h100001c0)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = or(_T_245, _T_250)
node _T_252 = and(_T_240, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_252)
node _T_254 = and(_T_236, _T_253)
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_254, UInt<1>(0h1), "") : assert_26
node _T_258 = asUInt(reset)
node _T_259 = eq(_T_258, UInt<1>(0h0))
when _T_259 :
node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(is_aligned, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_264 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_265 = asUInt(reset)
node _T_266 = eq(_T_265, UInt<1>(0h0))
when _T_266 :
node _T_267 = eq(_T_264, UInt<1>(0h0))
when _T_267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_264, UInt<1>(0h1), "") : assert_29
node _T_268 = eq(io.in.a.bits.mask, mask)
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(_T_268, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_268, UInt<1>(0h1), "") : assert_30
node _T_272 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_272 :
node _T_273 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_274 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_275 = and(_T_273, _T_274)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0)
node _T_276 = shr(io.in.a.bits.source, 5)
node _T_277 = eq(_T_276, UInt<1>(0h0))
node _T_278 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_279 = and(_T_277, _T_278)
node _T_280 = leq(uncommonBits_5, UInt<5>(0h13))
node _T_281 = and(_T_279, _T_280)
node _T_282 = and(_T_275, _T_281)
node _T_283 = or(UInt<1>(0h0), _T_282)
node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_285 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_286 = and(_T_284, _T_285)
node _T_287 = or(UInt<1>(0h0), _T_286)
node _T_288 = xor(io.in.a.bits.address, UInt<28>(0h80000c0))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<17>(0h101c0)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<32>(0h800000c0))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<29>(0h100001c0)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = or(_T_292, _T_297)
node _T_299 = and(_T_287, _T_298)
node _T_300 = or(UInt<1>(0h0), _T_299)
node _T_301 = and(_T_283, _T_300)
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_301, UInt<1>(0h1), "") : assert_31
node _T_305 = asUInt(reset)
node _T_306 = eq(_T_305, UInt<1>(0h0))
when _T_306 :
node _T_307 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_308 = asUInt(reset)
node _T_309 = eq(_T_308, UInt<1>(0h0))
when _T_309 :
node _T_310 = eq(is_aligned, UInt<1>(0h0))
when _T_310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_311 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_312 = asUInt(reset)
node _T_313 = eq(_T_312, UInt<1>(0h0))
when _T_313 :
node _T_314 = eq(_T_311, UInt<1>(0h0))
when _T_314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_311, UInt<1>(0h1), "") : assert_34
node _T_315 = not(mask)
node _T_316 = and(io.in.a.bits.mask, _T_315)
node _T_317 = eq(_T_316, UInt<1>(0h0))
node _T_318 = asUInt(reset)
node _T_319 = eq(_T_318, UInt<1>(0h0))
when _T_319 :
node _T_320 = eq(_T_317, UInt<1>(0h0))
when _T_320 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_317, UInt<1>(0h1), "") : assert_35
node _T_321 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_321 :
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_324 = and(_T_322, _T_323)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0)
node _T_325 = shr(io.in.a.bits.source, 5)
node _T_326 = eq(_T_325, UInt<1>(0h0))
node _T_327 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_328 = and(_T_326, _T_327)
node _T_329 = leq(uncommonBits_6, UInt<5>(0h13))
node _T_330 = and(_T_328, _T_329)
node _T_331 = and(_T_324, _T_330)
node _T_332 = or(UInt<1>(0h0), _T_331)
node _T_333 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_334 = xor(io.in.a.bits.address, UInt<28>(0h80000c0))
node _T_335 = cvt(_T_334)
node _T_336 = and(_T_335, asSInt(UInt<17>(0h101c0)))
node _T_337 = asSInt(_T_336)
node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0)))
node _T_339 = xor(io.in.a.bits.address, UInt<32>(0h800000c0))
node _T_340 = cvt(_T_339)
node _T_341 = and(_T_340, asSInt(UInt<29>(0h100001c0)))
node _T_342 = asSInt(_T_341)
node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0)))
node _T_344 = or(_T_338, _T_343)
node _T_345 = and(_T_333, _T_344)
node _T_346 = or(UInt<1>(0h0), _T_345)
node _T_347 = and(_T_332, _T_346)
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_347, UInt<1>(0h1), "") : assert_36
node _T_351 = asUInt(reset)
node _T_352 = eq(_T_351, UInt<1>(0h0))
when _T_352 :
node _T_353 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_354 = asUInt(reset)
node _T_355 = eq(_T_354, UInt<1>(0h0))
when _T_355 :
node _T_356 = eq(is_aligned, UInt<1>(0h0))
when _T_356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_357 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(_T_357, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_357, UInt<1>(0h1), "") : assert_39
node _T_361 = eq(io.in.a.bits.mask, mask)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_361, UInt<1>(0h1), "") : assert_40
node _T_365 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_365 :
node _T_366 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_367 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_368 = and(_T_366, _T_367)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0)
node _T_369 = shr(io.in.a.bits.source, 5)
node _T_370 = eq(_T_369, UInt<1>(0h0))
node _T_371 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_372 = and(_T_370, _T_371)
node _T_373 = leq(uncommonBits_7, UInt<5>(0h13))
node _T_374 = and(_T_372, _T_373)
node _T_375 = and(_T_368, _T_374)
node _T_376 = or(UInt<1>(0h0), _T_375)
node _T_377 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_378 = xor(io.in.a.bits.address, UInt<28>(0h80000c0))
node _T_379 = cvt(_T_378)
node _T_380 = and(_T_379, asSInt(UInt<17>(0h101c0)))
node _T_381 = asSInt(_T_380)
node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0)))
node _T_383 = xor(io.in.a.bits.address, UInt<32>(0h800000c0))
node _T_384 = cvt(_T_383)
node _T_385 = and(_T_384, asSInt(UInt<29>(0h100001c0)))
node _T_386 = asSInt(_T_385)
node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0)))
node _T_388 = or(_T_382, _T_387)
node _T_389 = and(_T_377, _T_388)
node _T_390 = or(UInt<1>(0h0), _T_389)
node _T_391 = and(_T_376, _T_390)
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_T_391, UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_391, UInt<1>(0h1), "") : assert_41
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(is_aligned, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_401 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_T_401, UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_401, UInt<1>(0h1), "") : assert_44
node _T_405 = eq(io.in.a.bits.mask, mask)
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_405, UInt<1>(0h1), "") : assert_45
node _T_409 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_409 :
node _T_410 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_411 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_412 = and(_T_410, _T_411)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0)
node _T_413 = shr(io.in.a.bits.source, 5)
node _T_414 = eq(_T_413, UInt<1>(0h0))
node _T_415 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_416 = and(_T_414, _T_415)
node _T_417 = leq(uncommonBits_8, UInt<5>(0h13))
node _T_418 = and(_T_416, _T_417)
node _T_419 = and(_T_412, _T_418)
node _T_420 = or(UInt<1>(0h0), _T_419)
node _T_421 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_422 = xor(io.in.a.bits.address, UInt<28>(0h80000c0))
node _T_423 = cvt(_T_422)
node _T_424 = and(_T_423, asSInt(UInt<17>(0h101c0)))
node _T_425 = asSInt(_T_424)
node _T_426 = eq(_T_425, asSInt(UInt<1>(0h0)))
node _T_427 = xor(io.in.a.bits.address, UInt<32>(0h800000c0))
node _T_428 = cvt(_T_427)
node _T_429 = and(_T_428, asSInt(UInt<29>(0h100001c0)))
node _T_430 = asSInt(_T_429)
node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0)))
node _T_432 = or(_T_426, _T_431)
node _T_433 = and(_T_421, _T_432)
node _T_434 = or(UInt<1>(0h0), _T_433)
node _T_435 = and(_T_420, _T_434)
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_435, UInt<1>(0h1), "") : assert_46
node _T_439 = asUInt(reset)
node _T_440 = eq(_T_439, UInt<1>(0h0))
when _T_440 :
node _T_441 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_442 = asUInt(reset)
node _T_443 = eq(_T_442, UInt<1>(0h0))
when _T_443 :
node _T_444 = eq(is_aligned, UInt<1>(0h0))
when _T_444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_445 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_445, UInt<1>(0h1), "") : assert_49
node _T_449 = eq(io.in.a.bits.mask, mask)
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_T_449, UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_449, UInt<1>(0h1), "") : assert_50
node _T_453 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(_T_453, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_453, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_457 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_457, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 5)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h13))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_461 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_461 :
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_465 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_466 = asUInt(reset)
node _T_467 = eq(_T_466, UInt<1>(0h0))
when _T_467 :
node _T_468 = eq(_T_465, UInt<1>(0h0))
when _T_468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_465, UInt<1>(0h1), "") : assert_54
node _T_469 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_469, UInt<1>(0h1), "") : assert_55
node _T_473 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_473, UInt<1>(0h1), "") : assert_56
node _T_477 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_477, UInt<1>(0h1), "") : assert_57
node _T_481 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_481 :
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_485 = asUInt(reset)
node _T_486 = eq(_T_485, UInt<1>(0h0))
when _T_486 :
node _T_487 = eq(sink_ok, UInt<1>(0h0))
when _T_487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_488 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_488, UInt<1>(0h1), "") : assert_60
node _T_492 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(_T_492, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_492, UInt<1>(0h1), "") : assert_61
node _T_496 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_496, UInt<1>(0h1), "") : assert_62
node _T_500 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(_T_500, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_500, UInt<1>(0h1), "") : assert_63
node _T_504 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_505 = or(UInt<1>(0h1), _T_504)
node _T_506 = asUInt(reset)
node _T_507 = eq(_T_506, UInt<1>(0h0))
when _T_507 :
node _T_508 = eq(_T_505, UInt<1>(0h0))
when _T_508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_505, UInt<1>(0h1), "") : assert_64
node _T_509 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_509 :
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_513 = asUInt(reset)
node _T_514 = eq(_T_513, UInt<1>(0h0))
when _T_514 :
node _T_515 = eq(sink_ok, UInt<1>(0h0))
when _T_515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_516 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_517 = asUInt(reset)
node _T_518 = eq(_T_517, UInt<1>(0h0))
when _T_518 :
node _T_519 = eq(_T_516, UInt<1>(0h0))
when _T_519 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_516, UInt<1>(0h1), "") : assert_67
node _T_520 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_521 = asUInt(reset)
node _T_522 = eq(_T_521, UInt<1>(0h0))
when _T_522 :
node _T_523 = eq(_T_520, UInt<1>(0h0))
when _T_523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_520, UInt<1>(0h1), "") : assert_68
node _T_524 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(_T_524, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_524, UInt<1>(0h1), "") : assert_69
node _T_528 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_529 = or(_T_528, io.in.d.bits.corrupt)
node _T_530 = asUInt(reset)
node _T_531 = eq(_T_530, UInt<1>(0h0))
when _T_531 :
node _T_532 = eq(_T_529, UInt<1>(0h0))
when _T_532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_529, UInt<1>(0h1), "") : assert_70
node _T_533 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_534 = or(UInt<1>(0h1), _T_533)
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_534, UInt<1>(0h1), "") : assert_71
node _T_538 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_538 :
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_542 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_542, UInt<1>(0h1), "") : assert_73
node _T_546 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_T_546, UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_546, UInt<1>(0h1), "") : assert_74
node _T_550 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_551 = or(UInt<1>(0h1), _T_550)
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_551, UInt<1>(0h1), "") : assert_75
node _T_555 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_555 :
node _T_556 = asUInt(reset)
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_559 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_559, UInt<1>(0h1), "") : assert_77
node _T_563 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_564 = or(_T_563, io.in.d.bits.corrupt)
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(_T_564, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_564, UInt<1>(0h1), "") : assert_78
node _T_568 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_569 = or(UInt<1>(0h1), _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_569, UInt<1>(0h1), "") : assert_79
node _T_573 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_573 :
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_577 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_577, UInt<1>(0h1), "") : assert_81
node _T_581 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_582 = asUInt(reset)
node _T_583 = eq(_T_582, UInt<1>(0h0))
when _T_583 :
node _T_584 = eq(_T_581, UInt<1>(0h0))
when _T_584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_581, UInt<1>(0h1), "") : assert_82
node _T_585 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_586 = or(UInt<1>(0h1), _T_585)
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(_T_586, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_586, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_590 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(_T_590, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_590, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_594 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_594, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_598 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_599 = asUInt(reset)
node _T_600 = eq(_T_599, UInt<1>(0h0))
when _T_600 :
node _T_601 = eq(_T_598, UInt<1>(0h0))
when _T_601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_598, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_602 = eq(a_first, UInt<1>(0h0))
node _T_603 = and(io.in.a.valid, _T_602)
when _T_603 :
node _T_604 = eq(io.in.a.bits.opcode, opcode)
node _T_605 = asUInt(reset)
node _T_606 = eq(_T_605, UInt<1>(0h0))
when _T_606 :
node _T_607 = eq(_T_604, UInt<1>(0h0))
when _T_607 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_604, UInt<1>(0h1), "") : assert_87
node _T_608 = eq(io.in.a.bits.param, param)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_608, UInt<1>(0h1), "") : assert_88
node _T_612 = eq(io.in.a.bits.size, size)
node _T_613 = asUInt(reset)
node _T_614 = eq(_T_613, UInt<1>(0h0))
when _T_614 :
node _T_615 = eq(_T_612, UInt<1>(0h0))
when _T_615 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_612, UInt<1>(0h1), "") : assert_89
node _T_616 = eq(io.in.a.bits.source, source)
node _T_617 = asUInt(reset)
node _T_618 = eq(_T_617, UInt<1>(0h0))
when _T_618 :
node _T_619 = eq(_T_616, UInt<1>(0h0))
when _T_619 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_616, UInt<1>(0h1), "") : assert_90
node _T_620 = eq(io.in.a.bits.address, address)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_620, UInt<1>(0h1), "") : assert_91
node _T_624 = and(io.in.a.ready, io.in.a.valid)
node _T_625 = and(_T_624, a_first)
when _T_625 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_626 = eq(d_first, UInt<1>(0h0))
node _T_627 = and(io.in.d.valid, _T_626)
when _T_627 :
node _T_628 = eq(io.in.d.bits.opcode, opcode_1)
node _T_629 = asUInt(reset)
node _T_630 = eq(_T_629, UInt<1>(0h0))
when _T_630 :
node _T_631 = eq(_T_628, UInt<1>(0h0))
when _T_631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_628, UInt<1>(0h1), "") : assert_92
node _T_632 = eq(io.in.d.bits.param, param_1)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_632, UInt<1>(0h1), "") : assert_93
node _T_636 = eq(io.in.d.bits.size, size_1)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_636, UInt<1>(0h1), "") : assert_94
node _T_640 = eq(io.in.d.bits.source, source_1)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_640, UInt<1>(0h1), "") : assert_95
node _T_644 = eq(io.in.d.bits.sink, sink)
node _T_645 = asUInt(reset)
node _T_646 = eq(_T_645, UInt<1>(0h0))
when _T_646 :
node _T_647 = eq(_T_644, UInt<1>(0h0))
when _T_647 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_644, UInt<1>(0h1), "") : assert_96
node _T_648 = eq(io.in.d.bits.denied, denied)
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(_T_648, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_648, UInt<1>(0h1), "") : assert_97
node _T_652 = and(io.in.d.ready, io.in.d.valid)
node _T_653 = and(_T_652, d_first)
when _T_653 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_opcodes : UInt<80>, clock, reset, UInt<80>(0h0)
regreset inflight_sizes : UInt<80>, clock, reset, UInt<80>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<20>
connect a_set, UInt<20>(0h0)
wire a_set_wo_ready : UInt<20>
connect a_set_wo_ready, UInt<20>(0h0)
wire a_opcodes_set : UInt<80>
connect a_opcodes_set, UInt<80>(0h0)
wire a_sizes_set : UInt<80>
connect a_sizes_set, UInt<80>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_654 = and(io.in.a.valid, a_first_1)
node _T_655 = and(_T_654, UInt<1>(0h1))
when _T_655 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_656 = and(io.in.a.ready, io.in.a.valid)
node _T_657 = and(_T_656, a_first_1)
node _T_658 = and(_T_657, UInt<1>(0h1))
when _T_658 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_659 = dshr(inflight, io.in.a.bits.source)
node _T_660 = bits(_T_659, 0, 0)
node _T_661 = eq(_T_660, UInt<1>(0h0))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_661, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<20>
connect d_clr, UInt<20>(0h0)
wire d_clr_wo_ready : UInt<20>
connect d_clr_wo_ready, UInt<20>(0h0)
wire d_opcodes_clr : UInt<80>
connect d_opcodes_clr, UInt<80>(0h0)
wire d_sizes_clr : UInt<80>
connect d_sizes_clr, UInt<80>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_665 = and(io.in.d.valid, d_first_1)
node _T_666 = and(_T_665, UInt<1>(0h1))
node _T_667 = eq(d_release_ack, UInt<1>(0h0))
node _T_668 = and(_T_666, _T_667)
when _T_668 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_669 = and(io.in.d.ready, io.in.d.valid)
node _T_670 = and(_T_669, d_first_1)
node _T_671 = and(_T_670, UInt<1>(0h1))
node _T_672 = eq(d_release_ack, UInt<1>(0h0))
node _T_673 = and(_T_671, _T_672)
when _T_673 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_674 = and(io.in.d.valid, d_first_1)
node _T_675 = and(_T_674, UInt<1>(0h1))
node _T_676 = eq(d_release_ack, UInt<1>(0h0))
node _T_677 = and(_T_675, _T_676)
when _T_677 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_678 = dshr(inflight, io.in.d.bits.source)
node _T_679 = bits(_T_678, 0, 0)
node _T_680 = or(_T_679, same_cycle_resp)
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(_T_680, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_680, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_684 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_685 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_686 = or(_T_684, _T_685)
node _T_687 = asUInt(reset)
node _T_688 = eq(_T_687, UInt<1>(0h0))
when _T_688 :
node _T_689 = eq(_T_686, UInt<1>(0h0))
when _T_689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_686, UInt<1>(0h1), "") : assert_100
node _T_690 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_691 = asUInt(reset)
node _T_692 = eq(_T_691, UInt<1>(0h0))
when _T_692 :
node _T_693 = eq(_T_690, UInt<1>(0h0))
when _T_693 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_690, UInt<1>(0h1), "") : assert_101
else :
node _T_694 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_695 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_696 = or(_T_694, _T_695)
node _T_697 = asUInt(reset)
node _T_698 = eq(_T_697, UInt<1>(0h0))
when _T_698 :
node _T_699 = eq(_T_696, UInt<1>(0h0))
when _T_699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_696, UInt<1>(0h1), "") : assert_102
node _T_700 = eq(io.in.d.bits.size, a_size_lookup)
node _T_701 = asUInt(reset)
node _T_702 = eq(_T_701, UInt<1>(0h0))
when _T_702 :
node _T_703 = eq(_T_700, UInt<1>(0h0))
when _T_703 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_700, UInt<1>(0h1), "") : assert_103
node _T_704 = and(io.in.d.valid, d_first_1)
node _T_705 = and(_T_704, a_first_1)
node _T_706 = and(_T_705, io.in.a.valid)
node _T_707 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_708 = and(_T_706, _T_707)
node _T_709 = eq(d_release_ack, UInt<1>(0h0))
node _T_710 = and(_T_708, _T_709)
when _T_710 :
node _T_711 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_712 = or(_T_711, io.in.a.ready)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_712, UInt<1>(0h1), "") : assert_104
node _T_716 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_717 = orr(a_set_wo_ready)
node _T_718 = eq(_T_717, UInt<1>(0h0))
node _T_719 = or(_T_716, _T_718)
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_719, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_154
node _T_723 = orr(inflight)
node _T_724 = eq(_T_723, UInt<1>(0h0))
node _T_725 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_726 = or(_T_724, _T_725)
node _T_727 = lt(watchdog, plusarg_reader.out)
node _T_728 = or(_T_726, _T_727)
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_T_728, UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_728, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_732 = and(io.in.a.ready, io.in.a.valid)
node _T_733 = and(io.in.d.ready, io.in.d.valid)
node _T_734 = or(_T_732, _T_733)
when _T_734 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_opcodes_1 : UInt<80>, clock, reset, UInt<80>(0h0)
regreset inflight_sizes_1 : UInt<80>, clock, reset, UInt<80>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<5>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<20>
connect c_set, UInt<20>(0h0)
wire c_set_wo_ready : UInt<20>
connect c_set_wo_ready, UInt<20>(0h0)
wire c_opcodes_set : UInt<80>
connect c_opcodes_set, UInt<80>(0h0)
wire c_sizes_set : UInt<80>
connect c_sizes_set, UInt<80>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_735 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_736 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_737 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_738 = and(_T_736, _T_737)
node _T_739 = and(_T_735, _T_738)
when _T_739 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<5>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_740 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_741 = and(_T_740, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<5>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_742 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_743 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_744 = and(_T_742, _T_743)
node _T_745 = and(_T_741, _T_744)
when _T_745 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<5>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_746 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_747 = bits(_T_746, 0, 0)
node _T_748 = eq(_T_747, UInt<1>(0h0))
node _T_749 = asUInt(reset)
node _T_750 = eq(_T_749, UInt<1>(0h0))
when _T_750 :
node _T_751 = eq(_T_748, UInt<1>(0h0))
when _T_751 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_748, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<20>
connect d_clr_1, UInt<20>(0h0)
wire d_clr_wo_ready_1 : UInt<20>
connect d_clr_wo_ready_1, UInt<20>(0h0)
wire d_opcodes_clr_1 : UInt<80>
connect d_opcodes_clr_1, UInt<80>(0h0)
wire d_sizes_clr_1 : UInt<80>
connect d_sizes_clr_1, UInt<80>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_752 = and(io.in.d.valid, d_first_2)
node _T_753 = and(_T_752, UInt<1>(0h1))
node _T_754 = and(_T_753, d_release_ack_1)
when _T_754 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_755 = and(io.in.d.ready, io.in.d.valid)
node _T_756 = and(_T_755, d_first_2)
node _T_757 = and(_T_756, UInt<1>(0h1))
node _T_758 = and(_T_757, d_release_ack_1)
when _T_758 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_759 = and(io.in.d.valid, d_first_2)
node _T_760 = and(_T_759, UInt<1>(0h1))
node _T_761 = and(_T_760, d_release_ack_1)
when _T_761 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_762 = dshr(inflight_1, io.in.d.bits.source)
node _T_763 = bits(_T_762, 0, 0)
node _T_764 = or(_T_763, same_cycle_resp_1)
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_T_764, UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_764, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<5>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_768 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(_T_768, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_768, UInt<1>(0h1), "") : assert_109
else :
node _T_772 = eq(io.in.d.bits.size, c_size_lookup)
node _T_773 = asUInt(reset)
node _T_774 = eq(_T_773, UInt<1>(0h0))
when _T_774 :
node _T_775 = eq(_T_772, UInt<1>(0h0))
when _T_775 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_772, UInt<1>(0h1), "") : assert_110
node _T_776 = and(io.in.d.valid, d_first_2)
node _T_777 = and(_T_776, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<5>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_778 = and(_T_777, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<5>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_779 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_780 = and(_T_778, _T_779)
node _T_781 = and(_T_780, d_release_ack_1)
node _T_782 = eq(c_probe_ack, UInt<1>(0h0))
node _T_783 = and(_T_781, _T_782)
when _T_783 :
node _T_784 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<5>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_785 = or(_T_784, _WIRE_23.ready)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_785, UInt<1>(0h1), "") : assert_111
node _T_789 = orr(c_set_wo_ready)
when _T_789 :
node _T_790 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_791 = asUInt(reset)
node _T_792 = eq(_T_791, UInt<1>(0h0))
when _T_792 :
node _T_793 = eq(_T_790, UInt<1>(0h0))
when _T_793 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_790, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_155
node _T_794 = orr(inflight_1)
node _T_795 = eq(_T_794, UInt<1>(0h0))
node _T_796 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_797 = or(_T_795, _T_796)
node _T_798 = lt(watchdog_1, plusarg_reader_1.out)
node _T_799 = or(_T_797, _T_798)
node _T_800 = asUInt(reset)
node _T_801 = eq(_T_800, UInt<1>(0h0))
when _T_801 :
node _T_802 = eq(_T_799, UInt<1>(0h0))
when _T_802 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_799, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<5>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_803 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_804 = and(io.in.d.ready, io.in.d.valid)
node _T_805 = or(_T_803, _T_804)
when _T_805 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_156 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_157 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_77( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [258:0] _c_sizes_set_T_1 = 259'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [79:0] c_opcodes_set = 80'h0; // @[Monitor.scala:740:34]
wire [79:0] c_sizes_set = 80'h0; // @[Monitor.scala:741:34]
wire [19:0] c_set = 20'h0; // @[Monitor.scala:738:34]
wire [19:0] c_set_wo_ready = 20'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_732 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_732; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_732; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_805 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_805; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_805; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_805; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [19:0] inflight; // @[Monitor.scala:614:27]
reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [79:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [19:0] a_set; // @[Monitor.scala:626:34]
wire [19:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [79:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [79:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_658 = _T_732 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_658 ? _a_set_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_658 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_658 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_658 ? _a_opcodes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_658 ? _a_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [19:0] d_clr; // @[Monitor.scala:664:34]
wire [19:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [79:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [79:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_704 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_704 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_673 = _T_805 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_673 ? _d_clr_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_673 ? _d_opcodes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_673 ? _d_sizes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [19:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [19:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [79:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [79:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [19:0] inflight_1; // @[Monitor.scala:726:35]
wire [19:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [79:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [19:0] d_clr_1; // @[Monitor.scala:774:34]
wire [19:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [79:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [79:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_776 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_776 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_758 = _T_805 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_758 ? _d_clr_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_758 ? _d_opcodes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_758 ? _d_sizes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [19:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module ExecuteController :
input clock : Clock
input reset : Reset
output io : { flip cmd : { flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}}, im2col : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, ocol : UInt<8>, krow : UInt<4>, icol : UInt<9>, irow : UInt<9>, stride : UInt<3>, channel : UInt<9>, row_turn : UInt<11>, kdim2 : UInt<8>, row_left : UInt<4>, im2col_cmd : UInt<1>, weight_double_bank : UInt<1>, weight_triple_bank : UInt<1>, start_inputting : UInt<1>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { a_im2col : { bits : UInt<32>}[4], im2col_end : UInt<1>, im2col_turn : UInt<9>, row_turn : UInt<7>, im2col_delay : UInt<1>}}}, srams : { read : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<12>, fromDMA : UInt<1>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<128>, fromDMA : UInt<1>}}}[4], write : { en : UInt<1>, addr : UInt<12>, mask : UInt<1>[16], data : UInt<128>}[4]}, acc : { read_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { scale : { bits : UInt<32>}, addr : UInt<12>, igelu_qb : { bits : UInt<32>}, igelu_qc : { bits : UInt<32>}, iexp_qln2 : { bits : UInt<32>}, iexp_qln2_inv : { bits : UInt<32>}, act : UInt<3>, full : UInt<1>, fromDMA : UInt<1>}}[1], flip read_resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { full_data : { bits : UInt<32>}[1][4], data : { bits : UInt<32>}[1][4], acc_bank_id : UInt<2>, fromDMA : UInt<1>}}[1], write : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<12>, data : { bits : UInt<32>}[1][4], acc : UInt<1>, mask : UInt<1>[16]}}[1]}, completed : { valid : UInt<1>, bits : UInt<6>}, busy : UInt<1>, counter : { event_signal : UInt<1>[45], external_values : UInt<32>[8], flip external_reset : UInt<1>}}
inst unrolled_cmd_mod of TransposePreloadUnroller
connect unrolled_cmd_mod.clock, clock
connect unrolled_cmd_mod.reset, reset
connect unrolled_cmd_mod.io.in, io.cmd
connect unrolled_cmd_mod.io.counter.external_reset, io.counter.external_reset
connect io.counter.event_signal[44], unrolled_cmd_mod.io.counter.event_signal[44]
inst cmd_q of MultiHeadedQueue_1
connect cmd_q.clock, clock
connect cmd_q.reset, reset
connect cmd_q.io.enq, unrolled_cmd_mod.io.out
connect cmd_q.io.deq.pop, UInt<1>(0h0)
regreset control_state : UInt<2>, clock, reset, UInt<2>(0h0)
reg current_dataflow : UInt<1>, clock
wire rs1s : UInt<64>[3]
connect rs1s[0], cmd_q.io.deq.bits[0].cmd.rs1
connect rs1s[1], cmd_q.io.deq.bits[1].cmd.rs1
connect rs1s[2], cmd_q.io.deq.bits[2].cmd.rs1
wire rs2s : UInt<64>[3]
connect rs2s[0], cmd_q.io.deq.bits[0].cmd.rs2
connect rs2s[1], cmd_q.io.deq.bits[1].cmd.rs2
connect rs2s[2], cmd_q.io.deq.bits[2].cmd.rs2
node DoConfig = eq(cmd_q.io.deq.bits[0].cmd.inst.funct, UInt<1>(0h0))
node _DoComputes_T = eq(cmd_q.io.deq.bits[0].cmd.inst.funct, UInt<3>(0h4))
node _DoComputes_T_1 = eq(cmd_q.io.deq.bits[0].cmd.inst.funct, UInt<3>(0h5))
node DoComputes_0 = or(_DoComputes_T, _DoComputes_T_1)
node _DoComputes_T_2 = eq(cmd_q.io.deq.bits[1].cmd.inst.funct, UInt<3>(0h4))
node _DoComputes_T_3 = eq(cmd_q.io.deq.bits[1].cmd.inst.funct, UInt<3>(0h5))
node DoComputes_1 = or(_DoComputes_T_2, _DoComputes_T_3)
node _DoComputes_T_4 = eq(cmd_q.io.deq.bits[2].cmd.inst.funct, UInt<3>(0h4))
node _DoComputes_T_5 = eq(cmd_q.io.deq.bits[2].cmd.inst.funct, UInt<3>(0h5))
node DoComputes_2 = or(_DoComputes_T_4, _DoComputes_T_5)
node DoPreloads_0 = eq(cmd_q.io.deq.bits[0].cmd.inst.funct, UInt<3>(0h6))
node DoPreloads_1 = eq(cmd_q.io.deq.bits[1].cmd.inst.funct, UInt<3>(0h6))
node DoPreloads_2 = eq(cmd_q.io.deq.bits[2].cmd.inst.funct, UInt<3>(0h6))
node preload_cmd_place = mux(DoPreloads_0, UInt<1>(0h0), UInt<1>(0h1))
node in_prop = eq(cmd_q.io.deq.bits[0].cmd.inst.funct, UInt<3>(0h4))
reg in_prop_flush : UInt<1>, clock
node _T = eq(current_dataflow, UInt<1>(0h1))
when _T :
connect in_prop_flush, UInt<1>(0h0)
regreset ocol : UInt<8>, clock, reset, UInt<8>(0h0)
regreset orow : UInt<8>, clock, reset, UInt<8>(0h0)
regreset krow : UInt<4>, clock, reset, UInt<4>(0h0)
regreset weight_stride : UInt<3>, clock, reset, UInt<3>(0h0)
regreset channel : UInt<9>, clock, reset, UInt<9>(0h0)
regreset row_turn : UInt<11>, clock, reset, UInt<11>(0h0)
regreset row_left : UInt<4>, clock, reset, UInt<4>(0h0)
regreset kdim2 : UInt<8>, clock, reset, UInt<8>(0h0)
regreset weight_double_bank : UInt<1>, clock, reset, UInt<1>(0h0)
regreset weight_triple_bank : UInt<1>, clock, reset, UInt<1>(0h0)
wire icol : UInt<9>
connect icol, UInt<9>(0h0)
wire irow : UInt<9>
connect irow, UInt<9>(0h0)
node _icol_T = sub(ocol, UInt<1>(0h1))
node _icol_T_1 = tail(_icol_T, 1)
node _icol_T_2 = mul(_icol_T_1, weight_stride)
node _icol_T_3 = add(_icol_T_2, krow)
node _icol_T_4 = tail(_icol_T_3, 1)
connect icol, _icol_T_4
node _irow_T = sub(orow, UInt<1>(0h1))
node _irow_T_1 = tail(_irow_T, 1)
node _irow_T_2 = mul(_irow_T_1, weight_stride)
node _irow_T_3 = add(_irow_T_2, krow)
node _irow_T_4 = tail(_irow_T_3, 1)
connect irow, _irow_T_4
wire im2col_turn : UInt<9>
connect im2col_turn, UInt<9>(0h0)
reg in_shift : UInt<5>, clock
reg acc_scale : { bits : UInt<32>}, clock
reg activation : UInt<3>, clock
reg a_transpose : UInt<1>, clock
reg bd_transpose : UInt<1>, clock
regreset config_initialized : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_should_be_fed_into_transposer_T = eq(current_dataflow, UInt<1>(0h0))
node _a_should_be_fed_into_transposer_T_1 = eq(a_transpose, UInt<1>(0h0))
node a_should_be_fed_into_transposer = mux(_a_should_be_fed_into_transposer_T, _a_should_be_fed_into_transposer_T_1, a_transpose)
node _a_address_place_T = eq(preload_cmd_place, UInt<1>(0h0))
node _a_address_place_T_1 = mux(a_should_be_fed_into_transposer, UInt<2>(0h2), UInt<1>(0h0))
node a_address_place = mux(_a_address_place_T, UInt<1>(0h1), _a_address_place_T_1)
node _b_should_be_fed_into_transposer_T = eq(current_dataflow, UInt<1>(0h0))
node b_should_be_fed_into_transposer = and(_b_should_be_fed_into_transposer_T, bd_transpose)
node _b_address_place_T = eq(preload_cmd_place, UInt<1>(0h0))
node _b_address_place_T_1 = mux(b_should_be_fed_into_transposer, UInt<2>(0h2), UInt<1>(0h0))
node b_address_place = mux(_b_address_place_T, UInt<1>(0h1), _b_address_place_T_1)
node _d_should_be_fed_into_transposer_T = eq(current_dataflow, UInt<1>(0h1))
node d_should_be_fed_into_transposer = and(_d_should_be_fed_into_transposer_T, bd_transpose)
node _T_1 = add(a_should_be_fed_into_transposer, b_should_be_fed_into_transposer)
node _T_2 = add(_T_1, d_should_be_fed_into_transposer)
node _T_3 = gt(_T_2, UInt<1>(0h1))
node _T_4 = and(config_initialized, _T_3)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed: Too many inputs are being fed into the single transposer we have\n at ExecuteController.scala:131 assert(!(config_initialized &&\n") : printf
assert(clock, _T_5, UInt<1>(0h1), "") : assert
node _im2col_en_T = neq(weight_stride, UInt<1>(0h0))
node im2col_en = and(UInt<1>(0h0), _im2col_en_T)
wire a_address_rs1 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _a_address_rs1_WIRE : UInt<32>
connect _a_address_rs1_WIRE, rs1s[a_address_place]
node _a_address_rs1_T = bits(_a_address_rs1_WIRE, 13, 0)
connect a_address_rs1.data, _a_address_rs1_T
node _a_address_rs1_T_1 = bits(_a_address_rs1_WIRE, 14, 14)
connect a_address_rs1.garbage_bit, _a_address_rs1_T_1
node _a_address_rs1_T_2 = bits(_a_address_rs1_WIRE, 25, 15)
connect a_address_rs1.garbage, _a_address_rs1_T_2
node _a_address_rs1_T_3 = bits(_a_address_rs1_WIRE, 28, 26)
wire _a_address_rs1_WIRE_1 : UInt<3>
connect _a_address_rs1_WIRE_1, _a_address_rs1_T_3
wire _a_address_rs1_WIRE_2 : UInt<3>
connect _a_address_rs1_WIRE_2, _a_address_rs1_WIRE_1
connect a_address_rs1.norm_cmd, _a_address_rs1_WIRE_2
node _a_address_rs1_T_4 = bits(_a_address_rs1_WIRE, 29, 29)
connect a_address_rs1.read_full_acc_row, _a_address_rs1_T_4
node _a_address_rs1_T_5 = bits(_a_address_rs1_WIRE, 30, 30)
connect a_address_rs1.accumulate, _a_address_rs1_T_5
node _a_address_rs1_T_6 = bits(_a_address_rs1_WIRE, 31, 31)
connect a_address_rs1.is_acc_addr, _a_address_rs1_T_6
wire b_address_rs2 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _b_address_rs2_WIRE : UInt<32>
connect _b_address_rs2_WIRE, rs2s[b_address_place]
node _b_address_rs2_T = bits(_b_address_rs2_WIRE, 13, 0)
connect b_address_rs2.data, _b_address_rs2_T
node _b_address_rs2_T_1 = bits(_b_address_rs2_WIRE, 14, 14)
connect b_address_rs2.garbage_bit, _b_address_rs2_T_1
node _b_address_rs2_T_2 = bits(_b_address_rs2_WIRE, 25, 15)
connect b_address_rs2.garbage, _b_address_rs2_T_2
node _b_address_rs2_T_3 = bits(_b_address_rs2_WIRE, 28, 26)
wire _b_address_rs2_WIRE_1 : UInt<3>
connect _b_address_rs2_WIRE_1, _b_address_rs2_T_3
wire _b_address_rs2_WIRE_2 : UInt<3>
connect _b_address_rs2_WIRE_2, _b_address_rs2_WIRE_1
connect b_address_rs2.norm_cmd, _b_address_rs2_WIRE_2
node _b_address_rs2_T_4 = bits(_b_address_rs2_WIRE, 29, 29)
connect b_address_rs2.read_full_acc_row, _b_address_rs2_T_4
node _b_address_rs2_T_5 = bits(_b_address_rs2_WIRE, 30, 30)
connect b_address_rs2.accumulate, _b_address_rs2_T_5
node _b_address_rs2_T_6 = bits(_b_address_rs2_WIRE, 31, 31)
connect b_address_rs2.is_acc_addr, _b_address_rs2_T_6
wire d_address_rs1 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _d_address_rs1_WIRE : UInt<32>
connect _d_address_rs1_WIRE, rs1s[preload_cmd_place]
node _d_address_rs1_T = bits(_d_address_rs1_WIRE, 13, 0)
connect d_address_rs1.data, _d_address_rs1_T
node _d_address_rs1_T_1 = bits(_d_address_rs1_WIRE, 14, 14)
connect d_address_rs1.garbage_bit, _d_address_rs1_T_1
node _d_address_rs1_T_2 = bits(_d_address_rs1_WIRE, 25, 15)
connect d_address_rs1.garbage, _d_address_rs1_T_2
node _d_address_rs1_T_3 = bits(_d_address_rs1_WIRE, 28, 26)
wire _d_address_rs1_WIRE_1 : UInt<3>
connect _d_address_rs1_WIRE_1, _d_address_rs1_T_3
wire _d_address_rs1_WIRE_2 : UInt<3>
connect _d_address_rs1_WIRE_2, _d_address_rs1_WIRE_1
connect d_address_rs1.norm_cmd, _d_address_rs1_WIRE_2
node _d_address_rs1_T_4 = bits(_d_address_rs1_WIRE, 29, 29)
connect d_address_rs1.read_full_acc_row, _d_address_rs1_T_4
node _d_address_rs1_T_5 = bits(_d_address_rs1_WIRE, 30, 30)
connect d_address_rs1.accumulate, _d_address_rs1_T_5
node _d_address_rs1_T_6 = bits(_d_address_rs1_WIRE, 31, 31)
connect d_address_rs1.is_acc_addr, _d_address_rs1_T_6
wire c_address_rs2 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _c_address_rs2_WIRE : UInt<32>
connect _c_address_rs2_WIRE, rs2s[preload_cmd_place]
node _c_address_rs2_T = bits(_c_address_rs2_WIRE, 13, 0)
connect c_address_rs2.data, _c_address_rs2_T
node _c_address_rs2_T_1 = bits(_c_address_rs2_WIRE, 14, 14)
connect c_address_rs2.garbage_bit, _c_address_rs2_T_1
node _c_address_rs2_T_2 = bits(_c_address_rs2_WIRE, 25, 15)
connect c_address_rs2.garbage, _c_address_rs2_T_2
node _c_address_rs2_T_3 = bits(_c_address_rs2_WIRE, 28, 26)
wire _c_address_rs2_WIRE_1 : UInt<3>
connect _c_address_rs2_WIRE_1, _c_address_rs2_T_3
wire _c_address_rs2_WIRE_2 : UInt<3>
connect _c_address_rs2_WIRE_2, _c_address_rs2_WIRE_1
connect c_address_rs2.norm_cmd, _c_address_rs2_WIRE_2
node _c_address_rs2_T_4 = bits(_c_address_rs2_WIRE, 29, 29)
connect c_address_rs2.read_full_acc_row, _c_address_rs2_T_4
node _c_address_rs2_T_5 = bits(_c_address_rs2_WIRE, 30, 30)
connect c_address_rs2.accumulate, _c_address_rs2_T_5
node _c_address_rs2_T_6 = bits(_c_address_rs2_WIRE, 31, 31)
connect c_address_rs2.is_acc_addr, _c_address_rs2_T_6
node _multiply_garbage_T = and(a_address_rs1.is_acc_addr, a_address_rs1.accumulate)
node _multiply_garbage_T_1 = and(_multiply_garbage_T, a_address_rs1.read_full_acc_row)
node _multiply_garbage_T_2 = andr(a_address_rs1.data)
node _multiply_garbage_T_3 = and(_multiply_garbage_T_1, _multiply_garbage_T_2)
node _multiply_garbage_T_4 = bits(a_address_rs1.garbage_bit, 0, 0)
node multiply_garbage = and(_multiply_garbage_T_3, _multiply_garbage_T_4)
node _accumulate_zeros_T = and(b_address_rs2.is_acc_addr, b_address_rs2.accumulate)
node _accumulate_zeros_T_1 = and(_accumulate_zeros_T, b_address_rs2.read_full_acc_row)
node _accumulate_zeros_T_2 = andr(b_address_rs2.data)
node _accumulate_zeros_T_3 = and(_accumulate_zeros_T_1, _accumulate_zeros_T_2)
node _accumulate_zeros_T_4 = bits(b_address_rs2.garbage_bit, 0, 0)
node accumulate_zeros = and(_accumulate_zeros_T_3, _accumulate_zeros_T_4)
node _preload_zeros_T = and(d_address_rs1.is_acc_addr, d_address_rs1.accumulate)
node _preload_zeros_T_1 = and(_preload_zeros_T, d_address_rs1.read_full_acc_row)
node _preload_zeros_T_2 = andr(d_address_rs1.data)
node _preload_zeros_T_3 = and(_preload_zeros_T_1, _preload_zeros_T_2)
node _preload_zeros_T_4 = bits(d_address_rs1.garbage_bit, 0, 0)
node preload_zeros = and(_preload_zeros_T_3, _preload_zeros_T_4)
node a_cols_default = bits(rs1s[a_address_place], 34, 32)
node a_rows_default = bits(rs1s[a_address_place], 50, 48)
node b_cols_default = bits(rs2s[b_address_place], 34, 32)
node b_rows_default = bits(rs2s[b_address_place], 50, 48)
node d_cols_default = bits(rs1s[preload_cmd_place], 34, 32)
node d_rows_default = bits(rs1s[preload_cmd_place], 50, 48)
node a_cols = mux(a_transpose, a_rows_default, a_cols_default)
node a_rows = mux(a_transpose, a_cols_default, a_rows_default)
node _b_cols_T = eq(current_dataflow, UInt<1>(0h0))
node _b_cols_T_1 = and(_b_cols_T, bd_transpose)
node b_cols = mux(_b_cols_T_1, b_rows_default, b_cols_default)
node _b_rows_T = eq(current_dataflow, UInt<1>(0h0))
node _b_rows_T_1 = and(_b_rows_T, bd_transpose)
node b_rows = mux(_b_rows_T_1, b_cols_default, b_rows_default)
node _d_cols_T = eq(current_dataflow, UInt<1>(0h1))
node _d_cols_T_1 = and(_d_cols_T, bd_transpose)
node d_cols = mux(_d_cols_T_1, d_rows_default, d_cols_default)
node _d_rows_T = eq(current_dataflow, UInt<1>(0h1))
node _d_rows_T_1 = and(_d_rows_T, bd_transpose)
node d_rows = mux(_d_rows_T_1, d_cols_default, d_rows_default)
node c_cols = bits(rs2s[preload_cmd_place], 34, 32)
node c_rows = bits(rs2s[preload_cmd_place], 50, 48)
connect io.completed.valid, UInt<1>(0h0)
invalidate io.completed.bits
reg pending_completed_rob_ids : { valid : UInt<1>, bits : UInt<6>}[2], clock
inst mesh_cntl_signals_q of Queue2_ComputeCntlSignals
connect mesh_cntl_signals_q.clock, clock
connect mesh_cntl_signals_q.reset, reset
inst mesh of MeshWithDelays
connect mesh.clock, clock
connect mesh.reset, reset
connect mesh.io.a.valid, UInt<1>(0h0)
connect mesh.io.b.valid, UInt<1>(0h0)
connect mesh.io.d.valid, UInt<1>(0h0)
node _mesh_io_req_valid_T = eq(control_state, UInt<2>(0h2))
connect mesh.io.req.valid, _mesh_io_req_valid_T
invalidate mesh.io.a.bits[0][0].bits
invalidate mesh.io.a.bits[1][0].bits
invalidate mesh.io.a.bits[2][0].bits
invalidate mesh.io.a.bits[3][0].bits
invalidate mesh.io.b.bits[0][0].bits
invalidate mesh.io.b.bits[1][0].bits
invalidate mesh.io.b.bits[2][0].bits
invalidate mesh.io.b.bits[3][0].bits
invalidate mesh.io.d.bits[0][0].bits
invalidate mesh.io.d.bits[1][0].bits
invalidate mesh.io.d.bits[2][0].bits
invalidate mesh.io.d.bits[3][0].bits
invalidate mesh.io.req.bits.tag.cols
invalidate mesh.io.req.bits.tag.rows
invalidate mesh.io.req.bits.tag.addr.data
invalidate mesh.io.req.bits.tag.addr.garbage_bit
invalidate mesh.io.req.bits.tag.addr.garbage
invalidate mesh.io.req.bits.tag.addr.norm_cmd
invalidate mesh.io.req.bits.tag.addr.read_full_acc_row
invalidate mesh.io.req.bits.tag.addr.accumulate
invalidate mesh.io.req.bits.tag.addr.is_acc_addr
invalidate mesh.io.req.bits.tag.rob_id.bits
invalidate mesh.io.req.bits.tag.rob_id.valid
connect mesh.io.req.bits.tag.cols, mesh_cntl_signals_q.io.deq.bits.c_cols
connect mesh.io.req.bits.tag.rows, mesh_cntl_signals_q.io.deq.bits.c_rows
connect mesh.io.req.bits.total_rows, UInt<3>(0h4)
node _mesh_io_req_bits_pe_control_propagate_T = eq(control_state, UInt<2>(0h2))
node _mesh_io_req_bits_pe_control_propagate_T_1 = mux(_mesh_io_req_bits_pe_control_propagate_T, in_prop_flush, mesh_cntl_signals_q.io.deq.bits.prop)
connect mesh.io.req.bits.pe_control.propagate, _mesh_io_req_bits_pe_control_propagate_T_1
connect mesh.io.req.bits.pe_control.dataflow, mesh_cntl_signals_q.io.deq.bits.dataflow
connect mesh.io.req.bits.pe_control.shift, mesh_cntl_signals_q.io.deq.bits.shift
connect mesh.io.req.bits.a_transpose, mesh_cntl_signals_q.io.deq.bits.a_transpose
connect mesh.io.req.bits.bd_transpose, mesh_cntl_signals_q.io.deq.bits.bd_transpose
connect mesh.io.req.bits.tag.rob_id.bits, mesh_cntl_signals_q.io.deq.bits.rob_id.bits
connect mesh.io.req.bits.tag.rob_id.valid, mesh_cntl_signals_q.io.deq.bits.rob_id.valid
node _mesh_io_req_bits_flush_T = eq(control_state, UInt<2>(0h2))
node _mesh_io_req_bits_flush_T_1 = eq(mesh_cntl_signals_q.io.deq.valid, UInt<1>(0h0))
node _mesh_io_req_bits_flush_T_2 = and(_mesh_io_req_bits_flush_T, _mesh_io_req_bits_flush_T_1)
node _mesh_io_req_bits_flush_T_3 = mux(_mesh_io_req_bits_flush_T_2, UInt<1>(0h1), UInt<1>(0h0))
connect mesh.io.req.bits.flush, _mesh_io_req_bits_flush_T_3
node _raw_hazard_pre_is_garbage_T = and(mesh.io.tags_in_progress[0].addr.is_acc_addr, mesh.io.tags_in_progress[0].addr.accumulate)
node _raw_hazard_pre_is_garbage_T_1 = and(_raw_hazard_pre_is_garbage_T, mesh.io.tags_in_progress[0].addr.read_full_acc_row)
node _raw_hazard_pre_is_garbage_T_2 = andr(mesh.io.tags_in_progress[0].addr.data)
node _raw_hazard_pre_is_garbage_T_3 = and(_raw_hazard_pre_is_garbage_T_1, _raw_hazard_pre_is_garbage_T_2)
node _raw_hazard_pre_is_garbage_T_4 = bits(mesh.io.tags_in_progress[0].addr.garbage_bit, 0, 0)
node raw_hazard_pre_is_garbage = and(_raw_hazard_pre_is_garbage_T_3, _raw_hazard_pre_is_garbage_T_4)
wire _raw_hazard_pre_pre_raw_haz_WIRE : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_pre_raw_haz_WIRE_1 : UInt<32>
connect _raw_hazard_pre_pre_raw_haz_WIRE_1, rs1s[0]
node _raw_hazard_pre_pre_raw_haz_T = bits(_raw_hazard_pre_pre_raw_haz_WIRE_1, 13, 0)
connect _raw_hazard_pre_pre_raw_haz_WIRE.data, _raw_hazard_pre_pre_raw_haz_T
node _raw_hazard_pre_pre_raw_haz_T_1 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_1, 14, 14)
connect _raw_hazard_pre_pre_raw_haz_WIRE.garbage_bit, _raw_hazard_pre_pre_raw_haz_T_1
node _raw_hazard_pre_pre_raw_haz_T_2 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_1, 25, 15)
connect _raw_hazard_pre_pre_raw_haz_WIRE.garbage, _raw_hazard_pre_pre_raw_haz_T_2
node _raw_hazard_pre_pre_raw_haz_T_3 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_1, 28, 26)
wire _raw_hazard_pre_pre_raw_haz_WIRE_2 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_2, _raw_hazard_pre_pre_raw_haz_T_3
wire _raw_hazard_pre_pre_raw_haz_WIRE_3 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_3, _raw_hazard_pre_pre_raw_haz_WIRE_2
connect _raw_hazard_pre_pre_raw_haz_WIRE.norm_cmd, _raw_hazard_pre_pre_raw_haz_WIRE_3
node _raw_hazard_pre_pre_raw_haz_T_4 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_1, 29, 29)
connect _raw_hazard_pre_pre_raw_haz_WIRE.read_full_acc_row, _raw_hazard_pre_pre_raw_haz_T_4
node _raw_hazard_pre_pre_raw_haz_T_5 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_1, 30, 30)
connect _raw_hazard_pre_pre_raw_haz_WIRE.accumulate, _raw_hazard_pre_pre_raw_haz_T_5
node _raw_hazard_pre_pre_raw_haz_T_6 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_1, 31, 31)
connect _raw_hazard_pre_pre_raw_haz_WIRE.is_acc_addr, _raw_hazard_pre_pre_raw_haz_T_6
node _raw_hazard_pre_pre_raw_haz_T_7 = eq(mesh.io.tags_in_progress[0].addr.is_acc_addr, _raw_hazard_pre_pre_raw_haz_WIRE.is_acc_addr)
node _raw_hazard_pre_pre_raw_haz_T_8 = eq(mesh.io.tags_in_progress[0].addr.data, _raw_hazard_pre_pre_raw_haz_WIRE.data)
node raw_hazard_pre_pre_raw_haz = and(_raw_hazard_pre_pre_raw_haz_T_7, _raw_hazard_pre_pre_raw_haz_T_8)
wire _raw_hazard_pre_mul_raw_haz_WIRE : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_1 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_1, rs1s[1]
node _raw_hazard_pre_mul_raw_haz_T = bits(_raw_hazard_pre_mul_raw_haz_WIRE_1, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE.data, _raw_hazard_pre_mul_raw_haz_T
node _raw_hazard_pre_mul_raw_haz_T_1 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_1, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_1
node _raw_hazard_pre_mul_raw_haz_T_2 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_1, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE.garbage, _raw_hazard_pre_mul_raw_haz_T_2
node _raw_hazard_pre_mul_raw_haz_T_3 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_1, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_2 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_2, _raw_hazard_pre_mul_raw_haz_T_3
wire _raw_hazard_pre_mul_raw_haz_WIRE_3 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_3, _raw_hazard_pre_mul_raw_haz_WIRE_2
connect _raw_hazard_pre_mul_raw_haz_WIRE.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_3
node _raw_hazard_pre_mul_raw_haz_T_4 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_1, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_4
node _raw_hazard_pre_mul_raw_haz_T_5 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_1, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE.accumulate, _raw_hazard_pre_mul_raw_haz_T_5
node _raw_hazard_pre_mul_raw_haz_T_6 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_1, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_6
node _raw_hazard_pre_mul_raw_haz_T_7 = eq(mesh.io.tags_in_progress[0].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_8 = eq(mesh.io.tags_in_progress[0].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE.data)
node _raw_hazard_pre_mul_raw_haz_T_9 = and(_raw_hazard_pre_mul_raw_haz_T_7, _raw_hazard_pre_mul_raw_haz_T_8)
wire _raw_hazard_pre_mul_raw_haz_WIRE_4 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_5 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_5, rs2s[1]
node _raw_hazard_pre_mul_raw_haz_T_10 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_5, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_4.data, _raw_hazard_pre_mul_raw_haz_T_10
node _raw_hazard_pre_mul_raw_haz_T_11 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_5, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_4.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_11
node _raw_hazard_pre_mul_raw_haz_T_12 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_5, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_4.garbage, _raw_hazard_pre_mul_raw_haz_T_12
node _raw_hazard_pre_mul_raw_haz_T_13 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_5, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_6 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_6, _raw_hazard_pre_mul_raw_haz_T_13
wire _raw_hazard_pre_mul_raw_haz_WIRE_7 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_7, _raw_hazard_pre_mul_raw_haz_WIRE_6
connect _raw_hazard_pre_mul_raw_haz_WIRE_4.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_7
node _raw_hazard_pre_mul_raw_haz_T_14 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_5, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_4.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_14
node _raw_hazard_pre_mul_raw_haz_T_15 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_5, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_4.accumulate, _raw_hazard_pre_mul_raw_haz_T_15
node _raw_hazard_pre_mul_raw_haz_T_16 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_5, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_4.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_16
node _raw_hazard_pre_mul_raw_haz_T_17 = eq(mesh.io.tags_in_progress[0].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_4.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_18 = eq(mesh.io.tags_in_progress[0].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_4.data)
node _raw_hazard_pre_mul_raw_haz_T_19 = and(_raw_hazard_pre_mul_raw_haz_T_17, _raw_hazard_pre_mul_raw_haz_T_18)
node raw_hazard_pre_mul_raw_haz = or(_raw_hazard_pre_mul_raw_haz_T_9, _raw_hazard_pre_mul_raw_haz_T_19)
node _raw_hazard_pre_T = eq(raw_hazard_pre_is_garbage, UInt<1>(0h0))
node _raw_hazard_pre_T_1 = or(raw_hazard_pre_pre_raw_haz, raw_hazard_pre_mul_raw_haz)
node _raw_hazard_pre_T_2 = and(_raw_hazard_pre_T, _raw_hazard_pre_T_1)
node _raw_hazard_pre_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_pre_T_4 = and(_raw_hazard_pre_T_2, _raw_hazard_pre_T_3)
node _raw_hazard_pre_is_garbage_T_5 = and(mesh.io.tags_in_progress[1].addr.is_acc_addr, mesh.io.tags_in_progress[1].addr.accumulate)
node _raw_hazard_pre_is_garbage_T_6 = and(_raw_hazard_pre_is_garbage_T_5, mesh.io.tags_in_progress[1].addr.read_full_acc_row)
node _raw_hazard_pre_is_garbage_T_7 = andr(mesh.io.tags_in_progress[1].addr.data)
node _raw_hazard_pre_is_garbage_T_8 = and(_raw_hazard_pre_is_garbage_T_6, _raw_hazard_pre_is_garbage_T_7)
node _raw_hazard_pre_is_garbage_T_9 = bits(mesh.io.tags_in_progress[1].addr.garbage_bit, 0, 0)
node raw_hazard_pre_is_garbage_1 = and(_raw_hazard_pre_is_garbage_T_8, _raw_hazard_pre_is_garbage_T_9)
wire _raw_hazard_pre_pre_raw_haz_WIRE_4 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_pre_raw_haz_WIRE_5 : UInt<32>
connect _raw_hazard_pre_pre_raw_haz_WIRE_5, rs1s[0]
node _raw_hazard_pre_pre_raw_haz_T_9 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_5, 13, 0)
connect _raw_hazard_pre_pre_raw_haz_WIRE_4.data, _raw_hazard_pre_pre_raw_haz_T_9
node _raw_hazard_pre_pre_raw_haz_T_10 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_5, 14, 14)
connect _raw_hazard_pre_pre_raw_haz_WIRE_4.garbage_bit, _raw_hazard_pre_pre_raw_haz_T_10
node _raw_hazard_pre_pre_raw_haz_T_11 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_5, 25, 15)
connect _raw_hazard_pre_pre_raw_haz_WIRE_4.garbage, _raw_hazard_pre_pre_raw_haz_T_11
node _raw_hazard_pre_pre_raw_haz_T_12 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_5, 28, 26)
wire _raw_hazard_pre_pre_raw_haz_WIRE_6 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_6, _raw_hazard_pre_pre_raw_haz_T_12
wire _raw_hazard_pre_pre_raw_haz_WIRE_7 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_7, _raw_hazard_pre_pre_raw_haz_WIRE_6
connect _raw_hazard_pre_pre_raw_haz_WIRE_4.norm_cmd, _raw_hazard_pre_pre_raw_haz_WIRE_7
node _raw_hazard_pre_pre_raw_haz_T_13 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_5, 29, 29)
connect _raw_hazard_pre_pre_raw_haz_WIRE_4.read_full_acc_row, _raw_hazard_pre_pre_raw_haz_T_13
node _raw_hazard_pre_pre_raw_haz_T_14 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_5, 30, 30)
connect _raw_hazard_pre_pre_raw_haz_WIRE_4.accumulate, _raw_hazard_pre_pre_raw_haz_T_14
node _raw_hazard_pre_pre_raw_haz_T_15 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_5, 31, 31)
connect _raw_hazard_pre_pre_raw_haz_WIRE_4.is_acc_addr, _raw_hazard_pre_pre_raw_haz_T_15
node _raw_hazard_pre_pre_raw_haz_T_16 = eq(mesh.io.tags_in_progress[1].addr.is_acc_addr, _raw_hazard_pre_pre_raw_haz_WIRE_4.is_acc_addr)
node _raw_hazard_pre_pre_raw_haz_T_17 = eq(mesh.io.tags_in_progress[1].addr.data, _raw_hazard_pre_pre_raw_haz_WIRE_4.data)
node raw_hazard_pre_pre_raw_haz_1 = and(_raw_hazard_pre_pre_raw_haz_T_16, _raw_hazard_pre_pre_raw_haz_T_17)
wire _raw_hazard_pre_mul_raw_haz_WIRE_8 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_9 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_9, rs1s[1]
node _raw_hazard_pre_mul_raw_haz_T_20 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_9, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_8.data, _raw_hazard_pre_mul_raw_haz_T_20
node _raw_hazard_pre_mul_raw_haz_T_21 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_9, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_8.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_21
node _raw_hazard_pre_mul_raw_haz_T_22 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_9, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_8.garbage, _raw_hazard_pre_mul_raw_haz_T_22
node _raw_hazard_pre_mul_raw_haz_T_23 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_9, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_10 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_10, _raw_hazard_pre_mul_raw_haz_T_23
wire _raw_hazard_pre_mul_raw_haz_WIRE_11 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_11, _raw_hazard_pre_mul_raw_haz_WIRE_10
connect _raw_hazard_pre_mul_raw_haz_WIRE_8.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_11
node _raw_hazard_pre_mul_raw_haz_T_24 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_9, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_8.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_24
node _raw_hazard_pre_mul_raw_haz_T_25 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_9, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_8.accumulate, _raw_hazard_pre_mul_raw_haz_T_25
node _raw_hazard_pre_mul_raw_haz_T_26 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_9, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_8.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_26
node _raw_hazard_pre_mul_raw_haz_T_27 = eq(mesh.io.tags_in_progress[1].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_8.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_28 = eq(mesh.io.tags_in_progress[1].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_8.data)
node _raw_hazard_pre_mul_raw_haz_T_29 = and(_raw_hazard_pre_mul_raw_haz_T_27, _raw_hazard_pre_mul_raw_haz_T_28)
wire _raw_hazard_pre_mul_raw_haz_WIRE_12 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_13 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_13, rs2s[1]
node _raw_hazard_pre_mul_raw_haz_T_30 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_13, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_12.data, _raw_hazard_pre_mul_raw_haz_T_30
node _raw_hazard_pre_mul_raw_haz_T_31 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_13, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_12.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_31
node _raw_hazard_pre_mul_raw_haz_T_32 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_13, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_12.garbage, _raw_hazard_pre_mul_raw_haz_T_32
node _raw_hazard_pre_mul_raw_haz_T_33 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_13, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_14 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_14, _raw_hazard_pre_mul_raw_haz_T_33
wire _raw_hazard_pre_mul_raw_haz_WIRE_15 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_15, _raw_hazard_pre_mul_raw_haz_WIRE_14
connect _raw_hazard_pre_mul_raw_haz_WIRE_12.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_15
node _raw_hazard_pre_mul_raw_haz_T_34 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_13, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_12.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_34
node _raw_hazard_pre_mul_raw_haz_T_35 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_13, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_12.accumulate, _raw_hazard_pre_mul_raw_haz_T_35
node _raw_hazard_pre_mul_raw_haz_T_36 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_13, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_12.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_36
node _raw_hazard_pre_mul_raw_haz_T_37 = eq(mesh.io.tags_in_progress[1].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_12.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_38 = eq(mesh.io.tags_in_progress[1].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_12.data)
node _raw_hazard_pre_mul_raw_haz_T_39 = and(_raw_hazard_pre_mul_raw_haz_T_37, _raw_hazard_pre_mul_raw_haz_T_38)
node raw_hazard_pre_mul_raw_haz_1 = or(_raw_hazard_pre_mul_raw_haz_T_29, _raw_hazard_pre_mul_raw_haz_T_39)
node _raw_hazard_pre_T_5 = eq(raw_hazard_pre_is_garbage_1, UInt<1>(0h0))
node _raw_hazard_pre_T_6 = or(raw_hazard_pre_pre_raw_haz_1, raw_hazard_pre_mul_raw_haz_1)
node _raw_hazard_pre_T_7 = and(_raw_hazard_pre_T_5, _raw_hazard_pre_T_6)
node _raw_hazard_pre_T_8 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_pre_T_9 = and(_raw_hazard_pre_T_7, _raw_hazard_pre_T_8)
node _raw_hazard_pre_is_garbage_T_10 = and(mesh.io.tags_in_progress[2].addr.is_acc_addr, mesh.io.tags_in_progress[2].addr.accumulate)
node _raw_hazard_pre_is_garbage_T_11 = and(_raw_hazard_pre_is_garbage_T_10, mesh.io.tags_in_progress[2].addr.read_full_acc_row)
node _raw_hazard_pre_is_garbage_T_12 = andr(mesh.io.tags_in_progress[2].addr.data)
node _raw_hazard_pre_is_garbage_T_13 = and(_raw_hazard_pre_is_garbage_T_11, _raw_hazard_pre_is_garbage_T_12)
node _raw_hazard_pre_is_garbage_T_14 = bits(mesh.io.tags_in_progress[2].addr.garbage_bit, 0, 0)
node raw_hazard_pre_is_garbage_2 = and(_raw_hazard_pre_is_garbage_T_13, _raw_hazard_pre_is_garbage_T_14)
wire _raw_hazard_pre_pre_raw_haz_WIRE_8 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_pre_raw_haz_WIRE_9 : UInt<32>
connect _raw_hazard_pre_pre_raw_haz_WIRE_9, rs1s[0]
node _raw_hazard_pre_pre_raw_haz_T_18 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_9, 13, 0)
connect _raw_hazard_pre_pre_raw_haz_WIRE_8.data, _raw_hazard_pre_pre_raw_haz_T_18
node _raw_hazard_pre_pre_raw_haz_T_19 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_9, 14, 14)
connect _raw_hazard_pre_pre_raw_haz_WIRE_8.garbage_bit, _raw_hazard_pre_pre_raw_haz_T_19
node _raw_hazard_pre_pre_raw_haz_T_20 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_9, 25, 15)
connect _raw_hazard_pre_pre_raw_haz_WIRE_8.garbage, _raw_hazard_pre_pre_raw_haz_T_20
node _raw_hazard_pre_pre_raw_haz_T_21 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_9, 28, 26)
wire _raw_hazard_pre_pre_raw_haz_WIRE_10 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_10, _raw_hazard_pre_pre_raw_haz_T_21
wire _raw_hazard_pre_pre_raw_haz_WIRE_11 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_11, _raw_hazard_pre_pre_raw_haz_WIRE_10
connect _raw_hazard_pre_pre_raw_haz_WIRE_8.norm_cmd, _raw_hazard_pre_pre_raw_haz_WIRE_11
node _raw_hazard_pre_pre_raw_haz_T_22 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_9, 29, 29)
connect _raw_hazard_pre_pre_raw_haz_WIRE_8.read_full_acc_row, _raw_hazard_pre_pre_raw_haz_T_22
node _raw_hazard_pre_pre_raw_haz_T_23 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_9, 30, 30)
connect _raw_hazard_pre_pre_raw_haz_WIRE_8.accumulate, _raw_hazard_pre_pre_raw_haz_T_23
node _raw_hazard_pre_pre_raw_haz_T_24 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_9, 31, 31)
connect _raw_hazard_pre_pre_raw_haz_WIRE_8.is_acc_addr, _raw_hazard_pre_pre_raw_haz_T_24
node _raw_hazard_pre_pre_raw_haz_T_25 = eq(mesh.io.tags_in_progress[2].addr.is_acc_addr, _raw_hazard_pre_pre_raw_haz_WIRE_8.is_acc_addr)
node _raw_hazard_pre_pre_raw_haz_T_26 = eq(mesh.io.tags_in_progress[2].addr.data, _raw_hazard_pre_pre_raw_haz_WIRE_8.data)
node raw_hazard_pre_pre_raw_haz_2 = and(_raw_hazard_pre_pre_raw_haz_T_25, _raw_hazard_pre_pre_raw_haz_T_26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_16 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_17 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_17, rs1s[1]
node _raw_hazard_pre_mul_raw_haz_T_40 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_17, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_16.data, _raw_hazard_pre_mul_raw_haz_T_40
node _raw_hazard_pre_mul_raw_haz_T_41 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_17, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_16.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_41
node _raw_hazard_pre_mul_raw_haz_T_42 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_17, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_16.garbage, _raw_hazard_pre_mul_raw_haz_T_42
node _raw_hazard_pre_mul_raw_haz_T_43 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_17, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_18 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_18, _raw_hazard_pre_mul_raw_haz_T_43
wire _raw_hazard_pre_mul_raw_haz_WIRE_19 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_19, _raw_hazard_pre_mul_raw_haz_WIRE_18
connect _raw_hazard_pre_mul_raw_haz_WIRE_16.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_19
node _raw_hazard_pre_mul_raw_haz_T_44 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_17, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_16.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_44
node _raw_hazard_pre_mul_raw_haz_T_45 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_17, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_16.accumulate, _raw_hazard_pre_mul_raw_haz_T_45
node _raw_hazard_pre_mul_raw_haz_T_46 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_17, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_16.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_46
node _raw_hazard_pre_mul_raw_haz_T_47 = eq(mesh.io.tags_in_progress[2].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_16.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_48 = eq(mesh.io.tags_in_progress[2].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_16.data)
node _raw_hazard_pre_mul_raw_haz_T_49 = and(_raw_hazard_pre_mul_raw_haz_T_47, _raw_hazard_pre_mul_raw_haz_T_48)
wire _raw_hazard_pre_mul_raw_haz_WIRE_20 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_21 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_21, rs2s[1]
node _raw_hazard_pre_mul_raw_haz_T_50 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_21, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_20.data, _raw_hazard_pre_mul_raw_haz_T_50
node _raw_hazard_pre_mul_raw_haz_T_51 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_21, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_20.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_51
node _raw_hazard_pre_mul_raw_haz_T_52 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_21, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_20.garbage, _raw_hazard_pre_mul_raw_haz_T_52
node _raw_hazard_pre_mul_raw_haz_T_53 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_21, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_22 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_22, _raw_hazard_pre_mul_raw_haz_T_53
wire _raw_hazard_pre_mul_raw_haz_WIRE_23 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_23, _raw_hazard_pre_mul_raw_haz_WIRE_22
connect _raw_hazard_pre_mul_raw_haz_WIRE_20.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_23
node _raw_hazard_pre_mul_raw_haz_T_54 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_21, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_20.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_54
node _raw_hazard_pre_mul_raw_haz_T_55 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_21, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_20.accumulate, _raw_hazard_pre_mul_raw_haz_T_55
node _raw_hazard_pre_mul_raw_haz_T_56 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_21, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_20.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_56
node _raw_hazard_pre_mul_raw_haz_T_57 = eq(mesh.io.tags_in_progress[2].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_20.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_58 = eq(mesh.io.tags_in_progress[2].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_20.data)
node _raw_hazard_pre_mul_raw_haz_T_59 = and(_raw_hazard_pre_mul_raw_haz_T_57, _raw_hazard_pre_mul_raw_haz_T_58)
node raw_hazard_pre_mul_raw_haz_2 = or(_raw_hazard_pre_mul_raw_haz_T_49, _raw_hazard_pre_mul_raw_haz_T_59)
node _raw_hazard_pre_T_10 = eq(raw_hazard_pre_is_garbage_2, UInt<1>(0h0))
node _raw_hazard_pre_T_11 = or(raw_hazard_pre_pre_raw_haz_2, raw_hazard_pre_mul_raw_haz_2)
node _raw_hazard_pre_T_12 = and(_raw_hazard_pre_T_10, _raw_hazard_pre_T_11)
node _raw_hazard_pre_T_13 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_pre_T_14 = and(_raw_hazard_pre_T_12, _raw_hazard_pre_T_13)
node _raw_hazard_pre_is_garbage_T_15 = and(mesh.io.tags_in_progress[3].addr.is_acc_addr, mesh.io.tags_in_progress[3].addr.accumulate)
node _raw_hazard_pre_is_garbage_T_16 = and(_raw_hazard_pre_is_garbage_T_15, mesh.io.tags_in_progress[3].addr.read_full_acc_row)
node _raw_hazard_pre_is_garbage_T_17 = andr(mesh.io.tags_in_progress[3].addr.data)
node _raw_hazard_pre_is_garbage_T_18 = and(_raw_hazard_pre_is_garbage_T_16, _raw_hazard_pre_is_garbage_T_17)
node _raw_hazard_pre_is_garbage_T_19 = bits(mesh.io.tags_in_progress[3].addr.garbage_bit, 0, 0)
node raw_hazard_pre_is_garbage_3 = and(_raw_hazard_pre_is_garbage_T_18, _raw_hazard_pre_is_garbage_T_19)
wire _raw_hazard_pre_pre_raw_haz_WIRE_12 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_pre_raw_haz_WIRE_13 : UInt<32>
connect _raw_hazard_pre_pre_raw_haz_WIRE_13, rs1s[0]
node _raw_hazard_pre_pre_raw_haz_T_27 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_13, 13, 0)
connect _raw_hazard_pre_pre_raw_haz_WIRE_12.data, _raw_hazard_pre_pre_raw_haz_T_27
node _raw_hazard_pre_pre_raw_haz_T_28 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_13, 14, 14)
connect _raw_hazard_pre_pre_raw_haz_WIRE_12.garbage_bit, _raw_hazard_pre_pre_raw_haz_T_28
node _raw_hazard_pre_pre_raw_haz_T_29 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_13, 25, 15)
connect _raw_hazard_pre_pre_raw_haz_WIRE_12.garbage, _raw_hazard_pre_pre_raw_haz_T_29
node _raw_hazard_pre_pre_raw_haz_T_30 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_13, 28, 26)
wire _raw_hazard_pre_pre_raw_haz_WIRE_14 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_14, _raw_hazard_pre_pre_raw_haz_T_30
wire _raw_hazard_pre_pre_raw_haz_WIRE_15 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_15, _raw_hazard_pre_pre_raw_haz_WIRE_14
connect _raw_hazard_pre_pre_raw_haz_WIRE_12.norm_cmd, _raw_hazard_pre_pre_raw_haz_WIRE_15
node _raw_hazard_pre_pre_raw_haz_T_31 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_13, 29, 29)
connect _raw_hazard_pre_pre_raw_haz_WIRE_12.read_full_acc_row, _raw_hazard_pre_pre_raw_haz_T_31
node _raw_hazard_pre_pre_raw_haz_T_32 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_13, 30, 30)
connect _raw_hazard_pre_pre_raw_haz_WIRE_12.accumulate, _raw_hazard_pre_pre_raw_haz_T_32
node _raw_hazard_pre_pre_raw_haz_T_33 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_13, 31, 31)
connect _raw_hazard_pre_pre_raw_haz_WIRE_12.is_acc_addr, _raw_hazard_pre_pre_raw_haz_T_33
node _raw_hazard_pre_pre_raw_haz_T_34 = eq(mesh.io.tags_in_progress[3].addr.is_acc_addr, _raw_hazard_pre_pre_raw_haz_WIRE_12.is_acc_addr)
node _raw_hazard_pre_pre_raw_haz_T_35 = eq(mesh.io.tags_in_progress[3].addr.data, _raw_hazard_pre_pre_raw_haz_WIRE_12.data)
node raw_hazard_pre_pre_raw_haz_3 = and(_raw_hazard_pre_pre_raw_haz_T_34, _raw_hazard_pre_pre_raw_haz_T_35)
wire _raw_hazard_pre_mul_raw_haz_WIRE_24 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_25 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_25, rs1s[1]
node _raw_hazard_pre_mul_raw_haz_T_60 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_25, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_24.data, _raw_hazard_pre_mul_raw_haz_T_60
node _raw_hazard_pre_mul_raw_haz_T_61 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_25, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_24.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_61
node _raw_hazard_pre_mul_raw_haz_T_62 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_25, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_24.garbage, _raw_hazard_pre_mul_raw_haz_T_62
node _raw_hazard_pre_mul_raw_haz_T_63 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_25, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_26 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_26, _raw_hazard_pre_mul_raw_haz_T_63
wire _raw_hazard_pre_mul_raw_haz_WIRE_27 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_27, _raw_hazard_pre_mul_raw_haz_WIRE_26
connect _raw_hazard_pre_mul_raw_haz_WIRE_24.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_27
node _raw_hazard_pre_mul_raw_haz_T_64 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_25, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_24.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_64
node _raw_hazard_pre_mul_raw_haz_T_65 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_25, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_24.accumulate, _raw_hazard_pre_mul_raw_haz_T_65
node _raw_hazard_pre_mul_raw_haz_T_66 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_25, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_24.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_66
node _raw_hazard_pre_mul_raw_haz_T_67 = eq(mesh.io.tags_in_progress[3].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_24.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_68 = eq(mesh.io.tags_in_progress[3].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_24.data)
node _raw_hazard_pre_mul_raw_haz_T_69 = and(_raw_hazard_pre_mul_raw_haz_T_67, _raw_hazard_pre_mul_raw_haz_T_68)
wire _raw_hazard_pre_mul_raw_haz_WIRE_28 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_29 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_29, rs2s[1]
node _raw_hazard_pre_mul_raw_haz_T_70 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_29, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_28.data, _raw_hazard_pre_mul_raw_haz_T_70
node _raw_hazard_pre_mul_raw_haz_T_71 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_29, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_28.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_71
node _raw_hazard_pre_mul_raw_haz_T_72 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_29, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_28.garbage, _raw_hazard_pre_mul_raw_haz_T_72
node _raw_hazard_pre_mul_raw_haz_T_73 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_29, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_30 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_30, _raw_hazard_pre_mul_raw_haz_T_73
wire _raw_hazard_pre_mul_raw_haz_WIRE_31 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_31, _raw_hazard_pre_mul_raw_haz_WIRE_30
connect _raw_hazard_pre_mul_raw_haz_WIRE_28.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_31
node _raw_hazard_pre_mul_raw_haz_T_74 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_29, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_28.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_74
node _raw_hazard_pre_mul_raw_haz_T_75 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_29, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_28.accumulate, _raw_hazard_pre_mul_raw_haz_T_75
node _raw_hazard_pre_mul_raw_haz_T_76 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_29, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_28.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_76
node _raw_hazard_pre_mul_raw_haz_T_77 = eq(mesh.io.tags_in_progress[3].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_28.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_78 = eq(mesh.io.tags_in_progress[3].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_28.data)
node _raw_hazard_pre_mul_raw_haz_T_79 = and(_raw_hazard_pre_mul_raw_haz_T_77, _raw_hazard_pre_mul_raw_haz_T_78)
node raw_hazard_pre_mul_raw_haz_3 = or(_raw_hazard_pre_mul_raw_haz_T_69, _raw_hazard_pre_mul_raw_haz_T_79)
node _raw_hazard_pre_T_15 = eq(raw_hazard_pre_is_garbage_3, UInt<1>(0h0))
node _raw_hazard_pre_T_16 = or(raw_hazard_pre_pre_raw_haz_3, raw_hazard_pre_mul_raw_haz_3)
node _raw_hazard_pre_T_17 = and(_raw_hazard_pre_T_15, _raw_hazard_pre_T_16)
node _raw_hazard_pre_T_18 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_pre_T_19 = and(_raw_hazard_pre_T_17, _raw_hazard_pre_T_18)
node _raw_hazard_pre_is_garbage_T_20 = and(mesh.io.tags_in_progress[4].addr.is_acc_addr, mesh.io.tags_in_progress[4].addr.accumulate)
node _raw_hazard_pre_is_garbage_T_21 = and(_raw_hazard_pre_is_garbage_T_20, mesh.io.tags_in_progress[4].addr.read_full_acc_row)
node _raw_hazard_pre_is_garbage_T_22 = andr(mesh.io.tags_in_progress[4].addr.data)
node _raw_hazard_pre_is_garbage_T_23 = and(_raw_hazard_pre_is_garbage_T_21, _raw_hazard_pre_is_garbage_T_22)
node _raw_hazard_pre_is_garbage_T_24 = bits(mesh.io.tags_in_progress[4].addr.garbage_bit, 0, 0)
node raw_hazard_pre_is_garbage_4 = and(_raw_hazard_pre_is_garbage_T_23, _raw_hazard_pre_is_garbage_T_24)
wire _raw_hazard_pre_pre_raw_haz_WIRE_16 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_pre_raw_haz_WIRE_17 : UInt<32>
connect _raw_hazard_pre_pre_raw_haz_WIRE_17, rs1s[0]
node _raw_hazard_pre_pre_raw_haz_T_36 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_17, 13, 0)
connect _raw_hazard_pre_pre_raw_haz_WIRE_16.data, _raw_hazard_pre_pre_raw_haz_T_36
node _raw_hazard_pre_pre_raw_haz_T_37 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_17, 14, 14)
connect _raw_hazard_pre_pre_raw_haz_WIRE_16.garbage_bit, _raw_hazard_pre_pre_raw_haz_T_37
node _raw_hazard_pre_pre_raw_haz_T_38 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_17, 25, 15)
connect _raw_hazard_pre_pre_raw_haz_WIRE_16.garbage, _raw_hazard_pre_pre_raw_haz_T_38
node _raw_hazard_pre_pre_raw_haz_T_39 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_17, 28, 26)
wire _raw_hazard_pre_pre_raw_haz_WIRE_18 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_18, _raw_hazard_pre_pre_raw_haz_T_39
wire _raw_hazard_pre_pre_raw_haz_WIRE_19 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_19, _raw_hazard_pre_pre_raw_haz_WIRE_18
connect _raw_hazard_pre_pre_raw_haz_WIRE_16.norm_cmd, _raw_hazard_pre_pre_raw_haz_WIRE_19
node _raw_hazard_pre_pre_raw_haz_T_40 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_17, 29, 29)
connect _raw_hazard_pre_pre_raw_haz_WIRE_16.read_full_acc_row, _raw_hazard_pre_pre_raw_haz_T_40
node _raw_hazard_pre_pre_raw_haz_T_41 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_17, 30, 30)
connect _raw_hazard_pre_pre_raw_haz_WIRE_16.accumulate, _raw_hazard_pre_pre_raw_haz_T_41
node _raw_hazard_pre_pre_raw_haz_T_42 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_17, 31, 31)
connect _raw_hazard_pre_pre_raw_haz_WIRE_16.is_acc_addr, _raw_hazard_pre_pre_raw_haz_T_42
node _raw_hazard_pre_pre_raw_haz_T_43 = eq(mesh.io.tags_in_progress[4].addr.is_acc_addr, _raw_hazard_pre_pre_raw_haz_WIRE_16.is_acc_addr)
node _raw_hazard_pre_pre_raw_haz_T_44 = eq(mesh.io.tags_in_progress[4].addr.data, _raw_hazard_pre_pre_raw_haz_WIRE_16.data)
node raw_hazard_pre_pre_raw_haz_4 = and(_raw_hazard_pre_pre_raw_haz_T_43, _raw_hazard_pre_pre_raw_haz_T_44)
wire _raw_hazard_pre_mul_raw_haz_WIRE_32 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_33 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_33, rs1s[1]
node _raw_hazard_pre_mul_raw_haz_T_80 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_33, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_32.data, _raw_hazard_pre_mul_raw_haz_T_80
node _raw_hazard_pre_mul_raw_haz_T_81 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_33, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_32.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_81
node _raw_hazard_pre_mul_raw_haz_T_82 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_33, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_32.garbage, _raw_hazard_pre_mul_raw_haz_T_82
node _raw_hazard_pre_mul_raw_haz_T_83 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_33, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_34 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_34, _raw_hazard_pre_mul_raw_haz_T_83
wire _raw_hazard_pre_mul_raw_haz_WIRE_35 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_35, _raw_hazard_pre_mul_raw_haz_WIRE_34
connect _raw_hazard_pre_mul_raw_haz_WIRE_32.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_35
node _raw_hazard_pre_mul_raw_haz_T_84 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_33, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_32.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_84
node _raw_hazard_pre_mul_raw_haz_T_85 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_33, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_32.accumulate, _raw_hazard_pre_mul_raw_haz_T_85
node _raw_hazard_pre_mul_raw_haz_T_86 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_33, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_32.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_86
node _raw_hazard_pre_mul_raw_haz_T_87 = eq(mesh.io.tags_in_progress[4].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_32.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_88 = eq(mesh.io.tags_in_progress[4].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_32.data)
node _raw_hazard_pre_mul_raw_haz_T_89 = and(_raw_hazard_pre_mul_raw_haz_T_87, _raw_hazard_pre_mul_raw_haz_T_88)
wire _raw_hazard_pre_mul_raw_haz_WIRE_36 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_37 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_37, rs2s[1]
node _raw_hazard_pre_mul_raw_haz_T_90 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_37, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_36.data, _raw_hazard_pre_mul_raw_haz_T_90
node _raw_hazard_pre_mul_raw_haz_T_91 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_37, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_36.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_91
node _raw_hazard_pre_mul_raw_haz_T_92 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_37, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_36.garbage, _raw_hazard_pre_mul_raw_haz_T_92
node _raw_hazard_pre_mul_raw_haz_T_93 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_37, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_38 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_38, _raw_hazard_pre_mul_raw_haz_T_93
wire _raw_hazard_pre_mul_raw_haz_WIRE_39 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_39, _raw_hazard_pre_mul_raw_haz_WIRE_38
connect _raw_hazard_pre_mul_raw_haz_WIRE_36.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_39
node _raw_hazard_pre_mul_raw_haz_T_94 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_37, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_36.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_94
node _raw_hazard_pre_mul_raw_haz_T_95 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_37, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_36.accumulate, _raw_hazard_pre_mul_raw_haz_T_95
node _raw_hazard_pre_mul_raw_haz_T_96 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_37, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_36.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_96
node _raw_hazard_pre_mul_raw_haz_T_97 = eq(mesh.io.tags_in_progress[4].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_36.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_98 = eq(mesh.io.tags_in_progress[4].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_36.data)
node _raw_hazard_pre_mul_raw_haz_T_99 = and(_raw_hazard_pre_mul_raw_haz_T_97, _raw_hazard_pre_mul_raw_haz_T_98)
node raw_hazard_pre_mul_raw_haz_4 = or(_raw_hazard_pre_mul_raw_haz_T_89, _raw_hazard_pre_mul_raw_haz_T_99)
node _raw_hazard_pre_T_20 = eq(raw_hazard_pre_is_garbage_4, UInt<1>(0h0))
node _raw_hazard_pre_T_21 = or(raw_hazard_pre_pre_raw_haz_4, raw_hazard_pre_mul_raw_haz_4)
node _raw_hazard_pre_T_22 = and(_raw_hazard_pre_T_20, _raw_hazard_pre_T_21)
node _raw_hazard_pre_T_23 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_pre_T_24 = and(_raw_hazard_pre_T_22, _raw_hazard_pre_T_23)
node _raw_hazard_pre_is_garbage_T_25 = and(mesh.io.tags_in_progress[5].addr.is_acc_addr, mesh.io.tags_in_progress[5].addr.accumulate)
node _raw_hazard_pre_is_garbage_T_26 = and(_raw_hazard_pre_is_garbage_T_25, mesh.io.tags_in_progress[5].addr.read_full_acc_row)
node _raw_hazard_pre_is_garbage_T_27 = andr(mesh.io.tags_in_progress[5].addr.data)
node _raw_hazard_pre_is_garbage_T_28 = and(_raw_hazard_pre_is_garbage_T_26, _raw_hazard_pre_is_garbage_T_27)
node _raw_hazard_pre_is_garbage_T_29 = bits(mesh.io.tags_in_progress[5].addr.garbage_bit, 0, 0)
node raw_hazard_pre_is_garbage_5 = and(_raw_hazard_pre_is_garbage_T_28, _raw_hazard_pre_is_garbage_T_29)
wire _raw_hazard_pre_pre_raw_haz_WIRE_20 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_pre_raw_haz_WIRE_21 : UInt<32>
connect _raw_hazard_pre_pre_raw_haz_WIRE_21, rs1s[0]
node _raw_hazard_pre_pre_raw_haz_T_45 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_21, 13, 0)
connect _raw_hazard_pre_pre_raw_haz_WIRE_20.data, _raw_hazard_pre_pre_raw_haz_T_45
node _raw_hazard_pre_pre_raw_haz_T_46 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_21, 14, 14)
connect _raw_hazard_pre_pre_raw_haz_WIRE_20.garbage_bit, _raw_hazard_pre_pre_raw_haz_T_46
node _raw_hazard_pre_pre_raw_haz_T_47 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_21, 25, 15)
connect _raw_hazard_pre_pre_raw_haz_WIRE_20.garbage, _raw_hazard_pre_pre_raw_haz_T_47
node _raw_hazard_pre_pre_raw_haz_T_48 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_21, 28, 26)
wire _raw_hazard_pre_pre_raw_haz_WIRE_22 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_22, _raw_hazard_pre_pre_raw_haz_T_48
wire _raw_hazard_pre_pre_raw_haz_WIRE_23 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_23, _raw_hazard_pre_pre_raw_haz_WIRE_22
connect _raw_hazard_pre_pre_raw_haz_WIRE_20.norm_cmd, _raw_hazard_pre_pre_raw_haz_WIRE_23
node _raw_hazard_pre_pre_raw_haz_T_49 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_21, 29, 29)
connect _raw_hazard_pre_pre_raw_haz_WIRE_20.read_full_acc_row, _raw_hazard_pre_pre_raw_haz_T_49
node _raw_hazard_pre_pre_raw_haz_T_50 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_21, 30, 30)
connect _raw_hazard_pre_pre_raw_haz_WIRE_20.accumulate, _raw_hazard_pre_pre_raw_haz_T_50
node _raw_hazard_pre_pre_raw_haz_T_51 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_21, 31, 31)
connect _raw_hazard_pre_pre_raw_haz_WIRE_20.is_acc_addr, _raw_hazard_pre_pre_raw_haz_T_51
node _raw_hazard_pre_pre_raw_haz_T_52 = eq(mesh.io.tags_in_progress[5].addr.is_acc_addr, _raw_hazard_pre_pre_raw_haz_WIRE_20.is_acc_addr)
node _raw_hazard_pre_pre_raw_haz_T_53 = eq(mesh.io.tags_in_progress[5].addr.data, _raw_hazard_pre_pre_raw_haz_WIRE_20.data)
node raw_hazard_pre_pre_raw_haz_5 = and(_raw_hazard_pre_pre_raw_haz_T_52, _raw_hazard_pre_pre_raw_haz_T_53)
wire _raw_hazard_pre_mul_raw_haz_WIRE_40 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_41 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_41, rs1s[1]
node _raw_hazard_pre_mul_raw_haz_T_100 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_41, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_40.data, _raw_hazard_pre_mul_raw_haz_T_100
node _raw_hazard_pre_mul_raw_haz_T_101 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_41, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_40.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_101
node _raw_hazard_pre_mul_raw_haz_T_102 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_41, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_40.garbage, _raw_hazard_pre_mul_raw_haz_T_102
node _raw_hazard_pre_mul_raw_haz_T_103 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_41, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_42 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_42, _raw_hazard_pre_mul_raw_haz_T_103
wire _raw_hazard_pre_mul_raw_haz_WIRE_43 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_43, _raw_hazard_pre_mul_raw_haz_WIRE_42
connect _raw_hazard_pre_mul_raw_haz_WIRE_40.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_43
node _raw_hazard_pre_mul_raw_haz_T_104 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_41, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_40.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_104
node _raw_hazard_pre_mul_raw_haz_T_105 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_41, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_40.accumulate, _raw_hazard_pre_mul_raw_haz_T_105
node _raw_hazard_pre_mul_raw_haz_T_106 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_41, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_40.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_106
node _raw_hazard_pre_mul_raw_haz_T_107 = eq(mesh.io.tags_in_progress[5].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_40.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_108 = eq(mesh.io.tags_in_progress[5].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_40.data)
node _raw_hazard_pre_mul_raw_haz_T_109 = and(_raw_hazard_pre_mul_raw_haz_T_107, _raw_hazard_pre_mul_raw_haz_T_108)
wire _raw_hazard_pre_mul_raw_haz_WIRE_44 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_45 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_45, rs2s[1]
node _raw_hazard_pre_mul_raw_haz_T_110 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_45, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_44.data, _raw_hazard_pre_mul_raw_haz_T_110
node _raw_hazard_pre_mul_raw_haz_T_111 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_45, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_44.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_111
node _raw_hazard_pre_mul_raw_haz_T_112 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_45, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_44.garbage, _raw_hazard_pre_mul_raw_haz_T_112
node _raw_hazard_pre_mul_raw_haz_T_113 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_45, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_46 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_46, _raw_hazard_pre_mul_raw_haz_T_113
wire _raw_hazard_pre_mul_raw_haz_WIRE_47 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_47, _raw_hazard_pre_mul_raw_haz_WIRE_46
connect _raw_hazard_pre_mul_raw_haz_WIRE_44.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_47
node _raw_hazard_pre_mul_raw_haz_T_114 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_45, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_44.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_114
node _raw_hazard_pre_mul_raw_haz_T_115 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_45, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_44.accumulate, _raw_hazard_pre_mul_raw_haz_T_115
node _raw_hazard_pre_mul_raw_haz_T_116 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_45, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_44.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_116
node _raw_hazard_pre_mul_raw_haz_T_117 = eq(mesh.io.tags_in_progress[5].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_44.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_118 = eq(mesh.io.tags_in_progress[5].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_44.data)
node _raw_hazard_pre_mul_raw_haz_T_119 = and(_raw_hazard_pre_mul_raw_haz_T_117, _raw_hazard_pre_mul_raw_haz_T_118)
node raw_hazard_pre_mul_raw_haz_5 = or(_raw_hazard_pre_mul_raw_haz_T_109, _raw_hazard_pre_mul_raw_haz_T_119)
node _raw_hazard_pre_T_25 = eq(raw_hazard_pre_is_garbage_5, UInt<1>(0h0))
node _raw_hazard_pre_T_26 = or(raw_hazard_pre_pre_raw_haz_5, raw_hazard_pre_mul_raw_haz_5)
node _raw_hazard_pre_T_27 = and(_raw_hazard_pre_T_25, _raw_hazard_pre_T_26)
node _raw_hazard_pre_T_28 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_pre_T_29 = and(_raw_hazard_pre_T_27, _raw_hazard_pre_T_28)
node _raw_hazard_pre_is_garbage_T_30 = and(mesh.io.tags_in_progress[6].addr.is_acc_addr, mesh.io.tags_in_progress[6].addr.accumulate)
node _raw_hazard_pre_is_garbage_T_31 = and(_raw_hazard_pre_is_garbage_T_30, mesh.io.tags_in_progress[6].addr.read_full_acc_row)
node _raw_hazard_pre_is_garbage_T_32 = andr(mesh.io.tags_in_progress[6].addr.data)
node _raw_hazard_pre_is_garbage_T_33 = and(_raw_hazard_pre_is_garbage_T_31, _raw_hazard_pre_is_garbage_T_32)
node _raw_hazard_pre_is_garbage_T_34 = bits(mesh.io.tags_in_progress[6].addr.garbage_bit, 0, 0)
node raw_hazard_pre_is_garbage_6 = and(_raw_hazard_pre_is_garbage_T_33, _raw_hazard_pre_is_garbage_T_34)
wire _raw_hazard_pre_pre_raw_haz_WIRE_24 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_pre_raw_haz_WIRE_25 : UInt<32>
connect _raw_hazard_pre_pre_raw_haz_WIRE_25, rs1s[0]
node _raw_hazard_pre_pre_raw_haz_T_54 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_25, 13, 0)
connect _raw_hazard_pre_pre_raw_haz_WIRE_24.data, _raw_hazard_pre_pre_raw_haz_T_54
node _raw_hazard_pre_pre_raw_haz_T_55 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_25, 14, 14)
connect _raw_hazard_pre_pre_raw_haz_WIRE_24.garbage_bit, _raw_hazard_pre_pre_raw_haz_T_55
node _raw_hazard_pre_pre_raw_haz_T_56 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_25, 25, 15)
connect _raw_hazard_pre_pre_raw_haz_WIRE_24.garbage, _raw_hazard_pre_pre_raw_haz_T_56
node _raw_hazard_pre_pre_raw_haz_T_57 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_25, 28, 26)
wire _raw_hazard_pre_pre_raw_haz_WIRE_26 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_26, _raw_hazard_pre_pre_raw_haz_T_57
wire _raw_hazard_pre_pre_raw_haz_WIRE_27 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_27, _raw_hazard_pre_pre_raw_haz_WIRE_26
connect _raw_hazard_pre_pre_raw_haz_WIRE_24.norm_cmd, _raw_hazard_pre_pre_raw_haz_WIRE_27
node _raw_hazard_pre_pre_raw_haz_T_58 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_25, 29, 29)
connect _raw_hazard_pre_pre_raw_haz_WIRE_24.read_full_acc_row, _raw_hazard_pre_pre_raw_haz_T_58
node _raw_hazard_pre_pre_raw_haz_T_59 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_25, 30, 30)
connect _raw_hazard_pre_pre_raw_haz_WIRE_24.accumulate, _raw_hazard_pre_pre_raw_haz_T_59
node _raw_hazard_pre_pre_raw_haz_T_60 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_25, 31, 31)
connect _raw_hazard_pre_pre_raw_haz_WIRE_24.is_acc_addr, _raw_hazard_pre_pre_raw_haz_T_60
node _raw_hazard_pre_pre_raw_haz_T_61 = eq(mesh.io.tags_in_progress[6].addr.is_acc_addr, _raw_hazard_pre_pre_raw_haz_WIRE_24.is_acc_addr)
node _raw_hazard_pre_pre_raw_haz_T_62 = eq(mesh.io.tags_in_progress[6].addr.data, _raw_hazard_pre_pre_raw_haz_WIRE_24.data)
node raw_hazard_pre_pre_raw_haz_6 = and(_raw_hazard_pre_pre_raw_haz_T_61, _raw_hazard_pre_pre_raw_haz_T_62)
wire _raw_hazard_pre_mul_raw_haz_WIRE_48 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_49 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_49, rs1s[1]
node _raw_hazard_pre_mul_raw_haz_T_120 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_49, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_48.data, _raw_hazard_pre_mul_raw_haz_T_120
node _raw_hazard_pre_mul_raw_haz_T_121 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_49, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_48.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_121
node _raw_hazard_pre_mul_raw_haz_T_122 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_49, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_48.garbage, _raw_hazard_pre_mul_raw_haz_T_122
node _raw_hazard_pre_mul_raw_haz_T_123 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_49, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_50 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_50, _raw_hazard_pre_mul_raw_haz_T_123
wire _raw_hazard_pre_mul_raw_haz_WIRE_51 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_51, _raw_hazard_pre_mul_raw_haz_WIRE_50
connect _raw_hazard_pre_mul_raw_haz_WIRE_48.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_51
node _raw_hazard_pre_mul_raw_haz_T_124 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_49, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_48.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_124
node _raw_hazard_pre_mul_raw_haz_T_125 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_49, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_48.accumulate, _raw_hazard_pre_mul_raw_haz_T_125
node _raw_hazard_pre_mul_raw_haz_T_126 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_49, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_48.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_126
node _raw_hazard_pre_mul_raw_haz_T_127 = eq(mesh.io.tags_in_progress[6].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_48.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_128 = eq(mesh.io.tags_in_progress[6].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_48.data)
node _raw_hazard_pre_mul_raw_haz_T_129 = and(_raw_hazard_pre_mul_raw_haz_T_127, _raw_hazard_pre_mul_raw_haz_T_128)
wire _raw_hazard_pre_mul_raw_haz_WIRE_52 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_53 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_53, rs2s[1]
node _raw_hazard_pre_mul_raw_haz_T_130 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_53, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_52.data, _raw_hazard_pre_mul_raw_haz_T_130
node _raw_hazard_pre_mul_raw_haz_T_131 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_53, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_52.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_131
node _raw_hazard_pre_mul_raw_haz_T_132 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_53, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_52.garbage, _raw_hazard_pre_mul_raw_haz_T_132
node _raw_hazard_pre_mul_raw_haz_T_133 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_53, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_54 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_54, _raw_hazard_pre_mul_raw_haz_T_133
wire _raw_hazard_pre_mul_raw_haz_WIRE_55 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_55, _raw_hazard_pre_mul_raw_haz_WIRE_54
connect _raw_hazard_pre_mul_raw_haz_WIRE_52.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_55
node _raw_hazard_pre_mul_raw_haz_T_134 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_53, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_52.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_134
node _raw_hazard_pre_mul_raw_haz_T_135 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_53, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_52.accumulate, _raw_hazard_pre_mul_raw_haz_T_135
node _raw_hazard_pre_mul_raw_haz_T_136 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_53, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_52.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_136
node _raw_hazard_pre_mul_raw_haz_T_137 = eq(mesh.io.tags_in_progress[6].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_52.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_138 = eq(mesh.io.tags_in_progress[6].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_52.data)
node _raw_hazard_pre_mul_raw_haz_T_139 = and(_raw_hazard_pre_mul_raw_haz_T_137, _raw_hazard_pre_mul_raw_haz_T_138)
node raw_hazard_pre_mul_raw_haz_6 = or(_raw_hazard_pre_mul_raw_haz_T_129, _raw_hazard_pre_mul_raw_haz_T_139)
node _raw_hazard_pre_T_30 = eq(raw_hazard_pre_is_garbage_6, UInt<1>(0h0))
node _raw_hazard_pre_T_31 = or(raw_hazard_pre_pre_raw_haz_6, raw_hazard_pre_mul_raw_haz_6)
node _raw_hazard_pre_T_32 = and(_raw_hazard_pre_T_30, _raw_hazard_pre_T_31)
node _raw_hazard_pre_T_33 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_pre_T_34 = and(_raw_hazard_pre_T_32, _raw_hazard_pre_T_33)
node _raw_hazard_pre_is_garbage_T_35 = and(mesh.io.tags_in_progress[7].addr.is_acc_addr, mesh.io.tags_in_progress[7].addr.accumulate)
node _raw_hazard_pre_is_garbage_T_36 = and(_raw_hazard_pre_is_garbage_T_35, mesh.io.tags_in_progress[7].addr.read_full_acc_row)
node _raw_hazard_pre_is_garbage_T_37 = andr(mesh.io.tags_in_progress[7].addr.data)
node _raw_hazard_pre_is_garbage_T_38 = and(_raw_hazard_pre_is_garbage_T_36, _raw_hazard_pre_is_garbage_T_37)
node _raw_hazard_pre_is_garbage_T_39 = bits(mesh.io.tags_in_progress[7].addr.garbage_bit, 0, 0)
node raw_hazard_pre_is_garbage_7 = and(_raw_hazard_pre_is_garbage_T_38, _raw_hazard_pre_is_garbage_T_39)
wire _raw_hazard_pre_pre_raw_haz_WIRE_28 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_pre_raw_haz_WIRE_29 : UInt<32>
connect _raw_hazard_pre_pre_raw_haz_WIRE_29, rs1s[0]
node _raw_hazard_pre_pre_raw_haz_T_63 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_29, 13, 0)
connect _raw_hazard_pre_pre_raw_haz_WIRE_28.data, _raw_hazard_pre_pre_raw_haz_T_63
node _raw_hazard_pre_pre_raw_haz_T_64 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_29, 14, 14)
connect _raw_hazard_pre_pre_raw_haz_WIRE_28.garbage_bit, _raw_hazard_pre_pre_raw_haz_T_64
node _raw_hazard_pre_pre_raw_haz_T_65 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_29, 25, 15)
connect _raw_hazard_pre_pre_raw_haz_WIRE_28.garbage, _raw_hazard_pre_pre_raw_haz_T_65
node _raw_hazard_pre_pre_raw_haz_T_66 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_29, 28, 26)
wire _raw_hazard_pre_pre_raw_haz_WIRE_30 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_30, _raw_hazard_pre_pre_raw_haz_T_66
wire _raw_hazard_pre_pre_raw_haz_WIRE_31 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_31, _raw_hazard_pre_pre_raw_haz_WIRE_30
connect _raw_hazard_pre_pre_raw_haz_WIRE_28.norm_cmd, _raw_hazard_pre_pre_raw_haz_WIRE_31
node _raw_hazard_pre_pre_raw_haz_T_67 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_29, 29, 29)
connect _raw_hazard_pre_pre_raw_haz_WIRE_28.read_full_acc_row, _raw_hazard_pre_pre_raw_haz_T_67
node _raw_hazard_pre_pre_raw_haz_T_68 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_29, 30, 30)
connect _raw_hazard_pre_pre_raw_haz_WIRE_28.accumulate, _raw_hazard_pre_pre_raw_haz_T_68
node _raw_hazard_pre_pre_raw_haz_T_69 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_29, 31, 31)
connect _raw_hazard_pre_pre_raw_haz_WIRE_28.is_acc_addr, _raw_hazard_pre_pre_raw_haz_T_69
node _raw_hazard_pre_pre_raw_haz_T_70 = eq(mesh.io.tags_in_progress[7].addr.is_acc_addr, _raw_hazard_pre_pre_raw_haz_WIRE_28.is_acc_addr)
node _raw_hazard_pre_pre_raw_haz_T_71 = eq(mesh.io.tags_in_progress[7].addr.data, _raw_hazard_pre_pre_raw_haz_WIRE_28.data)
node raw_hazard_pre_pre_raw_haz_7 = and(_raw_hazard_pre_pre_raw_haz_T_70, _raw_hazard_pre_pre_raw_haz_T_71)
wire _raw_hazard_pre_mul_raw_haz_WIRE_56 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_57 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_57, rs1s[1]
node _raw_hazard_pre_mul_raw_haz_T_140 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_57, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_56.data, _raw_hazard_pre_mul_raw_haz_T_140
node _raw_hazard_pre_mul_raw_haz_T_141 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_57, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_56.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_141
node _raw_hazard_pre_mul_raw_haz_T_142 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_57, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_56.garbage, _raw_hazard_pre_mul_raw_haz_T_142
node _raw_hazard_pre_mul_raw_haz_T_143 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_57, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_58 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_58, _raw_hazard_pre_mul_raw_haz_T_143
wire _raw_hazard_pre_mul_raw_haz_WIRE_59 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_59, _raw_hazard_pre_mul_raw_haz_WIRE_58
connect _raw_hazard_pre_mul_raw_haz_WIRE_56.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_59
node _raw_hazard_pre_mul_raw_haz_T_144 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_57, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_56.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_144
node _raw_hazard_pre_mul_raw_haz_T_145 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_57, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_56.accumulate, _raw_hazard_pre_mul_raw_haz_T_145
node _raw_hazard_pre_mul_raw_haz_T_146 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_57, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_56.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_146
node _raw_hazard_pre_mul_raw_haz_T_147 = eq(mesh.io.tags_in_progress[7].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_56.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_148 = eq(mesh.io.tags_in_progress[7].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_56.data)
node _raw_hazard_pre_mul_raw_haz_T_149 = and(_raw_hazard_pre_mul_raw_haz_T_147, _raw_hazard_pre_mul_raw_haz_T_148)
wire _raw_hazard_pre_mul_raw_haz_WIRE_60 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_61 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_61, rs2s[1]
node _raw_hazard_pre_mul_raw_haz_T_150 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_61, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_60.data, _raw_hazard_pre_mul_raw_haz_T_150
node _raw_hazard_pre_mul_raw_haz_T_151 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_61, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_60.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_151
node _raw_hazard_pre_mul_raw_haz_T_152 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_61, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_60.garbage, _raw_hazard_pre_mul_raw_haz_T_152
node _raw_hazard_pre_mul_raw_haz_T_153 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_61, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_62 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_62, _raw_hazard_pre_mul_raw_haz_T_153
wire _raw_hazard_pre_mul_raw_haz_WIRE_63 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_63, _raw_hazard_pre_mul_raw_haz_WIRE_62
connect _raw_hazard_pre_mul_raw_haz_WIRE_60.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_63
node _raw_hazard_pre_mul_raw_haz_T_154 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_61, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_60.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_154
node _raw_hazard_pre_mul_raw_haz_T_155 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_61, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_60.accumulate, _raw_hazard_pre_mul_raw_haz_T_155
node _raw_hazard_pre_mul_raw_haz_T_156 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_61, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_60.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_156
node _raw_hazard_pre_mul_raw_haz_T_157 = eq(mesh.io.tags_in_progress[7].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_60.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_158 = eq(mesh.io.tags_in_progress[7].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_60.data)
node _raw_hazard_pre_mul_raw_haz_T_159 = and(_raw_hazard_pre_mul_raw_haz_T_157, _raw_hazard_pre_mul_raw_haz_T_158)
node raw_hazard_pre_mul_raw_haz_7 = or(_raw_hazard_pre_mul_raw_haz_T_149, _raw_hazard_pre_mul_raw_haz_T_159)
node _raw_hazard_pre_T_35 = eq(raw_hazard_pre_is_garbage_7, UInt<1>(0h0))
node _raw_hazard_pre_T_36 = or(raw_hazard_pre_pre_raw_haz_7, raw_hazard_pre_mul_raw_haz_7)
node _raw_hazard_pre_T_37 = and(_raw_hazard_pre_T_35, _raw_hazard_pre_T_36)
node _raw_hazard_pre_T_38 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_pre_T_39 = and(_raw_hazard_pre_T_37, _raw_hazard_pre_T_38)
node _raw_hazard_pre_is_garbage_T_40 = and(mesh.io.tags_in_progress[8].addr.is_acc_addr, mesh.io.tags_in_progress[8].addr.accumulate)
node _raw_hazard_pre_is_garbage_T_41 = and(_raw_hazard_pre_is_garbage_T_40, mesh.io.tags_in_progress[8].addr.read_full_acc_row)
node _raw_hazard_pre_is_garbage_T_42 = andr(mesh.io.tags_in_progress[8].addr.data)
node _raw_hazard_pre_is_garbage_T_43 = and(_raw_hazard_pre_is_garbage_T_41, _raw_hazard_pre_is_garbage_T_42)
node _raw_hazard_pre_is_garbage_T_44 = bits(mesh.io.tags_in_progress[8].addr.garbage_bit, 0, 0)
node raw_hazard_pre_is_garbage_8 = and(_raw_hazard_pre_is_garbage_T_43, _raw_hazard_pre_is_garbage_T_44)
wire _raw_hazard_pre_pre_raw_haz_WIRE_32 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_pre_raw_haz_WIRE_33 : UInt<32>
connect _raw_hazard_pre_pre_raw_haz_WIRE_33, rs1s[0]
node _raw_hazard_pre_pre_raw_haz_T_72 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_33, 13, 0)
connect _raw_hazard_pre_pre_raw_haz_WIRE_32.data, _raw_hazard_pre_pre_raw_haz_T_72
node _raw_hazard_pre_pre_raw_haz_T_73 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_33, 14, 14)
connect _raw_hazard_pre_pre_raw_haz_WIRE_32.garbage_bit, _raw_hazard_pre_pre_raw_haz_T_73
node _raw_hazard_pre_pre_raw_haz_T_74 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_33, 25, 15)
connect _raw_hazard_pre_pre_raw_haz_WIRE_32.garbage, _raw_hazard_pre_pre_raw_haz_T_74
node _raw_hazard_pre_pre_raw_haz_T_75 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_33, 28, 26)
wire _raw_hazard_pre_pre_raw_haz_WIRE_34 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_34, _raw_hazard_pre_pre_raw_haz_T_75
wire _raw_hazard_pre_pre_raw_haz_WIRE_35 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_35, _raw_hazard_pre_pre_raw_haz_WIRE_34
connect _raw_hazard_pre_pre_raw_haz_WIRE_32.norm_cmd, _raw_hazard_pre_pre_raw_haz_WIRE_35
node _raw_hazard_pre_pre_raw_haz_T_76 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_33, 29, 29)
connect _raw_hazard_pre_pre_raw_haz_WIRE_32.read_full_acc_row, _raw_hazard_pre_pre_raw_haz_T_76
node _raw_hazard_pre_pre_raw_haz_T_77 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_33, 30, 30)
connect _raw_hazard_pre_pre_raw_haz_WIRE_32.accumulate, _raw_hazard_pre_pre_raw_haz_T_77
node _raw_hazard_pre_pre_raw_haz_T_78 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_33, 31, 31)
connect _raw_hazard_pre_pre_raw_haz_WIRE_32.is_acc_addr, _raw_hazard_pre_pre_raw_haz_T_78
node _raw_hazard_pre_pre_raw_haz_T_79 = eq(mesh.io.tags_in_progress[8].addr.is_acc_addr, _raw_hazard_pre_pre_raw_haz_WIRE_32.is_acc_addr)
node _raw_hazard_pre_pre_raw_haz_T_80 = eq(mesh.io.tags_in_progress[8].addr.data, _raw_hazard_pre_pre_raw_haz_WIRE_32.data)
node raw_hazard_pre_pre_raw_haz_8 = and(_raw_hazard_pre_pre_raw_haz_T_79, _raw_hazard_pre_pre_raw_haz_T_80)
wire _raw_hazard_pre_mul_raw_haz_WIRE_64 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_65 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_65, rs1s[1]
node _raw_hazard_pre_mul_raw_haz_T_160 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_65, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_64.data, _raw_hazard_pre_mul_raw_haz_T_160
node _raw_hazard_pre_mul_raw_haz_T_161 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_65, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_64.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_161
node _raw_hazard_pre_mul_raw_haz_T_162 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_65, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_64.garbage, _raw_hazard_pre_mul_raw_haz_T_162
node _raw_hazard_pre_mul_raw_haz_T_163 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_65, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_66 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_66, _raw_hazard_pre_mul_raw_haz_T_163
wire _raw_hazard_pre_mul_raw_haz_WIRE_67 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_67, _raw_hazard_pre_mul_raw_haz_WIRE_66
connect _raw_hazard_pre_mul_raw_haz_WIRE_64.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_67
node _raw_hazard_pre_mul_raw_haz_T_164 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_65, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_64.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_164
node _raw_hazard_pre_mul_raw_haz_T_165 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_65, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_64.accumulate, _raw_hazard_pre_mul_raw_haz_T_165
node _raw_hazard_pre_mul_raw_haz_T_166 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_65, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_64.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_166
node _raw_hazard_pre_mul_raw_haz_T_167 = eq(mesh.io.tags_in_progress[8].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_64.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_168 = eq(mesh.io.tags_in_progress[8].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_64.data)
node _raw_hazard_pre_mul_raw_haz_T_169 = and(_raw_hazard_pre_mul_raw_haz_T_167, _raw_hazard_pre_mul_raw_haz_T_168)
wire _raw_hazard_pre_mul_raw_haz_WIRE_68 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_69 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_69, rs2s[1]
node _raw_hazard_pre_mul_raw_haz_T_170 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_69, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_68.data, _raw_hazard_pre_mul_raw_haz_T_170
node _raw_hazard_pre_mul_raw_haz_T_171 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_69, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_68.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_171
node _raw_hazard_pre_mul_raw_haz_T_172 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_69, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_68.garbage, _raw_hazard_pre_mul_raw_haz_T_172
node _raw_hazard_pre_mul_raw_haz_T_173 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_69, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_70 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_70, _raw_hazard_pre_mul_raw_haz_T_173
wire _raw_hazard_pre_mul_raw_haz_WIRE_71 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_71, _raw_hazard_pre_mul_raw_haz_WIRE_70
connect _raw_hazard_pre_mul_raw_haz_WIRE_68.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_71
node _raw_hazard_pre_mul_raw_haz_T_174 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_69, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_68.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_174
node _raw_hazard_pre_mul_raw_haz_T_175 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_69, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_68.accumulate, _raw_hazard_pre_mul_raw_haz_T_175
node _raw_hazard_pre_mul_raw_haz_T_176 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_69, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_68.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_176
node _raw_hazard_pre_mul_raw_haz_T_177 = eq(mesh.io.tags_in_progress[8].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_68.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_178 = eq(mesh.io.tags_in_progress[8].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_68.data)
node _raw_hazard_pre_mul_raw_haz_T_179 = and(_raw_hazard_pre_mul_raw_haz_T_177, _raw_hazard_pre_mul_raw_haz_T_178)
node raw_hazard_pre_mul_raw_haz_8 = or(_raw_hazard_pre_mul_raw_haz_T_169, _raw_hazard_pre_mul_raw_haz_T_179)
node _raw_hazard_pre_T_40 = eq(raw_hazard_pre_is_garbage_8, UInt<1>(0h0))
node _raw_hazard_pre_T_41 = or(raw_hazard_pre_pre_raw_haz_8, raw_hazard_pre_mul_raw_haz_8)
node _raw_hazard_pre_T_42 = and(_raw_hazard_pre_T_40, _raw_hazard_pre_T_41)
node _raw_hazard_pre_T_43 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_pre_T_44 = and(_raw_hazard_pre_T_42, _raw_hazard_pre_T_43)
node _raw_hazard_pre_is_garbage_T_45 = and(mesh.io.tags_in_progress[9].addr.is_acc_addr, mesh.io.tags_in_progress[9].addr.accumulate)
node _raw_hazard_pre_is_garbage_T_46 = and(_raw_hazard_pre_is_garbage_T_45, mesh.io.tags_in_progress[9].addr.read_full_acc_row)
node _raw_hazard_pre_is_garbage_T_47 = andr(mesh.io.tags_in_progress[9].addr.data)
node _raw_hazard_pre_is_garbage_T_48 = and(_raw_hazard_pre_is_garbage_T_46, _raw_hazard_pre_is_garbage_T_47)
node _raw_hazard_pre_is_garbage_T_49 = bits(mesh.io.tags_in_progress[9].addr.garbage_bit, 0, 0)
node raw_hazard_pre_is_garbage_9 = and(_raw_hazard_pre_is_garbage_T_48, _raw_hazard_pre_is_garbage_T_49)
wire _raw_hazard_pre_pre_raw_haz_WIRE_36 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_pre_raw_haz_WIRE_37 : UInt<32>
connect _raw_hazard_pre_pre_raw_haz_WIRE_37, rs1s[0]
node _raw_hazard_pre_pre_raw_haz_T_81 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_37, 13, 0)
connect _raw_hazard_pre_pre_raw_haz_WIRE_36.data, _raw_hazard_pre_pre_raw_haz_T_81
node _raw_hazard_pre_pre_raw_haz_T_82 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_37, 14, 14)
connect _raw_hazard_pre_pre_raw_haz_WIRE_36.garbage_bit, _raw_hazard_pre_pre_raw_haz_T_82
node _raw_hazard_pre_pre_raw_haz_T_83 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_37, 25, 15)
connect _raw_hazard_pre_pre_raw_haz_WIRE_36.garbage, _raw_hazard_pre_pre_raw_haz_T_83
node _raw_hazard_pre_pre_raw_haz_T_84 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_37, 28, 26)
wire _raw_hazard_pre_pre_raw_haz_WIRE_38 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_38, _raw_hazard_pre_pre_raw_haz_T_84
wire _raw_hazard_pre_pre_raw_haz_WIRE_39 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_39, _raw_hazard_pre_pre_raw_haz_WIRE_38
connect _raw_hazard_pre_pre_raw_haz_WIRE_36.norm_cmd, _raw_hazard_pre_pre_raw_haz_WIRE_39
node _raw_hazard_pre_pre_raw_haz_T_85 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_37, 29, 29)
connect _raw_hazard_pre_pre_raw_haz_WIRE_36.read_full_acc_row, _raw_hazard_pre_pre_raw_haz_T_85
node _raw_hazard_pre_pre_raw_haz_T_86 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_37, 30, 30)
connect _raw_hazard_pre_pre_raw_haz_WIRE_36.accumulate, _raw_hazard_pre_pre_raw_haz_T_86
node _raw_hazard_pre_pre_raw_haz_T_87 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_37, 31, 31)
connect _raw_hazard_pre_pre_raw_haz_WIRE_36.is_acc_addr, _raw_hazard_pre_pre_raw_haz_T_87
node _raw_hazard_pre_pre_raw_haz_T_88 = eq(mesh.io.tags_in_progress[9].addr.is_acc_addr, _raw_hazard_pre_pre_raw_haz_WIRE_36.is_acc_addr)
node _raw_hazard_pre_pre_raw_haz_T_89 = eq(mesh.io.tags_in_progress[9].addr.data, _raw_hazard_pre_pre_raw_haz_WIRE_36.data)
node raw_hazard_pre_pre_raw_haz_9 = and(_raw_hazard_pre_pre_raw_haz_T_88, _raw_hazard_pre_pre_raw_haz_T_89)
wire _raw_hazard_pre_mul_raw_haz_WIRE_72 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_73 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_73, rs1s[1]
node _raw_hazard_pre_mul_raw_haz_T_180 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_73, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_72.data, _raw_hazard_pre_mul_raw_haz_T_180
node _raw_hazard_pre_mul_raw_haz_T_181 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_73, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_72.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_181
node _raw_hazard_pre_mul_raw_haz_T_182 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_73, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_72.garbage, _raw_hazard_pre_mul_raw_haz_T_182
node _raw_hazard_pre_mul_raw_haz_T_183 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_73, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_74 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_74, _raw_hazard_pre_mul_raw_haz_T_183
wire _raw_hazard_pre_mul_raw_haz_WIRE_75 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_75, _raw_hazard_pre_mul_raw_haz_WIRE_74
connect _raw_hazard_pre_mul_raw_haz_WIRE_72.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_75
node _raw_hazard_pre_mul_raw_haz_T_184 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_73, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_72.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_184
node _raw_hazard_pre_mul_raw_haz_T_185 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_73, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_72.accumulate, _raw_hazard_pre_mul_raw_haz_T_185
node _raw_hazard_pre_mul_raw_haz_T_186 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_73, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_72.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_186
node _raw_hazard_pre_mul_raw_haz_T_187 = eq(mesh.io.tags_in_progress[9].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_72.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_188 = eq(mesh.io.tags_in_progress[9].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_72.data)
node _raw_hazard_pre_mul_raw_haz_T_189 = and(_raw_hazard_pre_mul_raw_haz_T_187, _raw_hazard_pre_mul_raw_haz_T_188)
wire _raw_hazard_pre_mul_raw_haz_WIRE_76 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_77 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_77, rs2s[1]
node _raw_hazard_pre_mul_raw_haz_T_190 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_77, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_76.data, _raw_hazard_pre_mul_raw_haz_T_190
node _raw_hazard_pre_mul_raw_haz_T_191 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_77, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_76.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_191
node _raw_hazard_pre_mul_raw_haz_T_192 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_77, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_76.garbage, _raw_hazard_pre_mul_raw_haz_T_192
node _raw_hazard_pre_mul_raw_haz_T_193 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_77, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_78 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_78, _raw_hazard_pre_mul_raw_haz_T_193
wire _raw_hazard_pre_mul_raw_haz_WIRE_79 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_79, _raw_hazard_pre_mul_raw_haz_WIRE_78
connect _raw_hazard_pre_mul_raw_haz_WIRE_76.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_79
node _raw_hazard_pre_mul_raw_haz_T_194 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_77, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_76.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_194
node _raw_hazard_pre_mul_raw_haz_T_195 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_77, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_76.accumulate, _raw_hazard_pre_mul_raw_haz_T_195
node _raw_hazard_pre_mul_raw_haz_T_196 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_77, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_76.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_196
node _raw_hazard_pre_mul_raw_haz_T_197 = eq(mesh.io.tags_in_progress[9].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_76.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_198 = eq(mesh.io.tags_in_progress[9].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_76.data)
node _raw_hazard_pre_mul_raw_haz_T_199 = and(_raw_hazard_pre_mul_raw_haz_T_197, _raw_hazard_pre_mul_raw_haz_T_198)
node raw_hazard_pre_mul_raw_haz_9 = or(_raw_hazard_pre_mul_raw_haz_T_189, _raw_hazard_pre_mul_raw_haz_T_199)
node _raw_hazard_pre_T_45 = eq(raw_hazard_pre_is_garbage_9, UInt<1>(0h0))
node _raw_hazard_pre_T_46 = or(raw_hazard_pre_pre_raw_haz_9, raw_hazard_pre_mul_raw_haz_9)
node _raw_hazard_pre_T_47 = and(_raw_hazard_pre_T_45, _raw_hazard_pre_T_46)
node _raw_hazard_pre_T_48 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_pre_T_49 = and(_raw_hazard_pre_T_47, _raw_hazard_pre_T_48)
node _raw_hazard_pre_is_garbage_T_50 = and(mesh.io.tags_in_progress[10].addr.is_acc_addr, mesh.io.tags_in_progress[10].addr.accumulate)
node _raw_hazard_pre_is_garbage_T_51 = and(_raw_hazard_pre_is_garbage_T_50, mesh.io.tags_in_progress[10].addr.read_full_acc_row)
node _raw_hazard_pre_is_garbage_T_52 = andr(mesh.io.tags_in_progress[10].addr.data)
node _raw_hazard_pre_is_garbage_T_53 = and(_raw_hazard_pre_is_garbage_T_51, _raw_hazard_pre_is_garbage_T_52)
node _raw_hazard_pre_is_garbage_T_54 = bits(mesh.io.tags_in_progress[10].addr.garbage_bit, 0, 0)
node raw_hazard_pre_is_garbage_10 = and(_raw_hazard_pre_is_garbage_T_53, _raw_hazard_pre_is_garbage_T_54)
wire _raw_hazard_pre_pre_raw_haz_WIRE_40 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_pre_raw_haz_WIRE_41 : UInt<32>
connect _raw_hazard_pre_pre_raw_haz_WIRE_41, rs1s[0]
node _raw_hazard_pre_pre_raw_haz_T_90 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_41, 13, 0)
connect _raw_hazard_pre_pre_raw_haz_WIRE_40.data, _raw_hazard_pre_pre_raw_haz_T_90
node _raw_hazard_pre_pre_raw_haz_T_91 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_41, 14, 14)
connect _raw_hazard_pre_pre_raw_haz_WIRE_40.garbage_bit, _raw_hazard_pre_pre_raw_haz_T_91
node _raw_hazard_pre_pre_raw_haz_T_92 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_41, 25, 15)
connect _raw_hazard_pre_pre_raw_haz_WIRE_40.garbage, _raw_hazard_pre_pre_raw_haz_T_92
node _raw_hazard_pre_pre_raw_haz_T_93 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_41, 28, 26)
wire _raw_hazard_pre_pre_raw_haz_WIRE_42 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_42, _raw_hazard_pre_pre_raw_haz_T_93
wire _raw_hazard_pre_pre_raw_haz_WIRE_43 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_43, _raw_hazard_pre_pre_raw_haz_WIRE_42
connect _raw_hazard_pre_pre_raw_haz_WIRE_40.norm_cmd, _raw_hazard_pre_pre_raw_haz_WIRE_43
node _raw_hazard_pre_pre_raw_haz_T_94 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_41, 29, 29)
connect _raw_hazard_pre_pre_raw_haz_WIRE_40.read_full_acc_row, _raw_hazard_pre_pre_raw_haz_T_94
node _raw_hazard_pre_pre_raw_haz_T_95 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_41, 30, 30)
connect _raw_hazard_pre_pre_raw_haz_WIRE_40.accumulate, _raw_hazard_pre_pre_raw_haz_T_95
node _raw_hazard_pre_pre_raw_haz_T_96 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_41, 31, 31)
connect _raw_hazard_pre_pre_raw_haz_WIRE_40.is_acc_addr, _raw_hazard_pre_pre_raw_haz_T_96
node _raw_hazard_pre_pre_raw_haz_T_97 = eq(mesh.io.tags_in_progress[10].addr.is_acc_addr, _raw_hazard_pre_pre_raw_haz_WIRE_40.is_acc_addr)
node _raw_hazard_pre_pre_raw_haz_T_98 = eq(mesh.io.tags_in_progress[10].addr.data, _raw_hazard_pre_pre_raw_haz_WIRE_40.data)
node raw_hazard_pre_pre_raw_haz_10 = and(_raw_hazard_pre_pre_raw_haz_T_97, _raw_hazard_pre_pre_raw_haz_T_98)
wire _raw_hazard_pre_mul_raw_haz_WIRE_80 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_81 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_81, rs1s[1]
node _raw_hazard_pre_mul_raw_haz_T_200 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_81, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_80.data, _raw_hazard_pre_mul_raw_haz_T_200
node _raw_hazard_pre_mul_raw_haz_T_201 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_81, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_80.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_201
node _raw_hazard_pre_mul_raw_haz_T_202 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_81, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_80.garbage, _raw_hazard_pre_mul_raw_haz_T_202
node _raw_hazard_pre_mul_raw_haz_T_203 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_81, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_82 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_82, _raw_hazard_pre_mul_raw_haz_T_203
wire _raw_hazard_pre_mul_raw_haz_WIRE_83 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_83, _raw_hazard_pre_mul_raw_haz_WIRE_82
connect _raw_hazard_pre_mul_raw_haz_WIRE_80.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_83
node _raw_hazard_pre_mul_raw_haz_T_204 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_81, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_80.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_204
node _raw_hazard_pre_mul_raw_haz_T_205 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_81, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_80.accumulate, _raw_hazard_pre_mul_raw_haz_T_205
node _raw_hazard_pre_mul_raw_haz_T_206 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_81, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_80.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_206
node _raw_hazard_pre_mul_raw_haz_T_207 = eq(mesh.io.tags_in_progress[10].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_80.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_208 = eq(mesh.io.tags_in_progress[10].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_80.data)
node _raw_hazard_pre_mul_raw_haz_T_209 = and(_raw_hazard_pre_mul_raw_haz_T_207, _raw_hazard_pre_mul_raw_haz_T_208)
wire _raw_hazard_pre_mul_raw_haz_WIRE_84 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_85 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_85, rs2s[1]
node _raw_hazard_pre_mul_raw_haz_T_210 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_85, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_84.data, _raw_hazard_pre_mul_raw_haz_T_210
node _raw_hazard_pre_mul_raw_haz_T_211 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_85, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_84.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_211
node _raw_hazard_pre_mul_raw_haz_T_212 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_85, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_84.garbage, _raw_hazard_pre_mul_raw_haz_T_212
node _raw_hazard_pre_mul_raw_haz_T_213 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_85, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_86 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_86, _raw_hazard_pre_mul_raw_haz_T_213
wire _raw_hazard_pre_mul_raw_haz_WIRE_87 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_87, _raw_hazard_pre_mul_raw_haz_WIRE_86
connect _raw_hazard_pre_mul_raw_haz_WIRE_84.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_87
node _raw_hazard_pre_mul_raw_haz_T_214 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_85, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_84.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_214
node _raw_hazard_pre_mul_raw_haz_T_215 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_85, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_84.accumulate, _raw_hazard_pre_mul_raw_haz_T_215
node _raw_hazard_pre_mul_raw_haz_T_216 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_85, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_84.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_216
node _raw_hazard_pre_mul_raw_haz_T_217 = eq(mesh.io.tags_in_progress[10].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_84.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_218 = eq(mesh.io.tags_in_progress[10].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_84.data)
node _raw_hazard_pre_mul_raw_haz_T_219 = and(_raw_hazard_pre_mul_raw_haz_T_217, _raw_hazard_pre_mul_raw_haz_T_218)
node raw_hazard_pre_mul_raw_haz_10 = or(_raw_hazard_pre_mul_raw_haz_T_209, _raw_hazard_pre_mul_raw_haz_T_219)
node _raw_hazard_pre_T_50 = eq(raw_hazard_pre_is_garbage_10, UInt<1>(0h0))
node _raw_hazard_pre_T_51 = or(raw_hazard_pre_pre_raw_haz_10, raw_hazard_pre_mul_raw_haz_10)
node _raw_hazard_pre_T_52 = and(_raw_hazard_pre_T_50, _raw_hazard_pre_T_51)
node _raw_hazard_pre_T_53 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_pre_T_54 = and(_raw_hazard_pre_T_52, _raw_hazard_pre_T_53)
node _raw_hazard_pre_is_garbage_T_55 = and(mesh.io.tags_in_progress[11].addr.is_acc_addr, mesh.io.tags_in_progress[11].addr.accumulate)
node _raw_hazard_pre_is_garbage_T_56 = and(_raw_hazard_pre_is_garbage_T_55, mesh.io.tags_in_progress[11].addr.read_full_acc_row)
node _raw_hazard_pre_is_garbage_T_57 = andr(mesh.io.tags_in_progress[11].addr.data)
node _raw_hazard_pre_is_garbage_T_58 = and(_raw_hazard_pre_is_garbage_T_56, _raw_hazard_pre_is_garbage_T_57)
node _raw_hazard_pre_is_garbage_T_59 = bits(mesh.io.tags_in_progress[11].addr.garbage_bit, 0, 0)
node raw_hazard_pre_is_garbage_11 = and(_raw_hazard_pre_is_garbage_T_58, _raw_hazard_pre_is_garbage_T_59)
wire _raw_hazard_pre_pre_raw_haz_WIRE_44 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_pre_raw_haz_WIRE_45 : UInt<32>
connect _raw_hazard_pre_pre_raw_haz_WIRE_45, rs1s[0]
node _raw_hazard_pre_pre_raw_haz_T_99 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_45, 13, 0)
connect _raw_hazard_pre_pre_raw_haz_WIRE_44.data, _raw_hazard_pre_pre_raw_haz_T_99
node _raw_hazard_pre_pre_raw_haz_T_100 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_45, 14, 14)
connect _raw_hazard_pre_pre_raw_haz_WIRE_44.garbage_bit, _raw_hazard_pre_pre_raw_haz_T_100
node _raw_hazard_pre_pre_raw_haz_T_101 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_45, 25, 15)
connect _raw_hazard_pre_pre_raw_haz_WIRE_44.garbage, _raw_hazard_pre_pre_raw_haz_T_101
node _raw_hazard_pre_pre_raw_haz_T_102 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_45, 28, 26)
wire _raw_hazard_pre_pre_raw_haz_WIRE_46 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_46, _raw_hazard_pre_pre_raw_haz_T_102
wire _raw_hazard_pre_pre_raw_haz_WIRE_47 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_47, _raw_hazard_pre_pre_raw_haz_WIRE_46
connect _raw_hazard_pre_pre_raw_haz_WIRE_44.norm_cmd, _raw_hazard_pre_pre_raw_haz_WIRE_47
node _raw_hazard_pre_pre_raw_haz_T_103 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_45, 29, 29)
connect _raw_hazard_pre_pre_raw_haz_WIRE_44.read_full_acc_row, _raw_hazard_pre_pre_raw_haz_T_103
node _raw_hazard_pre_pre_raw_haz_T_104 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_45, 30, 30)
connect _raw_hazard_pre_pre_raw_haz_WIRE_44.accumulate, _raw_hazard_pre_pre_raw_haz_T_104
node _raw_hazard_pre_pre_raw_haz_T_105 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_45, 31, 31)
connect _raw_hazard_pre_pre_raw_haz_WIRE_44.is_acc_addr, _raw_hazard_pre_pre_raw_haz_T_105
node _raw_hazard_pre_pre_raw_haz_T_106 = eq(mesh.io.tags_in_progress[11].addr.is_acc_addr, _raw_hazard_pre_pre_raw_haz_WIRE_44.is_acc_addr)
node _raw_hazard_pre_pre_raw_haz_T_107 = eq(mesh.io.tags_in_progress[11].addr.data, _raw_hazard_pre_pre_raw_haz_WIRE_44.data)
node raw_hazard_pre_pre_raw_haz_11 = and(_raw_hazard_pre_pre_raw_haz_T_106, _raw_hazard_pre_pre_raw_haz_T_107)
wire _raw_hazard_pre_mul_raw_haz_WIRE_88 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_89 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_89, rs1s[1]
node _raw_hazard_pre_mul_raw_haz_T_220 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_89, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_88.data, _raw_hazard_pre_mul_raw_haz_T_220
node _raw_hazard_pre_mul_raw_haz_T_221 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_89, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_88.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_221
node _raw_hazard_pre_mul_raw_haz_T_222 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_89, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_88.garbage, _raw_hazard_pre_mul_raw_haz_T_222
node _raw_hazard_pre_mul_raw_haz_T_223 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_89, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_90 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_90, _raw_hazard_pre_mul_raw_haz_T_223
wire _raw_hazard_pre_mul_raw_haz_WIRE_91 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_91, _raw_hazard_pre_mul_raw_haz_WIRE_90
connect _raw_hazard_pre_mul_raw_haz_WIRE_88.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_91
node _raw_hazard_pre_mul_raw_haz_T_224 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_89, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_88.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_224
node _raw_hazard_pre_mul_raw_haz_T_225 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_89, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_88.accumulate, _raw_hazard_pre_mul_raw_haz_T_225
node _raw_hazard_pre_mul_raw_haz_T_226 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_89, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_88.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_226
node _raw_hazard_pre_mul_raw_haz_T_227 = eq(mesh.io.tags_in_progress[11].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_88.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_228 = eq(mesh.io.tags_in_progress[11].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_88.data)
node _raw_hazard_pre_mul_raw_haz_T_229 = and(_raw_hazard_pre_mul_raw_haz_T_227, _raw_hazard_pre_mul_raw_haz_T_228)
wire _raw_hazard_pre_mul_raw_haz_WIRE_92 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_93 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_93, rs2s[1]
node _raw_hazard_pre_mul_raw_haz_T_230 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_93, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_92.data, _raw_hazard_pre_mul_raw_haz_T_230
node _raw_hazard_pre_mul_raw_haz_T_231 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_93, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_92.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_231
node _raw_hazard_pre_mul_raw_haz_T_232 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_93, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_92.garbage, _raw_hazard_pre_mul_raw_haz_T_232
node _raw_hazard_pre_mul_raw_haz_T_233 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_93, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_94 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_94, _raw_hazard_pre_mul_raw_haz_T_233
wire _raw_hazard_pre_mul_raw_haz_WIRE_95 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_95, _raw_hazard_pre_mul_raw_haz_WIRE_94
connect _raw_hazard_pre_mul_raw_haz_WIRE_92.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_95
node _raw_hazard_pre_mul_raw_haz_T_234 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_93, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_92.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_234
node _raw_hazard_pre_mul_raw_haz_T_235 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_93, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_92.accumulate, _raw_hazard_pre_mul_raw_haz_T_235
node _raw_hazard_pre_mul_raw_haz_T_236 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_93, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_92.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_236
node _raw_hazard_pre_mul_raw_haz_T_237 = eq(mesh.io.tags_in_progress[11].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_92.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_238 = eq(mesh.io.tags_in_progress[11].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_92.data)
node _raw_hazard_pre_mul_raw_haz_T_239 = and(_raw_hazard_pre_mul_raw_haz_T_237, _raw_hazard_pre_mul_raw_haz_T_238)
node raw_hazard_pre_mul_raw_haz_11 = or(_raw_hazard_pre_mul_raw_haz_T_229, _raw_hazard_pre_mul_raw_haz_T_239)
node _raw_hazard_pre_T_55 = eq(raw_hazard_pre_is_garbage_11, UInt<1>(0h0))
node _raw_hazard_pre_T_56 = or(raw_hazard_pre_pre_raw_haz_11, raw_hazard_pre_mul_raw_haz_11)
node _raw_hazard_pre_T_57 = and(_raw_hazard_pre_T_55, _raw_hazard_pre_T_56)
node _raw_hazard_pre_T_58 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_pre_T_59 = and(_raw_hazard_pre_T_57, _raw_hazard_pre_T_58)
node _raw_hazard_pre_is_garbage_T_60 = and(mesh.io.tags_in_progress[12].addr.is_acc_addr, mesh.io.tags_in_progress[12].addr.accumulate)
node _raw_hazard_pre_is_garbage_T_61 = and(_raw_hazard_pre_is_garbage_T_60, mesh.io.tags_in_progress[12].addr.read_full_acc_row)
node _raw_hazard_pre_is_garbage_T_62 = andr(mesh.io.tags_in_progress[12].addr.data)
node _raw_hazard_pre_is_garbage_T_63 = and(_raw_hazard_pre_is_garbage_T_61, _raw_hazard_pre_is_garbage_T_62)
node _raw_hazard_pre_is_garbage_T_64 = bits(mesh.io.tags_in_progress[12].addr.garbage_bit, 0, 0)
node raw_hazard_pre_is_garbage_12 = and(_raw_hazard_pre_is_garbage_T_63, _raw_hazard_pre_is_garbage_T_64)
wire _raw_hazard_pre_pre_raw_haz_WIRE_48 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_pre_raw_haz_WIRE_49 : UInt<32>
connect _raw_hazard_pre_pre_raw_haz_WIRE_49, rs1s[0]
node _raw_hazard_pre_pre_raw_haz_T_108 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_49, 13, 0)
connect _raw_hazard_pre_pre_raw_haz_WIRE_48.data, _raw_hazard_pre_pre_raw_haz_T_108
node _raw_hazard_pre_pre_raw_haz_T_109 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_49, 14, 14)
connect _raw_hazard_pre_pre_raw_haz_WIRE_48.garbage_bit, _raw_hazard_pre_pre_raw_haz_T_109
node _raw_hazard_pre_pre_raw_haz_T_110 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_49, 25, 15)
connect _raw_hazard_pre_pre_raw_haz_WIRE_48.garbage, _raw_hazard_pre_pre_raw_haz_T_110
node _raw_hazard_pre_pre_raw_haz_T_111 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_49, 28, 26)
wire _raw_hazard_pre_pre_raw_haz_WIRE_50 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_50, _raw_hazard_pre_pre_raw_haz_T_111
wire _raw_hazard_pre_pre_raw_haz_WIRE_51 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_51, _raw_hazard_pre_pre_raw_haz_WIRE_50
connect _raw_hazard_pre_pre_raw_haz_WIRE_48.norm_cmd, _raw_hazard_pre_pre_raw_haz_WIRE_51
node _raw_hazard_pre_pre_raw_haz_T_112 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_49, 29, 29)
connect _raw_hazard_pre_pre_raw_haz_WIRE_48.read_full_acc_row, _raw_hazard_pre_pre_raw_haz_T_112
node _raw_hazard_pre_pre_raw_haz_T_113 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_49, 30, 30)
connect _raw_hazard_pre_pre_raw_haz_WIRE_48.accumulate, _raw_hazard_pre_pre_raw_haz_T_113
node _raw_hazard_pre_pre_raw_haz_T_114 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_49, 31, 31)
connect _raw_hazard_pre_pre_raw_haz_WIRE_48.is_acc_addr, _raw_hazard_pre_pre_raw_haz_T_114
node _raw_hazard_pre_pre_raw_haz_T_115 = eq(mesh.io.tags_in_progress[12].addr.is_acc_addr, _raw_hazard_pre_pre_raw_haz_WIRE_48.is_acc_addr)
node _raw_hazard_pre_pre_raw_haz_T_116 = eq(mesh.io.tags_in_progress[12].addr.data, _raw_hazard_pre_pre_raw_haz_WIRE_48.data)
node raw_hazard_pre_pre_raw_haz_12 = and(_raw_hazard_pre_pre_raw_haz_T_115, _raw_hazard_pre_pre_raw_haz_T_116)
wire _raw_hazard_pre_mul_raw_haz_WIRE_96 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_97 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_97, rs1s[1]
node _raw_hazard_pre_mul_raw_haz_T_240 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_97, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_96.data, _raw_hazard_pre_mul_raw_haz_T_240
node _raw_hazard_pre_mul_raw_haz_T_241 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_97, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_96.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_241
node _raw_hazard_pre_mul_raw_haz_T_242 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_97, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_96.garbage, _raw_hazard_pre_mul_raw_haz_T_242
node _raw_hazard_pre_mul_raw_haz_T_243 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_97, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_98 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_98, _raw_hazard_pre_mul_raw_haz_T_243
wire _raw_hazard_pre_mul_raw_haz_WIRE_99 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_99, _raw_hazard_pre_mul_raw_haz_WIRE_98
connect _raw_hazard_pre_mul_raw_haz_WIRE_96.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_99
node _raw_hazard_pre_mul_raw_haz_T_244 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_97, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_96.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_244
node _raw_hazard_pre_mul_raw_haz_T_245 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_97, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_96.accumulate, _raw_hazard_pre_mul_raw_haz_T_245
node _raw_hazard_pre_mul_raw_haz_T_246 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_97, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_96.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_246
node _raw_hazard_pre_mul_raw_haz_T_247 = eq(mesh.io.tags_in_progress[12].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_96.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_248 = eq(mesh.io.tags_in_progress[12].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_96.data)
node _raw_hazard_pre_mul_raw_haz_T_249 = and(_raw_hazard_pre_mul_raw_haz_T_247, _raw_hazard_pre_mul_raw_haz_T_248)
wire _raw_hazard_pre_mul_raw_haz_WIRE_100 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_101 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_101, rs2s[1]
node _raw_hazard_pre_mul_raw_haz_T_250 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_101, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_100.data, _raw_hazard_pre_mul_raw_haz_T_250
node _raw_hazard_pre_mul_raw_haz_T_251 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_101, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_100.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_251
node _raw_hazard_pre_mul_raw_haz_T_252 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_101, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_100.garbage, _raw_hazard_pre_mul_raw_haz_T_252
node _raw_hazard_pre_mul_raw_haz_T_253 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_101, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_102 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_102, _raw_hazard_pre_mul_raw_haz_T_253
wire _raw_hazard_pre_mul_raw_haz_WIRE_103 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_103, _raw_hazard_pre_mul_raw_haz_WIRE_102
connect _raw_hazard_pre_mul_raw_haz_WIRE_100.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_103
node _raw_hazard_pre_mul_raw_haz_T_254 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_101, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_100.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_254
node _raw_hazard_pre_mul_raw_haz_T_255 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_101, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_100.accumulate, _raw_hazard_pre_mul_raw_haz_T_255
node _raw_hazard_pre_mul_raw_haz_T_256 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_101, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_100.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_256
node _raw_hazard_pre_mul_raw_haz_T_257 = eq(mesh.io.tags_in_progress[12].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_100.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_258 = eq(mesh.io.tags_in_progress[12].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_100.data)
node _raw_hazard_pre_mul_raw_haz_T_259 = and(_raw_hazard_pre_mul_raw_haz_T_257, _raw_hazard_pre_mul_raw_haz_T_258)
node raw_hazard_pre_mul_raw_haz_12 = or(_raw_hazard_pre_mul_raw_haz_T_249, _raw_hazard_pre_mul_raw_haz_T_259)
node _raw_hazard_pre_T_60 = eq(raw_hazard_pre_is_garbage_12, UInt<1>(0h0))
node _raw_hazard_pre_T_61 = or(raw_hazard_pre_pre_raw_haz_12, raw_hazard_pre_mul_raw_haz_12)
node _raw_hazard_pre_T_62 = and(_raw_hazard_pre_T_60, _raw_hazard_pre_T_61)
node _raw_hazard_pre_T_63 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_pre_T_64 = and(_raw_hazard_pre_T_62, _raw_hazard_pre_T_63)
node _raw_hazard_pre_is_garbage_T_65 = and(mesh.io.tags_in_progress[13].addr.is_acc_addr, mesh.io.tags_in_progress[13].addr.accumulate)
node _raw_hazard_pre_is_garbage_T_66 = and(_raw_hazard_pre_is_garbage_T_65, mesh.io.tags_in_progress[13].addr.read_full_acc_row)
node _raw_hazard_pre_is_garbage_T_67 = andr(mesh.io.tags_in_progress[13].addr.data)
node _raw_hazard_pre_is_garbage_T_68 = and(_raw_hazard_pre_is_garbage_T_66, _raw_hazard_pre_is_garbage_T_67)
node _raw_hazard_pre_is_garbage_T_69 = bits(mesh.io.tags_in_progress[13].addr.garbage_bit, 0, 0)
node raw_hazard_pre_is_garbage_13 = and(_raw_hazard_pre_is_garbage_T_68, _raw_hazard_pre_is_garbage_T_69)
wire _raw_hazard_pre_pre_raw_haz_WIRE_52 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_pre_raw_haz_WIRE_53 : UInt<32>
connect _raw_hazard_pre_pre_raw_haz_WIRE_53, rs1s[0]
node _raw_hazard_pre_pre_raw_haz_T_117 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_53, 13, 0)
connect _raw_hazard_pre_pre_raw_haz_WIRE_52.data, _raw_hazard_pre_pre_raw_haz_T_117
node _raw_hazard_pre_pre_raw_haz_T_118 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_53, 14, 14)
connect _raw_hazard_pre_pre_raw_haz_WIRE_52.garbage_bit, _raw_hazard_pre_pre_raw_haz_T_118
node _raw_hazard_pre_pre_raw_haz_T_119 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_53, 25, 15)
connect _raw_hazard_pre_pre_raw_haz_WIRE_52.garbage, _raw_hazard_pre_pre_raw_haz_T_119
node _raw_hazard_pre_pre_raw_haz_T_120 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_53, 28, 26)
wire _raw_hazard_pre_pre_raw_haz_WIRE_54 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_54, _raw_hazard_pre_pre_raw_haz_T_120
wire _raw_hazard_pre_pre_raw_haz_WIRE_55 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_55, _raw_hazard_pre_pre_raw_haz_WIRE_54
connect _raw_hazard_pre_pre_raw_haz_WIRE_52.norm_cmd, _raw_hazard_pre_pre_raw_haz_WIRE_55
node _raw_hazard_pre_pre_raw_haz_T_121 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_53, 29, 29)
connect _raw_hazard_pre_pre_raw_haz_WIRE_52.read_full_acc_row, _raw_hazard_pre_pre_raw_haz_T_121
node _raw_hazard_pre_pre_raw_haz_T_122 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_53, 30, 30)
connect _raw_hazard_pre_pre_raw_haz_WIRE_52.accumulate, _raw_hazard_pre_pre_raw_haz_T_122
node _raw_hazard_pre_pre_raw_haz_T_123 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_53, 31, 31)
connect _raw_hazard_pre_pre_raw_haz_WIRE_52.is_acc_addr, _raw_hazard_pre_pre_raw_haz_T_123
node _raw_hazard_pre_pre_raw_haz_T_124 = eq(mesh.io.tags_in_progress[13].addr.is_acc_addr, _raw_hazard_pre_pre_raw_haz_WIRE_52.is_acc_addr)
node _raw_hazard_pre_pre_raw_haz_T_125 = eq(mesh.io.tags_in_progress[13].addr.data, _raw_hazard_pre_pre_raw_haz_WIRE_52.data)
node raw_hazard_pre_pre_raw_haz_13 = and(_raw_hazard_pre_pre_raw_haz_T_124, _raw_hazard_pre_pre_raw_haz_T_125)
wire _raw_hazard_pre_mul_raw_haz_WIRE_104 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_105 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_105, rs1s[1]
node _raw_hazard_pre_mul_raw_haz_T_260 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_105, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_104.data, _raw_hazard_pre_mul_raw_haz_T_260
node _raw_hazard_pre_mul_raw_haz_T_261 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_105, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_104.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_261
node _raw_hazard_pre_mul_raw_haz_T_262 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_105, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_104.garbage, _raw_hazard_pre_mul_raw_haz_T_262
node _raw_hazard_pre_mul_raw_haz_T_263 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_105, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_106 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_106, _raw_hazard_pre_mul_raw_haz_T_263
wire _raw_hazard_pre_mul_raw_haz_WIRE_107 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_107, _raw_hazard_pre_mul_raw_haz_WIRE_106
connect _raw_hazard_pre_mul_raw_haz_WIRE_104.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_107
node _raw_hazard_pre_mul_raw_haz_T_264 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_105, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_104.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_264
node _raw_hazard_pre_mul_raw_haz_T_265 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_105, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_104.accumulate, _raw_hazard_pre_mul_raw_haz_T_265
node _raw_hazard_pre_mul_raw_haz_T_266 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_105, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_104.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_266
node _raw_hazard_pre_mul_raw_haz_T_267 = eq(mesh.io.tags_in_progress[13].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_104.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_268 = eq(mesh.io.tags_in_progress[13].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_104.data)
node _raw_hazard_pre_mul_raw_haz_T_269 = and(_raw_hazard_pre_mul_raw_haz_T_267, _raw_hazard_pre_mul_raw_haz_T_268)
wire _raw_hazard_pre_mul_raw_haz_WIRE_108 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_109 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_109, rs2s[1]
node _raw_hazard_pre_mul_raw_haz_T_270 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_109, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_108.data, _raw_hazard_pre_mul_raw_haz_T_270
node _raw_hazard_pre_mul_raw_haz_T_271 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_109, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_108.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_271
node _raw_hazard_pre_mul_raw_haz_T_272 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_109, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_108.garbage, _raw_hazard_pre_mul_raw_haz_T_272
node _raw_hazard_pre_mul_raw_haz_T_273 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_109, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_110 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_110, _raw_hazard_pre_mul_raw_haz_T_273
wire _raw_hazard_pre_mul_raw_haz_WIRE_111 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_111, _raw_hazard_pre_mul_raw_haz_WIRE_110
connect _raw_hazard_pre_mul_raw_haz_WIRE_108.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_111
node _raw_hazard_pre_mul_raw_haz_T_274 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_109, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_108.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_274
node _raw_hazard_pre_mul_raw_haz_T_275 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_109, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_108.accumulate, _raw_hazard_pre_mul_raw_haz_T_275
node _raw_hazard_pre_mul_raw_haz_T_276 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_109, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_108.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_276
node _raw_hazard_pre_mul_raw_haz_T_277 = eq(mesh.io.tags_in_progress[13].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_108.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_278 = eq(mesh.io.tags_in_progress[13].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_108.data)
node _raw_hazard_pre_mul_raw_haz_T_279 = and(_raw_hazard_pre_mul_raw_haz_T_277, _raw_hazard_pre_mul_raw_haz_T_278)
node raw_hazard_pre_mul_raw_haz_13 = or(_raw_hazard_pre_mul_raw_haz_T_269, _raw_hazard_pre_mul_raw_haz_T_279)
node _raw_hazard_pre_T_65 = eq(raw_hazard_pre_is_garbage_13, UInt<1>(0h0))
node _raw_hazard_pre_T_66 = or(raw_hazard_pre_pre_raw_haz_13, raw_hazard_pre_mul_raw_haz_13)
node _raw_hazard_pre_T_67 = and(_raw_hazard_pre_T_65, _raw_hazard_pre_T_66)
node _raw_hazard_pre_T_68 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_pre_T_69 = and(_raw_hazard_pre_T_67, _raw_hazard_pre_T_68)
node _raw_hazard_pre_is_garbage_T_70 = and(mesh.io.tags_in_progress[14].addr.is_acc_addr, mesh.io.tags_in_progress[14].addr.accumulate)
node _raw_hazard_pre_is_garbage_T_71 = and(_raw_hazard_pre_is_garbage_T_70, mesh.io.tags_in_progress[14].addr.read_full_acc_row)
node _raw_hazard_pre_is_garbage_T_72 = andr(mesh.io.tags_in_progress[14].addr.data)
node _raw_hazard_pre_is_garbage_T_73 = and(_raw_hazard_pre_is_garbage_T_71, _raw_hazard_pre_is_garbage_T_72)
node _raw_hazard_pre_is_garbage_T_74 = bits(mesh.io.tags_in_progress[14].addr.garbage_bit, 0, 0)
node raw_hazard_pre_is_garbage_14 = and(_raw_hazard_pre_is_garbage_T_73, _raw_hazard_pre_is_garbage_T_74)
wire _raw_hazard_pre_pre_raw_haz_WIRE_56 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_pre_raw_haz_WIRE_57 : UInt<32>
connect _raw_hazard_pre_pre_raw_haz_WIRE_57, rs1s[0]
node _raw_hazard_pre_pre_raw_haz_T_126 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_57, 13, 0)
connect _raw_hazard_pre_pre_raw_haz_WIRE_56.data, _raw_hazard_pre_pre_raw_haz_T_126
node _raw_hazard_pre_pre_raw_haz_T_127 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_57, 14, 14)
connect _raw_hazard_pre_pre_raw_haz_WIRE_56.garbage_bit, _raw_hazard_pre_pre_raw_haz_T_127
node _raw_hazard_pre_pre_raw_haz_T_128 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_57, 25, 15)
connect _raw_hazard_pre_pre_raw_haz_WIRE_56.garbage, _raw_hazard_pre_pre_raw_haz_T_128
node _raw_hazard_pre_pre_raw_haz_T_129 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_57, 28, 26)
wire _raw_hazard_pre_pre_raw_haz_WIRE_58 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_58, _raw_hazard_pre_pre_raw_haz_T_129
wire _raw_hazard_pre_pre_raw_haz_WIRE_59 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_59, _raw_hazard_pre_pre_raw_haz_WIRE_58
connect _raw_hazard_pre_pre_raw_haz_WIRE_56.norm_cmd, _raw_hazard_pre_pre_raw_haz_WIRE_59
node _raw_hazard_pre_pre_raw_haz_T_130 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_57, 29, 29)
connect _raw_hazard_pre_pre_raw_haz_WIRE_56.read_full_acc_row, _raw_hazard_pre_pre_raw_haz_T_130
node _raw_hazard_pre_pre_raw_haz_T_131 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_57, 30, 30)
connect _raw_hazard_pre_pre_raw_haz_WIRE_56.accumulate, _raw_hazard_pre_pre_raw_haz_T_131
node _raw_hazard_pre_pre_raw_haz_T_132 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_57, 31, 31)
connect _raw_hazard_pre_pre_raw_haz_WIRE_56.is_acc_addr, _raw_hazard_pre_pre_raw_haz_T_132
node _raw_hazard_pre_pre_raw_haz_T_133 = eq(mesh.io.tags_in_progress[14].addr.is_acc_addr, _raw_hazard_pre_pre_raw_haz_WIRE_56.is_acc_addr)
node _raw_hazard_pre_pre_raw_haz_T_134 = eq(mesh.io.tags_in_progress[14].addr.data, _raw_hazard_pre_pre_raw_haz_WIRE_56.data)
node raw_hazard_pre_pre_raw_haz_14 = and(_raw_hazard_pre_pre_raw_haz_T_133, _raw_hazard_pre_pre_raw_haz_T_134)
wire _raw_hazard_pre_mul_raw_haz_WIRE_112 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_113 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_113, rs1s[1]
node _raw_hazard_pre_mul_raw_haz_T_280 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_113, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_112.data, _raw_hazard_pre_mul_raw_haz_T_280
node _raw_hazard_pre_mul_raw_haz_T_281 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_113, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_112.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_281
node _raw_hazard_pre_mul_raw_haz_T_282 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_113, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_112.garbage, _raw_hazard_pre_mul_raw_haz_T_282
node _raw_hazard_pre_mul_raw_haz_T_283 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_113, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_114 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_114, _raw_hazard_pre_mul_raw_haz_T_283
wire _raw_hazard_pre_mul_raw_haz_WIRE_115 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_115, _raw_hazard_pre_mul_raw_haz_WIRE_114
connect _raw_hazard_pre_mul_raw_haz_WIRE_112.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_115
node _raw_hazard_pre_mul_raw_haz_T_284 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_113, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_112.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_284
node _raw_hazard_pre_mul_raw_haz_T_285 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_113, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_112.accumulate, _raw_hazard_pre_mul_raw_haz_T_285
node _raw_hazard_pre_mul_raw_haz_T_286 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_113, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_112.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_286
node _raw_hazard_pre_mul_raw_haz_T_287 = eq(mesh.io.tags_in_progress[14].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_112.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_288 = eq(mesh.io.tags_in_progress[14].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_112.data)
node _raw_hazard_pre_mul_raw_haz_T_289 = and(_raw_hazard_pre_mul_raw_haz_T_287, _raw_hazard_pre_mul_raw_haz_T_288)
wire _raw_hazard_pre_mul_raw_haz_WIRE_116 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_117 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_117, rs2s[1]
node _raw_hazard_pre_mul_raw_haz_T_290 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_117, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_116.data, _raw_hazard_pre_mul_raw_haz_T_290
node _raw_hazard_pre_mul_raw_haz_T_291 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_117, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_116.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_291
node _raw_hazard_pre_mul_raw_haz_T_292 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_117, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_116.garbage, _raw_hazard_pre_mul_raw_haz_T_292
node _raw_hazard_pre_mul_raw_haz_T_293 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_117, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_118 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_118, _raw_hazard_pre_mul_raw_haz_T_293
wire _raw_hazard_pre_mul_raw_haz_WIRE_119 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_119, _raw_hazard_pre_mul_raw_haz_WIRE_118
connect _raw_hazard_pre_mul_raw_haz_WIRE_116.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_119
node _raw_hazard_pre_mul_raw_haz_T_294 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_117, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_116.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_294
node _raw_hazard_pre_mul_raw_haz_T_295 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_117, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_116.accumulate, _raw_hazard_pre_mul_raw_haz_T_295
node _raw_hazard_pre_mul_raw_haz_T_296 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_117, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_116.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_296
node _raw_hazard_pre_mul_raw_haz_T_297 = eq(mesh.io.tags_in_progress[14].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_116.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_298 = eq(mesh.io.tags_in_progress[14].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_116.data)
node _raw_hazard_pre_mul_raw_haz_T_299 = and(_raw_hazard_pre_mul_raw_haz_T_297, _raw_hazard_pre_mul_raw_haz_T_298)
node raw_hazard_pre_mul_raw_haz_14 = or(_raw_hazard_pre_mul_raw_haz_T_289, _raw_hazard_pre_mul_raw_haz_T_299)
node _raw_hazard_pre_T_70 = eq(raw_hazard_pre_is_garbage_14, UInt<1>(0h0))
node _raw_hazard_pre_T_71 = or(raw_hazard_pre_pre_raw_haz_14, raw_hazard_pre_mul_raw_haz_14)
node _raw_hazard_pre_T_72 = and(_raw_hazard_pre_T_70, _raw_hazard_pre_T_71)
node _raw_hazard_pre_T_73 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_pre_T_74 = and(_raw_hazard_pre_T_72, _raw_hazard_pre_T_73)
node _raw_hazard_pre_is_garbage_T_75 = and(mesh.io.tags_in_progress[15].addr.is_acc_addr, mesh.io.tags_in_progress[15].addr.accumulate)
node _raw_hazard_pre_is_garbage_T_76 = and(_raw_hazard_pre_is_garbage_T_75, mesh.io.tags_in_progress[15].addr.read_full_acc_row)
node _raw_hazard_pre_is_garbage_T_77 = andr(mesh.io.tags_in_progress[15].addr.data)
node _raw_hazard_pre_is_garbage_T_78 = and(_raw_hazard_pre_is_garbage_T_76, _raw_hazard_pre_is_garbage_T_77)
node _raw_hazard_pre_is_garbage_T_79 = bits(mesh.io.tags_in_progress[15].addr.garbage_bit, 0, 0)
node raw_hazard_pre_is_garbage_15 = and(_raw_hazard_pre_is_garbage_T_78, _raw_hazard_pre_is_garbage_T_79)
wire _raw_hazard_pre_pre_raw_haz_WIRE_60 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_pre_raw_haz_WIRE_61 : UInt<32>
connect _raw_hazard_pre_pre_raw_haz_WIRE_61, rs1s[0]
node _raw_hazard_pre_pre_raw_haz_T_135 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_61, 13, 0)
connect _raw_hazard_pre_pre_raw_haz_WIRE_60.data, _raw_hazard_pre_pre_raw_haz_T_135
node _raw_hazard_pre_pre_raw_haz_T_136 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_61, 14, 14)
connect _raw_hazard_pre_pre_raw_haz_WIRE_60.garbage_bit, _raw_hazard_pre_pre_raw_haz_T_136
node _raw_hazard_pre_pre_raw_haz_T_137 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_61, 25, 15)
connect _raw_hazard_pre_pre_raw_haz_WIRE_60.garbage, _raw_hazard_pre_pre_raw_haz_T_137
node _raw_hazard_pre_pre_raw_haz_T_138 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_61, 28, 26)
wire _raw_hazard_pre_pre_raw_haz_WIRE_62 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_62, _raw_hazard_pre_pre_raw_haz_T_138
wire _raw_hazard_pre_pre_raw_haz_WIRE_63 : UInt<3>
connect _raw_hazard_pre_pre_raw_haz_WIRE_63, _raw_hazard_pre_pre_raw_haz_WIRE_62
connect _raw_hazard_pre_pre_raw_haz_WIRE_60.norm_cmd, _raw_hazard_pre_pre_raw_haz_WIRE_63
node _raw_hazard_pre_pre_raw_haz_T_139 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_61, 29, 29)
connect _raw_hazard_pre_pre_raw_haz_WIRE_60.read_full_acc_row, _raw_hazard_pre_pre_raw_haz_T_139
node _raw_hazard_pre_pre_raw_haz_T_140 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_61, 30, 30)
connect _raw_hazard_pre_pre_raw_haz_WIRE_60.accumulate, _raw_hazard_pre_pre_raw_haz_T_140
node _raw_hazard_pre_pre_raw_haz_T_141 = bits(_raw_hazard_pre_pre_raw_haz_WIRE_61, 31, 31)
connect _raw_hazard_pre_pre_raw_haz_WIRE_60.is_acc_addr, _raw_hazard_pre_pre_raw_haz_T_141
node _raw_hazard_pre_pre_raw_haz_T_142 = eq(mesh.io.tags_in_progress[15].addr.is_acc_addr, _raw_hazard_pre_pre_raw_haz_WIRE_60.is_acc_addr)
node _raw_hazard_pre_pre_raw_haz_T_143 = eq(mesh.io.tags_in_progress[15].addr.data, _raw_hazard_pre_pre_raw_haz_WIRE_60.data)
node raw_hazard_pre_pre_raw_haz_15 = and(_raw_hazard_pre_pre_raw_haz_T_142, _raw_hazard_pre_pre_raw_haz_T_143)
wire _raw_hazard_pre_mul_raw_haz_WIRE_120 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_121 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_121, rs1s[1]
node _raw_hazard_pre_mul_raw_haz_T_300 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_121, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_120.data, _raw_hazard_pre_mul_raw_haz_T_300
node _raw_hazard_pre_mul_raw_haz_T_301 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_121, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_120.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_301
node _raw_hazard_pre_mul_raw_haz_T_302 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_121, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_120.garbage, _raw_hazard_pre_mul_raw_haz_T_302
node _raw_hazard_pre_mul_raw_haz_T_303 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_121, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_122 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_122, _raw_hazard_pre_mul_raw_haz_T_303
wire _raw_hazard_pre_mul_raw_haz_WIRE_123 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_123, _raw_hazard_pre_mul_raw_haz_WIRE_122
connect _raw_hazard_pre_mul_raw_haz_WIRE_120.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_123
node _raw_hazard_pre_mul_raw_haz_T_304 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_121, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_120.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_304
node _raw_hazard_pre_mul_raw_haz_T_305 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_121, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_120.accumulate, _raw_hazard_pre_mul_raw_haz_T_305
node _raw_hazard_pre_mul_raw_haz_T_306 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_121, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_120.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_306
node _raw_hazard_pre_mul_raw_haz_T_307 = eq(mesh.io.tags_in_progress[15].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_120.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_308 = eq(mesh.io.tags_in_progress[15].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_120.data)
node _raw_hazard_pre_mul_raw_haz_T_309 = and(_raw_hazard_pre_mul_raw_haz_T_307, _raw_hazard_pre_mul_raw_haz_T_308)
wire _raw_hazard_pre_mul_raw_haz_WIRE_124 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_pre_mul_raw_haz_WIRE_125 : UInt<32>
connect _raw_hazard_pre_mul_raw_haz_WIRE_125, rs2s[1]
node _raw_hazard_pre_mul_raw_haz_T_310 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_125, 13, 0)
connect _raw_hazard_pre_mul_raw_haz_WIRE_124.data, _raw_hazard_pre_mul_raw_haz_T_310
node _raw_hazard_pre_mul_raw_haz_T_311 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_125, 14, 14)
connect _raw_hazard_pre_mul_raw_haz_WIRE_124.garbage_bit, _raw_hazard_pre_mul_raw_haz_T_311
node _raw_hazard_pre_mul_raw_haz_T_312 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_125, 25, 15)
connect _raw_hazard_pre_mul_raw_haz_WIRE_124.garbage, _raw_hazard_pre_mul_raw_haz_T_312
node _raw_hazard_pre_mul_raw_haz_T_313 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_125, 28, 26)
wire _raw_hazard_pre_mul_raw_haz_WIRE_126 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_126, _raw_hazard_pre_mul_raw_haz_T_313
wire _raw_hazard_pre_mul_raw_haz_WIRE_127 : UInt<3>
connect _raw_hazard_pre_mul_raw_haz_WIRE_127, _raw_hazard_pre_mul_raw_haz_WIRE_126
connect _raw_hazard_pre_mul_raw_haz_WIRE_124.norm_cmd, _raw_hazard_pre_mul_raw_haz_WIRE_127
node _raw_hazard_pre_mul_raw_haz_T_314 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_125, 29, 29)
connect _raw_hazard_pre_mul_raw_haz_WIRE_124.read_full_acc_row, _raw_hazard_pre_mul_raw_haz_T_314
node _raw_hazard_pre_mul_raw_haz_T_315 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_125, 30, 30)
connect _raw_hazard_pre_mul_raw_haz_WIRE_124.accumulate, _raw_hazard_pre_mul_raw_haz_T_315
node _raw_hazard_pre_mul_raw_haz_T_316 = bits(_raw_hazard_pre_mul_raw_haz_WIRE_125, 31, 31)
connect _raw_hazard_pre_mul_raw_haz_WIRE_124.is_acc_addr, _raw_hazard_pre_mul_raw_haz_T_316
node _raw_hazard_pre_mul_raw_haz_T_317 = eq(mesh.io.tags_in_progress[15].addr.is_acc_addr, _raw_hazard_pre_mul_raw_haz_WIRE_124.is_acc_addr)
node _raw_hazard_pre_mul_raw_haz_T_318 = eq(mesh.io.tags_in_progress[15].addr.data, _raw_hazard_pre_mul_raw_haz_WIRE_124.data)
node _raw_hazard_pre_mul_raw_haz_T_319 = and(_raw_hazard_pre_mul_raw_haz_T_317, _raw_hazard_pre_mul_raw_haz_T_318)
node raw_hazard_pre_mul_raw_haz_15 = or(_raw_hazard_pre_mul_raw_haz_T_309, _raw_hazard_pre_mul_raw_haz_T_319)
node _raw_hazard_pre_T_75 = eq(raw_hazard_pre_is_garbage_15, UInt<1>(0h0))
node _raw_hazard_pre_T_76 = or(raw_hazard_pre_pre_raw_haz_15, raw_hazard_pre_mul_raw_haz_15)
node _raw_hazard_pre_T_77 = and(_raw_hazard_pre_T_75, _raw_hazard_pre_T_76)
node _raw_hazard_pre_T_78 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_pre_T_79 = and(_raw_hazard_pre_T_77, _raw_hazard_pre_T_78)
node _raw_hazard_pre_T_80 = or(_raw_hazard_pre_T_4, _raw_hazard_pre_T_9)
node _raw_hazard_pre_T_81 = or(_raw_hazard_pre_T_80, _raw_hazard_pre_T_14)
node _raw_hazard_pre_T_82 = or(_raw_hazard_pre_T_81, _raw_hazard_pre_T_19)
node _raw_hazard_pre_T_83 = or(_raw_hazard_pre_T_82, _raw_hazard_pre_T_24)
node _raw_hazard_pre_T_84 = or(_raw_hazard_pre_T_83, _raw_hazard_pre_T_29)
node _raw_hazard_pre_T_85 = or(_raw_hazard_pre_T_84, _raw_hazard_pre_T_34)
node _raw_hazard_pre_T_86 = or(_raw_hazard_pre_T_85, _raw_hazard_pre_T_39)
node _raw_hazard_pre_T_87 = or(_raw_hazard_pre_T_86, _raw_hazard_pre_T_44)
node _raw_hazard_pre_T_88 = or(_raw_hazard_pre_T_87, _raw_hazard_pre_T_49)
node _raw_hazard_pre_T_89 = or(_raw_hazard_pre_T_88, _raw_hazard_pre_T_54)
node _raw_hazard_pre_T_90 = or(_raw_hazard_pre_T_89, _raw_hazard_pre_T_59)
node _raw_hazard_pre_T_91 = or(_raw_hazard_pre_T_90, _raw_hazard_pre_T_64)
node _raw_hazard_pre_T_92 = or(_raw_hazard_pre_T_91, _raw_hazard_pre_T_69)
node _raw_hazard_pre_T_93 = or(_raw_hazard_pre_T_92, _raw_hazard_pre_T_74)
node raw_hazard_pre = or(_raw_hazard_pre_T_93, _raw_hazard_pre_T_79)
node _raw_hazard_mulpre_is_garbage_T = and(mesh.io.tags_in_progress[0].addr.is_acc_addr, mesh.io.tags_in_progress[0].addr.accumulate)
node _raw_hazard_mulpre_is_garbage_T_1 = and(_raw_hazard_mulpre_is_garbage_T, mesh.io.tags_in_progress[0].addr.read_full_acc_row)
node _raw_hazard_mulpre_is_garbage_T_2 = andr(mesh.io.tags_in_progress[0].addr.data)
node _raw_hazard_mulpre_is_garbage_T_3 = and(_raw_hazard_mulpre_is_garbage_T_1, _raw_hazard_mulpre_is_garbage_T_2)
node _raw_hazard_mulpre_is_garbage_T_4 = bits(mesh.io.tags_in_progress[0].addr.garbage_bit, 0, 0)
node raw_hazard_mulpre_is_garbage = and(_raw_hazard_mulpre_is_garbage_T_3, _raw_hazard_mulpre_is_garbage_T_4)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_1 : UInt<32>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_1, rs1s[1]
node _raw_hazard_mulpre_pre_raw_haz_T = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_1, 13, 0)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE.data, _raw_hazard_mulpre_pre_raw_haz_T
node _raw_hazard_mulpre_pre_raw_haz_T_1 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_1, 14, 14)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE.garbage_bit, _raw_hazard_mulpre_pre_raw_haz_T_1
node _raw_hazard_mulpre_pre_raw_haz_T_2 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_1, 25, 15)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE.garbage, _raw_hazard_mulpre_pre_raw_haz_T_2
node _raw_hazard_mulpre_pre_raw_haz_T_3 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_1, 28, 26)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_2 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_2, _raw_hazard_mulpre_pre_raw_haz_T_3
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_3 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_3, _raw_hazard_mulpre_pre_raw_haz_WIRE_2
connect _raw_hazard_mulpre_pre_raw_haz_WIRE.norm_cmd, _raw_hazard_mulpre_pre_raw_haz_WIRE_3
node _raw_hazard_mulpre_pre_raw_haz_T_4 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_1, 29, 29)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE.read_full_acc_row, _raw_hazard_mulpre_pre_raw_haz_T_4
node _raw_hazard_mulpre_pre_raw_haz_T_5 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_1, 30, 30)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE.accumulate, _raw_hazard_mulpre_pre_raw_haz_T_5
node _raw_hazard_mulpre_pre_raw_haz_T_6 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_1, 31, 31)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_T_6
node _raw_hazard_mulpre_pre_raw_haz_T_7 = eq(mesh.io.tags_in_progress[0].addr.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_WIRE.is_acc_addr)
node _raw_hazard_mulpre_pre_raw_haz_T_8 = eq(mesh.io.tags_in_progress[0].addr.data, _raw_hazard_mulpre_pre_raw_haz_WIRE.data)
node raw_hazard_mulpre_pre_raw_haz = and(_raw_hazard_mulpre_pre_raw_haz_T_7, _raw_hazard_mulpre_pre_raw_haz_T_8)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_1 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_1, rs1s[2]
node _raw_hazard_mulpre_mul_raw_haz_T = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_1, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE.data, _raw_hazard_mulpre_mul_raw_haz_T
node _raw_hazard_mulpre_mul_raw_haz_T_1 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_1, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_1
node _raw_hazard_mulpre_mul_raw_haz_T_2 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_1, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE.garbage, _raw_hazard_mulpre_mul_raw_haz_T_2
node _raw_hazard_mulpre_mul_raw_haz_T_3 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_1, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_2 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_2, _raw_hazard_mulpre_mul_raw_haz_T_3
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_3 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_3, _raw_hazard_mulpre_mul_raw_haz_WIRE_2
connect _raw_hazard_mulpre_mul_raw_haz_WIRE.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_3
node _raw_hazard_mulpre_mul_raw_haz_T_4 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_1, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_4
node _raw_hazard_mulpre_mul_raw_haz_T_5 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_1, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_5
node _raw_hazard_mulpre_mul_raw_haz_T_6 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_1, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_6
node _raw_hazard_mulpre_mul_raw_haz_T_7 = eq(mesh.io.tags_in_progress[0].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_8 = eq(mesh.io.tags_in_progress[0].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE.data)
node _raw_hazard_mulpre_mul_raw_haz_T_9 = and(_raw_hazard_mulpre_mul_raw_haz_T_7, _raw_hazard_mulpre_mul_raw_haz_T_8)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_4 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_5 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_5, rs2s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_10 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_5, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_4.data, _raw_hazard_mulpre_mul_raw_haz_T_10
node _raw_hazard_mulpre_mul_raw_haz_T_11 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_5, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_4.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_11
node _raw_hazard_mulpre_mul_raw_haz_T_12 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_5, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_4.garbage, _raw_hazard_mulpre_mul_raw_haz_T_12
node _raw_hazard_mulpre_mul_raw_haz_T_13 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_5, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_6 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_6, _raw_hazard_mulpre_mul_raw_haz_T_13
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_7 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_7, _raw_hazard_mulpre_mul_raw_haz_WIRE_6
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_4.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_7
node _raw_hazard_mulpre_mul_raw_haz_T_14 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_5, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_4.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_14
node _raw_hazard_mulpre_mul_raw_haz_T_15 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_5, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_4.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_15
node _raw_hazard_mulpre_mul_raw_haz_T_16 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_5, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_4.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_16
node _raw_hazard_mulpre_mul_raw_haz_T_17 = eq(mesh.io.tags_in_progress[0].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_4.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_18 = eq(mesh.io.tags_in_progress[0].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_4.data)
node _raw_hazard_mulpre_mul_raw_haz_T_19 = and(_raw_hazard_mulpre_mul_raw_haz_T_17, _raw_hazard_mulpre_mul_raw_haz_T_18)
node raw_hazard_mulpre_mul_raw_haz = or(_raw_hazard_mulpre_mul_raw_haz_T_9, _raw_hazard_mulpre_mul_raw_haz_T_19)
node _raw_hazard_mulpre_T = eq(raw_hazard_mulpre_is_garbage, UInt<1>(0h0))
node _raw_hazard_mulpre_T_1 = or(raw_hazard_mulpre_mul_raw_haz, raw_hazard_mulpre_pre_raw_haz)
node _raw_hazard_mulpre_T_2 = and(_raw_hazard_mulpre_T, _raw_hazard_mulpre_T_1)
node _raw_hazard_mulpre_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_mulpre_T_4 = and(_raw_hazard_mulpre_T_2, _raw_hazard_mulpre_T_3)
node _raw_hazard_mulpre_is_garbage_T_5 = and(mesh.io.tags_in_progress[1].addr.is_acc_addr, mesh.io.tags_in_progress[1].addr.accumulate)
node _raw_hazard_mulpre_is_garbage_T_6 = and(_raw_hazard_mulpre_is_garbage_T_5, mesh.io.tags_in_progress[1].addr.read_full_acc_row)
node _raw_hazard_mulpre_is_garbage_T_7 = andr(mesh.io.tags_in_progress[1].addr.data)
node _raw_hazard_mulpre_is_garbage_T_8 = and(_raw_hazard_mulpre_is_garbage_T_6, _raw_hazard_mulpre_is_garbage_T_7)
node _raw_hazard_mulpre_is_garbage_T_9 = bits(mesh.io.tags_in_progress[1].addr.garbage_bit, 0, 0)
node raw_hazard_mulpre_is_garbage_1 = and(_raw_hazard_mulpre_is_garbage_T_8, _raw_hazard_mulpre_is_garbage_T_9)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_4 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_5 : UInt<32>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_5, rs1s[1]
node _raw_hazard_mulpre_pre_raw_haz_T_9 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_5, 13, 0)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_4.data, _raw_hazard_mulpre_pre_raw_haz_T_9
node _raw_hazard_mulpre_pre_raw_haz_T_10 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_5, 14, 14)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_4.garbage_bit, _raw_hazard_mulpre_pre_raw_haz_T_10
node _raw_hazard_mulpre_pre_raw_haz_T_11 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_5, 25, 15)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_4.garbage, _raw_hazard_mulpre_pre_raw_haz_T_11
node _raw_hazard_mulpre_pre_raw_haz_T_12 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_5, 28, 26)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_6 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_6, _raw_hazard_mulpre_pre_raw_haz_T_12
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_7 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_7, _raw_hazard_mulpre_pre_raw_haz_WIRE_6
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_4.norm_cmd, _raw_hazard_mulpre_pre_raw_haz_WIRE_7
node _raw_hazard_mulpre_pre_raw_haz_T_13 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_5, 29, 29)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_4.read_full_acc_row, _raw_hazard_mulpre_pre_raw_haz_T_13
node _raw_hazard_mulpre_pre_raw_haz_T_14 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_5, 30, 30)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_4.accumulate, _raw_hazard_mulpre_pre_raw_haz_T_14
node _raw_hazard_mulpre_pre_raw_haz_T_15 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_5, 31, 31)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_4.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_T_15
node _raw_hazard_mulpre_pre_raw_haz_T_16 = eq(mesh.io.tags_in_progress[1].addr.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_WIRE_4.is_acc_addr)
node _raw_hazard_mulpre_pre_raw_haz_T_17 = eq(mesh.io.tags_in_progress[1].addr.data, _raw_hazard_mulpre_pre_raw_haz_WIRE_4.data)
node raw_hazard_mulpre_pre_raw_haz_1 = and(_raw_hazard_mulpre_pre_raw_haz_T_16, _raw_hazard_mulpre_pre_raw_haz_T_17)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_8 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_9 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_9, rs1s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_20 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_9, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_8.data, _raw_hazard_mulpre_mul_raw_haz_T_20
node _raw_hazard_mulpre_mul_raw_haz_T_21 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_9, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_8.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_21
node _raw_hazard_mulpre_mul_raw_haz_T_22 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_9, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_8.garbage, _raw_hazard_mulpre_mul_raw_haz_T_22
node _raw_hazard_mulpre_mul_raw_haz_T_23 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_9, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_10 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_10, _raw_hazard_mulpre_mul_raw_haz_T_23
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_11 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_11, _raw_hazard_mulpre_mul_raw_haz_WIRE_10
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_8.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_11
node _raw_hazard_mulpre_mul_raw_haz_T_24 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_9, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_8.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_24
node _raw_hazard_mulpre_mul_raw_haz_T_25 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_9, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_8.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_25
node _raw_hazard_mulpre_mul_raw_haz_T_26 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_9, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_8.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_26
node _raw_hazard_mulpre_mul_raw_haz_T_27 = eq(mesh.io.tags_in_progress[1].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_8.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_28 = eq(mesh.io.tags_in_progress[1].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_8.data)
node _raw_hazard_mulpre_mul_raw_haz_T_29 = and(_raw_hazard_mulpre_mul_raw_haz_T_27, _raw_hazard_mulpre_mul_raw_haz_T_28)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_12 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_13 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_13, rs2s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_30 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_13, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_12.data, _raw_hazard_mulpre_mul_raw_haz_T_30
node _raw_hazard_mulpre_mul_raw_haz_T_31 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_13, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_12.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_31
node _raw_hazard_mulpre_mul_raw_haz_T_32 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_13, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_12.garbage, _raw_hazard_mulpre_mul_raw_haz_T_32
node _raw_hazard_mulpre_mul_raw_haz_T_33 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_13, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_14 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_14, _raw_hazard_mulpre_mul_raw_haz_T_33
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_15 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_15, _raw_hazard_mulpre_mul_raw_haz_WIRE_14
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_12.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_15
node _raw_hazard_mulpre_mul_raw_haz_T_34 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_13, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_12.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_34
node _raw_hazard_mulpre_mul_raw_haz_T_35 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_13, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_12.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_35
node _raw_hazard_mulpre_mul_raw_haz_T_36 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_13, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_12.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_36
node _raw_hazard_mulpre_mul_raw_haz_T_37 = eq(mesh.io.tags_in_progress[1].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_12.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_38 = eq(mesh.io.tags_in_progress[1].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_12.data)
node _raw_hazard_mulpre_mul_raw_haz_T_39 = and(_raw_hazard_mulpre_mul_raw_haz_T_37, _raw_hazard_mulpre_mul_raw_haz_T_38)
node raw_hazard_mulpre_mul_raw_haz_1 = or(_raw_hazard_mulpre_mul_raw_haz_T_29, _raw_hazard_mulpre_mul_raw_haz_T_39)
node _raw_hazard_mulpre_T_5 = eq(raw_hazard_mulpre_is_garbage_1, UInt<1>(0h0))
node _raw_hazard_mulpre_T_6 = or(raw_hazard_mulpre_mul_raw_haz_1, raw_hazard_mulpre_pre_raw_haz_1)
node _raw_hazard_mulpre_T_7 = and(_raw_hazard_mulpre_T_5, _raw_hazard_mulpre_T_6)
node _raw_hazard_mulpre_T_8 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_mulpre_T_9 = and(_raw_hazard_mulpre_T_7, _raw_hazard_mulpre_T_8)
node _raw_hazard_mulpre_is_garbage_T_10 = and(mesh.io.tags_in_progress[2].addr.is_acc_addr, mesh.io.tags_in_progress[2].addr.accumulate)
node _raw_hazard_mulpre_is_garbage_T_11 = and(_raw_hazard_mulpre_is_garbage_T_10, mesh.io.tags_in_progress[2].addr.read_full_acc_row)
node _raw_hazard_mulpre_is_garbage_T_12 = andr(mesh.io.tags_in_progress[2].addr.data)
node _raw_hazard_mulpre_is_garbage_T_13 = and(_raw_hazard_mulpre_is_garbage_T_11, _raw_hazard_mulpre_is_garbage_T_12)
node _raw_hazard_mulpre_is_garbage_T_14 = bits(mesh.io.tags_in_progress[2].addr.garbage_bit, 0, 0)
node raw_hazard_mulpre_is_garbage_2 = and(_raw_hazard_mulpre_is_garbage_T_13, _raw_hazard_mulpre_is_garbage_T_14)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_8 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_9 : UInt<32>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_9, rs1s[1]
node _raw_hazard_mulpre_pre_raw_haz_T_18 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_9, 13, 0)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_8.data, _raw_hazard_mulpre_pre_raw_haz_T_18
node _raw_hazard_mulpre_pre_raw_haz_T_19 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_9, 14, 14)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_8.garbage_bit, _raw_hazard_mulpre_pre_raw_haz_T_19
node _raw_hazard_mulpre_pre_raw_haz_T_20 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_9, 25, 15)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_8.garbage, _raw_hazard_mulpre_pre_raw_haz_T_20
node _raw_hazard_mulpre_pre_raw_haz_T_21 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_9, 28, 26)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_10 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_10, _raw_hazard_mulpre_pre_raw_haz_T_21
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_11 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_11, _raw_hazard_mulpre_pre_raw_haz_WIRE_10
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_8.norm_cmd, _raw_hazard_mulpre_pre_raw_haz_WIRE_11
node _raw_hazard_mulpre_pre_raw_haz_T_22 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_9, 29, 29)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_8.read_full_acc_row, _raw_hazard_mulpre_pre_raw_haz_T_22
node _raw_hazard_mulpre_pre_raw_haz_T_23 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_9, 30, 30)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_8.accumulate, _raw_hazard_mulpre_pre_raw_haz_T_23
node _raw_hazard_mulpre_pre_raw_haz_T_24 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_9, 31, 31)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_8.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_T_24
node _raw_hazard_mulpre_pre_raw_haz_T_25 = eq(mesh.io.tags_in_progress[2].addr.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_WIRE_8.is_acc_addr)
node _raw_hazard_mulpre_pre_raw_haz_T_26 = eq(mesh.io.tags_in_progress[2].addr.data, _raw_hazard_mulpre_pre_raw_haz_WIRE_8.data)
node raw_hazard_mulpre_pre_raw_haz_2 = and(_raw_hazard_mulpre_pre_raw_haz_T_25, _raw_hazard_mulpre_pre_raw_haz_T_26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_16 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_17 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_17, rs1s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_40 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_17, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_16.data, _raw_hazard_mulpre_mul_raw_haz_T_40
node _raw_hazard_mulpre_mul_raw_haz_T_41 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_17, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_16.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_41
node _raw_hazard_mulpre_mul_raw_haz_T_42 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_17, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_16.garbage, _raw_hazard_mulpre_mul_raw_haz_T_42
node _raw_hazard_mulpre_mul_raw_haz_T_43 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_17, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_18 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_18, _raw_hazard_mulpre_mul_raw_haz_T_43
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_19 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_19, _raw_hazard_mulpre_mul_raw_haz_WIRE_18
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_16.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_19
node _raw_hazard_mulpre_mul_raw_haz_T_44 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_17, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_16.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_44
node _raw_hazard_mulpre_mul_raw_haz_T_45 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_17, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_16.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_45
node _raw_hazard_mulpre_mul_raw_haz_T_46 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_17, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_16.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_46
node _raw_hazard_mulpre_mul_raw_haz_T_47 = eq(mesh.io.tags_in_progress[2].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_16.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_48 = eq(mesh.io.tags_in_progress[2].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_16.data)
node _raw_hazard_mulpre_mul_raw_haz_T_49 = and(_raw_hazard_mulpre_mul_raw_haz_T_47, _raw_hazard_mulpre_mul_raw_haz_T_48)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_20 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_21 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_21, rs2s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_50 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_21, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_20.data, _raw_hazard_mulpre_mul_raw_haz_T_50
node _raw_hazard_mulpre_mul_raw_haz_T_51 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_21, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_20.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_51
node _raw_hazard_mulpre_mul_raw_haz_T_52 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_21, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_20.garbage, _raw_hazard_mulpre_mul_raw_haz_T_52
node _raw_hazard_mulpre_mul_raw_haz_T_53 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_21, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_22 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_22, _raw_hazard_mulpre_mul_raw_haz_T_53
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_23 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_23, _raw_hazard_mulpre_mul_raw_haz_WIRE_22
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_20.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_23
node _raw_hazard_mulpre_mul_raw_haz_T_54 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_21, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_20.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_54
node _raw_hazard_mulpre_mul_raw_haz_T_55 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_21, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_20.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_55
node _raw_hazard_mulpre_mul_raw_haz_T_56 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_21, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_20.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_56
node _raw_hazard_mulpre_mul_raw_haz_T_57 = eq(mesh.io.tags_in_progress[2].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_20.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_58 = eq(mesh.io.tags_in_progress[2].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_20.data)
node _raw_hazard_mulpre_mul_raw_haz_T_59 = and(_raw_hazard_mulpre_mul_raw_haz_T_57, _raw_hazard_mulpre_mul_raw_haz_T_58)
node raw_hazard_mulpre_mul_raw_haz_2 = or(_raw_hazard_mulpre_mul_raw_haz_T_49, _raw_hazard_mulpre_mul_raw_haz_T_59)
node _raw_hazard_mulpre_T_10 = eq(raw_hazard_mulpre_is_garbage_2, UInt<1>(0h0))
node _raw_hazard_mulpre_T_11 = or(raw_hazard_mulpre_mul_raw_haz_2, raw_hazard_mulpre_pre_raw_haz_2)
node _raw_hazard_mulpre_T_12 = and(_raw_hazard_mulpre_T_10, _raw_hazard_mulpre_T_11)
node _raw_hazard_mulpre_T_13 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_mulpre_T_14 = and(_raw_hazard_mulpre_T_12, _raw_hazard_mulpre_T_13)
node _raw_hazard_mulpre_is_garbage_T_15 = and(mesh.io.tags_in_progress[3].addr.is_acc_addr, mesh.io.tags_in_progress[3].addr.accumulate)
node _raw_hazard_mulpre_is_garbage_T_16 = and(_raw_hazard_mulpre_is_garbage_T_15, mesh.io.tags_in_progress[3].addr.read_full_acc_row)
node _raw_hazard_mulpre_is_garbage_T_17 = andr(mesh.io.tags_in_progress[3].addr.data)
node _raw_hazard_mulpre_is_garbage_T_18 = and(_raw_hazard_mulpre_is_garbage_T_16, _raw_hazard_mulpre_is_garbage_T_17)
node _raw_hazard_mulpre_is_garbage_T_19 = bits(mesh.io.tags_in_progress[3].addr.garbage_bit, 0, 0)
node raw_hazard_mulpre_is_garbage_3 = and(_raw_hazard_mulpre_is_garbage_T_18, _raw_hazard_mulpre_is_garbage_T_19)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_12 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_13 : UInt<32>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_13, rs1s[1]
node _raw_hazard_mulpre_pre_raw_haz_T_27 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_13, 13, 0)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_12.data, _raw_hazard_mulpre_pre_raw_haz_T_27
node _raw_hazard_mulpre_pre_raw_haz_T_28 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_13, 14, 14)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_12.garbage_bit, _raw_hazard_mulpre_pre_raw_haz_T_28
node _raw_hazard_mulpre_pre_raw_haz_T_29 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_13, 25, 15)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_12.garbage, _raw_hazard_mulpre_pre_raw_haz_T_29
node _raw_hazard_mulpre_pre_raw_haz_T_30 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_13, 28, 26)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_14 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_14, _raw_hazard_mulpre_pre_raw_haz_T_30
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_15 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_15, _raw_hazard_mulpre_pre_raw_haz_WIRE_14
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_12.norm_cmd, _raw_hazard_mulpre_pre_raw_haz_WIRE_15
node _raw_hazard_mulpre_pre_raw_haz_T_31 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_13, 29, 29)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_12.read_full_acc_row, _raw_hazard_mulpre_pre_raw_haz_T_31
node _raw_hazard_mulpre_pre_raw_haz_T_32 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_13, 30, 30)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_12.accumulate, _raw_hazard_mulpre_pre_raw_haz_T_32
node _raw_hazard_mulpre_pre_raw_haz_T_33 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_13, 31, 31)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_12.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_T_33
node _raw_hazard_mulpre_pre_raw_haz_T_34 = eq(mesh.io.tags_in_progress[3].addr.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_WIRE_12.is_acc_addr)
node _raw_hazard_mulpre_pre_raw_haz_T_35 = eq(mesh.io.tags_in_progress[3].addr.data, _raw_hazard_mulpre_pre_raw_haz_WIRE_12.data)
node raw_hazard_mulpre_pre_raw_haz_3 = and(_raw_hazard_mulpre_pre_raw_haz_T_34, _raw_hazard_mulpre_pre_raw_haz_T_35)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_24 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_25 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_25, rs1s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_60 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_25, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_24.data, _raw_hazard_mulpre_mul_raw_haz_T_60
node _raw_hazard_mulpre_mul_raw_haz_T_61 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_25, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_24.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_61
node _raw_hazard_mulpre_mul_raw_haz_T_62 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_25, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_24.garbage, _raw_hazard_mulpre_mul_raw_haz_T_62
node _raw_hazard_mulpre_mul_raw_haz_T_63 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_25, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_26 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_26, _raw_hazard_mulpre_mul_raw_haz_T_63
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_27 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_27, _raw_hazard_mulpre_mul_raw_haz_WIRE_26
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_24.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_27
node _raw_hazard_mulpre_mul_raw_haz_T_64 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_25, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_24.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_64
node _raw_hazard_mulpre_mul_raw_haz_T_65 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_25, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_24.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_65
node _raw_hazard_mulpre_mul_raw_haz_T_66 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_25, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_24.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_66
node _raw_hazard_mulpre_mul_raw_haz_T_67 = eq(mesh.io.tags_in_progress[3].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_24.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_68 = eq(mesh.io.tags_in_progress[3].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_24.data)
node _raw_hazard_mulpre_mul_raw_haz_T_69 = and(_raw_hazard_mulpre_mul_raw_haz_T_67, _raw_hazard_mulpre_mul_raw_haz_T_68)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_28 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_29 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_29, rs2s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_70 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_29, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_28.data, _raw_hazard_mulpre_mul_raw_haz_T_70
node _raw_hazard_mulpre_mul_raw_haz_T_71 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_29, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_28.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_71
node _raw_hazard_mulpre_mul_raw_haz_T_72 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_29, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_28.garbage, _raw_hazard_mulpre_mul_raw_haz_T_72
node _raw_hazard_mulpre_mul_raw_haz_T_73 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_29, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_30 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_30, _raw_hazard_mulpre_mul_raw_haz_T_73
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_31 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_31, _raw_hazard_mulpre_mul_raw_haz_WIRE_30
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_28.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_31
node _raw_hazard_mulpre_mul_raw_haz_T_74 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_29, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_28.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_74
node _raw_hazard_mulpre_mul_raw_haz_T_75 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_29, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_28.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_75
node _raw_hazard_mulpre_mul_raw_haz_T_76 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_29, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_28.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_76
node _raw_hazard_mulpre_mul_raw_haz_T_77 = eq(mesh.io.tags_in_progress[3].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_28.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_78 = eq(mesh.io.tags_in_progress[3].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_28.data)
node _raw_hazard_mulpre_mul_raw_haz_T_79 = and(_raw_hazard_mulpre_mul_raw_haz_T_77, _raw_hazard_mulpre_mul_raw_haz_T_78)
node raw_hazard_mulpre_mul_raw_haz_3 = or(_raw_hazard_mulpre_mul_raw_haz_T_69, _raw_hazard_mulpre_mul_raw_haz_T_79)
node _raw_hazard_mulpre_T_15 = eq(raw_hazard_mulpre_is_garbage_3, UInt<1>(0h0))
node _raw_hazard_mulpre_T_16 = or(raw_hazard_mulpre_mul_raw_haz_3, raw_hazard_mulpre_pre_raw_haz_3)
node _raw_hazard_mulpre_T_17 = and(_raw_hazard_mulpre_T_15, _raw_hazard_mulpre_T_16)
node _raw_hazard_mulpre_T_18 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_mulpre_T_19 = and(_raw_hazard_mulpre_T_17, _raw_hazard_mulpre_T_18)
node _raw_hazard_mulpre_is_garbage_T_20 = and(mesh.io.tags_in_progress[4].addr.is_acc_addr, mesh.io.tags_in_progress[4].addr.accumulate)
node _raw_hazard_mulpre_is_garbage_T_21 = and(_raw_hazard_mulpre_is_garbage_T_20, mesh.io.tags_in_progress[4].addr.read_full_acc_row)
node _raw_hazard_mulpre_is_garbage_T_22 = andr(mesh.io.tags_in_progress[4].addr.data)
node _raw_hazard_mulpre_is_garbage_T_23 = and(_raw_hazard_mulpre_is_garbage_T_21, _raw_hazard_mulpre_is_garbage_T_22)
node _raw_hazard_mulpre_is_garbage_T_24 = bits(mesh.io.tags_in_progress[4].addr.garbage_bit, 0, 0)
node raw_hazard_mulpre_is_garbage_4 = and(_raw_hazard_mulpre_is_garbage_T_23, _raw_hazard_mulpre_is_garbage_T_24)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_16 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_17 : UInt<32>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_17, rs1s[1]
node _raw_hazard_mulpre_pre_raw_haz_T_36 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_17, 13, 0)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_16.data, _raw_hazard_mulpre_pre_raw_haz_T_36
node _raw_hazard_mulpre_pre_raw_haz_T_37 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_17, 14, 14)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_16.garbage_bit, _raw_hazard_mulpre_pre_raw_haz_T_37
node _raw_hazard_mulpre_pre_raw_haz_T_38 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_17, 25, 15)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_16.garbage, _raw_hazard_mulpre_pre_raw_haz_T_38
node _raw_hazard_mulpre_pre_raw_haz_T_39 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_17, 28, 26)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_18 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_18, _raw_hazard_mulpre_pre_raw_haz_T_39
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_19 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_19, _raw_hazard_mulpre_pre_raw_haz_WIRE_18
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_16.norm_cmd, _raw_hazard_mulpre_pre_raw_haz_WIRE_19
node _raw_hazard_mulpre_pre_raw_haz_T_40 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_17, 29, 29)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_16.read_full_acc_row, _raw_hazard_mulpre_pre_raw_haz_T_40
node _raw_hazard_mulpre_pre_raw_haz_T_41 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_17, 30, 30)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_16.accumulate, _raw_hazard_mulpre_pre_raw_haz_T_41
node _raw_hazard_mulpre_pre_raw_haz_T_42 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_17, 31, 31)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_16.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_T_42
node _raw_hazard_mulpre_pre_raw_haz_T_43 = eq(mesh.io.tags_in_progress[4].addr.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_WIRE_16.is_acc_addr)
node _raw_hazard_mulpre_pre_raw_haz_T_44 = eq(mesh.io.tags_in_progress[4].addr.data, _raw_hazard_mulpre_pre_raw_haz_WIRE_16.data)
node raw_hazard_mulpre_pre_raw_haz_4 = and(_raw_hazard_mulpre_pre_raw_haz_T_43, _raw_hazard_mulpre_pre_raw_haz_T_44)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_32 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_33 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_33, rs1s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_80 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_33, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_32.data, _raw_hazard_mulpre_mul_raw_haz_T_80
node _raw_hazard_mulpre_mul_raw_haz_T_81 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_33, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_32.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_81
node _raw_hazard_mulpre_mul_raw_haz_T_82 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_33, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_32.garbage, _raw_hazard_mulpre_mul_raw_haz_T_82
node _raw_hazard_mulpre_mul_raw_haz_T_83 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_33, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_34 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_34, _raw_hazard_mulpre_mul_raw_haz_T_83
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_35 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_35, _raw_hazard_mulpre_mul_raw_haz_WIRE_34
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_32.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_35
node _raw_hazard_mulpre_mul_raw_haz_T_84 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_33, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_32.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_84
node _raw_hazard_mulpre_mul_raw_haz_T_85 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_33, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_32.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_85
node _raw_hazard_mulpre_mul_raw_haz_T_86 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_33, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_32.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_86
node _raw_hazard_mulpre_mul_raw_haz_T_87 = eq(mesh.io.tags_in_progress[4].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_32.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_88 = eq(mesh.io.tags_in_progress[4].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_32.data)
node _raw_hazard_mulpre_mul_raw_haz_T_89 = and(_raw_hazard_mulpre_mul_raw_haz_T_87, _raw_hazard_mulpre_mul_raw_haz_T_88)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_36 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_37 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_37, rs2s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_90 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_37, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_36.data, _raw_hazard_mulpre_mul_raw_haz_T_90
node _raw_hazard_mulpre_mul_raw_haz_T_91 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_37, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_36.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_91
node _raw_hazard_mulpre_mul_raw_haz_T_92 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_37, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_36.garbage, _raw_hazard_mulpre_mul_raw_haz_T_92
node _raw_hazard_mulpre_mul_raw_haz_T_93 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_37, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_38 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_38, _raw_hazard_mulpre_mul_raw_haz_T_93
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_39 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_39, _raw_hazard_mulpre_mul_raw_haz_WIRE_38
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_36.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_39
node _raw_hazard_mulpre_mul_raw_haz_T_94 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_37, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_36.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_94
node _raw_hazard_mulpre_mul_raw_haz_T_95 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_37, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_36.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_95
node _raw_hazard_mulpre_mul_raw_haz_T_96 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_37, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_36.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_96
node _raw_hazard_mulpre_mul_raw_haz_T_97 = eq(mesh.io.tags_in_progress[4].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_36.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_98 = eq(mesh.io.tags_in_progress[4].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_36.data)
node _raw_hazard_mulpre_mul_raw_haz_T_99 = and(_raw_hazard_mulpre_mul_raw_haz_T_97, _raw_hazard_mulpre_mul_raw_haz_T_98)
node raw_hazard_mulpre_mul_raw_haz_4 = or(_raw_hazard_mulpre_mul_raw_haz_T_89, _raw_hazard_mulpre_mul_raw_haz_T_99)
node _raw_hazard_mulpre_T_20 = eq(raw_hazard_mulpre_is_garbage_4, UInt<1>(0h0))
node _raw_hazard_mulpre_T_21 = or(raw_hazard_mulpre_mul_raw_haz_4, raw_hazard_mulpre_pre_raw_haz_4)
node _raw_hazard_mulpre_T_22 = and(_raw_hazard_mulpre_T_20, _raw_hazard_mulpre_T_21)
node _raw_hazard_mulpre_T_23 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_mulpre_T_24 = and(_raw_hazard_mulpre_T_22, _raw_hazard_mulpre_T_23)
node _raw_hazard_mulpre_is_garbage_T_25 = and(mesh.io.tags_in_progress[5].addr.is_acc_addr, mesh.io.tags_in_progress[5].addr.accumulate)
node _raw_hazard_mulpre_is_garbage_T_26 = and(_raw_hazard_mulpre_is_garbage_T_25, mesh.io.tags_in_progress[5].addr.read_full_acc_row)
node _raw_hazard_mulpre_is_garbage_T_27 = andr(mesh.io.tags_in_progress[5].addr.data)
node _raw_hazard_mulpre_is_garbage_T_28 = and(_raw_hazard_mulpre_is_garbage_T_26, _raw_hazard_mulpre_is_garbage_T_27)
node _raw_hazard_mulpre_is_garbage_T_29 = bits(mesh.io.tags_in_progress[5].addr.garbage_bit, 0, 0)
node raw_hazard_mulpre_is_garbage_5 = and(_raw_hazard_mulpre_is_garbage_T_28, _raw_hazard_mulpre_is_garbage_T_29)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_20 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_21 : UInt<32>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_21, rs1s[1]
node _raw_hazard_mulpre_pre_raw_haz_T_45 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_21, 13, 0)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_20.data, _raw_hazard_mulpre_pre_raw_haz_T_45
node _raw_hazard_mulpre_pre_raw_haz_T_46 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_21, 14, 14)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_20.garbage_bit, _raw_hazard_mulpre_pre_raw_haz_T_46
node _raw_hazard_mulpre_pre_raw_haz_T_47 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_21, 25, 15)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_20.garbage, _raw_hazard_mulpre_pre_raw_haz_T_47
node _raw_hazard_mulpre_pre_raw_haz_T_48 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_21, 28, 26)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_22 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_22, _raw_hazard_mulpre_pre_raw_haz_T_48
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_23 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_23, _raw_hazard_mulpre_pre_raw_haz_WIRE_22
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_20.norm_cmd, _raw_hazard_mulpre_pre_raw_haz_WIRE_23
node _raw_hazard_mulpre_pre_raw_haz_T_49 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_21, 29, 29)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_20.read_full_acc_row, _raw_hazard_mulpre_pre_raw_haz_T_49
node _raw_hazard_mulpre_pre_raw_haz_T_50 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_21, 30, 30)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_20.accumulate, _raw_hazard_mulpre_pre_raw_haz_T_50
node _raw_hazard_mulpre_pre_raw_haz_T_51 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_21, 31, 31)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_20.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_T_51
node _raw_hazard_mulpre_pre_raw_haz_T_52 = eq(mesh.io.tags_in_progress[5].addr.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_WIRE_20.is_acc_addr)
node _raw_hazard_mulpre_pre_raw_haz_T_53 = eq(mesh.io.tags_in_progress[5].addr.data, _raw_hazard_mulpre_pre_raw_haz_WIRE_20.data)
node raw_hazard_mulpre_pre_raw_haz_5 = and(_raw_hazard_mulpre_pre_raw_haz_T_52, _raw_hazard_mulpre_pre_raw_haz_T_53)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_40 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_41 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_41, rs1s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_100 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_41, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_40.data, _raw_hazard_mulpre_mul_raw_haz_T_100
node _raw_hazard_mulpre_mul_raw_haz_T_101 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_41, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_40.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_101
node _raw_hazard_mulpre_mul_raw_haz_T_102 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_41, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_40.garbage, _raw_hazard_mulpre_mul_raw_haz_T_102
node _raw_hazard_mulpre_mul_raw_haz_T_103 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_41, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_42 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_42, _raw_hazard_mulpre_mul_raw_haz_T_103
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_43 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_43, _raw_hazard_mulpre_mul_raw_haz_WIRE_42
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_40.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_43
node _raw_hazard_mulpre_mul_raw_haz_T_104 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_41, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_40.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_104
node _raw_hazard_mulpre_mul_raw_haz_T_105 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_41, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_40.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_105
node _raw_hazard_mulpre_mul_raw_haz_T_106 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_41, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_40.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_106
node _raw_hazard_mulpre_mul_raw_haz_T_107 = eq(mesh.io.tags_in_progress[5].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_40.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_108 = eq(mesh.io.tags_in_progress[5].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_40.data)
node _raw_hazard_mulpre_mul_raw_haz_T_109 = and(_raw_hazard_mulpre_mul_raw_haz_T_107, _raw_hazard_mulpre_mul_raw_haz_T_108)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_44 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_45 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_45, rs2s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_110 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_45, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_44.data, _raw_hazard_mulpre_mul_raw_haz_T_110
node _raw_hazard_mulpre_mul_raw_haz_T_111 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_45, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_44.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_111
node _raw_hazard_mulpre_mul_raw_haz_T_112 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_45, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_44.garbage, _raw_hazard_mulpre_mul_raw_haz_T_112
node _raw_hazard_mulpre_mul_raw_haz_T_113 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_45, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_46 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_46, _raw_hazard_mulpre_mul_raw_haz_T_113
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_47 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_47, _raw_hazard_mulpre_mul_raw_haz_WIRE_46
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_44.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_47
node _raw_hazard_mulpre_mul_raw_haz_T_114 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_45, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_44.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_114
node _raw_hazard_mulpre_mul_raw_haz_T_115 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_45, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_44.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_115
node _raw_hazard_mulpre_mul_raw_haz_T_116 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_45, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_44.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_116
node _raw_hazard_mulpre_mul_raw_haz_T_117 = eq(mesh.io.tags_in_progress[5].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_44.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_118 = eq(mesh.io.tags_in_progress[5].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_44.data)
node _raw_hazard_mulpre_mul_raw_haz_T_119 = and(_raw_hazard_mulpre_mul_raw_haz_T_117, _raw_hazard_mulpre_mul_raw_haz_T_118)
node raw_hazard_mulpre_mul_raw_haz_5 = or(_raw_hazard_mulpre_mul_raw_haz_T_109, _raw_hazard_mulpre_mul_raw_haz_T_119)
node _raw_hazard_mulpre_T_25 = eq(raw_hazard_mulpre_is_garbage_5, UInt<1>(0h0))
node _raw_hazard_mulpre_T_26 = or(raw_hazard_mulpre_mul_raw_haz_5, raw_hazard_mulpre_pre_raw_haz_5)
node _raw_hazard_mulpre_T_27 = and(_raw_hazard_mulpre_T_25, _raw_hazard_mulpre_T_26)
node _raw_hazard_mulpre_T_28 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_mulpre_T_29 = and(_raw_hazard_mulpre_T_27, _raw_hazard_mulpre_T_28)
node _raw_hazard_mulpre_is_garbage_T_30 = and(mesh.io.tags_in_progress[6].addr.is_acc_addr, mesh.io.tags_in_progress[6].addr.accumulate)
node _raw_hazard_mulpre_is_garbage_T_31 = and(_raw_hazard_mulpre_is_garbage_T_30, mesh.io.tags_in_progress[6].addr.read_full_acc_row)
node _raw_hazard_mulpre_is_garbage_T_32 = andr(mesh.io.tags_in_progress[6].addr.data)
node _raw_hazard_mulpre_is_garbage_T_33 = and(_raw_hazard_mulpre_is_garbage_T_31, _raw_hazard_mulpre_is_garbage_T_32)
node _raw_hazard_mulpre_is_garbage_T_34 = bits(mesh.io.tags_in_progress[6].addr.garbage_bit, 0, 0)
node raw_hazard_mulpre_is_garbage_6 = and(_raw_hazard_mulpre_is_garbage_T_33, _raw_hazard_mulpre_is_garbage_T_34)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_24 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_25 : UInt<32>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_25, rs1s[1]
node _raw_hazard_mulpre_pre_raw_haz_T_54 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_25, 13, 0)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_24.data, _raw_hazard_mulpre_pre_raw_haz_T_54
node _raw_hazard_mulpre_pre_raw_haz_T_55 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_25, 14, 14)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_24.garbage_bit, _raw_hazard_mulpre_pre_raw_haz_T_55
node _raw_hazard_mulpre_pre_raw_haz_T_56 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_25, 25, 15)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_24.garbage, _raw_hazard_mulpre_pre_raw_haz_T_56
node _raw_hazard_mulpre_pre_raw_haz_T_57 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_25, 28, 26)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_26 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_26, _raw_hazard_mulpre_pre_raw_haz_T_57
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_27 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_27, _raw_hazard_mulpre_pre_raw_haz_WIRE_26
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_24.norm_cmd, _raw_hazard_mulpre_pre_raw_haz_WIRE_27
node _raw_hazard_mulpre_pre_raw_haz_T_58 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_25, 29, 29)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_24.read_full_acc_row, _raw_hazard_mulpre_pre_raw_haz_T_58
node _raw_hazard_mulpre_pre_raw_haz_T_59 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_25, 30, 30)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_24.accumulate, _raw_hazard_mulpre_pre_raw_haz_T_59
node _raw_hazard_mulpre_pre_raw_haz_T_60 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_25, 31, 31)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_24.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_T_60
node _raw_hazard_mulpre_pre_raw_haz_T_61 = eq(mesh.io.tags_in_progress[6].addr.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_WIRE_24.is_acc_addr)
node _raw_hazard_mulpre_pre_raw_haz_T_62 = eq(mesh.io.tags_in_progress[6].addr.data, _raw_hazard_mulpre_pre_raw_haz_WIRE_24.data)
node raw_hazard_mulpre_pre_raw_haz_6 = and(_raw_hazard_mulpre_pre_raw_haz_T_61, _raw_hazard_mulpre_pre_raw_haz_T_62)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_48 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_49 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_49, rs1s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_120 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_49, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_48.data, _raw_hazard_mulpre_mul_raw_haz_T_120
node _raw_hazard_mulpre_mul_raw_haz_T_121 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_49, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_48.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_121
node _raw_hazard_mulpre_mul_raw_haz_T_122 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_49, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_48.garbage, _raw_hazard_mulpre_mul_raw_haz_T_122
node _raw_hazard_mulpre_mul_raw_haz_T_123 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_49, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_50 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_50, _raw_hazard_mulpre_mul_raw_haz_T_123
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_51 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_51, _raw_hazard_mulpre_mul_raw_haz_WIRE_50
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_48.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_51
node _raw_hazard_mulpre_mul_raw_haz_T_124 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_49, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_48.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_124
node _raw_hazard_mulpre_mul_raw_haz_T_125 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_49, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_48.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_125
node _raw_hazard_mulpre_mul_raw_haz_T_126 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_49, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_48.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_126
node _raw_hazard_mulpre_mul_raw_haz_T_127 = eq(mesh.io.tags_in_progress[6].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_48.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_128 = eq(mesh.io.tags_in_progress[6].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_48.data)
node _raw_hazard_mulpre_mul_raw_haz_T_129 = and(_raw_hazard_mulpre_mul_raw_haz_T_127, _raw_hazard_mulpre_mul_raw_haz_T_128)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_52 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_53 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_53, rs2s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_130 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_53, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_52.data, _raw_hazard_mulpre_mul_raw_haz_T_130
node _raw_hazard_mulpre_mul_raw_haz_T_131 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_53, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_52.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_131
node _raw_hazard_mulpre_mul_raw_haz_T_132 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_53, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_52.garbage, _raw_hazard_mulpre_mul_raw_haz_T_132
node _raw_hazard_mulpre_mul_raw_haz_T_133 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_53, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_54 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_54, _raw_hazard_mulpre_mul_raw_haz_T_133
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_55 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_55, _raw_hazard_mulpre_mul_raw_haz_WIRE_54
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_52.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_55
node _raw_hazard_mulpre_mul_raw_haz_T_134 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_53, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_52.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_134
node _raw_hazard_mulpre_mul_raw_haz_T_135 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_53, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_52.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_135
node _raw_hazard_mulpre_mul_raw_haz_T_136 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_53, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_52.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_136
node _raw_hazard_mulpre_mul_raw_haz_T_137 = eq(mesh.io.tags_in_progress[6].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_52.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_138 = eq(mesh.io.tags_in_progress[6].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_52.data)
node _raw_hazard_mulpre_mul_raw_haz_T_139 = and(_raw_hazard_mulpre_mul_raw_haz_T_137, _raw_hazard_mulpre_mul_raw_haz_T_138)
node raw_hazard_mulpre_mul_raw_haz_6 = or(_raw_hazard_mulpre_mul_raw_haz_T_129, _raw_hazard_mulpre_mul_raw_haz_T_139)
node _raw_hazard_mulpre_T_30 = eq(raw_hazard_mulpre_is_garbage_6, UInt<1>(0h0))
node _raw_hazard_mulpre_T_31 = or(raw_hazard_mulpre_mul_raw_haz_6, raw_hazard_mulpre_pre_raw_haz_6)
node _raw_hazard_mulpre_T_32 = and(_raw_hazard_mulpre_T_30, _raw_hazard_mulpre_T_31)
node _raw_hazard_mulpre_T_33 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_mulpre_T_34 = and(_raw_hazard_mulpre_T_32, _raw_hazard_mulpre_T_33)
node _raw_hazard_mulpre_is_garbage_T_35 = and(mesh.io.tags_in_progress[7].addr.is_acc_addr, mesh.io.tags_in_progress[7].addr.accumulate)
node _raw_hazard_mulpre_is_garbage_T_36 = and(_raw_hazard_mulpre_is_garbage_T_35, mesh.io.tags_in_progress[7].addr.read_full_acc_row)
node _raw_hazard_mulpre_is_garbage_T_37 = andr(mesh.io.tags_in_progress[7].addr.data)
node _raw_hazard_mulpre_is_garbage_T_38 = and(_raw_hazard_mulpre_is_garbage_T_36, _raw_hazard_mulpre_is_garbage_T_37)
node _raw_hazard_mulpre_is_garbage_T_39 = bits(mesh.io.tags_in_progress[7].addr.garbage_bit, 0, 0)
node raw_hazard_mulpre_is_garbage_7 = and(_raw_hazard_mulpre_is_garbage_T_38, _raw_hazard_mulpre_is_garbage_T_39)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_28 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_29 : UInt<32>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_29, rs1s[1]
node _raw_hazard_mulpre_pre_raw_haz_T_63 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_29, 13, 0)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_28.data, _raw_hazard_mulpre_pre_raw_haz_T_63
node _raw_hazard_mulpre_pre_raw_haz_T_64 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_29, 14, 14)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_28.garbage_bit, _raw_hazard_mulpre_pre_raw_haz_T_64
node _raw_hazard_mulpre_pre_raw_haz_T_65 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_29, 25, 15)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_28.garbage, _raw_hazard_mulpre_pre_raw_haz_T_65
node _raw_hazard_mulpre_pre_raw_haz_T_66 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_29, 28, 26)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_30 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_30, _raw_hazard_mulpre_pre_raw_haz_T_66
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_31 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_31, _raw_hazard_mulpre_pre_raw_haz_WIRE_30
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_28.norm_cmd, _raw_hazard_mulpre_pre_raw_haz_WIRE_31
node _raw_hazard_mulpre_pre_raw_haz_T_67 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_29, 29, 29)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_28.read_full_acc_row, _raw_hazard_mulpre_pre_raw_haz_T_67
node _raw_hazard_mulpre_pre_raw_haz_T_68 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_29, 30, 30)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_28.accumulate, _raw_hazard_mulpre_pre_raw_haz_T_68
node _raw_hazard_mulpre_pre_raw_haz_T_69 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_29, 31, 31)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_28.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_T_69
node _raw_hazard_mulpre_pre_raw_haz_T_70 = eq(mesh.io.tags_in_progress[7].addr.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_WIRE_28.is_acc_addr)
node _raw_hazard_mulpre_pre_raw_haz_T_71 = eq(mesh.io.tags_in_progress[7].addr.data, _raw_hazard_mulpre_pre_raw_haz_WIRE_28.data)
node raw_hazard_mulpre_pre_raw_haz_7 = and(_raw_hazard_mulpre_pre_raw_haz_T_70, _raw_hazard_mulpre_pre_raw_haz_T_71)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_56 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_57 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_57, rs1s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_140 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_57, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_56.data, _raw_hazard_mulpre_mul_raw_haz_T_140
node _raw_hazard_mulpre_mul_raw_haz_T_141 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_57, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_56.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_141
node _raw_hazard_mulpre_mul_raw_haz_T_142 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_57, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_56.garbage, _raw_hazard_mulpre_mul_raw_haz_T_142
node _raw_hazard_mulpre_mul_raw_haz_T_143 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_57, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_58 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_58, _raw_hazard_mulpre_mul_raw_haz_T_143
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_59 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_59, _raw_hazard_mulpre_mul_raw_haz_WIRE_58
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_56.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_59
node _raw_hazard_mulpre_mul_raw_haz_T_144 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_57, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_56.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_144
node _raw_hazard_mulpre_mul_raw_haz_T_145 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_57, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_56.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_145
node _raw_hazard_mulpre_mul_raw_haz_T_146 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_57, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_56.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_146
node _raw_hazard_mulpre_mul_raw_haz_T_147 = eq(mesh.io.tags_in_progress[7].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_56.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_148 = eq(mesh.io.tags_in_progress[7].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_56.data)
node _raw_hazard_mulpre_mul_raw_haz_T_149 = and(_raw_hazard_mulpre_mul_raw_haz_T_147, _raw_hazard_mulpre_mul_raw_haz_T_148)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_60 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_61 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_61, rs2s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_150 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_61, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_60.data, _raw_hazard_mulpre_mul_raw_haz_T_150
node _raw_hazard_mulpre_mul_raw_haz_T_151 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_61, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_60.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_151
node _raw_hazard_mulpre_mul_raw_haz_T_152 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_61, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_60.garbage, _raw_hazard_mulpre_mul_raw_haz_T_152
node _raw_hazard_mulpre_mul_raw_haz_T_153 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_61, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_62 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_62, _raw_hazard_mulpre_mul_raw_haz_T_153
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_63 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_63, _raw_hazard_mulpre_mul_raw_haz_WIRE_62
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_60.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_63
node _raw_hazard_mulpre_mul_raw_haz_T_154 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_61, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_60.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_154
node _raw_hazard_mulpre_mul_raw_haz_T_155 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_61, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_60.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_155
node _raw_hazard_mulpre_mul_raw_haz_T_156 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_61, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_60.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_156
node _raw_hazard_mulpre_mul_raw_haz_T_157 = eq(mesh.io.tags_in_progress[7].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_60.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_158 = eq(mesh.io.tags_in_progress[7].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_60.data)
node _raw_hazard_mulpre_mul_raw_haz_T_159 = and(_raw_hazard_mulpre_mul_raw_haz_T_157, _raw_hazard_mulpre_mul_raw_haz_T_158)
node raw_hazard_mulpre_mul_raw_haz_7 = or(_raw_hazard_mulpre_mul_raw_haz_T_149, _raw_hazard_mulpre_mul_raw_haz_T_159)
node _raw_hazard_mulpre_T_35 = eq(raw_hazard_mulpre_is_garbage_7, UInt<1>(0h0))
node _raw_hazard_mulpre_T_36 = or(raw_hazard_mulpre_mul_raw_haz_7, raw_hazard_mulpre_pre_raw_haz_7)
node _raw_hazard_mulpre_T_37 = and(_raw_hazard_mulpre_T_35, _raw_hazard_mulpre_T_36)
node _raw_hazard_mulpre_T_38 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_mulpre_T_39 = and(_raw_hazard_mulpre_T_37, _raw_hazard_mulpre_T_38)
node _raw_hazard_mulpre_is_garbage_T_40 = and(mesh.io.tags_in_progress[8].addr.is_acc_addr, mesh.io.tags_in_progress[8].addr.accumulate)
node _raw_hazard_mulpre_is_garbage_T_41 = and(_raw_hazard_mulpre_is_garbage_T_40, mesh.io.tags_in_progress[8].addr.read_full_acc_row)
node _raw_hazard_mulpre_is_garbage_T_42 = andr(mesh.io.tags_in_progress[8].addr.data)
node _raw_hazard_mulpre_is_garbage_T_43 = and(_raw_hazard_mulpre_is_garbage_T_41, _raw_hazard_mulpre_is_garbage_T_42)
node _raw_hazard_mulpre_is_garbage_T_44 = bits(mesh.io.tags_in_progress[8].addr.garbage_bit, 0, 0)
node raw_hazard_mulpre_is_garbage_8 = and(_raw_hazard_mulpre_is_garbage_T_43, _raw_hazard_mulpre_is_garbage_T_44)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_32 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_33 : UInt<32>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_33, rs1s[1]
node _raw_hazard_mulpre_pre_raw_haz_T_72 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_33, 13, 0)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_32.data, _raw_hazard_mulpre_pre_raw_haz_T_72
node _raw_hazard_mulpre_pre_raw_haz_T_73 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_33, 14, 14)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_32.garbage_bit, _raw_hazard_mulpre_pre_raw_haz_T_73
node _raw_hazard_mulpre_pre_raw_haz_T_74 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_33, 25, 15)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_32.garbage, _raw_hazard_mulpre_pre_raw_haz_T_74
node _raw_hazard_mulpre_pre_raw_haz_T_75 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_33, 28, 26)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_34 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_34, _raw_hazard_mulpre_pre_raw_haz_T_75
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_35 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_35, _raw_hazard_mulpre_pre_raw_haz_WIRE_34
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_32.norm_cmd, _raw_hazard_mulpre_pre_raw_haz_WIRE_35
node _raw_hazard_mulpre_pre_raw_haz_T_76 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_33, 29, 29)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_32.read_full_acc_row, _raw_hazard_mulpre_pre_raw_haz_T_76
node _raw_hazard_mulpre_pre_raw_haz_T_77 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_33, 30, 30)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_32.accumulate, _raw_hazard_mulpre_pre_raw_haz_T_77
node _raw_hazard_mulpre_pre_raw_haz_T_78 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_33, 31, 31)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_32.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_T_78
node _raw_hazard_mulpre_pre_raw_haz_T_79 = eq(mesh.io.tags_in_progress[8].addr.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_WIRE_32.is_acc_addr)
node _raw_hazard_mulpre_pre_raw_haz_T_80 = eq(mesh.io.tags_in_progress[8].addr.data, _raw_hazard_mulpre_pre_raw_haz_WIRE_32.data)
node raw_hazard_mulpre_pre_raw_haz_8 = and(_raw_hazard_mulpre_pre_raw_haz_T_79, _raw_hazard_mulpre_pre_raw_haz_T_80)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_64 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_65 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_65, rs1s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_160 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_65, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_64.data, _raw_hazard_mulpre_mul_raw_haz_T_160
node _raw_hazard_mulpre_mul_raw_haz_T_161 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_65, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_64.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_161
node _raw_hazard_mulpre_mul_raw_haz_T_162 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_65, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_64.garbage, _raw_hazard_mulpre_mul_raw_haz_T_162
node _raw_hazard_mulpre_mul_raw_haz_T_163 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_65, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_66 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_66, _raw_hazard_mulpre_mul_raw_haz_T_163
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_67 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_67, _raw_hazard_mulpre_mul_raw_haz_WIRE_66
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_64.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_67
node _raw_hazard_mulpre_mul_raw_haz_T_164 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_65, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_64.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_164
node _raw_hazard_mulpre_mul_raw_haz_T_165 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_65, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_64.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_165
node _raw_hazard_mulpre_mul_raw_haz_T_166 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_65, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_64.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_166
node _raw_hazard_mulpre_mul_raw_haz_T_167 = eq(mesh.io.tags_in_progress[8].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_64.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_168 = eq(mesh.io.tags_in_progress[8].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_64.data)
node _raw_hazard_mulpre_mul_raw_haz_T_169 = and(_raw_hazard_mulpre_mul_raw_haz_T_167, _raw_hazard_mulpre_mul_raw_haz_T_168)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_68 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_69 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_69, rs2s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_170 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_69, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_68.data, _raw_hazard_mulpre_mul_raw_haz_T_170
node _raw_hazard_mulpre_mul_raw_haz_T_171 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_69, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_68.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_171
node _raw_hazard_mulpre_mul_raw_haz_T_172 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_69, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_68.garbage, _raw_hazard_mulpre_mul_raw_haz_T_172
node _raw_hazard_mulpre_mul_raw_haz_T_173 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_69, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_70 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_70, _raw_hazard_mulpre_mul_raw_haz_T_173
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_71 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_71, _raw_hazard_mulpre_mul_raw_haz_WIRE_70
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_68.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_71
node _raw_hazard_mulpre_mul_raw_haz_T_174 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_69, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_68.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_174
node _raw_hazard_mulpre_mul_raw_haz_T_175 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_69, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_68.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_175
node _raw_hazard_mulpre_mul_raw_haz_T_176 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_69, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_68.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_176
node _raw_hazard_mulpre_mul_raw_haz_T_177 = eq(mesh.io.tags_in_progress[8].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_68.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_178 = eq(mesh.io.tags_in_progress[8].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_68.data)
node _raw_hazard_mulpre_mul_raw_haz_T_179 = and(_raw_hazard_mulpre_mul_raw_haz_T_177, _raw_hazard_mulpre_mul_raw_haz_T_178)
node raw_hazard_mulpre_mul_raw_haz_8 = or(_raw_hazard_mulpre_mul_raw_haz_T_169, _raw_hazard_mulpre_mul_raw_haz_T_179)
node _raw_hazard_mulpre_T_40 = eq(raw_hazard_mulpre_is_garbage_8, UInt<1>(0h0))
node _raw_hazard_mulpre_T_41 = or(raw_hazard_mulpre_mul_raw_haz_8, raw_hazard_mulpre_pre_raw_haz_8)
node _raw_hazard_mulpre_T_42 = and(_raw_hazard_mulpre_T_40, _raw_hazard_mulpre_T_41)
node _raw_hazard_mulpre_T_43 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_mulpre_T_44 = and(_raw_hazard_mulpre_T_42, _raw_hazard_mulpre_T_43)
node _raw_hazard_mulpre_is_garbage_T_45 = and(mesh.io.tags_in_progress[9].addr.is_acc_addr, mesh.io.tags_in_progress[9].addr.accumulate)
node _raw_hazard_mulpre_is_garbage_T_46 = and(_raw_hazard_mulpre_is_garbage_T_45, mesh.io.tags_in_progress[9].addr.read_full_acc_row)
node _raw_hazard_mulpre_is_garbage_T_47 = andr(mesh.io.tags_in_progress[9].addr.data)
node _raw_hazard_mulpre_is_garbage_T_48 = and(_raw_hazard_mulpre_is_garbage_T_46, _raw_hazard_mulpre_is_garbage_T_47)
node _raw_hazard_mulpre_is_garbage_T_49 = bits(mesh.io.tags_in_progress[9].addr.garbage_bit, 0, 0)
node raw_hazard_mulpre_is_garbage_9 = and(_raw_hazard_mulpre_is_garbage_T_48, _raw_hazard_mulpre_is_garbage_T_49)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_36 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_37 : UInt<32>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_37, rs1s[1]
node _raw_hazard_mulpre_pre_raw_haz_T_81 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_37, 13, 0)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_36.data, _raw_hazard_mulpre_pre_raw_haz_T_81
node _raw_hazard_mulpre_pre_raw_haz_T_82 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_37, 14, 14)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_36.garbage_bit, _raw_hazard_mulpre_pre_raw_haz_T_82
node _raw_hazard_mulpre_pre_raw_haz_T_83 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_37, 25, 15)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_36.garbage, _raw_hazard_mulpre_pre_raw_haz_T_83
node _raw_hazard_mulpre_pre_raw_haz_T_84 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_37, 28, 26)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_38 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_38, _raw_hazard_mulpre_pre_raw_haz_T_84
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_39 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_39, _raw_hazard_mulpre_pre_raw_haz_WIRE_38
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_36.norm_cmd, _raw_hazard_mulpre_pre_raw_haz_WIRE_39
node _raw_hazard_mulpre_pre_raw_haz_T_85 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_37, 29, 29)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_36.read_full_acc_row, _raw_hazard_mulpre_pre_raw_haz_T_85
node _raw_hazard_mulpre_pre_raw_haz_T_86 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_37, 30, 30)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_36.accumulate, _raw_hazard_mulpre_pre_raw_haz_T_86
node _raw_hazard_mulpre_pre_raw_haz_T_87 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_37, 31, 31)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_36.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_T_87
node _raw_hazard_mulpre_pre_raw_haz_T_88 = eq(mesh.io.tags_in_progress[9].addr.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_WIRE_36.is_acc_addr)
node _raw_hazard_mulpre_pre_raw_haz_T_89 = eq(mesh.io.tags_in_progress[9].addr.data, _raw_hazard_mulpre_pre_raw_haz_WIRE_36.data)
node raw_hazard_mulpre_pre_raw_haz_9 = and(_raw_hazard_mulpre_pre_raw_haz_T_88, _raw_hazard_mulpre_pre_raw_haz_T_89)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_72 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_73 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_73, rs1s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_180 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_73, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_72.data, _raw_hazard_mulpre_mul_raw_haz_T_180
node _raw_hazard_mulpre_mul_raw_haz_T_181 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_73, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_72.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_181
node _raw_hazard_mulpre_mul_raw_haz_T_182 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_73, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_72.garbage, _raw_hazard_mulpre_mul_raw_haz_T_182
node _raw_hazard_mulpre_mul_raw_haz_T_183 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_73, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_74 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_74, _raw_hazard_mulpre_mul_raw_haz_T_183
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_75 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_75, _raw_hazard_mulpre_mul_raw_haz_WIRE_74
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_72.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_75
node _raw_hazard_mulpre_mul_raw_haz_T_184 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_73, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_72.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_184
node _raw_hazard_mulpre_mul_raw_haz_T_185 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_73, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_72.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_185
node _raw_hazard_mulpre_mul_raw_haz_T_186 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_73, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_72.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_186
node _raw_hazard_mulpre_mul_raw_haz_T_187 = eq(mesh.io.tags_in_progress[9].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_72.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_188 = eq(mesh.io.tags_in_progress[9].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_72.data)
node _raw_hazard_mulpre_mul_raw_haz_T_189 = and(_raw_hazard_mulpre_mul_raw_haz_T_187, _raw_hazard_mulpre_mul_raw_haz_T_188)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_76 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_77 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_77, rs2s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_190 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_77, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_76.data, _raw_hazard_mulpre_mul_raw_haz_T_190
node _raw_hazard_mulpre_mul_raw_haz_T_191 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_77, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_76.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_191
node _raw_hazard_mulpre_mul_raw_haz_T_192 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_77, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_76.garbage, _raw_hazard_mulpre_mul_raw_haz_T_192
node _raw_hazard_mulpre_mul_raw_haz_T_193 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_77, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_78 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_78, _raw_hazard_mulpre_mul_raw_haz_T_193
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_79 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_79, _raw_hazard_mulpre_mul_raw_haz_WIRE_78
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_76.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_79
node _raw_hazard_mulpre_mul_raw_haz_T_194 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_77, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_76.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_194
node _raw_hazard_mulpre_mul_raw_haz_T_195 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_77, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_76.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_195
node _raw_hazard_mulpre_mul_raw_haz_T_196 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_77, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_76.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_196
node _raw_hazard_mulpre_mul_raw_haz_T_197 = eq(mesh.io.tags_in_progress[9].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_76.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_198 = eq(mesh.io.tags_in_progress[9].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_76.data)
node _raw_hazard_mulpre_mul_raw_haz_T_199 = and(_raw_hazard_mulpre_mul_raw_haz_T_197, _raw_hazard_mulpre_mul_raw_haz_T_198)
node raw_hazard_mulpre_mul_raw_haz_9 = or(_raw_hazard_mulpre_mul_raw_haz_T_189, _raw_hazard_mulpre_mul_raw_haz_T_199)
node _raw_hazard_mulpre_T_45 = eq(raw_hazard_mulpre_is_garbage_9, UInt<1>(0h0))
node _raw_hazard_mulpre_T_46 = or(raw_hazard_mulpre_mul_raw_haz_9, raw_hazard_mulpre_pre_raw_haz_9)
node _raw_hazard_mulpre_T_47 = and(_raw_hazard_mulpre_T_45, _raw_hazard_mulpre_T_46)
node _raw_hazard_mulpre_T_48 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_mulpre_T_49 = and(_raw_hazard_mulpre_T_47, _raw_hazard_mulpre_T_48)
node _raw_hazard_mulpre_is_garbage_T_50 = and(mesh.io.tags_in_progress[10].addr.is_acc_addr, mesh.io.tags_in_progress[10].addr.accumulate)
node _raw_hazard_mulpre_is_garbage_T_51 = and(_raw_hazard_mulpre_is_garbage_T_50, mesh.io.tags_in_progress[10].addr.read_full_acc_row)
node _raw_hazard_mulpre_is_garbage_T_52 = andr(mesh.io.tags_in_progress[10].addr.data)
node _raw_hazard_mulpre_is_garbage_T_53 = and(_raw_hazard_mulpre_is_garbage_T_51, _raw_hazard_mulpre_is_garbage_T_52)
node _raw_hazard_mulpre_is_garbage_T_54 = bits(mesh.io.tags_in_progress[10].addr.garbage_bit, 0, 0)
node raw_hazard_mulpre_is_garbage_10 = and(_raw_hazard_mulpre_is_garbage_T_53, _raw_hazard_mulpre_is_garbage_T_54)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_40 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_41 : UInt<32>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_41, rs1s[1]
node _raw_hazard_mulpre_pre_raw_haz_T_90 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_41, 13, 0)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_40.data, _raw_hazard_mulpre_pre_raw_haz_T_90
node _raw_hazard_mulpre_pre_raw_haz_T_91 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_41, 14, 14)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_40.garbage_bit, _raw_hazard_mulpre_pre_raw_haz_T_91
node _raw_hazard_mulpre_pre_raw_haz_T_92 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_41, 25, 15)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_40.garbage, _raw_hazard_mulpre_pre_raw_haz_T_92
node _raw_hazard_mulpre_pre_raw_haz_T_93 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_41, 28, 26)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_42 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_42, _raw_hazard_mulpre_pre_raw_haz_T_93
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_43 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_43, _raw_hazard_mulpre_pre_raw_haz_WIRE_42
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_40.norm_cmd, _raw_hazard_mulpre_pre_raw_haz_WIRE_43
node _raw_hazard_mulpre_pre_raw_haz_T_94 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_41, 29, 29)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_40.read_full_acc_row, _raw_hazard_mulpre_pre_raw_haz_T_94
node _raw_hazard_mulpre_pre_raw_haz_T_95 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_41, 30, 30)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_40.accumulate, _raw_hazard_mulpre_pre_raw_haz_T_95
node _raw_hazard_mulpre_pre_raw_haz_T_96 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_41, 31, 31)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_40.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_T_96
node _raw_hazard_mulpre_pre_raw_haz_T_97 = eq(mesh.io.tags_in_progress[10].addr.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_WIRE_40.is_acc_addr)
node _raw_hazard_mulpre_pre_raw_haz_T_98 = eq(mesh.io.tags_in_progress[10].addr.data, _raw_hazard_mulpre_pre_raw_haz_WIRE_40.data)
node raw_hazard_mulpre_pre_raw_haz_10 = and(_raw_hazard_mulpre_pre_raw_haz_T_97, _raw_hazard_mulpre_pre_raw_haz_T_98)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_80 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_81 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_81, rs1s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_200 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_81, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_80.data, _raw_hazard_mulpre_mul_raw_haz_T_200
node _raw_hazard_mulpre_mul_raw_haz_T_201 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_81, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_80.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_201
node _raw_hazard_mulpre_mul_raw_haz_T_202 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_81, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_80.garbage, _raw_hazard_mulpre_mul_raw_haz_T_202
node _raw_hazard_mulpre_mul_raw_haz_T_203 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_81, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_82 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_82, _raw_hazard_mulpre_mul_raw_haz_T_203
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_83 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_83, _raw_hazard_mulpre_mul_raw_haz_WIRE_82
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_80.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_83
node _raw_hazard_mulpre_mul_raw_haz_T_204 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_81, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_80.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_204
node _raw_hazard_mulpre_mul_raw_haz_T_205 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_81, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_80.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_205
node _raw_hazard_mulpre_mul_raw_haz_T_206 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_81, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_80.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_206
node _raw_hazard_mulpre_mul_raw_haz_T_207 = eq(mesh.io.tags_in_progress[10].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_80.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_208 = eq(mesh.io.tags_in_progress[10].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_80.data)
node _raw_hazard_mulpre_mul_raw_haz_T_209 = and(_raw_hazard_mulpre_mul_raw_haz_T_207, _raw_hazard_mulpre_mul_raw_haz_T_208)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_84 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_85 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_85, rs2s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_210 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_85, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_84.data, _raw_hazard_mulpre_mul_raw_haz_T_210
node _raw_hazard_mulpre_mul_raw_haz_T_211 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_85, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_84.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_211
node _raw_hazard_mulpre_mul_raw_haz_T_212 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_85, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_84.garbage, _raw_hazard_mulpre_mul_raw_haz_T_212
node _raw_hazard_mulpre_mul_raw_haz_T_213 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_85, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_86 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_86, _raw_hazard_mulpre_mul_raw_haz_T_213
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_87 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_87, _raw_hazard_mulpre_mul_raw_haz_WIRE_86
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_84.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_87
node _raw_hazard_mulpre_mul_raw_haz_T_214 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_85, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_84.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_214
node _raw_hazard_mulpre_mul_raw_haz_T_215 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_85, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_84.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_215
node _raw_hazard_mulpre_mul_raw_haz_T_216 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_85, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_84.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_216
node _raw_hazard_mulpre_mul_raw_haz_T_217 = eq(mesh.io.tags_in_progress[10].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_84.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_218 = eq(mesh.io.tags_in_progress[10].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_84.data)
node _raw_hazard_mulpre_mul_raw_haz_T_219 = and(_raw_hazard_mulpre_mul_raw_haz_T_217, _raw_hazard_mulpre_mul_raw_haz_T_218)
node raw_hazard_mulpre_mul_raw_haz_10 = or(_raw_hazard_mulpre_mul_raw_haz_T_209, _raw_hazard_mulpre_mul_raw_haz_T_219)
node _raw_hazard_mulpre_T_50 = eq(raw_hazard_mulpre_is_garbage_10, UInt<1>(0h0))
node _raw_hazard_mulpre_T_51 = or(raw_hazard_mulpre_mul_raw_haz_10, raw_hazard_mulpre_pre_raw_haz_10)
node _raw_hazard_mulpre_T_52 = and(_raw_hazard_mulpre_T_50, _raw_hazard_mulpre_T_51)
node _raw_hazard_mulpre_T_53 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_mulpre_T_54 = and(_raw_hazard_mulpre_T_52, _raw_hazard_mulpre_T_53)
node _raw_hazard_mulpre_is_garbage_T_55 = and(mesh.io.tags_in_progress[11].addr.is_acc_addr, mesh.io.tags_in_progress[11].addr.accumulate)
node _raw_hazard_mulpre_is_garbage_T_56 = and(_raw_hazard_mulpre_is_garbage_T_55, mesh.io.tags_in_progress[11].addr.read_full_acc_row)
node _raw_hazard_mulpre_is_garbage_T_57 = andr(mesh.io.tags_in_progress[11].addr.data)
node _raw_hazard_mulpre_is_garbage_T_58 = and(_raw_hazard_mulpre_is_garbage_T_56, _raw_hazard_mulpre_is_garbage_T_57)
node _raw_hazard_mulpre_is_garbage_T_59 = bits(mesh.io.tags_in_progress[11].addr.garbage_bit, 0, 0)
node raw_hazard_mulpre_is_garbage_11 = and(_raw_hazard_mulpre_is_garbage_T_58, _raw_hazard_mulpre_is_garbage_T_59)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_44 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_45 : UInt<32>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_45, rs1s[1]
node _raw_hazard_mulpre_pre_raw_haz_T_99 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_45, 13, 0)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_44.data, _raw_hazard_mulpre_pre_raw_haz_T_99
node _raw_hazard_mulpre_pre_raw_haz_T_100 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_45, 14, 14)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_44.garbage_bit, _raw_hazard_mulpre_pre_raw_haz_T_100
node _raw_hazard_mulpre_pre_raw_haz_T_101 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_45, 25, 15)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_44.garbage, _raw_hazard_mulpre_pre_raw_haz_T_101
node _raw_hazard_mulpre_pre_raw_haz_T_102 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_45, 28, 26)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_46 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_46, _raw_hazard_mulpre_pre_raw_haz_T_102
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_47 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_47, _raw_hazard_mulpre_pre_raw_haz_WIRE_46
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_44.norm_cmd, _raw_hazard_mulpre_pre_raw_haz_WIRE_47
node _raw_hazard_mulpre_pre_raw_haz_T_103 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_45, 29, 29)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_44.read_full_acc_row, _raw_hazard_mulpre_pre_raw_haz_T_103
node _raw_hazard_mulpre_pre_raw_haz_T_104 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_45, 30, 30)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_44.accumulate, _raw_hazard_mulpre_pre_raw_haz_T_104
node _raw_hazard_mulpre_pre_raw_haz_T_105 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_45, 31, 31)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_44.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_T_105
node _raw_hazard_mulpre_pre_raw_haz_T_106 = eq(mesh.io.tags_in_progress[11].addr.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_WIRE_44.is_acc_addr)
node _raw_hazard_mulpre_pre_raw_haz_T_107 = eq(mesh.io.tags_in_progress[11].addr.data, _raw_hazard_mulpre_pre_raw_haz_WIRE_44.data)
node raw_hazard_mulpre_pre_raw_haz_11 = and(_raw_hazard_mulpre_pre_raw_haz_T_106, _raw_hazard_mulpre_pre_raw_haz_T_107)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_88 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_89 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_89, rs1s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_220 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_89, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_88.data, _raw_hazard_mulpre_mul_raw_haz_T_220
node _raw_hazard_mulpre_mul_raw_haz_T_221 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_89, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_88.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_221
node _raw_hazard_mulpre_mul_raw_haz_T_222 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_89, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_88.garbage, _raw_hazard_mulpre_mul_raw_haz_T_222
node _raw_hazard_mulpre_mul_raw_haz_T_223 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_89, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_90 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_90, _raw_hazard_mulpre_mul_raw_haz_T_223
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_91 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_91, _raw_hazard_mulpre_mul_raw_haz_WIRE_90
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_88.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_91
node _raw_hazard_mulpre_mul_raw_haz_T_224 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_89, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_88.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_224
node _raw_hazard_mulpre_mul_raw_haz_T_225 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_89, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_88.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_225
node _raw_hazard_mulpre_mul_raw_haz_T_226 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_89, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_88.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_226
node _raw_hazard_mulpre_mul_raw_haz_T_227 = eq(mesh.io.tags_in_progress[11].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_88.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_228 = eq(mesh.io.tags_in_progress[11].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_88.data)
node _raw_hazard_mulpre_mul_raw_haz_T_229 = and(_raw_hazard_mulpre_mul_raw_haz_T_227, _raw_hazard_mulpre_mul_raw_haz_T_228)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_92 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_93 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_93, rs2s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_230 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_93, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_92.data, _raw_hazard_mulpre_mul_raw_haz_T_230
node _raw_hazard_mulpre_mul_raw_haz_T_231 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_93, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_92.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_231
node _raw_hazard_mulpre_mul_raw_haz_T_232 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_93, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_92.garbage, _raw_hazard_mulpre_mul_raw_haz_T_232
node _raw_hazard_mulpre_mul_raw_haz_T_233 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_93, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_94 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_94, _raw_hazard_mulpre_mul_raw_haz_T_233
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_95 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_95, _raw_hazard_mulpre_mul_raw_haz_WIRE_94
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_92.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_95
node _raw_hazard_mulpre_mul_raw_haz_T_234 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_93, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_92.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_234
node _raw_hazard_mulpre_mul_raw_haz_T_235 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_93, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_92.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_235
node _raw_hazard_mulpre_mul_raw_haz_T_236 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_93, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_92.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_236
node _raw_hazard_mulpre_mul_raw_haz_T_237 = eq(mesh.io.tags_in_progress[11].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_92.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_238 = eq(mesh.io.tags_in_progress[11].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_92.data)
node _raw_hazard_mulpre_mul_raw_haz_T_239 = and(_raw_hazard_mulpre_mul_raw_haz_T_237, _raw_hazard_mulpre_mul_raw_haz_T_238)
node raw_hazard_mulpre_mul_raw_haz_11 = or(_raw_hazard_mulpre_mul_raw_haz_T_229, _raw_hazard_mulpre_mul_raw_haz_T_239)
node _raw_hazard_mulpre_T_55 = eq(raw_hazard_mulpre_is_garbage_11, UInt<1>(0h0))
node _raw_hazard_mulpre_T_56 = or(raw_hazard_mulpre_mul_raw_haz_11, raw_hazard_mulpre_pre_raw_haz_11)
node _raw_hazard_mulpre_T_57 = and(_raw_hazard_mulpre_T_55, _raw_hazard_mulpre_T_56)
node _raw_hazard_mulpre_T_58 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_mulpre_T_59 = and(_raw_hazard_mulpre_T_57, _raw_hazard_mulpre_T_58)
node _raw_hazard_mulpre_is_garbage_T_60 = and(mesh.io.tags_in_progress[12].addr.is_acc_addr, mesh.io.tags_in_progress[12].addr.accumulate)
node _raw_hazard_mulpre_is_garbage_T_61 = and(_raw_hazard_mulpre_is_garbage_T_60, mesh.io.tags_in_progress[12].addr.read_full_acc_row)
node _raw_hazard_mulpre_is_garbage_T_62 = andr(mesh.io.tags_in_progress[12].addr.data)
node _raw_hazard_mulpre_is_garbage_T_63 = and(_raw_hazard_mulpre_is_garbage_T_61, _raw_hazard_mulpre_is_garbage_T_62)
node _raw_hazard_mulpre_is_garbage_T_64 = bits(mesh.io.tags_in_progress[12].addr.garbage_bit, 0, 0)
node raw_hazard_mulpre_is_garbage_12 = and(_raw_hazard_mulpre_is_garbage_T_63, _raw_hazard_mulpre_is_garbage_T_64)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_48 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_49 : UInt<32>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_49, rs1s[1]
node _raw_hazard_mulpre_pre_raw_haz_T_108 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_49, 13, 0)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_48.data, _raw_hazard_mulpre_pre_raw_haz_T_108
node _raw_hazard_mulpre_pre_raw_haz_T_109 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_49, 14, 14)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_48.garbage_bit, _raw_hazard_mulpre_pre_raw_haz_T_109
node _raw_hazard_mulpre_pre_raw_haz_T_110 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_49, 25, 15)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_48.garbage, _raw_hazard_mulpre_pre_raw_haz_T_110
node _raw_hazard_mulpre_pre_raw_haz_T_111 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_49, 28, 26)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_50 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_50, _raw_hazard_mulpre_pre_raw_haz_T_111
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_51 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_51, _raw_hazard_mulpre_pre_raw_haz_WIRE_50
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_48.norm_cmd, _raw_hazard_mulpre_pre_raw_haz_WIRE_51
node _raw_hazard_mulpre_pre_raw_haz_T_112 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_49, 29, 29)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_48.read_full_acc_row, _raw_hazard_mulpre_pre_raw_haz_T_112
node _raw_hazard_mulpre_pre_raw_haz_T_113 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_49, 30, 30)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_48.accumulate, _raw_hazard_mulpre_pre_raw_haz_T_113
node _raw_hazard_mulpre_pre_raw_haz_T_114 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_49, 31, 31)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_48.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_T_114
node _raw_hazard_mulpre_pre_raw_haz_T_115 = eq(mesh.io.tags_in_progress[12].addr.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_WIRE_48.is_acc_addr)
node _raw_hazard_mulpre_pre_raw_haz_T_116 = eq(mesh.io.tags_in_progress[12].addr.data, _raw_hazard_mulpre_pre_raw_haz_WIRE_48.data)
node raw_hazard_mulpre_pre_raw_haz_12 = and(_raw_hazard_mulpre_pre_raw_haz_T_115, _raw_hazard_mulpre_pre_raw_haz_T_116)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_96 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_97 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_97, rs1s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_240 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_97, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_96.data, _raw_hazard_mulpre_mul_raw_haz_T_240
node _raw_hazard_mulpre_mul_raw_haz_T_241 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_97, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_96.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_241
node _raw_hazard_mulpre_mul_raw_haz_T_242 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_97, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_96.garbage, _raw_hazard_mulpre_mul_raw_haz_T_242
node _raw_hazard_mulpre_mul_raw_haz_T_243 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_97, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_98 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_98, _raw_hazard_mulpre_mul_raw_haz_T_243
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_99 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_99, _raw_hazard_mulpre_mul_raw_haz_WIRE_98
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_96.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_99
node _raw_hazard_mulpre_mul_raw_haz_T_244 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_97, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_96.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_244
node _raw_hazard_mulpre_mul_raw_haz_T_245 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_97, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_96.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_245
node _raw_hazard_mulpre_mul_raw_haz_T_246 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_97, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_96.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_246
node _raw_hazard_mulpre_mul_raw_haz_T_247 = eq(mesh.io.tags_in_progress[12].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_96.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_248 = eq(mesh.io.tags_in_progress[12].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_96.data)
node _raw_hazard_mulpre_mul_raw_haz_T_249 = and(_raw_hazard_mulpre_mul_raw_haz_T_247, _raw_hazard_mulpre_mul_raw_haz_T_248)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_100 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_101 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_101, rs2s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_250 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_101, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_100.data, _raw_hazard_mulpre_mul_raw_haz_T_250
node _raw_hazard_mulpre_mul_raw_haz_T_251 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_101, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_100.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_251
node _raw_hazard_mulpre_mul_raw_haz_T_252 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_101, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_100.garbage, _raw_hazard_mulpre_mul_raw_haz_T_252
node _raw_hazard_mulpre_mul_raw_haz_T_253 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_101, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_102 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_102, _raw_hazard_mulpre_mul_raw_haz_T_253
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_103 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_103, _raw_hazard_mulpre_mul_raw_haz_WIRE_102
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_100.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_103
node _raw_hazard_mulpre_mul_raw_haz_T_254 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_101, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_100.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_254
node _raw_hazard_mulpre_mul_raw_haz_T_255 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_101, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_100.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_255
node _raw_hazard_mulpre_mul_raw_haz_T_256 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_101, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_100.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_256
node _raw_hazard_mulpre_mul_raw_haz_T_257 = eq(mesh.io.tags_in_progress[12].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_100.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_258 = eq(mesh.io.tags_in_progress[12].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_100.data)
node _raw_hazard_mulpre_mul_raw_haz_T_259 = and(_raw_hazard_mulpre_mul_raw_haz_T_257, _raw_hazard_mulpre_mul_raw_haz_T_258)
node raw_hazard_mulpre_mul_raw_haz_12 = or(_raw_hazard_mulpre_mul_raw_haz_T_249, _raw_hazard_mulpre_mul_raw_haz_T_259)
node _raw_hazard_mulpre_T_60 = eq(raw_hazard_mulpre_is_garbage_12, UInt<1>(0h0))
node _raw_hazard_mulpre_T_61 = or(raw_hazard_mulpre_mul_raw_haz_12, raw_hazard_mulpre_pre_raw_haz_12)
node _raw_hazard_mulpre_T_62 = and(_raw_hazard_mulpre_T_60, _raw_hazard_mulpre_T_61)
node _raw_hazard_mulpre_T_63 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_mulpre_T_64 = and(_raw_hazard_mulpre_T_62, _raw_hazard_mulpre_T_63)
node _raw_hazard_mulpre_is_garbage_T_65 = and(mesh.io.tags_in_progress[13].addr.is_acc_addr, mesh.io.tags_in_progress[13].addr.accumulate)
node _raw_hazard_mulpre_is_garbage_T_66 = and(_raw_hazard_mulpre_is_garbage_T_65, mesh.io.tags_in_progress[13].addr.read_full_acc_row)
node _raw_hazard_mulpre_is_garbage_T_67 = andr(mesh.io.tags_in_progress[13].addr.data)
node _raw_hazard_mulpre_is_garbage_T_68 = and(_raw_hazard_mulpre_is_garbage_T_66, _raw_hazard_mulpre_is_garbage_T_67)
node _raw_hazard_mulpre_is_garbage_T_69 = bits(mesh.io.tags_in_progress[13].addr.garbage_bit, 0, 0)
node raw_hazard_mulpre_is_garbage_13 = and(_raw_hazard_mulpre_is_garbage_T_68, _raw_hazard_mulpre_is_garbage_T_69)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_52 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_53 : UInt<32>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_53, rs1s[1]
node _raw_hazard_mulpre_pre_raw_haz_T_117 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_53, 13, 0)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_52.data, _raw_hazard_mulpre_pre_raw_haz_T_117
node _raw_hazard_mulpre_pre_raw_haz_T_118 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_53, 14, 14)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_52.garbage_bit, _raw_hazard_mulpre_pre_raw_haz_T_118
node _raw_hazard_mulpre_pre_raw_haz_T_119 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_53, 25, 15)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_52.garbage, _raw_hazard_mulpre_pre_raw_haz_T_119
node _raw_hazard_mulpre_pre_raw_haz_T_120 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_53, 28, 26)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_54 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_54, _raw_hazard_mulpre_pre_raw_haz_T_120
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_55 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_55, _raw_hazard_mulpre_pre_raw_haz_WIRE_54
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_52.norm_cmd, _raw_hazard_mulpre_pre_raw_haz_WIRE_55
node _raw_hazard_mulpre_pre_raw_haz_T_121 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_53, 29, 29)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_52.read_full_acc_row, _raw_hazard_mulpre_pre_raw_haz_T_121
node _raw_hazard_mulpre_pre_raw_haz_T_122 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_53, 30, 30)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_52.accumulate, _raw_hazard_mulpre_pre_raw_haz_T_122
node _raw_hazard_mulpre_pre_raw_haz_T_123 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_53, 31, 31)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_52.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_T_123
node _raw_hazard_mulpre_pre_raw_haz_T_124 = eq(mesh.io.tags_in_progress[13].addr.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_WIRE_52.is_acc_addr)
node _raw_hazard_mulpre_pre_raw_haz_T_125 = eq(mesh.io.tags_in_progress[13].addr.data, _raw_hazard_mulpre_pre_raw_haz_WIRE_52.data)
node raw_hazard_mulpre_pre_raw_haz_13 = and(_raw_hazard_mulpre_pre_raw_haz_T_124, _raw_hazard_mulpre_pre_raw_haz_T_125)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_104 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_105 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_105, rs1s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_260 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_105, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_104.data, _raw_hazard_mulpre_mul_raw_haz_T_260
node _raw_hazard_mulpre_mul_raw_haz_T_261 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_105, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_104.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_261
node _raw_hazard_mulpre_mul_raw_haz_T_262 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_105, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_104.garbage, _raw_hazard_mulpre_mul_raw_haz_T_262
node _raw_hazard_mulpre_mul_raw_haz_T_263 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_105, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_106 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_106, _raw_hazard_mulpre_mul_raw_haz_T_263
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_107 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_107, _raw_hazard_mulpre_mul_raw_haz_WIRE_106
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_104.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_107
node _raw_hazard_mulpre_mul_raw_haz_T_264 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_105, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_104.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_264
node _raw_hazard_mulpre_mul_raw_haz_T_265 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_105, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_104.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_265
node _raw_hazard_mulpre_mul_raw_haz_T_266 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_105, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_104.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_266
node _raw_hazard_mulpre_mul_raw_haz_T_267 = eq(mesh.io.tags_in_progress[13].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_104.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_268 = eq(mesh.io.tags_in_progress[13].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_104.data)
node _raw_hazard_mulpre_mul_raw_haz_T_269 = and(_raw_hazard_mulpre_mul_raw_haz_T_267, _raw_hazard_mulpre_mul_raw_haz_T_268)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_108 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_109 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_109, rs2s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_270 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_109, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_108.data, _raw_hazard_mulpre_mul_raw_haz_T_270
node _raw_hazard_mulpre_mul_raw_haz_T_271 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_109, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_108.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_271
node _raw_hazard_mulpre_mul_raw_haz_T_272 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_109, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_108.garbage, _raw_hazard_mulpre_mul_raw_haz_T_272
node _raw_hazard_mulpre_mul_raw_haz_T_273 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_109, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_110 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_110, _raw_hazard_mulpre_mul_raw_haz_T_273
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_111 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_111, _raw_hazard_mulpre_mul_raw_haz_WIRE_110
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_108.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_111
node _raw_hazard_mulpre_mul_raw_haz_T_274 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_109, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_108.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_274
node _raw_hazard_mulpre_mul_raw_haz_T_275 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_109, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_108.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_275
node _raw_hazard_mulpre_mul_raw_haz_T_276 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_109, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_108.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_276
node _raw_hazard_mulpre_mul_raw_haz_T_277 = eq(mesh.io.tags_in_progress[13].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_108.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_278 = eq(mesh.io.tags_in_progress[13].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_108.data)
node _raw_hazard_mulpre_mul_raw_haz_T_279 = and(_raw_hazard_mulpre_mul_raw_haz_T_277, _raw_hazard_mulpre_mul_raw_haz_T_278)
node raw_hazard_mulpre_mul_raw_haz_13 = or(_raw_hazard_mulpre_mul_raw_haz_T_269, _raw_hazard_mulpre_mul_raw_haz_T_279)
node _raw_hazard_mulpre_T_65 = eq(raw_hazard_mulpre_is_garbage_13, UInt<1>(0h0))
node _raw_hazard_mulpre_T_66 = or(raw_hazard_mulpre_mul_raw_haz_13, raw_hazard_mulpre_pre_raw_haz_13)
node _raw_hazard_mulpre_T_67 = and(_raw_hazard_mulpre_T_65, _raw_hazard_mulpre_T_66)
node _raw_hazard_mulpre_T_68 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_mulpre_T_69 = and(_raw_hazard_mulpre_T_67, _raw_hazard_mulpre_T_68)
node _raw_hazard_mulpre_is_garbage_T_70 = and(mesh.io.tags_in_progress[14].addr.is_acc_addr, mesh.io.tags_in_progress[14].addr.accumulate)
node _raw_hazard_mulpre_is_garbage_T_71 = and(_raw_hazard_mulpre_is_garbage_T_70, mesh.io.tags_in_progress[14].addr.read_full_acc_row)
node _raw_hazard_mulpre_is_garbage_T_72 = andr(mesh.io.tags_in_progress[14].addr.data)
node _raw_hazard_mulpre_is_garbage_T_73 = and(_raw_hazard_mulpre_is_garbage_T_71, _raw_hazard_mulpre_is_garbage_T_72)
node _raw_hazard_mulpre_is_garbage_T_74 = bits(mesh.io.tags_in_progress[14].addr.garbage_bit, 0, 0)
node raw_hazard_mulpre_is_garbage_14 = and(_raw_hazard_mulpre_is_garbage_T_73, _raw_hazard_mulpre_is_garbage_T_74)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_56 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_57 : UInt<32>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_57, rs1s[1]
node _raw_hazard_mulpre_pre_raw_haz_T_126 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_57, 13, 0)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_56.data, _raw_hazard_mulpre_pre_raw_haz_T_126
node _raw_hazard_mulpre_pre_raw_haz_T_127 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_57, 14, 14)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_56.garbage_bit, _raw_hazard_mulpre_pre_raw_haz_T_127
node _raw_hazard_mulpre_pre_raw_haz_T_128 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_57, 25, 15)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_56.garbage, _raw_hazard_mulpre_pre_raw_haz_T_128
node _raw_hazard_mulpre_pre_raw_haz_T_129 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_57, 28, 26)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_58 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_58, _raw_hazard_mulpre_pre_raw_haz_T_129
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_59 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_59, _raw_hazard_mulpre_pre_raw_haz_WIRE_58
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_56.norm_cmd, _raw_hazard_mulpre_pre_raw_haz_WIRE_59
node _raw_hazard_mulpre_pre_raw_haz_T_130 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_57, 29, 29)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_56.read_full_acc_row, _raw_hazard_mulpre_pre_raw_haz_T_130
node _raw_hazard_mulpre_pre_raw_haz_T_131 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_57, 30, 30)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_56.accumulate, _raw_hazard_mulpre_pre_raw_haz_T_131
node _raw_hazard_mulpre_pre_raw_haz_T_132 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_57, 31, 31)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_56.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_T_132
node _raw_hazard_mulpre_pre_raw_haz_T_133 = eq(mesh.io.tags_in_progress[14].addr.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_WIRE_56.is_acc_addr)
node _raw_hazard_mulpre_pre_raw_haz_T_134 = eq(mesh.io.tags_in_progress[14].addr.data, _raw_hazard_mulpre_pre_raw_haz_WIRE_56.data)
node raw_hazard_mulpre_pre_raw_haz_14 = and(_raw_hazard_mulpre_pre_raw_haz_T_133, _raw_hazard_mulpre_pre_raw_haz_T_134)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_112 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_113 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_113, rs1s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_280 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_113, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_112.data, _raw_hazard_mulpre_mul_raw_haz_T_280
node _raw_hazard_mulpre_mul_raw_haz_T_281 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_113, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_112.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_281
node _raw_hazard_mulpre_mul_raw_haz_T_282 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_113, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_112.garbage, _raw_hazard_mulpre_mul_raw_haz_T_282
node _raw_hazard_mulpre_mul_raw_haz_T_283 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_113, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_114 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_114, _raw_hazard_mulpre_mul_raw_haz_T_283
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_115 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_115, _raw_hazard_mulpre_mul_raw_haz_WIRE_114
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_112.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_115
node _raw_hazard_mulpre_mul_raw_haz_T_284 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_113, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_112.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_284
node _raw_hazard_mulpre_mul_raw_haz_T_285 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_113, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_112.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_285
node _raw_hazard_mulpre_mul_raw_haz_T_286 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_113, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_112.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_286
node _raw_hazard_mulpre_mul_raw_haz_T_287 = eq(mesh.io.tags_in_progress[14].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_112.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_288 = eq(mesh.io.tags_in_progress[14].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_112.data)
node _raw_hazard_mulpre_mul_raw_haz_T_289 = and(_raw_hazard_mulpre_mul_raw_haz_T_287, _raw_hazard_mulpre_mul_raw_haz_T_288)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_116 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_117 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_117, rs2s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_290 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_117, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_116.data, _raw_hazard_mulpre_mul_raw_haz_T_290
node _raw_hazard_mulpre_mul_raw_haz_T_291 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_117, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_116.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_291
node _raw_hazard_mulpre_mul_raw_haz_T_292 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_117, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_116.garbage, _raw_hazard_mulpre_mul_raw_haz_T_292
node _raw_hazard_mulpre_mul_raw_haz_T_293 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_117, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_118 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_118, _raw_hazard_mulpre_mul_raw_haz_T_293
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_119 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_119, _raw_hazard_mulpre_mul_raw_haz_WIRE_118
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_116.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_119
node _raw_hazard_mulpre_mul_raw_haz_T_294 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_117, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_116.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_294
node _raw_hazard_mulpre_mul_raw_haz_T_295 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_117, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_116.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_295
node _raw_hazard_mulpre_mul_raw_haz_T_296 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_117, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_116.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_296
node _raw_hazard_mulpre_mul_raw_haz_T_297 = eq(mesh.io.tags_in_progress[14].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_116.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_298 = eq(mesh.io.tags_in_progress[14].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_116.data)
node _raw_hazard_mulpre_mul_raw_haz_T_299 = and(_raw_hazard_mulpre_mul_raw_haz_T_297, _raw_hazard_mulpre_mul_raw_haz_T_298)
node raw_hazard_mulpre_mul_raw_haz_14 = or(_raw_hazard_mulpre_mul_raw_haz_T_289, _raw_hazard_mulpre_mul_raw_haz_T_299)
node _raw_hazard_mulpre_T_70 = eq(raw_hazard_mulpre_is_garbage_14, UInt<1>(0h0))
node _raw_hazard_mulpre_T_71 = or(raw_hazard_mulpre_mul_raw_haz_14, raw_hazard_mulpre_pre_raw_haz_14)
node _raw_hazard_mulpre_T_72 = and(_raw_hazard_mulpre_T_70, _raw_hazard_mulpre_T_71)
node _raw_hazard_mulpre_T_73 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_mulpre_T_74 = and(_raw_hazard_mulpre_T_72, _raw_hazard_mulpre_T_73)
node _raw_hazard_mulpre_is_garbage_T_75 = and(mesh.io.tags_in_progress[15].addr.is_acc_addr, mesh.io.tags_in_progress[15].addr.accumulate)
node _raw_hazard_mulpre_is_garbage_T_76 = and(_raw_hazard_mulpre_is_garbage_T_75, mesh.io.tags_in_progress[15].addr.read_full_acc_row)
node _raw_hazard_mulpre_is_garbage_T_77 = andr(mesh.io.tags_in_progress[15].addr.data)
node _raw_hazard_mulpre_is_garbage_T_78 = and(_raw_hazard_mulpre_is_garbage_T_76, _raw_hazard_mulpre_is_garbage_T_77)
node _raw_hazard_mulpre_is_garbage_T_79 = bits(mesh.io.tags_in_progress[15].addr.garbage_bit, 0, 0)
node raw_hazard_mulpre_is_garbage_15 = and(_raw_hazard_mulpre_is_garbage_T_78, _raw_hazard_mulpre_is_garbage_T_79)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_60 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_61 : UInt<32>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_61, rs1s[1]
node _raw_hazard_mulpre_pre_raw_haz_T_135 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_61, 13, 0)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_60.data, _raw_hazard_mulpre_pre_raw_haz_T_135
node _raw_hazard_mulpre_pre_raw_haz_T_136 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_61, 14, 14)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_60.garbage_bit, _raw_hazard_mulpre_pre_raw_haz_T_136
node _raw_hazard_mulpre_pre_raw_haz_T_137 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_61, 25, 15)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_60.garbage, _raw_hazard_mulpre_pre_raw_haz_T_137
node _raw_hazard_mulpre_pre_raw_haz_T_138 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_61, 28, 26)
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_62 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_62, _raw_hazard_mulpre_pre_raw_haz_T_138
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_63 : UInt<3>
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_63, _raw_hazard_mulpre_pre_raw_haz_WIRE_62
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_60.norm_cmd, _raw_hazard_mulpre_pre_raw_haz_WIRE_63
node _raw_hazard_mulpre_pre_raw_haz_T_139 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_61, 29, 29)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_60.read_full_acc_row, _raw_hazard_mulpre_pre_raw_haz_T_139
node _raw_hazard_mulpre_pre_raw_haz_T_140 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_61, 30, 30)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_60.accumulate, _raw_hazard_mulpre_pre_raw_haz_T_140
node _raw_hazard_mulpre_pre_raw_haz_T_141 = bits(_raw_hazard_mulpre_pre_raw_haz_WIRE_61, 31, 31)
connect _raw_hazard_mulpre_pre_raw_haz_WIRE_60.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_T_141
node _raw_hazard_mulpre_pre_raw_haz_T_142 = eq(mesh.io.tags_in_progress[15].addr.is_acc_addr, _raw_hazard_mulpre_pre_raw_haz_WIRE_60.is_acc_addr)
node _raw_hazard_mulpre_pre_raw_haz_T_143 = eq(mesh.io.tags_in_progress[15].addr.data, _raw_hazard_mulpre_pre_raw_haz_WIRE_60.data)
node raw_hazard_mulpre_pre_raw_haz_15 = and(_raw_hazard_mulpre_pre_raw_haz_T_142, _raw_hazard_mulpre_pre_raw_haz_T_143)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_120 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_121 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_121, rs1s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_300 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_121, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_120.data, _raw_hazard_mulpre_mul_raw_haz_T_300
node _raw_hazard_mulpre_mul_raw_haz_T_301 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_121, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_120.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_301
node _raw_hazard_mulpre_mul_raw_haz_T_302 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_121, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_120.garbage, _raw_hazard_mulpre_mul_raw_haz_T_302
node _raw_hazard_mulpre_mul_raw_haz_T_303 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_121, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_122 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_122, _raw_hazard_mulpre_mul_raw_haz_T_303
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_123 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_123, _raw_hazard_mulpre_mul_raw_haz_WIRE_122
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_120.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_123
node _raw_hazard_mulpre_mul_raw_haz_T_304 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_121, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_120.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_304
node _raw_hazard_mulpre_mul_raw_haz_T_305 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_121, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_120.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_305
node _raw_hazard_mulpre_mul_raw_haz_T_306 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_121, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_120.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_306
node _raw_hazard_mulpre_mul_raw_haz_T_307 = eq(mesh.io.tags_in_progress[15].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_120.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_308 = eq(mesh.io.tags_in_progress[15].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_120.data)
node _raw_hazard_mulpre_mul_raw_haz_T_309 = and(_raw_hazard_mulpre_mul_raw_haz_T_307, _raw_hazard_mulpre_mul_raw_haz_T_308)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_124 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_125 : UInt<32>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_125, rs2s[2]
node _raw_hazard_mulpre_mul_raw_haz_T_310 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_125, 13, 0)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_124.data, _raw_hazard_mulpre_mul_raw_haz_T_310
node _raw_hazard_mulpre_mul_raw_haz_T_311 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_125, 14, 14)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_124.garbage_bit, _raw_hazard_mulpre_mul_raw_haz_T_311
node _raw_hazard_mulpre_mul_raw_haz_T_312 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_125, 25, 15)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_124.garbage, _raw_hazard_mulpre_mul_raw_haz_T_312
node _raw_hazard_mulpre_mul_raw_haz_T_313 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_125, 28, 26)
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_126 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_126, _raw_hazard_mulpre_mul_raw_haz_T_313
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_127 : UInt<3>
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_127, _raw_hazard_mulpre_mul_raw_haz_WIRE_126
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_124.norm_cmd, _raw_hazard_mulpre_mul_raw_haz_WIRE_127
node _raw_hazard_mulpre_mul_raw_haz_T_314 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_125, 29, 29)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_124.read_full_acc_row, _raw_hazard_mulpre_mul_raw_haz_T_314
node _raw_hazard_mulpre_mul_raw_haz_T_315 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_125, 30, 30)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_124.accumulate, _raw_hazard_mulpre_mul_raw_haz_T_315
node _raw_hazard_mulpre_mul_raw_haz_T_316 = bits(_raw_hazard_mulpre_mul_raw_haz_WIRE_125, 31, 31)
connect _raw_hazard_mulpre_mul_raw_haz_WIRE_124.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_T_316
node _raw_hazard_mulpre_mul_raw_haz_T_317 = eq(mesh.io.tags_in_progress[15].addr.is_acc_addr, _raw_hazard_mulpre_mul_raw_haz_WIRE_124.is_acc_addr)
node _raw_hazard_mulpre_mul_raw_haz_T_318 = eq(mesh.io.tags_in_progress[15].addr.data, _raw_hazard_mulpre_mul_raw_haz_WIRE_124.data)
node _raw_hazard_mulpre_mul_raw_haz_T_319 = and(_raw_hazard_mulpre_mul_raw_haz_T_317, _raw_hazard_mulpre_mul_raw_haz_T_318)
node raw_hazard_mulpre_mul_raw_haz_15 = or(_raw_hazard_mulpre_mul_raw_haz_T_309, _raw_hazard_mulpre_mul_raw_haz_T_319)
node _raw_hazard_mulpre_T_75 = eq(raw_hazard_mulpre_is_garbage_15, UInt<1>(0h0))
node _raw_hazard_mulpre_T_76 = or(raw_hazard_mulpre_mul_raw_haz_15, raw_hazard_mulpre_pre_raw_haz_15)
node _raw_hazard_mulpre_T_77 = and(_raw_hazard_mulpre_T_75, _raw_hazard_mulpre_T_76)
node _raw_hazard_mulpre_T_78 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _raw_hazard_mulpre_T_79 = and(_raw_hazard_mulpre_T_77, _raw_hazard_mulpre_T_78)
node _raw_hazard_mulpre_T_80 = or(_raw_hazard_mulpre_T_4, _raw_hazard_mulpre_T_9)
node _raw_hazard_mulpre_T_81 = or(_raw_hazard_mulpre_T_80, _raw_hazard_mulpre_T_14)
node _raw_hazard_mulpre_T_82 = or(_raw_hazard_mulpre_T_81, _raw_hazard_mulpre_T_19)
node _raw_hazard_mulpre_T_83 = or(_raw_hazard_mulpre_T_82, _raw_hazard_mulpre_T_24)
node _raw_hazard_mulpre_T_84 = or(_raw_hazard_mulpre_T_83, _raw_hazard_mulpre_T_29)
node _raw_hazard_mulpre_T_85 = or(_raw_hazard_mulpre_T_84, _raw_hazard_mulpre_T_34)
node _raw_hazard_mulpre_T_86 = or(_raw_hazard_mulpre_T_85, _raw_hazard_mulpre_T_39)
node _raw_hazard_mulpre_T_87 = or(_raw_hazard_mulpre_T_86, _raw_hazard_mulpre_T_44)
node _raw_hazard_mulpre_T_88 = or(_raw_hazard_mulpre_T_87, _raw_hazard_mulpre_T_49)
node _raw_hazard_mulpre_T_89 = or(_raw_hazard_mulpre_T_88, _raw_hazard_mulpre_T_54)
node _raw_hazard_mulpre_T_90 = or(_raw_hazard_mulpre_T_89, _raw_hazard_mulpre_T_59)
node _raw_hazard_mulpre_T_91 = or(_raw_hazard_mulpre_T_90, _raw_hazard_mulpre_T_64)
node _raw_hazard_mulpre_T_92 = or(_raw_hazard_mulpre_T_91, _raw_hazard_mulpre_T_69)
node _raw_hazard_mulpre_T_93 = or(_raw_hazard_mulpre_T_92, _raw_hazard_mulpre_T_74)
node raw_hazard_mulpre = or(_raw_hazard_mulpre_T_93, _raw_hazard_mulpre_T_79)
node _third_instruction_needed_T = gt(a_address_place, UInt<1>(0h1))
node _third_instruction_needed_T_1 = gt(b_address_place, UInt<1>(0h1))
node _third_instruction_needed_T_2 = or(_third_instruction_needed_T, _third_instruction_needed_T_1)
node _third_instruction_needed_T_3 = gt(preload_cmd_place, UInt<1>(0h1))
node _third_instruction_needed_T_4 = or(_third_instruction_needed_T_2, _third_instruction_needed_T_3)
node _third_instruction_needed_T_5 = eq(UInt<1>(0h0), UInt<1>(0h0))
node third_instruction_needed = or(_third_instruction_needed_T_4, _third_instruction_needed_T_5)
node _matmul_in_progress_T = or(mesh.io.tags_in_progress[0].rob_id.valid, mesh.io.tags_in_progress[1].rob_id.valid)
node _matmul_in_progress_T_1 = or(_matmul_in_progress_T, mesh.io.tags_in_progress[2].rob_id.valid)
node _matmul_in_progress_T_2 = or(_matmul_in_progress_T_1, mesh.io.tags_in_progress[3].rob_id.valid)
node _matmul_in_progress_T_3 = or(_matmul_in_progress_T_2, mesh.io.tags_in_progress[4].rob_id.valid)
node _matmul_in_progress_T_4 = or(_matmul_in_progress_T_3, mesh.io.tags_in_progress[5].rob_id.valid)
node _matmul_in_progress_T_5 = or(_matmul_in_progress_T_4, mesh.io.tags_in_progress[6].rob_id.valid)
node _matmul_in_progress_T_6 = or(_matmul_in_progress_T_5, mesh.io.tags_in_progress[7].rob_id.valid)
node _matmul_in_progress_T_7 = or(_matmul_in_progress_T_6, mesh.io.tags_in_progress[8].rob_id.valid)
node _matmul_in_progress_T_8 = or(_matmul_in_progress_T_7, mesh.io.tags_in_progress[9].rob_id.valid)
node _matmul_in_progress_T_9 = or(_matmul_in_progress_T_8, mesh.io.tags_in_progress[10].rob_id.valid)
node _matmul_in_progress_T_10 = or(_matmul_in_progress_T_9, mesh.io.tags_in_progress[11].rob_id.valid)
node _matmul_in_progress_T_11 = or(_matmul_in_progress_T_10, mesh.io.tags_in_progress[12].rob_id.valid)
node _matmul_in_progress_T_12 = or(_matmul_in_progress_T_11, mesh.io.tags_in_progress[13].rob_id.valid)
node _matmul_in_progress_T_13 = or(_matmul_in_progress_T_12, mesh.io.tags_in_progress[14].rob_id.valid)
node matmul_in_progress = or(_matmul_in_progress_T_13, mesh.io.tags_in_progress[15].rob_id.valid)
node _io_busy_T = or(cmd_q.io.deq.valid[0], matmul_in_progress)
connect io.busy, _io_busy_T
reg a_fire_counter : UInt<2>, clock
reg b_fire_counter : UInt<2>, clock
reg d_fire_counter : UInt<2>, clock
regreset a_fire_started : UInt<1>, clock, reset, UInt<1>(0h0)
regreset d_fire_started : UInt<1>, clock, reset, UInt<1>(0h0)
regreset b_fire_started : UInt<1>, clock, reset, UInt<1>(0h0)
reg a_addr_offset : UInt<18>, clock
reg a_addr_stride : UInt<16>, clock
reg c_addr_stride : UInt<16>, clock
wire a_address : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
connect a_address, a_address_rs1
node _a_address_result_data_T = add(a_address_rs1.data, a_addr_offset)
node _a_address_result_data_T_1 = tail(_a_address_result_data_T, 1)
connect a_address.data, _a_address_result_data_T_1
wire b_address : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
connect b_address, b_address_rs2
node _b_address_result_data_T = add(b_address_rs2.data, b_fire_counter)
node _b_address_result_data_T_1 = tail(_b_address_result_data_T, 1)
connect b_address.data, _b_address_result_data_T_1
node _d_address_T = sub(UInt<3>(0h4), UInt<1>(0h1))
node _d_address_T_1 = tail(_d_address_T, 1)
node _d_address_T_2 = sub(_d_address_T_1, d_fire_counter)
node _d_address_T_3 = tail(_d_address_T_2, 1)
wire d_address : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
connect d_address, d_address_rs1
node _d_address_result_data_T = add(d_address_rs1.data, _d_address_T_3)
node _d_address_result_data_T_1 = tail(_d_address_result_data_T, 1)
connect d_address.data, _d_address_result_data_T_1
node dataAbank = bits(a_address.data, 13, 12)
node dataBbank = bits(b_address.data, 13, 12)
node dataDbank = bits(d_address.data, 13, 12)
node a_read_from_acc = and(UInt<1>(0h1), a_address_rs1.is_acc_addr)
node b_read_from_acc = and(UInt<1>(0h1), b_address_rs2.is_acc_addr)
node d_read_from_acc = and(UInt<1>(0h1), d_address_rs1.is_acc_addr)
wire start_inputting_a : UInt<1>
connect start_inputting_a, UInt<1>(0h0)
wire start_inputting_b : UInt<1>
connect start_inputting_b, UInt<1>(0h0)
wire start_inputting_d : UInt<1>
connect start_inputting_d, UInt<1>(0h0)
wire start_array_outputting : UInt<1>
connect start_array_outputting, UInt<1>(0h0)
node _a_garbage_T = and(a_address_rs1.is_acc_addr, a_address_rs1.accumulate)
node _a_garbage_T_1 = and(_a_garbage_T, a_address_rs1.read_full_acc_row)
node _a_garbage_T_2 = andr(a_address_rs1.data)
node _a_garbage_T_3 = and(_a_garbage_T_1, _a_garbage_T_2)
node _a_garbage_T_4 = bits(a_address_rs1.garbage_bit, 0, 0)
node _a_garbage_T_5 = and(_a_garbage_T_3, _a_garbage_T_4)
node _a_garbage_T_6 = eq(start_inputting_a, UInt<1>(0h0))
node a_garbage = or(_a_garbage_T_5, _a_garbage_T_6)
node _b_garbage_T = and(b_address_rs2.is_acc_addr, b_address_rs2.accumulate)
node _b_garbage_T_1 = and(_b_garbage_T, b_address_rs2.read_full_acc_row)
node _b_garbage_T_2 = andr(b_address_rs2.data)
node _b_garbage_T_3 = and(_b_garbage_T_1, _b_garbage_T_2)
node _b_garbage_T_4 = bits(b_address_rs2.garbage_bit, 0, 0)
node _b_garbage_T_5 = and(_b_garbage_T_3, _b_garbage_T_4)
node _b_garbage_T_6 = eq(start_inputting_b, UInt<1>(0h0))
node b_garbage = or(_b_garbage_T_5, _b_garbage_T_6)
node _d_garbage_T = and(d_address_rs1.is_acc_addr, d_address_rs1.accumulate)
node _d_garbage_T_1 = and(_d_garbage_T, d_address_rs1.read_full_acc_row)
node _d_garbage_T_2 = andr(d_address_rs1.data)
node _d_garbage_T_3 = and(_d_garbage_T_1, _d_garbage_T_2)
node _d_garbage_T_4 = bits(d_address_rs1.garbage_bit, 0, 0)
node _d_garbage_T_5 = and(_d_garbage_T_3, _d_garbage_T_4)
node _d_garbage_T_6 = eq(start_inputting_d, UInt<1>(0h0))
node d_garbage = or(_d_garbage_T_5, _d_garbage_T_6)
regreset perform_single_preload : UInt<1>, clock, reset, UInt<1>(0h0)
regreset perform_single_mul : UInt<1>, clock, reset, UInt<1>(0h0)
regreset perform_mul_pre : UInt<1>, clock, reset, UInt<1>(0h0)
node _performing_single_preload_T = eq(control_state, UInt<2>(0h1))
node _performing_single_preload_T_1 = and(perform_single_preload, _performing_single_preload_T)
wire performing_single_preload : UInt<1>
connect performing_single_preload, _performing_single_preload_T_1
node _performing_single_mul_T = eq(control_state, UInt<2>(0h1))
node _performing_single_mul_T_1 = and(perform_single_mul, _performing_single_mul_T)
wire performing_single_mul : UInt<1>
connect performing_single_mul, _performing_single_mul_T_1
node _performing_mul_pre_T = eq(control_state, UInt<2>(0h1))
node _performing_mul_pre_T_1 = and(perform_mul_pre, _performing_mul_pre_T)
wire performing_mul_pre : UInt<1>
connect performing_mul_pre, _performing_mul_pre_T_1
wire total_rows : UInt
connect total_rows, UInt<3>(0h4)
node _T_9 = eq(current_dataflow, UInt<1>(0h1))
node _T_10 = and(_T_9, d_garbage)
node _T_11 = eq(a_should_be_fed_into_transposer, UInt<1>(0h0))
node _T_12 = and(_T_10, _T_11)
node _T_13 = eq(b_should_be_fed_into_transposer, UInt<1>(0h0))
node _T_14 = and(_T_12, _T_13)
node _T_15 = eq(d_should_be_fed_into_transposer, UInt<1>(0h0))
node _T_16 = and(_T_14, _T_15)
when _T_16 :
node rows_a = mux(a_garbage, UInt<1>(0h1), a_rows)
node rows_b = mux(b_garbage, UInt<1>(0h1), b_rows)
node _total_rows_T = gt(rows_a, rows_b)
node _total_rows_T_1 = mux(_total_rows_T, rows_a, rows_b)
node _total_rows_T_2 = gt(_total_rows_T_1, UInt<3>(0h4))
node _total_rows_T_3 = mux(_total_rows_T_2, _total_rows_T_1, UInt<3>(0h4))
connect total_rows, _total_rows_T_3
regreset mul_pre_counter_sub : UInt<3>, clock, reset, UInt<3>(0h0)
regreset mul_pre_counter_count : UInt<3>, clock, reset, UInt<3>(0h0)
regreset mul_pre_counter_lock : UInt<1>, clock, reset, UInt<1>(0h0)
node a_row_is_not_all_zeros = lt(a_fire_counter, a_rows)
node b_row_is_not_all_zeros = lt(b_fire_counter, b_rows)
node _d_row_is_not_all_zeros_T = sub(UInt<3>(0h4), UInt<1>(0h1))
node _d_row_is_not_all_zeros_T_1 = tail(_d_row_is_not_all_zeros_T, 1)
node _d_row_is_not_all_zeros_T_2 = sub(_d_row_is_not_all_zeros_T_1, d_fire_counter)
node _d_row_is_not_all_zeros_T_3 = tail(_d_row_is_not_all_zeros_T_2, 1)
node d_row_is_not_all_zeros = lt(_d_row_is_not_all_zeros_T_3, d_rows)
wire a_ready : UInt<1>
connect a_ready, UInt<1>(0h1)
wire b_ready : UInt<1>
connect b_ready, UInt<1>(0h1)
wire d_ready : UInt<1>
connect d_ready, UInt<1>(0h1)
node _T_17 = and(a_address_rs1.is_acc_addr, a_address_rs1.accumulate)
node _T_18 = and(_T_17, a_address_rs1.read_full_acc_row)
node _T_19 = andr(a_address_rs1.data)
node _T_20 = and(_T_18, _T_19)
node _T_21 = bits(a_address_rs1.garbage_bit, 0, 0)
node _T_22 = and(_T_20, _T_21)
node _done_T = eq(a_fire_counter, UInt<1>(0h0))
node done = and(_done_T, a_fire_started)
node _T_23 = and(b_address_rs2.is_acc_addr, b_address_rs2.accumulate)
node _T_24 = and(_T_23, b_address_rs2.read_full_acc_row)
node _T_25 = andr(b_address_rs2.data)
node _T_26 = and(_T_24, _T_25)
node _T_27 = bits(b_address_rs2.garbage_bit, 0, 0)
node _T_28 = and(_T_26, _T_27)
node _done_T_1 = eq(b_fire_counter, UInt<1>(0h0))
node done_1 = and(_done_T_1, b_fire_started)
node _T_29 = and(d_address_rs1.is_acc_addr, d_address_rs1.accumulate)
node _T_30 = and(_T_29, d_address_rs1.read_full_acc_row)
node _T_31 = andr(d_address_rs1.data)
node _T_32 = and(_T_30, _T_31)
node _T_33 = bits(d_address_rs1.garbage_bit, 0, 0)
node _T_34 = and(_T_32, _T_33)
node _done_T_2 = eq(d_fire_counter, UInt<1>(0h0))
node done_2 = and(_done_T_2, d_fire_started)
node _same_banks_is_garbage_T = or(_T_22, _T_28)
node _same_banks_is_garbage_T_1 = eq(start_inputting_a, UInt<1>(0h0))
node _same_banks_is_garbage_T_2 = or(_same_banks_is_garbage_T, _same_banks_is_garbage_T_1)
node _same_banks_is_garbage_T_3 = eq(start_inputting_b, UInt<1>(0h0))
node same_banks_is_garbage = or(_same_banks_is_garbage_T_2, _same_banks_is_garbage_T_3)
node _same_banks_is_being_im2colled_T = and(UInt<1>(0h1), io.im2col.req.ready)
node same_banks_is_being_im2colled = and(_same_banks_is_being_im2colled_T, im2col_en)
node _same_banks_T = eq(same_banks_is_garbage, UInt<1>(0h0))
node _same_banks_T_1 = eq(same_banks_is_being_im2colled, UInt<1>(0h0))
node _same_banks_T_2 = and(_same_banks_T, _same_banks_T_1)
node _same_banks_T_3 = and(a_address.is_acc_addr, b_address.is_acc_addr)
node _same_banks_T_4 = eq(a_address.is_acc_addr, UInt<1>(0h0))
node _same_banks_T_5 = eq(b_address.is_acc_addr, UInt<1>(0h0))
node _same_banks_T_6 = and(_same_banks_T_4, _same_banks_T_5)
node _same_banks_T_7 = bits(a_address.data, 13, 12)
node _same_banks_T_8 = bits(b_address.data, 13, 12)
node _same_banks_T_9 = eq(_same_banks_T_7, _same_banks_T_8)
node _same_banks_T_10 = and(_same_banks_T_6, _same_banks_T_9)
node _same_banks_T_11 = or(_same_banks_T_3, _same_banks_T_10)
node same_banks_0 = and(_same_banks_T_2, _same_banks_T_11)
node _same_banks_is_garbage_T_4 = or(_T_22, _T_34)
node _same_banks_is_garbage_T_5 = eq(start_inputting_a, UInt<1>(0h0))
node _same_banks_is_garbage_T_6 = or(_same_banks_is_garbage_T_4, _same_banks_is_garbage_T_5)
node _same_banks_is_garbage_T_7 = eq(start_inputting_d, UInt<1>(0h0))
node same_banks_is_garbage_1 = or(_same_banks_is_garbage_T_6, _same_banks_is_garbage_T_7)
node _same_banks_is_being_im2colled_T_1 = and(UInt<1>(0h1), io.im2col.req.ready)
node same_banks_is_being_im2colled_1 = and(_same_banks_is_being_im2colled_T_1, im2col_en)
node _same_banks_T_12 = eq(same_banks_is_garbage_1, UInt<1>(0h0))
node _same_banks_T_13 = eq(same_banks_is_being_im2colled_1, UInt<1>(0h0))
node _same_banks_T_14 = and(_same_banks_T_12, _same_banks_T_13)
node _same_banks_T_15 = and(a_address.is_acc_addr, d_address.is_acc_addr)
node _same_banks_T_16 = eq(a_address.is_acc_addr, UInt<1>(0h0))
node _same_banks_T_17 = eq(d_address.is_acc_addr, UInt<1>(0h0))
node _same_banks_T_18 = and(_same_banks_T_16, _same_banks_T_17)
node _same_banks_T_19 = bits(a_address.data, 13, 12)
node _same_banks_T_20 = bits(d_address.data, 13, 12)
node _same_banks_T_21 = eq(_same_banks_T_19, _same_banks_T_20)
node _same_banks_T_22 = and(_same_banks_T_18, _same_banks_T_21)
node _same_banks_T_23 = or(_same_banks_T_15, _same_banks_T_22)
node same_banks_1 = and(_same_banks_T_14, _same_banks_T_23)
node _same_counter_T = eq(a_fire_started, b_fire_started)
node _same_counter_T_1 = eq(a_fire_counter, b_fire_counter)
node same_counter_0 = and(_same_counter_T, _same_counter_T_1)
node _same_counter_T_2 = eq(a_fire_started, d_fire_started)
node _same_counter_T_3 = eq(a_fire_counter, d_fire_counter)
node same_counter_1 = and(_same_counter_T_2, _same_counter_T_3)
node _one_ahead_max_T = sub(total_rows, UInt<1>(0h1))
node one_ahead_max = tail(_one_ahead_max_T, 1)
node _one_ahead_T = leq(UInt<1>(0h1), one_ahead_max)
node _one_ahead_T_1 = eq(one_ahead_max, UInt<1>(0h0))
node _one_ahead_T_2 = or(_one_ahead_T, _one_ahead_T_1)
node _one_ahead_T_3 = asUInt(reset)
node _one_ahead_T_4 = eq(_one_ahead_T_3, UInt<1>(0h0))
when _one_ahead_T_4 :
node _one_ahead_T_5 = eq(_one_ahead_T_2, UInt<1>(0h0))
when _one_ahead_T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed: cannot wrapAdd when n is larger than max, unless max is 0\n at Util.scala:19 assert(n <= max || max === 0.U, \"cannot wrapAdd when n is larger than max, unless max is 0\")\n") : one_ahead_printf
assert(clock, _one_ahead_T_2, UInt<1>(0h1), "") : one_ahead_assert
node _one_ahead_T_6 = add(b_fire_counter, UInt<1>(0h1))
node _one_ahead_T_7 = tail(_one_ahead_T_6, 1)
node _one_ahead_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _one_ahead_T_9 = eq(one_ahead_max, UInt<1>(0h0))
node _one_ahead_T_10 = sub(one_ahead_max, UInt<1>(0h1))
node _one_ahead_T_11 = tail(_one_ahead_T_10, 1)
node _one_ahead_T_12 = add(_one_ahead_T_11, UInt<1>(0h1))
node _one_ahead_T_13 = tail(_one_ahead_T_12, 1)
node _one_ahead_T_14 = geq(b_fire_counter, _one_ahead_T_13)
node _one_ahead_T_15 = neq(UInt<1>(0h1), UInt<1>(0h0))
node _one_ahead_T_16 = and(_one_ahead_T_14, _one_ahead_T_15)
node _one_ahead_T_17 = sub(one_ahead_max, b_fire_counter)
node _one_ahead_T_18 = tail(_one_ahead_T_17, 1)
node _one_ahead_T_19 = sub(UInt<1>(0h1), _one_ahead_T_18)
node _one_ahead_T_20 = tail(_one_ahead_T_19, 1)
node _one_ahead_T_21 = sub(_one_ahead_T_20, UInt<1>(0h1))
node _one_ahead_T_22 = tail(_one_ahead_T_21, 1)
node _one_ahead_T_23 = mux(_one_ahead_T_16, _one_ahead_T_22, _one_ahead_T_7)
node _one_ahead_T_24 = mux(_one_ahead_T_9, UInt<1>(0h0), _one_ahead_T_23)
node _one_ahead_T_25 = mux(_one_ahead_T_8, b_fire_counter, _one_ahead_T_24)
node _one_ahead_T_26 = eq(a_fire_counter, _one_ahead_T_25)
node one_ahead_0 = and(a_fire_started, _one_ahead_T_26)
node _one_ahead_max_T_1 = sub(total_rows, UInt<1>(0h1))
node one_ahead_max_1 = tail(_one_ahead_max_T_1, 1)
node _one_ahead_T_27 = leq(UInt<1>(0h1), one_ahead_max_1)
node _one_ahead_T_28 = eq(one_ahead_max_1, UInt<1>(0h0))
node _one_ahead_T_29 = or(_one_ahead_T_27, _one_ahead_T_28)
node _one_ahead_T_30 = asUInt(reset)
node _one_ahead_T_31 = eq(_one_ahead_T_30, UInt<1>(0h0))
when _one_ahead_T_31 :
node _one_ahead_T_32 = eq(_one_ahead_T_29, UInt<1>(0h0))
when _one_ahead_T_32 :
printf(clock, UInt<1>(0h1), "Assertion failed: cannot wrapAdd when n is larger than max, unless max is 0\n at Util.scala:19 assert(n <= max || max === 0.U, \"cannot wrapAdd when n is larger than max, unless max is 0\")\n") : one_ahead_printf_1
assert(clock, _one_ahead_T_29, UInt<1>(0h1), "") : one_ahead_assert_1
node _one_ahead_T_33 = add(d_fire_counter, UInt<1>(0h1))
node _one_ahead_T_34 = tail(_one_ahead_T_33, 1)
node _one_ahead_T_35 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _one_ahead_T_36 = eq(one_ahead_max_1, UInt<1>(0h0))
node _one_ahead_T_37 = sub(one_ahead_max_1, UInt<1>(0h1))
node _one_ahead_T_38 = tail(_one_ahead_T_37, 1)
node _one_ahead_T_39 = add(_one_ahead_T_38, UInt<1>(0h1))
node _one_ahead_T_40 = tail(_one_ahead_T_39, 1)
node _one_ahead_T_41 = geq(d_fire_counter, _one_ahead_T_40)
node _one_ahead_T_42 = neq(UInt<1>(0h1), UInt<1>(0h0))
node _one_ahead_T_43 = and(_one_ahead_T_41, _one_ahead_T_42)
node _one_ahead_T_44 = sub(one_ahead_max_1, d_fire_counter)
node _one_ahead_T_45 = tail(_one_ahead_T_44, 1)
node _one_ahead_T_46 = sub(UInt<1>(0h1), _one_ahead_T_45)
node _one_ahead_T_47 = tail(_one_ahead_T_46, 1)
node _one_ahead_T_48 = sub(_one_ahead_T_47, UInt<1>(0h1))
node _one_ahead_T_49 = tail(_one_ahead_T_48, 1)
node _one_ahead_T_50 = mux(_one_ahead_T_43, _one_ahead_T_49, _one_ahead_T_34)
node _one_ahead_T_51 = mux(_one_ahead_T_36, UInt<1>(0h0), _one_ahead_T_50)
node _one_ahead_T_52 = mux(_one_ahead_T_35, d_fire_counter, _one_ahead_T_51)
node _one_ahead_T_53 = eq(a_fire_counter, _one_ahead_T_52)
node one_ahead_1 = and(a_fire_started, _one_ahead_T_53)
node _must_wait_for_T = and(same_banks_0, UInt<1>(0h0))
node _must_wait_for_T_1 = and(_must_wait_for_T, same_counter_0)
node must_wait_for_0 = or(_must_wait_for_T_1, one_ahead_0)
node _must_wait_for_T_2 = and(same_banks_1, UInt<1>(0h0))
node _must_wait_for_T_3 = and(_must_wait_for_T_2, same_counter_1)
node must_wait_for_1 = or(_must_wait_for_T_3, one_ahead_1)
node _T_35 = or(must_wait_for_0, must_wait_for_1)
node a_valid = eq(_T_35, UInt<1>(0h0))
node _same_banks_is_garbage_T_8 = or(_T_28, _T_22)
node _same_banks_is_garbage_T_9 = eq(start_inputting_b, UInt<1>(0h0))
node _same_banks_is_garbage_T_10 = or(_same_banks_is_garbage_T_8, _same_banks_is_garbage_T_9)
node _same_banks_is_garbage_T_11 = eq(start_inputting_a, UInt<1>(0h0))
node same_banks_is_garbage_2 = or(_same_banks_is_garbage_T_10, _same_banks_is_garbage_T_11)
node _same_banks_is_being_im2colled_T_2 = and(UInt<1>(0h1), io.im2col.req.ready)
node same_banks_is_being_im2colled_2 = and(_same_banks_is_being_im2colled_T_2, im2col_en)
node _same_banks_T_24 = eq(same_banks_is_garbage_2, UInt<1>(0h0))
node _same_banks_T_25 = eq(same_banks_is_being_im2colled_2, UInt<1>(0h0))
node _same_banks_T_26 = and(_same_banks_T_24, _same_banks_T_25)
node _same_banks_T_27 = and(b_address.is_acc_addr, a_address.is_acc_addr)
node _same_banks_T_28 = eq(b_address.is_acc_addr, UInt<1>(0h0))
node _same_banks_T_29 = eq(a_address.is_acc_addr, UInt<1>(0h0))
node _same_banks_T_30 = and(_same_banks_T_28, _same_banks_T_29)
node _same_banks_T_31 = bits(b_address.data, 13, 12)
node _same_banks_T_32 = bits(a_address.data, 13, 12)
node _same_banks_T_33 = eq(_same_banks_T_31, _same_banks_T_32)
node _same_banks_T_34 = and(_same_banks_T_30, _same_banks_T_33)
node _same_banks_T_35 = or(_same_banks_T_27, _same_banks_T_34)
node same_banks_0_1 = and(_same_banks_T_26, _same_banks_T_35)
node _same_banks_is_garbage_T_12 = or(_T_28, _T_34)
node _same_banks_is_garbage_T_13 = eq(start_inputting_b, UInt<1>(0h0))
node _same_banks_is_garbage_T_14 = or(_same_banks_is_garbage_T_12, _same_banks_is_garbage_T_13)
node _same_banks_is_garbage_T_15 = eq(start_inputting_d, UInt<1>(0h0))
node same_banks_is_garbage_3 = or(_same_banks_is_garbage_T_14, _same_banks_is_garbage_T_15)
node _same_banks_is_being_im2colled_T_3 = and(UInt<1>(0h0), io.im2col.req.ready)
node same_banks_is_being_im2colled_3 = and(_same_banks_is_being_im2colled_T_3, im2col_en)
node _same_banks_T_36 = eq(same_banks_is_garbage_3, UInt<1>(0h0))
node _same_banks_T_37 = eq(same_banks_is_being_im2colled_3, UInt<1>(0h0))
node _same_banks_T_38 = and(_same_banks_T_36, _same_banks_T_37)
node _same_banks_T_39 = and(b_address.is_acc_addr, d_address.is_acc_addr)
node _same_banks_T_40 = eq(b_address.is_acc_addr, UInt<1>(0h0))
node _same_banks_T_41 = eq(d_address.is_acc_addr, UInt<1>(0h0))
node _same_banks_T_42 = and(_same_banks_T_40, _same_banks_T_41)
node _same_banks_T_43 = bits(b_address.data, 13, 12)
node _same_banks_T_44 = bits(d_address.data, 13, 12)
node _same_banks_T_45 = eq(_same_banks_T_43, _same_banks_T_44)
node _same_banks_T_46 = and(_same_banks_T_42, _same_banks_T_45)
node _same_banks_T_47 = or(_same_banks_T_39, _same_banks_T_46)
node same_banks_1_1 = and(_same_banks_T_38, _same_banks_T_47)
node _same_counter_T_4 = eq(b_fire_started, a_fire_started)
node _same_counter_T_5 = eq(b_fire_counter, a_fire_counter)
node same_counter_0_1 = and(_same_counter_T_4, _same_counter_T_5)
node _same_counter_T_6 = eq(b_fire_started, d_fire_started)
node _same_counter_T_7 = eq(b_fire_counter, d_fire_counter)
node same_counter_1_1 = and(_same_counter_T_6, _same_counter_T_7)
node _one_ahead_max_T_2 = sub(total_rows, UInt<1>(0h1))
node one_ahead_max_2 = tail(_one_ahead_max_T_2, 1)
node _one_ahead_T_54 = leq(UInt<1>(0h1), one_ahead_max_2)
node _one_ahead_T_55 = eq(one_ahead_max_2, UInt<1>(0h0))
node _one_ahead_T_56 = or(_one_ahead_T_54, _one_ahead_T_55)
node _one_ahead_T_57 = asUInt(reset)
node _one_ahead_T_58 = eq(_one_ahead_T_57, UInt<1>(0h0))
when _one_ahead_T_58 :
node _one_ahead_T_59 = eq(_one_ahead_T_56, UInt<1>(0h0))
when _one_ahead_T_59 :
printf(clock, UInt<1>(0h1), "Assertion failed: cannot wrapAdd when n is larger than max, unless max is 0\n at Util.scala:19 assert(n <= max || max === 0.U, \"cannot wrapAdd when n is larger than max, unless max is 0\")\n") : one_ahead_printf_2
assert(clock, _one_ahead_T_56, UInt<1>(0h1), "") : one_ahead_assert_2
node _one_ahead_T_60 = add(a_fire_counter, UInt<1>(0h1))
node _one_ahead_T_61 = tail(_one_ahead_T_60, 1)
node _one_ahead_T_62 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _one_ahead_T_63 = eq(one_ahead_max_2, UInt<1>(0h0))
node _one_ahead_T_64 = sub(one_ahead_max_2, UInt<1>(0h1))
node _one_ahead_T_65 = tail(_one_ahead_T_64, 1)
node _one_ahead_T_66 = add(_one_ahead_T_65, UInt<1>(0h1))
node _one_ahead_T_67 = tail(_one_ahead_T_66, 1)
node _one_ahead_T_68 = geq(a_fire_counter, _one_ahead_T_67)
node _one_ahead_T_69 = neq(UInt<1>(0h1), UInt<1>(0h0))
node _one_ahead_T_70 = and(_one_ahead_T_68, _one_ahead_T_69)
node _one_ahead_T_71 = sub(one_ahead_max_2, a_fire_counter)
node _one_ahead_T_72 = tail(_one_ahead_T_71, 1)
node _one_ahead_T_73 = sub(UInt<1>(0h1), _one_ahead_T_72)
node _one_ahead_T_74 = tail(_one_ahead_T_73, 1)
node _one_ahead_T_75 = sub(_one_ahead_T_74, UInt<1>(0h1))
node _one_ahead_T_76 = tail(_one_ahead_T_75, 1)
node _one_ahead_T_77 = mux(_one_ahead_T_70, _one_ahead_T_76, _one_ahead_T_61)
node _one_ahead_T_78 = mux(_one_ahead_T_63, UInt<1>(0h0), _one_ahead_T_77)
node _one_ahead_T_79 = mux(_one_ahead_T_62, a_fire_counter, _one_ahead_T_78)
node _one_ahead_T_80 = eq(b_fire_counter, _one_ahead_T_79)
node one_ahead_0_1 = and(b_fire_started, _one_ahead_T_80)
node _one_ahead_max_T_3 = sub(total_rows, UInt<1>(0h1))
node one_ahead_max_3 = tail(_one_ahead_max_T_3, 1)
node _one_ahead_T_81 = leq(UInt<1>(0h1), one_ahead_max_3)
node _one_ahead_T_82 = eq(one_ahead_max_3, UInt<1>(0h0))
node _one_ahead_T_83 = or(_one_ahead_T_81, _one_ahead_T_82)
node _one_ahead_T_84 = asUInt(reset)
node _one_ahead_T_85 = eq(_one_ahead_T_84, UInt<1>(0h0))
when _one_ahead_T_85 :
node _one_ahead_T_86 = eq(_one_ahead_T_83, UInt<1>(0h0))
when _one_ahead_T_86 :
printf(clock, UInt<1>(0h1), "Assertion failed: cannot wrapAdd when n is larger than max, unless max is 0\n at Util.scala:19 assert(n <= max || max === 0.U, \"cannot wrapAdd when n is larger than max, unless max is 0\")\n") : one_ahead_printf_3
assert(clock, _one_ahead_T_83, UInt<1>(0h1), "") : one_ahead_assert_3
node _one_ahead_T_87 = add(d_fire_counter, UInt<1>(0h1))
node _one_ahead_T_88 = tail(_one_ahead_T_87, 1)
node _one_ahead_T_89 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _one_ahead_T_90 = eq(one_ahead_max_3, UInt<1>(0h0))
node _one_ahead_T_91 = sub(one_ahead_max_3, UInt<1>(0h1))
node _one_ahead_T_92 = tail(_one_ahead_T_91, 1)
node _one_ahead_T_93 = add(_one_ahead_T_92, UInt<1>(0h1))
node _one_ahead_T_94 = tail(_one_ahead_T_93, 1)
node _one_ahead_T_95 = geq(d_fire_counter, _one_ahead_T_94)
node _one_ahead_T_96 = neq(UInt<1>(0h1), UInt<1>(0h0))
node _one_ahead_T_97 = and(_one_ahead_T_95, _one_ahead_T_96)
node _one_ahead_T_98 = sub(one_ahead_max_3, d_fire_counter)
node _one_ahead_T_99 = tail(_one_ahead_T_98, 1)
node _one_ahead_T_100 = sub(UInt<1>(0h1), _one_ahead_T_99)
node _one_ahead_T_101 = tail(_one_ahead_T_100, 1)
node _one_ahead_T_102 = sub(_one_ahead_T_101, UInt<1>(0h1))
node _one_ahead_T_103 = tail(_one_ahead_T_102, 1)
node _one_ahead_T_104 = mux(_one_ahead_T_97, _one_ahead_T_103, _one_ahead_T_88)
node _one_ahead_T_105 = mux(_one_ahead_T_90, UInt<1>(0h0), _one_ahead_T_104)
node _one_ahead_T_106 = mux(_one_ahead_T_89, d_fire_counter, _one_ahead_T_105)
node _one_ahead_T_107 = eq(b_fire_counter, _one_ahead_T_106)
node one_ahead_1_1 = and(b_fire_started, _one_ahead_T_107)
node _must_wait_for_T_4 = and(same_banks_0_1, UInt<1>(0h1))
node _must_wait_for_T_5 = and(_must_wait_for_T_4, same_counter_0_1)
node must_wait_for_0_1 = or(_must_wait_for_T_5, one_ahead_0_1)
node _must_wait_for_T_6 = and(same_banks_1_1, UInt<1>(0h0))
node _must_wait_for_T_7 = and(_must_wait_for_T_6, same_counter_1_1)
node must_wait_for_1_1 = or(_must_wait_for_T_7, one_ahead_1_1)
node _T_36 = or(must_wait_for_0_1, must_wait_for_1_1)
node b_valid = eq(_T_36, UInt<1>(0h0))
node _same_banks_is_garbage_T_16 = or(_T_34, _T_22)
node _same_banks_is_garbage_T_17 = eq(start_inputting_d, UInt<1>(0h0))
node _same_banks_is_garbage_T_18 = or(_same_banks_is_garbage_T_16, _same_banks_is_garbage_T_17)
node _same_banks_is_garbage_T_19 = eq(start_inputting_a, UInt<1>(0h0))
node same_banks_is_garbage_4 = or(_same_banks_is_garbage_T_18, _same_banks_is_garbage_T_19)
node _same_banks_is_being_im2colled_T_4 = and(UInt<1>(0h1), io.im2col.req.ready)
node same_banks_is_being_im2colled_4 = and(_same_banks_is_being_im2colled_T_4, im2col_en)
node _same_banks_T_48 = eq(same_banks_is_garbage_4, UInt<1>(0h0))
node _same_banks_T_49 = eq(same_banks_is_being_im2colled_4, UInt<1>(0h0))
node _same_banks_T_50 = and(_same_banks_T_48, _same_banks_T_49)
node _same_banks_T_51 = and(d_address.is_acc_addr, a_address.is_acc_addr)
node _same_banks_T_52 = eq(d_address.is_acc_addr, UInt<1>(0h0))
node _same_banks_T_53 = eq(a_address.is_acc_addr, UInt<1>(0h0))
node _same_banks_T_54 = and(_same_banks_T_52, _same_banks_T_53)
node _same_banks_T_55 = bits(d_address.data, 13, 12)
node _same_banks_T_56 = bits(a_address.data, 13, 12)
node _same_banks_T_57 = eq(_same_banks_T_55, _same_banks_T_56)
node _same_banks_T_58 = and(_same_banks_T_54, _same_banks_T_57)
node _same_banks_T_59 = or(_same_banks_T_51, _same_banks_T_58)
node same_banks_0_2 = and(_same_banks_T_50, _same_banks_T_59)
node _same_banks_is_garbage_T_20 = or(_T_34, _T_28)
node _same_banks_is_garbage_T_21 = eq(start_inputting_d, UInt<1>(0h0))
node _same_banks_is_garbage_T_22 = or(_same_banks_is_garbage_T_20, _same_banks_is_garbage_T_21)
node _same_banks_is_garbage_T_23 = eq(start_inputting_b, UInt<1>(0h0))
node same_banks_is_garbage_5 = or(_same_banks_is_garbage_T_22, _same_banks_is_garbage_T_23)
node _same_banks_is_being_im2colled_T_5 = and(UInt<1>(0h0), io.im2col.req.ready)
node same_banks_is_being_im2colled_5 = and(_same_banks_is_being_im2colled_T_5, im2col_en)
node _same_banks_T_60 = eq(same_banks_is_garbage_5, UInt<1>(0h0))
node _same_banks_T_61 = eq(same_banks_is_being_im2colled_5, UInt<1>(0h0))
node _same_banks_T_62 = and(_same_banks_T_60, _same_banks_T_61)
node _same_banks_T_63 = and(d_address.is_acc_addr, b_address.is_acc_addr)
node _same_banks_T_64 = eq(d_address.is_acc_addr, UInt<1>(0h0))
node _same_banks_T_65 = eq(b_address.is_acc_addr, UInt<1>(0h0))
node _same_banks_T_66 = and(_same_banks_T_64, _same_banks_T_65)
node _same_banks_T_67 = bits(d_address.data, 13, 12)
node _same_banks_T_68 = bits(b_address.data, 13, 12)
node _same_banks_T_69 = eq(_same_banks_T_67, _same_banks_T_68)
node _same_banks_T_70 = and(_same_banks_T_66, _same_banks_T_69)
node _same_banks_T_71 = or(_same_banks_T_63, _same_banks_T_70)
node same_banks_1_2 = and(_same_banks_T_62, _same_banks_T_71)
node _same_counter_T_8 = eq(d_fire_started, a_fire_started)
node _same_counter_T_9 = eq(d_fire_counter, a_fire_counter)
node same_counter_0_2 = and(_same_counter_T_8, _same_counter_T_9)
node _same_counter_T_10 = eq(d_fire_started, b_fire_started)
node _same_counter_T_11 = eq(d_fire_counter, b_fire_counter)
node same_counter_1_2 = and(_same_counter_T_10, _same_counter_T_11)
node _one_ahead_max_T_4 = sub(total_rows, UInt<1>(0h1))
node one_ahead_max_4 = tail(_one_ahead_max_T_4, 1)
node _one_ahead_T_108 = leq(UInt<1>(0h1), one_ahead_max_4)
node _one_ahead_T_109 = eq(one_ahead_max_4, UInt<1>(0h0))
node _one_ahead_T_110 = or(_one_ahead_T_108, _one_ahead_T_109)
node _one_ahead_T_111 = asUInt(reset)
node _one_ahead_T_112 = eq(_one_ahead_T_111, UInt<1>(0h0))
when _one_ahead_T_112 :
node _one_ahead_T_113 = eq(_one_ahead_T_110, UInt<1>(0h0))
when _one_ahead_T_113 :
printf(clock, UInt<1>(0h1), "Assertion failed: cannot wrapAdd when n is larger than max, unless max is 0\n at Util.scala:19 assert(n <= max || max === 0.U, \"cannot wrapAdd when n is larger than max, unless max is 0\")\n") : one_ahead_printf_4
assert(clock, _one_ahead_T_110, UInt<1>(0h1), "") : one_ahead_assert_4
node _one_ahead_T_114 = add(a_fire_counter, UInt<1>(0h1))
node _one_ahead_T_115 = tail(_one_ahead_T_114, 1)
node _one_ahead_T_116 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _one_ahead_T_117 = eq(one_ahead_max_4, UInt<1>(0h0))
node _one_ahead_T_118 = sub(one_ahead_max_4, UInt<1>(0h1))
node _one_ahead_T_119 = tail(_one_ahead_T_118, 1)
node _one_ahead_T_120 = add(_one_ahead_T_119, UInt<1>(0h1))
node _one_ahead_T_121 = tail(_one_ahead_T_120, 1)
node _one_ahead_T_122 = geq(a_fire_counter, _one_ahead_T_121)
node _one_ahead_T_123 = neq(UInt<1>(0h1), UInt<1>(0h0))
node _one_ahead_T_124 = and(_one_ahead_T_122, _one_ahead_T_123)
node _one_ahead_T_125 = sub(one_ahead_max_4, a_fire_counter)
node _one_ahead_T_126 = tail(_one_ahead_T_125, 1)
node _one_ahead_T_127 = sub(UInt<1>(0h1), _one_ahead_T_126)
node _one_ahead_T_128 = tail(_one_ahead_T_127, 1)
node _one_ahead_T_129 = sub(_one_ahead_T_128, UInt<1>(0h1))
node _one_ahead_T_130 = tail(_one_ahead_T_129, 1)
node _one_ahead_T_131 = mux(_one_ahead_T_124, _one_ahead_T_130, _one_ahead_T_115)
node _one_ahead_T_132 = mux(_one_ahead_T_117, UInt<1>(0h0), _one_ahead_T_131)
node _one_ahead_T_133 = mux(_one_ahead_T_116, a_fire_counter, _one_ahead_T_132)
node _one_ahead_T_134 = eq(d_fire_counter, _one_ahead_T_133)
node one_ahead_0_2 = and(d_fire_started, _one_ahead_T_134)
node _one_ahead_max_T_5 = sub(total_rows, UInt<1>(0h1))
node one_ahead_max_5 = tail(_one_ahead_max_T_5, 1)
node _one_ahead_T_135 = leq(UInt<1>(0h1), one_ahead_max_5)
node _one_ahead_T_136 = eq(one_ahead_max_5, UInt<1>(0h0))
node _one_ahead_T_137 = or(_one_ahead_T_135, _one_ahead_T_136)
node _one_ahead_T_138 = asUInt(reset)
node _one_ahead_T_139 = eq(_one_ahead_T_138, UInt<1>(0h0))
when _one_ahead_T_139 :
node _one_ahead_T_140 = eq(_one_ahead_T_137, UInt<1>(0h0))
when _one_ahead_T_140 :
printf(clock, UInt<1>(0h1), "Assertion failed: cannot wrapAdd when n is larger than max, unless max is 0\n at Util.scala:19 assert(n <= max || max === 0.U, \"cannot wrapAdd when n is larger than max, unless max is 0\")\n") : one_ahead_printf_5
assert(clock, _one_ahead_T_137, UInt<1>(0h1), "") : one_ahead_assert_5
node _one_ahead_T_141 = add(b_fire_counter, UInt<1>(0h1))
node _one_ahead_T_142 = tail(_one_ahead_T_141, 1)
node _one_ahead_T_143 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _one_ahead_T_144 = eq(one_ahead_max_5, UInt<1>(0h0))
node _one_ahead_T_145 = sub(one_ahead_max_5, UInt<1>(0h1))
node _one_ahead_T_146 = tail(_one_ahead_T_145, 1)
node _one_ahead_T_147 = add(_one_ahead_T_146, UInt<1>(0h1))
node _one_ahead_T_148 = tail(_one_ahead_T_147, 1)
node _one_ahead_T_149 = geq(b_fire_counter, _one_ahead_T_148)
node _one_ahead_T_150 = neq(UInt<1>(0h1), UInt<1>(0h0))
node _one_ahead_T_151 = and(_one_ahead_T_149, _one_ahead_T_150)
node _one_ahead_T_152 = sub(one_ahead_max_5, b_fire_counter)
node _one_ahead_T_153 = tail(_one_ahead_T_152, 1)
node _one_ahead_T_154 = sub(UInt<1>(0h1), _one_ahead_T_153)
node _one_ahead_T_155 = tail(_one_ahead_T_154, 1)
node _one_ahead_T_156 = sub(_one_ahead_T_155, UInt<1>(0h1))
node _one_ahead_T_157 = tail(_one_ahead_T_156, 1)
node _one_ahead_T_158 = mux(_one_ahead_T_151, _one_ahead_T_157, _one_ahead_T_142)
node _one_ahead_T_159 = mux(_one_ahead_T_144, UInt<1>(0h0), _one_ahead_T_158)
node _one_ahead_T_160 = mux(_one_ahead_T_143, b_fire_counter, _one_ahead_T_159)
node _one_ahead_T_161 = eq(d_fire_counter, _one_ahead_T_160)
node one_ahead_1_2 = and(d_fire_started, _one_ahead_T_161)
node _must_wait_for_T_8 = and(same_banks_0_2, UInt<1>(0h1))
node _must_wait_for_T_9 = and(_must_wait_for_T_8, same_counter_0_2)
node must_wait_for_0_2 = or(_must_wait_for_T_9, one_ahead_0_2)
node _must_wait_for_T_10 = and(same_banks_1_2, UInt<1>(0h1))
node _must_wait_for_T_11 = and(_must_wait_for_T_10, same_counter_1_2)
node must_wait_for_1_2 = or(_must_wait_for_T_11, one_ahead_1_2)
node _T_37 = or(must_wait_for_0_2, must_wait_for_1_2)
node d_valid = eq(_T_37, UInt<1>(0h0))
node a_fire = and(a_valid, a_ready)
node b_fire = and(b_valid, b_ready)
node d_fire = and(d_valid, d_ready)
node _firing_T = or(start_inputting_a, start_inputting_b)
node firing = or(_firing_T, start_inputting_d)
node _T_38 = eq(firing, UInt<1>(0h0))
when _T_38 :
connect a_fire_counter, UInt<1>(0h0)
connect a_addr_offset, UInt<1>(0h0)
else :
node _T_39 = and(firing, a_fire)
node _T_40 = and(_T_39, mesh_cntl_signals_q.io.enq.ready)
when _T_40 :
node _a_fire_counter_max_T = sub(total_rows, UInt<1>(0h1))
node a_fire_counter_max = tail(_a_fire_counter_max_T, 1)
node _a_fire_counter_T = leq(UInt<1>(0h1), a_fire_counter_max)
node _a_fire_counter_T_1 = eq(a_fire_counter_max, UInt<1>(0h0))
node _a_fire_counter_T_2 = or(_a_fire_counter_T, _a_fire_counter_T_1)
node _a_fire_counter_T_3 = asUInt(reset)
node _a_fire_counter_T_4 = eq(_a_fire_counter_T_3, UInt<1>(0h0))
when _a_fire_counter_T_4 :
node _a_fire_counter_T_5 = eq(_a_fire_counter_T_2, UInt<1>(0h0))
when _a_fire_counter_T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed: cannot wrapAdd when n is larger than max, unless max is 0\n at Util.scala:19 assert(n <= max || max === 0.U, \"cannot wrapAdd when n is larger than max, unless max is 0\")\n") : a_fire_counter_printf
assert(clock, _a_fire_counter_T_2, UInt<1>(0h1), "") : a_fire_counter_assert
node _a_fire_counter_T_6 = add(a_fire_counter, UInt<1>(0h1))
node _a_fire_counter_T_7 = tail(_a_fire_counter_T_6, 1)
node _a_fire_counter_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _a_fire_counter_T_9 = eq(a_fire_counter_max, UInt<1>(0h0))
node _a_fire_counter_T_10 = sub(a_fire_counter_max, UInt<1>(0h1))
node _a_fire_counter_T_11 = tail(_a_fire_counter_T_10, 1)
node _a_fire_counter_T_12 = add(_a_fire_counter_T_11, UInt<1>(0h1))
node _a_fire_counter_T_13 = tail(_a_fire_counter_T_12, 1)
node _a_fire_counter_T_14 = geq(a_fire_counter, _a_fire_counter_T_13)
node _a_fire_counter_T_15 = neq(UInt<1>(0h1), UInt<1>(0h0))
node _a_fire_counter_T_16 = and(_a_fire_counter_T_14, _a_fire_counter_T_15)
node _a_fire_counter_T_17 = sub(a_fire_counter_max, a_fire_counter)
node _a_fire_counter_T_18 = tail(_a_fire_counter_T_17, 1)
node _a_fire_counter_T_19 = sub(UInt<1>(0h1), _a_fire_counter_T_18)
node _a_fire_counter_T_20 = tail(_a_fire_counter_T_19, 1)
node _a_fire_counter_T_21 = sub(_a_fire_counter_T_20, UInt<1>(0h1))
node _a_fire_counter_T_22 = tail(_a_fire_counter_T_21, 1)
node _a_fire_counter_T_23 = mux(_a_fire_counter_T_16, _a_fire_counter_T_22, _a_fire_counter_T_7)
node _a_fire_counter_T_24 = mux(_a_fire_counter_T_9, UInt<1>(0h0), _a_fire_counter_T_23)
node _a_fire_counter_T_25 = mux(_a_fire_counter_T_8, a_fire_counter, _a_fire_counter_T_24)
connect a_fire_counter, _a_fire_counter_T_25
node _a_addr_offset_T = sub(total_rows, UInt<1>(0h1))
node _a_addr_offset_T_1 = tail(_a_addr_offset_T, 1)
node _a_addr_offset_T_2 = eq(a_fire_counter, _a_addr_offset_T_1)
node _a_addr_offset_T_3 = add(a_addr_offset, a_addr_stride)
node _a_addr_offset_T_4 = tail(_a_addr_offset_T_3, 1)
node _a_addr_offset_T_5 = mux(_a_addr_offset_T_2, UInt<1>(0h0), _a_addr_offset_T_4)
connect a_addr_offset, _a_addr_offset_T_5
connect a_fire_started, UInt<1>(0h1)
node _T_41 = eq(firing, UInt<1>(0h0))
when _T_41 :
connect b_fire_counter, UInt<1>(0h0)
else :
node _T_42 = and(firing, b_fire)
node _T_43 = and(_T_42, mesh_cntl_signals_q.io.enq.ready)
when _T_43 :
node _b_fire_counter_max_T = sub(total_rows, UInt<1>(0h1))
node b_fire_counter_max = tail(_b_fire_counter_max_T, 1)
node _b_fire_counter_T = leq(UInt<1>(0h1), b_fire_counter_max)
node _b_fire_counter_T_1 = eq(b_fire_counter_max, UInt<1>(0h0))
node _b_fire_counter_T_2 = or(_b_fire_counter_T, _b_fire_counter_T_1)
node _b_fire_counter_T_3 = asUInt(reset)
node _b_fire_counter_T_4 = eq(_b_fire_counter_T_3, UInt<1>(0h0))
when _b_fire_counter_T_4 :
node _b_fire_counter_T_5 = eq(_b_fire_counter_T_2, UInt<1>(0h0))
when _b_fire_counter_T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed: cannot wrapAdd when n is larger than max, unless max is 0\n at Util.scala:19 assert(n <= max || max === 0.U, \"cannot wrapAdd when n is larger than max, unless max is 0\")\n") : b_fire_counter_printf
assert(clock, _b_fire_counter_T_2, UInt<1>(0h1), "") : b_fire_counter_assert
node _b_fire_counter_T_6 = add(b_fire_counter, UInt<1>(0h1))
node _b_fire_counter_T_7 = tail(_b_fire_counter_T_6, 1)
node _b_fire_counter_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _b_fire_counter_T_9 = eq(b_fire_counter_max, UInt<1>(0h0))
node _b_fire_counter_T_10 = sub(b_fire_counter_max, UInt<1>(0h1))
node _b_fire_counter_T_11 = tail(_b_fire_counter_T_10, 1)
node _b_fire_counter_T_12 = add(_b_fire_counter_T_11, UInt<1>(0h1))
node _b_fire_counter_T_13 = tail(_b_fire_counter_T_12, 1)
node _b_fire_counter_T_14 = geq(b_fire_counter, _b_fire_counter_T_13)
node _b_fire_counter_T_15 = neq(UInt<1>(0h1), UInt<1>(0h0))
node _b_fire_counter_T_16 = and(_b_fire_counter_T_14, _b_fire_counter_T_15)
node _b_fire_counter_T_17 = sub(b_fire_counter_max, b_fire_counter)
node _b_fire_counter_T_18 = tail(_b_fire_counter_T_17, 1)
node _b_fire_counter_T_19 = sub(UInt<1>(0h1), _b_fire_counter_T_18)
node _b_fire_counter_T_20 = tail(_b_fire_counter_T_19, 1)
node _b_fire_counter_T_21 = sub(_b_fire_counter_T_20, UInt<1>(0h1))
node _b_fire_counter_T_22 = tail(_b_fire_counter_T_21, 1)
node _b_fire_counter_T_23 = mux(_b_fire_counter_T_16, _b_fire_counter_T_22, _b_fire_counter_T_7)
node _b_fire_counter_T_24 = mux(_b_fire_counter_T_9, UInt<1>(0h0), _b_fire_counter_T_23)
node _b_fire_counter_T_25 = mux(_b_fire_counter_T_8, b_fire_counter, _b_fire_counter_T_24)
connect b_fire_counter, _b_fire_counter_T_25
connect b_fire_started, UInt<1>(0h1)
node _T_44 = eq(firing, UInt<1>(0h0))
when _T_44 :
connect d_fire_counter, UInt<1>(0h0)
else :
node _T_45 = and(firing, d_fire)
node _T_46 = and(_T_45, mesh_cntl_signals_q.io.enq.ready)
when _T_46 :
node _d_fire_counter_max_T = sub(total_rows, UInt<1>(0h1))
node d_fire_counter_max = tail(_d_fire_counter_max_T, 1)
node _d_fire_counter_T = leq(UInt<1>(0h1), d_fire_counter_max)
node _d_fire_counter_T_1 = eq(d_fire_counter_max, UInt<1>(0h0))
node _d_fire_counter_T_2 = or(_d_fire_counter_T, _d_fire_counter_T_1)
node _d_fire_counter_T_3 = asUInt(reset)
node _d_fire_counter_T_4 = eq(_d_fire_counter_T_3, UInt<1>(0h0))
when _d_fire_counter_T_4 :
node _d_fire_counter_T_5 = eq(_d_fire_counter_T_2, UInt<1>(0h0))
when _d_fire_counter_T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed: cannot wrapAdd when n is larger than max, unless max is 0\n at Util.scala:19 assert(n <= max || max === 0.U, \"cannot wrapAdd when n is larger than max, unless max is 0\")\n") : d_fire_counter_printf
assert(clock, _d_fire_counter_T_2, UInt<1>(0h1), "") : d_fire_counter_assert
node _d_fire_counter_T_6 = add(d_fire_counter, UInt<1>(0h1))
node _d_fire_counter_T_7 = tail(_d_fire_counter_T_6, 1)
node _d_fire_counter_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _d_fire_counter_T_9 = eq(d_fire_counter_max, UInt<1>(0h0))
node _d_fire_counter_T_10 = sub(d_fire_counter_max, UInt<1>(0h1))
node _d_fire_counter_T_11 = tail(_d_fire_counter_T_10, 1)
node _d_fire_counter_T_12 = add(_d_fire_counter_T_11, UInt<1>(0h1))
node _d_fire_counter_T_13 = tail(_d_fire_counter_T_12, 1)
node _d_fire_counter_T_14 = geq(d_fire_counter, _d_fire_counter_T_13)
node _d_fire_counter_T_15 = neq(UInt<1>(0h1), UInt<1>(0h0))
node _d_fire_counter_T_16 = and(_d_fire_counter_T_14, _d_fire_counter_T_15)
node _d_fire_counter_T_17 = sub(d_fire_counter_max, d_fire_counter)
node _d_fire_counter_T_18 = tail(_d_fire_counter_T_17, 1)
node _d_fire_counter_T_19 = sub(UInt<1>(0h1), _d_fire_counter_T_18)
node _d_fire_counter_T_20 = tail(_d_fire_counter_T_19, 1)
node _d_fire_counter_T_21 = sub(_d_fire_counter_T_20, UInt<1>(0h1))
node _d_fire_counter_T_22 = tail(_d_fire_counter_T_21, 1)
node _d_fire_counter_T_23 = mux(_d_fire_counter_T_16, _d_fire_counter_T_22, _d_fire_counter_T_7)
node _d_fire_counter_T_24 = mux(_d_fire_counter_T_9, UInt<1>(0h0), _d_fire_counter_T_23)
node _d_fire_counter_T_25 = mux(_d_fire_counter_T_8, d_fire_counter, _d_fire_counter_T_24)
connect d_fire_counter, _d_fire_counter_T_25
connect d_fire_started, UInt<1>(0h1)
node _T_47 = eq(mesh_cntl_signals_q.io.enq.ready, UInt<1>(0h0))
node _T_48 = and(performing_mul_pre, _T_47)
node _T_49 = eq(mul_pre_counter_lock, UInt<1>(0h0))
node _T_50 = and(_T_48, _T_49)
when _T_50 :
connect mul_pre_counter_count, d_fire_counter
else :
node _T_51 = eq(performing_mul_pre, UInt<1>(0h0))
when _T_51 :
connect mul_pre_counter_count, UInt<1>(0h0)
connect mul_pre_counter_lock, UInt<1>(0h0)
else :
node _T_52 = eq(mesh_cntl_signals_q.io.enq.ready, UInt<1>(0h0))
when _T_52 :
connect mul_pre_counter_lock, UInt<1>(0h1)
node _T_53 = eq(io.im2col.resp.bits.im2col_delay, UInt<1>(0h0))
node _T_54 = and(_T_53, performing_mul_pre)
when _T_54 :
node _mul_pre_counter_sub_T = gt(mul_pre_counter_sub, UInt<1>(0h0))
node _mul_pre_counter_sub_T_1 = sub(mul_pre_counter_sub, UInt<1>(0h1))
node _mul_pre_counter_sub_T_2 = tail(_mul_pre_counter_sub_T_1, 1)
node _mul_pre_counter_sub_T_3 = mux(_mul_pre_counter_sub_T, _mul_pre_counter_sub_T_2, UInt<1>(0h0))
connect mul_pre_counter_sub, _mul_pre_counter_sub_T_3
else :
when io.im2col.resp.bits.im2col_delay :
connect mul_pre_counter_sub, UInt<2>(0h2)
else :
connect mul_pre_counter_sub, UInt<1>(0h0)
node _about_to_fire_all_rows_T = sub(total_rows, UInt<1>(0h1))
node _about_to_fire_all_rows_T_1 = tail(_about_to_fire_all_rows_T, 1)
node _about_to_fire_all_rows_T_2 = eq(a_fire_counter, _about_to_fire_all_rows_T_1)
node _about_to_fire_all_rows_T_3 = and(_about_to_fire_all_rows_T_2, a_fire)
node _about_to_fire_all_rows_T_4 = eq(a_fire_counter, UInt<1>(0h0))
node _about_to_fire_all_rows_T_5 = or(_about_to_fire_all_rows_T_3, _about_to_fire_all_rows_T_4)
node _about_to_fire_all_rows_T_6 = sub(total_rows, UInt<1>(0h1))
node _about_to_fire_all_rows_T_7 = tail(_about_to_fire_all_rows_T_6, 1)
node _about_to_fire_all_rows_T_8 = eq(b_fire_counter, _about_to_fire_all_rows_T_7)
node _about_to_fire_all_rows_T_9 = and(_about_to_fire_all_rows_T_8, b_fire)
node _about_to_fire_all_rows_T_10 = eq(b_fire_counter, UInt<1>(0h0))
node _about_to_fire_all_rows_T_11 = or(_about_to_fire_all_rows_T_9, _about_to_fire_all_rows_T_10)
node _about_to_fire_all_rows_T_12 = and(_about_to_fire_all_rows_T_5, _about_to_fire_all_rows_T_11)
node _about_to_fire_all_rows_T_13 = sub(total_rows, UInt<1>(0h1))
node _about_to_fire_all_rows_T_14 = tail(_about_to_fire_all_rows_T_13, 1)
node _about_to_fire_all_rows_T_15 = eq(d_fire_counter, _about_to_fire_all_rows_T_14)
node _about_to_fire_all_rows_T_16 = and(_about_to_fire_all_rows_T_15, d_fire)
node _about_to_fire_all_rows_T_17 = eq(d_fire_counter, UInt<1>(0h0))
node _about_to_fire_all_rows_T_18 = or(_about_to_fire_all_rows_T_16, _about_to_fire_all_rows_T_17)
node _about_to_fire_all_rows_T_19 = and(_about_to_fire_all_rows_T_12, _about_to_fire_all_rows_T_18)
node _about_to_fire_all_rows_T_20 = or(a_fire_started, b_fire_started)
node _about_to_fire_all_rows_T_21 = or(_about_to_fire_all_rows_T_20, d_fire_started)
node _about_to_fire_all_rows_T_22 = and(_about_to_fire_all_rows_T_19, _about_to_fire_all_rows_T_21)
node about_to_fire_all_rows = and(_about_to_fire_all_rows_T_22, mesh_cntl_signals_q.io.enq.ready)
when about_to_fire_all_rows :
connect a_fire_started, UInt<1>(0h0)
connect b_fire_started, UInt<1>(0h0)
connect d_fire_started, UInt<1>(0h0)
wire d_fire_counter_mulpre : UInt
connect d_fire_counter_mulpre, b_fire_counter
node _T_55 = eq(io.im2col.resp.bits.im2col_delay, UInt<1>(0h0))
node _T_56 = and(performing_mul_pre, _T_55)
node _T_57 = and(_T_56, im2col_en)
when _T_57 :
node _d_fire_counter_mulpre_T = sub(d_fire_counter, mul_pre_counter_sub)
node _d_fire_counter_mulpre_T_1 = tail(_d_fire_counter_mulpre_T, 1)
connect d_fire_counter_mulpre, _d_fire_counter_mulpre_T_1
else :
connect d_fire_counter_mulpre, d_fire_counter
node _read_a_T = eq(a_read_from_acc, UInt<1>(0h0))
node _read_a_T_1 = and(a_valid, _read_a_T)
node _read_a_T_2 = eq(dataAbank, UInt<1>(0h0))
node _read_a_T_3 = and(_read_a_T_1, _read_a_T_2)
node _read_a_T_4 = and(_read_a_T_3, start_inputting_a)
node _read_a_T_5 = eq(multiply_garbage, UInt<1>(0h0))
node _read_a_T_6 = and(_read_a_T_4, _read_a_T_5)
node _read_a_T_7 = and(_read_a_T_6, a_row_is_not_all_zeros)
node _read_a_T_8 = and(io.im2col.req.ready, im2col_en)
node _read_a_T_9 = eq(_read_a_T_8, UInt<1>(0h0))
node read_a = and(_read_a_T_7, _read_a_T_9)
node _read_b_T = eq(b_read_from_acc, UInt<1>(0h0))
node _read_b_T_1 = and(b_valid, _read_b_T)
node _read_b_T_2 = eq(dataBbank, UInt<1>(0h0))
node _read_b_T_3 = and(_read_b_T_1, _read_b_T_2)
node _read_b_T_4 = and(_read_b_T_3, start_inputting_b)
node _read_b_T_5 = eq(accumulate_zeros, UInt<1>(0h0))
node _read_b_T_6 = and(_read_b_T_4, _read_b_T_5)
node read_b = and(_read_b_T_6, b_row_is_not_all_zeros)
node _read_d_T = eq(d_read_from_acc, UInt<1>(0h0))
node _read_d_T_1 = and(d_valid, _read_d_T)
node _read_d_T_2 = eq(dataDbank, UInt<1>(0h0))
node _read_d_T_3 = and(_read_d_T_1, _read_d_T_2)
node _read_d_T_4 = and(_read_d_T_3, start_inputting_d)
node _read_d_T_5 = eq(preload_zeros, UInt<1>(0h0))
node _read_d_T_6 = and(_read_d_T_4, _read_d_T_5)
node read_d = and(_read_d_T_6, d_row_is_not_all_zeros)
node _T_58 = eq(io.srams.read[0].req.ready, UInt<1>(0h0))
node _T_59 = and(read_a, _T_58)
when _T_59 :
connect a_ready, UInt<1>(0h0)
node _T_60 = eq(io.srams.read[0].req.ready, UInt<1>(0h0))
node _T_61 = and(read_b, _T_60)
when _T_61 :
connect b_ready, UInt<1>(0h0)
node _T_62 = eq(io.srams.read[0].req.ready, UInt<1>(0h0))
node _T_63 = and(read_d, _T_62)
when _T_63 :
connect d_ready, UInt<1>(0h0)
node _io_srams_read_0_req_valid_T = or(read_a, read_b)
node _io_srams_read_0_req_valid_T_1 = or(_io_srams_read_0_req_valid_T, read_d)
node _io_srams_read_0_req_valid_T_2 = and(_io_srams_read_0_req_valid_T_1, mesh_cntl_signals_q.io.enq.ready)
connect io.srams.read[0].req.valid, _io_srams_read_0_req_valid_T_2
connect io.srams.read[0].req.bits.fromDMA, UInt<1>(0h0)
node _io_srams_read_0_req_bits_addr_T = bits(a_address_rs1.data, 11, 0)
node _io_srams_read_0_req_bits_addr_T_1 = add(_io_srams_read_0_req_bits_addr_T, a_fire_counter)
node _io_srams_read_0_req_bits_addr_T_2 = tail(_io_srams_read_0_req_bits_addr_T_1, 1)
node _io_srams_read_0_req_bits_addr_T_3 = bits(b_address_rs2.data, 11, 0)
node _io_srams_read_0_req_bits_addr_T_4 = add(_io_srams_read_0_req_bits_addr_T_3, b_fire_counter)
node _io_srams_read_0_req_bits_addr_T_5 = tail(_io_srams_read_0_req_bits_addr_T_4, 1)
node _io_srams_read_0_req_bits_addr_T_6 = bits(d_address_rs1.data, 11, 0)
node _io_srams_read_0_req_bits_addr_T_7 = add(_io_srams_read_0_req_bits_addr_T_6, UInt<3>(0h4))
node _io_srams_read_0_req_bits_addr_T_8 = tail(_io_srams_read_0_req_bits_addr_T_7, 1)
node _io_srams_read_0_req_bits_addr_T_9 = sub(_io_srams_read_0_req_bits_addr_T_8, UInt<1>(0h1))
node _io_srams_read_0_req_bits_addr_T_10 = tail(_io_srams_read_0_req_bits_addr_T_9, 1)
node _io_srams_read_0_req_bits_addr_T_11 = sub(_io_srams_read_0_req_bits_addr_T_10, d_fire_counter_mulpre)
node _io_srams_read_0_req_bits_addr_T_12 = tail(_io_srams_read_0_req_bits_addr_T_11, 1)
node _io_srams_read_0_req_bits_addr_T_13 = mux(read_d, _io_srams_read_0_req_bits_addr_T_12, _io_srams_read_0_req_bits_addr_T_2)
node _io_srams_read_0_req_bits_addr_T_14 = mux(read_b, _io_srams_read_0_req_bits_addr_T_5, _io_srams_read_0_req_bits_addr_T_13)
connect io.srams.read[0].req.bits.addr, _io_srams_read_0_req_bits_addr_T_14
node _T_64 = eq(im2col_en, UInt<1>(0h0))
when _T_64 :
node _io_srams_read_0_req_bits_addr_T_15 = bits(a_address.data, 11, 0)
node _io_srams_read_0_req_bits_addr_T_16 = bits(b_address.data, 11, 0)
node _io_srams_read_0_req_bits_addr_T_17 = bits(d_address.data, 11, 0)
node _io_srams_read_0_req_bits_addr_T_18 = mux(read_d, _io_srams_read_0_req_bits_addr_T_17, _io_srams_read_0_req_bits_addr_T_15)
node _io_srams_read_0_req_bits_addr_T_19 = mux(read_b, _io_srams_read_0_req_bits_addr_T_16, _io_srams_read_0_req_bits_addr_T_18)
connect io.srams.read[0].req.bits.addr, _io_srams_read_0_req_bits_addr_T_19
connect io.srams.read[0].resp.ready, UInt<1>(0h0)
node _read_a_T_10 = eq(a_read_from_acc, UInt<1>(0h0))
node _read_a_T_11 = and(a_valid, _read_a_T_10)
node _read_a_T_12 = eq(dataAbank, UInt<1>(0h1))
node _read_a_T_13 = and(_read_a_T_11, _read_a_T_12)
node _read_a_T_14 = and(_read_a_T_13, start_inputting_a)
node _read_a_T_15 = eq(multiply_garbage, UInt<1>(0h0))
node _read_a_T_16 = and(_read_a_T_14, _read_a_T_15)
node _read_a_T_17 = and(_read_a_T_16, a_row_is_not_all_zeros)
node _read_a_T_18 = and(io.im2col.req.ready, im2col_en)
node _read_a_T_19 = eq(_read_a_T_18, UInt<1>(0h0))
node read_a_1 = and(_read_a_T_17, _read_a_T_19)
node _read_b_T_7 = eq(b_read_from_acc, UInt<1>(0h0))
node _read_b_T_8 = and(b_valid, _read_b_T_7)
node _read_b_T_9 = eq(dataBbank, UInt<1>(0h1))
node _read_b_T_10 = and(_read_b_T_8, _read_b_T_9)
node _read_b_T_11 = and(_read_b_T_10, start_inputting_b)
node _read_b_T_12 = eq(accumulate_zeros, UInt<1>(0h0))
node _read_b_T_13 = and(_read_b_T_11, _read_b_T_12)
node read_b_1 = and(_read_b_T_13, b_row_is_not_all_zeros)
node _read_d_T_7 = eq(d_read_from_acc, UInt<1>(0h0))
node _read_d_T_8 = and(d_valid, _read_d_T_7)
node _read_d_T_9 = eq(dataDbank, UInt<1>(0h1))
node _read_d_T_10 = and(_read_d_T_8, _read_d_T_9)
node _read_d_T_11 = and(_read_d_T_10, start_inputting_d)
node _read_d_T_12 = eq(preload_zeros, UInt<1>(0h0))
node _read_d_T_13 = and(_read_d_T_11, _read_d_T_12)
node read_d_1 = and(_read_d_T_13, d_row_is_not_all_zeros)
node _T_65 = eq(io.srams.read[1].req.ready, UInt<1>(0h0))
node _T_66 = and(read_a_1, _T_65)
when _T_66 :
connect a_ready, UInt<1>(0h0)
node _T_67 = eq(io.srams.read[1].req.ready, UInt<1>(0h0))
node _T_68 = and(read_b_1, _T_67)
when _T_68 :
connect b_ready, UInt<1>(0h0)
node _T_69 = eq(io.srams.read[1].req.ready, UInt<1>(0h0))
node _T_70 = and(read_d_1, _T_69)
when _T_70 :
connect d_ready, UInt<1>(0h0)
node _io_srams_read_1_req_valid_T = or(read_a_1, read_b_1)
node _io_srams_read_1_req_valid_T_1 = or(_io_srams_read_1_req_valid_T, read_d_1)
node _io_srams_read_1_req_valid_T_2 = and(_io_srams_read_1_req_valid_T_1, mesh_cntl_signals_q.io.enq.ready)
connect io.srams.read[1].req.valid, _io_srams_read_1_req_valid_T_2
connect io.srams.read[1].req.bits.fromDMA, UInt<1>(0h0)
node _io_srams_read_1_req_bits_addr_T = bits(a_address_rs1.data, 11, 0)
node _io_srams_read_1_req_bits_addr_T_1 = add(_io_srams_read_1_req_bits_addr_T, a_fire_counter)
node _io_srams_read_1_req_bits_addr_T_2 = tail(_io_srams_read_1_req_bits_addr_T_1, 1)
node _io_srams_read_1_req_bits_addr_T_3 = bits(b_address_rs2.data, 11, 0)
node _io_srams_read_1_req_bits_addr_T_4 = add(_io_srams_read_1_req_bits_addr_T_3, b_fire_counter)
node _io_srams_read_1_req_bits_addr_T_5 = tail(_io_srams_read_1_req_bits_addr_T_4, 1)
node _io_srams_read_1_req_bits_addr_T_6 = bits(d_address_rs1.data, 11, 0)
node _io_srams_read_1_req_bits_addr_T_7 = add(_io_srams_read_1_req_bits_addr_T_6, UInt<3>(0h4))
node _io_srams_read_1_req_bits_addr_T_8 = tail(_io_srams_read_1_req_bits_addr_T_7, 1)
node _io_srams_read_1_req_bits_addr_T_9 = sub(_io_srams_read_1_req_bits_addr_T_8, UInt<1>(0h1))
node _io_srams_read_1_req_bits_addr_T_10 = tail(_io_srams_read_1_req_bits_addr_T_9, 1)
node _io_srams_read_1_req_bits_addr_T_11 = sub(_io_srams_read_1_req_bits_addr_T_10, d_fire_counter_mulpre)
node _io_srams_read_1_req_bits_addr_T_12 = tail(_io_srams_read_1_req_bits_addr_T_11, 1)
node _io_srams_read_1_req_bits_addr_T_13 = mux(read_d_1, _io_srams_read_1_req_bits_addr_T_12, _io_srams_read_1_req_bits_addr_T_2)
node _io_srams_read_1_req_bits_addr_T_14 = mux(read_b_1, _io_srams_read_1_req_bits_addr_T_5, _io_srams_read_1_req_bits_addr_T_13)
connect io.srams.read[1].req.bits.addr, _io_srams_read_1_req_bits_addr_T_14
node _T_71 = eq(im2col_en, UInt<1>(0h0))
when _T_71 :
node _io_srams_read_1_req_bits_addr_T_15 = bits(a_address.data, 11, 0)
node _io_srams_read_1_req_bits_addr_T_16 = bits(b_address.data, 11, 0)
node _io_srams_read_1_req_bits_addr_T_17 = bits(d_address.data, 11, 0)
node _io_srams_read_1_req_bits_addr_T_18 = mux(read_d_1, _io_srams_read_1_req_bits_addr_T_17, _io_srams_read_1_req_bits_addr_T_15)
node _io_srams_read_1_req_bits_addr_T_19 = mux(read_b_1, _io_srams_read_1_req_bits_addr_T_16, _io_srams_read_1_req_bits_addr_T_18)
connect io.srams.read[1].req.bits.addr, _io_srams_read_1_req_bits_addr_T_19
connect io.srams.read[1].resp.ready, UInt<1>(0h0)
node _read_a_T_20 = eq(a_read_from_acc, UInt<1>(0h0))
node _read_a_T_21 = and(a_valid, _read_a_T_20)
node _read_a_T_22 = eq(dataAbank, UInt<2>(0h2))
node _read_a_T_23 = and(_read_a_T_21, _read_a_T_22)
node _read_a_T_24 = and(_read_a_T_23, start_inputting_a)
node _read_a_T_25 = eq(multiply_garbage, UInt<1>(0h0))
node _read_a_T_26 = and(_read_a_T_24, _read_a_T_25)
node _read_a_T_27 = and(_read_a_T_26, a_row_is_not_all_zeros)
node _read_a_T_28 = and(io.im2col.req.ready, im2col_en)
node _read_a_T_29 = eq(_read_a_T_28, UInt<1>(0h0))
node read_a_2 = and(_read_a_T_27, _read_a_T_29)
node _read_b_T_14 = eq(b_read_from_acc, UInt<1>(0h0))
node _read_b_T_15 = and(b_valid, _read_b_T_14)
node _read_b_T_16 = eq(dataBbank, UInt<2>(0h2))
node _read_b_T_17 = and(_read_b_T_15, _read_b_T_16)
node _read_b_T_18 = and(_read_b_T_17, start_inputting_b)
node _read_b_T_19 = eq(accumulate_zeros, UInt<1>(0h0))
node _read_b_T_20 = and(_read_b_T_18, _read_b_T_19)
node read_b_2 = and(_read_b_T_20, b_row_is_not_all_zeros)
node _read_d_T_14 = eq(d_read_from_acc, UInt<1>(0h0))
node _read_d_T_15 = and(d_valid, _read_d_T_14)
node _read_d_T_16 = eq(dataDbank, UInt<2>(0h2))
node _read_d_T_17 = and(_read_d_T_15, _read_d_T_16)
node _read_d_T_18 = and(_read_d_T_17, start_inputting_d)
node _read_d_T_19 = eq(preload_zeros, UInt<1>(0h0))
node _read_d_T_20 = and(_read_d_T_18, _read_d_T_19)
node read_d_2 = and(_read_d_T_20, d_row_is_not_all_zeros)
node _T_72 = eq(io.srams.read[2].req.ready, UInt<1>(0h0))
node _T_73 = and(read_a_2, _T_72)
when _T_73 :
connect a_ready, UInt<1>(0h0)
node _T_74 = eq(io.srams.read[2].req.ready, UInt<1>(0h0))
node _T_75 = and(read_b_2, _T_74)
when _T_75 :
connect b_ready, UInt<1>(0h0)
node _T_76 = eq(io.srams.read[2].req.ready, UInt<1>(0h0))
node _T_77 = and(read_d_2, _T_76)
when _T_77 :
connect d_ready, UInt<1>(0h0)
node _io_srams_read_2_req_valid_T = or(read_a_2, read_b_2)
node _io_srams_read_2_req_valid_T_1 = or(_io_srams_read_2_req_valid_T, read_d_2)
node _io_srams_read_2_req_valid_T_2 = and(_io_srams_read_2_req_valid_T_1, mesh_cntl_signals_q.io.enq.ready)
connect io.srams.read[2].req.valid, _io_srams_read_2_req_valid_T_2
connect io.srams.read[2].req.bits.fromDMA, UInt<1>(0h0)
node _io_srams_read_2_req_bits_addr_T = bits(a_address_rs1.data, 11, 0)
node _io_srams_read_2_req_bits_addr_T_1 = add(_io_srams_read_2_req_bits_addr_T, a_fire_counter)
node _io_srams_read_2_req_bits_addr_T_2 = tail(_io_srams_read_2_req_bits_addr_T_1, 1)
node _io_srams_read_2_req_bits_addr_T_3 = bits(b_address_rs2.data, 11, 0)
node _io_srams_read_2_req_bits_addr_T_4 = add(_io_srams_read_2_req_bits_addr_T_3, b_fire_counter)
node _io_srams_read_2_req_bits_addr_T_5 = tail(_io_srams_read_2_req_bits_addr_T_4, 1)
node _io_srams_read_2_req_bits_addr_T_6 = bits(d_address_rs1.data, 11, 0)
node _io_srams_read_2_req_bits_addr_T_7 = add(_io_srams_read_2_req_bits_addr_T_6, UInt<3>(0h4))
node _io_srams_read_2_req_bits_addr_T_8 = tail(_io_srams_read_2_req_bits_addr_T_7, 1)
node _io_srams_read_2_req_bits_addr_T_9 = sub(_io_srams_read_2_req_bits_addr_T_8, UInt<1>(0h1))
node _io_srams_read_2_req_bits_addr_T_10 = tail(_io_srams_read_2_req_bits_addr_T_9, 1)
node _io_srams_read_2_req_bits_addr_T_11 = sub(_io_srams_read_2_req_bits_addr_T_10, d_fire_counter_mulpre)
node _io_srams_read_2_req_bits_addr_T_12 = tail(_io_srams_read_2_req_bits_addr_T_11, 1)
node _io_srams_read_2_req_bits_addr_T_13 = mux(read_d_2, _io_srams_read_2_req_bits_addr_T_12, _io_srams_read_2_req_bits_addr_T_2)
node _io_srams_read_2_req_bits_addr_T_14 = mux(read_b_2, _io_srams_read_2_req_bits_addr_T_5, _io_srams_read_2_req_bits_addr_T_13)
connect io.srams.read[2].req.bits.addr, _io_srams_read_2_req_bits_addr_T_14
node _T_78 = eq(im2col_en, UInt<1>(0h0))
when _T_78 :
node _io_srams_read_2_req_bits_addr_T_15 = bits(a_address.data, 11, 0)
node _io_srams_read_2_req_bits_addr_T_16 = bits(b_address.data, 11, 0)
node _io_srams_read_2_req_bits_addr_T_17 = bits(d_address.data, 11, 0)
node _io_srams_read_2_req_bits_addr_T_18 = mux(read_d_2, _io_srams_read_2_req_bits_addr_T_17, _io_srams_read_2_req_bits_addr_T_15)
node _io_srams_read_2_req_bits_addr_T_19 = mux(read_b_2, _io_srams_read_2_req_bits_addr_T_16, _io_srams_read_2_req_bits_addr_T_18)
connect io.srams.read[2].req.bits.addr, _io_srams_read_2_req_bits_addr_T_19
connect io.srams.read[2].resp.ready, UInt<1>(0h0)
node _read_a_T_30 = eq(a_read_from_acc, UInt<1>(0h0))
node _read_a_T_31 = and(a_valid, _read_a_T_30)
node _read_a_T_32 = eq(dataAbank, UInt<2>(0h3))
node _read_a_T_33 = and(_read_a_T_31, _read_a_T_32)
node _read_a_T_34 = and(_read_a_T_33, start_inputting_a)
node _read_a_T_35 = eq(multiply_garbage, UInt<1>(0h0))
node _read_a_T_36 = and(_read_a_T_34, _read_a_T_35)
node _read_a_T_37 = and(_read_a_T_36, a_row_is_not_all_zeros)
node _read_a_T_38 = and(io.im2col.req.ready, im2col_en)
node _read_a_T_39 = eq(_read_a_T_38, UInt<1>(0h0))
node read_a_3 = and(_read_a_T_37, _read_a_T_39)
node _read_b_T_21 = eq(b_read_from_acc, UInt<1>(0h0))
node _read_b_T_22 = and(b_valid, _read_b_T_21)
node _read_b_T_23 = eq(dataBbank, UInt<2>(0h3))
node _read_b_T_24 = and(_read_b_T_22, _read_b_T_23)
node _read_b_T_25 = and(_read_b_T_24, start_inputting_b)
node _read_b_T_26 = eq(accumulate_zeros, UInt<1>(0h0))
node _read_b_T_27 = and(_read_b_T_25, _read_b_T_26)
node read_b_3 = and(_read_b_T_27, b_row_is_not_all_zeros)
node _read_d_T_21 = eq(d_read_from_acc, UInt<1>(0h0))
node _read_d_T_22 = and(d_valid, _read_d_T_21)
node _read_d_T_23 = eq(dataDbank, UInt<2>(0h3))
node _read_d_T_24 = and(_read_d_T_22, _read_d_T_23)
node _read_d_T_25 = and(_read_d_T_24, start_inputting_d)
node _read_d_T_26 = eq(preload_zeros, UInt<1>(0h0))
node _read_d_T_27 = and(_read_d_T_25, _read_d_T_26)
node read_d_3 = and(_read_d_T_27, d_row_is_not_all_zeros)
node _T_79 = eq(io.srams.read[3].req.ready, UInt<1>(0h0))
node _T_80 = and(read_a_3, _T_79)
when _T_80 :
connect a_ready, UInt<1>(0h0)
node _T_81 = eq(io.srams.read[3].req.ready, UInt<1>(0h0))
node _T_82 = and(read_b_3, _T_81)
when _T_82 :
connect b_ready, UInt<1>(0h0)
node _T_83 = eq(io.srams.read[3].req.ready, UInt<1>(0h0))
node _T_84 = and(read_d_3, _T_83)
when _T_84 :
connect d_ready, UInt<1>(0h0)
node _io_srams_read_3_req_valid_T = or(read_a_3, read_b_3)
node _io_srams_read_3_req_valid_T_1 = or(_io_srams_read_3_req_valid_T, read_d_3)
node _io_srams_read_3_req_valid_T_2 = and(_io_srams_read_3_req_valid_T_1, mesh_cntl_signals_q.io.enq.ready)
connect io.srams.read[3].req.valid, _io_srams_read_3_req_valid_T_2
connect io.srams.read[3].req.bits.fromDMA, UInt<1>(0h0)
node _io_srams_read_3_req_bits_addr_T = bits(a_address_rs1.data, 11, 0)
node _io_srams_read_3_req_bits_addr_T_1 = add(_io_srams_read_3_req_bits_addr_T, a_fire_counter)
node _io_srams_read_3_req_bits_addr_T_2 = tail(_io_srams_read_3_req_bits_addr_T_1, 1)
node _io_srams_read_3_req_bits_addr_T_3 = bits(b_address_rs2.data, 11, 0)
node _io_srams_read_3_req_bits_addr_T_4 = add(_io_srams_read_3_req_bits_addr_T_3, b_fire_counter)
node _io_srams_read_3_req_bits_addr_T_5 = tail(_io_srams_read_3_req_bits_addr_T_4, 1)
node _io_srams_read_3_req_bits_addr_T_6 = bits(d_address_rs1.data, 11, 0)
node _io_srams_read_3_req_bits_addr_T_7 = add(_io_srams_read_3_req_bits_addr_T_6, UInt<3>(0h4))
node _io_srams_read_3_req_bits_addr_T_8 = tail(_io_srams_read_3_req_bits_addr_T_7, 1)
node _io_srams_read_3_req_bits_addr_T_9 = sub(_io_srams_read_3_req_bits_addr_T_8, UInt<1>(0h1))
node _io_srams_read_3_req_bits_addr_T_10 = tail(_io_srams_read_3_req_bits_addr_T_9, 1)
node _io_srams_read_3_req_bits_addr_T_11 = sub(_io_srams_read_3_req_bits_addr_T_10, d_fire_counter_mulpre)
node _io_srams_read_3_req_bits_addr_T_12 = tail(_io_srams_read_3_req_bits_addr_T_11, 1)
node _io_srams_read_3_req_bits_addr_T_13 = mux(read_d_3, _io_srams_read_3_req_bits_addr_T_12, _io_srams_read_3_req_bits_addr_T_2)
node _io_srams_read_3_req_bits_addr_T_14 = mux(read_b_3, _io_srams_read_3_req_bits_addr_T_5, _io_srams_read_3_req_bits_addr_T_13)
connect io.srams.read[3].req.bits.addr, _io_srams_read_3_req_bits_addr_T_14
node _T_85 = eq(im2col_en, UInt<1>(0h0))
when _T_85 :
node _io_srams_read_3_req_bits_addr_T_15 = bits(a_address.data, 11, 0)
node _io_srams_read_3_req_bits_addr_T_16 = bits(b_address.data, 11, 0)
node _io_srams_read_3_req_bits_addr_T_17 = bits(d_address.data, 11, 0)
node _io_srams_read_3_req_bits_addr_T_18 = mux(read_d_3, _io_srams_read_3_req_bits_addr_T_17, _io_srams_read_3_req_bits_addr_T_15)
node _io_srams_read_3_req_bits_addr_T_19 = mux(read_b_3, _io_srams_read_3_req_bits_addr_T_16, _io_srams_read_3_req_bits_addr_T_18)
connect io.srams.read[3].req.bits.addr, _io_srams_read_3_req_bits_addr_T_19
connect io.srams.read[3].resp.ready, UInt<1>(0h0)
node _read_a_from_acc_T = and(a_valid, a_read_from_acc)
node _read_a_from_acc_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _read_a_from_acc_T_2 = and(_read_a_from_acc_T, _read_a_from_acc_T_1)
node _read_a_from_acc_T_3 = and(_read_a_from_acc_T_2, start_inputting_a)
node _read_a_from_acc_T_4 = eq(multiply_garbage, UInt<1>(0h0))
node _read_a_from_acc_T_5 = and(_read_a_from_acc_T_3, _read_a_from_acc_T_4)
node _read_a_from_acc_T_6 = and(_read_a_from_acc_T_5, a_row_is_not_all_zeros)
node _read_a_from_acc_T_7 = and(io.im2col.req.ready, im2col_en)
node _read_a_from_acc_T_8 = eq(_read_a_from_acc_T_7, UInt<1>(0h0))
node read_a_from_acc = and(_read_a_from_acc_T_6, _read_a_from_acc_T_8)
node _read_b_from_acc_T = and(b_valid, b_read_from_acc)
node _read_b_from_acc_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _read_b_from_acc_T_2 = and(_read_b_from_acc_T, _read_b_from_acc_T_1)
node _read_b_from_acc_T_3 = and(_read_b_from_acc_T_2, start_inputting_b)
node _read_b_from_acc_T_4 = eq(accumulate_zeros, UInt<1>(0h0))
node _read_b_from_acc_T_5 = and(_read_b_from_acc_T_3, _read_b_from_acc_T_4)
node read_b_from_acc = and(_read_b_from_acc_T_5, b_row_is_not_all_zeros)
node _read_d_from_acc_T = and(d_valid, d_read_from_acc)
node _read_d_from_acc_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _read_d_from_acc_T_2 = and(_read_d_from_acc_T, _read_d_from_acc_T_1)
node _read_d_from_acc_T_3 = and(_read_d_from_acc_T_2, start_inputting_d)
node _read_d_from_acc_T_4 = eq(preload_zeros, UInt<1>(0h0))
node _read_d_from_acc_T_5 = and(_read_d_from_acc_T_3, _read_d_from_acc_T_4)
node read_d_from_acc = and(_read_d_from_acc_T_5, d_row_is_not_all_zeros)
node _T_86 = eq(io.acc.read_req[0].ready, UInt<1>(0h0))
node _T_87 = and(read_a_from_acc, _T_86)
when _T_87 :
connect a_ready, UInt<1>(0h0)
node _T_88 = eq(io.acc.read_req[0].ready, UInt<1>(0h0))
node _T_89 = and(read_b_from_acc, _T_88)
when _T_89 :
connect b_ready, UInt<1>(0h0)
node _T_90 = eq(io.acc.read_req[0].ready, UInt<1>(0h0))
node _T_91 = and(read_d_from_acc, _T_90)
when _T_91 :
connect d_ready, UInt<1>(0h0)
node _io_acc_read_req_0_valid_T = or(read_a_from_acc, read_b_from_acc)
node _io_acc_read_req_0_valid_T_1 = or(_io_acc_read_req_0_valid_T, read_d_from_acc)
connect io.acc.read_req[0].valid, _io_acc_read_req_0_valid_T_1
connect io.acc.read_req[0].bits.scale, acc_scale
connect io.acc.read_req[0].bits.full, UInt<1>(0h0)
invalidate io.acc.read_req[0].bits.igelu_qb.bits
invalidate io.acc.read_req[0].bits.igelu_qc.bits
invalidate io.acc.read_req[0].bits.iexp_qln2.bits
invalidate io.acc.read_req[0].bits.iexp_qln2_inv.bits
connect io.acc.read_req[0].bits.act, activation
connect io.acc.read_req[0].bits.fromDMA, UInt<1>(0h0)
node _io_acc_read_req_0_bits_addr_T = bits(a_address_rs1.data, 11, 0)
node _io_acc_read_req_0_bits_addr_T_1 = add(_io_acc_read_req_0_bits_addr_T, a_fire_counter)
node _io_acc_read_req_0_bits_addr_T_2 = tail(_io_acc_read_req_0_bits_addr_T_1, 1)
node _io_acc_read_req_0_bits_addr_T_3 = bits(b_address_rs2.data, 11, 0)
node _io_acc_read_req_0_bits_addr_T_4 = add(_io_acc_read_req_0_bits_addr_T_3, b_fire_counter)
node _io_acc_read_req_0_bits_addr_T_5 = tail(_io_acc_read_req_0_bits_addr_T_4, 1)
node _io_acc_read_req_0_bits_addr_T_6 = bits(d_address_rs1.data, 11, 0)
node _io_acc_read_req_0_bits_addr_T_7 = add(_io_acc_read_req_0_bits_addr_T_6, UInt<3>(0h4))
node _io_acc_read_req_0_bits_addr_T_8 = tail(_io_acc_read_req_0_bits_addr_T_7, 1)
node _io_acc_read_req_0_bits_addr_T_9 = sub(_io_acc_read_req_0_bits_addr_T_8, UInt<1>(0h1))
node _io_acc_read_req_0_bits_addr_T_10 = tail(_io_acc_read_req_0_bits_addr_T_9, 1)
node _io_acc_read_req_0_bits_addr_T_11 = sub(_io_acc_read_req_0_bits_addr_T_10, d_fire_counter)
node _io_acc_read_req_0_bits_addr_T_12 = tail(_io_acc_read_req_0_bits_addr_T_11, 1)
node _io_acc_read_req_0_bits_addr_T_13 = mux(read_d_from_acc, _io_acc_read_req_0_bits_addr_T_12, _io_acc_read_req_0_bits_addr_T_2)
node _io_acc_read_req_0_bits_addr_T_14 = mux(read_b_from_acc, _io_acc_read_req_0_bits_addr_T_5, _io_acc_read_req_0_bits_addr_T_13)
connect io.acc.read_req[0].bits.addr, _io_acc_read_req_0_bits_addr_T_14
node _T_92 = eq(im2col_en, UInt<1>(0h0))
when _T_92 :
node _io_acc_read_req_0_bits_addr_T_15 = bits(a_address.data, 11, 0)
node _io_acc_read_req_0_bits_addr_T_16 = bits(b_address.data, 11, 0)
node _io_acc_read_req_0_bits_addr_T_17 = bits(d_address.data, 11, 0)
node _io_acc_read_req_0_bits_addr_T_18 = mux(read_d_from_acc, _io_acc_read_req_0_bits_addr_T_17, _io_acc_read_req_0_bits_addr_T_15)
node _io_acc_read_req_0_bits_addr_T_19 = mux(read_b_from_acc, _io_acc_read_req_0_bits_addr_T_16, _io_acc_read_req_0_bits_addr_T_18)
connect io.acc.read_req[0].bits.addr, _io_acc_read_req_0_bits_addr_T_19
connect io.acc.read_resp[0].ready, UInt<1>(0h0)
node _read_a_T_40 = and(a_valid, start_inputting_a)
node _read_a_T_41 = eq(multiply_garbage, UInt<1>(0h0))
node _read_a_T_42 = and(_read_a_T_40, _read_a_T_41)
node _read_a_T_43 = and(_read_a_T_42, io.im2col.req.ready)
node read_a_4 = and(_read_a_T_43, im2col_en)
node _T_93 = eq(io.im2col.req.ready, UInt<1>(0h0))
node _T_94 = and(read_a_4, _T_93)
when _T_94 :
connect a_ready, UInt<1>(0h0)
connect io.im2col.req.valid, read_a_4
connect io.im2col.req.bits.addr, a_address_rs1
connect io.im2col.req.bits.icol, icol
connect io.im2col.req.bits.irow, irow
connect io.im2col.req.bits.ocol, ocol
connect io.im2col.req.bits.stride, weight_stride
connect io.im2col.req.bits.krow, krow
connect io.im2col.req.bits.kdim2, kdim2
connect io.im2col.req.bits.row_turn, row_turn
connect io.im2col.req.bits.row_left, row_left
connect io.im2col.req.bits.channel, channel
connect io.im2col.req.bits.im2col_cmd, im2col_en
connect io.im2col.req.bits.start_inputting, start_inputting_a
connect io.im2col.req.bits.weight_double_bank, weight_double_bank
connect io.im2col.req.bits.weight_triple_bank, weight_triple_bank
connect io.im2col.resp.ready, mesh.io.a.ready
node _T_95 = eq(UInt<2>(0h0), control_state)
when _T_95 :
connect perform_single_preload, UInt<1>(0h0)
connect perform_mul_pre, UInt<1>(0h0)
connect perform_single_mul, UInt<1>(0h0)
when cmd_q.io.deq.valid[0] :
node _T_96 = eq(matmul_in_progress, UInt<1>(0h0))
node _T_97 = and(DoConfig, _T_96)
node _T_98 = or(pending_completed_rob_ids[0].valid, pending_completed_rob_ids[1].valid)
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = and(_T_97, _T_99)
when _T_100 :
wire config_ex_rs1 : { _spacer2 : UInt<0>, acc_scale : UInt<32>, a_stride : UInt<16>, _spacer1 : UInt<6>, b_transpose : UInt<1>, a_transpose : UInt<1>, set_only_strides : UInt<1>, _spacer0 : UInt<2>, activation : UInt<2>, dataflow : UInt<1>, cmd_type : UInt<2>}
wire _config_ex_rs1_WIRE : UInt<64>
connect _config_ex_rs1_WIRE, rs1s[0]
node _config_ex_rs1_T = bits(_config_ex_rs1_WIRE, 1, 0)
connect config_ex_rs1.cmd_type, _config_ex_rs1_T
node _config_ex_rs1_T_1 = bits(_config_ex_rs1_WIRE, 2, 2)
connect config_ex_rs1.dataflow, _config_ex_rs1_T_1
node _config_ex_rs1_T_2 = bits(_config_ex_rs1_WIRE, 4, 3)
connect config_ex_rs1.activation, _config_ex_rs1_T_2
node _config_ex_rs1_T_3 = bits(_config_ex_rs1_WIRE, 6, 5)
connect config_ex_rs1._spacer0, _config_ex_rs1_T_3
node _config_ex_rs1_T_4 = bits(_config_ex_rs1_WIRE, 7, 7)
connect config_ex_rs1.set_only_strides, _config_ex_rs1_T_4
node _config_ex_rs1_T_5 = bits(_config_ex_rs1_WIRE, 8, 8)
connect config_ex_rs1.a_transpose, _config_ex_rs1_T_5
node _config_ex_rs1_T_6 = bits(_config_ex_rs1_WIRE, 9, 9)
connect config_ex_rs1.b_transpose, _config_ex_rs1_T_6
node _config_ex_rs1_T_7 = bits(_config_ex_rs1_WIRE, 15, 10)
connect config_ex_rs1._spacer1, _config_ex_rs1_T_7
node _config_ex_rs1_T_8 = bits(_config_ex_rs1_WIRE, 31, 16)
connect config_ex_rs1.a_stride, _config_ex_rs1_T_8
node _config_ex_rs1_T_9 = bits(_config_ex_rs1_WIRE, 63, 32)
connect config_ex_rs1.acc_scale, _config_ex_rs1_T_9
invalidate config_ex_rs1._spacer2
wire config_ex_rs2 : { c_stride : UInt<16>, relu6_shift : UInt<16>, in_shift : UInt<32>}
wire _config_ex_rs2_WIRE : UInt<64>
connect _config_ex_rs2_WIRE, rs2s[0]
node _config_ex_rs2_T = bits(_config_ex_rs2_WIRE, 31, 0)
connect config_ex_rs2.in_shift, _config_ex_rs2_T
node _config_ex_rs2_T_1 = bits(_config_ex_rs2_WIRE, 47, 32)
connect config_ex_rs2.relu6_shift, _config_ex_rs2_T_1
node _config_ex_rs2_T_2 = bits(_config_ex_rs2_WIRE, 63, 48)
connect config_ex_rs2.c_stride, _config_ex_rs2_T_2
node config_cmd_type = bits(rs1s[0], 1, 0)
node _T_101 = eq(config_cmd_type, UInt<1>(0h0))
when _T_101 :
node _T_102 = eq(config_ex_rs1.set_only_strides, UInt<1>(0h0))
when _T_102 :
connect activation, config_ex_rs1.activation
connect in_shift, config_ex_rs2.in_shift
node _acc_scale_T = bits(rs1s[0], 63, 32)
wire _acc_scale_WIRE : { bits : UInt<32>}
wire _acc_scale_WIRE_1 : UInt<32>
connect _acc_scale_WIRE_1, _acc_scale_T
node _acc_scale_T_1 = bits(_acc_scale_WIRE_1, 31, 0)
connect _acc_scale_WIRE.bits, _acc_scale_T_1
connect acc_scale, _acc_scale_WIRE
connect a_transpose, config_ex_rs1.a_transpose
connect bd_transpose, config_ex_rs1.b_transpose
connect current_dataflow, config_ex_rs1.dataflow
connect a_addr_stride, config_ex_rs1.a_stride
connect c_addr_stride, config_ex_rs2.c_stride
connect config_initialized, UInt<1>(0h1)
else :
node _ocol_T = bits(cmd_q.io.deq.bits[0].cmd.rs2, 63, 56)
connect ocol, _ocol_T
node _kdim2_T = bits(cmd_q.io.deq.bits[0].cmd.rs2, 55, 48)
connect kdim2, _kdim2_T
node _krow_T = bits(cmd_q.io.deq.bits[0].cmd.rs2, 47, 44)
connect krow, _krow_T
node _channel_T = bits(cmd_q.io.deq.bits[0].cmd.rs2, 31, 23)
connect channel, _channel_T
node _weight_stride_T = bits(cmd_q.io.deq.bits[0].cmd.rs2, 22, 20)
connect weight_stride, _weight_stride_T
node _weight_double_bank_T = bits(cmd_q.io.deq.bits[0].cmd.rs1, 58, 58)
connect weight_double_bank, _weight_double_bank_T
node _weight_triple_bank_T = bits(cmd_q.io.deq.bits[0].cmd.rs1, 59, 59)
connect weight_triple_bank, _weight_triple_bank_T
node _row_left_T = bits(cmd_q.io.deq.bits[0].cmd.rs1, 57, 54)
connect row_left, _row_left_T
node _row_turn_T = bits(cmd_q.io.deq.bits[0].cmd.rs1, 53, 42)
connect row_turn, _row_turn_T
connect io.completed, cmd_q.io.deq.bits[0].rob_id
connect cmd_q.io.deq.pop, UInt<1>(0h1)
else :
node _T_103 = and(DoPreloads_0, cmd_q.io.deq.valid[1])
node _T_104 = eq(raw_hazard_pre, UInt<1>(0h0))
node _T_105 = or(UInt<1>(0h0), _T_104)
node _T_106 = and(_T_103, _T_105)
when _T_106 :
connect perform_single_preload, UInt<1>(0h1)
connect performing_single_preload, UInt<1>(0h1)
connect start_inputting_a, a_should_be_fed_into_transposer
connect start_inputting_b, b_should_be_fed_into_transposer
connect start_inputting_d, UInt<1>(0h1)
connect control_state, UInt<2>(0h1)
else :
node _T_107 = and(DoComputes_0, cmd_q.io.deq.valid[1])
node _T_108 = and(_T_107, DoPreloads_1)
node _T_109 = eq(third_instruction_needed, UInt<1>(0h0))
node _T_110 = eq(raw_hazard_mulpre, UInt<1>(0h0))
node _T_111 = and(cmd_q.io.deq.valid[2], _T_110)
node _T_112 = or(_T_109, _T_111)
node _T_113 = and(_T_108, _T_112)
when _T_113 :
connect perform_mul_pre, UInt<1>(0h1)
connect performing_mul_pre, UInt<1>(0h1)
connect start_inputting_a, UInt<1>(0h1)
connect start_inputting_b, UInt<1>(0h1)
connect start_inputting_d, UInt<1>(0h1)
connect control_state, UInt<2>(0h1)
else :
when DoComputes_0 :
connect perform_single_mul, UInt<1>(0h1)
connect performing_single_mul, UInt<1>(0h1)
node _start_inputting_a_T = eq(a_should_be_fed_into_transposer, UInt<1>(0h0))
connect start_inputting_a, _start_inputting_a_T
node _start_inputting_b_T = eq(b_should_be_fed_into_transposer, UInt<1>(0h0))
connect start_inputting_b, _start_inputting_b_T
connect control_state, UInt<2>(0h1)
else :
node _T_114 = eq(current_dataflow, UInt<1>(0h0))
node _T_115 = or(_T_114, DoConfig)
node _T_116 = and(matmul_in_progress, _T_115)
when _T_116 :
connect control_state, UInt<2>(0h2)
else :
node _T_117 = eq(current_dataflow, UInt<1>(0h0))
node _T_118 = and(matmul_in_progress, _T_117)
when _T_118 :
connect control_state, UInt<2>(0h2)
else :
node _T_119 = eq(UInt<2>(0h1), control_state)
when _T_119 :
when perform_single_preload :
connect start_inputting_a, a_should_be_fed_into_transposer
connect start_inputting_b, b_should_be_fed_into_transposer
connect start_inputting_d, UInt<1>(0h1)
when about_to_fire_all_rows :
connect cmd_q.io.deq.pop, UInt<1>(0h1)
connect control_state, UInt<2>(0h0)
node _pending_completed_rob_ids_0_valid_T = and(c_address_rs2.is_acc_addr, c_address_rs2.accumulate)
node _pending_completed_rob_ids_0_valid_T_1 = and(_pending_completed_rob_ids_0_valid_T, c_address_rs2.read_full_acc_row)
node _pending_completed_rob_ids_0_valid_T_2 = andr(c_address_rs2.data)
node _pending_completed_rob_ids_0_valid_T_3 = and(_pending_completed_rob_ids_0_valid_T_1, _pending_completed_rob_ids_0_valid_T_2)
node _pending_completed_rob_ids_0_valid_T_4 = bits(c_address_rs2.garbage_bit, 0, 0)
node _pending_completed_rob_ids_0_valid_T_5 = and(_pending_completed_rob_ids_0_valid_T_3, _pending_completed_rob_ids_0_valid_T_4)
node _pending_completed_rob_ids_0_valid_T_6 = and(cmd_q.io.deq.bits[0].rob_id.valid, _pending_completed_rob_ids_0_valid_T_5)
connect pending_completed_rob_ids[0].valid, _pending_completed_rob_ids_0_valid_T_6
connect pending_completed_rob_ids[0].bits, cmd_q.io.deq.bits[0].rob_id.bits
node _T_120 = eq(current_dataflow, UInt<1>(0h0))
when _T_120 :
wire in_prop_flush_qual1 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _in_prop_flush_qual1_WIRE : UInt<32>
connect _in_prop_flush_qual1_WIRE, rs2s[0]
node _in_prop_flush_qual1_T = bits(_in_prop_flush_qual1_WIRE, 13, 0)
connect in_prop_flush_qual1.data, _in_prop_flush_qual1_T
node _in_prop_flush_qual1_T_1 = bits(_in_prop_flush_qual1_WIRE, 14, 14)
connect in_prop_flush_qual1.garbage_bit, _in_prop_flush_qual1_T_1
node _in_prop_flush_qual1_T_2 = bits(_in_prop_flush_qual1_WIRE, 25, 15)
connect in_prop_flush_qual1.garbage, _in_prop_flush_qual1_T_2
node _in_prop_flush_qual1_T_3 = bits(_in_prop_flush_qual1_WIRE, 28, 26)
wire _in_prop_flush_qual1_WIRE_1 : UInt<3>
connect _in_prop_flush_qual1_WIRE_1, _in_prop_flush_qual1_T_3
wire _in_prop_flush_qual1_WIRE_2 : UInt<3>
connect _in_prop_flush_qual1_WIRE_2, _in_prop_flush_qual1_WIRE_1
connect in_prop_flush_qual1.norm_cmd, _in_prop_flush_qual1_WIRE_2
node _in_prop_flush_qual1_T_4 = bits(_in_prop_flush_qual1_WIRE, 29, 29)
connect in_prop_flush_qual1.read_full_acc_row, _in_prop_flush_qual1_T_4
node _in_prop_flush_qual1_T_5 = bits(_in_prop_flush_qual1_WIRE, 30, 30)
connect in_prop_flush_qual1.accumulate, _in_prop_flush_qual1_T_5
node _in_prop_flush_qual1_T_6 = bits(_in_prop_flush_qual1_WIRE, 31, 31)
connect in_prop_flush_qual1.is_acc_addr, _in_prop_flush_qual1_T_6
node _in_prop_flush_T = and(in_prop_flush_qual1.is_acc_addr, in_prop_flush_qual1.accumulate)
node _in_prop_flush_T_1 = and(_in_prop_flush_T, in_prop_flush_qual1.read_full_acc_row)
node _in_prop_flush_T_2 = andr(in_prop_flush_qual1.data)
node _in_prop_flush_T_3 = and(_in_prop_flush_T_1, _in_prop_flush_T_2)
node _in_prop_flush_T_4 = bits(in_prop_flush_qual1.garbage_bit, 0, 0)
node _in_prop_flush_T_5 = and(_in_prop_flush_T_3, _in_prop_flush_T_4)
node _in_prop_flush_T_6 = eq(_in_prop_flush_T_5, UInt<1>(0h0))
connect in_prop_flush, _in_prop_flush_T_6
else :
when perform_mul_pre :
connect start_inputting_a, UInt<1>(0h1)
connect start_inputting_b, UInt<1>(0h1)
connect start_inputting_d, UInt<1>(0h1)
when about_to_fire_all_rows :
connect cmd_q.io.deq.pop, UInt<2>(0h2)
connect control_state, UInt<2>(0h0)
connect pending_completed_rob_ids[0], cmd_q.io.deq.bits[0].rob_id
node _pending_completed_rob_ids_1_valid_T = and(c_address_rs2.is_acc_addr, c_address_rs2.accumulate)
node _pending_completed_rob_ids_1_valid_T_1 = and(_pending_completed_rob_ids_1_valid_T, c_address_rs2.read_full_acc_row)
node _pending_completed_rob_ids_1_valid_T_2 = andr(c_address_rs2.data)
node _pending_completed_rob_ids_1_valid_T_3 = and(_pending_completed_rob_ids_1_valid_T_1, _pending_completed_rob_ids_1_valid_T_2)
node _pending_completed_rob_ids_1_valid_T_4 = bits(c_address_rs2.garbage_bit, 0, 0)
node _pending_completed_rob_ids_1_valid_T_5 = and(_pending_completed_rob_ids_1_valid_T_3, _pending_completed_rob_ids_1_valid_T_4)
node _pending_completed_rob_ids_1_valid_T_6 = and(cmd_q.io.deq.bits[1].rob_id.valid, _pending_completed_rob_ids_1_valid_T_5)
connect pending_completed_rob_ids[1].valid, _pending_completed_rob_ids_1_valid_T_6
connect pending_completed_rob_ids[1].bits, cmd_q.io.deq.bits[1].rob_id.bits
node _T_121 = eq(current_dataflow, UInt<1>(0h0))
when _T_121 :
wire in_prop_flush_qual2 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
wire _in_prop_flush_qual2_WIRE : UInt<32>
connect _in_prop_flush_qual2_WIRE, rs2s[1]
node _in_prop_flush_qual2_T = bits(_in_prop_flush_qual2_WIRE, 13, 0)
connect in_prop_flush_qual2.data, _in_prop_flush_qual2_T
node _in_prop_flush_qual2_T_1 = bits(_in_prop_flush_qual2_WIRE, 14, 14)
connect in_prop_flush_qual2.garbage_bit, _in_prop_flush_qual2_T_1
node _in_prop_flush_qual2_T_2 = bits(_in_prop_flush_qual2_WIRE, 25, 15)
connect in_prop_flush_qual2.garbage, _in_prop_flush_qual2_T_2
node _in_prop_flush_qual2_T_3 = bits(_in_prop_flush_qual2_WIRE, 28, 26)
wire _in_prop_flush_qual2_WIRE_1 : UInt<3>
connect _in_prop_flush_qual2_WIRE_1, _in_prop_flush_qual2_T_3
wire _in_prop_flush_qual2_WIRE_2 : UInt<3>
connect _in_prop_flush_qual2_WIRE_2, _in_prop_flush_qual2_WIRE_1
connect in_prop_flush_qual2.norm_cmd, _in_prop_flush_qual2_WIRE_2
node _in_prop_flush_qual2_T_4 = bits(_in_prop_flush_qual2_WIRE, 29, 29)
connect in_prop_flush_qual2.read_full_acc_row, _in_prop_flush_qual2_T_4
node _in_prop_flush_qual2_T_5 = bits(_in_prop_flush_qual2_WIRE, 30, 30)
connect in_prop_flush_qual2.accumulate, _in_prop_flush_qual2_T_5
node _in_prop_flush_qual2_T_6 = bits(_in_prop_flush_qual2_WIRE, 31, 31)
connect in_prop_flush_qual2.is_acc_addr, _in_prop_flush_qual2_T_6
node _in_prop_flush_T_7 = and(in_prop_flush_qual2.is_acc_addr, in_prop_flush_qual2.accumulate)
node _in_prop_flush_T_8 = and(_in_prop_flush_T_7, in_prop_flush_qual2.read_full_acc_row)
node _in_prop_flush_T_9 = andr(in_prop_flush_qual2.data)
node _in_prop_flush_T_10 = and(_in_prop_flush_T_8, _in_prop_flush_T_9)
node _in_prop_flush_T_11 = bits(in_prop_flush_qual2.garbage_bit, 0, 0)
node _in_prop_flush_T_12 = and(_in_prop_flush_T_10, _in_prop_flush_T_11)
node _in_prop_flush_T_13 = eq(_in_prop_flush_T_12, UInt<1>(0h0))
connect in_prop_flush, _in_prop_flush_T_13
else :
when perform_single_mul :
node _start_inputting_a_T_1 = eq(a_should_be_fed_into_transposer, UInt<1>(0h0))
connect start_inputting_a, _start_inputting_a_T_1
node _start_inputting_b_T_1 = eq(b_should_be_fed_into_transposer, UInt<1>(0h0))
connect start_inputting_b, _start_inputting_b_T_1
when about_to_fire_all_rows :
connect cmd_q.io.deq.pop, UInt<1>(0h1)
connect control_state, UInt<2>(0h0)
connect pending_completed_rob_ids[0], cmd_q.io.deq.bits[0].rob_id
else :
node _T_122 = eq(UInt<2>(0h2), control_state)
when _T_122 :
node _T_123 = and(mesh.io.req.ready, mesh.io.req.valid)
when _T_123 :
connect control_state, UInt<2>(0h3)
else :
node _T_124 = eq(UInt<2>(0h3), control_state)
when _T_124 :
when mesh.io.req.ready :
connect control_state, UInt<2>(0h0)
node _computing_T = or(performing_mul_pre, performing_single_mul)
node computing = or(_computing_T, performing_single_preload)
connect mesh_cntl_signals_q.io.enq.valid, computing
connect mesh_cntl_signals_q.io.enq.bits.perform_mul_pre, performing_mul_pre
connect mesh_cntl_signals_q.io.enq.bits.perform_single_mul, performing_single_mul
connect mesh_cntl_signals_q.io.enq.bits.perform_single_preload, performing_single_preload
connect mesh_cntl_signals_q.io.enq.bits.a_bank, dataAbank
connect mesh_cntl_signals_q.io.enq.bits.b_bank, dataBbank
connect mesh_cntl_signals_q.io.enq.bits.d_bank, dataDbank
connect mesh_cntl_signals_q.io.enq.bits.a_bank_acc, UInt<1>(0h0)
connect mesh_cntl_signals_q.io.enq.bits.b_bank_acc, UInt<1>(0h0)
connect mesh_cntl_signals_q.io.enq.bits.d_bank_acc, UInt<1>(0h0)
connect mesh_cntl_signals_q.io.enq.bits.a_garbage, a_garbage
connect mesh_cntl_signals_q.io.enq.bits.b_garbage, b_garbage
connect mesh_cntl_signals_q.io.enq.bits.d_garbage, d_garbage
connect mesh_cntl_signals_q.io.enq.bits.a_read_from_acc, a_read_from_acc
connect mesh_cntl_signals_q.io.enq.bits.b_read_from_acc, b_read_from_acc
connect mesh_cntl_signals_q.io.enq.bits.d_read_from_acc, d_read_from_acc
connect mesh_cntl_signals_q.io.enq.bits.accumulate_zeros, accumulate_zeros
connect mesh_cntl_signals_q.io.enq.bits.preload_zeros, preload_zeros
node _mesh_cntl_signals_q_io_enq_bits_a_unpadded_cols_T = mux(a_row_is_not_all_zeros, a_cols, UInt<1>(0h0))
connect mesh_cntl_signals_q.io.enq.bits.a_unpadded_cols, _mesh_cntl_signals_q_io_enq_bits_a_unpadded_cols_T
node _mesh_cntl_signals_q_io_enq_bits_b_unpadded_cols_T = mux(b_row_is_not_all_zeros, b_cols, UInt<1>(0h0))
connect mesh_cntl_signals_q.io.enq.bits.b_unpadded_cols, _mesh_cntl_signals_q_io_enq_bits_b_unpadded_cols_T
node _mesh_cntl_signals_q_io_enq_bits_d_unpadded_cols_T = mux(d_row_is_not_all_zeros, d_cols, UInt<1>(0h0))
connect mesh_cntl_signals_q.io.enq.bits.d_unpadded_cols, _mesh_cntl_signals_q_io_enq_bits_d_unpadded_cols_T
connect mesh_cntl_signals_q.io.enq.bits.total_rows, total_rows
connect mesh_cntl_signals_q.io.enq.bits.a_fire, a_fire
connect mesh_cntl_signals_q.io.enq.bits.b_fire, b_fire
connect mesh_cntl_signals_q.io.enq.bits.d_fire, d_fire
connect mesh_cntl_signals_q.io.enq.bits.c_addr.data, c_address_rs2.data
connect mesh_cntl_signals_q.io.enq.bits.c_addr.garbage_bit, c_address_rs2.garbage_bit
connect mesh_cntl_signals_q.io.enq.bits.c_addr.garbage, c_address_rs2.garbage
connect mesh_cntl_signals_q.io.enq.bits.c_addr.norm_cmd, c_address_rs2.norm_cmd
connect mesh_cntl_signals_q.io.enq.bits.c_addr.read_full_acc_row, c_address_rs2.read_full_acc_row
connect mesh_cntl_signals_q.io.enq.bits.c_addr.accumulate, c_address_rs2.accumulate
connect mesh_cntl_signals_q.io.enq.bits.c_addr.is_acc_addr, c_address_rs2.is_acc_addr
connect mesh_cntl_signals_q.io.enq.bits.c_rows, c_rows
connect mesh_cntl_signals_q.io.enq.bits.c_cols, c_cols
connect mesh_cntl_signals_q.io.enq.bits.a_transpose, a_transpose
connect mesh_cntl_signals_q.io.enq.bits.bd_transpose, bd_transpose
node _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T = eq(performing_single_mul, UInt<1>(0h0))
node _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_1 = and(c_address_rs2.is_acc_addr, c_address_rs2.accumulate)
node _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_2 = and(_mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_1, c_address_rs2.read_full_acc_row)
node _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_3 = andr(c_address_rs2.data)
node _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_4 = and(_mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_2, _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_3)
node _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_5 = bits(c_address_rs2.garbage_bit, 0, 0)
node _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_6 = and(_mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_4, _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_5)
node _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_7 = eq(_mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_6, UInt<1>(0h0))
node _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_8 = and(_mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T, _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_7)
connect mesh_cntl_signals_q.io.enq.bits.rob_id.valid, _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_8
connect mesh_cntl_signals_q.io.enq.bits.rob_id.bits, cmd_q.io.deq.bits[preload_cmd_place].rob_id.bits
connect mesh_cntl_signals_q.io.enq.bits.dataflow, current_dataflow
node _mesh_cntl_signals_q_io_enq_bits_prop_T = mux(performing_single_preload, in_prop_flush, in_prop)
connect mesh_cntl_signals_q.io.enq.bits.prop, _mesh_cntl_signals_q_io_enq_bits_prop_T
connect mesh_cntl_signals_q.io.enq.bits.shift, in_shift
node _mesh_cntl_signals_q_io_enq_bits_im2colling_T = and(io.im2col.req.ready, im2col_en)
connect mesh_cntl_signals_q.io.enq.bits.im2colling, _mesh_cntl_signals_q_io_enq_bits_im2colling_T
node _mesh_cntl_signals_q_io_enq_bits_first_T = eq(a_fire_started, UInt<1>(0h0))
node _mesh_cntl_signals_q_io_enq_bits_first_T_1 = eq(b_fire_started, UInt<1>(0h0))
node _mesh_cntl_signals_q_io_enq_bits_first_T_2 = and(_mesh_cntl_signals_q_io_enq_bits_first_T, _mesh_cntl_signals_q_io_enq_bits_first_T_1)
node _mesh_cntl_signals_q_io_enq_bits_first_T_3 = eq(d_fire_started, UInt<1>(0h0))
node _mesh_cntl_signals_q_io_enq_bits_first_T_4 = and(_mesh_cntl_signals_q_io_enq_bits_first_T_2, _mesh_cntl_signals_q_io_enq_bits_first_T_3)
connect mesh_cntl_signals_q.io.enq.bits.first, _mesh_cntl_signals_q_io_enq_bits_first_T_4
wire readData : UInt<128>[4]
connect readData[0], io.srams.read[0].resp.bits.data
connect readData[1], io.srams.read[1].resp.bits.data
connect readData[2], io.srams.read[2].resp.bits.data
connect readData[3], io.srams.read[3].resp.bits.data
node accReadData_lo = cat(io.acc.read_resp[0].bits.data[1][0].bits, io.acc.read_resp[0].bits.data[0][0].bits)
node accReadData_hi = cat(io.acc.read_resp[0].bits.data[3][0].bits, io.acc.read_resp[0].bits.data[2][0].bits)
node _accReadData_T = cat(accReadData_hi, accReadData_lo)
wire accReadData : UInt<128>[1]
connect accReadData[0], _accReadData_T
node im2ColData_lo = cat(io.im2col.resp.bits.a_im2col[1].bits, io.im2col.resp.bits.a_im2col[0].bits)
node im2ColData_hi = cat(io.im2col.resp.bits.a_im2col[3].bits, io.im2col.resp.bits.a_im2col[2].bits)
node im2ColData = cat(im2ColData_hi, im2ColData_lo)
node _readValid_T = and(UInt<1>(0h1), io.srams.read[0].resp.valid)
node _readValid_T_1 = eq(io.srams.read[0].resp.bits.fromDMA, UInt<1>(0h0))
node _readValid_T_2 = and(_readValid_T, _readValid_T_1)
node _readValid_T_3 = and(UInt<1>(0h1), io.srams.read[1].resp.valid)
node _readValid_T_4 = eq(io.srams.read[1].resp.bits.fromDMA, UInt<1>(0h0))
node _readValid_T_5 = and(_readValid_T_3, _readValid_T_4)
node _readValid_T_6 = and(UInt<1>(0h1), io.srams.read[2].resp.valid)
node _readValid_T_7 = eq(io.srams.read[2].resp.bits.fromDMA, UInt<1>(0h0))
node _readValid_T_8 = and(_readValid_T_6, _readValid_T_7)
node _readValid_T_9 = and(UInt<1>(0h1), io.srams.read[3].resp.valid)
node _readValid_T_10 = eq(io.srams.read[3].resp.bits.fromDMA, UInt<1>(0h0))
node _readValid_T_11 = and(_readValid_T_9, _readValid_T_10)
wire readValid : UInt<1>[4]
connect readValid[0], _readValid_T_2
connect readValid[1], _readValid_T_5
connect readValid[2], _readValid_T_8
connect readValid[3], _readValid_T_11
node _accReadValid_T = and(UInt<1>(0h1), io.acc.read_resp[0].valid)
node _accReadValid_T_1 = eq(io.acc.read_resp[0].bits.fromDMA, UInt<1>(0h0))
node _accReadValid_T_2 = and(_accReadValid_T, _accReadValid_T_1)
wire accReadValid : UInt<1>[1]
connect accReadValid[0], _accReadValid_T_2
node _mesh_cntl_signals_q_io_deq_ready_T = eq(mesh_cntl_signals_q.io.deq.bits.a_fire, UInt<1>(0h0))
node _mesh_cntl_signals_q_io_deq_ready_T_1 = and(mesh.io.a.ready, mesh.io.a.valid)
node _mesh_cntl_signals_q_io_deq_ready_T_2 = or(_mesh_cntl_signals_q_io_deq_ready_T, _mesh_cntl_signals_q_io_deq_ready_T_1)
node _mesh_cntl_signals_q_io_deq_ready_T_3 = eq(mesh.io.a.ready, UInt<1>(0h0))
node _mesh_cntl_signals_q_io_deq_ready_T_4 = or(_mesh_cntl_signals_q_io_deq_ready_T_2, _mesh_cntl_signals_q_io_deq_ready_T_3)
node _mesh_cntl_signals_q_io_deq_ready_T_5 = eq(mesh_cntl_signals_q.io.deq.bits.b_fire, UInt<1>(0h0))
node _mesh_cntl_signals_q_io_deq_ready_T_6 = and(mesh.io.b.ready, mesh.io.b.valid)
node _mesh_cntl_signals_q_io_deq_ready_T_7 = or(_mesh_cntl_signals_q_io_deq_ready_T_5, _mesh_cntl_signals_q_io_deq_ready_T_6)
node _mesh_cntl_signals_q_io_deq_ready_T_8 = eq(mesh.io.b.ready, UInt<1>(0h0))
node _mesh_cntl_signals_q_io_deq_ready_T_9 = or(_mesh_cntl_signals_q_io_deq_ready_T_7, _mesh_cntl_signals_q_io_deq_ready_T_8)
node _mesh_cntl_signals_q_io_deq_ready_T_10 = and(_mesh_cntl_signals_q_io_deq_ready_T_4, _mesh_cntl_signals_q_io_deq_ready_T_9)
node _mesh_cntl_signals_q_io_deq_ready_T_11 = eq(mesh_cntl_signals_q.io.deq.bits.d_fire, UInt<1>(0h0))
node _mesh_cntl_signals_q_io_deq_ready_T_12 = and(mesh.io.d.ready, mesh.io.d.valid)
node _mesh_cntl_signals_q_io_deq_ready_T_13 = or(_mesh_cntl_signals_q_io_deq_ready_T_11, _mesh_cntl_signals_q_io_deq_ready_T_12)
node _mesh_cntl_signals_q_io_deq_ready_T_14 = eq(mesh.io.d.ready, UInt<1>(0h0))
node _mesh_cntl_signals_q_io_deq_ready_T_15 = or(_mesh_cntl_signals_q_io_deq_ready_T_13, _mesh_cntl_signals_q_io_deq_ready_T_14)
node _mesh_cntl_signals_q_io_deq_ready_T_16 = and(_mesh_cntl_signals_q_io_deq_ready_T_10, _mesh_cntl_signals_q_io_deq_ready_T_15)
node _mesh_cntl_signals_q_io_deq_ready_T_17 = eq(mesh_cntl_signals_q.io.deq.bits.first, UInt<1>(0h0))
node _mesh_cntl_signals_q_io_deq_ready_T_18 = or(_mesh_cntl_signals_q_io_deq_ready_T_17, mesh.io.req.ready)
node _mesh_cntl_signals_q_io_deq_ready_T_19 = and(_mesh_cntl_signals_q_io_deq_ready_T_16, _mesh_cntl_signals_q_io_deq_ready_T_18)
connect mesh_cntl_signals_q.io.deq.ready, _mesh_cntl_signals_q_io_deq_ready_T_19
node _dataA_valid_T = eq(mesh_cntl_signals_q.io.deq.bits.a_unpadded_cols, UInt<1>(0h0))
node _dataA_valid_T_1 = or(mesh_cntl_signals_q.io.deq.bits.a_garbage, _dataA_valid_T)
wire _dataA_valid_WIRE : UInt
connect _dataA_valid_WIRE, UInt<1>(0h0)
node _dataA_valid_T_2 = mux(mesh_cntl_signals_q.io.deq.bits.a_read_from_acc, accReadValid[_dataA_valid_WIRE], readValid[mesh_cntl_signals_q.io.deq.bits.a_bank])
node _dataA_valid_T_3 = mux(mesh_cntl_signals_q.io.deq.bits.im2colling, io.im2col.resp.valid, _dataA_valid_T_2)
node dataA_valid = or(_dataA_valid_T_1, _dataA_valid_T_3)
node _dataB_valid_T = eq(mesh_cntl_signals_q.io.deq.bits.b_unpadded_cols, UInt<1>(0h0))
node _dataB_valid_T_1 = or(mesh_cntl_signals_q.io.deq.bits.b_garbage, _dataB_valid_T)
wire _dataB_valid_WIRE : UInt
connect _dataB_valid_WIRE, UInt<1>(0h0)
node _dataB_valid_T_2 = mux(mesh_cntl_signals_q.io.deq.bits.b_read_from_acc, accReadValid[_dataB_valid_WIRE], readValid[mesh_cntl_signals_q.io.deq.bits.b_bank])
node _dataB_valid_T_3 = mux(mesh_cntl_signals_q.io.deq.bits.accumulate_zeros, UInt<1>(0h0), _dataB_valid_T_2)
node dataB_valid = or(_dataB_valid_T_1, _dataB_valid_T_3)
node _dataD_valid_T = eq(mesh_cntl_signals_q.io.deq.bits.d_unpadded_cols, UInt<1>(0h0))
node _dataD_valid_T_1 = or(mesh_cntl_signals_q.io.deq.bits.d_garbage, _dataD_valid_T)
wire _dataD_valid_WIRE : UInt
connect _dataD_valid_WIRE, UInt<1>(0h0)
node _dataD_valid_T_2 = mux(mesh_cntl_signals_q.io.deq.bits.d_read_from_acc, accReadValid[_dataD_valid_WIRE], readValid[mesh_cntl_signals_q.io.deq.bits.d_bank])
node _dataD_valid_T_3 = mux(mesh_cntl_signals_q.io.deq.bits.preload_zeros, UInt<1>(0h0), _dataD_valid_T_2)
node dataD_valid = or(_dataD_valid_T_1, _dataD_valid_T_3)
regreset preload_zero_counter : UInt<5>, clock, reset, UInt<5>(0h0)
node _preload_zero_counter_T = and(dataA_valid, dataD_valid)
node _preload_zero_counter_T_1 = and(_preload_zero_counter_T, mesh_cntl_signals_q.io.deq.bits.preload_zeros)
node _preload_zero_counter_T_2 = or(mesh_cntl_signals_q.io.deq.bits.perform_single_preload, mesh_cntl_signals_q.io.deq.bits.perform_mul_pre)
node _preload_zero_counter_T_3 = and(_preload_zero_counter_T_1, _preload_zero_counter_T_2)
node _preload_zero_counter_max_T = sub(UInt<3>(0h4), UInt<1>(0h1))
node preload_zero_counter_max = tail(_preload_zero_counter_max_T, 1)
node _preload_zero_counter_T_4 = leq(UInt<1>(0h1), preload_zero_counter_max)
node _preload_zero_counter_T_5 = eq(preload_zero_counter_max, UInt<1>(0h0))
node _preload_zero_counter_T_6 = or(_preload_zero_counter_T_4, _preload_zero_counter_T_5)
node _preload_zero_counter_T_7 = asUInt(reset)
node _preload_zero_counter_T_8 = eq(_preload_zero_counter_T_7, UInt<1>(0h0))
when _preload_zero_counter_T_8 :
node _preload_zero_counter_T_9 = eq(_preload_zero_counter_T_6, UInt<1>(0h0))
when _preload_zero_counter_T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed: cannot wrapAdd when n is larger than max, unless max is 0\n at Util.scala:19 assert(n <= max || max === 0.U, \"cannot wrapAdd when n is larger than max, unless max is 0\")\n") : preload_zero_counter_printf
assert(clock, _preload_zero_counter_T_6, UInt<1>(0h1), "") : preload_zero_counter_assert
node _preload_zero_counter_T_10 = add(preload_zero_counter, UInt<1>(0h1))
node _preload_zero_counter_T_11 = tail(_preload_zero_counter_T_10, 1)
node _preload_zero_counter_T_12 = eq(_preload_zero_counter_T_3, UInt<1>(0h0))
node _preload_zero_counter_T_13 = eq(preload_zero_counter_max, UInt<1>(0h0))
node _preload_zero_counter_T_14 = sub(preload_zero_counter_max, UInt<1>(0h1))
node _preload_zero_counter_T_15 = tail(_preload_zero_counter_T_14, 1)
node _preload_zero_counter_T_16 = add(_preload_zero_counter_T_15, UInt<1>(0h1))
node _preload_zero_counter_T_17 = tail(_preload_zero_counter_T_16, 1)
node _preload_zero_counter_T_18 = geq(preload_zero_counter, _preload_zero_counter_T_17)
node _preload_zero_counter_T_19 = neq(UInt<1>(0h1), UInt<1>(0h0))
node _preload_zero_counter_T_20 = and(_preload_zero_counter_T_18, _preload_zero_counter_T_19)
node _preload_zero_counter_T_21 = sub(preload_zero_counter_max, preload_zero_counter)
node _preload_zero_counter_T_22 = tail(_preload_zero_counter_T_21, 1)
node _preload_zero_counter_T_23 = sub(UInt<1>(0h1), _preload_zero_counter_T_22)
node _preload_zero_counter_T_24 = tail(_preload_zero_counter_T_23, 1)
node _preload_zero_counter_T_25 = sub(_preload_zero_counter_T_24, UInt<1>(0h1))
node _preload_zero_counter_T_26 = tail(_preload_zero_counter_T_25, 1)
node _preload_zero_counter_T_27 = mux(_preload_zero_counter_T_20, _preload_zero_counter_T_26, _preload_zero_counter_T_11)
node _preload_zero_counter_T_28 = mux(_preload_zero_counter_T_13, UInt<1>(0h0), _preload_zero_counter_T_27)
node _preload_zero_counter_T_29 = mux(_preload_zero_counter_T_12, preload_zero_counter, _preload_zero_counter_T_28)
connect preload_zero_counter, _preload_zero_counter_T_29
wire _dataA_unpadded_WIRE : UInt
connect _dataA_unpadded_WIRE, UInt<1>(0h0)
node _dataA_unpadded_T = mux(mesh_cntl_signals_q.io.deq.bits.a_read_from_acc, accReadData[_dataA_unpadded_WIRE], readData[mesh_cntl_signals_q.io.deq.bits.a_bank])
node dataA_unpadded = mux(mesh_cntl_signals_q.io.deq.bits.im2colling, im2ColData, _dataA_unpadded_T)
wire _dataB_unpadded_WIRE : UInt
connect _dataB_unpadded_WIRE, UInt<1>(0h0)
node _dataB_unpadded_T = mux(mesh_cntl_signals_q.io.deq.bits.b_read_from_acc, accReadData[_dataB_unpadded_WIRE], readData[mesh_cntl_signals_q.io.deq.bits.b_bank])
node dataB_unpadded = mux(mesh_cntl_signals_q.io.deq.bits.accumulate_zeros, UInt<1>(0h0), _dataB_unpadded_T)
wire _dataD_unpadded_WIRE : UInt
connect _dataD_unpadded_WIRE, UInt<1>(0h0)
node _dataD_unpadded_T = mux(mesh_cntl_signals_q.io.deq.bits.d_read_from_acc, accReadData[_dataD_unpadded_WIRE], readData[mesh_cntl_signals_q.io.deq.bits.d_bank])
node dataD_unpadded = mux(mesh_cntl_signals_q.io.deq.bits.preload_zeros, UInt<1>(0h0), _dataD_unpadded_T)
wire _dataA_WIRE : { bits : UInt<32>}[4]
wire _dataA_WIRE_1 : UInt<128>
connect _dataA_WIRE_1, dataA_unpadded
node _dataA_T = bits(_dataA_WIRE_1, 31, 0)
connect _dataA_WIRE[0].bits, _dataA_T
node _dataA_T_1 = bits(_dataA_WIRE_1, 63, 32)
connect _dataA_WIRE[1].bits, _dataA_T_1
node _dataA_T_2 = bits(_dataA_WIRE_1, 95, 64)
connect _dataA_WIRE[2].bits, _dataA_T_2
node _dataA_T_3 = bits(_dataA_WIRE_1, 127, 96)
connect _dataA_WIRE[3].bits, _dataA_T_3
node _dataA_T_4 = lt(UInt<1>(0h0), mesh_cntl_signals_q.io.deq.bits.a_unpadded_cols)
wire _dataA_WIRE_2 : { bits : UInt<32>}
connect _dataA_WIRE_2.bits, UInt<32>(0h0)
node _dataA_T_5 = mux(_dataA_T_4, _dataA_WIRE[0], _dataA_WIRE_2)
node _dataA_T_6 = lt(UInt<1>(0h1), mesh_cntl_signals_q.io.deq.bits.a_unpadded_cols)
wire _dataA_WIRE_3 : { bits : UInt<32>}
connect _dataA_WIRE_3.bits, UInt<32>(0h0)
node _dataA_T_7 = mux(_dataA_T_6, _dataA_WIRE[1], _dataA_WIRE_3)
node _dataA_T_8 = lt(UInt<2>(0h2), mesh_cntl_signals_q.io.deq.bits.a_unpadded_cols)
wire _dataA_WIRE_4 : { bits : UInt<32>}
connect _dataA_WIRE_4.bits, UInt<32>(0h0)
node _dataA_T_9 = mux(_dataA_T_8, _dataA_WIRE[2], _dataA_WIRE_4)
node _dataA_T_10 = lt(UInt<2>(0h3), mesh_cntl_signals_q.io.deq.bits.a_unpadded_cols)
wire _dataA_WIRE_5 : { bits : UInt<32>}
connect _dataA_WIRE_5.bits, UInt<32>(0h0)
node _dataA_T_11 = mux(_dataA_T_10, _dataA_WIRE[3], _dataA_WIRE_5)
wire dataA : { bits : UInt<32>}[4]
connect dataA[0], _dataA_T_5
connect dataA[1], _dataA_T_7
connect dataA[2], _dataA_T_9
connect dataA[3], _dataA_T_11
wire _dataB_WIRE : { bits : UInt<32>}[4]
wire _dataB_WIRE_1 : UInt<128>
connect _dataB_WIRE_1, dataB_unpadded
node _dataB_T = bits(_dataB_WIRE_1, 31, 0)
connect _dataB_WIRE[0].bits, _dataB_T
node _dataB_T_1 = bits(_dataB_WIRE_1, 63, 32)
connect _dataB_WIRE[1].bits, _dataB_T_1
node _dataB_T_2 = bits(_dataB_WIRE_1, 95, 64)
connect _dataB_WIRE[2].bits, _dataB_T_2
node _dataB_T_3 = bits(_dataB_WIRE_1, 127, 96)
connect _dataB_WIRE[3].bits, _dataB_T_3
node _dataB_T_4 = lt(UInt<1>(0h0), mesh_cntl_signals_q.io.deq.bits.b_unpadded_cols)
wire _dataB_WIRE_2 : { bits : UInt<32>}
connect _dataB_WIRE_2.bits, UInt<32>(0h0)
node _dataB_T_5 = mux(_dataB_T_4, _dataB_WIRE[0], _dataB_WIRE_2)
node _dataB_T_6 = lt(UInt<1>(0h1), mesh_cntl_signals_q.io.deq.bits.b_unpadded_cols)
wire _dataB_WIRE_3 : { bits : UInt<32>}
connect _dataB_WIRE_3.bits, UInt<32>(0h0)
node _dataB_T_7 = mux(_dataB_T_6, _dataB_WIRE[1], _dataB_WIRE_3)
node _dataB_T_8 = lt(UInt<2>(0h2), mesh_cntl_signals_q.io.deq.bits.b_unpadded_cols)
wire _dataB_WIRE_4 : { bits : UInt<32>}
connect _dataB_WIRE_4.bits, UInt<32>(0h0)
node _dataB_T_9 = mux(_dataB_T_8, _dataB_WIRE[2], _dataB_WIRE_4)
node _dataB_T_10 = lt(UInt<2>(0h3), mesh_cntl_signals_q.io.deq.bits.b_unpadded_cols)
wire _dataB_WIRE_5 : { bits : UInt<32>}
connect _dataB_WIRE_5.bits, UInt<32>(0h0)
node _dataB_T_11 = mux(_dataB_T_10, _dataB_WIRE[3], _dataB_WIRE_5)
wire dataB : { bits : UInt<32>}[4]
connect dataB[0], _dataB_T_5
connect dataB[1], _dataB_T_7
connect dataB[2], _dataB_T_9
connect dataB[3], _dataB_T_11
wire _dataD_WIRE : { bits : UInt<32>}[4]
wire _dataD_WIRE_1 : UInt<128>
connect _dataD_WIRE_1, dataD_unpadded
node _dataD_T = bits(_dataD_WIRE_1, 31, 0)
connect _dataD_WIRE[0].bits, _dataD_T
node _dataD_T_1 = bits(_dataD_WIRE_1, 63, 32)
connect _dataD_WIRE[1].bits, _dataD_T_1
node _dataD_T_2 = bits(_dataD_WIRE_1, 95, 64)
connect _dataD_WIRE[2].bits, _dataD_T_2
node _dataD_T_3 = bits(_dataD_WIRE_1, 127, 96)
connect _dataD_WIRE[3].bits, _dataD_T_3
node _dataD_T_4 = lt(UInt<1>(0h0), mesh_cntl_signals_q.io.deq.bits.d_unpadded_cols)
wire _dataD_WIRE_2 : { bits : UInt<32>}
connect _dataD_WIRE_2.bits, UInt<32>(0h0)
node _dataD_T_5 = mux(_dataD_T_4, _dataD_WIRE[0], _dataD_WIRE_2)
node _dataD_T_6 = lt(UInt<1>(0h1), mesh_cntl_signals_q.io.deq.bits.d_unpadded_cols)
wire _dataD_WIRE_3 : { bits : UInt<32>}
connect _dataD_WIRE_3.bits, UInt<32>(0h0)
node _dataD_T_7 = mux(_dataD_T_6, _dataD_WIRE[1], _dataD_WIRE_3)
node _dataD_T_8 = lt(UInt<2>(0h2), mesh_cntl_signals_q.io.deq.bits.d_unpadded_cols)
wire _dataD_WIRE_4 : { bits : UInt<32>}
connect _dataD_WIRE_4.bits, UInt<32>(0h0)
node _dataD_T_9 = mux(_dataD_T_8, _dataD_WIRE[2], _dataD_WIRE_4)
node _dataD_T_10 = lt(UInt<2>(0h3), mesh_cntl_signals_q.io.deq.bits.d_unpadded_cols)
wire _dataD_WIRE_5 : { bits : UInt<32>}
connect _dataD_WIRE_5.bits, UInt<32>(0h0)
node _dataD_T_11 = mux(_dataD_T_10, _dataD_WIRE[3], _dataD_WIRE_5)
wire dataD : { bits : UInt<32>}[4]
connect dataD[0], _dataD_T_5
connect dataD[1], _dataD_T_7
connect dataD[2], _dataD_T_9
connect dataD[3], _dataD_T_11
node _T_125 = and(mesh_cntl_signals_q.io.deq.ready, mesh_cntl_signals_q.io.deq.valid)
when _T_125 :
node _T_126 = and(mesh.io.a.ready, mesh.io.a.valid)
node _T_127 = and(mesh_cntl_signals_q.io.deq.bits.a_fire, _T_126)
node _T_128 = eq(mesh_cntl_signals_q.io.deq.bits.a_garbage, UInt<1>(0h0))
node _T_129 = and(_T_127, _T_128)
node _T_130 = gt(mesh_cntl_signals_q.io.deq.bits.a_unpadded_cols, UInt<1>(0h0))
node _T_131 = and(_T_129, _T_130)
node _T_132 = eq(mesh_cntl_signals_q.io.deq.bits.im2colling, UInt<1>(0h0))
node _T_133 = and(_T_131, _T_132)
when _T_133 :
when mesh_cntl_signals_q.io.deq.bits.a_read_from_acc :
wire _WIRE : UInt
connect _WIRE, UInt<1>(0h0)
wire _io_acc_read_resp_ready_WIRE : UInt
connect _io_acc_read_resp_ready_WIRE, UInt<1>(0h0)
node _io_acc_read_resp_ready_T = eq(io.acc.read_resp[_io_acc_read_resp_ready_WIRE].bits.fromDMA, UInt<1>(0h0))
connect io.acc.read_resp[_WIRE].ready, _io_acc_read_resp_ready_T
else :
node _io_srams_read_resp_ready_T = eq(io.srams.read[mesh_cntl_signals_q.io.deq.bits.a_bank].resp.bits.fromDMA, UInt<1>(0h0))
connect io.srams.read[mesh_cntl_signals_q.io.deq.bits.a_bank].resp.ready, _io_srams_read_resp_ready_T
node _T_134 = and(mesh.io.b.ready, mesh.io.b.valid)
node _T_135 = and(mesh_cntl_signals_q.io.deq.bits.b_fire, _T_134)
node _T_136 = eq(mesh_cntl_signals_q.io.deq.bits.b_garbage, UInt<1>(0h0))
node _T_137 = and(_T_135, _T_136)
node _T_138 = eq(mesh_cntl_signals_q.io.deq.bits.accumulate_zeros, UInt<1>(0h0))
node _T_139 = and(_T_137, _T_138)
node _T_140 = gt(mesh_cntl_signals_q.io.deq.bits.b_unpadded_cols, UInt<1>(0h0))
node _T_141 = and(_T_139, _T_140)
when _T_141 :
when mesh_cntl_signals_q.io.deq.bits.b_read_from_acc :
wire _WIRE_1 : UInt
connect _WIRE_1, UInt<1>(0h0)
wire _io_acc_read_resp_ready_WIRE_1 : UInt
connect _io_acc_read_resp_ready_WIRE_1, UInt<1>(0h0)
node _io_acc_read_resp_ready_T_1 = eq(io.acc.read_resp[_io_acc_read_resp_ready_WIRE_1].bits.fromDMA, UInt<1>(0h0))
connect io.acc.read_resp[_WIRE_1].ready, _io_acc_read_resp_ready_T_1
else :
node _io_srams_read_resp_ready_T_1 = eq(io.srams.read[mesh_cntl_signals_q.io.deq.bits.b_bank].resp.bits.fromDMA, UInt<1>(0h0))
connect io.srams.read[mesh_cntl_signals_q.io.deq.bits.b_bank].resp.ready, _io_srams_read_resp_ready_T_1
node _T_142 = and(mesh.io.d.ready, mesh.io.d.valid)
node _T_143 = and(mesh_cntl_signals_q.io.deq.bits.d_fire, _T_142)
node _T_144 = eq(mesh_cntl_signals_q.io.deq.bits.d_garbage, UInt<1>(0h0))
node _T_145 = and(_T_143, _T_144)
node _T_146 = eq(mesh_cntl_signals_q.io.deq.bits.preload_zeros, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = gt(mesh_cntl_signals_q.io.deq.bits.d_unpadded_cols, UInt<1>(0h0))
node _T_149 = and(_T_147, _T_148)
when _T_149 :
when mesh_cntl_signals_q.io.deq.bits.d_read_from_acc :
wire _WIRE_2 : UInt
connect _WIRE_2, UInt<1>(0h0)
wire _io_acc_read_resp_ready_WIRE_2 : UInt
connect _io_acc_read_resp_ready_WIRE_2, UInt<1>(0h0)
node _io_acc_read_resp_ready_T_2 = eq(io.acc.read_resp[_io_acc_read_resp_ready_WIRE_2].bits.fromDMA, UInt<1>(0h0))
connect io.acc.read_resp[_WIRE_2].ready, _io_acc_read_resp_ready_T_2
else :
node _io_srams_read_resp_ready_T_2 = eq(io.srams.read[mesh_cntl_signals_q.io.deq.bits.d_bank].resp.bits.fromDMA, UInt<1>(0h0))
connect io.srams.read[mesh_cntl_signals_q.io.deq.bits.d_bank].resp.ready, _io_srams_read_resp_ready_T_2
when mesh_cntl_signals_q.io.deq.valid :
node _mesh_io_a_valid_T = and(mesh_cntl_signals_q.io.deq.bits.a_fire, dataA_valid)
connect mesh.io.a.valid, _mesh_io_a_valid_T
node _mesh_io_b_valid_T = and(mesh_cntl_signals_q.io.deq.bits.b_fire, dataB_valid)
connect mesh.io.b.valid, _mesh_io_b_valid_T
node _mesh_io_d_valid_T = and(mesh_cntl_signals_q.io.deq.bits.d_fire, dataD_valid)
connect mesh.io.d.valid, _mesh_io_d_valid_T
wire _WIRE_3 : { bits : UInt<32>}[1][4]
node lo = cat(dataA[1].bits, dataA[0].bits)
node hi = cat(dataA[3].bits, dataA[2].bits)
node _T_150 = cat(hi, lo)
wire _WIRE_4 : UInt<128>
connect _WIRE_4, _T_150
node _T_151 = bits(_WIRE_4, 31, 0)
connect _WIRE_3[0][0].bits, _T_151
node _T_152 = bits(_WIRE_4, 63, 32)
connect _WIRE_3[1][0].bits, _T_152
node _T_153 = bits(_WIRE_4, 95, 64)
connect _WIRE_3[2][0].bits, _T_153
node _T_154 = bits(_WIRE_4, 127, 96)
connect _WIRE_3[3][0].bits, _T_154
connect mesh.io.a.bits[0][0].bits, _WIRE_3[0][0].bits
connect mesh.io.a.bits[1][0].bits, _WIRE_3[1][0].bits
connect mesh.io.a.bits[2][0].bits, _WIRE_3[2][0].bits
connect mesh.io.a.bits[3][0].bits, _WIRE_3[3][0].bits
wire _WIRE_5 : { bits : UInt<32>}[1][4]
node lo_1 = cat(dataB[1].bits, dataB[0].bits)
node hi_1 = cat(dataB[3].bits, dataB[2].bits)
node _T_155 = cat(hi_1, lo_1)
wire _WIRE_6 : UInt<128>
connect _WIRE_6, _T_155
node _T_156 = bits(_WIRE_6, 31, 0)
connect _WIRE_5[0][0].bits, _T_156
node _T_157 = bits(_WIRE_6, 63, 32)
connect _WIRE_5[1][0].bits, _T_157
node _T_158 = bits(_WIRE_6, 95, 64)
connect _WIRE_5[2][0].bits, _T_158
node _T_159 = bits(_WIRE_6, 127, 96)
connect _WIRE_5[3][0].bits, _T_159
connect mesh.io.b.bits[0][0].bits, _WIRE_5[0][0].bits
connect mesh.io.b.bits[1][0].bits, _WIRE_5[1][0].bits
connect mesh.io.b.bits[2][0].bits, _WIRE_5[2][0].bits
connect mesh.io.b.bits[3][0].bits, _WIRE_5[3][0].bits
wire _WIRE_7 : { bits : UInt<32>}[1][4]
node lo_2 = cat(dataD[1].bits, dataD[0].bits)
node hi_2 = cat(dataD[3].bits, dataD[2].bits)
node _T_160 = cat(hi_2, lo_2)
wire _WIRE_8 : UInt<128>
connect _WIRE_8, _T_160
node _T_161 = bits(_WIRE_8, 31, 0)
connect _WIRE_7[0][0].bits, _T_161
node _T_162 = bits(_WIRE_8, 63, 32)
connect _WIRE_7[1][0].bits, _T_162
node _T_163 = bits(_WIRE_8, 95, 64)
connect _WIRE_7[2][0].bits, _T_163
node _T_164 = bits(_WIRE_8, 127, 96)
connect _WIRE_7[3][0].bits, _T_164
connect mesh.io.d.bits[0][0].bits, _WIRE_7[0][0].bits
connect mesh.io.d.bits[1][0].bits, _WIRE_7[1][0].bits
connect mesh.io.d.bits[2][0].bits, _WIRE_7[2][0].bits
connect mesh.io.d.bits[3][0].bits, _WIRE_7[3][0].bits
node _mesh_io_req_valid_T_1 = and(mesh_cntl_signals_q.io.deq.ready, mesh_cntl_signals_q.io.deq.valid)
node _mesh_io_req_valid_T_2 = or(mesh_cntl_signals_q.io.deq.bits.a_fire, mesh_cntl_signals_q.io.deq.bits.b_fire)
node _mesh_io_req_valid_T_3 = or(_mesh_io_req_valid_T_2, mesh_cntl_signals_q.io.deq.bits.d_fire)
node _mesh_io_req_valid_T_4 = and(_mesh_io_req_valid_T_1, _mesh_io_req_valid_T_3)
connect mesh.io.req.valid, _mesh_io_req_valid_T_4
connect mesh.io.req.bits.tag.addr.data, mesh_cntl_signals_q.io.deq.bits.c_addr.data
connect mesh.io.req.bits.tag.addr.garbage_bit, mesh_cntl_signals_q.io.deq.bits.c_addr.garbage_bit
connect mesh.io.req.bits.tag.addr.garbage, mesh_cntl_signals_q.io.deq.bits.c_addr.garbage
connect mesh.io.req.bits.tag.addr.norm_cmd, mesh_cntl_signals_q.io.deq.bits.c_addr.norm_cmd
connect mesh.io.req.bits.tag.addr.read_full_acc_row, mesh_cntl_signals_q.io.deq.bits.c_addr.read_full_acc_row
connect mesh.io.req.bits.tag.addr.accumulate, mesh_cntl_signals_q.io.deq.bits.c_addr.accumulate
connect mesh.io.req.bits.tag.addr.is_acc_addr, mesh_cntl_signals_q.io.deq.bits.c_addr.is_acc_addr
connect mesh.io.req.bits.total_rows, mesh_cntl_signals_q.io.deq.bits.total_rows
node _T_165 = and(mesh_cntl_signals_q.io.deq.valid, mesh_cntl_signals_q.io.deq.bits.perform_single_preload)
when _T_165 :
node lo_3 = cat(dataA[1].bits, dataA[0].bits)
node hi_3 = cat(dataA[3].bits, dataA[2].bits)
node _T_166 = cat(hi_3, lo_3)
node _T_167 = mux(a_should_be_fed_into_transposer, _T_166, UInt<1>(0h0))
wire _WIRE_9 : { bits : UInt<32>}[1][4]
wire _WIRE_10 : UInt<128>
connect _WIRE_10, _T_167
node _T_168 = bits(_WIRE_10, 31, 0)
connect _WIRE_9[0][0].bits, _T_168
node _T_169 = bits(_WIRE_10, 63, 32)
connect _WIRE_9[1][0].bits, _T_169
node _T_170 = bits(_WIRE_10, 95, 64)
connect _WIRE_9[2][0].bits, _T_170
node _T_171 = bits(_WIRE_10, 127, 96)
connect _WIRE_9[3][0].bits, _T_171
connect mesh.io.a.bits[0][0].bits, _WIRE_9[0][0].bits
connect mesh.io.a.bits[1][0].bits, _WIRE_9[1][0].bits
connect mesh.io.a.bits[2][0].bits, _WIRE_9[2][0].bits
connect mesh.io.a.bits[3][0].bits, _WIRE_9[3][0].bits
node lo_4 = cat(dataB[1].bits, dataB[0].bits)
node hi_4 = cat(dataB[3].bits, dataB[2].bits)
node _T_172 = cat(hi_4, lo_4)
node _T_173 = mux(b_should_be_fed_into_transposer, _T_172, UInt<1>(0h0))
wire _WIRE_11 : { bits : UInt<32>}[1][4]
wire _WIRE_12 : UInt<128>
connect _WIRE_12, _T_173
node _T_174 = bits(_WIRE_12, 31, 0)
connect _WIRE_11[0][0].bits, _T_174
node _T_175 = bits(_WIRE_12, 63, 32)
connect _WIRE_11[1][0].bits, _T_175
node _T_176 = bits(_WIRE_12, 95, 64)
connect _WIRE_11[2][0].bits, _T_176
node _T_177 = bits(_WIRE_12, 127, 96)
connect _WIRE_11[3][0].bits, _T_177
connect mesh.io.b.bits[0][0].bits, _WIRE_11[0][0].bits
connect mesh.io.b.bits[1][0].bits, _WIRE_11[1][0].bits
connect mesh.io.b.bits[2][0].bits, _WIRE_11[2][0].bits
connect mesh.io.b.bits[3][0].bits, _WIRE_11[3][0].bits
node _T_178 = and(mesh_cntl_signals_q.io.deq.valid, mesh_cntl_signals_q.io.deq.bits.perform_single_mul)
when _T_178 :
node lo_5 = cat(dataA[1].bits, dataA[0].bits)
node hi_5 = cat(dataA[3].bits, dataA[2].bits)
node _T_179 = cat(hi_5, lo_5)
node _T_180 = mux(a_should_be_fed_into_transposer, UInt<1>(0h0), _T_179)
wire _WIRE_13 : { bits : UInt<32>}[1][4]
wire _WIRE_14 : UInt<128>
connect _WIRE_14, _T_180
node _T_181 = bits(_WIRE_14, 31, 0)
connect _WIRE_13[0][0].bits, _T_181
node _T_182 = bits(_WIRE_14, 63, 32)
connect _WIRE_13[1][0].bits, _T_182
node _T_183 = bits(_WIRE_14, 95, 64)
connect _WIRE_13[2][0].bits, _T_183
node _T_184 = bits(_WIRE_14, 127, 96)
connect _WIRE_13[3][0].bits, _T_184
connect mesh.io.a.bits[0][0].bits, _WIRE_13[0][0].bits
connect mesh.io.a.bits[1][0].bits, _WIRE_13[1][0].bits
connect mesh.io.a.bits[2][0].bits, _WIRE_13[2][0].bits
connect mesh.io.a.bits[3][0].bits, _WIRE_13[3][0].bits
node lo_6 = cat(dataB[1].bits, dataB[0].bits)
node hi_6 = cat(dataB[3].bits, dataB[2].bits)
node _T_185 = cat(hi_6, lo_6)
node _T_186 = mux(b_should_be_fed_into_transposer, UInt<1>(0h0), _T_185)
wire _WIRE_15 : { bits : UInt<32>}[1][4]
wire _WIRE_16 : UInt<128>
connect _WIRE_16, _T_186
node _T_187 = bits(_WIRE_16, 31, 0)
connect _WIRE_15[0][0].bits, _T_187
node _T_188 = bits(_WIRE_16, 63, 32)
connect _WIRE_15[1][0].bits, _T_188
node _T_189 = bits(_WIRE_16, 95, 64)
connect _WIRE_15[2][0].bits, _T_189
node _T_190 = bits(_WIRE_16, 127, 96)
connect _WIRE_15[3][0].bits, _T_190
connect mesh.io.b.bits[0][0].bits, _WIRE_15[0][0].bits
connect mesh.io.b.bits[1][0].bits, _WIRE_15[1][0].bits
connect mesh.io.b.bits[2][0].bits, _WIRE_15[2][0].bits
connect mesh.io.b.bits[3][0].bits, _WIRE_15[3][0].bits
connect mesh.io.req.bits.tag.addr.is_acc_addr, UInt<1>(0h1)
connect mesh.io.req.bits.tag.addr.accumulate, UInt<1>(0h1)
connect mesh.io.req.bits.tag.addr.read_full_acc_row, UInt<1>(0h1)
connect mesh.io.req.bits.tag.addr.garbage_bit, UInt<1>(0h1)
node _mesh_io_req_bits_tag_addr_data_T = not(UInt<14>(0h0))
connect mesh.io.req.bits.tag.addr.data, _mesh_io_req_bits_tag_addr_data_T
regreset output_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _w_address_T = eq(current_dataflow, UInt<1>(0h1))
node _w_address_T_1 = mul(output_counter, c_addr_stride)
wire w_address_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
connect w_address_result, mesh.io.resp.bits.tag.addr
node _w_address_result_data_T = add(mesh.io.resp.bits.tag.addr.data, _w_address_T_1)
node _w_address_result_data_T_1 = tail(_w_address_result_data_T, 1)
connect w_address_result.data, _w_address_result_data_T_1
node _w_address_T_2 = sub(mesh.io.resp.bits.total_rows, UInt<1>(0h1))
node _w_address_T_3 = tail(_w_address_T_2, 1)
node _w_address_T_4 = mul(output_counter, c_addr_stride)
node _w_address_T_5 = sub(_w_address_T_3, _w_address_T_4)
node _w_address_T_6 = tail(_w_address_T_5, 1)
wire w_address_result_1 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
connect w_address_result_1, mesh.io.resp.bits.tag.addr
node _w_address_result_data_T_2 = add(mesh.io.resp.bits.tag.addr.data, _w_address_T_6)
node _w_address_result_data_T_3 = tail(_w_address_result_data_T_2, 1)
connect w_address_result_1.data, _w_address_result_data_T_3
node w_address = mux(_w_address_T, w_address_result, w_address_result_1)
node _w_bank_T = bits(w_address.data, 13, 12)
node w_bank = mux(w_address.is_acc_addr, UInt<1>(0h0), _w_bank_T)
node _w_row_T = bits(w_address.data, 11, 0)
node _w_row_T_1 = bits(w_address.data, 11, 0)
node w_row = mux(w_address.is_acc_addr, _w_row_T, _w_row_T_1)
node _is_garbage_addr_T = and(mesh.io.resp.bits.tag.addr.is_acc_addr, mesh.io.resp.bits.tag.addr.accumulate)
node _is_garbage_addr_T_1 = and(_is_garbage_addr_T, mesh.io.resp.bits.tag.addr.read_full_acc_row)
node _is_garbage_addr_T_2 = andr(mesh.io.resp.bits.tag.addr.data)
node _is_garbage_addr_T_3 = and(_is_garbage_addr_T_1, _is_garbage_addr_T_2)
node _is_garbage_addr_T_4 = bits(mesh.io.resp.bits.tag.addr.garbage_bit, 0, 0)
node is_garbage_addr = and(_is_garbage_addr_T_3, _is_garbage_addr_T_4)
node _write_this_row_T = eq(current_dataflow, UInt<1>(0h1))
node _write_this_row_T_1 = lt(output_counter, mesh.io.resp.bits.tag.rows)
node _write_this_row_T_2 = sub(mesh.io.resp.bits.total_rows, UInt<1>(0h1))
node _write_this_row_T_3 = tail(_write_this_row_T_2, 1)
node _write_this_row_T_4 = sub(_write_this_row_T_3, output_counter)
node _write_this_row_T_5 = tail(_write_this_row_T_4, 1)
node _write_this_row_T_6 = lt(_write_this_row_T_5, mesh.io.resp.bits.tag.rows)
node write_this_row = mux(_write_this_row_T, _write_this_row_T_1, _write_this_row_T_6)
node w_mask_0 = lt(UInt<1>(0h0), mesh.io.resp.bits.tag.cols)
node w_mask_1 = lt(UInt<1>(0h1), mesh.io.resp.bits.tag.cols)
node w_mask_2 = lt(UInt<2>(0h2), mesh.io.resp.bits.tag.cols)
node w_mask_3 = lt(UInt<2>(0h3), mesh.io.resp.bits.tag.cols)
node activated_wdata_e_clipped_self_rec_rawIn_sign = bits(mesh.io.resp.bits.data[0][0].bits, 31, 31)
node activated_wdata_e_clipped_self_rec_rawIn_expIn = bits(mesh.io.resp.bits.data[0][0].bits, 30, 23)
node activated_wdata_e_clipped_self_rec_rawIn_fractIn = bits(mesh.io.resp.bits.data[0][0].bits, 22, 0)
node activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn = eq(activated_wdata_e_clipped_self_rec_rawIn_expIn, UInt<1>(0h0))
node activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn = eq(activated_wdata_e_clipped_self_rec_rawIn_fractIn, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 0, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_1 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 1, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_2 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 2, 2)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_3 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 3, 3)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_4 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 4, 4)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_5 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 5, 5)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_6 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 6, 6)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_7 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 7, 7)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_8 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 8, 8)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_9 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 9, 9)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_10 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 10, 10)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_11 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 11, 11)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_12 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 12, 12)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_13 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 13, 13)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_14 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 14, 14)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_15 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 15, 15)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_16 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 16, 16)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_17 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 17, 17)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_18 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 18, 18)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_19 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 19, 19)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_20 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 20, 20)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_21 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 21, 21)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_22 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn, 22, 22)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_23 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_24 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_23)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_25 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_24)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_26 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_25)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_27 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_26)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_28 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_27)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_29 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_28)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_30 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_29)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_31 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_30)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_32 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_31)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_33 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_32)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_34 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_33)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_35 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_34)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_36 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_35)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_37 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_36)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_38 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_37)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_39 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_38)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_40 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_39)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_41 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_40)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_42 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_41)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_43 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_42)
node activated_wdata_e_clipped_self_rec_rawIn_normDist = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_43)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T = dshl(activated_wdata_e_clipped_self_rec_rawIn_fractIn, activated_wdata_e_clipped_self_rec_rawIn_normDist)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_1 = bits(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T, 21, 0)
node activated_wdata_e_clipped_self_rec_rawIn_subnormFract = shl(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_1, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T = xor(activated_wdata_e_clipped_self_rec_rawIn_normDist, UInt<9>(0h1ff))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_1 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T, activated_wdata_e_clipped_self_rec_rawIn_expIn)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_2 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_2)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_4 = add(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_1, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_3)
node activated_wdata_e_clipped_self_rec_rawIn_adjustedExp = tail(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_4, 1)
node activated_wdata_e_clipped_self_rec_rawIn_isZero = and(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn)
node _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp, 8, 7)
node activated_wdata_e_clipped_self_rec_rawIn_isSpecial = eq(_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T, UInt<2>(0h3))
wire activated_wdata_e_clipped_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T = eq(activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_1 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T)
connect activated_wdata_e_clipped_self_rec_rawIn.isNaN, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_1
node _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn)
connect activated_wdata_e_clipped_self_rec_rawIn.isInf, _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T
connect activated_wdata_e_clipped_self_rec_rawIn.isZero, activated_wdata_e_clipped_self_rec_rawIn_isZero
connect activated_wdata_e_clipped_self_rec_rawIn.sign, activated_wdata_e_clipped_self_rec_rawIn_sign
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp, 8, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_1 = cvt(_activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T)
connect activated_wdata_e_clipped_self_rec_rawIn.sExp, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_1
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T = eq(activated_wdata_e_clipped_self_rec_rawIn_isZero, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_2 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn, activated_wdata_e_clipped_self_rec_rawIn_subnormFract, activated_wdata_e_clipped_self_rec_rawIn_fractIn)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_3 = cat(_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_1, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_2)
connect activated_wdata_e_clipped_self_rec_rawIn.sig, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_3
node _activated_wdata_e_clipped_self_rec_T = bits(activated_wdata_e_clipped_self_rec_rawIn.sExp, 8, 6)
node _activated_wdata_e_clipped_self_rec_T_1 = mux(activated_wdata_e_clipped_self_rec_rawIn.isZero, UInt<3>(0h0), _activated_wdata_e_clipped_self_rec_T)
node _activated_wdata_e_clipped_self_rec_T_2 = mux(activated_wdata_e_clipped_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_T_3 = or(_activated_wdata_e_clipped_self_rec_T_1, _activated_wdata_e_clipped_self_rec_T_2)
node _activated_wdata_e_clipped_self_rec_T_4 = cat(activated_wdata_e_clipped_self_rec_rawIn.sign, _activated_wdata_e_clipped_self_rec_T_3)
node _activated_wdata_e_clipped_self_rec_T_5 = bits(activated_wdata_e_clipped_self_rec_rawIn.sExp, 5, 0)
node _activated_wdata_e_clipped_self_rec_T_6 = cat(_activated_wdata_e_clipped_self_rec_T_4, _activated_wdata_e_clipped_self_rec_T_5)
node _activated_wdata_e_clipped_self_rec_T_7 = bits(activated_wdata_e_clipped_self_rec_rawIn.sig, 22, 0)
node activated_wdata_e_clipped_self_rec = cat(_activated_wdata_e_clipped_self_rec_T_6, _activated_wdata_e_clipped_self_rec_T_7)
inst activated_wdata_e_clipped_resizer of RecFNToRecFN_240
connect activated_wdata_e_clipped_resizer.io.in, activated_wdata_e_clipped_self_rec
connect activated_wdata_e_clipped_resizer.io.roundingMode, UInt<3>(0h0)
connect activated_wdata_e_clipped_resizer.io.detectTininess, UInt<1>(0h1)
wire activated_wdata_e_clipped : { bits : UInt<32>}
node activated_wdata_e_clipped_result_bits_rawIn_exp = bits(activated_wdata_e_clipped_resizer.io.out, 31, 23)
node _activated_wdata_e_clipped_result_bits_rawIn_isZero_T = bits(activated_wdata_e_clipped_result_bits_rawIn_exp, 8, 6)
node activated_wdata_e_clipped_result_bits_rawIn_isZero = eq(_activated_wdata_e_clipped_result_bits_rawIn_isZero_T, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T = bits(activated_wdata_e_clipped_result_bits_rawIn_exp, 8, 7)
node activated_wdata_e_clipped_result_bits_rawIn_isSpecial = eq(_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T, UInt<2>(0h3))
wire activated_wdata_e_clipped_result_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T = bits(activated_wdata_e_clipped_result_bits_rawIn_exp, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_1 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T)
connect activated_wdata_e_clipped_result_bits_rawIn.isNaN, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_1
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T = bits(activated_wdata_e_clipped_result_bits_rawIn_exp, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_1 = eq(_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_2 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_1)
connect activated_wdata_e_clipped_result_bits_rawIn.isInf, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_2
connect activated_wdata_e_clipped_result_bits_rawIn.isZero, activated_wdata_e_clipped_result_bits_rawIn_isZero
node _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T = bits(activated_wdata_e_clipped_resizer.io.out, 32, 32)
connect activated_wdata_e_clipped_result_bits_rawIn.sign, _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T
node _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T = cvt(activated_wdata_e_clipped_result_bits_rawIn_exp)
connect activated_wdata_e_clipped_result_bits_rawIn.sExp, _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T = eq(activated_wdata_e_clipped_result_bits_rawIn_isZero, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_2 = bits(activated_wdata_e_clipped_resizer.io.out, 22, 0)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_3 = cat(_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_1, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_2)
connect activated_wdata_e_clipped_result_bits_rawIn.sig, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_3
node activated_wdata_e_clipped_result_bits_isSubnormal = lt(activated_wdata_e_clipped_result_bits_rawIn.sExp, asSInt(UInt<9>(0h82)))
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T = bits(activated_wdata_e_clipped_result_bits_rawIn.sExp, 4, 0)
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _activated_wdata_e_clipped_result_bits_denormShiftDist_T)
node activated_wdata_e_clipped_result_bits_denormShiftDist = tail(_activated_wdata_e_clipped_result_bits_denormShiftDist_T_1, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T = shr(activated_wdata_e_clipped_result_bits_rawIn.sig, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_1 = dshr(_activated_wdata_e_clipped_result_bits_denormFract_T, activated_wdata_e_clipped_result_bits_denormShiftDist)
node activated_wdata_e_clipped_result_bits_denormFract = bits(_activated_wdata_e_clipped_result_bits_denormFract_T_1, 22, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T = bits(activated_wdata_e_clipped_result_bits_rawIn.sExp, 7, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_1 = sub(_activated_wdata_e_clipped_result_bits_expOut_T, UInt<8>(0h81))
node _activated_wdata_e_clipped_result_bits_expOut_T_2 = tail(_activated_wdata_e_clipped_result_bits_expOut_T_1, 1)
node _activated_wdata_e_clipped_result_bits_expOut_T_3 = mux(activated_wdata_e_clipped_result_bits_isSubnormal, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_expOut_T_2)
node _activated_wdata_e_clipped_result_bits_expOut_T_4 = or(activated_wdata_e_clipped_result_bits_rawIn.isNaN, activated_wdata_e_clipped_result_bits_rawIn.isInf)
node _activated_wdata_e_clipped_result_bits_expOut_T_5 = mux(_activated_wdata_e_clipped_result_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0))
node activated_wdata_e_clipped_result_bits_expOut = or(_activated_wdata_e_clipped_result_bits_expOut_T_3, _activated_wdata_e_clipped_result_bits_expOut_T_5)
node _activated_wdata_e_clipped_result_bits_fractOut_T = bits(activated_wdata_e_clipped_result_bits_rawIn.sig, 22, 0)
node _activated_wdata_e_clipped_result_bits_fractOut_T_1 = mux(activated_wdata_e_clipped_result_bits_rawIn.isInf, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_fractOut_T)
node activated_wdata_e_clipped_result_bits_fractOut = mux(activated_wdata_e_clipped_result_bits_isSubnormal, activated_wdata_e_clipped_result_bits_denormFract, _activated_wdata_e_clipped_result_bits_fractOut_T_1)
node activated_wdata_e_clipped_result_bits_hi = cat(activated_wdata_e_clipped_result_bits_rawIn.sign, activated_wdata_e_clipped_result_bits_expOut)
node _activated_wdata_e_clipped_result_bits_T = cat(activated_wdata_e_clipped_result_bits_hi, activated_wdata_e_clipped_result_bits_fractOut)
connect activated_wdata_e_clipped.bits, _activated_wdata_e_clipped_result_bits_T
node _activated_wdata_e_act_T = eq(activation, UInt<1>(0h1))
node activated_wdata_e_act_raw_sign = bits(activated_wdata_e_clipped.bits, 31, 31)
node activated_wdata_e_act_raw_expIn = bits(activated_wdata_e_clipped.bits, 30, 23)
node activated_wdata_e_act_raw_fractIn = bits(activated_wdata_e_clipped.bits, 22, 0)
node activated_wdata_e_act_raw_isZeroExpIn = eq(activated_wdata_e_act_raw_expIn, UInt<1>(0h0))
node activated_wdata_e_act_raw_isZeroFractIn = eq(activated_wdata_e_act_raw_fractIn, UInt<1>(0h0))
node _activated_wdata_e_act_raw_normDist_T = bits(activated_wdata_e_act_raw_fractIn, 0, 0)
node _activated_wdata_e_act_raw_normDist_T_1 = bits(activated_wdata_e_act_raw_fractIn, 1, 1)
node _activated_wdata_e_act_raw_normDist_T_2 = bits(activated_wdata_e_act_raw_fractIn, 2, 2)
node _activated_wdata_e_act_raw_normDist_T_3 = bits(activated_wdata_e_act_raw_fractIn, 3, 3)
node _activated_wdata_e_act_raw_normDist_T_4 = bits(activated_wdata_e_act_raw_fractIn, 4, 4)
node _activated_wdata_e_act_raw_normDist_T_5 = bits(activated_wdata_e_act_raw_fractIn, 5, 5)
node _activated_wdata_e_act_raw_normDist_T_6 = bits(activated_wdata_e_act_raw_fractIn, 6, 6)
node _activated_wdata_e_act_raw_normDist_T_7 = bits(activated_wdata_e_act_raw_fractIn, 7, 7)
node _activated_wdata_e_act_raw_normDist_T_8 = bits(activated_wdata_e_act_raw_fractIn, 8, 8)
node _activated_wdata_e_act_raw_normDist_T_9 = bits(activated_wdata_e_act_raw_fractIn, 9, 9)
node _activated_wdata_e_act_raw_normDist_T_10 = bits(activated_wdata_e_act_raw_fractIn, 10, 10)
node _activated_wdata_e_act_raw_normDist_T_11 = bits(activated_wdata_e_act_raw_fractIn, 11, 11)
node _activated_wdata_e_act_raw_normDist_T_12 = bits(activated_wdata_e_act_raw_fractIn, 12, 12)
node _activated_wdata_e_act_raw_normDist_T_13 = bits(activated_wdata_e_act_raw_fractIn, 13, 13)
node _activated_wdata_e_act_raw_normDist_T_14 = bits(activated_wdata_e_act_raw_fractIn, 14, 14)
node _activated_wdata_e_act_raw_normDist_T_15 = bits(activated_wdata_e_act_raw_fractIn, 15, 15)
node _activated_wdata_e_act_raw_normDist_T_16 = bits(activated_wdata_e_act_raw_fractIn, 16, 16)
node _activated_wdata_e_act_raw_normDist_T_17 = bits(activated_wdata_e_act_raw_fractIn, 17, 17)
node _activated_wdata_e_act_raw_normDist_T_18 = bits(activated_wdata_e_act_raw_fractIn, 18, 18)
node _activated_wdata_e_act_raw_normDist_T_19 = bits(activated_wdata_e_act_raw_fractIn, 19, 19)
node _activated_wdata_e_act_raw_normDist_T_20 = bits(activated_wdata_e_act_raw_fractIn, 20, 20)
node _activated_wdata_e_act_raw_normDist_T_21 = bits(activated_wdata_e_act_raw_fractIn, 21, 21)
node _activated_wdata_e_act_raw_normDist_T_22 = bits(activated_wdata_e_act_raw_fractIn, 22, 22)
node _activated_wdata_e_act_raw_normDist_T_23 = mux(_activated_wdata_e_act_raw_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_act_raw_normDist_T_24 = mux(_activated_wdata_e_act_raw_normDist_T_2, UInt<5>(0h14), _activated_wdata_e_act_raw_normDist_T_23)
node _activated_wdata_e_act_raw_normDist_T_25 = mux(_activated_wdata_e_act_raw_normDist_T_3, UInt<5>(0h13), _activated_wdata_e_act_raw_normDist_T_24)
node _activated_wdata_e_act_raw_normDist_T_26 = mux(_activated_wdata_e_act_raw_normDist_T_4, UInt<5>(0h12), _activated_wdata_e_act_raw_normDist_T_25)
node _activated_wdata_e_act_raw_normDist_T_27 = mux(_activated_wdata_e_act_raw_normDist_T_5, UInt<5>(0h11), _activated_wdata_e_act_raw_normDist_T_26)
node _activated_wdata_e_act_raw_normDist_T_28 = mux(_activated_wdata_e_act_raw_normDist_T_6, UInt<5>(0h10), _activated_wdata_e_act_raw_normDist_T_27)
node _activated_wdata_e_act_raw_normDist_T_29 = mux(_activated_wdata_e_act_raw_normDist_T_7, UInt<4>(0hf), _activated_wdata_e_act_raw_normDist_T_28)
node _activated_wdata_e_act_raw_normDist_T_30 = mux(_activated_wdata_e_act_raw_normDist_T_8, UInt<4>(0he), _activated_wdata_e_act_raw_normDist_T_29)
node _activated_wdata_e_act_raw_normDist_T_31 = mux(_activated_wdata_e_act_raw_normDist_T_9, UInt<4>(0hd), _activated_wdata_e_act_raw_normDist_T_30)
node _activated_wdata_e_act_raw_normDist_T_32 = mux(_activated_wdata_e_act_raw_normDist_T_10, UInt<4>(0hc), _activated_wdata_e_act_raw_normDist_T_31)
node _activated_wdata_e_act_raw_normDist_T_33 = mux(_activated_wdata_e_act_raw_normDist_T_11, UInt<4>(0hb), _activated_wdata_e_act_raw_normDist_T_32)
node _activated_wdata_e_act_raw_normDist_T_34 = mux(_activated_wdata_e_act_raw_normDist_T_12, UInt<4>(0ha), _activated_wdata_e_act_raw_normDist_T_33)
node _activated_wdata_e_act_raw_normDist_T_35 = mux(_activated_wdata_e_act_raw_normDist_T_13, UInt<4>(0h9), _activated_wdata_e_act_raw_normDist_T_34)
node _activated_wdata_e_act_raw_normDist_T_36 = mux(_activated_wdata_e_act_raw_normDist_T_14, UInt<4>(0h8), _activated_wdata_e_act_raw_normDist_T_35)
node _activated_wdata_e_act_raw_normDist_T_37 = mux(_activated_wdata_e_act_raw_normDist_T_15, UInt<3>(0h7), _activated_wdata_e_act_raw_normDist_T_36)
node _activated_wdata_e_act_raw_normDist_T_38 = mux(_activated_wdata_e_act_raw_normDist_T_16, UInt<3>(0h6), _activated_wdata_e_act_raw_normDist_T_37)
node _activated_wdata_e_act_raw_normDist_T_39 = mux(_activated_wdata_e_act_raw_normDist_T_17, UInt<3>(0h5), _activated_wdata_e_act_raw_normDist_T_38)
node _activated_wdata_e_act_raw_normDist_T_40 = mux(_activated_wdata_e_act_raw_normDist_T_18, UInt<3>(0h4), _activated_wdata_e_act_raw_normDist_T_39)
node _activated_wdata_e_act_raw_normDist_T_41 = mux(_activated_wdata_e_act_raw_normDist_T_19, UInt<2>(0h3), _activated_wdata_e_act_raw_normDist_T_40)
node _activated_wdata_e_act_raw_normDist_T_42 = mux(_activated_wdata_e_act_raw_normDist_T_20, UInt<2>(0h2), _activated_wdata_e_act_raw_normDist_T_41)
node _activated_wdata_e_act_raw_normDist_T_43 = mux(_activated_wdata_e_act_raw_normDist_T_21, UInt<1>(0h1), _activated_wdata_e_act_raw_normDist_T_42)
node activated_wdata_e_act_raw_normDist = mux(_activated_wdata_e_act_raw_normDist_T_22, UInt<1>(0h0), _activated_wdata_e_act_raw_normDist_T_43)
node _activated_wdata_e_act_raw_subnormFract_T = dshl(activated_wdata_e_act_raw_fractIn, activated_wdata_e_act_raw_normDist)
node _activated_wdata_e_act_raw_subnormFract_T_1 = bits(_activated_wdata_e_act_raw_subnormFract_T, 21, 0)
node activated_wdata_e_act_raw_subnormFract = shl(_activated_wdata_e_act_raw_subnormFract_T_1, 1)
node _activated_wdata_e_act_raw_adjustedExp_T = xor(activated_wdata_e_act_raw_normDist, UInt<9>(0h1ff))
node _activated_wdata_e_act_raw_adjustedExp_T_1 = mux(activated_wdata_e_act_raw_isZeroExpIn, _activated_wdata_e_act_raw_adjustedExp_T, activated_wdata_e_act_raw_expIn)
node _activated_wdata_e_act_raw_adjustedExp_T_2 = mux(activated_wdata_e_act_raw_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_act_raw_adjustedExp_T_3 = or(UInt<8>(0h80), _activated_wdata_e_act_raw_adjustedExp_T_2)
node _activated_wdata_e_act_raw_adjustedExp_T_4 = add(_activated_wdata_e_act_raw_adjustedExp_T_1, _activated_wdata_e_act_raw_adjustedExp_T_3)
node activated_wdata_e_act_raw_adjustedExp = tail(_activated_wdata_e_act_raw_adjustedExp_T_4, 1)
node activated_wdata_e_act_raw_isZero = and(activated_wdata_e_act_raw_isZeroExpIn, activated_wdata_e_act_raw_isZeroFractIn)
node _activated_wdata_e_act_raw_isSpecial_T = bits(activated_wdata_e_act_raw_adjustedExp, 8, 7)
node activated_wdata_e_act_raw_isSpecial = eq(_activated_wdata_e_act_raw_isSpecial_T, UInt<2>(0h3))
wire activated_wdata_e_act_raw : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_act_raw_out_isNaN_T = eq(activated_wdata_e_act_raw_isZeroFractIn, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_isNaN_T_1 = and(activated_wdata_e_act_raw_isSpecial, _activated_wdata_e_act_raw_out_isNaN_T)
connect activated_wdata_e_act_raw.isNaN, _activated_wdata_e_act_raw_out_isNaN_T_1
node _activated_wdata_e_act_raw_out_isInf_T = and(activated_wdata_e_act_raw_isSpecial, activated_wdata_e_act_raw_isZeroFractIn)
connect activated_wdata_e_act_raw.isInf, _activated_wdata_e_act_raw_out_isInf_T
connect activated_wdata_e_act_raw.isZero, activated_wdata_e_act_raw_isZero
connect activated_wdata_e_act_raw.sign, activated_wdata_e_act_raw_sign
node _activated_wdata_e_act_raw_out_sExp_T = bits(activated_wdata_e_act_raw_adjustedExp, 8, 0)
node _activated_wdata_e_act_raw_out_sExp_T_1 = cvt(_activated_wdata_e_act_raw_out_sExp_T)
connect activated_wdata_e_act_raw.sExp, _activated_wdata_e_act_raw_out_sExp_T_1
node _activated_wdata_e_act_raw_out_sig_T = eq(activated_wdata_e_act_raw_isZero, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_sig_T_1 = cat(UInt<1>(0h0), _activated_wdata_e_act_raw_out_sig_T)
node _activated_wdata_e_act_raw_out_sig_T_2 = mux(activated_wdata_e_act_raw_isZeroExpIn, activated_wdata_e_act_raw_subnormFract, activated_wdata_e_act_raw_fractIn)
node _activated_wdata_e_act_raw_out_sig_T_3 = cat(_activated_wdata_e_act_raw_out_sig_T_1, _activated_wdata_e_act_raw_out_sig_T_2)
connect activated_wdata_e_act_raw.sig, _activated_wdata_e_act_raw_out_sig_T_3
wire activated_wdata_e_act_result : { bits : UInt<32>}
node _activated_wdata_e_act_result_bits_T = eq(activated_wdata_e_act_raw.isZero, UInt<1>(0h0))
node _activated_wdata_e_act_result_bits_T_1 = and(_activated_wdata_e_act_result_bits_T, activated_wdata_e_act_raw.sign)
node _activated_wdata_e_act_result_bits_T_2 = mux(_activated_wdata_e_act_result_bits_T_1, UInt<1>(0h0), activated_wdata_e_clipped.bits)
connect activated_wdata_e_act_result.bits, _activated_wdata_e_act_result_bits_T_2
node activated_wdata_e_act = mux(_activated_wdata_e_act_T, activated_wdata_e_act_result, activated_wdata_e_clipped)
wire _activated_wdata_WIRE : { bits : UInt<32>}[1]
connect _activated_wdata_WIRE[0], activated_wdata_e_act
node activated_wdata_e_clipped_self_rec_rawIn_sign_1 = bits(mesh.io.resp.bits.data[1][0].bits, 31, 31)
node activated_wdata_e_clipped_self_rec_rawIn_expIn_1 = bits(mesh.io.resp.bits.data[1][0].bits, 30, 23)
node activated_wdata_e_clipped_self_rec_rawIn_fractIn_1 = bits(mesh.io.resp.bits.data[1][0].bits, 22, 0)
node activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_1 = eq(activated_wdata_e_clipped_self_rec_rawIn_expIn_1, UInt<1>(0h0))
node activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_1 = eq(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_44 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 0, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_45 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 1, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_46 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 2, 2)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_47 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 3, 3)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_48 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 4, 4)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_49 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 5, 5)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_50 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 6, 6)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_51 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 7, 7)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_52 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 8, 8)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_53 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 9, 9)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_54 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 10, 10)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_55 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 11, 11)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_56 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 12, 12)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_57 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 13, 13)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_58 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 14, 14)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_59 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 15, 15)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_60 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 16, 16)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_61 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 17, 17)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_62 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 18, 18)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_63 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 19, 19)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_64 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 20, 20)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_65 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 21, 21)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_66 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, 22, 22)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_67 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_45, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_68 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_46, UInt<5>(0h14), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_67)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_69 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_47, UInt<5>(0h13), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_68)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_70 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_48, UInt<5>(0h12), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_69)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_71 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_49, UInt<5>(0h11), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_70)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_72 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_50, UInt<5>(0h10), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_71)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_73 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_51, UInt<4>(0hf), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_72)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_74 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_52, UInt<4>(0he), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_73)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_75 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_53, UInt<4>(0hd), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_74)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_76 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_54, UInt<4>(0hc), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_75)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_77 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_55, UInt<4>(0hb), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_76)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_78 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_56, UInt<4>(0ha), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_77)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_79 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_57, UInt<4>(0h9), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_78)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_80 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_58, UInt<4>(0h8), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_79)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_81 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_59, UInt<3>(0h7), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_80)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_82 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_60, UInt<3>(0h6), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_81)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_83 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_61, UInt<3>(0h5), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_82)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_84 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_62, UInt<3>(0h4), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_83)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_85 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_63, UInt<2>(0h3), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_84)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_86 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_64, UInt<2>(0h2), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_85)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_87 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_65, UInt<1>(0h1), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_86)
node activated_wdata_e_clipped_self_rec_rawIn_normDist_1 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_66, UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_87)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_2 = dshl(activated_wdata_e_clipped_self_rec_rawIn_fractIn_1, activated_wdata_e_clipped_self_rec_rawIn_normDist_1)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_3 = bits(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_2, 21, 0)
node activated_wdata_e_clipped_self_rec_rawIn_subnormFract_1 = shl(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_3, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_5 = xor(activated_wdata_e_clipped_self_rec_rawIn_normDist_1, UInt<9>(0h1ff))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_6 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_1, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_5, activated_wdata_e_clipped_self_rec_rawIn_expIn_1)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_7 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_7)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_9 = add(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_6, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_8)
node activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_1 = tail(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_9, 1)
node activated_wdata_e_clipped_self_rec_rawIn_isZero_1 = and(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_1, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_1)
node _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_1 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_1, 8, 7)
node activated_wdata_e_clipped_self_rec_rawIn_isSpecial_1 = eq(_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_1, UInt<2>(0h3))
wire activated_wdata_e_clipped_self_rec_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_2 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_1, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_3 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_1, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_2)
connect activated_wdata_e_clipped_self_rec_rawIn_1.isNaN, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_3
node _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_1 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_1, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_1)
connect activated_wdata_e_clipped_self_rec_rawIn_1.isInf, _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_1
connect activated_wdata_e_clipped_self_rec_rawIn_1.isZero, activated_wdata_e_clipped_self_rec_rawIn_isZero_1
connect activated_wdata_e_clipped_self_rec_rawIn_1.sign, activated_wdata_e_clipped_self_rec_rawIn_sign_1
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_2 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_1, 8, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_3 = cvt(_activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_2)
connect activated_wdata_e_clipped_self_rec_rawIn_1.sExp, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_3
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_4 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZero_1, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_4)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_6 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_1, activated_wdata_e_clipped_self_rec_rawIn_subnormFract_1, activated_wdata_e_clipped_self_rec_rawIn_fractIn_1)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_7 = cat(_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_5, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_6)
connect activated_wdata_e_clipped_self_rec_rawIn_1.sig, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_7
node _activated_wdata_e_clipped_self_rec_T_8 = bits(activated_wdata_e_clipped_self_rec_rawIn_1.sExp, 8, 6)
node _activated_wdata_e_clipped_self_rec_T_9 = mux(activated_wdata_e_clipped_self_rec_rawIn_1.isZero, UInt<3>(0h0), _activated_wdata_e_clipped_self_rec_T_8)
node _activated_wdata_e_clipped_self_rec_T_10 = mux(activated_wdata_e_clipped_self_rec_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_T_11 = or(_activated_wdata_e_clipped_self_rec_T_9, _activated_wdata_e_clipped_self_rec_T_10)
node _activated_wdata_e_clipped_self_rec_T_12 = cat(activated_wdata_e_clipped_self_rec_rawIn_1.sign, _activated_wdata_e_clipped_self_rec_T_11)
node _activated_wdata_e_clipped_self_rec_T_13 = bits(activated_wdata_e_clipped_self_rec_rawIn_1.sExp, 5, 0)
node _activated_wdata_e_clipped_self_rec_T_14 = cat(_activated_wdata_e_clipped_self_rec_T_12, _activated_wdata_e_clipped_self_rec_T_13)
node _activated_wdata_e_clipped_self_rec_T_15 = bits(activated_wdata_e_clipped_self_rec_rawIn_1.sig, 22, 0)
node activated_wdata_e_clipped_self_rec_1 = cat(_activated_wdata_e_clipped_self_rec_T_14, _activated_wdata_e_clipped_self_rec_T_15)
inst activated_wdata_e_clipped_resizer_1 of RecFNToRecFN_241
connect activated_wdata_e_clipped_resizer_1.io.in, activated_wdata_e_clipped_self_rec_1
connect activated_wdata_e_clipped_resizer_1.io.roundingMode, UInt<3>(0h0)
connect activated_wdata_e_clipped_resizer_1.io.detectTininess, UInt<1>(0h1)
wire activated_wdata_e_clipped_1 : { bits : UInt<32>}
node activated_wdata_e_clipped_result_bits_rawIn_exp_1 = bits(activated_wdata_e_clipped_resizer_1.io.out, 31, 23)
node _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_1 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_1, 8, 6)
node activated_wdata_e_clipped_result_bits_rawIn_isZero_1 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isZero_T_1, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_1 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_1, 8, 7)
node activated_wdata_e_clipped_result_bits_rawIn_isSpecial_1 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_1, UInt<2>(0h3))
wire activated_wdata_e_clipped_result_bits_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_2 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_1, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_3 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_1, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_2)
connect activated_wdata_e_clipped_result_bits_rawIn_1.isNaN, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_3
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_3 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_1, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_4 = eq(_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_3, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_5 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_1, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_4)
connect activated_wdata_e_clipped_result_bits_rawIn_1.isInf, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_5
connect activated_wdata_e_clipped_result_bits_rawIn_1.isZero, activated_wdata_e_clipped_result_bits_rawIn_isZero_1
node _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_1 = bits(activated_wdata_e_clipped_resizer_1.io.out, 32, 32)
connect activated_wdata_e_clipped_result_bits_rawIn_1.sign, _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_1
node _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_1 = cvt(activated_wdata_e_clipped_result_bits_rawIn_exp_1)
connect activated_wdata_e_clipped_result_bits_rawIn_1.sExp, _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_1
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_4 = eq(activated_wdata_e_clipped_result_bits_rawIn_isZero_1, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_4)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_6 = bits(activated_wdata_e_clipped_resizer_1.io.out, 22, 0)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_7 = cat(_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_5, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_6)
connect activated_wdata_e_clipped_result_bits_rawIn_1.sig, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_7
node activated_wdata_e_clipped_result_bits_isSubnormal_1 = lt(activated_wdata_e_clipped_result_bits_rawIn_1.sExp, asSInt(UInt<9>(0h82)))
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_2 = bits(activated_wdata_e_clipped_result_bits_rawIn_1.sExp, 4, 0)
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_3 = sub(UInt<1>(0h1), _activated_wdata_e_clipped_result_bits_denormShiftDist_T_2)
node activated_wdata_e_clipped_result_bits_denormShiftDist_1 = tail(_activated_wdata_e_clipped_result_bits_denormShiftDist_T_3, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_2 = shr(activated_wdata_e_clipped_result_bits_rawIn_1.sig, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_3 = dshr(_activated_wdata_e_clipped_result_bits_denormFract_T_2, activated_wdata_e_clipped_result_bits_denormShiftDist_1)
node activated_wdata_e_clipped_result_bits_denormFract_1 = bits(_activated_wdata_e_clipped_result_bits_denormFract_T_3, 22, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_6 = bits(activated_wdata_e_clipped_result_bits_rawIn_1.sExp, 7, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_7 = sub(_activated_wdata_e_clipped_result_bits_expOut_T_6, UInt<8>(0h81))
node _activated_wdata_e_clipped_result_bits_expOut_T_8 = tail(_activated_wdata_e_clipped_result_bits_expOut_T_7, 1)
node _activated_wdata_e_clipped_result_bits_expOut_T_9 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_1, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_expOut_T_8)
node _activated_wdata_e_clipped_result_bits_expOut_T_10 = or(activated_wdata_e_clipped_result_bits_rawIn_1.isNaN, activated_wdata_e_clipped_result_bits_rawIn_1.isInf)
node _activated_wdata_e_clipped_result_bits_expOut_T_11 = mux(_activated_wdata_e_clipped_result_bits_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0))
node activated_wdata_e_clipped_result_bits_expOut_1 = or(_activated_wdata_e_clipped_result_bits_expOut_T_9, _activated_wdata_e_clipped_result_bits_expOut_T_11)
node _activated_wdata_e_clipped_result_bits_fractOut_T_2 = bits(activated_wdata_e_clipped_result_bits_rawIn_1.sig, 22, 0)
node _activated_wdata_e_clipped_result_bits_fractOut_T_3 = mux(activated_wdata_e_clipped_result_bits_rawIn_1.isInf, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_fractOut_T_2)
node activated_wdata_e_clipped_result_bits_fractOut_1 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_1, activated_wdata_e_clipped_result_bits_denormFract_1, _activated_wdata_e_clipped_result_bits_fractOut_T_3)
node activated_wdata_e_clipped_result_bits_hi_1 = cat(activated_wdata_e_clipped_result_bits_rawIn_1.sign, activated_wdata_e_clipped_result_bits_expOut_1)
node _activated_wdata_e_clipped_result_bits_T_1 = cat(activated_wdata_e_clipped_result_bits_hi_1, activated_wdata_e_clipped_result_bits_fractOut_1)
connect activated_wdata_e_clipped_1.bits, _activated_wdata_e_clipped_result_bits_T_1
node _activated_wdata_e_act_T_1 = eq(activation, UInt<1>(0h1))
node activated_wdata_e_act_raw_sign_1 = bits(activated_wdata_e_clipped_1.bits, 31, 31)
node activated_wdata_e_act_raw_expIn_1 = bits(activated_wdata_e_clipped_1.bits, 30, 23)
node activated_wdata_e_act_raw_fractIn_1 = bits(activated_wdata_e_clipped_1.bits, 22, 0)
node activated_wdata_e_act_raw_isZeroExpIn_1 = eq(activated_wdata_e_act_raw_expIn_1, UInt<1>(0h0))
node activated_wdata_e_act_raw_isZeroFractIn_1 = eq(activated_wdata_e_act_raw_fractIn_1, UInt<1>(0h0))
node _activated_wdata_e_act_raw_normDist_T_44 = bits(activated_wdata_e_act_raw_fractIn_1, 0, 0)
node _activated_wdata_e_act_raw_normDist_T_45 = bits(activated_wdata_e_act_raw_fractIn_1, 1, 1)
node _activated_wdata_e_act_raw_normDist_T_46 = bits(activated_wdata_e_act_raw_fractIn_1, 2, 2)
node _activated_wdata_e_act_raw_normDist_T_47 = bits(activated_wdata_e_act_raw_fractIn_1, 3, 3)
node _activated_wdata_e_act_raw_normDist_T_48 = bits(activated_wdata_e_act_raw_fractIn_1, 4, 4)
node _activated_wdata_e_act_raw_normDist_T_49 = bits(activated_wdata_e_act_raw_fractIn_1, 5, 5)
node _activated_wdata_e_act_raw_normDist_T_50 = bits(activated_wdata_e_act_raw_fractIn_1, 6, 6)
node _activated_wdata_e_act_raw_normDist_T_51 = bits(activated_wdata_e_act_raw_fractIn_1, 7, 7)
node _activated_wdata_e_act_raw_normDist_T_52 = bits(activated_wdata_e_act_raw_fractIn_1, 8, 8)
node _activated_wdata_e_act_raw_normDist_T_53 = bits(activated_wdata_e_act_raw_fractIn_1, 9, 9)
node _activated_wdata_e_act_raw_normDist_T_54 = bits(activated_wdata_e_act_raw_fractIn_1, 10, 10)
node _activated_wdata_e_act_raw_normDist_T_55 = bits(activated_wdata_e_act_raw_fractIn_1, 11, 11)
node _activated_wdata_e_act_raw_normDist_T_56 = bits(activated_wdata_e_act_raw_fractIn_1, 12, 12)
node _activated_wdata_e_act_raw_normDist_T_57 = bits(activated_wdata_e_act_raw_fractIn_1, 13, 13)
node _activated_wdata_e_act_raw_normDist_T_58 = bits(activated_wdata_e_act_raw_fractIn_1, 14, 14)
node _activated_wdata_e_act_raw_normDist_T_59 = bits(activated_wdata_e_act_raw_fractIn_1, 15, 15)
node _activated_wdata_e_act_raw_normDist_T_60 = bits(activated_wdata_e_act_raw_fractIn_1, 16, 16)
node _activated_wdata_e_act_raw_normDist_T_61 = bits(activated_wdata_e_act_raw_fractIn_1, 17, 17)
node _activated_wdata_e_act_raw_normDist_T_62 = bits(activated_wdata_e_act_raw_fractIn_1, 18, 18)
node _activated_wdata_e_act_raw_normDist_T_63 = bits(activated_wdata_e_act_raw_fractIn_1, 19, 19)
node _activated_wdata_e_act_raw_normDist_T_64 = bits(activated_wdata_e_act_raw_fractIn_1, 20, 20)
node _activated_wdata_e_act_raw_normDist_T_65 = bits(activated_wdata_e_act_raw_fractIn_1, 21, 21)
node _activated_wdata_e_act_raw_normDist_T_66 = bits(activated_wdata_e_act_raw_fractIn_1, 22, 22)
node _activated_wdata_e_act_raw_normDist_T_67 = mux(_activated_wdata_e_act_raw_normDist_T_45, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_act_raw_normDist_T_68 = mux(_activated_wdata_e_act_raw_normDist_T_46, UInt<5>(0h14), _activated_wdata_e_act_raw_normDist_T_67)
node _activated_wdata_e_act_raw_normDist_T_69 = mux(_activated_wdata_e_act_raw_normDist_T_47, UInt<5>(0h13), _activated_wdata_e_act_raw_normDist_T_68)
node _activated_wdata_e_act_raw_normDist_T_70 = mux(_activated_wdata_e_act_raw_normDist_T_48, UInt<5>(0h12), _activated_wdata_e_act_raw_normDist_T_69)
node _activated_wdata_e_act_raw_normDist_T_71 = mux(_activated_wdata_e_act_raw_normDist_T_49, UInt<5>(0h11), _activated_wdata_e_act_raw_normDist_T_70)
node _activated_wdata_e_act_raw_normDist_T_72 = mux(_activated_wdata_e_act_raw_normDist_T_50, UInt<5>(0h10), _activated_wdata_e_act_raw_normDist_T_71)
node _activated_wdata_e_act_raw_normDist_T_73 = mux(_activated_wdata_e_act_raw_normDist_T_51, UInt<4>(0hf), _activated_wdata_e_act_raw_normDist_T_72)
node _activated_wdata_e_act_raw_normDist_T_74 = mux(_activated_wdata_e_act_raw_normDist_T_52, UInt<4>(0he), _activated_wdata_e_act_raw_normDist_T_73)
node _activated_wdata_e_act_raw_normDist_T_75 = mux(_activated_wdata_e_act_raw_normDist_T_53, UInt<4>(0hd), _activated_wdata_e_act_raw_normDist_T_74)
node _activated_wdata_e_act_raw_normDist_T_76 = mux(_activated_wdata_e_act_raw_normDist_T_54, UInt<4>(0hc), _activated_wdata_e_act_raw_normDist_T_75)
node _activated_wdata_e_act_raw_normDist_T_77 = mux(_activated_wdata_e_act_raw_normDist_T_55, UInt<4>(0hb), _activated_wdata_e_act_raw_normDist_T_76)
node _activated_wdata_e_act_raw_normDist_T_78 = mux(_activated_wdata_e_act_raw_normDist_T_56, UInt<4>(0ha), _activated_wdata_e_act_raw_normDist_T_77)
node _activated_wdata_e_act_raw_normDist_T_79 = mux(_activated_wdata_e_act_raw_normDist_T_57, UInt<4>(0h9), _activated_wdata_e_act_raw_normDist_T_78)
node _activated_wdata_e_act_raw_normDist_T_80 = mux(_activated_wdata_e_act_raw_normDist_T_58, UInt<4>(0h8), _activated_wdata_e_act_raw_normDist_T_79)
node _activated_wdata_e_act_raw_normDist_T_81 = mux(_activated_wdata_e_act_raw_normDist_T_59, UInt<3>(0h7), _activated_wdata_e_act_raw_normDist_T_80)
node _activated_wdata_e_act_raw_normDist_T_82 = mux(_activated_wdata_e_act_raw_normDist_T_60, UInt<3>(0h6), _activated_wdata_e_act_raw_normDist_T_81)
node _activated_wdata_e_act_raw_normDist_T_83 = mux(_activated_wdata_e_act_raw_normDist_T_61, UInt<3>(0h5), _activated_wdata_e_act_raw_normDist_T_82)
node _activated_wdata_e_act_raw_normDist_T_84 = mux(_activated_wdata_e_act_raw_normDist_T_62, UInt<3>(0h4), _activated_wdata_e_act_raw_normDist_T_83)
node _activated_wdata_e_act_raw_normDist_T_85 = mux(_activated_wdata_e_act_raw_normDist_T_63, UInt<2>(0h3), _activated_wdata_e_act_raw_normDist_T_84)
node _activated_wdata_e_act_raw_normDist_T_86 = mux(_activated_wdata_e_act_raw_normDist_T_64, UInt<2>(0h2), _activated_wdata_e_act_raw_normDist_T_85)
node _activated_wdata_e_act_raw_normDist_T_87 = mux(_activated_wdata_e_act_raw_normDist_T_65, UInt<1>(0h1), _activated_wdata_e_act_raw_normDist_T_86)
node activated_wdata_e_act_raw_normDist_1 = mux(_activated_wdata_e_act_raw_normDist_T_66, UInt<1>(0h0), _activated_wdata_e_act_raw_normDist_T_87)
node _activated_wdata_e_act_raw_subnormFract_T_2 = dshl(activated_wdata_e_act_raw_fractIn_1, activated_wdata_e_act_raw_normDist_1)
node _activated_wdata_e_act_raw_subnormFract_T_3 = bits(_activated_wdata_e_act_raw_subnormFract_T_2, 21, 0)
node activated_wdata_e_act_raw_subnormFract_1 = shl(_activated_wdata_e_act_raw_subnormFract_T_3, 1)
node _activated_wdata_e_act_raw_adjustedExp_T_5 = xor(activated_wdata_e_act_raw_normDist_1, UInt<9>(0h1ff))
node _activated_wdata_e_act_raw_adjustedExp_T_6 = mux(activated_wdata_e_act_raw_isZeroExpIn_1, _activated_wdata_e_act_raw_adjustedExp_T_5, activated_wdata_e_act_raw_expIn_1)
node _activated_wdata_e_act_raw_adjustedExp_T_7 = mux(activated_wdata_e_act_raw_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_act_raw_adjustedExp_T_8 = or(UInt<8>(0h80), _activated_wdata_e_act_raw_adjustedExp_T_7)
node _activated_wdata_e_act_raw_adjustedExp_T_9 = add(_activated_wdata_e_act_raw_adjustedExp_T_6, _activated_wdata_e_act_raw_adjustedExp_T_8)
node activated_wdata_e_act_raw_adjustedExp_1 = tail(_activated_wdata_e_act_raw_adjustedExp_T_9, 1)
node activated_wdata_e_act_raw_isZero_1 = and(activated_wdata_e_act_raw_isZeroExpIn_1, activated_wdata_e_act_raw_isZeroFractIn_1)
node _activated_wdata_e_act_raw_isSpecial_T_1 = bits(activated_wdata_e_act_raw_adjustedExp_1, 8, 7)
node activated_wdata_e_act_raw_isSpecial_1 = eq(_activated_wdata_e_act_raw_isSpecial_T_1, UInt<2>(0h3))
wire activated_wdata_e_act_raw_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_act_raw_out_isNaN_T_2 = eq(activated_wdata_e_act_raw_isZeroFractIn_1, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_isNaN_T_3 = and(activated_wdata_e_act_raw_isSpecial_1, _activated_wdata_e_act_raw_out_isNaN_T_2)
connect activated_wdata_e_act_raw_1.isNaN, _activated_wdata_e_act_raw_out_isNaN_T_3
node _activated_wdata_e_act_raw_out_isInf_T_1 = and(activated_wdata_e_act_raw_isSpecial_1, activated_wdata_e_act_raw_isZeroFractIn_1)
connect activated_wdata_e_act_raw_1.isInf, _activated_wdata_e_act_raw_out_isInf_T_1
connect activated_wdata_e_act_raw_1.isZero, activated_wdata_e_act_raw_isZero_1
connect activated_wdata_e_act_raw_1.sign, activated_wdata_e_act_raw_sign_1
node _activated_wdata_e_act_raw_out_sExp_T_2 = bits(activated_wdata_e_act_raw_adjustedExp_1, 8, 0)
node _activated_wdata_e_act_raw_out_sExp_T_3 = cvt(_activated_wdata_e_act_raw_out_sExp_T_2)
connect activated_wdata_e_act_raw_1.sExp, _activated_wdata_e_act_raw_out_sExp_T_3
node _activated_wdata_e_act_raw_out_sig_T_4 = eq(activated_wdata_e_act_raw_isZero_1, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_sig_T_5 = cat(UInt<1>(0h0), _activated_wdata_e_act_raw_out_sig_T_4)
node _activated_wdata_e_act_raw_out_sig_T_6 = mux(activated_wdata_e_act_raw_isZeroExpIn_1, activated_wdata_e_act_raw_subnormFract_1, activated_wdata_e_act_raw_fractIn_1)
node _activated_wdata_e_act_raw_out_sig_T_7 = cat(_activated_wdata_e_act_raw_out_sig_T_5, _activated_wdata_e_act_raw_out_sig_T_6)
connect activated_wdata_e_act_raw_1.sig, _activated_wdata_e_act_raw_out_sig_T_7
wire activated_wdata_e_act_result_1 : { bits : UInt<32>}
node _activated_wdata_e_act_result_bits_T_3 = eq(activated_wdata_e_act_raw_1.isZero, UInt<1>(0h0))
node _activated_wdata_e_act_result_bits_T_4 = and(_activated_wdata_e_act_result_bits_T_3, activated_wdata_e_act_raw_1.sign)
node _activated_wdata_e_act_result_bits_T_5 = mux(_activated_wdata_e_act_result_bits_T_4, UInt<1>(0h0), activated_wdata_e_clipped_1.bits)
connect activated_wdata_e_act_result_1.bits, _activated_wdata_e_act_result_bits_T_5
node activated_wdata_e_act_1 = mux(_activated_wdata_e_act_T_1, activated_wdata_e_act_result_1, activated_wdata_e_clipped_1)
wire _activated_wdata_WIRE_1 : { bits : UInt<32>}[1]
connect _activated_wdata_WIRE_1[0], activated_wdata_e_act_1
node activated_wdata_e_clipped_self_rec_rawIn_sign_2 = bits(mesh.io.resp.bits.data[2][0].bits, 31, 31)
node activated_wdata_e_clipped_self_rec_rawIn_expIn_2 = bits(mesh.io.resp.bits.data[2][0].bits, 30, 23)
node activated_wdata_e_clipped_self_rec_rawIn_fractIn_2 = bits(mesh.io.resp.bits.data[2][0].bits, 22, 0)
node activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_2 = eq(activated_wdata_e_clipped_self_rec_rawIn_expIn_2, UInt<1>(0h0))
node activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_2 = eq(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_88 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 0, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_89 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 1, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_90 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 2, 2)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_91 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 3, 3)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_92 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 4, 4)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_93 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 5, 5)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_94 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 6, 6)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_95 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 7, 7)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_96 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 8, 8)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_97 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 9, 9)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_98 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 10, 10)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_99 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 11, 11)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_100 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 12, 12)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_101 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 13, 13)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_102 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 14, 14)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_103 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 15, 15)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_104 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 16, 16)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_105 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 17, 17)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_106 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 18, 18)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_107 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 19, 19)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_108 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 20, 20)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_109 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 21, 21)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_110 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, 22, 22)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_111 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_89, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_112 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_90, UInt<5>(0h14), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_111)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_113 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_91, UInt<5>(0h13), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_112)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_114 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_92, UInt<5>(0h12), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_113)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_115 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_93, UInt<5>(0h11), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_114)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_116 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_94, UInt<5>(0h10), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_115)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_117 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_95, UInt<4>(0hf), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_116)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_118 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_96, UInt<4>(0he), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_117)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_119 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_97, UInt<4>(0hd), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_118)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_120 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_98, UInt<4>(0hc), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_119)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_121 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_99, UInt<4>(0hb), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_120)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_122 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_100, UInt<4>(0ha), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_121)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_123 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_101, UInt<4>(0h9), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_122)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_124 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_102, UInt<4>(0h8), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_123)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_125 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_103, UInt<3>(0h7), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_124)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_126 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_104, UInt<3>(0h6), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_125)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_127 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_105, UInt<3>(0h5), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_126)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_128 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_106, UInt<3>(0h4), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_127)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_129 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_107, UInt<2>(0h3), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_128)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_130 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_108, UInt<2>(0h2), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_129)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_131 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_109, UInt<1>(0h1), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_130)
node activated_wdata_e_clipped_self_rec_rawIn_normDist_2 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_110, UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_131)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_4 = dshl(activated_wdata_e_clipped_self_rec_rawIn_fractIn_2, activated_wdata_e_clipped_self_rec_rawIn_normDist_2)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_5 = bits(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_4, 21, 0)
node activated_wdata_e_clipped_self_rec_rawIn_subnormFract_2 = shl(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_5, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_10 = xor(activated_wdata_e_clipped_self_rec_rawIn_normDist_2, UInt<9>(0h1ff))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_11 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_2, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_10, activated_wdata_e_clipped_self_rec_rawIn_expIn_2)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_12 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_2, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_13 = or(UInt<8>(0h80), _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_12)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_14 = add(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_11, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_13)
node activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_2 = tail(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_14, 1)
node activated_wdata_e_clipped_self_rec_rawIn_isZero_2 = and(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_2, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_2)
node _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_2 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_2, 8, 7)
node activated_wdata_e_clipped_self_rec_rawIn_isSpecial_2 = eq(_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_2, UInt<2>(0h3))
wire activated_wdata_e_clipped_self_rec_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_4 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_2, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_5 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_2, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_4)
connect activated_wdata_e_clipped_self_rec_rawIn_2.isNaN, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_5
node _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_2 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_2, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_2)
connect activated_wdata_e_clipped_self_rec_rawIn_2.isInf, _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_2
connect activated_wdata_e_clipped_self_rec_rawIn_2.isZero, activated_wdata_e_clipped_self_rec_rawIn_isZero_2
connect activated_wdata_e_clipped_self_rec_rawIn_2.sign, activated_wdata_e_clipped_self_rec_rawIn_sign_2
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_4 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_2, 8, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_5 = cvt(_activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_4)
connect activated_wdata_e_clipped_self_rec_rawIn_2.sExp, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_5
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_8 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZero_2, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_8)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_10 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_2, activated_wdata_e_clipped_self_rec_rawIn_subnormFract_2, activated_wdata_e_clipped_self_rec_rawIn_fractIn_2)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_11 = cat(_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_9, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_10)
connect activated_wdata_e_clipped_self_rec_rawIn_2.sig, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_11
node _activated_wdata_e_clipped_self_rec_T_16 = bits(activated_wdata_e_clipped_self_rec_rawIn_2.sExp, 8, 6)
node _activated_wdata_e_clipped_self_rec_T_17 = mux(activated_wdata_e_clipped_self_rec_rawIn_2.isZero, UInt<3>(0h0), _activated_wdata_e_clipped_self_rec_T_16)
node _activated_wdata_e_clipped_self_rec_T_18 = mux(activated_wdata_e_clipped_self_rec_rawIn_2.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_T_19 = or(_activated_wdata_e_clipped_self_rec_T_17, _activated_wdata_e_clipped_self_rec_T_18)
node _activated_wdata_e_clipped_self_rec_T_20 = cat(activated_wdata_e_clipped_self_rec_rawIn_2.sign, _activated_wdata_e_clipped_self_rec_T_19)
node _activated_wdata_e_clipped_self_rec_T_21 = bits(activated_wdata_e_clipped_self_rec_rawIn_2.sExp, 5, 0)
node _activated_wdata_e_clipped_self_rec_T_22 = cat(_activated_wdata_e_clipped_self_rec_T_20, _activated_wdata_e_clipped_self_rec_T_21)
node _activated_wdata_e_clipped_self_rec_T_23 = bits(activated_wdata_e_clipped_self_rec_rawIn_2.sig, 22, 0)
node activated_wdata_e_clipped_self_rec_2 = cat(_activated_wdata_e_clipped_self_rec_T_22, _activated_wdata_e_clipped_self_rec_T_23)
inst activated_wdata_e_clipped_resizer_2 of RecFNToRecFN_242
connect activated_wdata_e_clipped_resizer_2.io.in, activated_wdata_e_clipped_self_rec_2
connect activated_wdata_e_clipped_resizer_2.io.roundingMode, UInt<3>(0h0)
connect activated_wdata_e_clipped_resizer_2.io.detectTininess, UInt<1>(0h1)
wire activated_wdata_e_clipped_2 : { bits : UInt<32>}
node activated_wdata_e_clipped_result_bits_rawIn_exp_2 = bits(activated_wdata_e_clipped_resizer_2.io.out, 31, 23)
node _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_2 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_2, 8, 6)
node activated_wdata_e_clipped_result_bits_rawIn_isZero_2 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isZero_T_2, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_2 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_2, 8, 7)
node activated_wdata_e_clipped_result_bits_rawIn_isSpecial_2 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_2, UInt<2>(0h3))
wire activated_wdata_e_clipped_result_bits_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_4 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_2, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_5 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_2, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_4)
connect activated_wdata_e_clipped_result_bits_rawIn_2.isNaN, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_5
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_6 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_2, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_7 = eq(_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_6, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_8 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_2, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_7)
connect activated_wdata_e_clipped_result_bits_rawIn_2.isInf, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_8
connect activated_wdata_e_clipped_result_bits_rawIn_2.isZero, activated_wdata_e_clipped_result_bits_rawIn_isZero_2
node _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_2 = bits(activated_wdata_e_clipped_resizer_2.io.out, 32, 32)
connect activated_wdata_e_clipped_result_bits_rawIn_2.sign, _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_2
node _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_2 = cvt(activated_wdata_e_clipped_result_bits_rawIn_exp_2)
connect activated_wdata_e_clipped_result_bits_rawIn_2.sExp, _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_2
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_8 = eq(activated_wdata_e_clipped_result_bits_rawIn_isZero_2, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_8)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_10 = bits(activated_wdata_e_clipped_resizer_2.io.out, 22, 0)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_11 = cat(_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_9, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_10)
connect activated_wdata_e_clipped_result_bits_rawIn_2.sig, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_11
node activated_wdata_e_clipped_result_bits_isSubnormal_2 = lt(activated_wdata_e_clipped_result_bits_rawIn_2.sExp, asSInt(UInt<9>(0h82)))
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_4 = bits(activated_wdata_e_clipped_result_bits_rawIn_2.sExp, 4, 0)
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_5 = sub(UInt<1>(0h1), _activated_wdata_e_clipped_result_bits_denormShiftDist_T_4)
node activated_wdata_e_clipped_result_bits_denormShiftDist_2 = tail(_activated_wdata_e_clipped_result_bits_denormShiftDist_T_5, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_4 = shr(activated_wdata_e_clipped_result_bits_rawIn_2.sig, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_5 = dshr(_activated_wdata_e_clipped_result_bits_denormFract_T_4, activated_wdata_e_clipped_result_bits_denormShiftDist_2)
node activated_wdata_e_clipped_result_bits_denormFract_2 = bits(_activated_wdata_e_clipped_result_bits_denormFract_T_5, 22, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_12 = bits(activated_wdata_e_clipped_result_bits_rawIn_2.sExp, 7, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_13 = sub(_activated_wdata_e_clipped_result_bits_expOut_T_12, UInt<8>(0h81))
node _activated_wdata_e_clipped_result_bits_expOut_T_14 = tail(_activated_wdata_e_clipped_result_bits_expOut_T_13, 1)
node _activated_wdata_e_clipped_result_bits_expOut_T_15 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_2, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_expOut_T_14)
node _activated_wdata_e_clipped_result_bits_expOut_T_16 = or(activated_wdata_e_clipped_result_bits_rawIn_2.isNaN, activated_wdata_e_clipped_result_bits_rawIn_2.isInf)
node _activated_wdata_e_clipped_result_bits_expOut_T_17 = mux(_activated_wdata_e_clipped_result_bits_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0))
node activated_wdata_e_clipped_result_bits_expOut_2 = or(_activated_wdata_e_clipped_result_bits_expOut_T_15, _activated_wdata_e_clipped_result_bits_expOut_T_17)
node _activated_wdata_e_clipped_result_bits_fractOut_T_4 = bits(activated_wdata_e_clipped_result_bits_rawIn_2.sig, 22, 0)
node _activated_wdata_e_clipped_result_bits_fractOut_T_5 = mux(activated_wdata_e_clipped_result_bits_rawIn_2.isInf, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_fractOut_T_4)
node activated_wdata_e_clipped_result_bits_fractOut_2 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_2, activated_wdata_e_clipped_result_bits_denormFract_2, _activated_wdata_e_clipped_result_bits_fractOut_T_5)
node activated_wdata_e_clipped_result_bits_hi_2 = cat(activated_wdata_e_clipped_result_bits_rawIn_2.sign, activated_wdata_e_clipped_result_bits_expOut_2)
node _activated_wdata_e_clipped_result_bits_T_2 = cat(activated_wdata_e_clipped_result_bits_hi_2, activated_wdata_e_clipped_result_bits_fractOut_2)
connect activated_wdata_e_clipped_2.bits, _activated_wdata_e_clipped_result_bits_T_2
node _activated_wdata_e_act_T_2 = eq(activation, UInt<1>(0h1))
node activated_wdata_e_act_raw_sign_2 = bits(activated_wdata_e_clipped_2.bits, 31, 31)
node activated_wdata_e_act_raw_expIn_2 = bits(activated_wdata_e_clipped_2.bits, 30, 23)
node activated_wdata_e_act_raw_fractIn_2 = bits(activated_wdata_e_clipped_2.bits, 22, 0)
node activated_wdata_e_act_raw_isZeroExpIn_2 = eq(activated_wdata_e_act_raw_expIn_2, UInt<1>(0h0))
node activated_wdata_e_act_raw_isZeroFractIn_2 = eq(activated_wdata_e_act_raw_fractIn_2, UInt<1>(0h0))
node _activated_wdata_e_act_raw_normDist_T_88 = bits(activated_wdata_e_act_raw_fractIn_2, 0, 0)
node _activated_wdata_e_act_raw_normDist_T_89 = bits(activated_wdata_e_act_raw_fractIn_2, 1, 1)
node _activated_wdata_e_act_raw_normDist_T_90 = bits(activated_wdata_e_act_raw_fractIn_2, 2, 2)
node _activated_wdata_e_act_raw_normDist_T_91 = bits(activated_wdata_e_act_raw_fractIn_2, 3, 3)
node _activated_wdata_e_act_raw_normDist_T_92 = bits(activated_wdata_e_act_raw_fractIn_2, 4, 4)
node _activated_wdata_e_act_raw_normDist_T_93 = bits(activated_wdata_e_act_raw_fractIn_2, 5, 5)
node _activated_wdata_e_act_raw_normDist_T_94 = bits(activated_wdata_e_act_raw_fractIn_2, 6, 6)
node _activated_wdata_e_act_raw_normDist_T_95 = bits(activated_wdata_e_act_raw_fractIn_2, 7, 7)
node _activated_wdata_e_act_raw_normDist_T_96 = bits(activated_wdata_e_act_raw_fractIn_2, 8, 8)
node _activated_wdata_e_act_raw_normDist_T_97 = bits(activated_wdata_e_act_raw_fractIn_2, 9, 9)
node _activated_wdata_e_act_raw_normDist_T_98 = bits(activated_wdata_e_act_raw_fractIn_2, 10, 10)
node _activated_wdata_e_act_raw_normDist_T_99 = bits(activated_wdata_e_act_raw_fractIn_2, 11, 11)
node _activated_wdata_e_act_raw_normDist_T_100 = bits(activated_wdata_e_act_raw_fractIn_2, 12, 12)
node _activated_wdata_e_act_raw_normDist_T_101 = bits(activated_wdata_e_act_raw_fractIn_2, 13, 13)
node _activated_wdata_e_act_raw_normDist_T_102 = bits(activated_wdata_e_act_raw_fractIn_2, 14, 14)
node _activated_wdata_e_act_raw_normDist_T_103 = bits(activated_wdata_e_act_raw_fractIn_2, 15, 15)
node _activated_wdata_e_act_raw_normDist_T_104 = bits(activated_wdata_e_act_raw_fractIn_2, 16, 16)
node _activated_wdata_e_act_raw_normDist_T_105 = bits(activated_wdata_e_act_raw_fractIn_2, 17, 17)
node _activated_wdata_e_act_raw_normDist_T_106 = bits(activated_wdata_e_act_raw_fractIn_2, 18, 18)
node _activated_wdata_e_act_raw_normDist_T_107 = bits(activated_wdata_e_act_raw_fractIn_2, 19, 19)
node _activated_wdata_e_act_raw_normDist_T_108 = bits(activated_wdata_e_act_raw_fractIn_2, 20, 20)
node _activated_wdata_e_act_raw_normDist_T_109 = bits(activated_wdata_e_act_raw_fractIn_2, 21, 21)
node _activated_wdata_e_act_raw_normDist_T_110 = bits(activated_wdata_e_act_raw_fractIn_2, 22, 22)
node _activated_wdata_e_act_raw_normDist_T_111 = mux(_activated_wdata_e_act_raw_normDist_T_89, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_act_raw_normDist_T_112 = mux(_activated_wdata_e_act_raw_normDist_T_90, UInt<5>(0h14), _activated_wdata_e_act_raw_normDist_T_111)
node _activated_wdata_e_act_raw_normDist_T_113 = mux(_activated_wdata_e_act_raw_normDist_T_91, UInt<5>(0h13), _activated_wdata_e_act_raw_normDist_T_112)
node _activated_wdata_e_act_raw_normDist_T_114 = mux(_activated_wdata_e_act_raw_normDist_T_92, UInt<5>(0h12), _activated_wdata_e_act_raw_normDist_T_113)
node _activated_wdata_e_act_raw_normDist_T_115 = mux(_activated_wdata_e_act_raw_normDist_T_93, UInt<5>(0h11), _activated_wdata_e_act_raw_normDist_T_114)
node _activated_wdata_e_act_raw_normDist_T_116 = mux(_activated_wdata_e_act_raw_normDist_T_94, UInt<5>(0h10), _activated_wdata_e_act_raw_normDist_T_115)
node _activated_wdata_e_act_raw_normDist_T_117 = mux(_activated_wdata_e_act_raw_normDist_T_95, UInt<4>(0hf), _activated_wdata_e_act_raw_normDist_T_116)
node _activated_wdata_e_act_raw_normDist_T_118 = mux(_activated_wdata_e_act_raw_normDist_T_96, UInt<4>(0he), _activated_wdata_e_act_raw_normDist_T_117)
node _activated_wdata_e_act_raw_normDist_T_119 = mux(_activated_wdata_e_act_raw_normDist_T_97, UInt<4>(0hd), _activated_wdata_e_act_raw_normDist_T_118)
node _activated_wdata_e_act_raw_normDist_T_120 = mux(_activated_wdata_e_act_raw_normDist_T_98, UInt<4>(0hc), _activated_wdata_e_act_raw_normDist_T_119)
node _activated_wdata_e_act_raw_normDist_T_121 = mux(_activated_wdata_e_act_raw_normDist_T_99, UInt<4>(0hb), _activated_wdata_e_act_raw_normDist_T_120)
node _activated_wdata_e_act_raw_normDist_T_122 = mux(_activated_wdata_e_act_raw_normDist_T_100, UInt<4>(0ha), _activated_wdata_e_act_raw_normDist_T_121)
node _activated_wdata_e_act_raw_normDist_T_123 = mux(_activated_wdata_e_act_raw_normDist_T_101, UInt<4>(0h9), _activated_wdata_e_act_raw_normDist_T_122)
node _activated_wdata_e_act_raw_normDist_T_124 = mux(_activated_wdata_e_act_raw_normDist_T_102, UInt<4>(0h8), _activated_wdata_e_act_raw_normDist_T_123)
node _activated_wdata_e_act_raw_normDist_T_125 = mux(_activated_wdata_e_act_raw_normDist_T_103, UInt<3>(0h7), _activated_wdata_e_act_raw_normDist_T_124)
node _activated_wdata_e_act_raw_normDist_T_126 = mux(_activated_wdata_e_act_raw_normDist_T_104, UInt<3>(0h6), _activated_wdata_e_act_raw_normDist_T_125)
node _activated_wdata_e_act_raw_normDist_T_127 = mux(_activated_wdata_e_act_raw_normDist_T_105, UInt<3>(0h5), _activated_wdata_e_act_raw_normDist_T_126)
node _activated_wdata_e_act_raw_normDist_T_128 = mux(_activated_wdata_e_act_raw_normDist_T_106, UInt<3>(0h4), _activated_wdata_e_act_raw_normDist_T_127)
node _activated_wdata_e_act_raw_normDist_T_129 = mux(_activated_wdata_e_act_raw_normDist_T_107, UInt<2>(0h3), _activated_wdata_e_act_raw_normDist_T_128)
node _activated_wdata_e_act_raw_normDist_T_130 = mux(_activated_wdata_e_act_raw_normDist_T_108, UInt<2>(0h2), _activated_wdata_e_act_raw_normDist_T_129)
node _activated_wdata_e_act_raw_normDist_T_131 = mux(_activated_wdata_e_act_raw_normDist_T_109, UInt<1>(0h1), _activated_wdata_e_act_raw_normDist_T_130)
node activated_wdata_e_act_raw_normDist_2 = mux(_activated_wdata_e_act_raw_normDist_T_110, UInt<1>(0h0), _activated_wdata_e_act_raw_normDist_T_131)
node _activated_wdata_e_act_raw_subnormFract_T_4 = dshl(activated_wdata_e_act_raw_fractIn_2, activated_wdata_e_act_raw_normDist_2)
node _activated_wdata_e_act_raw_subnormFract_T_5 = bits(_activated_wdata_e_act_raw_subnormFract_T_4, 21, 0)
node activated_wdata_e_act_raw_subnormFract_2 = shl(_activated_wdata_e_act_raw_subnormFract_T_5, 1)
node _activated_wdata_e_act_raw_adjustedExp_T_10 = xor(activated_wdata_e_act_raw_normDist_2, UInt<9>(0h1ff))
node _activated_wdata_e_act_raw_adjustedExp_T_11 = mux(activated_wdata_e_act_raw_isZeroExpIn_2, _activated_wdata_e_act_raw_adjustedExp_T_10, activated_wdata_e_act_raw_expIn_2)
node _activated_wdata_e_act_raw_adjustedExp_T_12 = mux(activated_wdata_e_act_raw_isZeroExpIn_2, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_act_raw_adjustedExp_T_13 = or(UInt<8>(0h80), _activated_wdata_e_act_raw_adjustedExp_T_12)
node _activated_wdata_e_act_raw_adjustedExp_T_14 = add(_activated_wdata_e_act_raw_adjustedExp_T_11, _activated_wdata_e_act_raw_adjustedExp_T_13)
node activated_wdata_e_act_raw_adjustedExp_2 = tail(_activated_wdata_e_act_raw_adjustedExp_T_14, 1)
node activated_wdata_e_act_raw_isZero_2 = and(activated_wdata_e_act_raw_isZeroExpIn_2, activated_wdata_e_act_raw_isZeroFractIn_2)
node _activated_wdata_e_act_raw_isSpecial_T_2 = bits(activated_wdata_e_act_raw_adjustedExp_2, 8, 7)
node activated_wdata_e_act_raw_isSpecial_2 = eq(_activated_wdata_e_act_raw_isSpecial_T_2, UInt<2>(0h3))
wire activated_wdata_e_act_raw_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_act_raw_out_isNaN_T_4 = eq(activated_wdata_e_act_raw_isZeroFractIn_2, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_isNaN_T_5 = and(activated_wdata_e_act_raw_isSpecial_2, _activated_wdata_e_act_raw_out_isNaN_T_4)
connect activated_wdata_e_act_raw_2.isNaN, _activated_wdata_e_act_raw_out_isNaN_T_5
node _activated_wdata_e_act_raw_out_isInf_T_2 = and(activated_wdata_e_act_raw_isSpecial_2, activated_wdata_e_act_raw_isZeroFractIn_2)
connect activated_wdata_e_act_raw_2.isInf, _activated_wdata_e_act_raw_out_isInf_T_2
connect activated_wdata_e_act_raw_2.isZero, activated_wdata_e_act_raw_isZero_2
connect activated_wdata_e_act_raw_2.sign, activated_wdata_e_act_raw_sign_2
node _activated_wdata_e_act_raw_out_sExp_T_4 = bits(activated_wdata_e_act_raw_adjustedExp_2, 8, 0)
node _activated_wdata_e_act_raw_out_sExp_T_5 = cvt(_activated_wdata_e_act_raw_out_sExp_T_4)
connect activated_wdata_e_act_raw_2.sExp, _activated_wdata_e_act_raw_out_sExp_T_5
node _activated_wdata_e_act_raw_out_sig_T_8 = eq(activated_wdata_e_act_raw_isZero_2, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_sig_T_9 = cat(UInt<1>(0h0), _activated_wdata_e_act_raw_out_sig_T_8)
node _activated_wdata_e_act_raw_out_sig_T_10 = mux(activated_wdata_e_act_raw_isZeroExpIn_2, activated_wdata_e_act_raw_subnormFract_2, activated_wdata_e_act_raw_fractIn_2)
node _activated_wdata_e_act_raw_out_sig_T_11 = cat(_activated_wdata_e_act_raw_out_sig_T_9, _activated_wdata_e_act_raw_out_sig_T_10)
connect activated_wdata_e_act_raw_2.sig, _activated_wdata_e_act_raw_out_sig_T_11
wire activated_wdata_e_act_result_2 : { bits : UInt<32>}
node _activated_wdata_e_act_result_bits_T_6 = eq(activated_wdata_e_act_raw_2.isZero, UInt<1>(0h0))
node _activated_wdata_e_act_result_bits_T_7 = and(_activated_wdata_e_act_result_bits_T_6, activated_wdata_e_act_raw_2.sign)
node _activated_wdata_e_act_result_bits_T_8 = mux(_activated_wdata_e_act_result_bits_T_7, UInt<1>(0h0), activated_wdata_e_clipped_2.bits)
connect activated_wdata_e_act_result_2.bits, _activated_wdata_e_act_result_bits_T_8
node activated_wdata_e_act_2 = mux(_activated_wdata_e_act_T_2, activated_wdata_e_act_result_2, activated_wdata_e_clipped_2)
wire _activated_wdata_WIRE_2 : { bits : UInt<32>}[1]
connect _activated_wdata_WIRE_2[0], activated_wdata_e_act_2
node activated_wdata_e_clipped_self_rec_rawIn_sign_3 = bits(mesh.io.resp.bits.data[3][0].bits, 31, 31)
node activated_wdata_e_clipped_self_rec_rawIn_expIn_3 = bits(mesh.io.resp.bits.data[3][0].bits, 30, 23)
node activated_wdata_e_clipped_self_rec_rawIn_fractIn_3 = bits(mesh.io.resp.bits.data[3][0].bits, 22, 0)
node activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_3 = eq(activated_wdata_e_clipped_self_rec_rawIn_expIn_3, UInt<1>(0h0))
node activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_3 = eq(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_132 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 0, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_133 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 1, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_134 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 2, 2)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_135 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 3, 3)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_136 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 4, 4)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_137 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 5, 5)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_138 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 6, 6)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_139 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 7, 7)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_140 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 8, 8)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_141 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 9, 9)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_142 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 10, 10)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_143 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 11, 11)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_144 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 12, 12)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_145 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 13, 13)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_146 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 14, 14)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_147 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 15, 15)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_148 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 16, 16)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_149 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 17, 17)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_150 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 18, 18)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_151 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 19, 19)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_152 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 20, 20)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_153 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 21, 21)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_154 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, 22, 22)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_155 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_133, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_156 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_134, UInt<5>(0h14), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_155)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_157 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_135, UInt<5>(0h13), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_156)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_158 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_136, UInt<5>(0h12), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_157)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_159 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_137, UInt<5>(0h11), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_158)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_160 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_138, UInt<5>(0h10), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_159)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_161 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_139, UInt<4>(0hf), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_160)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_162 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_140, UInt<4>(0he), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_161)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_163 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_141, UInt<4>(0hd), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_162)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_164 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_142, UInt<4>(0hc), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_163)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_165 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_143, UInt<4>(0hb), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_164)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_166 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_144, UInt<4>(0ha), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_165)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_167 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_145, UInt<4>(0h9), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_166)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_168 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_146, UInt<4>(0h8), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_167)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_169 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_147, UInt<3>(0h7), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_168)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_170 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_148, UInt<3>(0h6), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_169)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_171 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_149, UInt<3>(0h5), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_170)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_172 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_150, UInt<3>(0h4), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_171)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_173 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_151, UInt<2>(0h3), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_172)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_174 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_152, UInt<2>(0h2), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_173)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_175 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_153, UInt<1>(0h1), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_174)
node activated_wdata_e_clipped_self_rec_rawIn_normDist_3 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_154, UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_175)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_6 = dshl(activated_wdata_e_clipped_self_rec_rawIn_fractIn_3, activated_wdata_e_clipped_self_rec_rawIn_normDist_3)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_7 = bits(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_6, 21, 0)
node activated_wdata_e_clipped_self_rec_rawIn_subnormFract_3 = shl(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_7, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_15 = xor(activated_wdata_e_clipped_self_rec_rawIn_normDist_3, UInt<9>(0h1ff))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_16 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_3, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_15, activated_wdata_e_clipped_self_rec_rawIn_expIn_3)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_17 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_3, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_18 = or(UInt<8>(0h80), _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_17)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_19 = add(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_16, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_18)
node activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_3 = tail(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_19, 1)
node activated_wdata_e_clipped_self_rec_rawIn_isZero_3 = and(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_3, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_3)
node _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_3 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_3, 8, 7)
node activated_wdata_e_clipped_self_rec_rawIn_isSpecial_3 = eq(_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_3, UInt<2>(0h3))
wire activated_wdata_e_clipped_self_rec_rawIn_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_6 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_3, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_7 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_3, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_6)
connect activated_wdata_e_clipped_self_rec_rawIn_3.isNaN, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_7
node _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_3 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_3, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_3)
connect activated_wdata_e_clipped_self_rec_rawIn_3.isInf, _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_3
connect activated_wdata_e_clipped_self_rec_rawIn_3.isZero, activated_wdata_e_clipped_self_rec_rawIn_isZero_3
connect activated_wdata_e_clipped_self_rec_rawIn_3.sign, activated_wdata_e_clipped_self_rec_rawIn_sign_3
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_6 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_3, 8, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_7 = cvt(_activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_6)
connect activated_wdata_e_clipped_self_rec_rawIn_3.sExp, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_7
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_12 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZero_3, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_13 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_12)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_14 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_3, activated_wdata_e_clipped_self_rec_rawIn_subnormFract_3, activated_wdata_e_clipped_self_rec_rawIn_fractIn_3)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_15 = cat(_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_13, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_14)
connect activated_wdata_e_clipped_self_rec_rawIn_3.sig, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_15
node _activated_wdata_e_clipped_self_rec_T_24 = bits(activated_wdata_e_clipped_self_rec_rawIn_3.sExp, 8, 6)
node _activated_wdata_e_clipped_self_rec_T_25 = mux(activated_wdata_e_clipped_self_rec_rawIn_3.isZero, UInt<3>(0h0), _activated_wdata_e_clipped_self_rec_T_24)
node _activated_wdata_e_clipped_self_rec_T_26 = mux(activated_wdata_e_clipped_self_rec_rawIn_3.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_T_27 = or(_activated_wdata_e_clipped_self_rec_T_25, _activated_wdata_e_clipped_self_rec_T_26)
node _activated_wdata_e_clipped_self_rec_T_28 = cat(activated_wdata_e_clipped_self_rec_rawIn_3.sign, _activated_wdata_e_clipped_self_rec_T_27)
node _activated_wdata_e_clipped_self_rec_T_29 = bits(activated_wdata_e_clipped_self_rec_rawIn_3.sExp, 5, 0)
node _activated_wdata_e_clipped_self_rec_T_30 = cat(_activated_wdata_e_clipped_self_rec_T_28, _activated_wdata_e_clipped_self_rec_T_29)
node _activated_wdata_e_clipped_self_rec_T_31 = bits(activated_wdata_e_clipped_self_rec_rawIn_3.sig, 22, 0)
node activated_wdata_e_clipped_self_rec_3 = cat(_activated_wdata_e_clipped_self_rec_T_30, _activated_wdata_e_clipped_self_rec_T_31)
inst activated_wdata_e_clipped_resizer_3 of RecFNToRecFN_243
connect activated_wdata_e_clipped_resizer_3.io.in, activated_wdata_e_clipped_self_rec_3
connect activated_wdata_e_clipped_resizer_3.io.roundingMode, UInt<3>(0h0)
connect activated_wdata_e_clipped_resizer_3.io.detectTininess, UInt<1>(0h1)
wire activated_wdata_e_clipped_3 : { bits : UInt<32>}
node activated_wdata_e_clipped_result_bits_rawIn_exp_3 = bits(activated_wdata_e_clipped_resizer_3.io.out, 31, 23)
node _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_3 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_3, 8, 6)
node activated_wdata_e_clipped_result_bits_rawIn_isZero_3 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isZero_T_3, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_3 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_3, 8, 7)
node activated_wdata_e_clipped_result_bits_rawIn_isSpecial_3 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_3, UInt<2>(0h3))
wire activated_wdata_e_clipped_result_bits_rawIn_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_6 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_3, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_7 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_3, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_6)
connect activated_wdata_e_clipped_result_bits_rawIn_3.isNaN, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_7
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_9 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_3, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_10 = eq(_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_9, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_11 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_3, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_10)
connect activated_wdata_e_clipped_result_bits_rawIn_3.isInf, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_11
connect activated_wdata_e_clipped_result_bits_rawIn_3.isZero, activated_wdata_e_clipped_result_bits_rawIn_isZero_3
node _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_3 = bits(activated_wdata_e_clipped_resizer_3.io.out, 32, 32)
connect activated_wdata_e_clipped_result_bits_rawIn_3.sign, _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_3
node _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_3 = cvt(activated_wdata_e_clipped_result_bits_rawIn_exp_3)
connect activated_wdata_e_clipped_result_bits_rawIn_3.sExp, _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_3
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_12 = eq(activated_wdata_e_clipped_result_bits_rawIn_isZero_3, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_13 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_12)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_14 = bits(activated_wdata_e_clipped_resizer_3.io.out, 22, 0)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_15 = cat(_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_13, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_14)
connect activated_wdata_e_clipped_result_bits_rawIn_3.sig, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_15
node activated_wdata_e_clipped_result_bits_isSubnormal_3 = lt(activated_wdata_e_clipped_result_bits_rawIn_3.sExp, asSInt(UInt<9>(0h82)))
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_6 = bits(activated_wdata_e_clipped_result_bits_rawIn_3.sExp, 4, 0)
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_7 = sub(UInt<1>(0h1), _activated_wdata_e_clipped_result_bits_denormShiftDist_T_6)
node activated_wdata_e_clipped_result_bits_denormShiftDist_3 = tail(_activated_wdata_e_clipped_result_bits_denormShiftDist_T_7, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_6 = shr(activated_wdata_e_clipped_result_bits_rawIn_3.sig, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_7 = dshr(_activated_wdata_e_clipped_result_bits_denormFract_T_6, activated_wdata_e_clipped_result_bits_denormShiftDist_3)
node activated_wdata_e_clipped_result_bits_denormFract_3 = bits(_activated_wdata_e_clipped_result_bits_denormFract_T_7, 22, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_18 = bits(activated_wdata_e_clipped_result_bits_rawIn_3.sExp, 7, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_19 = sub(_activated_wdata_e_clipped_result_bits_expOut_T_18, UInt<8>(0h81))
node _activated_wdata_e_clipped_result_bits_expOut_T_20 = tail(_activated_wdata_e_clipped_result_bits_expOut_T_19, 1)
node _activated_wdata_e_clipped_result_bits_expOut_T_21 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_3, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_expOut_T_20)
node _activated_wdata_e_clipped_result_bits_expOut_T_22 = or(activated_wdata_e_clipped_result_bits_rawIn_3.isNaN, activated_wdata_e_clipped_result_bits_rawIn_3.isInf)
node _activated_wdata_e_clipped_result_bits_expOut_T_23 = mux(_activated_wdata_e_clipped_result_bits_expOut_T_22, UInt<8>(0hff), UInt<8>(0h0))
node activated_wdata_e_clipped_result_bits_expOut_3 = or(_activated_wdata_e_clipped_result_bits_expOut_T_21, _activated_wdata_e_clipped_result_bits_expOut_T_23)
node _activated_wdata_e_clipped_result_bits_fractOut_T_6 = bits(activated_wdata_e_clipped_result_bits_rawIn_3.sig, 22, 0)
node _activated_wdata_e_clipped_result_bits_fractOut_T_7 = mux(activated_wdata_e_clipped_result_bits_rawIn_3.isInf, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_fractOut_T_6)
node activated_wdata_e_clipped_result_bits_fractOut_3 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_3, activated_wdata_e_clipped_result_bits_denormFract_3, _activated_wdata_e_clipped_result_bits_fractOut_T_7)
node activated_wdata_e_clipped_result_bits_hi_3 = cat(activated_wdata_e_clipped_result_bits_rawIn_3.sign, activated_wdata_e_clipped_result_bits_expOut_3)
node _activated_wdata_e_clipped_result_bits_T_3 = cat(activated_wdata_e_clipped_result_bits_hi_3, activated_wdata_e_clipped_result_bits_fractOut_3)
connect activated_wdata_e_clipped_3.bits, _activated_wdata_e_clipped_result_bits_T_3
node _activated_wdata_e_act_T_3 = eq(activation, UInt<1>(0h1))
node activated_wdata_e_act_raw_sign_3 = bits(activated_wdata_e_clipped_3.bits, 31, 31)
node activated_wdata_e_act_raw_expIn_3 = bits(activated_wdata_e_clipped_3.bits, 30, 23)
node activated_wdata_e_act_raw_fractIn_3 = bits(activated_wdata_e_clipped_3.bits, 22, 0)
node activated_wdata_e_act_raw_isZeroExpIn_3 = eq(activated_wdata_e_act_raw_expIn_3, UInt<1>(0h0))
node activated_wdata_e_act_raw_isZeroFractIn_3 = eq(activated_wdata_e_act_raw_fractIn_3, UInt<1>(0h0))
node _activated_wdata_e_act_raw_normDist_T_132 = bits(activated_wdata_e_act_raw_fractIn_3, 0, 0)
node _activated_wdata_e_act_raw_normDist_T_133 = bits(activated_wdata_e_act_raw_fractIn_3, 1, 1)
node _activated_wdata_e_act_raw_normDist_T_134 = bits(activated_wdata_e_act_raw_fractIn_3, 2, 2)
node _activated_wdata_e_act_raw_normDist_T_135 = bits(activated_wdata_e_act_raw_fractIn_3, 3, 3)
node _activated_wdata_e_act_raw_normDist_T_136 = bits(activated_wdata_e_act_raw_fractIn_3, 4, 4)
node _activated_wdata_e_act_raw_normDist_T_137 = bits(activated_wdata_e_act_raw_fractIn_3, 5, 5)
node _activated_wdata_e_act_raw_normDist_T_138 = bits(activated_wdata_e_act_raw_fractIn_3, 6, 6)
node _activated_wdata_e_act_raw_normDist_T_139 = bits(activated_wdata_e_act_raw_fractIn_3, 7, 7)
node _activated_wdata_e_act_raw_normDist_T_140 = bits(activated_wdata_e_act_raw_fractIn_3, 8, 8)
node _activated_wdata_e_act_raw_normDist_T_141 = bits(activated_wdata_e_act_raw_fractIn_3, 9, 9)
node _activated_wdata_e_act_raw_normDist_T_142 = bits(activated_wdata_e_act_raw_fractIn_3, 10, 10)
node _activated_wdata_e_act_raw_normDist_T_143 = bits(activated_wdata_e_act_raw_fractIn_3, 11, 11)
node _activated_wdata_e_act_raw_normDist_T_144 = bits(activated_wdata_e_act_raw_fractIn_3, 12, 12)
node _activated_wdata_e_act_raw_normDist_T_145 = bits(activated_wdata_e_act_raw_fractIn_3, 13, 13)
node _activated_wdata_e_act_raw_normDist_T_146 = bits(activated_wdata_e_act_raw_fractIn_3, 14, 14)
node _activated_wdata_e_act_raw_normDist_T_147 = bits(activated_wdata_e_act_raw_fractIn_3, 15, 15)
node _activated_wdata_e_act_raw_normDist_T_148 = bits(activated_wdata_e_act_raw_fractIn_3, 16, 16)
node _activated_wdata_e_act_raw_normDist_T_149 = bits(activated_wdata_e_act_raw_fractIn_3, 17, 17)
node _activated_wdata_e_act_raw_normDist_T_150 = bits(activated_wdata_e_act_raw_fractIn_3, 18, 18)
node _activated_wdata_e_act_raw_normDist_T_151 = bits(activated_wdata_e_act_raw_fractIn_3, 19, 19)
node _activated_wdata_e_act_raw_normDist_T_152 = bits(activated_wdata_e_act_raw_fractIn_3, 20, 20)
node _activated_wdata_e_act_raw_normDist_T_153 = bits(activated_wdata_e_act_raw_fractIn_3, 21, 21)
node _activated_wdata_e_act_raw_normDist_T_154 = bits(activated_wdata_e_act_raw_fractIn_3, 22, 22)
node _activated_wdata_e_act_raw_normDist_T_155 = mux(_activated_wdata_e_act_raw_normDist_T_133, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_act_raw_normDist_T_156 = mux(_activated_wdata_e_act_raw_normDist_T_134, UInt<5>(0h14), _activated_wdata_e_act_raw_normDist_T_155)
node _activated_wdata_e_act_raw_normDist_T_157 = mux(_activated_wdata_e_act_raw_normDist_T_135, UInt<5>(0h13), _activated_wdata_e_act_raw_normDist_T_156)
node _activated_wdata_e_act_raw_normDist_T_158 = mux(_activated_wdata_e_act_raw_normDist_T_136, UInt<5>(0h12), _activated_wdata_e_act_raw_normDist_T_157)
node _activated_wdata_e_act_raw_normDist_T_159 = mux(_activated_wdata_e_act_raw_normDist_T_137, UInt<5>(0h11), _activated_wdata_e_act_raw_normDist_T_158)
node _activated_wdata_e_act_raw_normDist_T_160 = mux(_activated_wdata_e_act_raw_normDist_T_138, UInt<5>(0h10), _activated_wdata_e_act_raw_normDist_T_159)
node _activated_wdata_e_act_raw_normDist_T_161 = mux(_activated_wdata_e_act_raw_normDist_T_139, UInt<4>(0hf), _activated_wdata_e_act_raw_normDist_T_160)
node _activated_wdata_e_act_raw_normDist_T_162 = mux(_activated_wdata_e_act_raw_normDist_T_140, UInt<4>(0he), _activated_wdata_e_act_raw_normDist_T_161)
node _activated_wdata_e_act_raw_normDist_T_163 = mux(_activated_wdata_e_act_raw_normDist_T_141, UInt<4>(0hd), _activated_wdata_e_act_raw_normDist_T_162)
node _activated_wdata_e_act_raw_normDist_T_164 = mux(_activated_wdata_e_act_raw_normDist_T_142, UInt<4>(0hc), _activated_wdata_e_act_raw_normDist_T_163)
node _activated_wdata_e_act_raw_normDist_T_165 = mux(_activated_wdata_e_act_raw_normDist_T_143, UInt<4>(0hb), _activated_wdata_e_act_raw_normDist_T_164)
node _activated_wdata_e_act_raw_normDist_T_166 = mux(_activated_wdata_e_act_raw_normDist_T_144, UInt<4>(0ha), _activated_wdata_e_act_raw_normDist_T_165)
node _activated_wdata_e_act_raw_normDist_T_167 = mux(_activated_wdata_e_act_raw_normDist_T_145, UInt<4>(0h9), _activated_wdata_e_act_raw_normDist_T_166)
node _activated_wdata_e_act_raw_normDist_T_168 = mux(_activated_wdata_e_act_raw_normDist_T_146, UInt<4>(0h8), _activated_wdata_e_act_raw_normDist_T_167)
node _activated_wdata_e_act_raw_normDist_T_169 = mux(_activated_wdata_e_act_raw_normDist_T_147, UInt<3>(0h7), _activated_wdata_e_act_raw_normDist_T_168)
node _activated_wdata_e_act_raw_normDist_T_170 = mux(_activated_wdata_e_act_raw_normDist_T_148, UInt<3>(0h6), _activated_wdata_e_act_raw_normDist_T_169)
node _activated_wdata_e_act_raw_normDist_T_171 = mux(_activated_wdata_e_act_raw_normDist_T_149, UInt<3>(0h5), _activated_wdata_e_act_raw_normDist_T_170)
node _activated_wdata_e_act_raw_normDist_T_172 = mux(_activated_wdata_e_act_raw_normDist_T_150, UInt<3>(0h4), _activated_wdata_e_act_raw_normDist_T_171)
node _activated_wdata_e_act_raw_normDist_T_173 = mux(_activated_wdata_e_act_raw_normDist_T_151, UInt<2>(0h3), _activated_wdata_e_act_raw_normDist_T_172)
node _activated_wdata_e_act_raw_normDist_T_174 = mux(_activated_wdata_e_act_raw_normDist_T_152, UInt<2>(0h2), _activated_wdata_e_act_raw_normDist_T_173)
node _activated_wdata_e_act_raw_normDist_T_175 = mux(_activated_wdata_e_act_raw_normDist_T_153, UInt<1>(0h1), _activated_wdata_e_act_raw_normDist_T_174)
node activated_wdata_e_act_raw_normDist_3 = mux(_activated_wdata_e_act_raw_normDist_T_154, UInt<1>(0h0), _activated_wdata_e_act_raw_normDist_T_175)
node _activated_wdata_e_act_raw_subnormFract_T_6 = dshl(activated_wdata_e_act_raw_fractIn_3, activated_wdata_e_act_raw_normDist_3)
node _activated_wdata_e_act_raw_subnormFract_T_7 = bits(_activated_wdata_e_act_raw_subnormFract_T_6, 21, 0)
node activated_wdata_e_act_raw_subnormFract_3 = shl(_activated_wdata_e_act_raw_subnormFract_T_7, 1)
node _activated_wdata_e_act_raw_adjustedExp_T_15 = xor(activated_wdata_e_act_raw_normDist_3, UInt<9>(0h1ff))
node _activated_wdata_e_act_raw_adjustedExp_T_16 = mux(activated_wdata_e_act_raw_isZeroExpIn_3, _activated_wdata_e_act_raw_adjustedExp_T_15, activated_wdata_e_act_raw_expIn_3)
node _activated_wdata_e_act_raw_adjustedExp_T_17 = mux(activated_wdata_e_act_raw_isZeroExpIn_3, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_act_raw_adjustedExp_T_18 = or(UInt<8>(0h80), _activated_wdata_e_act_raw_adjustedExp_T_17)
node _activated_wdata_e_act_raw_adjustedExp_T_19 = add(_activated_wdata_e_act_raw_adjustedExp_T_16, _activated_wdata_e_act_raw_adjustedExp_T_18)
node activated_wdata_e_act_raw_adjustedExp_3 = tail(_activated_wdata_e_act_raw_adjustedExp_T_19, 1)
node activated_wdata_e_act_raw_isZero_3 = and(activated_wdata_e_act_raw_isZeroExpIn_3, activated_wdata_e_act_raw_isZeroFractIn_3)
node _activated_wdata_e_act_raw_isSpecial_T_3 = bits(activated_wdata_e_act_raw_adjustedExp_3, 8, 7)
node activated_wdata_e_act_raw_isSpecial_3 = eq(_activated_wdata_e_act_raw_isSpecial_T_3, UInt<2>(0h3))
wire activated_wdata_e_act_raw_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_act_raw_out_isNaN_T_6 = eq(activated_wdata_e_act_raw_isZeroFractIn_3, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_isNaN_T_7 = and(activated_wdata_e_act_raw_isSpecial_3, _activated_wdata_e_act_raw_out_isNaN_T_6)
connect activated_wdata_e_act_raw_3.isNaN, _activated_wdata_e_act_raw_out_isNaN_T_7
node _activated_wdata_e_act_raw_out_isInf_T_3 = and(activated_wdata_e_act_raw_isSpecial_3, activated_wdata_e_act_raw_isZeroFractIn_3)
connect activated_wdata_e_act_raw_3.isInf, _activated_wdata_e_act_raw_out_isInf_T_3
connect activated_wdata_e_act_raw_3.isZero, activated_wdata_e_act_raw_isZero_3
connect activated_wdata_e_act_raw_3.sign, activated_wdata_e_act_raw_sign_3
node _activated_wdata_e_act_raw_out_sExp_T_6 = bits(activated_wdata_e_act_raw_adjustedExp_3, 8, 0)
node _activated_wdata_e_act_raw_out_sExp_T_7 = cvt(_activated_wdata_e_act_raw_out_sExp_T_6)
connect activated_wdata_e_act_raw_3.sExp, _activated_wdata_e_act_raw_out_sExp_T_7
node _activated_wdata_e_act_raw_out_sig_T_12 = eq(activated_wdata_e_act_raw_isZero_3, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_sig_T_13 = cat(UInt<1>(0h0), _activated_wdata_e_act_raw_out_sig_T_12)
node _activated_wdata_e_act_raw_out_sig_T_14 = mux(activated_wdata_e_act_raw_isZeroExpIn_3, activated_wdata_e_act_raw_subnormFract_3, activated_wdata_e_act_raw_fractIn_3)
node _activated_wdata_e_act_raw_out_sig_T_15 = cat(_activated_wdata_e_act_raw_out_sig_T_13, _activated_wdata_e_act_raw_out_sig_T_14)
connect activated_wdata_e_act_raw_3.sig, _activated_wdata_e_act_raw_out_sig_T_15
wire activated_wdata_e_act_result_3 : { bits : UInt<32>}
node _activated_wdata_e_act_result_bits_T_9 = eq(activated_wdata_e_act_raw_3.isZero, UInt<1>(0h0))
node _activated_wdata_e_act_result_bits_T_10 = and(_activated_wdata_e_act_result_bits_T_9, activated_wdata_e_act_raw_3.sign)
node _activated_wdata_e_act_result_bits_T_11 = mux(_activated_wdata_e_act_result_bits_T_10, UInt<1>(0h0), activated_wdata_e_clipped_3.bits)
connect activated_wdata_e_act_result_3.bits, _activated_wdata_e_act_result_bits_T_11
node activated_wdata_e_act_3 = mux(_activated_wdata_e_act_T_3, activated_wdata_e_act_result_3, activated_wdata_e_clipped_3)
wire _activated_wdata_WIRE_3 : { bits : UInt<32>}[1]
connect _activated_wdata_WIRE_3[0], activated_wdata_e_act_3
wire activated_wdata : { bits : UInt<32>}[1][4]
connect activated_wdata[0], _activated_wdata_WIRE
connect activated_wdata[1], _activated_wdata_WIRE_1
connect activated_wdata[2], _activated_wdata_WIRE_2
connect activated_wdata[3], _activated_wdata_WIRE_3
node _io_srams_write_0_en_T = eq(w_bank, UInt<1>(0h0))
node _io_srams_write_0_en_T_1 = and(start_array_outputting, _io_srams_write_0_en_T)
node _io_srams_write_0_en_T_2 = eq(w_address.is_acc_addr, UInt<1>(0h0))
node _io_srams_write_0_en_T_3 = and(_io_srams_write_0_en_T_1, _io_srams_write_0_en_T_2)
node _io_srams_write_0_en_T_4 = eq(is_garbage_addr, UInt<1>(0h0))
node _io_srams_write_0_en_T_5 = and(_io_srams_write_0_en_T_3, _io_srams_write_0_en_T_4)
node _io_srams_write_0_en_T_6 = and(_io_srams_write_0_en_T_5, write_this_row)
connect io.srams.write[0].en, _io_srams_write_0_en_T_6
connect io.srams.write[0].addr, w_row
node io_srams_write_0_data_lo = cat(activated_wdata[1][0].bits, activated_wdata[0][0].bits)
node io_srams_write_0_data_hi = cat(activated_wdata[3][0].bits, activated_wdata[2][0].bits)
node _io_srams_write_0_data_T = cat(io_srams_write_0_data_hi, io_srams_write_0_data_lo)
connect io.srams.write[0].data, _io_srams_write_0_data_T
connect io.srams.write[0].mask[0], w_mask_0
connect io.srams.write[0].mask[1], w_mask_0
connect io.srams.write[0].mask[2], w_mask_0
connect io.srams.write[0].mask[3], w_mask_0
connect io.srams.write[0].mask[4], w_mask_1
connect io.srams.write[0].mask[5], w_mask_1
connect io.srams.write[0].mask[6], w_mask_1
connect io.srams.write[0].mask[7], w_mask_1
connect io.srams.write[0].mask[8], w_mask_2
connect io.srams.write[0].mask[9], w_mask_2
connect io.srams.write[0].mask[10], w_mask_2
connect io.srams.write[0].mask[11], w_mask_2
connect io.srams.write[0].mask[12], w_mask_3
connect io.srams.write[0].mask[13], w_mask_3
connect io.srams.write[0].mask[14], w_mask_3
connect io.srams.write[0].mask[15], w_mask_3
node activated_wdata_e_clipped_self_rec_rawIn_sign_4 = bits(mesh.io.resp.bits.data[0][0].bits, 31, 31)
node activated_wdata_e_clipped_self_rec_rawIn_expIn_4 = bits(mesh.io.resp.bits.data[0][0].bits, 30, 23)
node activated_wdata_e_clipped_self_rec_rawIn_fractIn_4 = bits(mesh.io.resp.bits.data[0][0].bits, 22, 0)
node activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_4 = eq(activated_wdata_e_clipped_self_rec_rawIn_expIn_4, UInt<1>(0h0))
node activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_4 = eq(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_176 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 0, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_177 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 1, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_178 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 2, 2)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_179 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 3, 3)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_180 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 4, 4)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_181 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 5, 5)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_182 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 6, 6)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_183 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 7, 7)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_184 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 8, 8)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_185 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 9, 9)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_186 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 10, 10)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_187 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 11, 11)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_188 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 12, 12)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_189 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 13, 13)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_190 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 14, 14)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_191 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 15, 15)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_192 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 16, 16)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_193 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 17, 17)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_194 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 18, 18)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_195 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 19, 19)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_196 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 20, 20)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_197 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 21, 21)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_198 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, 22, 22)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_199 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_177, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_200 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_178, UInt<5>(0h14), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_199)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_201 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_179, UInt<5>(0h13), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_200)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_202 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_180, UInt<5>(0h12), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_201)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_203 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_181, UInt<5>(0h11), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_202)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_204 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_182, UInt<5>(0h10), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_203)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_205 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_183, UInt<4>(0hf), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_204)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_206 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_184, UInt<4>(0he), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_205)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_207 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_185, UInt<4>(0hd), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_206)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_208 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_186, UInt<4>(0hc), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_207)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_209 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_187, UInt<4>(0hb), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_208)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_210 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_188, UInt<4>(0ha), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_209)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_211 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_189, UInt<4>(0h9), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_210)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_212 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_190, UInt<4>(0h8), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_211)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_213 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_191, UInt<3>(0h7), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_212)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_214 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_192, UInt<3>(0h6), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_213)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_215 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_193, UInt<3>(0h5), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_214)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_216 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_194, UInt<3>(0h4), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_215)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_217 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_195, UInt<2>(0h3), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_216)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_218 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_196, UInt<2>(0h2), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_217)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_219 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_197, UInt<1>(0h1), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_218)
node activated_wdata_e_clipped_self_rec_rawIn_normDist_4 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_198, UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_219)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_8 = dshl(activated_wdata_e_clipped_self_rec_rawIn_fractIn_4, activated_wdata_e_clipped_self_rec_rawIn_normDist_4)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_9 = bits(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_8, 21, 0)
node activated_wdata_e_clipped_self_rec_rawIn_subnormFract_4 = shl(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_9, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_20 = xor(activated_wdata_e_clipped_self_rec_rawIn_normDist_4, UInt<9>(0h1ff))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_21 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_4, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_20, activated_wdata_e_clipped_self_rec_rawIn_expIn_4)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_22 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_4, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_23 = or(UInt<8>(0h80), _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_22)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_24 = add(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_21, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_23)
node activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_4 = tail(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_24, 1)
node activated_wdata_e_clipped_self_rec_rawIn_isZero_4 = and(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_4, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_4)
node _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_4 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_4, 8, 7)
node activated_wdata_e_clipped_self_rec_rawIn_isSpecial_4 = eq(_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_4, UInt<2>(0h3))
wire activated_wdata_e_clipped_self_rec_rawIn_4 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_8 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_4, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_9 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_4, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_8)
connect activated_wdata_e_clipped_self_rec_rawIn_4.isNaN, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_9
node _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_4 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_4, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_4)
connect activated_wdata_e_clipped_self_rec_rawIn_4.isInf, _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_4
connect activated_wdata_e_clipped_self_rec_rawIn_4.isZero, activated_wdata_e_clipped_self_rec_rawIn_isZero_4
connect activated_wdata_e_clipped_self_rec_rawIn_4.sign, activated_wdata_e_clipped_self_rec_rawIn_sign_4
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_8 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_4, 8, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_9 = cvt(_activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_8)
connect activated_wdata_e_clipped_self_rec_rawIn_4.sExp, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_9
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_16 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZero_4, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_17 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_16)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_18 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_4, activated_wdata_e_clipped_self_rec_rawIn_subnormFract_4, activated_wdata_e_clipped_self_rec_rawIn_fractIn_4)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_19 = cat(_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_17, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_18)
connect activated_wdata_e_clipped_self_rec_rawIn_4.sig, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_19
node _activated_wdata_e_clipped_self_rec_T_32 = bits(activated_wdata_e_clipped_self_rec_rawIn_4.sExp, 8, 6)
node _activated_wdata_e_clipped_self_rec_T_33 = mux(activated_wdata_e_clipped_self_rec_rawIn_4.isZero, UInt<3>(0h0), _activated_wdata_e_clipped_self_rec_T_32)
node _activated_wdata_e_clipped_self_rec_T_34 = mux(activated_wdata_e_clipped_self_rec_rawIn_4.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_T_35 = or(_activated_wdata_e_clipped_self_rec_T_33, _activated_wdata_e_clipped_self_rec_T_34)
node _activated_wdata_e_clipped_self_rec_T_36 = cat(activated_wdata_e_clipped_self_rec_rawIn_4.sign, _activated_wdata_e_clipped_self_rec_T_35)
node _activated_wdata_e_clipped_self_rec_T_37 = bits(activated_wdata_e_clipped_self_rec_rawIn_4.sExp, 5, 0)
node _activated_wdata_e_clipped_self_rec_T_38 = cat(_activated_wdata_e_clipped_self_rec_T_36, _activated_wdata_e_clipped_self_rec_T_37)
node _activated_wdata_e_clipped_self_rec_T_39 = bits(activated_wdata_e_clipped_self_rec_rawIn_4.sig, 22, 0)
node activated_wdata_e_clipped_self_rec_4 = cat(_activated_wdata_e_clipped_self_rec_T_38, _activated_wdata_e_clipped_self_rec_T_39)
inst activated_wdata_e_clipped_resizer_4 of RecFNToRecFN_244
connect activated_wdata_e_clipped_resizer_4.io.in, activated_wdata_e_clipped_self_rec_4
connect activated_wdata_e_clipped_resizer_4.io.roundingMode, UInt<3>(0h0)
connect activated_wdata_e_clipped_resizer_4.io.detectTininess, UInt<1>(0h1)
wire activated_wdata_e_clipped_4 : { bits : UInt<32>}
node activated_wdata_e_clipped_result_bits_rawIn_exp_4 = bits(activated_wdata_e_clipped_resizer_4.io.out, 31, 23)
node _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_4 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_4, 8, 6)
node activated_wdata_e_clipped_result_bits_rawIn_isZero_4 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isZero_T_4, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_4 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_4, 8, 7)
node activated_wdata_e_clipped_result_bits_rawIn_isSpecial_4 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_4, UInt<2>(0h3))
wire activated_wdata_e_clipped_result_bits_rawIn_4 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_8 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_4, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_9 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_4, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_8)
connect activated_wdata_e_clipped_result_bits_rawIn_4.isNaN, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_9
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_12 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_4, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_13 = eq(_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_12, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_14 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_4, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_13)
connect activated_wdata_e_clipped_result_bits_rawIn_4.isInf, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_14
connect activated_wdata_e_clipped_result_bits_rawIn_4.isZero, activated_wdata_e_clipped_result_bits_rawIn_isZero_4
node _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_4 = bits(activated_wdata_e_clipped_resizer_4.io.out, 32, 32)
connect activated_wdata_e_clipped_result_bits_rawIn_4.sign, _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_4
node _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_4 = cvt(activated_wdata_e_clipped_result_bits_rawIn_exp_4)
connect activated_wdata_e_clipped_result_bits_rawIn_4.sExp, _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_4
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_16 = eq(activated_wdata_e_clipped_result_bits_rawIn_isZero_4, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_17 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_16)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_18 = bits(activated_wdata_e_clipped_resizer_4.io.out, 22, 0)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_19 = cat(_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_17, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_18)
connect activated_wdata_e_clipped_result_bits_rawIn_4.sig, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_19
node activated_wdata_e_clipped_result_bits_isSubnormal_4 = lt(activated_wdata_e_clipped_result_bits_rawIn_4.sExp, asSInt(UInt<9>(0h82)))
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_8 = bits(activated_wdata_e_clipped_result_bits_rawIn_4.sExp, 4, 0)
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_9 = sub(UInt<1>(0h1), _activated_wdata_e_clipped_result_bits_denormShiftDist_T_8)
node activated_wdata_e_clipped_result_bits_denormShiftDist_4 = tail(_activated_wdata_e_clipped_result_bits_denormShiftDist_T_9, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_8 = shr(activated_wdata_e_clipped_result_bits_rawIn_4.sig, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_9 = dshr(_activated_wdata_e_clipped_result_bits_denormFract_T_8, activated_wdata_e_clipped_result_bits_denormShiftDist_4)
node activated_wdata_e_clipped_result_bits_denormFract_4 = bits(_activated_wdata_e_clipped_result_bits_denormFract_T_9, 22, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_24 = bits(activated_wdata_e_clipped_result_bits_rawIn_4.sExp, 7, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_25 = sub(_activated_wdata_e_clipped_result_bits_expOut_T_24, UInt<8>(0h81))
node _activated_wdata_e_clipped_result_bits_expOut_T_26 = tail(_activated_wdata_e_clipped_result_bits_expOut_T_25, 1)
node _activated_wdata_e_clipped_result_bits_expOut_T_27 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_4, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_expOut_T_26)
node _activated_wdata_e_clipped_result_bits_expOut_T_28 = or(activated_wdata_e_clipped_result_bits_rawIn_4.isNaN, activated_wdata_e_clipped_result_bits_rawIn_4.isInf)
node _activated_wdata_e_clipped_result_bits_expOut_T_29 = mux(_activated_wdata_e_clipped_result_bits_expOut_T_28, UInt<8>(0hff), UInt<8>(0h0))
node activated_wdata_e_clipped_result_bits_expOut_4 = or(_activated_wdata_e_clipped_result_bits_expOut_T_27, _activated_wdata_e_clipped_result_bits_expOut_T_29)
node _activated_wdata_e_clipped_result_bits_fractOut_T_8 = bits(activated_wdata_e_clipped_result_bits_rawIn_4.sig, 22, 0)
node _activated_wdata_e_clipped_result_bits_fractOut_T_9 = mux(activated_wdata_e_clipped_result_bits_rawIn_4.isInf, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_fractOut_T_8)
node activated_wdata_e_clipped_result_bits_fractOut_4 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_4, activated_wdata_e_clipped_result_bits_denormFract_4, _activated_wdata_e_clipped_result_bits_fractOut_T_9)
node activated_wdata_e_clipped_result_bits_hi_4 = cat(activated_wdata_e_clipped_result_bits_rawIn_4.sign, activated_wdata_e_clipped_result_bits_expOut_4)
node _activated_wdata_e_clipped_result_bits_T_4 = cat(activated_wdata_e_clipped_result_bits_hi_4, activated_wdata_e_clipped_result_bits_fractOut_4)
connect activated_wdata_e_clipped_4.bits, _activated_wdata_e_clipped_result_bits_T_4
node _activated_wdata_e_act_T_4 = eq(activation, UInt<1>(0h1))
node activated_wdata_e_act_raw_sign_4 = bits(activated_wdata_e_clipped_4.bits, 31, 31)
node activated_wdata_e_act_raw_expIn_4 = bits(activated_wdata_e_clipped_4.bits, 30, 23)
node activated_wdata_e_act_raw_fractIn_4 = bits(activated_wdata_e_clipped_4.bits, 22, 0)
node activated_wdata_e_act_raw_isZeroExpIn_4 = eq(activated_wdata_e_act_raw_expIn_4, UInt<1>(0h0))
node activated_wdata_e_act_raw_isZeroFractIn_4 = eq(activated_wdata_e_act_raw_fractIn_4, UInt<1>(0h0))
node _activated_wdata_e_act_raw_normDist_T_176 = bits(activated_wdata_e_act_raw_fractIn_4, 0, 0)
node _activated_wdata_e_act_raw_normDist_T_177 = bits(activated_wdata_e_act_raw_fractIn_4, 1, 1)
node _activated_wdata_e_act_raw_normDist_T_178 = bits(activated_wdata_e_act_raw_fractIn_4, 2, 2)
node _activated_wdata_e_act_raw_normDist_T_179 = bits(activated_wdata_e_act_raw_fractIn_4, 3, 3)
node _activated_wdata_e_act_raw_normDist_T_180 = bits(activated_wdata_e_act_raw_fractIn_4, 4, 4)
node _activated_wdata_e_act_raw_normDist_T_181 = bits(activated_wdata_e_act_raw_fractIn_4, 5, 5)
node _activated_wdata_e_act_raw_normDist_T_182 = bits(activated_wdata_e_act_raw_fractIn_4, 6, 6)
node _activated_wdata_e_act_raw_normDist_T_183 = bits(activated_wdata_e_act_raw_fractIn_4, 7, 7)
node _activated_wdata_e_act_raw_normDist_T_184 = bits(activated_wdata_e_act_raw_fractIn_4, 8, 8)
node _activated_wdata_e_act_raw_normDist_T_185 = bits(activated_wdata_e_act_raw_fractIn_4, 9, 9)
node _activated_wdata_e_act_raw_normDist_T_186 = bits(activated_wdata_e_act_raw_fractIn_4, 10, 10)
node _activated_wdata_e_act_raw_normDist_T_187 = bits(activated_wdata_e_act_raw_fractIn_4, 11, 11)
node _activated_wdata_e_act_raw_normDist_T_188 = bits(activated_wdata_e_act_raw_fractIn_4, 12, 12)
node _activated_wdata_e_act_raw_normDist_T_189 = bits(activated_wdata_e_act_raw_fractIn_4, 13, 13)
node _activated_wdata_e_act_raw_normDist_T_190 = bits(activated_wdata_e_act_raw_fractIn_4, 14, 14)
node _activated_wdata_e_act_raw_normDist_T_191 = bits(activated_wdata_e_act_raw_fractIn_4, 15, 15)
node _activated_wdata_e_act_raw_normDist_T_192 = bits(activated_wdata_e_act_raw_fractIn_4, 16, 16)
node _activated_wdata_e_act_raw_normDist_T_193 = bits(activated_wdata_e_act_raw_fractIn_4, 17, 17)
node _activated_wdata_e_act_raw_normDist_T_194 = bits(activated_wdata_e_act_raw_fractIn_4, 18, 18)
node _activated_wdata_e_act_raw_normDist_T_195 = bits(activated_wdata_e_act_raw_fractIn_4, 19, 19)
node _activated_wdata_e_act_raw_normDist_T_196 = bits(activated_wdata_e_act_raw_fractIn_4, 20, 20)
node _activated_wdata_e_act_raw_normDist_T_197 = bits(activated_wdata_e_act_raw_fractIn_4, 21, 21)
node _activated_wdata_e_act_raw_normDist_T_198 = bits(activated_wdata_e_act_raw_fractIn_4, 22, 22)
node _activated_wdata_e_act_raw_normDist_T_199 = mux(_activated_wdata_e_act_raw_normDist_T_177, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_act_raw_normDist_T_200 = mux(_activated_wdata_e_act_raw_normDist_T_178, UInt<5>(0h14), _activated_wdata_e_act_raw_normDist_T_199)
node _activated_wdata_e_act_raw_normDist_T_201 = mux(_activated_wdata_e_act_raw_normDist_T_179, UInt<5>(0h13), _activated_wdata_e_act_raw_normDist_T_200)
node _activated_wdata_e_act_raw_normDist_T_202 = mux(_activated_wdata_e_act_raw_normDist_T_180, UInt<5>(0h12), _activated_wdata_e_act_raw_normDist_T_201)
node _activated_wdata_e_act_raw_normDist_T_203 = mux(_activated_wdata_e_act_raw_normDist_T_181, UInt<5>(0h11), _activated_wdata_e_act_raw_normDist_T_202)
node _activated_wdata_e_act_raw_normDist_T_204 = mux(_activated_wdata_e_act_raw_normDist_T_182, UInt<5>(0h10), _activated_wdata_e_act_raw_normDist_T_203)
node _activated_wdata_e_act_raw_normDist_T_205 = mux(_activated_wdata_e_act_raw_normDist_T_183, UInt<4>(0hf), _activated_wdata_e_act_raw_normDist_T_204)
node _activated_wdata_e_act_raw_normDist_T_206 = mux(_activated_wdata_e_act_raw_normDist_T_184, UInt<4>(0he), _activated_wdata_e_act_raw_normDist_T_205)
node _activated_wdata_e_act_raw_normDist_T_207 = mux(_activated_wdata_e_act_raw_normDist_T_185, UInt<4>(0hd), _activated_wdata_e_act_raw_normDist_T_206)
node _activated_wdata_e_act_raw_normDist_T_208 = mux(_activated_wdata_e_act_raw_normDist_T_186, UInt<4>(0hc), _activated_wdata_e_act_raw_normDist_T_207)
node _activated_wdata_e_act_raw_normDist_T_209 = mux(_activated_wdata_e_act_raw_normDist_T_187, UInt<4>(0hb), _activated_wdata_e_act_raw_normDist_T_208)
node _activated_wdata_e_act_raw_normDist_T_210 = mux(_activated_wdata_e_act_raw_normDist_T_188, UInt<4>(0ha), _activated_wdata_e_act_raw_normDist_T_209)
node _activated_wdata_e_act_raw_normDist_T_211 = mux(_activated_wdata_e_act_raw_normDist_T_189, UInt<4>(0h9), _activated_wdata_e_act_raw_normDist_T_210)
node _activated_wdata_e_act_raw_normDist_T_212 = mux(_activated_wdata_e_act_raw_normDist_T_190, UInt<4>(0h8), _activated_wdata_e_act_raw_normDist_T_211)
node _activated_wdata_e_act_raw_normDist_T_213 = mux(_activated_wdata_e_act_raw_normDist_T_191, UInt<3>(0h7), _activated_wdata_e_act_raw_normDist_T_212)
node _activated_wdata_e_act_raw_normDist_T_214 = mux(_activated_wdata_e_act_raw_normDist_T_192, UInt<3>(0h6), _activated_wdata_e_act_raw_normDist_T_213)
node _activated_wdata_e_act_raw_normDist_T_215 = mux(_activated_wdata_e_act_raw_normDist_T_193, UInt<3>(0h5), _activated_wdata_e_act_raw_normDist_T_214)
node _activated_wdata_e_act_raw_normDist_T_216 = mux(_activated_wdata_e_act_raw_normDist_T_194, UInt<3>(0h4), _activated_wdata_e_act_raw_normDist_T_215)
node _activated_wdata_e_act_raw_normDist_T_217 = mux(_activated_wdata_e_act_raw_normDist_T_195, UInt<2>(0h3), _activated_wdata_e_act_raw_normDist_T_216)
node _activated_wdata_e_act_raw_normDist_T_218 = mux(_activated_wdata_e_act_raw_normDist_T_196, UInt<2>(0h2), _activated_wdata_e_act_raw_normDist_T_217)
node _activated_wdata_e_act_raw_normDist_T_219 = mux(_activated_wdata_e_act_raw_normDist_T_197, UInt<1>(0h1), _activated_wdata_e_act_raw_normDist_T_218)
node activated_wdata_e_act_raw_normDist_4 = mux(_activated_wdata_e_act_raw_normDist_T_198, UInt<1>(0h0), _activated_wdata_e_act_raw_normDist_T_219)
node _activated_wdata_e_act_raw_subnormFract_T_8 = dshl(activated_wdata_e_act_raw_fractIn_4, activated_wdata_e_act_raw_normDist_4)
node _activated_wdata_e_act_raw_subnormFract_T_9 = bits(_activated_wdata_e_act_raw_subnormFract_T_8, 21, 0)
node activated_wdata_e_act_raw_subnormFract_4 = shl(_activated_wdata_e_act_raw_subnormFract_T_9, 1)
node _activated_wdata_e_act_raw_adjustedExp_T_20 = xor(activated_wdata_e_act_raw_normDist_4, UInt<9>(0h1ff))
node _activated_wdata_e_act_raw_adjustedExp_T_21 = mux(activated_wdata_e_act_raw_isZeroExpIn_4, _activated_wdata_e_act_raw_adjustedExp_T_20, activated_wdata_e_act_raw_expIn_4)
node _activated_wdata_e_act_raw_adjustedExp_T_22 = mux(activated_wdata_e_act_raw_isZeroExpIn_4, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_act_raw_adjustedExp_T_23 = or(UInt<8>(0h80), _activated_wdata_e_act_raw_adjustedExp_T_22)
node _activated_wdata_e_act_raw_adjustedExp_T_24 = add(_activated_wdata_e_act_raw_adjustedExp_T_21, _activated_wdata_e_act_raw_adjustedExp_T_23)
node activated_wdata_e_act_raw_adjustedExp_4 = tail(_activated_wdata_e_act_raw_adjustedExp_T_24, 1)
node activated_wdata_e_act_raw_isZero_4 = and(activated_wdata_e_act_raw_isZeroExpIn_4, activated_wdata_e_act_raw_isZeroFractIn_4)
node _activated_wdata_e_act_raw_isSpecial_T_4 = bits(activated_wdata_e_act_raw_adjustedExp_4, 8, 7)
node activated_wdata_e_act_raw_isSpecial_4 = eq(_activated_wdata_e_act_raw_isSpecial_T_4, UInt<2>(0h3))
wire activated_wdata_e_act_raw_4 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_act_raw_out_isNaN_T_8 = eq(activated_wdata_e_act_raw_isZeroFractIn_4, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_isNaN_T_9 = and(activated_wdata_e_act_raw_isSpecial_4, _activated_wdata_e_act_raw_out_isNaN_T_8)
connect activated_wdata_e_act_raw_4.isNaN, _activated_wdata_e_act_raw_out_isNaN_T_9
node _activated_wdata_e_act_raw_out_isInf_T_4 = and(activated_wdata_e_act_raw_isSpecial_4, activated_wdata_e_act_raw_isZeroFractIn_4)
connect activated_wdata_e_act_raw_4.isInf, _activated_wdata_e_act_raw_out_isInf_T_4
connect activated_wdata_e_act_raw_4.isZero, activated_wdata_e_act_raw_isZero_4
connect activated_wdata_e_act_raw_4.sign, activated_wdata_e_act_raw_sign_4
node _activated_wdata_e_act_raw_out_sExp_T_8 = bits(activated_wdata_e_act_raw_adjustedExp_4, 8, 0)
node _activated_wdata_e_act_raw_out_sExp_T_9 = cvt(_activated_wdata_e_act_raw_out_sExp_T_8)
connect activated_wdata_e_act_raw_4.sExp, _activated_wdata_e_act_raw_out_sExp_T_9
node _activated_wdata_e_act_raw_out_sig_T_16 = eq(activated_wdata_e_act_raw_isZero_4, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_sig_T_17 = cat(UInt<1>(0h0), _activated_wdata_e_act_raw_out_sig_T_16)
node _activated_wdata_e_act_raw_out_sig_T_18 = mux(activated_wdata_e_act_raw_isZeroExpIn_4, activated_wdata_e_act_raw_subnormFract_4, activated_wdata_e_act_raw_fractIn_4)
node _activated_wdata_e_act_raw_out_sig_T_19 = cat(_activated_wdata_e_act_raw_out_sig_T_17, _activated_wdata_e_act_raw_out_sig_T_18)
connect activated_wdata_e_act_raw_4.sig, _activated_wdata_e_act_raw_out_sig_T_19
wire activated_wdata_e_act_result_4 : { bits : UInt<32>}
node _activated_wdata_e_act_result_bits_T_12 = eq(activated_wdata_e_act_raw_4.isZero, UInt<1>(0h0))
node _activated_wdata_e_act_result_bits_T_13 = and(_activated_wdata_e_act_result_bits_T_12, activated_wdata_e_act_raw_4.sign)
node _activated_wdata_e_act_result_bits_T_14 = mux(_activated_wdata_e_act_result_bits_T_13, UInt<1>(0h0), activated_wdata_e_clipped_4.bits)
connect activated_wdata_e_act_result_4.bits, _activated_wdata_e_act_result_bits_T_14
node activated_wdata_e_act_4 = mux(_activated_wdata_e_act_T_4, activated_wdata_e_act_result_4, activated_wdata_e_clipped_4)
wire _activated_wdata_WIRE_4 : { bits : UInt<32>}[1]
connect _activated_wdata_WIRE_4[0], activated_wdata_e_act_4
node activated_wdata_e_clipped_self_rec_rawIn_sign_5 = bits(mesh.io.resp.bits.data[1][0].bits, 31, 31)
node activated_wdata_e_clipped_self_rec_rawIn_expIn_5 = bits(mesh.io.resp.bits.data[1][0].bits, 30, 23)
node activated_wdata_e_clipped_self_rec_rawIn_fractIn_5 = bits(mesh.io.resp.bits.data[1][0].bits, 22, 0)
node activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_5 = eq(activated_wdata_e_clipped_self_rec_rawIn_expIn_5, UInt<1>(0h0))
node activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_5 = eq(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_220 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 0, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_221 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 1, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_222 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 2, 2)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_223 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 3, 3)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_224 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 4, 4)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_225 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 5, 5)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_226 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 6, 6)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_227 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 7, 7)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_228 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 8, 8)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_229 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 9, 9)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_230 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 10, 10)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_231 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 11, 11)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_232 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 12, 12)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_233 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 13, 13)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_234 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 14, 14)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_235 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 15, 15)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_236 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 16, 16)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_237 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 17, 17)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_238 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 18, 18)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_239 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 19, 19)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_240 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 20, 20)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_241 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 21, 21)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_242 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, 22, 22)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_243 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_221, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_244 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_222, UInt<5>(0h14), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_243)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_245 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_223, UInt<5>(0h13), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_244)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_246 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_224, UInt<5>(0h12), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_245)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_247 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_225, UInt<5>(0h11), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_246)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_248 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_226, UInt<5>(0h10), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_247)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_249 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_227, UInt<4>(0hf), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_248)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_250 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_228, UInt<4>(0he), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_249)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_251 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_229, UInt<4>(0hd), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_250)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_252 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_230, UInt<4>(0hc), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_251)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_253 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_231, UInt<4>(0hb), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_252)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_254 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_232, UInt<4>(0ha), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_253)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_255 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_233, UInt<4>(0h9), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_254)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_256 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_234, UInt<4>(0h8), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_255)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_257 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_235, UInt<3>(0h7), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_256)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_258 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_236, UInt<3>(0h6), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_257)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_259 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_237, UInt<3>(0h5), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_258)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_260 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_238, UInt<3>(0h4), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_259)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_261 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_239, UInt<2>(0h3), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_260)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_262 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_240, UInt<2>(0h2), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_261)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_263 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_241, UInt<1>(0h1), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_262)
node activated_wdata_e_clipped_self_rec_rawIn_normDist_5 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_242, UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_263)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_10 = dshl(activated_wdata_e_clipped_self_rec_rawIn_fractIn_5, activated_wdata_e_clipped_self_rec_rawIn_normDist_5)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_11 = bits(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_10, 21, 0)
node activated_wdata_e_clipped_self_rec_rawIn_subnormFract_5 = shl(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_11, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_25 = xor(activated_wdata_e_clipped_self_rec_rawIn_normDist_5, UInt<9>(0h1ff))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_26 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_5, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_25, activated_wdata_e_clipped_self_rec_rawIn_expIn_5)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_27 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_5, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_28 = or(UInt<8>(0h80), _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_27)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_29 = add(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_26, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_28)
node activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_5 = tail(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_29, 1)
node activated_wdata_e_clipped_self_rec_rawIn_isZero_5 = and(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_5, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_5)
node _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_5 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_5, 8, 7)
node activated_wdata_e_clipped_self_rec_rawIn_isSpecial_5 = eq(_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_5, UInt<2>(0h3))
wire activated_wdata_e_clipped_self_rec_rawIn_5 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_10 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_5, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_11 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_5, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_10)
connect activated_wdata_e_clipped_self_rec_rawIn_5.isNaN, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_11
node _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_5 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_5, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_5)
connect activated_wdata_e_clipped_self_rec_rawIn_5.isInf, _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_5
connect activated_wdata_e_clipped_self_rec_rawIn_5.isZero, activated_wdata_e_clipped_self_rec_rawIn_isZero_5
connect activated_wdata_e_clipped_self_rec_rawIn_5.sign, activated_wdata_e_clipped_self_rec_rawIn_sign_5
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_10 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_5, 8, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_11 = cvt(_activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_10)
connect activated_wdata_e_clipped_self_rec_rawIn_5.sExp, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_11
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_20 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZero_5, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_21 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_20)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_22 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_5, activated_wdata_e_clipped_self_rec_rawIn_subnormFract_5, activated_wdata_e_clipped_self_rec_rawIn_fractIn_5)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_23 = cat(_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_21, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_22)
connect activated_wdata_e_clipped_self_rec_rawIn_5.sig, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_23
node _activated_wdata_e_clipped_self_rec_T_40 = bits(activated_wdata_e_clipped_self_rec_rawIn_5.sExp, 8, 6)
node _activated_wdata_e_clipped_self_rec_T_41 = mux(activated_wdata_e_clipped_self_rec_rawIn_5.isZero, UInt<3>(0h0), _activated_wdata_e_clipped_self_rec_T_40)
node _activated_wdata_e_clipped_self_rec_T_42 = mux(activated_wdata_e_clipped_self_rec_rawIn_5.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_T_43 = or(_activated_wdata_e_clipped_self_rec_T_41, _activated_wdata_e_clipped_self_rec_T_42)
node _activated_wdata_e_clipped_self_rec_T_44 = cat(activated_wdata_e_clipped_self_rec_rawIn_5.sign, _activated_wdata_e_clipped_self_rec_T_43)
node _activated_wdata_e_clipped_self_rec_T_45 = bits(activated_wdata_e_clipped_self_rec_rawIn_5.sExp, 5, 0)
node _activated_wdata_e_clipped_self_rec_T_46 = cat(_activated_wdata_e_clipped_self_rec_T_44, _activated_wdata_e_clipped_self_rec_T_45)
node _activated_wdata_e_clipped_self_rec_T_47 = bits(activated_wdata_e_clipped_self_rec_rawIn_5.sig, 22, 0)
node activated_wdata_e_clipped_self_rec_5 = cat(_activated_wdata_e_clipped_self_rec_T_46, _activated_wdata_e_clipped_self_rec_T_47)
inst activated_wdata_e_clipped_resizer_5 of RecFNToRecFN_245
connect activated_wdata_e_clipped_resizer_5.io.in, activated_wdata_e_clipped_self_rec_5
connect activated_wdata_e_clipped_resizer_5.io.roundingMode, UInt<3>(0h0)
connect activated_wdata_e_clipped_resizer_5.io.detectTininess, UInt<1>(0h1)
wire activated_wdata_e_clipped_5 : { bits : UInt<32>}
node activated_wdata_e_clipped_result_bits_rawIn_exp_5 = bits(activated_wdata_e_clipped_resizer_5.io.out, 31, 23)
node _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_5 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_5, 8, 6)
node activated_wdata_e_clipped_result_bits_rawIn_isZero_5 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isZero_T_5, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_5 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_5, 8, 7)
node activated_wdata_e_clipped_result_bits_rawIn_isSpecial_5 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_5, UInt<2>(0h3))
wire activated_wdata_e_clipped_result_bits_rawIn_5 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_10 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_5, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_11 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_5, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_10)
connect activated_wdata_e_clipped_result_bits_rawIn_5.isNaN, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_11
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_15 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_5, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_16 = eq(_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_15, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_17 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_5, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_16)
connect activated_wdata_e_clipped_result_bits_rawIn_5.isInf, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_17
connect activated_wdata_e_clipped_result_bits_rawIn_5.isZero, activated_wdata_e_clipped_result_bits_rawIn_isZero_5
node _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_5 = bits(activated_wdata_e_clipped_resizer_5.io.out, 32, 32)
connect activated_wdata_e_clipped_result_bits_rawIn_5.sign, _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_5
node _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_5 = cvt(activated_wdata_e_clipped_result_bits_rawIn_exp_5)
connect activated_wdata_e_clipped_result_bits_rawIn_5.sExp, _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_5
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_20 = eq(activated_wdata_e_clipped_result_bits_rawIn_isZero_5, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_21 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_20)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_22 = bits(activated_wdata_e_clipped_resizer_5.io.out, 22, 0)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_23 = cat(_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_21, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_22)
connect activated_wdata_e_clipped_result_bits_rawIn_5.sig, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_23
node activated_wdata_e_clipped_result_bits_isSubnormal_5 = lt(activated_wdata_e_clipped_result_bits_rawIn_5.sExp, asSInt(UInt<9>(0h82)))
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_10 = bits(activated_wdata_e_clipped_result_bits_rawIn_5.sExp, 4, 0)
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_11 = sub(UInt<1>(0h1), _activated_wdata_e_clipped_result_bits_denormShiftDist_T_10)
node activated_wdata_e_clipped_result_bits_denormShiftDist_5 = tail(_activated_wdata_e_clipped_result_bits_denormShiftDist_T_11, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_10 = shr(activated_wdata_e_clipped_result_bits_rawIn_5.sig, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_11 = dshr(_activated_wdata_e_clipped_result_bits_denormFract_T_10, activated_wdata_e_clipped_result_bits_denormShiftDist_5)
node activated_wdata_e_clipped_result_bits_denormFract_5 = bits(_activated_wdata_e_clipped_result_bits_denormFract_T_11, 22, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_30 = bits(activated_wdata_e_clipped_result_bits_rawIn_5.sExp, 7, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_31 = sub(_activated_wdata_e_clipped_result_bits_expOut_T_30, UInt<8>(0h81))
node _activated_wdata_e_clipped_result_bits_expOut_T_32 = tail(_activated_wdata_e_clipped_result_bits_expOut_T_31, 1)
node _activated_wdata_e_clipped_result_bits_expOut_T_33 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_5, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_expOut_T_32)
node _activated_wdata_e_clipped_result_bits_expOut_T_34 = or(activated_wdata_e_clipped_result_bits_rawIn_5.isNaN, activated_wdata_e_clipped_result_bits_rawIn_5.isInf)
node _activated_wdata_e_clipped_result_bits_expOut_T_35 = mux(_activated_wdata_e_clipped_result_bits_expOut_T_34, UInt<8>(0hff), UInt<8>(0h0))
node activated_wdata_e_clipped_result_bits_expOut_5 = or(_activated_wdata_e_clipped_result_bits_expOut_T_33, _activated_wdata_e_clipped_result_bits_expOut_T_35)
node _activated_wdata_e_clipped_result_bits_fractOut_T_10 = bits(activated_wdata_e_clipped_result_bits_rawIn_5.sig, 22, 0)
node _activated_wdata_e_clipped_result_bits_fractOut_T_11 = mux(activated_wdata_e_clipped_result_bits_rawIn_5.isInf, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_fractOut_T_10)
node activated_wdata_e_clipped_result_bits_fractOut_5 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_5, activated_wdata_e_clipped_result_bits_denormFract_5, _activated_wdata_e_clipped_result_bits_fractOut_T_11)
node activated_wdata_e_clipped_result_bits_hi_5 = cat(activated_wdata_e_clipped_result_bits_rawIn_5.sign, activated_wdata_e_clipped_result_bits_expOut_5)
node _activated_wdata_e_clipped_result_bits_T_5 = cat(activated_wdata_e_clipped_result_bits_hi_5, activated_wdata_e_clipped_result_bits_fractOut_5)
connect activated_wdata_e_clipped_5.bits, _activated_wdata_e_clipped_result_bits_T_5
node _activated_wdata_e_act_T_5 = eq(activation, UInt<1>(0h1))
node activated_wdata_e_act_raw_sign_5 = bits(activated_wdata_e_clipped_5.bits, 31, 31)
node activated_wdata_e_act_raw_expIn_5 = bits(activated_wdata_e_clipped_5.bits, 30, 23)
node activated_wdata_e_act_raw_fractIn_5 = bits(activated_wdata_e_clipped_5.bits, 22, 0)
node activated_wdata_e_act_raw_isZeroExpIn_5 = eq(activated_wdata_e_act_raw_expIn_5, UInt<1>(0h0))
node activated_wdata_e_act_raw_isZeroFractIn_5 = eq(activated_wdata_e_act_raw_fractIn_5, UInt<1>(0h0))
node _activated_wdata_e_act_raw_normDist_T_220 = bits(activated_wdata_e_act_raw_fractIn_5, 0, 0)
node _activated_wdata_e_act_raw_normDist_T_221 = bits(activated_wdata_e_act_raw_fractIn_5, 1, 1)
node _activated_wdata_e_act_raw_normDist_T_222 = bits(activated_wdata_e_act_raw_fractIn_5, 2, 2)
node _activated_wdata_e_act_raw_normDist_T_223 = bits(activated_wdata_e_act_raw_fractIn_5, 3, 3)
node _activated_wdata_e_act_raw_normDist_T_224 = bits(activated_wdata_e_act_raw_fractIn_5, 4, 4)
node _activated_wdata_e_act_raw_normDist_T_225 = bits(activated_wdata_e_act_raw_fractIn_5, 5, 5)
node _activated_wdata_e_act_raw_normDist_T_226 = bits(activated_wdata_e_act_raw_fractIn_5, 6, 6)
node _activated_wdata_e_act_raw_normDist_T_227 = bits(activated_wdata_e_act_raw_fractIn_5, 7, 7)
node _activated_wdata_e_act_raw_normDist_T_228 = bits(activated_wdata_e_act_raw_fractIn_5, 8, 8)
node _activated_wdata_e_act_raw_normDist_T_229 = bits(activated_wdata_e_act_raw_fractIn_5, 9, 9)
node _activated_wdata_e_act_raw_normDist_T_230 = bits(activated_wdata_e_act_raw_fractIn_5, 10, 10)
node _activated_wdata_e_act_raw_normDist_T_231 = bits(activated_wdata_e_act_raw_fractIn_5, 11, 11)
node _activated_wdata_e_act_raw_normDist_T_232 = bits(activated_wdata_e_act_raw_fractIn_5, 12, 12)
node _activated_wdata_e_act_raw_normDist_T_233 = bits(activated_wdata_e_act_raw_fractIn_5, 13, 13)
node _activated_wdata_e_act_raw_normDist_T_234 = bits(activated_wdata_e_act_raw_fractIn_5, 14, 14)
node _activated_wdata_e_act_raw_normDist_T_235 = bits(activated_wdata_e_act_raw_fractIn_5, 15, 15)
node _activated_wdata_e_act_raw_normDist_T_236 = bits(activated_wdata_e_act_raw_fractIn_5, 16, 16)
node _activated_wdata_e_act_raw_normDist_T_237 = bits(activated_wdata_e_act_raw_fractIn_5, 17, 17)
node _activated_wdata_e_act_raw_normDist_T_238 = bits(activated_wdata_e_act_raw_fractIn_5, 18, 18)
node _activated_wdata_e_act_raw_normDist_T_239 = bits(activated_wdata_e_act_raw_fractIn_5, 19, 19)
node _activated_wdata_e_act_raw_normDist_T_240 = bits(activated_wdata_e_act_raw_fractIn_5, 20, 20)
node _activated_wdata_e_act_raw_normDist_T_241 = bits(activated_wdata_e_act_raw_fractIn_5, 21, 21)
node _activated_wdata_e_act_raw_normDist_T_242 = bits(activated_wdata_e_act_raw_fractIn_5, 22, 22)
node _activated_wdata_e_act_raw_normDist_T_243 = mux(_activated_wdata_e_act_raw_normDist_T_221, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_act_raw_normDist_T_244 = mux(_activated_wdata_e_act_raw_normDist_T_222, UInt<5>(0h14), _activated_wdata_e_act_raw_normDist_T_243)
node _activated_wdata_e_act_raw_normDist_T_245 = mux(_activated_wdata_e_act_raw_normDist_T_223, UInt<5>(0h13), _activated_wdata_e_act_raw_normDist_T_244)
node _activated_wdata_e_act_raw_normDist_T_246 = mux(_activated_wdata_e_act_raw_normDist_T_224, UInt<5>(0h12), _activated_wdata_e_act_raw_normDist_T_245)
node _activated_wdata_e_act_raw_normDist_T_247 = mux(_activated_wdata_e_act_raw_normDist_T_225, UInt<5>(0h11), _activated_wdata_e_act_raw_normDist_T_246)
node _activated_wdata_e_act_raw_normDist_T_248 = mux(_activated_wdata_e_act_raw_normDist_T_226, UInt<5>(0h10), _activated_wdata_e_act_raw_normDist_T_247)
node _activated_wdata_e_act_raw_normDist_T_249 = mux(_activated_wdata_e_act_raw_normDist_T_227, UInt<4>(0hf), _activated_wdata_e_act_raw_normDist_T_248)
node _activated_wdata_e_act_raw_normDist_T_250 = mux(_activated_wdata_e_act_raw_normDist_T_228, UInt<4>(0he), _activated_wdata_e_act_raw_normDist_T_249)
node _activated_wdata_e_act_raw_normDist_T_251 = mux(_activated_wdata_e_act_raw_normDist_T_229, UInt<4>(0hd), _activated_wdata_e_act_raw_normDist_T_250)
node _activated_wdata_e_act_raw_normDist_T_252 = mux(_activated_wdata_e_act_raw_normDist_T_230, UInt<4>(0hc), _activated_wdata_e_act_raw_normDist_T_251)
node _activated_wdata_e_act_raw_normDist_T_253 = mux(_activated_wdata_e_act_raw_normDist_T_231, UInt<4>(0hb), _activated_wdata_e_act_raw_normDist_T_252)
node _activated_wdata_e_act_raw_normDist_T_254 = mux(_activated_wdata_e_act_raw_normDist_T_232, UInt<4>(0ha), _activated_wdata_e_act_raw_normDist_T_253)
node _activated_wdata_e_act_raw_normDist_T_255 = mux(_activated_wdata_e_act_raw_normDist_T_233, UInt<4>(0h9), _activated_wdata_e_act_raw_normDist_T_254)
node _activated_wdata_e_act_raw_normDist_T_256 = mux(_activated_wdata_e_act_raw_normDist_T_234, UInt<4>(0h8), _activated_wdata_e_act_raw_normDist_T_255)
node _activated_wdata_e_act_raw_normDist_T_257 = mux(_activated_wdata_e_act_raw_normDist_T_235, UInt<3>(0h7), _activated_wdata_e_act_raw_normDist_T_256)
node _activated_wdata_e_act_raw_normDist_T_258 = mux(_activated_wdata_e_act_raw_normDist_T_236, UInt<3>(0h6), _activated_wdata_e_act_raw_normDist_T_257)
node _activated_wdata_e_act_raw_normDist_T_259 = mux(_activated_wdata_e_act_raw_normDist_T_237, UInt<3>(0h5), _activated_wdata_e_act_raw_normDist_T_258)
node _activated_wdata_e_act_raw_normDist_T_260 = mux(_activated_wdata_e_act_raw_normDist_T_238, UInt<3>(0h4), _activated_wdata_e_act_raw_normDist_T_259)
node _activated_wdata_e_act_raw_normDist_T_261 = mux(_activated_wdata_e_act_raw_normDist_T_239, UInt<2>(0h3), _activated_wdata_e_act_raw_normDist_T_260)
node _activated_wdata_e_act_raw_normDist_T_262 = mux(_activated_wdata_e_act_raw_normDist_T_240, UInt<2>(0h2), _activated_wdata_e_act_raw_normDist_T_261)
node _activated_wdata_e_act_raw_normDist_T_263 = mux(_activated_wdata_e_act_raw_normDist_T_241, UInt<1>(0h1), _activated_wdata_e_act_raw_normDist_T_262)
node activated_wdata_e_act_raw_normDist_5 = mux(_activated_wdata_e_act_raw_normDist_T_242, UInt<1>(0h0), _activated_wdata_e_act_raw_normDist_T_263)
node _activated_wdata_e_act_raw_subnormFract_T_10 = dshl(activated_wdata_e_act_raw_fractIn_5, activated_wdata_e_act_raw_normDist_5)
node _activated_wdata_e_act_raw_subnormFract_T_11 = bits(_activated_wdata_e_act_raw_subnormFract_T_10, 21, 0)
node activated_wdata_e_act_raw_subnormFract_5 = shl(_activated_wdata_e_act_raw_subnormFract_T_11, 1)
node _activated_wdata_e_act_raw_adjustedExp_T_25 = xor(activated_wdata_e_act_raw_normDist_5, UInt<9>(0h1ff))
node _activated_wdata_e_act_raw_adjustedExp_T_26 = mux(activated_wdata_e_act_raw_isZeroExpIn_5, _activated_wdata_e_act_raw_adjustedExp_T_25, activated_wdata_e_act_raw_expIn_5)
node _activated_wdata_e_act_raw_adjustedExp_T_27 = mux(activated_wdata_e_act_raw_isZeroExpIn_5, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_act_raw_adjustedExp_T_28 = or(UInt<8>(0h80), _activated_wdata_e_act_raw_adjustedExp_T_27)
node _activated_wdata_e_act_raw_adjustedExp_T_29 = add(_activated_wdata_e_act_raw_adjustedExp_T_26, _activated_wdata_e_act_raw_adjustedExp_T_28)
node activated_wdata_e_act_raw_adjustedExp_5 = tail(_activated_wdata_e_act_raw_adjustedExp_T_29, 1)
node activated_wdata_e_act_raw_isZero_5 = and(activated_wdata_e_act_raw_isZeroExpIn_5, activated_wdata_e_act_raw_isZeroFractIn_5)
node _activated_wdata_e_act_raw_isSpecial_T_5 = bits(activated_wdata_e_act_raw_adjustedExp_5, 8, 7)
node activated_wdata_e_act_raw_isSpecial_5 = eq(_activated_wdata_e_act_raw_isSpecial_T_5, UInt<2>(0h3))
wire activated_wdata_e_act_raw_5 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_act_raw_out_isNaN_T_10 = eq(activated_wdata_e_act_raw_isZeroFractIn_5, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_isNaN_T_11 = and(activated_wdata_e_act_raw_isSpecial_5, _activated_wdata_e_act_raw_out_isNaN_T_10)
connect activated_wdata_e_act_raw_5.isNaN, _activated_wdata_e_act_raw_out_isNaN_T_11
node _activated_wdata_e_act_raw_out_isInf_T_5 = and(activated_wdata_e_act_raw_isSpecial_5, activated_wdata_e_act_raw_isZeroFractIn_5)
connect activated_wdata_e_act_raw_5.isInf, _activated_wdata_e_act_raw_out_isInf_T_5
connect activated_wdata_e_act_raw_5.isZero, activated_wdata_e_act_raw_isZero_5
connect activated_wdata_e_act_raw_5.sign, activated_wdata_e_act_raw_sign_5
node _activated_wdata_e_act_raw_out_sExp_T_10 = bits(activated_wdata_e_act_raw_adjustedExp_5, 8, 0)
node _activated_wdata_e_act_raw_out_sExp_T_11 = cvt(_activated_wdata_e_act_raw_out_sExp_T_10)
connect activated_wdata_e_act_raw_5.sExp, _activated_wdata_e_act_raw_out_sExp_T_11
node _activated_wdata_e_act_raw_out_sig_T_20 = eq(activated_wdata_e_act_raw_isZero_5, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_sig_T_21 = cat(UInt<1>(0h0), _activated_wdata_e_act_raw_out_sig_T_20)
node _activated_wdata_e_act_raw_out_sig_T_22 = mux(activated_wdata_e_act_raw_isZeroExpIn_5, activated_wdata_e_act_raw_subnormFract_5, activated_wdata_e_act_raw_fractIn_5)
node _activated_wdata_e_act_raw_out_sig_T_23 = cat(_activated_wdata_e_act_raw_out_sig_T_21, _activated_wdata_e_act_raw_out_sig_T_22)
connect activated_wdata_e_act_raw_5.sig, _activated_wdata_e_act_raw_out_sig_T_23
wire activated_wdata_e_act_result_5 : { bits : UInt<32>}
node _activated_wdata_e_act_result_bits_T_15 = eq(activated_wdata_e_act_raw_5.isZero, UInt<1>(0h0))
node _activated_wdata_e_act_result_bits_T_16 = and(_activated_wdata_e_act_result_bits_T_15, activated_wdata_e_act_raw_5.sign)
node _activated_wdata_e_act_result_bits_T_17 = mux(_activated_wdata_e_act_result_bits_T_16, UInt<1>(0h0), activated_wdata_e_clipped_5.bits)
connect activated_wdata_e_act_result_5.bits, _activated_wdata_e_act_result_bits_T_17
node activated_wdata_e_act_5 = mux(_activated_wdata_e_act_T_5, activated_wdata_e_act_result_5, activated_wdata_e_clipped_5)
wire _activated_wdata_WIRE_5 : { bits : UInt<32>}[1]
connect _activated_wdata_WIRE_5[0], activated_wdata_e_act_5
node activated_wdata_e_clipped_self_rec_rawIn_sign_6 = bits(mesh.io.resp.bits.data[2][0].bits, 31, 31)
node activated_wdata_e_clipped_self_rec_rawIn_expIn_6 = bits(mesh.io.resp.bits.data[2][0].bits, 30, 23)
node activated_wdata_e_clipped_self_rec_rawIn_fractIn_6 = bits(mesh.io.resp.bits.data[2][0].bits, 22, 0)
node activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_6 = eq(activated_wdata_e_clipped_self_rec_rawIn_expIn_6, UInt<1>(0h0))
node activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_6 = eq(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_264 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 0, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_265 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 1, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_266 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 2, 2)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_267 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 3, 3)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_268 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 4, 4)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_269 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 5, 5)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_270 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 6, 6)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_271 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 7, 7)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_272 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 8, 8)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_273 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 9, 9)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_274 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 10, 10)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_275 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 11, 11)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_276 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 12, 12)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_277 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 13, 13)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_278 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 14, 14)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_279 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 15, 15)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_280 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 16, 16)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_281 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 17, 17)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_282 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 18, 18)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_283 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 19, 19)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_284 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 20, 20)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_285 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 21, 21)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_286 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, 22, 22)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_287 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_265, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_288 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_266, UInt<5>(0h14), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_287)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_289 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_267, UInt<5>(0h13), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_288)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_290 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_268, UInt<5>(0h12), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_289)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_291 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_269, UInt<5>(0h11), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_290)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_292 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_270, UInt<5>(0h10), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_291)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_293 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_271, UInt<4>(0hf), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_292)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_294 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_272, UInt<4>(0he), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_293)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_295 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_273, UInt<4>(0hd), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_294)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_296 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_274, UInt<4>(0hc), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_295)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_297 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_275, UInt<4>(0hb), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_296)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_298 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_276, UInt<4>(0ha), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_297)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_299 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_277, UInt<4>(0h9), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_298)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_300 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_278, UInt<4>(0h8), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_299)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_301 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_279, UInt<3>(0h7), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_300)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_302 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_280, UInt<3>(0h6), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_301)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_303 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_281, UInt<3>(0h5), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_302)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_304 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_282, UInt<3>(0h4), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_303)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_305 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_283, UInt<2>(0h3), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_304)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_306 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_284, UInt<2>(0h2), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_305)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_307 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_285, UInt<1>(0h1), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_306)
node activated_wdata_e_clipped_self_rec_rawIn_normDist_6 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_286, UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_307)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_12 = dshl(activated_wdata_e_clipped_self_rec_rawIn_fractIn_6, activated_wdata_e_clipped_self_rec_rawIn_normDist_6)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_13 = bits(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_12, 21, 0)
node activated_wdata_e_clipped_self_rec_rawIn_subnormFract_6 = shl(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_13, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_30 = xor(activated_wdata_e_clipped_self_rec_rawIn_normDist_6, UInt<9>(0h1ff))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_31 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_6, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_30, activated_wdata_e_clipped_self_rec_rawIn_expIn_6)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_32 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_6, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_33 = or(UInt<8>(0h80), _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_32)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_34 = add(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_31, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_33)
node activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_6 = tail(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_34, 1)
node activated_wdata_e_clipped_self_rec_rawIn_isZero_6 = and(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_6, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_6)
node _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_6 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_6, 8, 7)
node activated_wdata_e_clipped_self_rec_rawIn_isSpecial_6 = eq(_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_6, UInt<2>(0h3))
wire activated_wdata_e_clipped_self_rec_rawIn_6 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_12 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_6, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_13 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_6, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_12)
connect activated_wdata_e_clipped_self_rec_rawIn_6.isNaN, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_13
node _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_6 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_6, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_6)
connect activated_wdata_e_clipped_self_rec_rawIn_6.isInf, _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_6
connect activated_wdata_e_clipped_self_rec_rawIn_6.isZero, activated_wdata_e_clipped_self_rec_rawIn_isZero_6
connect activated_wdata_e_clipped_self_rec_rawIn_6.sign, activated_wdata_e_clipped_self_rec_rawIn_sign_6
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_12 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_6, 8, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_13 = cvt(_activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_12)
connect activated_wdata_e_clipped_self_rec_rawIn_6.sExp, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_13
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_24 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZero_6, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_25 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_24)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_26 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_6, activated_wdata_e_clipped_self_rec_rawIn_subnormFract_6, activated_wdata_e_clipped_self_rec_rawIn_fractIn_6)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_27 = cat(_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_25, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_26)
connect activated_wdata_e_clipped_self_rec_rawIn_6.sig, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_27
node _activated_wdata_e_clipped_self_rec_T_48 = bits(activated_wdata_e_clipped_self_rec_rawIn_6.sExp, 8, 6)
node _activated_wdata_e_clipped_self_rec_T_49 = mux(activated_wdata_e_clipped_self_rec_rawIn_6.isZero, UInt<3>(0h0), _activated_wdata_e_clipped_self_rec_T_48)
node _activated_wdata_e_clipped_self_rec_T_50 = mux(activated_wdata_e_clipped_self_rec_rawIn_6.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_T_51 = or(_activated_wdata_e_clipped_self_rec_T_49, _activated_wdata_e_clipped_self_rec_T_50)
node _activated_wdata_e_clipped_self_rec_T_52 = cat(activated_wdata_e_clipped_self_rec_rawIn_6.sign, _activated_wdata_e_clipped_self_rec_T_51)
node _activated_wdata_e_clipped_self_rec_T_53 = bits(activated_wdata_e_clipped_self_rec_rawIn_6.sExp, 5, 0)
node _activated_wdata_e_clipped_self_rec_T_54 = cat(_activated_wdata_e_clipped_self_rec_T_52, _activated_wdata_e_clipped_self_rec_T_53)
node _activated_wdata_e_clipped_self_rec_T_55 = bits(activated_wdata_e_clipped_self_rec_rawIn_6.sig, 22, 0)
node activated_wdata_e_clipped_self_rec_6 = cat(_activated_wdata_e_clipped_self_rec_T_54, _activated_wdata_e_clipped_self_rec_T_55)
inst activated_wdata_e_clipped_resizer_6 of RecFNToRecFN_246
connect activated_wdata_e_clipped_resizer_6.io.in, activated_wdata_e_clipped_self_rec_6
connect activated_wdata_e_clipped_resizer_6.io.roundingMode, UInt<3>(0h0)
connect activated_wdata_e_clipped_resizer_6.io.detectTininess, UInt<1>(0h1)
wire activated_wdata_e_clipped_6 : { bits : UInt<32>}
node activated_wdata_e_clipped_result_bits_rawIn_exp_6 = bits(activated_wdata_e_clipped_resizer_6.io.out, 31, 23)
node _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_6 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_6, 8, 6)
node activated_wdata_e_clipped_result_bits_rawIn_isZero_6 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isZero_T_6, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_6 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_6, 8, 7)
node activated_wdata_e_clipped_result_bits_rawIn_isSpecial_6 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_6, UInt<2>(0h3))
wire activated_wdata_e_clipped_result_bits_rawIn_6 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_12 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_6, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_13 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_6, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_12)
connect activated_wdata_e_clipped_result_bits_rawIn_6.isNaN, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_13
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_18 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_6, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_19 = eq(_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_18, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_20 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_6, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_19)
connect activated_wdata_e_clipped_result_bits_rawIn_6.isInf, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_20
connect activated_wdata_e_clipped_result_bits_rawIn_6.isZero, activated_wdata_e_clipped_result_bits_rawIn_isZero_6
node _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_6 = bits(activated_wdata_e_clipped_resizer_6.io.out, 32, 32)
connect activated_wdata_e_clipped_result_bits_rawIn_6.sign, _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_6
node _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_6 = cvt(activated_wdata_e_clipped_result_bits_rawIn_exp_6)
connect activated_wdata_e_clipped_result_bits_rawIn_6.sExp, _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_6
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_24 = eq(activated_wdata_e_clipped_result_bits_rawIn_isZero_6, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_25 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_24)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_26 = bits(activated_wdata_e_clipped_resizer_6.io.out, 22, 0)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_27 = cat(_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_25, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_26)
connect activated_wdata_e_clipped_result_bits_rawIn_6.sig, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_27
node activated_wdata_e_clipped_result_bits_isSubnormal_6 = lt(activated_wdata_e_clipped_result_bits_rawIn_6.sExp, asSInt(UInt<9>(0h82)))
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_12 = bits(activated_wdata_e_clipped_result_bits_rawIn_6.sExp, 4, 0)
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_13 = sub(UInt<1>(0h1), _activated_wdata_e_clipped_result_bits_denormShiftDist_T_12)
node activated_wdata_e_clipped_result_bits_denormShiftDist_6 = tail(_activated_wdata_e_clipped_result_bits_denormShiftDist_T_13, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_12 = shr(activated_wdata_e_clipped_result_bits_rawIn_6.sig, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_13 = dshr(_activated_wdata_e_clipped_result_bits_denormFract_T_12, activated_wdata_e_clipped_result_bits_denormShiftDist_6)
node activated_wdata_e_clipped_result_bits_denormFract_6 = bits(_activated_wdata_e_clipped_result_bits_denormFract_T_13, 22, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_36 = bits(activated_wdata_e_clipped_result_bits_rawIn_6.sExp, 7, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_37 = sub(_activated_wdata_e_clipped_result_bits_expOut_T_36, UInt<8>(0h81))
node _activated_wdata_e_clipped_result_bits_expOut_T_38 = tail(_activated_wdata_e_clipped_result_bits_expOut_T_37, 1)
node _activated_wdata_e_clipped_result_bits_expOut_T_39 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_6, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_expOut_T_38)
node _activated_wdata_e_clipped_result_bits_expOut_T_40 = or(activated_wdata_e_clipped_result_bits_rawIn_6.isNaN, activated_wdata_e_clipped_result_bits_rawIn_6.isInf)
node _activated_wdata_e_clipped_result_bits_expOut_T_41 = mux(_activated_wdata_e_clipped_result_bits_expOut_T_40, UInt<8>(0hff), UInt<8>(0h0))
node activated_wdata_e_clipped_result_bits_expOut_6 = or(_activated_wdata_e_clipped_result_bits_expOut_T_39, _activated_wdata_e_clipped_result_bits_expOut_T_41)
node _activated_wdata_e_clipped_result_bits_fractOut_T_12 = bits(activated_wdata_e_clipped_result_bits_rawIn_6.sig, 22, 0)
node _activated_wdata_e_clipped_result_bits_fractOut_T_13 = mux(activated_wdata_e_clipped_result_bits_rawIn_6.isInf, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_fractOut_T_12)
node activated_wdata_e_clipped_result_bits_fractOut_6 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_6, activated_wdata_e_clipped_result_bits_denormFract_6, _activated_wdata_e_clipped_result_bits_fractOut_T_13)
node activated_wdata_e_clipped_result_bits_hi_6 = cat(activated_wdata_e_clipped_result_bits_rawIn_6.sign, activated_wdata_e_clipped_result_bits_expOut_6)
node _activated_wdata_e_clipped_result_bits_T_6 = cat(activated_wdata_e_clipped_result_bits_hi_6, activated_wdata_e_clipped_result_bits_fractOut_6)
connect activated_wdata_e_clipped_6.bits, _activated_wdata_e_clipped_result_bits_T_6
node _activated_wdata_e_act_T_6 = eq(activation, UInt<1>(0h1))
node activated_wdata_e_act_raw_sign_6 = bits(activated_wdata_e_clipped_6.bits, 31, 31)
node activated_wdata_e_act_raw_expIn_6 = bits(activated_wdata_e_clipped_6.bits, 30, 23)
node activated_wdata_e_act_raw_fractIn_6 = bits(activated_wdata_e_clipped_6.bits, 22, 0)
node activated_wdata_e_act_raw_isZeroExpIn_6 = eq(activated_wdata_e_act_raw_expIn_6, UInt<1>(0h0))
node activated_wdata_e_act_raw_isZeroFractIn_6 = eq(activated_wdata_e_act_raw_fractIn_6, UInt<1>(0h0))
node _activated_wdata_e_act_raw_normDist_T_264 = bits(activated_wdata_e_act_raw_fractIn_6, 0, 0)
node _activated_wdata_e_act_raw_normDist_T_265 = bits(activated_wdata_e_act_raw_fractIn_6, 1, 1)
node _activated_wdata_e_act_raw_normDist_T_266 = bits(activated_wdata_e_act_raw_fractIn_6, 2, 2)
node _activated_wdata_e_act_raw_normDist_T_267 = bits(activated_wdata_e_act_raw_fractIn_6, 3, 3)
node _activated_wdata_e_act_raw_normDist_T_268 = bits(activated_wdata_e_act_raw_fractIn_6, 4, 4)
node _activated_wdata_e_act_raw_normDist_T_269 = bits(activated_wdata_e_act_raw_fractIn_6, 5, 5)
node _activated_wdata_e_act_raw_normDist_T_270 = bits(activated_wdata_e_act_raw_fractIn_6, 6, 6)
node _activated_wdata_e_act_raw_normDist_T_271 = bits(activated_wdata_e_act_raw_fractIn_6, 7, 7)
node _activated_wdata_e_act_raw_normDist_T_272 = bits(activated_wdata_e_act_raw_fractIn_6, 8, 8)
node _activated_wdata_e_act_raw_normDist_T_273 = bits(activated_wdata_e_act_raw_fractIn_6, 9, 9)
node _activated_wdata_e_act_raw_normDist_T_274 = bits(activated_wdata_e_act_raw_fractIn_6, 10, 10)
node _activated_wdata_e_act_raw_normDist_T_275 = bits(activated_wdata_e_act_raw_fractIn_6, 11, 11)
node _activated_wdata_e_act_raw_normDist_T_276 = bits(activated_wdata_e_act_raw_fractIn_6, 12, 12)
node _activated_wdata_e_act_raw_normDist_T_277 = bits(activated_wdata_e_act_raw_fractIn_6, 13, 13)
node _activated_wdata_e_act_raw_normDist_T_278 = bits(activated_wdata_e_act_raw_fractIn_6, 14, 14)
node _activated_wdata_e_act_raw_normDist_T_279 = bits(activated_wdata_e_act_raw_fractIn_6, 15, 15)
node _activated_wdata_e_act_raw_normDist_T_280 = bits(activated_wdata_e_act_raw_fractIn_6, 16, 16)
node _activated_wdata_e_act_raw_normDist_T_281 = bits(activated_wdata_e_act_raw_fractIn_6, 17, 17)
node _activated_wdata_e_act_raw_normDist_T_282 = bits(activated_wdata_e_act_raw_fractIn_6, 18, 18)
node _activated_wdata_e_act_raw_normDist_T_283 = bits(activated_wdata_e_act_raw_fractIn_6, 19, 19)
node _activated_wdata_e_act_raw_normDist_T_284 = bits(activated_wdata_e_act_raw_fractIn_6, 20, 20)
node _activated_wdata_e_act_raw_normDist_T_285 = bits(activated_wdata_e_act_raw_fractIn_6, 21, 21)
node _activated_wdata_e_act_raw_normDist_T_286 = bits(activated_wdata_e_act_raw_fractIn_6, 22, 22)
node _activated_wdata_e_act_raw_normDist_T_287 = mux(_activated_wdata_e_act_raw_normDist_T_265, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_act_raw_normDist_T_288 = mux(_activated_wdata_e_act_raw_normDist_T_266, UInt<5>(0h14), _activated_wdata_e_act_raw_normDist_T_287)
node _activated_wdata_e_act_raw_normDist_T_289 = mux(_activated_wdata_e_act_raw_normDist_T_267, UInt<5>(0h13), _activated_wdata_e_act_raw_normDist_T_288)
node _activated_wdata_e_act_raw_normDist_T_290 = mux(_activated_wdata_e_act_raw_normDist_T_268, UInt<5>(0h12), _activated_wdata_e_act_raw_normDist_T_289)
node _activated_wdata_e_act_raw_normDist_T_291 = mux(_activated_wdata_e_act_raw_normDist_T_269, UInt<5>(0h11), _activated_wdata_e_act_raw_normDist_T_290)
node _activated_wdata_e_act_raw_normDist_T_292 = mux(_activated_wdata_e_act_raw_normDist_T_270, UInt<5>(0h10), _activated_wdata_e_act_raw_normDist_T_291)
node _activated_wdata_e_act_raw_normDist_T_293 = mux(_activated_wdata_e_act_raw_normDist_T_271, UInt<4>(0hf), _activated_wdata_e_act_raw_normDist_T_292)
node _activated_wdata_e_act_raw_normDist_T_294 = mux(_activated_wdata_e_act_raw_normDist_T_272, UInt<4>(0he), _activated_wdata_e_act_raw_normDist_T_293)
node _activated_wdata_e_act_raw_normDist_T_295 = mux(_activated_wdata_e_act_raw_normDist_T_273, UInt<4>(0hd), _activated_wdata_e_act_raw_normDist_T_294)
node _activated_wdata_e_act_raw_normDist_T_296 = mux(_activated_wdata_e_act_raw_normDist_T_274, UInt<4>(0hc), _activated_wdata_e_act_raw_normDist_T_295)
node _activated_wdata_e_act_raw_normDist_T_297 = mux(_activated_wdata_e_act_raw_normDist_T_275, UInt<4>(0hb), _activated_wdata_e_act_raw_normDist_T_296)
node _activated_wdata_e_act_raw_normDist_T_298 = mux(_activated_wdata_e_act_raw_normDist_T_276, UInt<4>(0ha), _activated_wdata_e_act_raw_normDist_T_297)
node _activated_wdata_e_act_raw_normDist_T_299 = mux(_activated_wdata_e_act_raw_normDist_T_277, UInt<4>(0h9), _activated_wdata_e_act_raw_normDist_T_298)
node _activated_wdata_e_act_raw_normDist_T_300 = mux(_activated_wdata_e_act_raw_normDist_T_278, UInt<4>(0h8), _activated_wdata_e_act_raw_normDist_T_299)
node _activated_wdata_e_act_raw_normDist_T_301 = mux(_activated_wdata_e_act_raw_normDist_T_279, UInt<3>(0h7), _activated_wdata_e_act_raw_normDist_T_300)
node _activated_wdata_e_act_raw_normDist_T_302 = mux(_activated_wdata_e_act_raw_normDist_T_280, UInt<3>(0h6), _activated_wdata_e_act_raw_normDist_T_301)
node _activated_wdata_e_act_raw_normDist_T_303 = mux(_activated_wdata_e_act_raw_normDist_T_281, UInt<3>(0h5), _activated_wdata_e_act_raw_normDist_T_302)
node _activated_wdata_e_act_raw_normDist_T_304 = mux(_activated_wdata_e_act_raw_normDist_T_282, UInt<3>(0h4), _activated_wdata_e_act_raw_normDist_T_303)
node _activated_wdata_e_act_raw_normDist_T_305 = mux(_activated_wdata_e_act_raw_normDist_T_283, UInt<2>(0h3), _activated_wdata_e_act_raw_normDist_T_304)
node _activated_wdata_e_act_raw_normDist_T_306 = mux(_activated_wdata_e_act_raw_normDist_T_284, UInt<2>(0h2), _activated_wdata_e_act_raw_normDist_T_305)
node _activated_wdata_e_act_raw_normDist_T_307 = mux(_activated_wdata_e_act_raw_normDist_T_285, UInt<1>(0h1), _activated_wdata_e_act_raw_normDist_T_306)
node activated_wdata_e_act_raw_normDist_6 = mux(_activated_wdata_e_act_raw_normDist_T_286, UInt<1>(0h0), _activated_wdata_e_act_raw_normDist_T_307)
node _activated_wdata_e_act_raw_subnormFract_T_12 = dshl(activated_wdata_e_act_raw_fractIn_6, activated_wdata_e_act_raw_normDist_6)
node _activated_wdata_e_act_raw_subnormFract_T_13 = bits(_activated_wdata_e_act_raw_subnormFract_T_12, 21, 0)
node activated_wdata_e_act_raw_subnormFract_6 = shl(_activated_wdata_e_act_raw_subnormFract_T_13, 1)
node _activated_wdata_e_act_raw_adjustedExp_T_30 = xor(activated_wdata_e_act_raw_normDist_6, UInt<9>(0h1ff))
node _activated_wdata_e_act_raw_adjustedExp_T_31 = mux(activated_wdata_e_act_raw_isZeroExpIn_6, _activated_wdata_e_act_raw_adjustedExp_T_30, activated_wdata_e_act_raw_expIn_6)
node _activated_wdata_e_act_raw_adjustedExp_T_32 = mux(activated_wdata_e_act_raw_isZeroExpIn_6, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_act_raw_adjustedExp_T_33 = or(UInt<8>(0h80), _activated_wdata_e_act_raw_adjustedExp_T_32)
node _activated_wdata_e_act_raw_adjustedExp_T_34 = add(_activated_wdata_e_act_raw_adjustedExp_T_31, _activated_wdata_e_act_raw_adjustedExp_T_33)
node activated_wdata_e_act_raw_adjustedExp_6 = tail(_activated_wdata_e_act_raw_adjustedExp_T_34, 1)
node activated_wdata_e_act_raw_isZero_6 = and(activated_wdata_e_act_raw_isZeroExpIn_6, activated_wdata_e_act_raw_isZeroFractIn_6)
node _activated_wdata_e_act_raw_isSpecial_T_6 = bits(activated_wdata_e_act_raw_adjustedExp_6, 8, 7)
node activated_wdata_e_act_raw_isSpecial_6 = eq(_activated_wdata_e_act_raw_isSpecial_T_6, UInt<2>(0h3))
wire activated_wdata_e_act_raw_6 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_act_raw_out_isNaN_T_12 = eq(activated_wdata_e_act_raw_isZeroFractIn_6, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_isNaN_T_13 = and(activated_wdata_e_act_raw_isSpecial_6, _activated_wdata_e_act_raw_out_isNaN_T_12)
connect activated_wdata_e_act_raw_6.isNaN, _activated_wdata_e_act_raw_out_isNaN_T_13
node _activated_wdata_e_act_raw_out_isInf_T_6 = and(activated_wdata_e_act_raw_isSpecial_6, activated_wdata_e_act_raw_isZeroFractIn_6)
connect activated_wdata_e_act_raw_6.isInf, _activated_wdata_e_act_raw_out_isInf_T_6
connect activated_wdata_e_act_raw_6.isZero, activated_wdata_e_act_raw_isZero_6
connect activated_wdata_e_act_raw_6.sign, activated_wdata_e_act_raw_sign_6
node _activated_wdata_e_act_raw_out_sExp_T_12 = bits(activated_wdata_e_act_raw_adjustedExp_6, 8, 0)
node _activated_wdata_e_act_raw_out_sExp_T_13 = cvt(_activated_wdata_e_act_raw_out_sExp_T_12)
connect activated_wdata_e_act_raw_6.sExp, _activated_wdata_e_act_raw_out_sExp_T_13
node _activated_wdata_e_act_raw_out_sig_T_24 = eq(activated_wdata_e_act_raw_isZero_6, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_sig_T_25 = cat(UInt<1>(0h0), _activated_wdata_e_act_raw_out_sig_T_24)
node _activated_wdata_e_act_raw_out_sig_T_26 = mux(activated_wdata_e_act_raw_isZeroExpIn_6, activated_wdata_e_act_raw_subnormFract_6, activated_wdata_e_act_raw_fractIn_6)
node _activated_wdata_e_act_raw_out_sig_T_27 = cat(_activated_wdata_e_act_raw_out_sig_T_25, _activated_wdata_e_act_raw_out_sig_T_26)
connect activated_wdata_e_act_raw_6.sig, _activated_wdata_e_act_raw_out_sig_T_27
wire activated_wdata_e_act_result_6 : { bits : UInt<32>}
node _activated_wdata_e_act_result_bits_T_18 = eq(activated_wdata_e_act_raw_6.isZero, UInt<1>(0h0))
node _activated_wdata_e_act_result_bits_T_19 = and(_activated_wdata_e_act_result_bits_T_18, activated_wdata_e_act_raw_6.sign)
node _activated_wdata_e_act_result_bits_T_20 = mux(_activated_wdata_e_act_result_bits_T_19, UInt<1>(0h0), activated_wdata_e_clipped_6.bits)
connect activated_wdata_e_act_result_6.bits, _activated_wdata_e_act_result_bits_T_20
node activated_wdata_e_act_6 = mux(_activated_wdata_e_act_T_6, activated_wdata_e_act_result_6, activated_wdata_e_clipped_6)
wire _activated_wdata_WIRE_6 : { bits : UInt<32>}[1]
connect _activated_wdata_WIRE_6[0], activated_wdata_e_act_6
node activated_wdata_e_clipped_self_rec_rawIn_sign_7 = bits(mesh.io.resp.bits.data[3][0].bits, 31, 31)
node activated_wdata_e_clipped_self_rec_rawIn_expIn_7 = bits(mesh.io.resp.bits.data[3][0].bits, 30, 23)
node activated_wdata_e_clipped_self_rec_rawIn_fractIn_7 = bits(mesh.io.resp.bits.data[3][0].bits, 22, 0)
node activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_7 = eq(activated_wdata_e_clipped_self_rec_rawIn_expIn_7, UInt<1>(0h0))
node activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_7 = eq(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_308 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 0, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_309 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 1, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_310 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 2, 2)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_311 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 3, 3)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_312 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 4, 4)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_313 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 5, 5)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_314 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 6, 6)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_315 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 7, 7)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_316 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 8, 8)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_317 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 9, 9)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_318 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 10, 10)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_319 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 11, 11)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_320 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 12, 12)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_321 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 13, 13)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_322 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 14, 14)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_323 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 15, 15)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_324 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 16, 16)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_325 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 17, 17)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_326 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 18, 18)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_327 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 19, 19)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_328 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 20, 20)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_329 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 21, 21)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_330 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, 22, 22)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_331 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_309, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_332 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_310, UInt<5>(0h14), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_331)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_333 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_311, UInt<5>(0h13), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_332)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_334 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_312, UInt<5>(0h12), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_333)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_335 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_313, UInt<5>(0h11), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_334)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_336 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_314, UInt<5>(0h10), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_335)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_337 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_315, UInt<4>(0hf), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_336)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_338 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_316, UInt<4>(0he), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_337)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_339 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_317, UInt<4>(0hd), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_338)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_340 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_318, UInt<4>(0hc), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_339)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_341 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_319, UInt<4>(0hb), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_340)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_342 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_320, UInt<4>(0ha), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_341)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_343 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_321, UInt<4>(0h9), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_342)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_344 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_322, UInt<4>(0h8), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_343)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_345 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_323, UInt<3>(0h7), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_344)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_346 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_324, UInt<3>(0h6), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_345)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_347 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_325, UInt<3>(0h5), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_346)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_348 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_326, UInt<3>(0h4), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_347)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_349 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_327, UInt<2>(0h3), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_348)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_350 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_328, UInt<2>(0h2), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_349)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_351 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_329, UInt<1>(0h1), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_350)
node activated_wdata_e_clipped_self_rec_rawIn_normDist_7 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_330, UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_351)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_14 = dshl(activated_wdata_e_clipped_self_rec_rawIn_fractIn_7, activated_wdata_e_clipped_self_rec_rawIn_normDist_7)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_15 = bits(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_14, 21, 0)
node activated_wdata_e_clipped_self_rec_rawIn_subnormFract_7 = shl(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_15, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_35 = xor(activated_wdata_e_clipped_self_rec_rawIn_normDist_7, UInt<9>(0h1ff))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_36 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_7, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_35, activated_wdata_e_clipped_self_rec_rawIn_expIn_7)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_37 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_7, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_38 = or(UInt<8>(0h80), _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_37)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_39 = add(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_36, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_38)
node activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_7 = tail(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_39, 1)
node activated_wdata_e_clipped_self_rec_rawIn_isZero_7 = and(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_7, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_7)
node _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_7 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_7, 8, 7)
node activated_wdata_e_clipped_self_rec_rawIn_isSpecial_7 = eq(_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_7, UInt<2>(0h3))
wire activated_wdata_e_clipped_self_rec_rawIn_7 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_14 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_7, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_15 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_7, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_14)
connect activated_wdata_e_clipped_self_rec_rawIn_7.isNaN, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_15
node _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_7 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_7, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_7)
connect activated_wdata_e_clipped_self_rec_rawIn_7.isInf, _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_7
connect activated_wdata_e_clipped_self_rec_rawIn_7.isZero, activated_wdata_e_clipped_self_rec_rawIn_isZero_7
connect activated_wdata_e_clipped_self_rec_rawIn_7.sign, activated_wdata_e_clipped_self_rec_rawIn_sign_7
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_14 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_7, 8, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_15 = cvt(_activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_14)
connect activated_wdata_e_clipped_self_rec_rawIn_7.sExp, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_15
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_28 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZero_7, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_29 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_28)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_30 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_7, activated_wdata_e_clipped_self_rec_rawIn_subnormFract_7, activated_wdata_e_clipped_self_rec_rawIn_fractIn_7)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_31 = cat(_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_29, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_30)
connect activated_wdata_e_clipped_self_rec_rawIn_7.sig, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_31
node _activated_wdata_e_clipped_self_rec_T_56 = bits(activated_wdata_e_clipped_self_rec_rawIn_7.sExp, 8, 6)
node _activated_wdata_e_clipped_self_rec_T_57 = mux(activated_wdata_e_clipped_self_rec_rawIn_7.isZero, UInt<3>(0h0), _activated_wdata_e_clipped_self_rec_T_56)
node _activated_wdata_e_clipped_self_rec_T_58 = mux(activated_wdata_e_clipped_self_rec_rawIn_7.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_T_59 = or(_activated_wdata_e_clipped_self_rec_T_57, _activated_wdata_e_clipped_self_rec_T_58)
node _activated_wdata_e_clipped_self_rec_T_60 = cat(activated_wdata_e_clipped_self_rec_rawIn_7.sign, _activated_wdata_e_clipped_self_rec_T_59)
node _activated_wdata_e_clipped_self_rec_T_61 = bits(activated_wdata_e_clipped_self_rec_rawIn_7.sExp, 5, 0)
node _activated_wdata_e_clipped_self_rec_T_62 = cat(_activated_wdata_e_clipped_self_rec_T_60, _activated_wdata_e_clipped_self_rec_T_61)
node _activated_wdata_e_clipped_self_rec_T_63 = bits(activated_wdata_e_clipped_self_rec_rawIn_7.sig, 22, 0)
node activated_wdata_e_clipped_self_rec_7 = cat(_activated_wdata_e_clipped_self_rec_T_62, _activated_wdata_e_clipped_self_rec_T_63)
inst activated_wdata_e_clipped_resizer_7 of RecFNToRecFN_247
connect activated_wdata_e_clipped_resizer_7.io.in, activated_wdata_e_clipped_self_rec_7
connect activated_wdata_e_clipped_resizer_7.io.roundingMode, UInt<3>(0h0)
connect activated_wdata_e_clipped_resizer_7.io.detectTininess, UInt<1>(0h1)
wire activated_wdata_e_clipped_7 : { bits : UInt<32>}
node activated_wdata_e_clipped_result_bits_rawIn_exp_7 = bits(activated_wdata_e_clipped_resizer_7.io.out, 31, 23)
node _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_7 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_7, 8, 6)
node activated_wdata_e_clipped_result_bits_rawIn_isZero_7 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isZero_T_7, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_7 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_7, 8, 7)
node activated_wdata_e_clipped_result_bits_rawIn_isSpecial_7 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_7, UInt<2>(0h3))
wire activated_wdata_e_clipped_result_bits_rawIn_7 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_14 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_7, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_15 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_7, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_14)
connect activated_wdata_e_clipped_result_bits_rawIn_7.isNaN, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_15
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_21 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_7, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_22 = eq(_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_21, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_23 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_7, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_22)
connect activated_wdata_e_clipped_result_bits_rawIn_7.isInf, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_23
connect activated_wdata_e_clipped_result_bits_rawIn_7.isZero, activated_wdata_e_clipped_result_bits_rawIn_isZero_7
node _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_7 = bits(activated_wdata_e_clipped_resizer_7.io.out, 32, 32)
connect activated_wdata_e_clipped_result_bits_rawIn_7.sign, _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_7
node _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_7 = cvt(activated_wdata_e_clipped_result_bits_rawIn_exp_7)
connect activated_wdata_e_clipped_result_bits_rawIn_7.sExp, _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_7
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_28 = eq(activated_wdata_e_clipped_result_bits_rawIn_isZero_7, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_29 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_28)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_30 = bits(activated_wdata_e_clipped_resizer_7.io.out, 22, 0)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_31 = cat(_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_29, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_30)
connect activated_wdata_e_clipped_result_bits_rawIn_7.sig, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_31
node activated_wdata_e_clipped_result_bits_isSubnormal_7 = lt(activated_wdata_e_clipped_result_bits_rawIn_7.sExp, asSInt(UInt<9>(0h82)))
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_14 = bits(activated_wdata_e_clipped_result_bits_rawIn_7.sExp, 4, 0)
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_15 = sub(UInt<1>(0h1), _activated_wdata_e_clipped_result_bits_denormShiftDist_T_14)
node activated_wdata_e_clipped_result_bits_denormShiftDist_7 = tail(_activated_wdata_e_clipped_result_bits_denormShiftDist_T_15, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_14 = shr(activated_wdata_e_clipped_result_bits_rawIn_7.sig, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_15 = dshr(_activated_wdata_e_clipped_result_bits_denormFract_T_14, activated_wdata_e_clipped_result_bits_denormShiftDist_7)
node activated_wdata_e_clipped_result_bits_denormFract_7 = bits(_activated_wdata_e_clipped_result_bits_denormFract_T_15, 22, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_42 = bits(activated_wdata_e_clipped_result_bits_rawIn_7.sExp, 7, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_43 = sub(_activated_wdata_e_clipped_result_bits_expOut_T_42, UInt<8>(0h81))
node _activated_wdata_e_clipped_result_bits_expOut_T_44 = tail(_activated_wdata_e_clipped_result_bits_expOut_T_43, 1)
node _activated_wdata_e_clipped_result_bits_expOut_T_45 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_7, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_expOut_T_44)
node _activated_wdata_e_clipped_result_bits_expOut_T_46 = or(activated_wdata_e_clipped_result_bits_rawIn_7.isNaN, activated_wdata_e_clipped_result_bits_rawIn_7.isInf)
node _activated_wdata_e_clipped_result_bits_expOut_T_47 = mux(_activated_wdata_e_clipped_result_bits_expOut_T_46, UInt<8>(0hff), UInt<8>(0h0))
node activated_wdata_e_clipped_result_bits_expOut_7 = or(_activated_wdata_e_clipped_result_bits_expOut_T_45, _activated_wdata_e_clipped_result_bits_expOut_T_47)
node _activated_wdata_e_clipped_result_bits_fractOut_T_14 = bits(activated_wdata_e_clipped_result_bits_rawIn_7.sig, 22, 0)
node _activated_wdata_e_clipped_result_bits_fractOut_T_15 = mux(activated_wdata_e_clipped_result_bits_rawIn_7.isInf, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_fractOut_T_14)
node activated_wdata_e_clipped_result_bits_fractOut_7 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_7, activated_wdata_e_clipped_result_bits_denormFract_7, _activated_wdata_e_clipped_result_bits_fractOut_T_15)
node activated_wdata_e_clipped_result_bits_hi_7 = cat(activated_wdata_e_clipped_result_bits_rawIn_7.sign, activated_wdata_e_clipped_result_bits_expOut_7)
node _activated_wdata_e_clipped_result_bits_T_7 = cat(activated_wdata_e_clipped_result_bits_hi_7, activated_wdata_e_clipped_result_bits_fractOut_7)
connect activated_wdata_e_clipped_7.bits, _activated_wdata_e_clipped_result_bits_T_7
node _activated_wdata_e_act_T_7 = eq(activation, UInt<1>(0h1))
node activated_wdata_e_act_raw_sign_7 = bits(activated_wdata_e_clipped_7.bits, 31, 31)
node activated_wdata_e_act_raw_expIn_7 = bits(activated_wdata_e_clipped_7.bits, 30, 23)
node activated_wdata_e_act_raw_fractIn_7 = bits(activated_wdata_e_clipped_7.bits, 22, 0)
node activated_wdata_e_act_raw_isZeroExpIn_7 = eq(activated_wdata_e_act_raw_expIn_7, UInt<1>(0h0))
node activated_wdata_e_act_raw_isZeroFractIn_7 = eq(activated_wdata_e_act_raw_fractIn_7, UInt<1>(0h0))
node _activated_wdata_e_act_raw_normDist_T_308 = bits(activated_wdata_e_act_raw_fractIn_7, 0, 0)
node _activated_wdata_e_act_raw_normDist_T_309 = bits(activated_wdata_e_act_raw_fractIn_7, 1, 1)
node _activated_wdata_e_act_raw_normDist_T_310 = bits(activated_wdata_e_act_raw_fractIn_7, 2, 2)
node _activated_wdata_e_act_raw_normDist_T_311 = bits(activated_wdata_e_act_raw_fractIn_7, 3, 3)
node _activated_wdata_e_act_raw_normDist_T_312 = bits(activated_wdata_e_act_raw_fractIn_7, 4, 4)
node _activated_wdata_e_act_raw_normDist_T_313 = bits(activated_wdata_e_act_raw_fractIn_7, 5, 5)
node _activated_wdata_e_act_raw_normDist_T_314 = bits(activated_wdata_e_act_raw_fractIn_7, 6, 6)
node _activated_wdata_e_act_raw_normDist_T_315 = bits(activated_wdata_e_act_raw_fractIn_7, 7, 7)
node _activated_wdata_e_act_raw_normDist_T_316 = bits(activated_wdata_e_act_raw_fractIn_7, 8, 8)
node _activated_wdata_e_act_raw_normDist_T_317 = bits(activated_wdata_e_act_raw_fractIn_7, 9, 9)
node _activated_wdata_e_act_raw_normDist_T_318 = bits(activated_wdata_e_act_raw_fractIn_7, 10, 10)
node _activated_wdata_e_act_raw_normDist_T_319 = bits(activated_wdata_e_act_raw_fractIn_7, 11, 11)
node _activated_wdata_e_act_raw_normDist_T_320 = bits(activated_wdata_e_act_raw_fractIn_7, 12, 12)
node _activated_wdata_e_act_raw_normDist_T_321 = bits(activated_wdata_e_act_raw_fractIn_7, 13, 13)
node _activated_wdata_e_act_raw_normDist_T_322 = bits(activated_wdata_e_act_raw_fractIn_7, 14, 14)
node _activated_wdata_e_act_raw_normDist_T_323 = bits(activated_wdata_e_act_raw_fractIn_7, 15, 15)
node _activated_wdata_e_act_raw_normDist_T_324 = bits(activated_wdata_e_act_raw_fractIn_7, 16, 16)
node _activated_wdata_e_act_raw_normDist_T_325 = bits(activated_wdata_e_act_raw_fractIn_7, 17, 17)
node _activated_wdata_e_act_raw_normDist_T_326 = bits(activated_wdata_e_act_raw_fractIn_7, 18, 18)
node _activated_wdata_e_act_raw_normDist_T_327 = bits(activated_wdata_e_act_raw_fractIn_7, 19, 19)
node _activated_wdata_e_act_raw_normDist_T_328 = bits(activated_wdata_e_act_raw_fractIn_7, 20, 20)
node _activated_wdata_e_act_raw_normDist_T_329 = bits(activated_wdata_e_act_raw_fractIn_7, 21, 21)
node _activated_wdata_e_act_raw_normDist_T_330 = bits(activated_wdata_e_act_raw_fractIn_7, 22, 22)
node _activated_wdata_e_act_raw_normDist_T_331 = mux(_activated_wdata_e_act_raw_normDist_T_309, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_act_raw_normDist_T_332 = mux(_activated_wdata_e_act_raw_normDist_T_310, UInt<5>(0h14), _activated_wdata_e_act_raw_normDist_T_331)
node _activated_wdata_e_act_raw_normDist_T_333 = mux(_activated_wdata_e_act_raw_normDist_T_311, UInt<5>(0h13), _activated_wdata_e_act_raw_normDist_T_332)
node _activated_wdata_e_act_raw_normDist_T_334 = mux(_activated_wdata_e_act_raw_normDist_T_312, UInt<5>(0h12), _activated_wdata_e_act_raw_normDist_T_333)
node _activated_wdata_e_act_raw_normDist_T_335 = mux(_activated_wdata_e_act_raw_normDist_T_313, UInt<5>(0h11), _activated_wdata_e_act_raw_normDist_T_334)
node _activated_wdata_e_act_raw_normDist_T_336 = mux(_activated_wdata_e_act_raw_normDist_T_314, UInt<5>(0h10), _activated_wdata_e_act_raw_normDist_T_335)
node _activated_wdata_e_act_raw_normDist_T_337 = mux(_activated_wdata_e_act_raw_normDist_T_315, UInt<4>(0hf), _activated_wdata_e_act_raw_normDist_T_336)
node _activated_wdata_e_act_raw_normDist_T_338 = mux(_activated_wdata_e_act_raw_normDist_T_316, UInt<4>(0he), _activated_wdata_e_act_raw_normDist_T_337)
node _activated_wdata_e_act_raw_normDist_T_339 = mux(_activated_wdata_e_act_raw_normDist_T_317, UInt<4>(0hd), _activated_wdata_e_act_raw_normDist_T_338)
node _activated_wdata_e_act_raw_normDist_T_340 = mux(_activated_wdata_e_act_raw_normDist_T_318, UInt<4>(0hc), _activated_wdata_e_act_raw_normDist_T_339)
node _activated_wdata_e_act_raw_normDist_T_341 = mux(_activated_wdata_e_act_raw_normDist_T_319, UInt<4>(0hb), _activated_wdata_e_act_raw_normDist_T_340)
node _activated_wdata_e_act_raw_normDist_T_342 = mux(_activated_wdata_e_act_raw_normDist_T_320, UInt<4>(0ha), _activated_wdata_e_act_raw_normDist_T_341)
node _activated_wdata_e_act_raw_normDist_T_343 = mux(_activated_wdata_e_act_raw_normDist_T_321, UInt<4>(0h9), _activated_wdata_e_act_raw_normDist_T_342)
node _activated_wdata_e_act_raw_normDist_T_344 = mux(_activated_wdata_e_act_raw_normDist_T_322, UInt<4>(0h8), _activated_wdata_e_act_raw_normDist_T_343)
node _activated_wdata_e_act_raw_normDist_T_345 = mux(_activated_wdata_e_act_raw_normDist_T_323, UInt<3>(0h7), _activated_wdata_e_act_raw_normDist_T_344)
node _activated_wdata_e_act_raw_normDist_T_346 = mux(_activated_wdata_e_act_raw_normDist_T_324, UInt<3>(0h6), _activated_wdata_e_act_raw_normDist_T_345)
node _activated_wdata_e_act_raw_normDist_T_347 = mux(_activated_wdata_e_act_raw_normDist_T_325, UInt<3>(0h5), _activated_wdata_e_act_raw_normDist_T_346)
node _activated_wdata_e_act_raw_normDist_T_348 = mux(_activated_wdata_e_act_raw_normDist_T_326, UInt<3>(0h4), _activated_wdata_e_act_raw_normDist_T_347)
node _activated_wdata_e_act_raw_normDist_T_349 = mux(_activated_wdata_e_act_raw_normDist_T_327, UInt<2>(0h3), _activated_wdata_e_act_raw_normDist_T_348)
node _activated_wdata_e_act_raw_normDist_T_350 = mux(_activated_wdata_e_act_raw_normDist_T_328, UInt<2>(0h2), _activated_wdata_e_act_raw_normDist_T_349)
node _activated_wdata_e_act_raw_normDist_T_351 = mux(_activated_wdata_e_act_raw_normDist_T_329, UInt<1>(0h1), _activated_wdata_e_act_raw_normDist_T_350)
node activated_wdata_e_act_raw_normDist_7 = mux(_activated_wdata_e_act_raw_normDist_T_330, UInt<1>(0h0), _activated_wdata_e_act_raw_normDist_T_351)
node _activated_wdata_e_act_raw_subnormFract_T_14 = dshl(activated_wdata_e_act_raw_fractIn_7, activated_wdata_e_act_raw_normDist_7)
node _activated_wdata_e_act_raw_subnormFract_T_15 = bits(_activated_wdata_e_act_raw_subnormFract_T_14, 21, 0)
node activated_wdata_e_act_raw_subnormFract_7 = shl(_activated_wdata_e_act_raw_subnormFract_T_15, 1)
node _activated_wdata_e_act_raw_adjustedExp_T_35 = xor(activated_wdata_e_act_raw_normDist_7, UInt<9>(0h1ff))
node _activated_wdata_e_act_raw_adjustedExp_T_36 = mux(activated_wdata_e_act_raw_isZeroExpIn_7, _activated_wdata_e_act_raw_adjustedExp_T_35, activated_wdata_e_act_raw_expIn_7)
node _activated_wdata_e_act_raw_adjustedExp_T_37 = mux(activated_wdata_e_act_raw_isZeroExpIn_7, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_act_raw_adjustedExp_T_38 = or(UInt<8>(0h80), _activated_wdata_e_act_raw_adjustedExp_T_37)
node _activated_wdata_e_act_raw_adjustedExp_T_39 = add(_activated_wdata_e_act_raw_adjustedExp_T_36, _activated_wdata_e_act_raw_adjustedExp_T_38)
node activated_wdata_e_act_raw_adjustedExp_7 = tail(_activated_wdata_e_act_raw_adjustedExp_T_39, 1)
node activated_wdata_e_act_raw_isZero_7 = and(activated_wdata_e_act_raw_isZeroExpIn_7, activated_wdata_e_act_raw_isZeroFractIn_7)
node _activated_wdata_e_act_raw_isSpecial_T_7 = bits(activated_wdata_e_act_raw_adjustedExp_7, 8, 7)
node activated_wdata_e_act_raw_isSpecial_7 = eq(_activated_wdata_e_act_raw_isSpecial_T_7, UInt<2>(0h3))
wire activated_wdata_e_act_raw_7 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_act_raw_out_isNaN_T_14 = eq(activated_wdata_e_act_raw_isZeroFractIn_7, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_isNaN_T_15 = and(activated_wdata_e_act_raw_isSpecial_7, _activated_wdata_e_act_raw_out_isNaN_T_14)
connect activated_wdata_e_act_raw_7.isNaN, _activated_wdata_e_act_raw_out_isNaN_T_15
node _activated_wdata_e_act_raw_out_isInf_T_7 = and(activated_wdata_e_act_raw_isSpecial_7, activated_wdata_e_act_raw_isZeroFractIn_7)
connect activated_wdata_e_act_raw_7.isInf, _activated_wdata_e_act_raw_out_isInf_T_7
connect activated_wdata_e_act_raw_7.isZero, activated_wdata_e_act_raw_isZero_7
connect activated_wdata_e_act_raw_7.sign, activated_wdata_e_act_raw_sign_7
node _activated_wdata_e_act_raw_out_sExp_T_14 = bits(activated_wdata_e_act_raw_adjustedExp_7, 8, 0)
node _activated_wdata_e_act_raw_out_sExp_T_15 = cvt(_activated_wdata_e_act_raw_out_sExp_T_14)
connect activated_wdata_e_act_raw_7.sExp, _activated_wdata_e_act_raw_out_sExp_T_15
node _activated_wdata_e_act_raw_out_sig_T_28 = eq(activated_wdata_e_act_raw_isZero_7, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_sig_T_29 = cat(UInt<1>(0h0), _activated_wdata_e_act_raw_out_sig_T_28)
node _activated_wdata_e_act_raw_out_sig_T_30 = mux(activated_wdata_e_act_raw_isZeroExpIn_7, activated_wdata_e_act_raw_subnormFract_7, activated_wdata_e_act_raw_fractIn_7)
node _activated_wdata_e_act_raw_out_sig_T_31 = cat(_activated_wdata_e_act_raw_out_sig_T_29, _activated_wdata_e_act_raw_out_sig_T_30)
connect activated_wdata_e_act_raw_7.sig, _activated_wdata_e_act_raw_out_sig_T_31
wire activated_wdata_e_act_result_7 : { bits : UInt<32>}
node _activated_wdata_e_act_result_bits_T_21 = eq(activated_wdata_e_act_raw_7.isZero, UInt<1>(0h0))
node _activated_wdata_e_act_result_bits_T_22 = and(_activated_wdata_e_act_result_bits_T_21, activated_wdata_e_act_raw_7.sign)
node _activated_wdata_e_act_result_bits_T_23 = mux(_activated_wdata_e_act_result_bits_T_22, UInt<1>(0h0), activated_wdata_e_clipped_7.bits)
connect activated_wdata_e_act_result_7.bits, _activated_wdata_e_act_result_bits_T_23
node activated_wdata_e_act_7 = mux(_activated_wdata_e_act_T_7, activated_wdata_e_act_result_7, activated_wdata_e_clipped_7)
wire _activated_wdata_WIRE_7 : { bits : UInt<32>}[1]
connect _activated_wdata_WIRE_7[0], activated_wdata_e_act_7
wire activated_wdata_1 : { bits : UInt<32>}[1][4]
connect activated_wdata_1[0], _activated_wdata_WIRE_4
connect activated_wdata_1[1], _activated_wdata_WIRE_5
connect activated_wdata_1[2], _activated_wdata_WIRE_6
connect activated_wdata_1[3], _activated_wdata_WIRE_7
node _io_srams_write_1_en_T = eq(w_bank, UInt<1>(0h1))
node _io_srams_write_1_en_T_1 = and(start_array_outputting, _io_srams_write_1_en_T)
node _io_srams_write_1_en_T_2 = eq(w_address.is_acc_addr, UInt<1>(0h0))
node _io_srams_write_1_en_T_3 = and(_io_srams_write_1_en_T_1, _io_srams_write_1_en_T_2)
node _io_srams_write_1_en_T_4 = eq(is_garbage_addr, UInt<1>(0h0))
node _io_srams_write_1_en_T_5 = and(_io_srams_write_1_en_T_3, _io_srams_write_1_en_T_4)
node _io_srams_write_1_en_T_6 = and(_io_srams_write_1_en_T_5, write_this_row)
connect io.srams.write[1].en, _io_srams_write_1_en_T_6
connect io.srams.write[1].addr, w_row
node io_srams_write_1_data_lo = cat(activated_wdata_1[1][0].bits, activated_wdata_1[0][0].bits)
node io_srams_write_1_data_hi = cat(activated_wdata_1[3][0].bits, activated_wdata_1[2][0].bits)
node _io_srams_write_1_data_T = cat(io_srams_write_1_data_hi, io_srams_write_1_data_lo)
connect io.srams.write[1].data, _io_srams_write_1_data_T
connect io.srams.write[1].mask[0], w_mask_0
connect io.srams.write[1].mask[1], w_mask_0
connect io.srams.write[1].mask[2], w_mask_0
connect io.srams.write[1].mask[3], w_mask_0
connect io.srams.write[1].mask[4], w_mask_1
connect io.srams.write[1].mask[5], w_mask_1
connect io.srams.write[1].mask[6], w_mask_1
connect io.srams.write[1].mask[7], w_mask_1
connect io.srams.write[1].mask[8], w_mask_2
connect io.srams.write[1].mask[9], w_mask_2
connect io.srams.write[1].mask[10], w_mask_2
connect io.srams.write[1].mask[11], w_mask_2
connect io.srams.write[1].mask[12], w_mask_3
connect io.srams.write[1].mask[13], w_mask_3
connect io.srams.write[1].mask[14], w_mask_3
connect io.srams.write[1].mask[15], w_mask_3
node activated_wdata_e_clipped_self_rec_rawIn_sign_8 = bits(mesh.io.resp.bits.data[0][0].bits, 31, 31)
node activated_wdata_e_clipped_self_rec_rawIn_expIn_8 = bits(mesh.io.resp.bits.data[0][0].bits, 30, 23)
node activated_wdata_e_clipped_self_rec_rawIn_fractIn_8 = bits(mesh.io.resp.bits.data[0][0].bits, 22, 0)
node activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_8 = eq(activated_wdata_e_clipped_self_rec_rawIn_expIn_8, UInt<1>(0h0))
node activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_8 = eq(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_352 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 0, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_353 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 1, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_354 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 2, 2)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_355 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 3, 3)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_356 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 4, 4)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_357 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 5, 5)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_358 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 6, 6)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_359 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 7, 7)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_360 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 8, 8)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_361 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 9, 9)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_362 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 10, 10)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_363 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 11, 11)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_364 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 12, 12)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_365 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 13, 13)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_366 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 14, 14)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_367 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 15, 15)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_368 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 16, 16)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_369 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 17, 17)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_370 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 18, 18)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_371 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 19, 19)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_372 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 20, 20)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_373 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 21, 21)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_374 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, 22, 22)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_375 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_353, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_376 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_354, UInt<5>(0h14), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_375)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_377 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_355, UInt<5>(0h13), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_376)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_378 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_356, UInt<5>(0h12), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_377)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_379 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_357, UInt<5>(0h11), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_378)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_380 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_358, UInt<5>(0h10), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_379)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_381 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_359, UInt<4>(0hf), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_380)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_382 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_360, UInt<4>(0he), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_381)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_383 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_361, UInt<4>(0hd), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_382)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_384 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_362, UInt<4>(0hc), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_383)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_385 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_363, UInt<4>(0hb), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_384)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_386 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_364, UInt<4>(0ha), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_385)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_387 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_365, UInt<4>(0h9), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_386)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_388 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_366, UInt<4>(0h8), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_387)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_389 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_367, UInt<3>(0h7), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_388)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_390 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_368, UInt<3>(0h6), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_389)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_391 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_369, UInt<3>(0h5), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_390)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_392 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_370, UInt<3>(0h4), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_391)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_393 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_371, UInt<2>(0h3), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_392)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_394 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_372, UInt<2>(0h2), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_393)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_395 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_373, UInt<1>(0h1), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_394)
node activated_wdata_e_clipped_self_rec_rawIn_normDist_8 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_374, UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_395)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_16 = dshl(activated_wdata_e_clipped_self_rec_rawIn_fractIn_8, activated_wdata_e_clipped_self_rec_rawIn_normDist_8)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_17 = bits(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_16, 21, 0)
node activated_wdata_e_clipped_self_rec_rawIn_subnormFract_8 = shl(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_17, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_40 = xor(activated_wdata_e_clipped_self_rec_rawIn_normDist_8, UInt<9>(0h1ff))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_41 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_8, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_40, activated_wdata_e_clipped_self_rec_rawIn_expIn_8)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_42 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_8, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_43 = or(UInt<8>(0h80), _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_42)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_44 = add(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_41, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_43)
node activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_8 = tail(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_44, 1)
node activated_wdata_e_clipped_self_rec_rawIn_isZero_8 = and(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_8, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_8)
node _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_8 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_8, 8, 7)
node activated_wdata_e_clipped_self_rec_rawIn_isSpecial_8 = eq(_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_8, UInt<2>(0h3))
wire activated_wdata_e_clipped_self_rec_rawIn_8 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_16 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_8, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_17 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_8, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_16)
connect activated_wdata_e_clipped_self_rec_rawIn_8.isNaN, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_17
node _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_8 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_8, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_8)
connect activated_wdata_e_clipped_self_rec_rawIn_8.isInf, _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_8
connect activated_wdata_e_clipped_self_rec_rawIn_8.isZero, activated_wdata_e_clipped_self_rec_rawIn_isZero_8
connect activated_wdata_e_clipped_self_rec_rawIn_8.sign, activated_wdata_e_clipped_self_rec_rawIn_sign_8
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_16 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_8, 8, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_17 = cvt(_activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_16)
connect activated_wdata_e_clipped_self_rec_rawIn_8.sExp, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_17
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_32 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZero_8, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_33 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_32)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_34 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_8, activated_wdata_e_clipped_self_rec_rawIn_subnormFract_8, activated_wdata_e_clipped_self_rec_rawIn_fractIn_8)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_35 = cat(_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_33, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_34)
connect activated_wdata_e_clipped_self_rec_rawIn_8.sig, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_35
node _activated_wdata_e_clipped_self_rec_T_64 = bits(activated_wdata_e_clipped_self_rec_rawIn_8.sExp, 8, 6)
node _activated_wdata_e_clipped_self_rec_T_65 = mux(activated_wdata_e_clipped_self_rec_rawIn_8.isZero, UInt<3>(0h0), _activated_wdata_e_clipped_self_rec_T_64)
node _activated_wdata_e_clipped_self_rec_T_66 = mux(activated_wdata_e_clipped_self_rec_rawIn_8.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_T_67 = or(_activated_wdata_e_clipped_self_rec_T_65, _activated_wdata_e_clipped_self_rec_T_66)
node _activated_wdata_e_clipped_self_rec_T_68 = cat(activated_wdata_e_clipped_self_rec_rawIn_8.sign, _activated_wdata_e_clipped_self_rec_T_67)
node _activated_wdata_e_clipped_self_rec_T_69 = bits(activated_wdata_e_clipped_self_rec_rawIn_8.sExp, 5, 0)
node _activated_wdata_e_clipped_self_rec_T_70 = cat(_activated_wdata_e_clipped_self_rec_T_68, _activated_wdata_e_clipped_self_rec_T_69)
node _activated_wdata_e_clipped_self_rec_T_71 = bits(activated_wdata_e_clipped_self_rec_rawIn_8.sig, 22, 0)
node activated_wdata_e_clipped_self_rec_8 = cat(_activated_wdata_e_clipped_self_rec_T_70, _activated_wdata_e_clipped_self_rec_T_71)
inst activated_wdata_e_clipped_resizer_8 of RecFNToRecFN_248
connect activated_wdata_e_clipped_resizer_8.io.in, activated_wdata_e_clipped_self_rec_8
connect activated_wdata_e_clipped_resizer_8.io.roundingMode, UInt<3>(0h0)
connect activated_wdata_e_clipped_resizer_8.io.detectTininess, UInt<1>(0h1)
wire activated_wdata_e_clipped_8 : { bits : UInt<32>}
node activated_wdata_e_clipped_result_bits_rawIn_exp_8 = bits(activated_wdata_e_clipped_resizer_8.io.out, 31, 23)
node _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_8 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_8, 8, 6)
node activated_wdata_e_clipped_result_bits_rawIn_isZero_8 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isZero_T_8, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_8 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_8, 8, 7)
node activated_wdata_e_clipped_result_bits_rawIn_isSpecial_8 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_8, UInt<2>(0h3))
wire activated_wdata_e_clipped_result_bits_rawIn_8 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_16 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_8, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_17 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_8, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_16)
connect activated_wdata_e_clipped_result_bits_rawIn_8.isNaN, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_17
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_24 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_8, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_25 = eq(_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_24, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_26 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_8, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_25)
connect activated_wdata_e_clipped_result_bits_rawIn_8.isInf, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_26
connect activated_wdata_e_clipped_result_bits_rawIn_8.isZero, activated_wdata_e_clipped_result_bits_rawIn_isZero_8
node _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_8 = bits(activated_wdata_e_clipped_resizer_8.io.out, 32, 32)
connect activated_wdata_e_clipped_result_bits_rawIn_8.sign, _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_8
node _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_8 = cvt(activated_wdata_e_clipped_result_bits_rawIn_exp_8)
connect activated_wdata_e_clipped_result_bits_rawIn_8.sExp, _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_8
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_32 = eq(activated_wdata_e_clipped_result_bits_rawIn_isZero_8, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_33 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_32)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_34 = bits(activated_wdata_e_clipped_resizer_8.io.out, 22, 0)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_35 = cat(_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_33, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_34)
connect activated_wdata_e_clipped_result_bits_rawIn_8.sig, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_35
node activated_wdata_e_clipped_result_bits_isSubnormal_8 = lt(activated_wdata_e_clipped_result_bits_rawIn_8.sExp, asSInt(UInt<9>(0h82)))
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_16 = bits(activated_wdata_e_clipped_result_bits_rawIn_8.sExp, 4, 0)
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_17 = sub(UInt<1>(0h1), _activated_wdata_e_clipped_result_bits_denormShiftDist_T_16)
node activated_wdata_e_clipped_result_bits_denormShiftDist_8 = tail(_activated_wdata_e_clipped_result_bits_denormShiftDist_T_17, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_16 = shr(activated_wdata_e_clipped_result_bits_rawIn_8.sig, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_17 = dshr(_activated_wdata_e_clipped_result_bits_denormFract_T_16, activated_wdata_e_clipped_result_bits_denormShiftDist_8)
node activated_wdata_e_clipped_result_bits_denormFract_8 = bits(_activated_wdata_e_clipped_result_bits_denormFract_T_17, 22, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_48 = bits(activated_wdata_e_clipped_result_bits_rawIn_8.sExp, 7, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_49 = sub(_activated_wdata_e_clipped_result_bits_expOut_T_48, UInt<8>(0h81))
node _activated_wdata_e_clipped_result_bits_expOut_T_50 = tail(_activated_wdata_e_clipped_result_bits_expOut_T_49, 1)
node _activated_wdata_e_clipped_result_bits_expOut_T_51 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_8, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_expOut_T_50)
node _activated_wdata_e_clipped_result_bits_expOut_T_52 = or(activated_wdata_e_clipped_result_bits_rawIn_8.isNaN, activated_wdata_e_clipped_result_bits_rawIn_8.isInf)
node _activated_wdata_e_clipped_result_bits_expOut_T_53 = mux(_activated_wdata_e_clipped_result_bits_expOut_T_52, UInt<8>(0hff), UInt<8>(0h0))
node activated_wdata_e_clipped_result_bits_expOut_8 = or(_activated_wdata_e_clipped_result_bits_expOut_T_51, _activated_wdata_e_clipped_result_bits_expOut_T_53)
node _activated_wdata_e_clipped_result_bits_fractOut_T_16 = bits(activated_wdata_e_clipped_result_bits_rawIn_8.sig, 22, 0)
node _activated_wdata_e_clipped_result_bits_fractOut_T_17 = mux(activated_wdata_e_clipped_result_bits_rawIn_8.isInf, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_fractOut_T_16)
node activated_wdata_e_clipped_result_bits_fractOut_8 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_8, activated_wdata_e_clipped_result_bits_denormFract_8, _activated_wdata_e_clipped_result_bits_fractOut_T_17)
node activated_wdata_e_clipped_result_bits_hi_8 = cat(activated_wdata_e_clipped_result_bits_rawIn_8.sign, activated_wdata_e_clipped_result_bits_expOut_8)
node _activated_wdata_e_clipped_result_bits_T_8 = cat(activated_wdata_e_clipped_result_bits_hi_8, activated_wdata_e_clipped_result_bits_fractOut_8)
connect activated_wdata_e_clipped_8.bits, _activated_wdata_e_clipped_result_bits_T_8
node _activated_wdata_e_act_T_8 = eq(activation, UInt<1>(0h1))
node activated_wdata_e_act_raw_sign_8 = bits(activated_wdata_e_clipped_8.bits, 31, 31)
node activated_wdata_e_act_raw_expIn_8 = bits(activated_wdata_e_clipped_8.bits, 30, 23)
node activated_wdata_e_act_raw_fractIn_8 = bits(activated_wdata_e_clipped_8.bits, 22, 0)
node activated_wdata_e_act_raw_isZeroExpIn_8 = eq(activated_wdata_e_act_raw_expIn_8, UInt<1>(0h0))
node activated_wdata_e_act_raw_isZeroFractIn_8 = eq(activated_wdata_e_act_raw_fractIn_8, UInt<1>(0h0))
node _activated_wdata_e_act_raw_normDist_T_352 = bits(activated_wdata_e_act_raw_fractIn_8, 0, 0)
node _activated_wdata_e_act_raw_normDist_T_353 = bits(activated_wdata_e_act_raw_fractIn_8, 1, 1)
node _activated_wdata_e_act_raw_normDist_T_354 = bits(activated_wdata_e_act_raw_fractIn_8, 2, 2)
node _activated_wdata_e_act_raw_normDist_T_355 = bits(activated_wdata_e_act_raw_fractIn_8, 3, 3)
node _activated_wdata_e_act_raw_normDist_T_356 = bits(activated_wdata_e_act_raw_fractIn_8, 4, 4)
node _activated_wdata_e_act_raw_normDist_T_357 = bits(activated_wdata_e_act_raw_fractIn_8, 5, 5)
node _activated_wdata_e_act_raw_normDist_T_358 = bits(activated_wdata_e_act_raw_fractIn_8, 6, 6)
node _activated_wdata_e_act_raw_normDist_T_359 = bits(activated_wdata_e_act_raw_fractIn_8, 7, 7)
node _activated_wdata_e_act_raw_normDist_T_360 = bits(activated_wdata_e_act_raw_fractIn_8, 8, 8)
node _activated_wdata_e_act_raw_normDist_T_361 = bits(activated_wdata_e_act_raw_fractIn_8, 9, 9)
node _activated_wdata_e_act_raw_normDist_T_362 = bits(activated_wdata_e_act_raw_fractIn_8, 10, 10)
node _activated_wdata_e_act_raw_normDist_T_363 = bits(activated_wdata_e_act_raw_fractIn_8, 11, 11)
node _activated_wdata_e_act_raw_normDist_T_364 = bits(activated_wdata_e_act_raw_fractIn_8, 12, 12)
node _activated_wdata_e_act_raw_normDist_T_365 = bits(activated_wdata_e_act_raw_fractIn_8, 13, 13)
node _activated_wdata_e_act_raw_normDist_T_366 = bits(activated_wdata_e_act_raw_fractIn_8, 14, 14)
node _activated_wdata_e_act_raw_normDist_T_367 = bits(activated_wdata_e_act_raw_fractIn_8, 15, 15)
node _activated_wdata_e_act_raw_normDist_T_368 = bits(activated_wdata_e_act_raw_fractIn_8, 16, 16)
node _activated_wdata_e_act_raw_normDist_T_369 = bits(activated_wdata_e_act_raw_fractIn_8, 17, 17)
node _activated_wdata_e_act_raw_normDist_T_370 = bits(activated_wdata_e_act_raw_fractIn_8, 18, 18)
node _activated_wdata_e_act_raw_normDist_T_371 = bits(activated_wdata_e_act_raw_fractIn_8, 19, 19)
node _activated_wdata_e_act_raw_normDist_T_372 = bits(activated_wdata_e_act_raw_fractIn_8, 20, 20)
node _activated_wdata_e_act_raw_normDist_T_373 = bits(activated_wdata_e_act_raw_fractIn_8, 21, 21)
node _activated_wdata_e_act_raw_normDist_T_374 = bits(activated_wdata_e_act_raw_fractIn_8, 22, 22)
node _activated_wdata_e_act_raw_normDist_T_375 = mux(_activated_wdata_e_act_raw_normDist_T_353, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_act_raw_normDist_T_376 = mux(_activated_wdata_e_act_raw_normDist_T_354, UInt<5>(0h14), _activated_wdata_e_act_raw_normDist_T_375)
node _activated_wdata_e_act_raw_normDist_T_377 = mux(_activated_wdata_e_act_raw_normDist_T_355, UInt<5>(0h13), _activated_wdata_e_act_raw_normDist_T_376)
node _activated_wdata_e_act_raw_normDist_T_378 = mux(_activated_wdata_e_act_raw_normDist_T_356, UInt<5>(0h12), _activated_wdata_e_act_raw_normDist_T_377)
node _activated_wdata_e_act_raw_normDist_T_379 = mux(_activated_wdata_e_act_raw_normDist_T_357, UInt<5>(0h11), _activated_wdata_e_act_raw_normDist_T_378)
node _activated_wdata_e_act_raw_normDist_T_380 = mux(_activated_wdata_e_act_raw_normDist_T_358, UInt<5>(0h10), _activated_wdata_e_act_raw_normDist_T_379)
node _activated_wdata_e_act_raw_normDist_T_381 = mux(_activated_wdata_e_act_raw_normDist_T_359, UInt<4>(0hf), _activated_wdata_e_act_raw_normDist_T_380)
node _activated_wdata_e_act_raw_normDist_T_382 = mux(_activated_wdata_e_act_raw_normDist_T_360, UInt<4>(0he), _activated_wdata_e_act_raw_normDist_T_381)
node _activated_wdata_e_act_raw_normDist_T_383 = mux(_activated_wdata_e_act_raw_normDist_T_361, UInt<4>(0hd), _activated_wdata_e_act_raw_normDist_T_382)
node _activated_wdata_e_act_raw_normDist_T_384 = mux(_activated_wdata_e_act_raw_normDist_T_362, UInt<4>(0hc), _activated_wdata_e_act_raw_normDist_T_383)
node _activated_wdata_e_act_raw_normDist_T_385 = mux(_activated_wdata_e_act_raw_normDist_T_363, UInt<4>(0hb), _activated_wdata_e_act_raw_normDist_T_384)
node _activated_wdata_e_act_raw_normDist_T_386 = mux(_activated_wdata_e_act_raw_normDist_T_364, UInt<4>(0ha), _activated_wdata_e_act_raw_normDist_T_385)
node _activated_wdata_e_act_raw_normDist_T_387 = mux(_activated_wdata_e_act_raw_normDist_T_365, UInt<4>(0h9), _activated_wdata_e_act_raw_normDist_T_386)
node _activated_wdata_e_act_raw_normDist_T_388 = mux(_activated_wdata_e_act_raw_normDist_T_366, UInt<4>(0h8), _activated_wdata_e_act_raw_normDist_T_387)
node _activated_wdata_e_act_raw_normDist_T_389 = mux(_activated_wdata_e_act_raw_normDist_T_367, UInt<3>(0h7), _activated_wdata_e_act_raw_normDist_T_388)
node _activated_wdata_e_act_raw_normDist_T_390 = mux(_activated_wdata_e_act_raw_normDist_T_368, UInt<3>(0h6), _activated_wdata_e_act_raw_normDist_T_389)
node _activated_wdata_e_act_raw_normDist_T_391 = mux(_activated_wdata_e_act_raw_normDist_T_369, UInt<3>(0h5), _activated_wdata_e_act_raw_normDist_T_390)
node _activated_wdata_e_act_raw_normDist_T_392 = mux(_activated_wdata_e_act_raw_normDist_T_370, UInt<3>(0h4), _activated_wdata_e_act_raw_normDist_T_391)
node _activated_wdata_e_act_raw_normDist_T_393 = mux(_activated_wdata_e_act_raw_normDist_T_371, UInt<2>(0h3), _activated_wdata_e_act_raw_normDist_T_392)
node _activated_wdata_e_act_raw_normDist_T_394 = mux(_activated_wdata_e_act_raw_normDist_T_372, UInt<2>(0h2), _activated_wdata_e_act_raw_normDist_T_393)
node _activated_wdata_e_act_raw_normDist_T_395 = mux(_activated_wdata_e_act_raw_normDist_T_373, UInt<1>(0h1), _activated_wdata_e_act_raw_normDist_T_394)
node activated_wdata_e_act_raw_normDist_8 = mux(_activated_wdata_e_act_raw_normDist_T_374, UInt<1>(0h0), _activated_wdata_e_act_raw_normDist_T_395)
node _activated_wdata_e_act_raw_subnormFract_T_16 = dshl(activated_wdata_e_act_raw_fractIn_8, activated_wdata_e_act_raw_normDist_8)
node _activated_wdata_e_act_raw_subnormFract_T_17 = bits(_activated_wdata_e_act_raw_subnormFract_T_16, 21, 0)
node activated_wdata_e_act_raw_subnormFract_8 = shl(_activated_wdata_e_act_raw_subnormFract_T_17, 1)
node _activated_wdata_e_act_raw_adjustedExp_T_40 = xor(activated_wdata_e_act_raw_normDist_8, UInt<9>(0h1ff))
node _activated_wdata_e_act_raw_adjustedExp_T_41 = mux(activated_wdata_e_act_raw_isZeroExpIn_8, _activated_wdata_e_act_raw_adjustedExp_T_40, activated_wdata_e_act_raw_expIn_8)
node _activated_wdata_e_act_raw_adjustedExp_T_42 = mux(activated_wdata_e_act_raw_isZeroExpIn_8, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_act_raw_adjustedExp_T_43 = or(UInt<8>(0h80), _activated_wdata_e_act_raw_adjustedExp_T_42)
node _activated_wdata_e_act_raw_adjustedExp_T_44 = add(_activated_wdata_e_act_raw_adjustedExp_T_41, _activated_wdata_e_act_raw_adjustedExp_T_43)
node activated_wdata_e_act_raw_adjustedExp_8 = tail(_activated_wdata_e_act_raw_adjustedExp_T_44, 1)
node activated_wdata_e_act_raw_isZero_8 = and(activated_wdata_e_act_raw_isZeroExpIn_8, activated_wdata_e_act_raw_isZeroFractIn_8)
node _activated_wdata_e_act_raw_isSpecial_T_8 = bits(activated_wdata_e_act_raw_adjustedExp_8, 8, 7)
node activated_wdata_e_act_raw_isSpecial_8 = eq(_activated_wdata_e_act_raw_isSpecial_T_8, UInt<2>(0h3))
wire activated_wdata_e_act_raw_8 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_act_raw_out_isNaN_T_16 = eq(activated_wdata_e_act_raw_isZeroFractIn_8, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_isNaN_T_17 = and(activated_wdata_e_act_raw_isSpecial_8, _activated_wdata_e_act_raw_out_isNaN_T_16)
connect activated_wdata_e_act_raw_8.isNaN, _activated_wdata_e_act_raw_out_isNaN_T_17
node _activated_wdata_e_act_raw_out_isInf_T_8 = and(activated_wdata_e_act_raw_isSpecial_8, activated_wdata_e_act_raw_isZeroFractIn_8)
connect activated_wdata_e_act_raw_8.isInf, _activated_wdata_e_act_raw_out_isInf_T_8
connect activated_wdata_e_act_raw_8.isZero, activated_wdata_e_act_raw_isZero_8
connect activated_wdata_e_act_raw_8.sign, activated_wdata_e_act_raw_sign_8
node _activated_wdata_e_act_raw_out_sExp_T_16 = bits(activated_wdata_e_act_raw_adjustedExp_8, 8, 0)
node _activated_wdata_e_act_raw_out_sExp_T_17 = cvt(_activated_wdata_e_act_raw_out_sExp_T_16)
connect activated_wdata_e_act_raw_8.sExp, _activated_wdata_e_act_raw_out_sExp_T_17
node _activated_wdata_e_act_raw_out_sig_T_32 = eq(activated_wdata_e_act_raw_isZero_8, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_sig_T_33 = cat(UInt<1>(0h0), _activated_wdata_e_act_raw_out_sig_T_32)
node _activated_wdata_e_act_raw_out_sig_T_34 = mux(activated_wdata_e_act_raw_isZeroExpIn_8, activated_wdata_e_act_raw_subnormFract_8, activated_wdata_e_act_raw_fractIn_8)
node _activated_wdata_e_act_raw_out_sig_T_35 = cat(_activated_wdata_e_act_raw_out_sig_T_33, _activated_wdata_e_act_raw_out_sig_T_34)
connect activated_wdata_e_act_raw_8.sig, _activated_wdata_e_act_raw_out_sig_T_35
wire activated_wdata_e_act_result_8 : { bits : UInt<32>}
node _activated_wdata_e_act_result_bits_T_24 = eq(activated_wdata_e_act_raw_8.isZero, UInt<1>(0h0))
node _activated_wdata_e_act_result_bits_T_25 = and(_activated_wdata_e_act_result_bits_T_24, activated_wdata_e_act_raw_8.sign)
node _activated_wdata_e_act_result_bits_T_26 = mux(_activated_wdata_e_act_result_bits_T_25, UInt<1>(0h0), activated_wdata_e_clipped_8.bits)
connect activated_wdata_e_act_result_8.bits, _activated_wdata_e_act_result_bits_T_26
node activated_wdata_e_act_8 = mux(_activated_wdata_e_act_T_8, activated_wdata_e_act_result_8, activated_wdata_e_clipped_8)
wire _activated_wdata_WIRE_8 : { bits : UInt<32>}[1]
connect _activated_wdata_WIRE_8[0], activated_wdata_e_act_8
node activated_wdata_e_clipped_self_rec_rawIn_sign_9 = bits(mesh.io.resp.bits.data[1][0].bits, 31, 31)
node activated_wdata_e_clipped_self_rec_rawIn_expIn_9 = bits(mesh.io.resp.bits.data[1][0].bits, 30, 23)
node activated_wdata_e_clipped_self_rec_rawIn_fractIn_9 = bits(mesh.io.resp.bits.data[1][0].bits, 22, 0)
node activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_9 = eq(activated_wdata_e_clipped_self_rec_rawIn_expIn_9, UInt<1>(0h0))
node activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_9 = eq(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_396 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 0, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_397 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 1, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_398 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 2, 2)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_399 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 3, 3)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_400 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 4, 4)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_401 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 5, 5)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_402 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 6, 6)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_403 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 7, 7)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_404 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 8, 8)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_405 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 9, 9)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_406 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 10, 10)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_407 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 11, 11)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_408 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 12, 12)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_409 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 13, 13)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_410 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 14, 14)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_411 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 15, 15)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_412 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 16, 16)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_413 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 17, 17)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_414 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 18, 18)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_415 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 19, 19)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_416 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 20, 20)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_417 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 21, 21)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_418 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, 22, 22)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_419 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_397, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_420 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_398, UInt<5>(0h14), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_419)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_421 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_399, UInt<5>(0h13), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_420)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_422 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_400, UInt<5>(0h12), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_421)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_423 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_401, UInt<5>(0h11), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_422)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_424 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_402, UInt<5>(0h10), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_423)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_425 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_403, UInt<4>(0hf), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_424)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_426 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_404, UInt<4>(0he), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_425)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_427 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_405, UInt<4>(0hd), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_426)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_428 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_406, UInt<4>(0hc), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_427)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_429 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_407, UInt<4>(0hb), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_428)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_430 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_408, UInt<4>(0ha), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_429)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_431 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_409, UInt<4>(0h9), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_430)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_432 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_410, UInt<4>(0h8), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_431)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_433 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_411, UInt<3>(0h7), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_432)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_434 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_412, UInt<3>(0h6), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_433)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_435 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_413, UInt<3>(0h5), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_434)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_436 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_414, UInt<3>(0h4), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_435)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_437 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_415, UInt<2>(0h3), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_436)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_438 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_416, UInt<2>(0h2), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_437)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_439 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_417, UInt<1>(0h1), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_438)
node activated_wdata_e_clipped_self_rec_rawIn_normDist_9 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_418, UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_439)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_18 = dshl(activated_wdata_e_clipped_self_rec_rawIn_fractIn_9, activated_wdata_e_clipped_self_rec_rawIn_normDist_9)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_19 = bits(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_18, 21, 0)
node activated_wdata_e_clipped_self_rec_rawIn_subnormFract_9 = shl(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_19, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_45 = xor(activated_wdata_e_clipped_self_rec_rawIn_normDist_9, UInt<9>(0h1ff))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_46 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_9, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_45, activated_wdata_e_clipped_self_rec_rawIn_expIn_9)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_47 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_9, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_48 = or(UInt<8>(0h80), _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_47)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_49 = add(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_46, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_48)
node activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_9 = tail(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_49, 1)
node activated_wdata_e_clipped_self_rec_rawIn_isZero_9 = and(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_9, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_9)
node _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_9 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_9, 8, 7)
node activated_wdata_e_clipped_self_rec_rawIn_isSpecial_9 = eq(_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_9, UInt<2>(0h3))
wire activated_wdata_e_clipped_self_rec_rawIn_9 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_18 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_9, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_19 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_9, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_18)
connect activated_wdata_e_clipped_self_rec_rawIn_9.isNaN, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_19
node _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_9 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_9, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_9)
connect activated_wdata_e_clipped_self_rec_rawIn_9.isInf, _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_9
connect activated_wdata_e_clipped_self_rec_rawIn_9.isZero, activated_wdata_e_clipped_self_rec_rawIn_isZero_9
connect activated_wdata_e_clipped_self_rec_rawIn_9.sign, activated_wdata_e_clipped_self_rec_rawIn_sign_9
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_18 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_9, 8, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_19 = cvt(_activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_18)
connect activated_wdata_e_clipped_self_rec_rawIn_9.sExp, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_19
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_36 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZero_9, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_37 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_36)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_38 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_9, activated_wdata_e_clipped_self_rec_rawIn_subnormFract_9, activated_wdata_e_clipped_self_rec_rawIn_fractIn_9)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_39 = cat(_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_37, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_38)
connect activated_wdata_e_clipped_self_rec_rawIn_9.sig, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_39
node _activated_wdata_e_clipped_self_rec_T_72 = bits(activated_wdata_e_clipped_self_rec_rawIn_9.sExp, 8, 6)
node _activated_wdata_e_clipped_self_rec_T_73 = mux(activated_wdata_e_clipped_self_rec_rawIn_9.isZero, UInt<3>(0h0), _activated_wdata_e_clipped_self_rec_T_72)
node _activated_wdata_e_clipped_self_rec_T_74 = mux(activated_wdata_e_clipped_self_rec_rawIn_9.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_T_75 = or(_activated_wdata_e_clipped_self_rec_T_73, _activated_wdata_e_clipped_self_rec_T_74)
node _activated_wdata_e_clipped_self_rec_T_76 = cat(activated_wdata_e_clipped_self_rec_rawIn_9.sign, _activated_wdata_e_clipped_self_rec_T_75)
node _activated_wdata_e_clipped_self_rec_T_77 = bits(activated_wdata_e_clipped_self_rec_rawIn_9.sExp, 5, 0)
node _activated_wdata_e_clipped_self_rec_T_78 = cat(_activated_wdata_e_clipped_self_rec_T_76, _activated_wdata_e_clipped_self_rec_T_77)
node _activated_wdata_e_clipped_self_rec_T_79 = bits(activated_wdata_e_clipped_self_rec_rawIn_9.sig, 22, 0)
node activated_wdata_e_clipped_self_rec_9 = cat(_activated_wdata_e_clipped_self_rec_T_78, _activated_wdata_e_clipped_self_rec_T_79)
inst activated_wdata_e_clipped_resizer_9 of RecFNToRecFN_249
connect activated_wdata_e_clipped_resizer_9.io.in, activated_wdata_e_clipped_self_rec_9
connect activated_wdata_e_clipped_resizer_9.io.roundingMode, UInt<3>(0h0)
connect activated_wdata_e_clipped_resizer_9.io.detectTininess, UInt<1>(0h1)
wire activated_wdata_e_clipped_9 : { bits : UInt<32>}
node activated_wdata_e_clipped_result_bits_rawIn_exp_9 = bits(activated_wdata_e_clipped_resizer_9.io.out, 31, 23)
node _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_9 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_9, 8, 6)
node activated_wdata_e_clipped_result_bits_rawIn_isZero_9 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isZero_T_9, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_9 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_9, 8, 7)
node activated_wdata_e_clipped_result_bits_rawIn_isSpecial_9 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_9, UInt<2>(0h3))
wire activated_wdata_e_clipped_result_bits_rawIn_9 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_18 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_9, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_19 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_9, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_18)
connect activated_wdata_e_clipped_result_bits_rawIn_9.isNaN, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_19
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_27 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_9, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_28 = eq(_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_27, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_29 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_9, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_28)
connect activated_wdata_e_clipped_result_bits_rawIn_9.isInf, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_29
connect activated_wdata_e_clipped_result_bits_rawIn_9.isZero, activated_wdata_e_clipped_result_bits_rawIn_isZero_9
node _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_9 = bits(activated_wdata_e_clipped_resizer_9.io.out, 32, 32)
connect activated_wdata_e_clipped_result_bits_rawIn_9.sign, _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_9
node _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_9 = cvt(activated_wdata_e_clipped_result_bits_rawIn_exp_9)
connect activated_wdata_e_clipped_result_bits_rawIn_9.sExp, _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_9
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_36 = eq(activated_wdata_e_clipped_result_bits_rawIn_isZero_9, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_37 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_36)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_38 = bits(activated_wdata_e_clipped_resizer_9.io.out, 22, 0)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_39 = cat(_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_37, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_38)
connect activated_wdata_e_clipped_result_bits_rawIn_9.sig, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_39
node activated_wdata_e_clipped_result_bits_isSubnormal_9 = lt(activated_wdata_e_clipped_result_bits_rawIn_9.sExp, asSInt(UInt<9>(0h82)))
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_18 = bits(activated_wdata_e_clipped_result_bits_rawIn_9.sExp, 4, 0)
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_19 = sub(UInt<1>(0h1), _activated_wdata_e_clipped_result_bits_denormShiftDist_T_18)
node activated_wdata_e_clipped_result_bits_denormShiftDist_9 = tail(_activated_wdata_e_clipped_result_bits_denormShiftDist_T_19, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_18 = shr(activated_wdata_e_clipped_result_bits_rawIn_9.sig, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_19 = dshr(_activated_wdata_e_clipped_result_bits_denormFract_T_18, activated_wdata_e_clipped_result_bits_denormShiftDist_9)
node activated_wdata_e_clipped_result_bits_denormFract_9 = bits(_activated_wdata_e_clipped_result_bits_denormFract_T_19, 22, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_54 = bits(activated_wdata_e_clipped_result_bits_rawIn_9.sExp, 7, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_55 = sub(_activated_wdata_e_clipped_result_bits_expOut_T_54, UInt<8>(0h81))
node _activated_wdata_e_clipped_result_bits_expOut_T_56 = tail(_activated_wdata_e_clipped_result_bits_expOut_T_55, 1)
node _activated_wdata_e_clipped_result_bits_expOut_T_57 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_9, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_expOut_T_56)
node _activated_wdata_e_clipped_result_bits_expOut_T_58 = or(activated_wdata_e_clipped_result_bits_rawIn_9.isNaN, activated_wdata_e_clipped_result_bits_rawIn_9.isInf)
node _activated_wdata_e_clipped_result_bits_expOut_T_59 = mux(_activated_wdata_e_clipped_result_bits_expOut_T_58, UInt<8>(0hff), UInt<8>(0h0))
node activated_wdata_e_clipped_result_bits_expOut_9 = or(_activated_wdata_e_clipped_result_bits_expOut_T_57, _activated_wdata_e_clipped_result_bits_expOut_T_59)
node _activated_wdata_e_clipped_result_bits_fractOut_T_18 = bits(activated_wdata_e_clipped_result_bits_rawIn_9.sig, 22, 0)
node _activated_wdata_e_clipped_result_bits_fractOut_T_19 = mux(activated_wdata_e_clipped_result_bits_rawIn_9.isInf, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_fractOut_T_18)
node activated_wdata_e_clipped_result_bits_fractOut_9 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_9, activated_wdata_e_clipped_result_bits_denormFract_9, _activated_wdata_e_clipped_result_bits_fractOut_T_19)
node activated_wdata_e_clipped_result_bits_hi_9 = cat(activated_wdata_e_clipped_result_bits_rawIn_9.sign, activated_wdata_e_clipped_result_bits_expOut_9)
node _activated_wdata_e_clipped_result_bits_T_9 = cat(activated_wdata_e_clipped_result_bits_hi_9, activated_wdata_e_clipped_result_bits_fractOut_9)
connect activated_wdata_e_clipped_9.bits, _activated_wdata_e_clipped_result_bits_T_9
node _activated_wdata_e_act_T_9 = eq(activation, UInt<1>(0h1))
node activated_wdata_e_act_raw_sign_9 = bits(activated_wdata_e_clipped_9.bits, 31, 31)
node activated_wdata_e_act_raw_expIn_9 = bits(activated_wdata_e_clipped_9.bits, 30, 23)
node activated_wdata_e_act_raw_fractIn_9 = bits(activated_wdata_e_clipped_9.bits, 22, 0)
node activated_wdata_e_act_raw_isZeroExpIn_9 = eq(activated_wdata_e_act_raw_expIn_9, UInt<1>(0h0))
node activated_wdata_e_act_raw_isZeroFractIn_9 = eq(activated_wdata_e_act_raw_fractIn_9, UInt<1>(0h0))
node _activated_wdata_e_act_raw_normDist_T_396 = bits(activated_wdata_e_act_raw_fractIn_9, 0, 0)
node _activated_wdata_e_act_raw_normDist_T_397 = bits(activated_wdata_e_act_raw_fractIn_9, 1, 1)
node _activated_wdata_e_act_raw_normDist_T_398 = bits(activated_wdata_e_act_raw_fractIn_9, 2, 2)
node _activated_wdata_e_act_raw_normDist_T_399 = bits(activated_wdata_e_act_raw_fractIn_9, 3, 3)
node _activated_wdata_e_act_raw_normDist_T_400 = bits(activated_wdata_e_act_raw_fractIn_9, 4, 4)
node _activated_wdata_e_act_raw_normDist_T_401 = bits(activated_wdata_e_act_raw_fractIn_9, 5, 5)
node _activated_wdata_e_act_raw_normDist_T_402 = bits(activated_wdata_e_act_raw_fractIn_9, 6, 6)
node _activated_wdata_e_act_raw_normDist_T_403 = bits(activated_wdata_e_act_raw_fractIn_9, 7, 7)
node _activated_wdata_e_act_raw_normDist_T_404 = bits(activated_wdata_e_act_raw_fractIn_9, 8, 8)
node _activated_wdata_e_act_raw_normDist_T_405 = bits(activated_wdata_e_act_raw_fractIn_9, 9, 9)
node _activated_wdata_e_act_raw_normDist_T_406 = bits(activated_wdata_e_act_raw_fractIn_9, 10, 10)
node _activated_wdata_e_act_raw_normDist_T_407 = bits(activated_wdata_e_act_raw_fractIn_9, 11, 11)
node _activated_wdata_e_act_raw_normDist_T_408 = bits(activated_wdata_e_act_raw_fractIn_9, 12, 12)
node _activated_wdata_e_act_raw_normDist_T_409 = bits(activated_wdata_e_act_raw_fractIn_9, 13, 13)
node _activated_wdata_e_act_raw_normDist_T_410 = bits(activated_wdata_e_act_raw_fractIn_9, 14, 14)
node _activated_wdata_e_act_raw_normDist_T_411 = bits(activated_wdata_e_act_raw_fractIn_9, 15, 15)
node _activated_wdata_e_act_raw_normDist_T_412 = bits(activated_wdata_e_act_raw_fractIn_9, 16, 16)
node _activated_wdata_e_act_raw_normDist_T_413 = bits(activated_wdata_e_act_raw_fractIn_9, 17, 17)
node _activated_wdata_e_act_raw_normDist_T_414 = bits(activated_wdata_e_act_raw_fractIn_9, 18, 18)
node _activated_wdata_e_act_raw_normDist_T_415 = bits(activated_wdata_e_act_raw_fractIn_9, 19, 19)
node _activated_wdata_e_act_raw_normDist_T_416 = bits(activated_wdata_e_act_raw_fractIn_9, 20, 20)
node _activated_wdata_e_act_raw_normDist_T_417 = bits(activated_wdata_e_act_raw_fractIn_9, 21, 21)
node _activated_wdata_e_act_raw_normDist_T_418 = bits(activated_wdata_e_act_raw_fractIn_9, 22, 22)
node _activated_wdata_e_act_raw_normDist_T_419 = mux(_activated_wdata_e_act_raw_normDist_T_397, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_act_raw_normDist_T_420 = mux(_activated_wdata_e_act_raw_normDist_T_398, UInt<5>(0h14), _activated_wdata_e_act_raw_normDist_T_419)
node _activated_wdata_e_act_raw_normDist_T_421 = mux(_activated_wdata_e_act_raw_normDist_T_399, UInt<5>(0h13), _activated_wdata_e_act_raw_normDist_T_420)
node _activated_wdata_e_act_raw_normDist_T_422 = mux(_activated_wdata_e_act_raw_normDist_T_400, UInt<5>(0h12), _activated_wdata_e_act_raw_normDist_T_421)
node _activated_wdata_e_act_raw_normDist_T_423 = mux(_activated_wdata_e_act_raw_normDist_T_401, UInt<5>(0h11), _activated_wdata_e_act_raw_normDist_T_422)
node _activated_wdata_e_act_raw_normDist_T_424 = mux(_activated_wdata_e_act_raw_normDist_T_402, UInt<5>(0h10), _activated_wdata_e_act_raw_normDist_T_423)
node _activated_wdata_e_act_raw_normDist_T_425 = mux(_activated_wdata_e_act_raw_normDist_T_403, UInt<4>(0hf), _activated_wdata_e_act_raw_normDist_T_424)
node _activated_wdata_e_act_raw_normDist_T_426 = mux(_activated_wdata_e_act_raw_normDist_T_404, UInt<4>(0he), _activated_wdata_e_act_raw_normDist_T_425)
node _activated_wdata_e_act_raw_normDist_T_427 = mux(_activated_wdata_e_act_raw_normDist_T_405, UInt<4>(0hd), _activated_wdata_e_act_raw_normDist_T_426)
node _activated_wdata_e_act_raw_normDist_T_428 = mux(_activated_wdata_e_act_raw_normDist_T_406, UInt<4>(0hc), _activated_wdata_e_act_raw_normDist_T_427)
node _activated_wdata_e_act_raw_normDist_T_429 = mux(_activated_wdata_e_act_raw_normDist_T_407, UInt<4>(0hb), _activated_wdata_e_act_raw_normDist_T_428)
node _activated_wdata_e_act_raw_normDist_T_430 = mux(_activated_wdata_e_act_raw_normDist_T_408, UInt<4>(0ha), _activated_wdata_e_act_raw_normDist_T_429)
node _activated_wdata_e_act_raw_normDist_T_431 = mux(_activated_wdata_e_act_raw_normDist_T_409, UInt<4>(0h9), _activated_wdata_e_act_raw_normDist_T_430)
node _activated_wdata_e_act_raw_normDist_T_432 = mux(_activated_wdata_e_act_raw_normDist_T_410, UInt<4>(0h8), _activated_wdata_e_act_raw_normDist_T_431)
node _activated_wdata_e_act_raw_normDist_T_433 = mux(_activated_wdata_e_act_raw_normDist_T_411, UInt<3>(0h7), _activated_wdata_e_act_raw_normDist_T_432)
node _activated_wdata_e_act_raw_normDist_T_434 = mux(_activated_wdata_e_act_raw_normDist_T_412, UInt<3>(0h6), _activated_wdata_e_act_raw_normDist_T_433)
node _activated_wdata_e_act_raw_normDist_T_435 = mux(_activated_wdata_e_act_raw_normDist_T_413, UInt<3>(0h5), _activated_wdata_e_act_raw_normDist_T_434)
node _activated_wdata_e_act_raw_normDist_T_436 = mux(_activated_wdata_e_act_raw_normDist_T_414, UInt<3>(0h4), _activated_wdata_e_act_raw_normDist_T_435)
node _activated_wdata_e_act_raw_normDist_T_437 = mux(_activated_wdata_e_act_raw_normDist_T_415, UInt<2>(0h3), _activated_wdata_e_act_raw_normDist_T_436)
node _activated_wdata_e_act_raw_normDist_T_438 = mux(_activated_wdata_e_act_raw_normDist_T_416, UInt<2>(0h2), _activated_wdata_e_act_raw_normDist_T_437)
node _activated_wdata_e_act_raw_normDist_T_439 = mux(_activated_wdata_e_act_raw_normDist_T_417, UInt<1>(0h1), _activated_wdata_e_act_raw_normDist_T_438)
node activated_wdata_e_act_raw_normDist_9 = mux(_activated_wdata_e_act_raw_normDist_T_418, UInt<1>(0h0), _activated_wdata_e_act_raw_normDist_T_439)
node _activated_wdata_e_act_raw_subnormFract_T_18 = dshl(activated_wdata_e_act_raw_fractIn_9, activated_wdata_e_act_raw_normDist_9)
node _activated_wdata_e_act_raw_subnormFract_T_19 = bits(_activated_wdata_e_act_raw_subnormFract_T_18, 21, 0)
node activated_wdata_e_act_raw_subnormFract_9 = shl(_activated_wdata_e_act_raw_subnormFract_T_19, 1)
node _activated_wdata_e_act_raw_adjustedExp_T_45 = xor(activated_wdata_e_act_raw_normDist_9, UInt<9>(0h1ff))
node _activated_wdata_e_act_raw_adjustedExp_T_46 = mux(activated_wdata_e_act_raw_isZeroExpIn_9, _activated_wdata_e_act_raw_adjustedExp_T_45, activated_wdata_e_act_raw_expIn_9)
node _activated_wdata_e_act_raw_adjustedExp_T_47 = mux(activated_wdata_e_act_raw_isZeroExpIn_9, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_act_raw_adjustedExp_T_48 = or(UInt<8>(0h80), _activated_wdata_e_act_raw_adjustedExp_T_47)
node _activated_wdata_e_act_raw_adjustedExp_T_49 = add(_activated_wdata_e_act_raw_adjustedExp_T_46, _activated_wdata_e_act_raw_adjustedExp_T_48)
node activated_wdata_e_act_raw_adjustedExp_9 = tail(_activated_wdata_e_act_raw_adjustedExp_T_49, 1)
node activated_wdata_e_act_raw_isZero_9 = and(activated_wdata_e_act_raw_isZeroExpIn_9, activated_wdata_e_act_raw_isZeroFractIn_9)
node _activated_wdata_e_act_raw_isSpecial_T_9 = bits(activated_wdata_e_act_raw_adjustedExp_9, 8, 7)
node activated_wdata_e_act_raw_isSpecial_9 = eq(_activated_wdata_e_act_raw_isSpecial_T_9, UInt<2>(0h3))
wire activated_wdata_e_act_raw_9 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_act_raw_out_isNaN_T_18 = eq(activated_wdata_e_act_raw_isZeroFractIn_9, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_isNaN_T_19 = and(activated_wdata_e_act_raw_isSpecial_9, _activated_wdata_e_act_raw_out_isNaN_T_18)
connect activated_wdata_e_act_raw_9.isNaN, _activated_wdata_e_act_raw_out_isNaN_T_19
node _activated_wdata_e_act_raw_out_isInf_T_9 = and(activated_wdata_e_act_raw_isSpecial_9, activated_wdata_e_act_raw_isZeroFractIn_9)
connect activated_wdata_e_act_raw_9.isInf, _activated_wdata_e_act_raw_out_isInf_T_9
connect activated_wdata_e_act_raw_9.isZero, activated_wdata_e_act_raw_isZero_9
connect activated_wdata_e_act_raw_9.sign, activated_wdata_e_act_raw_sign_9
node _activated_wdata_e_act_raw_out_sExp_T_18 = bits(activated_wdata_e_act_raw_adjustedExp_9, 8, 0)
node _activated_wdata_e_act_raw_out_sExp_T_19 = cvt(_activated_wdata_e_act_raw_out_sExp_T_18)
connect activated_wdata_e_act_raw_9.sExp, _activated_wdata_e_act_raw_out_sExp_T_19
node _activated_wdata_e_act_raw_out_sig_T_36 = eq(activated_wdata_e_act_raw_isZero_9, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_sig_T_37 = cat(UInt<1>(0h0), _activated_wdata_e_act_raw_out_sig_T_36)
node _activated_wdata_e_act_raw_out_sig_T_38 = mux(activated_wdata_e_act_raw_isZeroExpIn_9, activated_wdata_e_act_raw_subnormFract_9, activated_wdata_e_act_raw_fractIn_9)
node _activated_wdata_e_act_raw_out_sig_T_39 = cat(_activated_wdata_e_act_raw_out_sig_T_37, _activated_wdata_e_act_raw_out_sig_T_38)
connect activated_wdata_e_act_raw_9.sig, _activated_wdata_e_act_raw_out_sig_T_39
wire activated_wdata_e_act_result_9 : { bits : UInt<32>}
node _activated_wdata_e_act_result_bits_T_27 = eq(activated_wdata_e_act_raw_9.isZero, UInt<1>(0h0))
node _activated_wdata_e_act_result_bits_T_28 = and(_activated_wdata_e_act_result_bits_T_27, activated_wdata_e_act_raw_9.sign)
node _activated_wdata_e_act_result_bits_T_29 = mux(_activated_wdata_e_act_result_bits_T_28, UInt<1>(0h0), activated_wdata_e_clipped_9.bits)
connect activated_wdata_e_act_result_9.bits, _activated_wdata_e_act_result_bits_T_29
node activated_wdata_e_act_9 = mux(_activated_wdata_e_act_T_9, activated_wdata_e_act_result_9, activated_wdata_e_clipped_9)
wire _activated_wdata_WIRE_9 : { bits : UInt<32>}[1]
connect _activated_wdata_WIRE_9[0], activated_wdata_e_act_9
node activated_wdata_e_clipped_self_rec_rawIn_sign_10 = bits(mesh.io.resp.bits.data[2][0].bits, 31, 31)
node activated_wdata_e_clipped_self_rec_rawIn_expIn_10 = bits(mesh.io.resp.bits.data[2][0].bits, 30, 23)
node activated_wdata_e_clipped_self_rec_rawIn_fractIn_10 = bits(mesh.io.resp.bits.data[2][0].bits, 22, 0)
node activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_10 = eq(activated_wdata_e_clipped_self_rec_rawIn_expIn_10, UInt<1>(0h0))
node activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_10 = eq(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_440 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 0, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_441 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 1, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_442 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 2, 2)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_443 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 3, 3)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_444 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 4, 4)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_445 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 5, 5)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_446 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 6, 6)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_447 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 7, 7)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_448 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 8, 8)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_449 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 9, 9)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_450 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 10, 10)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_451 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 11, 11)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_452 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 12, 12)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_453 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 13, 13)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_454 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 14, 14)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_455 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 15, 15)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_456 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 16, 16)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_457 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 17, 17)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_458 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 18, 18)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_459 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 19, 19)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_460 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 20, 20)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_461 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 21, 21)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_462 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, 22, 22)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_463 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_441, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_464 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_442, UInt<5>(0h14), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_463)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_465 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_443, UInt<5>(0h13), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_464)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_466 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_444, UInt<5>(0h12), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_465)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_467 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_445, UInt<5>(0h11), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_466)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_468 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_446, UInt<5>(0h10), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_467)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_469 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_447, UInt<4>(0hf), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_468)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_470 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_448, UInt<4>(0he), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_469)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_471 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_449, UInt<4>(0hd), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_470)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_472 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_450, UInt<4>(0hc), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_471)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_473 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_451, UInt<4>(0hb), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_472)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_474 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_452, UInt<4>(0ha), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_473)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_475 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_453, UInt<4>(0h9), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_474)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_476 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_454, UInt<4>(0h8), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_475)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_477 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_455, UInt<3>(0h7), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_476)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_478 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_456, UInt<3>(0h6), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_477)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_479 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_457, UInt<3>(0h5), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_478)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_480 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_458, UInt<3>(0h4), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_479)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_481 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_459, UInt<2>(0h3), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_480)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_482 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_460, UInt<2>(0h2), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_481)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_483 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_461, UInt<1>(0h1), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_482)
node activated_wdata_e_clipped_self_rec_rawIn_normDist_10 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_462, UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_483)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_20 = dshl(activated_wdata_e_clipped_self_rec_rawIn_fractIn_10, activated_wdata_e_clipped_self_rec_rawIn_normDist_10)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_21 = bits(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_20, 21, 0)
node activated_wdata_e_clipped_self_rec_rawIn_subnormFract_10 = shl(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_21, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_50 = xor(activated_wdata_e_clipped_self_rec_rawIn_normDist_10, UInt<9>(0h1ff))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_51 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_10, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_50, activated_wdata_e_clipped_self_rec_rawIn_expIn_10)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_52 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_10, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_53 = or(UInt<8>(0h80), _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_52)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_54 = add(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_51, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_53)
node activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_10 = tail(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_54, 1)
node activated_wdata_e_clipped_self_rec_rawIn_isZero_10 = and(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_10, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_10)
node _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_10 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_10, 8, 7)
node activated_wdata_e_clipped_self_rec_rawIn_isSpecial_10 = eq(_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_10, UInt<2>(0h3))
wire activated_wdata_e_clipped_self_rec_rawIn_10 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_20 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_10, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_21 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_10, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_20)
connect activated_wdata_e_clipped_self_rec_rawIn_10.isNaN, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_21
node _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_10 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_10, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_10)
connect activated_wdata_e_clipped_self_rec_rawIn_10.isInf, _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_10
connect activated_wdata_e_clipped_self_rec_rawIn_10.isZero, activated_wdata_e_clipped_self_rec_rawIn_isZero_10
connect activated_wdata_e_clipped_self_rec_rawIn_10.sign, activated_wdata_e_clipped_self_rec_rawIn_sign_10
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_20 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_10, 8, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_21 = cvt(_activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_20)
connect activated_wdata_e_clipped_self_rec_rawIn_10.sExp, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_21
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_40 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZero_10, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_41 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_40)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_42 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_10, activated_wdata_e_clipped_self_rec_rawIn_subnormFract_10, activated_wdata_e_clipped_self_rec_rawIn_fractIn_10)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_43 = cat(_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_41, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_42)
connect activated_wdata_e_clipped_self_rec_rawIn_10.sig, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_43
node _activated_wdata_e_clipped_self_rec_T_80 = bits(activated_wdata_e_clipped_self_rec_rawIn_10.sExp, 8, 6)
node _activated_wdata_e_clipped_self_rec_T_81 = mux(activated_wdata_e_clipped_self_rec_rawIn_10.isZero, UInt<3>(0h0), _activated_wdata_e_clipped_self_rec_T_80)
node _activated_wdata_e_clipped_self_rec_T_82 = mux(activated_wdata_e_clipped_self_rec_rawIn_10.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_T_83 = or(_activated_wdata_e_clipped_self_rec_T_81, _activated_wdata_e_clipped_self_rec_T_82)
node _activated_wdata_e_clipped_self_rec_T_84 = cat(activated_wdata_e_clipped_self_rec_rawIn_10.sign, _activated_wdata_e_clipped_self_rec_T_83)
node _activated_wdata_e_clipped_self_rec_T_85 = bits(activated_wdata_e_clipped_self_rec_rawIn_10.sExp, 5, 0)
node _activated_wdata_e_clipped_self_rec_T_86 = cat(_activated_wdata_e_clipped_self_rec_T_84, _activated_wdata_e_clipped_self_rec_T_85)
node _activated_wdata_e_clipped_self_rec_T_87 = bits(activated_wdata_e_clipped_self_rec_rawIn_10.sig, 22, 0)
node activated_wdata_e_clipped_self_rec_10 = cat(_activated_wdata_e_clipped_self_rec_T_86, _activated_wdata_e_clipped_self_rec_T_87)
inst activated_wdata_e_clipped_resizer_10 of RecFNToRecFN_250
connect activated_wdata_e_clipped_resizer_10.io.in, activated_wdata_e_clipped_self_rec_10
connect activated_wdata_e_clipped_resizer_10.io.roundingMode, UInt<3>(0h0)
connect activated_wdata_e_clipped_resizer_10.io.detectTininess, UInt<1>(0h1)
wire activated_wdata_e_clipped_10 : { bits : UInt<32>}
node activated_wdata_e_clipped_result_bits_rawIn_exp_10 = bits(activated_wdata_e_clipped_resizer_10.io.out, 31, 23)
node _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_10 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_10, 8, 6)
node activated_wdata_e_clipped_result_bits_rawIn_isZero_10 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isZero_T_10, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_10 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_10, 8, 7)
node activated_wdata_e_clipped_result_bits_rawIn_isSpecial_10 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_10, UInt<2>(0h3))
wire activated_wdata_e_clipped_result_bits_rawIn_10 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_20 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_10, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_21 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_10, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_20)
connect activated_wdata_e_clipped_result_bits_rawIn_10.isNaN, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_21
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_30 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_10, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_31 = eq(_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_30, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_32 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_10, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_31)
connect activated_wdata_e_clipped_result_bits_rawIn_10.isInf, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_32
connect activated_wdata_e_clipped_result_bits_rawIn_10.isZero, activated_wdata_e_clipped_result_bits_rawIn_isZero_10
node _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_10 = bits(activated_wdata_e_clipped_resizer_10.io.out, 32, 32)
connect activated_wdata_e_clipped_result_bits_rawIn_10.sign, _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_10
node _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_10 = cvt(activated_wdata_e_clipped_result_bits_rawIn_exp_10)
connect activated_wdata_e_clipped_result_bits_rawIn_10.sExp, _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_10
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_40 = eq(activated_wdata_e_clipped_result_bits_rawIn_isZero_10, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_41 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_40)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_42 = bits(activated_wdata_e_clipped_resizer_10.io.out, 22, 0)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_43 = cat(_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_41, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_42)
connect activated_wdata_e_clipped_result_bits_rawIn_10.sig, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_43
node activated_wdata_e_clipped_result_bits_isSubnormal_10 = lt(activated_wdata_e_clipped_result_bits_rawIn_10.sExp, asSInt(UInt<9>(0h82)))
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_20 = bits(activated_wdata_e_clipped_result_bits_rawIn_10.sExp, 4, 0)
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_21 = sub(UInt<1>(0h1), _activated_wdata_e_clipped_result_bits_denormShiftDist_T_20)
node activated_wdata_e_clipped_result_bits_denormShiftDist_10 = tail(_activated_wdata_e_clipped_result_bits_denormShiftDist_T_21, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_20 = shr(activated_wdata_e_clipped_result_bits_rawIn_10.sig, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_21 = dshr(_activated_wdata_e_clipped_result_bits_denormFract_T_20, activated_wdata_e_clipped_result_bits_denormShiftDist_10)
node activated_wdata_e_clipped_result_bits_denormFract_10 = bits(_activated_wdata_e_clipped_result_bits_denormFract_T_21, 22, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_60 = bits(activated_wdata_e_clipped_result_bits_rawIn_10.sExp, 7, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_61 = sub(_activated_wdata_e_clipped_result_bits_expOut_T_60, UInt<8>(0h81))
node _activated_wdata_e_clipped_result_bits_expOut_T_62 = tail(_activated_wdata_e_clipped_result_bits_expOut_T_61, 1)
node _activated_wdata_e_clipped_result_bits_expOut_T_63 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_10, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_expOut_T_62)
node _activated_wdata_e_clipped_result_bits_expOut_T_64 = or(activated_wdata_e_clipped_result_bits_rawIn_10.isNaN, activated_wdata_e_clipped_result_bits_rawIn_10.isInf)
node _activated_wdata_e_clipped_result_bits_expOut_T_65 = mux(_activated_wdata_e_clipped_result_bits_expOut_T_64, UInt<8>(0hff), UInt<8>(0h0))
node activated_wdata_e_clipped_result_bits_expOut_10 = or(_activated_wdata_e_clipped_result_bits_expOut_T_63, _activated_wdata_e_clipped_result_bits_expOut_T_65)
node _activated_wdata_e_clipped_result_bits_fractOut_T_20 = bits(activated_wdata_e_clipped_result_bits_rawIn_10.sig, 22, 0)
node _activated_wdata_e_clipped_result_bits_fractOut_T_21 = mux(activated_wdata_e_clipped_result_bits_rawIn_10.isInf, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_fractOut_T_20)
node activated_wdata_e_clipped_result_bits_fractOut_10 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_10, activated_wdata_e_clipped_result_bits_denormFract_10, _activated_wdata_e_clipped_result_bits_fractOut_T_21)
node activated_wdata_e_clipped_result_bits_hi_10 = cat(activated_wdata_e_clipped_result_bits_rawIn_10.sign, activated_wdata_e_clipped_result_bits_expOut_10)
node _activated_wdata_e_clipped_result_bits_T_10 = cat(activated_wdata_e_clipped_result_bits_hi_10, activated_wdata_e_clipped_result_bits_fractOut_10)
connect activated_wdata_e_clipped_10.bits, _activated_wdata_e_clipped_result_bits_T_10
node _activated_wdata_e_act_T_10 = eq(activation, UInt<1>(0h1))
node activated_wdata_e_act_raw_sign_10 = bits(activated_wdata_e_clipped_10.bits, 31, 31)
node activated_wdata_e_act_raw_expIn_10 = bits(activated_wdata_e_clipped_10.bits, 30, 23)
node activated_wdata_e_act_raw_fractIn_10 = bits(activated_wdata_e_clipped_10.bits, 22, 0)
node activated_wdata_e_act_raw_isZeroExpIn_10 = eq(activated_wdata_e_act_raw_expIn_10, UInt<1>(0h0))
node activated_wdata_e_act_raw_isZeroFractIn_10 = eq(activated_wdata_e_act_raw_fractIn_10, UInt<1>(0h0))
node _activated_wdata_e_act_raw_normDist_T_440 = bits(activated_wdata_e_act_raw_fractIn_10, 0, 0)
node _activated_wdata_e_act_raw_normDist_T_441 = bits(activated_wdata_e_act_raw_fractIn_10, 1, 1)
node _activated_wdata_e_act_raw_normDist_T_442 = bits(activated_wdata_e_act_raw_fractIn_10, 2, 2)
node _activated_wdata_e_act_raw_normDist_T_443 = bits(activated_wdata_e_act_raw_fractIn_10, 3, 3)
node _activated_wdata_e_act_raw_normDist_T_444 = bits(activated_wdata_e_act_raw_fractIn_10, 4, 4)
node _activated_wdata_e_act_raw_normDist_T_445 = bits(activated_wdata_e_act_raw_fractIn_10, 5, 5)
node _activated_wdata_e_act_raw_normDist_T_446 = bits(activated_wdata_e_act_raw_fractIn_10, 6, 6)
node _activated_wdata_e_act_raw_normDist_T_447 = bits(activated_wdata_e_act_raw_fractIn_10, 7, 7)
node _activated_wdata_e_act_raw_normDist_T_448 = bits(activated_wdata_e_act_raw_fractIn_10, 8, 8)
node _activated_wdata_e_act_raw_normDist_T_449 = bits(activated_wdata_e_act_raw_fractIn_10, 9, 9)
node _activated_wdata_e_act_raw_normDist_T_450 = bits(activated_wdata_e_act_raw_fractIn_10, 10, 10)
node _activated_wdata_e_act_raw_normDist_T_451 = bits(activated_wdata_e_act_raw_fractIn_10, 11, 11)
node _activated_wdata_e_act_raw_normDist_T_452 = bits(activated_wdata_e_act_raw_fractIn_10, 12, 12)
node _activated_wdata_e_act_raw_normDist_T_453 = bits(activated_wdata_e_act_raw_fractIn_10, 13, 13)
node _activated_wdata_e_act_raw_normDist_T_454 = bits(activated_wdata_e_act_raw_fractIn_10, 14, 14)
node _activated_wdata_e_act_raw_normDist_T_455 = bits(activated_wdata_e_act_raw_fractIn_10, 15, 15)
node _activated_wdata_e_act_raw_normDist_T_456 = bits(activated_wdata_e_act_raw_fractIn_10, 16, 16)
node _activated_wdata_e_act_raw_normDist_T_457 = bits(activated_wdata_e_act_raw_fractIn_10, 17, 17)
node _activated_wdata_e_act_raw_normDist_T_458 = bits(activated_wdata_e_act_raw_fractIn_10, 18, 18)
node _activated_wdata_e_act_raw_normDist_T_459 = bits(activated_wdata_e_act_raw_fractIn_10, 19, 19)
node _activated_wdata_e_act_raw_normDist_T_460 = bits(activated_wdata_e_act_raw_fractIn_10, 20, 20)
node _activated_wdata_e_act_raw_normDist_T_461 = bits(activated_wdata_e_act_raw_fractIn_10, 21, 21)
node _activated_wdata_e_act_raw_normDist_T_462 = bits(activated_wdata_e_act_raw_fractIn_10, 22, 22)
node _activated_wdata_e_act_raw_normDist_T_463 = mux(_activated_wdata_e_act_raw_normDist_T_441, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_act_raw_normDist_T_464 = mux(_activated_wdata_e_act_raw_normDist_T_442, UInt<5>(0h14), _activated_wdata_e_act_raw_normDist_T_463)
node _activated_wdata_e_act_raw_normDist_T_465 = mux(_activated_wdata_e_act_raw_normDist_T_443, UInt<5>(0h13), _activated_wdata_e_act_raw_normDist_T_464)
node _activated_wdata_e_act_raw_normDist_T_466 = mux(_activated_wdata_e_act_raw_normDist_T_444, UInt<5>(0h12), _activated_wdata_e_act_raw_normDist_T_465)
node _activated_wdata_e_act_raw_normDist_T_467 = mux(_activated_wdata_e_act_raw_normDist_T_445, UInt<5>(0h11), _activated_wdata_e_act_raw_normDist_T_466)
node _activated_wdata_e_act_raw_normDist_T_468 = mux(_activated_wdata_e_act_raw_normDist_T_446, UInt<5>(0h10), _activated_wdata_e_act_raw_normDist_T_467)
node _activated_wdata_e_act_raw_normDist_T_469 = mux(_activated_wdata_e_act_raw_normDist_T_447, UInt<4>(0hf), _activated_wdata_e_act_raw_normDist_T_468)
node _activated_wdata_e_act_raw_normDist_T_470 = mux(_activated_wdata_e_act_raw_normDist_T_448, UInt<4>(0he), _activated_wdata_e_act_raw_normDist_T_469)
node _activated_wdata_e_act_raw_normDist_T_471 = mux(_activated_wdata_e_act_raw_normDist_T_449, UInt<4>(0hd), _activated_wdata_e_act_raw_normDist_T_470)
node _activated_wdata_e_act_raw_normDist_T_472 = mux(_activated_wdata_e_act_raw_normDist_T_450, UInt<4>(0hc), _activated_wdata_e_act_raw_normDist_T_471)
node _activated_wdata_e_act_raw_normDist_T_473 = mux(_activated_wdata_e_act_raw_normDist_T_451, UInt<4>(0hb), _activated_wdata_e_act_raw_normDist_T_472)
node _activated_wdata_e_act_raw_normDist_T_474 = mux(_activated_wdata_e_act_raw_normDist_T_452, UInt<4>(0ha), _activated_wdata_e_act_raw_normDist_T_473)
node _activated_wdata_e_act_raw_normDist_T_475 = mux(_activated_wdata_e_act_raw_normDist_T_453, UInt<4>(0h9), _activated_wdata_e_act_raw_normDist_T_474)
node _activated_wdata_e_act_raw_normDist_T_476 = mux(_activated_wdata_e_act_raw_normDist_T_454, UInt<4>(0h8), _activated_wdata_e_act_raw_normDist_T_475)
node _activated_wdata_e_act_raw_normDist_T_477 = mux(_activated_wdata_e_act_raw_normDist_T_455, UInt<3>(0h7), _activated_wdata_e_act_raw_normDist_T_476)
node _activated_wdata_e_act_raw_normDist_T_478 = mux(_activated_wdata_e_act_raw_normDist_T_456, UInt<3>(0h6), _activated_wdata_e_act_raw_normDist_T_477)
node _activated_wdata_e_act_raw_normDist_T_479 = mux(_activated_wdata_e_act_raw_normDist_T_457, UInt<3>(0h5), _activated_wdata_e_act_raw_normDist_T_478)
node _activated_wdata_e_act_raw_normDist_T_480 = mux(_activated_wdata_e_act_raw_normDist_T_458, UInt<3>(0h4), _activated_wdata_e_act_raw_normDist_T_479)
node _activated_wdata_e_act_raw_normDist_T_481 = mux(_activated_wdata_e_act_raw_normDist_T_459, UInt<2>(0h3), _activated_wdata_e_act_raw_normDist_T_480)
node _activated_wdata_e_act_raw_normDist_T_482 = mux(_activated_wdata_e_act_raw_normDist_T_460, UInt<2>(0h2), _activated_wdata_e_act_raw_normDist_T_481)
node _activated_wdata_e_act_raw_normDist_T_483 = mux(_activated_wdata_e_act_raw_normDist_T_461, UInt<1>(0h1), _activated_wdata_e_act_raw_normDist_T_482)
node activated_wdata_e_act_raw_normDist_10 = mux(_activated_wdata_e_act_raw_normDist_T_462, UInt<1>(0h0), _activated_wdata_e_act_raw_normDist_T_483)
node _activated_wdata_e_act_raw_subnormFract_T_20 = dshl(activated_wdata_e_act_raw_fractIn_10, activated_wdata_e_act_raw_normDist_10)
node _activated_wdata_e_act_raw_subnormFract_T_21 = bits(_activated_wdata_e_act_raw_subnormFract_T_20, 21, 0)
node activated_wdata_e_act_raw_subnormFract_10 = shl(_activated_wdata_e_act_raw_subnormFract_T_21, 1)
node _activated_wdata_e_act_raw_adjustedExp_T_50 = xor(activated_wdata_e_act_raw_normDist_10, UInt<9>(0h1ff))
node _activated_wdata_e_act_raw_adjustedExp_T_51 = mux(activated_wdata_e_act_raw_isZeroExpIn_10, _activated_wdata_e_act_raw_adjustedExp_T_50, activated_wdata_e_act_raw_expIn_10)
node _activated_wdata_e_act_raw_adjustedExp_T_52 = mux(activated_wdata_e_act_raw_isZeroExpIn_10, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_act_raw_adjustedExp_T_53 = or(UInt<8>(0h80), _activated_wdata_e_act_raw_adjustedExp_T_52)
node _activated_wdata_e_act_raw_adjustedExp_T_54 = add(_activated_wdata_e_act_raw_adjustedExp_T_51, _activated_wdata_e_act_raw_adjustedExp_T_53)
node activated_wdata_e_act_raw_adjustedExp_10 = tail(_activated_wdata_e_act_raw_adjustedExp_T_54, 1)
node activated_wdata_e_act_raw_isZero_10 = and(activated_wdata_e_act_raw_isZeroExpIn_10, activated_wdata_e_act_raw_isZeroFractIn_10)
node _activated_wdata_e_act_raw_isSpecial_T_10 = bits(activated_wdata_e_act_raw_adjustedExp_10, 8, 7)
node activated_wdata_e_act_raw_isSpecial_10 = eq(_activated_wdata_e_act_raw_isSpecial_T_10, UInt<2>(0h3))
wire activated_wdata_e_act_raw_10 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_act_raw_out_isNaN_T_20 = eq(activated_wdata_e_act_raw_isZeroFractIn_10, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_isNaN_T_21 = and(activated_wdata_e_act_raw_isSpecial_10, _activated_wdata_e_act_raw_out_isNaN_T_20)
connect activated_wdata_e_act_raw_10.isNaN, _activated_wdata_e_act_raw_out_isNaN_T_21
node _activated_wdata_e_act_raw_out_isInf_T_10 = and(activated_wdata_e_act_raw_isSpecial_10, activated_wdata_e_act_raw_isZeroFractIn_10)
connect activated_wdata_e_act_raw_10.isInf, _activated_wdata_e_act_raw_out_isInf_T_10
connect activated_wdata_e_act_raw_10.isZero, activated_wdata_e_act_raw_isZero_10
connect activated_wdata_e_act_raw_10.sign, activated_wdata_e_act_raw_sign_10
node _activated_wdata_e_act_raw_out_sExp_T_20 = bits(activated_wdata_e_act_raw_adjustedExp_10, 8, 0)
node _activated_wdata_e_act_raw_out_sExp_T_21 = cvt(_activated_wdata_e_act_raw_out_sExp_T_20)
connect activated_wdata_e_act_raw_10.sExp, _activated_wdata_e_act_raw_out_sExp_T_21
node _activated_wdata_e_act_raw_out_sig_T_40 = eq(activated_wdata_e_act_raw_isZero_10, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_sig_T_41 = cat(UInt<1>(0h0), _activated_wdata_e_act_raw_out_sig_T_40)
node _activated_wdata_e_act_raw_out_sig_T_42 = mux(activated_wdata_e_act_raw_isZeroExpIn_10, activated_wdata_e_act_raw_subnormFract_10, activated_wdata_e_act_raw_fractIn_10)
node _activated_wdata_e_act_raw_out_sig_T_43 = cat(_activated_wdata_e_act_raw_out_sig_T_41, _activated_wdata_e_act_raw_out_sig_T_42)
connect activated_wdata_e_act_raw_10.sig, _activated_wdata_e_act_raw_out_sig_T_43
wire activated_wdata_e_act_result_10 : { bits : UInt<32>}
node _activated_wdata_e_act_result_bits_T_30 = eq(activated_wdata_e_act_raw_10.isZero, UInt<1>(0h0))
node _activated_wdata_e_act_result_bits_T_31 = and(_activated_wdata_e_act_result_bits_T_30, activated_wdata_e_act_raw_10.sign)
node _activated_wdata_e_act_result_bits_T_32 = mux(_activated_wdata_e_act_result_bits_T_31, UInt<1>(0h0), activated_wdata_e_clipped_10.bits)
connect activated_wdata_e_act_result_10.bits, _activated_wdata_e_act_result_bits_T_32
node activated_wdata_e_act_10 = mux(_activated_wdata_e_act_T_10, activated_wdata_e_act_result_10, activated_wdata_e_clipped_10)
wire _activated_wdata_WIRE_10 : { bits : UInt<32>}[1]
connect _activated_wdata_WIRE_10[0], activated_wdata_e_act_10
node activated_wdata_e_clipped_self_rec_rawIn_sign_11 = bits(mesh.io.resp.bits.data[3][0].bits, 31, 31)
node activated_wdata_e_clipped_self_rec_rawIn_expIn_11 = bits(mesh.io.resp.bits.data[3][0].bits, 30, 23)
node activated_wdata_e_clipped_self_rec_rawIn_fractIn_11 = bits(mesh.io.resp.bits.data[3][0].bits, 22, 0)
node activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_11 = eq(activated_wdata_e_clipped_self_rec_rawIn_expIn_11, UInt<1>(0h0))
node activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_11 = eq(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_484 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 0, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_485 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 1, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_486 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 2, 2)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_487 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 3, 3)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_488 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 4, 4)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_489 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 5, 5)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_490 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 6, 6)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_491 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 7, 7)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_492 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 8, 8)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_493 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 9, 9)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_494 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 10, 10)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_495 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 11, 11)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_496 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 12, 12)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_497 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 13, 13)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_498 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 14, 14)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_499 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 15, 15)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_500 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 16, 16)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_501 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 17, 17)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_502 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 18, 18)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_503 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 19, 19)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_504 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 20, 20)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_505 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 21, 21)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_506 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, 22, 22)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_507 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_485, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_508 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_486, UInt<5>(0h14), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_507)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_509 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_487, UInt<5>(0h13), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_508)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_510 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_488, UInt<5>(0h12), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_509)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_511 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_489, UInt<5>(0h11), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_510)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_512 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_490, UInt<5>(0h10), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_511)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_513 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_491, UInt<4>(0hf), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_512)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_514 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_492, UInt<4>(0he), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_513)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_515 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_493, UInt<4>(0hd), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_514)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_516 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_494, UInt<4>(0hc), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_515)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_517 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_495, UInt<4>(0hb), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_516)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_518 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_496, UInt<4>(0ha), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_517)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_519 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_497, UInt<4>(0h9), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_518)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_520 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_498, UInt<4>(0h8), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_519)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_521 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_499, UInt<3>(0h7), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_520)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_522 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_500, UInt<3>(0h6), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_521)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_523 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_501, UInt<3>(0h5), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_522)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_524 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_502, UInt<3>(0h4), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_523)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_525 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_503, UInt<2>(0h3), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_524)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_526 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_504, UInt<2>(0h2), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_525)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_527 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_505, UInt<1>(0h1), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_526)
node activated_wdata_e_clipped_self_rec_rawIn_normDist_11 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_506, UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_527)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_22 = dshl(activated_wdata_e_clipped_self_rec_rawIn_fractIn_11, activated_wdata_e_clipped_self_rec_rawIn_normDist_11)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_23 = bits(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_22, 21, 0)
node activated_wdata_e_clipped_self_rec_rawIn_subnormFract_11 = shl(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_23, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_55 = xor(activated_wdata_e_clipped_self_rec_rawIn_normDist_11, UInt<9>(0h1ff))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_56 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_11, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_55, activated_wdata_e_clipped_self_rec_rawIn_expIn_11)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_57 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_11, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_58 = or(UInt<8>(0h80), _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_57)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_59 = add(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_56, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_58)
node activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_11 = tail(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_59, 1)
node activated_wdata_e_clipped_self_rec_rawIn_isZero_11 = and(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_11, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_11)
node _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_11 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_11, 8, 7)
node activated_wdata_e_clipped_self_rec_rawIn_isSpecial_11 = eq(_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_11, UInt<2>(0h3))
wire activated_wdata_e_clipped_self_rec_rawIn_11 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_22 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_11, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_23 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_11, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_22)
connect activated_wdata_e_clipped_self_rec_rawIn_11.isNaN, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_23
node _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_11 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_11, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_11)
connect activated_wdata_e_clipped_self_rec_rawIn_11.isInf, _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_11
connect activated_wdata_e_clipped_self_rec_rawIn_11.isZero, activated_wdata_e_clipped_self_rec_rawIn_isZero_11
connect activated_wdata_e_clipped_self_rec_rawIn_11.sign, activated_wdata_e_clipped_self_rec_rawIn_sign_11
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_22 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_11, 8, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_23 = cvt(_activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_22)
connect activated_wdata_e_clipped_self_rec_rawIn_11.sExp, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_23
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_44 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZero_11, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_45 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_44)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_46 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_11, activated_wdata_e_clipped_self_rec_rawIn_subnormFract_11, activated_wdata_e_clipped_self_rec_rawIn_fractIn_11)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_47 = cat(_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_45, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_46)
connect activated_wdata_e_clipped_self_rec_rawIn_11.sig, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_47
node _activated_wdata_e_clipped_self_rec_T_88 = bits(activated_wdata_e_clipped_self_rec_rawIn_11.sExp, 8, 6)
node _activated_wdata_e_clipped_self_rec_T_89 = mux(activated_wdata_e_clipped_self_rec_rawIn_11.isZero, UInt<3>(0h0), _activated_wdata_e_clipped_self_rec_T_88)
node _activated_wdata_e_clipped_self_rec_T_90 = mux(activated_wdata_e_clipped_self_rec_rawIn_11.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_T_91 = or(_activated_wdata_e_clipped_self_rec_T_89, _activated_wdata_e_clipped_self_rec_T_90)
node _activated_wdata_e_clipped_self_rec_T_92 = cat(activated_wdata_e_clipped_self_rec_rawIn_11.sign, _activated_wdata_e_clipped_self_rec_T_91)
node _activated_wdata_e_clipped_self_rec_T_93 = bits(activated_wdata_e_clipped_self_rec_rawIn_11.sExp, 5, 0)
node _activated_wdata_e_clipped_self_rec_T_94 = cat(_activated_wdata_e_clipped_self_rec_T_92, _activated_wdata_e_clipped_self_rec_T_93)
node _activated_wdata_e_clipped_self_rec_T_95 = bits(activated_wdata_e_clipped_self_rec_rawIn_11.sig, 22, 0)
node activated_wdata_e_clipped_self_rec_11 = cat(_activated_wdata_e_clipped_self_rec_T_94, _activated_wdata_e_clipped_self_rec_T_95)
inst activated_wdata_e_clipped_resizer_11 of RecFNToRecFN_251
connect activated_wdata_e_clipped_resizer_11.io.in, activated_wdata_e_clipped_self_rec_11
connect activated_wdata_e_clipped_resizer_11.io.roundingMode, UInt<3>(0h0)
connect activated_wdata_e_clipped_resizer_11.io.detectTininess, UInt<1>(0h1)
wire activated_wdata_e_clipped_11 : { bits : UInt<32>}
node activated_wdata_e_clipped_result_bits_rawIn_exp_11 = bits(activated_wdata_e_clipped_resizer_11.io.out, 31, 23)
node _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_11 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_11, 8, 6)
node activated_wdata_e_clipped_result_bits_rawIn_isZero_11 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isZero_T_11, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_11 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_11, 8, 7)
node activated_wdata_e_clipped_result_bits_rawIn_isSpecial_11 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_11, UInt<2>(0h3))
wire activated_wdata_e_clipped_result_bits_rawIn_11 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_22 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_11, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_23 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_11, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_22)
connect activated_wdata_e_clipped_result_bits_rawIn_11.isNaN, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_23
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_33 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_11, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_34 = eq(_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_33, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_35 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_11, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_34)
connect activated_wdata_e_clipped_result_bits_rawIn_11.isInf, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_35
connect activated_wdata_e_clipped_result_bits_rawIn_11.isZero, activated_wdata_e_clipped_result_bits_rawIn_isZero_11
node _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_11 = bits(activated_wdata_e_clipped_resizer_11.io.out, 32, 32)
connect activated_wdata_e_clipped_result_bits_rawIn_11.sign, _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_11
node _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_11 = cvt(activated_wdata_e_clipped_result_bits_rawIn_exp_11)
connect activated_wdata_e_clipped_result_bits_rawIn_11.sExp, _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_11
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_44 = eq(activated_wdata_e_clipped_result_bits_rawIn_isZero_11, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_45 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_44)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_46 = bits(activated_wdata_e_clipped_resizer_11.io.out, 22, 0)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_47 = cat(_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_45, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_46)
connect activated_wdata_e_clipped_result_bits_rawIn_11.sig, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_47
node activated_wdata_e_clipped_result_bits_isSubnormal_11 = lt(activated_wdata_e_clipped_result_bits_rawIn_11.sExp, asSInt(UInt<9>(0h82)))
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_22 = bits(activated_wdata_e_clipped_result_bits_rawIn_11.sExp, 4, 0)
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_23 = sub(UInt<1>(0h1), _activated_wdata_e_clipped_result_bits_denormShiftDist_T_22)
node activated_wdata_e_clipped_result_bits_denormShiftDist_11 = tail(_activated_wdata_e_clipped_result_bits_denormShiftDist_T_23, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_22 = shr(activated_wdata_e_clipped_result_bits_rawIn_11.sig, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_23 = dshr(_activated_wdata_e_clipped_result_bits_denormFract_T_22, activated_wdata_e_clipped_result_bits_denormShiftDist_11)
node activated_wdata_e_clipped_result_bits_denormFract_11 = bits(_activated_wdata_e_clipped_result_bits_denormFract_T_23, 22, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_66 = bits(activated_wdata_e_clipped_result_bits_rawIn_11.sExp, 7, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_67 = sub(_activated_wdata_e_clipped_result_bits_expOut_T_66, UInt<8>(0h81))
node _activated_wdata_e_clipped_result_bits_expOut_T_68 = tail(_activated_wdata_e_clipped_result_bits_expOut_T_67, 1)
node _activated_wdata_e_clipped_result_bits_expOut_T_69 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_11, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_expOut_T_68)
node _activated_wdata_e_clipped_result_bits_expOut_T_70 = or(activated_wdata_e_clipped_result_bits_rawIn_11.isNaN, activated_wdata_e_clipped_result_bits_rawIn_11.isInf)
node _activated_wdata_e_clipped_result_bits_expOut_T_71 = mux(_activated_wdata_e_clipped_result_bits_expOut_T_70, UInt<8>(0hff), UInt<8>(0h0))
node activated_wdata_e_clipped_result_bits_expOut_11 = or(_activated_wdata_e_clipped_result_bits_expOut_T_69, _activated_wdata_e_clipped_result_bits_expOut_T_71)
node _activated_wdata_e_clipped_result_bits_fractOut_T_22 = bits(activated_wdata_e_clipped_result_bits_rawIn_11.sig, 22, 0)
node _activated_wdata_e_clipped_result_bits_fractOut_T_23 = mux(activated_wdata_e_clipped_result_bits_rawIn_11.isInf, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_fractOut_T_22)
node activated_wdata_e_clipped_result_bits_fractOut_11 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_11, activated_wdata_e_clipped_result_bits_denormFract_11, _activated_wdata_e_clipped_result_bits_fractOut_T_23)
node activated_wdata_e_clipped_result_bits_hi_11 = cat(activated_wdata_e_clipped_result_bits_rawIn_11.sign, activated_wdata_e_clipped_result_bits_expOut_11)
node _activated_wdata_e_clipped_result_bits_T_11 = cat(activated_wdata_e_clipped_result_bits_hi_11, activated_wdata_e_clipped_result_bits_fractOut_11)
connect activated_wdata_e_clipped_11.bits, _activated_wdata_e_clipped_result_bits_T_11
node _activated_wdata_e_act_T_11 = eq(activation, UInt<1>(0h1))
node activated_wdata_e_act_raw_sign_11 = bits(activated_wdata_e_clipped_11.bits, 31, 31)
node activated_wdata_e_act_raw_expIn_11 = bits(activated_wdata_e_clipped_11.bits, 30, 23)
node activated_wdata_e_act_raw_fractIn_11 = bits(activated_wdata_e_clipped_11.bits, 22, 0)
node activated_wdata_e_act_raw_isZeroExpIn_11 = eq(activated_wdata_e_act_raw_expIn_11, UInt<1>(0h0))
node activated_wdata_e_act_raw_isZeroFractIn_11 = eq(activated_wdata_e_act_raw_fractIn_11, UInt<1>(0h0))
node _activated_wdata_e_act_raw_normDist_T_484 = bits(activated_wdata_e_act_raw_fractIn_11, 0, 0)
node _activated_wdata_e_act_raw_normDist_T_485 = bits(activated_wdata_e_act_raw_fractIn_11, 1, 1)
node _activated_wdata_e_act_raw_normDist_T_486 = bits(activated_wdata_e_act_raw_fractIn_11, 2, 2)
node _activated_wdata_e_act_raw_normDist_T_487 = bits(activated_wdata_e_act_raw_fractIn_11, 3, 3)
node _activated_wdata_e_act_raw_normDist_T_488 = bits(activated_wdata_e_act_raw_fractIn_11, 4, 4)
node _activated_wdata_e_act_raw_normDist_T_489 = bits(activated_wdata_e_act_raw_fractIn_11, 5, 5)
node _activated_wdata_e_act_raw_normDist_T_490 = bits(activated_wdata_e_act_raw_fractIn_11, 6, 6)
node _activated_wdata_e_act_raw_normDist_T_491 = bits(activated_wdata_e_act_raw_fractIn_11, 7, 7)
node _activated_wdata_e_act_raw_normDist_T_492 = bits(activated_wdata_e_act_raw_fractIn_11, 8, 8)
node _activated_wdata_e_act_raw_normDist_T_493 = bits(activated_wdata_e_act_raw_fractIn_11, 9, 9)
node _activated_wdata_e_act_raw_normDist_T_494 = bits(activated_wdata_e_act_raw_fractIn_11, 10, 10)
node _activated_wdata_e_act_raw_normDist_T_495 = bits(activated_wdata_e_act_raw_fractIn_11, 11, 11)
node _activated_wdata_e_act_raw_normDist_T_496 = bits(activated_wdata_e_act_raw_fractIn_11, 12, 12)
node _activated_wdata_e_act_raw_normDist_T_497 = bits(activated_wdata_e_act_raw_fractIn_11, 13, 13)
node _activated_wdata_e_act_raw_normDist_T_498 = bits(activated_wdata_e_act_raw_fractIn_11, 14, 14)
node _activated_wdata_e_act_raw_normDist_T_499 = bits(activated_wdata_e_act_raw_fractIn_11, 15, 15)
node _activated_wdata_e_act_raw_normDist_T_500 = bits(activated_wdata_e_act_raw_fractIn_11, 16, 16)
node _activated_wdata_e_act_raw_normDist_T_501 = bits(activated_wdata_e_act_raw_fractIn_11, 17, 17)
node _activated_wdata_e_act_raw_normDist_T_502 = bits(activated_wdata_e_act_raw_fractIn_11, 18, 18)
node _activated_wdata_e_act_raw_normDist_T_503 = bits(activated_wdata_e_act_raw_fractIn_11, 19, 19)
node _activated_wdata_e_act_raw_normDist_T_504 = bits(activated_wdata_e_act_raw_fractIn_11, 20, 20)
node _activated_wdata_e_act_raw_normDist_T_505 = bits(activated_wdata_e_act_raw_fractIn_11, 21, 21)
node _activated_wdata_e_act_raw_normDist_T_506 = bits(activated_wdata_e_act_raw_fractIn_11, 22, 22)
node _activated_wdata_e_act_raw_normDist_T_507 = mux(_activated_wdata_e_act_raw_normDist_T_485, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_act_raw_normDist_T_508 = mux(_activated_wdata_e_act_raw_normDist_T_486, UInt<5>(0h14), _activated_wdata_e_act_raw_normDist_T_507)
node _activated_wdata_e_act_raw_normDist_T_509 = mux(_activated_wdata_e_act_raw_normDist_T_487, UInt<5>(0h13), _activated_wdata_e_act_raw_normDist_T_508)
node _activated_wdata_e_act_raw_normDist_T_510 = mux(_activated_wdata_e_act_raw_normDist_T_488, UInt<5>(0h12), _activated_wdata_e_act_raw_normDist_T_509)
node _activated_wdata_e_act_raw_normDist_T_511 = mux(_activated_wdata_e_act_raw_normDist_T_489, UInt<5>(0h11), _activated_wdata_e_act_raw_normDist_T_510)
node _activated_wdata_e_act_raw_normDist_T_512 = mux(_activated_wdata_e_act_raw_normDist_T_490, UInt<5>(0h10), _activated_wdata_e_act_raw_normDist_T_511)
node _activated_wdata_e_act_raw_normDist_T_513 = mux(_activated_wdata_e_act_raw_normDist_T_491, UInt<4>(0hf), _activated_wdata_e_act_raw_normDist_T_512)
node _activated_wdata_e_act_raw_normDist_T_514 = mux(_activated_wdata_e_act_raw_normDist_T_492, UInt<4>(0he), _activated_wdata_e_act_raw_normDist_T_513)
node _activated_wdata_e_act_raw_normDist_T_515 = mux(_activated_wdata_e_act_raw_normDist_T_493, UInt<4>(0hd), _activated_wdata_e_act_raw_normDist_T_514)
node _activated_wdata_e_act_raw_normDist_T_516 = mux(_activated_wdata_e_act_raw_normDist_T_494, UInt<4>(0hc), _activated_wdata_e_act_raw_normDist_T_515)
node _activated_wdata_e_act_raw_normDist_T_517 = mux(_activated_wdata_e_act_raw_normDist_T_495, UInt<4>(0hb), _activated_wdata_e_act_raw_normDist_T_516)
node _activated_wdata_e_act_raw_normDist_T_518 = mux(_activated_wdata_e_act_raw_normDist_T_496, UInt<4>(0ha), _activated_wdata_e_act_raw_normDist_T_517)
node _activated_wdata_e_act_raw_normDist_T_519 = mux(_activated_wdata_e_act_raw_normDist_T_497, UInt<4>(0h9), _activated_wdata_e_act_raw_normDist_T_518)
node _activated_wdata_e_act_raw_normDist_T_520 = mux(_activated_wdata_e_act_raw_normDist_T_498, UInt<4>(0h8), _activated_wdata_e_act_raw_normDist_T_519)
node _activated_wdata_e_act_raw_normDist_T_521 = mux(_activated_wdata_e_act_raw_normDist_T_499, UInt<3>(0h7), _activated_wdata_e_act_raw_normDist_T_520)
node _activated_wdata_e_act_raw_normDist_T_522 = mux(_activated_wdata_e_act_raw_normDist_T_500, UInt<3>(0h6), _activated_wdata_e_act_raw_normDist_T_521)
node _activated_wdata_e_act_raw_normDist_T_523 = mux(_activated_wdata_e_act_raw_normDist_T_501, UInt<3>(0h5), _activated_wdata_e_act_raw_normDist_T_522)
node _activated_wdata_e_act_raw_normDist_T_524 = mux(_activated_wdata_e_act_raw_normDist_T_502, UInt<3>(0h4), _activated_wdata_e_act_raw_normDist_T_523)
node _activated_wdata_e_act_raw_normDist_T_525 = mux(_activated_wdata_e_act_raw_normDist_T_503, UInt<2>(0h3), _activated_wdata_e_act_raw_normDist_T_524)
node _activated_wdata_e_act_raw_normDist_T_526 = mux(_activated_wdata_e_act_raw_normDist_T_504, UInt<2>(0h2), _activated_wdata_e_act_raw_normDist_T_525)
node _activated_wdata_e_act_raw_normDist_T_527 = mux(_activated_wdata_e_act_raw_normDist_T_505, UInt<1>(0h1), _activated_wdata_e_act_raw_normDist_T_526)
node activated_wdata_e_act_raw_normDist_11 = mux(_activated_wdata_e_act_raw_normDist_T_506, UInt<1>(0h0), _activated_wdata_e_act_raw_normDist_T_527)
node _activated_wdata_e_act_raw_subnormFract_T_22 = dshl(activated_wdata_e_act_raw_fractIn_11, activated_wdata_e_act_raw_normDist_11)
node _activated_wdata_e_act_raw_subnormFract_T_23 = bits(_activated_wdata_e_act_raw_subnormFract_T_22, 21, 0)
node activated_wdata_e_act_raw_subnormFract_11 = shl(_activated_wdata_e_act_raw_subnormFract_T_23, 1)
node _activated_wdata_e_act_raw_adjustedExp_T_55 = xor(activated_wdata_e_act_raw_normDist_11, UInt<9>(0h1ff))
node _activated_wdata_e_act_raw_adjustedExp_T_56 = mux(activated_wdata_e_act_raw_isZeroExpIn_11, _activated_wdata_e_act_raw_adjustedExp_T_55, activated_wdata_e_act_raw_expIn_11)
node _activated_wdata_e_act_raw_adjustedExp_T_57 = mux(activated_wdata_e_act_raw_isZeroExpIn_11, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_act_raw_adjustedExp_T_58 = or(UInt<8>(0h80), _activated_wdata_e_act_raw_adjustedExp_T_57)
node _activated_wdata_e_act_raw_adjustedExp_T_59 = add(_activated_wdata_e_act_raw_adjustedExp_T_56, _activated_wdata_e_act_raw_adjustedExp_T_58)
node activated_wdata_e_act_raw_adjustedExp_11 = tail(_activated_wdata_e_act_raw_adjustedExp_T_59, 1)
node activated_wdata_e_act_raw_isZero_11 = and(activated_wdata_e_act_raw_isZeroExpIn_11, activated_wdata_e_act_raw_isZeroFractIn_11)
node _activated_wdata_e_act_raw_isSpecial_T_11 = bits(activated_wdata_e_act_raw_adjustedExp_11, 8, 7)
node activated_wdata_e_act_raw_isSpecial_11 = eq(_activated_wdata_e_act_raw_isSpecial_T_11, UInt<2>(0h3))
wire activated_wdata_e_act_raw_11 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_act_raw_out_isNaN_T_22 = eq(activated_wdata_e_act_raw_isZeroFractIn_11, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_isNaN_T_23 = and(activated_wdata_e_act_raw_isSpecial_11, _activated_wdata_e_act_raw_out_isNaN_T_22)
connect activated_wdata_e_act_raw_11.isNaN, _activated_wdata_e_act_raw_out_isNaN_T_23
node _activated_wdata_e_act_raw_out_isInf_T_11 = and(activated_wdata_e_act_raw_isSpecial_11, activated_wdata_e_act_raw_isZeroFractIn_11)
connect activated_wdata_e_act_raw_11.isInf, _activated_wdata_e_act_raw_out_isInf_T_11
connect activated_wdata_e_act_raw_11.isZero, activated_wdata_e_act_raw_isZero_11
connect activated_wdata_e_act_raw_11.sign, activated_wdata_e_act_raw_sign_11
node _activated_wdata_e_act_raw_out_sExp_T_22 = bits(activated_wdata_e_act_raw_adjustedExp_11, 8, 0)
node _activated_wdata_e_act_raw_out_sExp_T_23 = cvt(_activated_wdata_e_act_raw_out_sExp_T_22)
connect activated_wdata_e_act_raw_11.sExp, _activated_wdata_e_act_raw_out_sExp_T_23
node _activated_wdata_e_act_raw_out_sig_T_44 = eq(activated_wdata_e_act_raw_isZero_11, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_sig_T_45 = cat(UInt<1>(0h0), _activated_wdata_e_act_raw_out_sig_T_44)
node _activated_wdata_e_act_raw_out_sig_T_46 = mux(activated_wdata_e_act_raw_isZeroExpIn_11, activated_wdata_e_act_raw_subnormFract_11, activated_wdata_e_act_raw_fractIn_11)
node _activated_wdata_e_act_raw_out_sig_T_47 = cat(_activated_wdata_e_act_raw_out_sig_T_45, _activated_wdata_e_act_raw_out_sig_T_46)
connect activated_wdata_e_act_raw_11.sig, _activated_wdata_e_act_raw_out_sig_T_47
wire activated_wdata_e_act_result_11 : { bits : UInt<32>}
node _activated_wdata_e_act_result_bits_T_33 = eq(activated_wdata_e_act_raw_11.isZero, UInt<1>(0h0))
node _activated_wdata_e_act_result_bits_T_34 = and(_activated_wdata_e_act_result_bits_T_33, activated_wdata_e_act_raw_11.sign)
node _activated_wdata_e_act_result_bits_T_35 = mux(_activated_wdata_e_act_result_bits_T_34, UInt<1>(0h0), activated_wdata_e_clipped_11.bits)
connect activated_wdata_e_act_result_11.bits, _activated_wdata_e_act_result_bits_T_35
node activated_wdata_e_act_11 = mux(_activated_wdata_e_act_T_11, activated_wdata_e_act_result_11, activated_wdata_e_clipped_11)
wire _activated_wdata_WIRE_11 : { bits : UInt<32>}[1]
connect _activated_wdata_WIRE_11[0], activated_wdata_e_act_11
wire activated_wdata_2 : { bits : UInt<32>}[1][4]
connect activated_wdata_2[0], _activated_wdata_WIRE_8
connect activated_wdata_2[1], _activated_wdata_WIRE_9
connect activated_wdata_2[2], _activated_wdata_WIRE_10
connect activated_wdata_2[3], _activated_wdata_WIRE_11
node _io_srams_write_2_en_T = eq(w_bank, UInt<2>(0h2))
node _io_srams_write_2_en_T_1 = and(start_array_outputting, _io_srams_write_2_en_T)
node _io_srams_write_2_en_T_2 = eq(w_address.is_acc_addr, UInt<1>(0h0))
node _io_srams_write_2_en_T_3 = and(_io_srams_write_2_en_T_1, _io_srams_write_2_en_T_2)
node _io_srams_write_2_en_T_4 = eq(is_garbage_addr, UInt<1>(0h0))
node _io_srams_write_2_en_T_5 = and(_io_srams_write_2_en_T_3, _io_srams_write_2_en_T_4)
node _io_srams_write_2_en_T_6 = and(_io_srams_write_2_en_T_5, write_this_row)
connect io.srams.write[2].en, _io_srams_write_2_en_T_6
connect io.srams.write[2].addr, w_row
node io_srams_write_2_data_lo = cat(activated_wdata_2[1][0].bits, activated_wdata_2[0][0].bits)
node io_srams_write_2_data_hi = cat(activated_wdata_2[3][0].bits, activated_wdata_2[2][0].bits)
node _io_srams_write_2_data_T = cat(io_srams_write_2_data_hi, io_srams_write_2_data_lo)
connect io.srams.write[2].data, _io_srams_write_2_data_T
connect io.srams.write[2].mask[0], w_mask_0
connect io.srams.write[2].mask[1], w_mask_0
connect io.srams.write[2].mask[2], w_mask_0
connect io.srams.write[2].mask[3], w_mask_0
connect io.srams.write[2].mask[4], w_mask_1
connect io.srams.write[2].mask[5], w_mask_1
connect io.srams.write[2].mask[6], w_mask_1
connect io.srams.write[2].mask[7], w_mask_1
connect io.srams.write[2].mask[8], w_mask_2
connect io.srams.write[2].mask[9], w_mask_2
connect io.srams.write[2].mask[10], w_mask_2
connect io.srams.write[2].mask[11], w_mask_2
connect io.srams.write[2].mask[12], w_mask_3
connect io.srams.write[2].mask[13], w_mask_3
connect io.srams.write[2].mask[14], w_mask_3
connect io.srams.write[2].mask[15], w_mask_3
node activated_wdata_e_clipped_self_rec_rawIn_sign_12 = bits(mesh.io.resp.bits.data[0][0].bits, 31, 31)
node activated_wdata_e_clipped_self_rec_rawIn_expIn_12 = bits(mesh.io.resp.bits.data[0][0].bits, 30, 23)
node activated_wdata_e_clipped_self_rec_rawIn_fractIn_12 = bits(mesh.io.resp.bits.data[0][0].bits, 22, 0)
node activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_12 = eq(activated_wdata_e_clipped_self_rec_rawIn_expIn_12, UInt<1>(0h0))
node activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_12 = eq(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_528 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 0, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_529 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 1, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_530 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 2, 2)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_531 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 3, 3)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_532 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 4, 4)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_533 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 5, 5)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_534 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 6, 6)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_535 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 7, 7)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_536 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 8, 8)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_537 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 9, 9)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_538 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 10, 10)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_539 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 11, 11)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_540 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 12, 12)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_541 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 13, 13)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_542 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 14, 14)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_543 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 15, 15)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_544 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 16, 16)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_545 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 17, 17)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_546 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 18, 18)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_547 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 19, 19)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_548 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 20, 20)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_549 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 21, 21)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_550 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, 22, 22)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_551 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_529, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_552 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_530, UInt<5>(0h14), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_551)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_553 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_531, UInt<5>(0h13), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_552)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_554 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_532, UInt<5>(0h12), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_553)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_555 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_533, UInt<5>(0h11), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_554)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_556 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_534, UInt<5>(0h10), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_555)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_557 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_535, UInt<4>(0hf), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_556)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_558 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_536, UInt<4>(0he), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_557)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_559 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_537, UInt<4>(0hd), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_558)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_560 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_538, UInt<4>(0hc), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_559)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_561 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_539, UInt<4>(0hb), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_560)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_562 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_540, UInt<4>(0ha), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_561)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_563 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_541, UInt<4>(0h9), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_562)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_564 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_542, UInt<4>(0h8), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_563)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_565 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_543, UInt<3>(0h7), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_564)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_566 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_544, UInt<3>(0h6), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_565)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_567 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_545, UInt<3>(0h5), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_566)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_568 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_546, UInt<3>(0h4), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_567)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_569 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_547, UInt<2>(0h3), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_568)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_570 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_548, UInt<2>(0h2), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_569)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_571 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_549, UInt<1>(0h1), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_570)
node activated_wdata_e_clipped_self_rec_rawIn_normDist_12 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_550, UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_571)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_24 = dshl(activated_wdata_e_clipped_self_rec_rawIn_fractIn_12, activated_wdata_e_clipped_self_rec_rawIn_normDist_12)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_25 = bits(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_24, 21, 0)
node activated_wdata_e_clipped_self_rec_rawIn_subnormFract_12 = shl(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_25, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_60 = xor(activated_wdata_e_clipped_self_rec_rawIn_normDist_12, UInt<9>(0h1ff))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_61 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_12, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_60, activated_wdata_e_clipped_self_rec_rawIn_expIn_12)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_62 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_12, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_63 = or(UInt<8>(0h80), _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_62)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_64 = add(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_61, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_63)
node activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_12 = tail(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_64, 1)
node activated_wdata_e_clipped_self_rec_rawIn_isZero_12 = and(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_12, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_12)
node _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_12 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_12, 8, 7)
node activated_wdata_e_clipped_self_rec_rawIn_isSpecial_12 = eq(_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_12, UInt<2>(0h3))
wire activated_wdata_e_clipped_self_rec_rawIn_12 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_24 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_12, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_25 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_12, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_24)
connect activated_wdata_e_clipped_self_rec_rawIn_12.isNaN, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_25
node _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_12 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_12, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_12)
connect activated_wdata_e_clipped_self_rec_rawIn_12.isInf, _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_12
connect activated_wdata_e_clipped_self_rec_rawIn_12.isZero, activated_wdata_e_clipped_self_rec_rawIn_isZero_12
connect activated_wdata_e_clipped_self_rec_rawIn_12.sign, activated_wdata_e_clipped_self_rec_rawIn_sign_12
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_24 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_12, 8, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_25 = cvt(_activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_24)
connect activated_wdata_e_clipped_self_rec_rawIn_12.sExp, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_25
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_48 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZero_12, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_49 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_48)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_50 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_12, activated_wdata_e_clipped_self_rec_rawIn_subnormFract_12, activated_wdata_e_clipped_self_rec_rawIn_fractIn_12)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_51 = cat(_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_49, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_50)
connect activated_wdata_e_clipped_self_rec_rawIn_12.sig, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_51
node _activated_wdata_e_clipped_self_rec_T_96 = bits(activated_wdata_e_clipped_self_rec_rawIn_12.sExp, 8, 6)
node _activated_wdata_e_clipped_self_rec_T_97 = mux(activated_wdata_e_clipped_self_rec_rawIn_12.isZero, UInt<3>(0h0), _activated_wdata_e_clipped_self_rec_T_96)
node _activated_wdata_e_clipped_self_rec_T_98 = mux(activated_wdata_e_clipped_self_rec_rawIn_12.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_T_99 = or(_activated_wdata_e_clipped_self_rec_T_97, _activated_wdata_e_clipped_self_rec_T_98)
node _activated_wdata_e_clipped_self_rec_T_100 = cat(activated_wdata_e_clipped_self_rec_rawIn_12.sign, _activated_wdata_e_clipped_self_rec_T_99)
node _activated_wdata_e_clipped_self_rec_T_101 = bits(activated_wdata_e_clipped_self_rec_rawIn_12.sExp, 5, 0)
node _activated_wdata_e_clipped_self_rec_T_102 = cat(_activated_wdata_e_clipped_self_rec_T_100, _activated_wdata_e_clipped_self_rec_T_101)
node _activated_wdata_e_clipped_self_rec_T_103 = bits(activated_wdata_e_clipped_self_rec_rawIn_12.sig, 22, 0)
node activated_wdata_e_clipped_self_rec_12 = cat(_activated_wdata_e_clipped_self_rec_T_102, _activated_wdata_e_clipped_self_rec_T_103)
inst activated_wdata_e_clipped_resizer_12 of RecFNToRecFN_252
connect activated_wdata_e_clipped_resizer_12.io.in, activated_wdata_e_clipped_self_rec_12
connect activated_wdata_e_clipped_resizer_12.io.roundingMode, UInt<3>(0h0)
connect activated_wdata_e_clipped_resizer_12.io.detectTininess, UInt<1>(0h1)
wire activated_wdata_e_clipped_12 : { bits : UInt<32>}
node activated_wdata_e_clipped_result_bits_rawIn_exp_12 = bits(activated_wdata_e_clipped_resizer_12.io.out, 31, 23)
node _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_12 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_12, 8, 6)
node activated_wdata_e_clipped_result_bits_rawIn_isZero_12 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isZero_T_12, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_12 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_12, 8, 7)
node activated_wdata_e_clipped_result_bits_rawIn_isSpecial_12 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_12, UInt<2>(0h3))
wire activated_wdata_e_clipped_result_bits_rawIn_12 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_24 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_12, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_25 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_12, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_24)
connect activated_wdata_e_clipped_result_bits_rawIn_12.isNaN, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_25
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_36 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_12, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_37 = eq(_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_36, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_38 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_12, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_37)
connect activated_wdata_e_clipped_result_bits_rawIn_12.isInf, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_38
connect activated_wdata_e_clipped_result_bits_rawIn_12.isZero, activated_wdata_e_clipped_result_bits_rawIn_isZero_12
node _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_12 = bits(activated_wdata_e_clipped_resizer_12.io.out, 32, 32)
connect activated_wdata_e_clipped_result_bits_rawIn_12.sign, _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_12
node _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_12 = cvt(activated_wdata_e_clipped_result_bits_rawIn_exp_12)
connect activated_wdata_e_clipped_result_bits_rawIn_12.sExp, _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_12
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_48 = eq(activated_wdata_e_clipped_result_bits_rawIn_isZero_12, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_49 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_48)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_50 = bits(activated_wdata_e_clipped_resizer_12.io.out, 22, 0)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_51 = cat(_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_49, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_50)
connect activated_wdata_e_clipped_result_bits_rawIn_12.sig, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_51
node activated_wdata_e_clipped_result_bits_isSubnormal_12 = lt(activated_wdata_e_clipped_result_bits_rawIn_12.sExp, asSInt(UInt<9>(0h82)))
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_24 = bits(activated_wdata_e_clipped_result_bits_rawIn_12.sExp, 4, 0)
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_25 = sub(UInt<1>(0h1), _activated_wdata_e_clipped_result_bits_denormShiftDist_T_24)
node activated_wdata_e_clipped_result_bits_denormShiftDist_12 = tail(_activated_wdata_e_clipped_result_bits_denormShiftDist_T_25, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_24 = shr(activated_wdata_e_clipped_result_bits_rawIn_12.sig, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_25 = dshr(_activated_wdata_e_clipped_result_bits_denormFract_T_24, activated_wdata_e_clipped_result_bits_denormShiftDist_12)
node activated_wdata_e_clipped_result_bits_denormFract_12 = bits(_activated_wdata_e_clipped_result_bits_denormFract_T_25, 22, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_72 = bits(activated_wdata_e_clipped_result_bits_rawIn_12.sExp, 7, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_73 = sub(_activated_wdata_e_clipped_result_bits_expOut_T_72, UInt<8>(0h81))
node _activated_wdata_e_clipped_result_bits_expOut_T_74 = tail(_activated_wdata_e_clipped_result_bits_expOut_T_73, 1)
node _activated_wdata_e_clipped_result_bits_expOut_T_75 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_12, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_expOut_T_74)
node _activated_wdata_e_clipped_result_bits_expOut_T_76 = or(activated_wdata_e_clipped_result_bits_rawIn_12.isNaN, activated_wdata_e_clipped_result_bits_rawIn_12.isInf)
node _activated_wdata_e_clipped_result_bits_expOut_T_77 = mux(_activated_wdata_e_clipped_result_bits_expOut_T_76, UInt<8>(0hff), UInt<8>(0h0))
node activated_wdata_e_clipped_result_bits_expOut_12 = or(_activated_wdata_e_clipped_result_bits_expOut_T_75, _activated_wdata_e_clipped_result_bits_expOut_T_77)
node _activated_wdata_e_clipped_result_bits_fractOut_T_24 = bits(activated_wdata_e_clipped_result_bits_rawIn_12.sig, 22, 0)
node _activated_wdata_e_clipped_result_bits_fractOut_T_25 = mux(activated_wdata_e_clipped_result_bits_rawIn_12.isInf, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_fractOut_T_24)
node activated_wdata_e_clipped_result_bits_fractOut_12 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_12, activated_wdata_e_clipped_result_bits_denormFract_12, _activated_wdata_e_clipped_result_bits_fractOut_T_25)
node activated_wdata_e_clipped_result_bits_hi_12 = cat(activated_wdata_e_clipped_result_bits_rawIn_12.sign, activated_wdata_e_clipped_result_bits_expOut_12)
node _activated_wdata_e_clipped_result_bits_T_12 = cat(activated_wdata_e_clipped_result_bits_hi_12, activated_wdata_e_clipped_result_bits_fractOut_12)
connect activated_wdata_e_clipped_12.bits, _activated_wdata_e_clipped_result_bits_T_12
node _activated_wdata_e_act_T_12 = eq(activation, UInt<1>(0h1))
node activated_wdata_e_act_raw_sign_12 = bits(activated_wdata_e_clipped_12.bits, 31, 31)
node activated_wdata_e_act_raw_expIn_12 = bits(activated_wdata_e_clipped_12.bits, 30, 23)
node activated_wdata_e_act_raw_fractIn_12 = bits(activated_wdata_e_clipped_12.bits, 22, 0)
node activated_wdata_e_act_raw_isZeroExpIn_12 = eq(activated_wdata_e_act_raw_expIn_12, UInt<1>(0h0))
node activated_wdata_e_act_raw_isZeroFractIn_12 = eq(activated_wdata_e_act_raw_fractIn_12, UInt<1>(0h0))
node _activated_wdata_e_act_raw_normDist_T_528 = bits(activated_wdata_e_act_raw_fractIn_12, 0, 0)
node _activated_wdata_e_act_raw_normDist_T_529 = bits(activated_wdata_e_act_raw_fractIn_12, 1, 1)
node _activated_wdata_e_act_raw_normDist_T_530 = bits(activated_wdata_e_act_raw_fractIn_12, 2, 2)
node _activated_wdata_e_act_raw_normDist_T_531 = bits(activated_wdata_e_act_raw_fractIn_12, 3, 3)
node _activated_wdata_e_act_raw_normDist_T_532 = bits(activated_wdata_e_act_raw_fractIn_12, 4, 4)
node _activated_wdata_e_act_raw_normDist_T_533 = bits(activated_wdata_e_act_raw_fractIn_12, 5, 5)
node _activated_wdata_e_act_raw_normDist_T_534 = bits(activated_wdata_e_act_raw_fractIn_12, 6, 6)
node _activated_wdata_e_act_raw_normDist_T_535 = bits(activated_wdata_e_act_raw_fractIn_12, 7, 7)
node _activated_wdata_e_act_raw_normDist_T_536 = bits(activated_wdata_e_act_raw_fractIn_12, 8, 8)
node _activated_wdata_e_act_raw_normDist_T_537 = bits(activated_wdata_e_act_raw_fractIn_12, 9, 9)
node _activated_wdata_e_act_raw_normDist_T_538 = bits(activated_wdata_e_act_raw_fractIn_12, 10, 10)
node _activated_wdata_e_act_raw_normDist_T_539 = bits(activated_wdata_e_act_raw_fractIn_12, 11, 11)
node _activated_wdata_e_act_raw_normDist_T_540 = bits(activated_wdata_e_act_raw_fractIn_12, 12, 12)
node _activated_wdata_e_act_raw_normDist_T_541 = bits(activated_wdata_e_act_raw_fractIn_12, 13, 13)
node _activated_wdata_e_act_raw_normDist_T_542 = bits(activated_wdata_e_act_raw_fractIn_12, 14, 14)
node _activated_wdata_e_act_raw_normDist_T_543 = bits(activated_wdata_e_act_raw_fractIn_12, 15, 15)
node _activated_wdata_e_act_raw_normDist_T_544 = bits(activated_wdata_e_act_raw_fractIn_12, 16, 16)
node _activated_wdata_e_act_raw_normDist_T_545 = bits(activated_wdata_e_act_raw_fractIn_12, 17, 17)
node _activated_wdata_e_act_raw_normDist_T_546 = bits(activated_wdata_e_act_raw_fractIn_12, 18, 18)
node _activated_wdata_e_act_raw_normDist_T_547 = bits(activated_wdata_e_act_raw_fractIn_12, 19, 19)
node _activated_wdata_e_act_raw_normDist_T_548 = bits(activated_wdata_e_act_raw_fractIn_12, 20, 20)
node _activated_wdata_e_act_raw_normDist_T_549 = bits(activated_wdata_e_act_raw_fractIn_12, 21, 21)
node _activated_wdata_e_act_raw_normDist_T_550 = bits(activated_wdata_e_act_raw_fractIn_12, 22, 22)
node _activated_wdata_e_act_raw_normDist_T_551 = mux(_activated_wdata_e_act_raw_normDist_T_529, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_act_raw_normDist_T_552 = mux(_activated_wdata_e_act_raw_normDist_T_530, UInt<5>(0h14), _activated_wdata_e_act_raw_normDist_T_551)
node _activated_wdata_e_act_raw_normDist_T_553 = mux(_activated_wdata_e_act_raw_normDist_T_531, UInt<5>(0h13), _activated_wdata_e_act_raw_normDist_T_552)
node _activated_wdata_e_act_raw_normDist_T_554 = mux(_activated_wdata_e_act_raw_normDist_T_532, UInt<5>(0h12), _activated_wdata_e_act_raw_normDist_T_553)
node _activated_wdata_e_act_raw_normDist_T_555 = mux(_activated_wdata_e_act_raw_normDist_T_533, UInt<5>(0h11), _activated_wdata_e_act_raw_normDist_T_554)
node _activated_wdata_e_act_raw_normDist_T_556 = mux(_activated_wdata_e_act_raw_normDist_T_534, UInt<5>(0h10), _activated_wdata_e_act_raw_normDist_T_555)
node _activated_wdata_e_act_raw_normDist_T_557 = mux(_activated_wdata_e_act_raw_normDist_T_535, UInt<4>(0hf), _activated_wdata_e_act_raw_normDist_T_556)
node _activated_wdata_e_act_raw_normDist_T_558 = mux(_activated_wdata_e_act_raw_normDist_T_536, UInt<4>(0he), _activated_wdata_e_act_raw_normDist_T_557)
node _activated_wdata_e_act_raw_normDist_T_559 = mux(_activated_wdata_e_act_raw_normDist_T_537, UInt<4>(0hd), _activated_wdata_e_act_raw_normDist_T_558)
node _activated_wdata_e_act_raw_normDist_T_560 = mux(_activated_wdata_e_act_raw_normDist_T_538, UInt<4>(0hc), _activated_wdata_e_act_raw_normDist_T_559)
node _activated_wdata_e_act_raw_normDist_T_561 = mux(_activated_wdata_e_act_raw_normDist_T_539, UInt<4>(0hb), _activated_wdata_e_act_raw_normDist_T_560)
node _activated_wdata_e_act_raw_normDist_T_562 = mux(_activated_wdata_e_act_raw_normDist_T_540, UInt<4>(0ha), _activated_wdata_e_act_raw_normDist_T_561)
node _activated_wdata_e_act_raw_normDist_T_563 = mux(_activated_wdata_e_act_raw_normDist_T_541, UInt<4>(0h9), _activated_wdata_e_act_raw_normDist_T_562)
node _activated_wdata_e_act_raw_normDist_T_564 = mux(_activated_wdata_e_act_raw_normDist_T_542, UInt<4>(0h8), _activated_wdata_e_act_raw_normDist_T_563)
node _activated_wdata_e_act_raw_normDist_T_565 = mux(_activated_wdata_e_act_raw_normDist_T_543, UInt<3>(0h7), _activated_wdata_e_act_raw_normDist_T_564)
node _activated_wdata_e_act_raw_normDist_T_566 = mux(_activated_wdata_e_act_raw_normDist_T_544, UInt<3>(0h6), _activated_wdata_e_act_raw_normDist_T_565)
node _activated_wdata_e_act_raw_normDist_T_567 = mux(_activated_wdata_e_act_raw_normDist_T_545, UInt<3>(0h5), _activated_wdata_e_act_raw_normDist_T_566)
node _activated_wdata_e_act_raw_normDist_T_568 = mux(_activated_wdata_e_act_raw_normDist_T_546, UInt<3>(0h4), _activated_wdata_e_act_raw_normDist_T_567)
node _activated_wdata_e_act_raw_normDist_T_569 = mux(_activated_wdata_e_act_raw_normDist_T_547, UInt<2>(0h3), _activated_wdata_e_act_raw_normDist_T_568)
node _activated_wdata_e_act_raw_normDist_T_570 = mux(_activated_wdata_e_act_raw_normDist_T_548, UInt<2>(0h2), _activated_wdata_e_act_raw_normDist_T_569)
node _activated_wdata_e_act_raw_normDist_T_571 = mux(_activated_wdata_e_act_raw_normDist_T_549, UInt<1>(0h1), _activated_wdata_e_act_raw_normDist_T_570)
node activated_wdata_e_act_raw_normDist_12 = mux(_activated_wdata_e_act_raw_normDist_T_550, UInt<1>(0h0), _activated_wdata_e_act_raw_normDist_T_571)
node _activated_wdata_e_act_raw_subnormFract_T_24 = dshl(activated_wdata_e_act_raw_fractIn_12, activated_wdata_e_act_raw_normDist_12)
node _activated_wdata_e_act_raw_subnormFract_T_25 = bits(_activated_wdata_e_act_raw_subnormFract_T_24, 21, 0)
node activated_wdata_e_act_raw_subnormFract_12 = shl(_activated_wdata_e_act_raw_subnormFract_T_25, 1)
node _activated_wdata_e_act_raw_adjustedExp_T_60 = xor(activated_wdata_e_act_raw_normDist_12, UInt<9>(0h1ff))
node _activated_wdata_e_act_raw_adjustedExp_T_61 = mux(activated_wdata_e_act_raw_isZeroExpIn_12, _activated_wdata_e_act_raw_adjustedExp_T_60, activated_wdata_e_act_raw_expIn_12)
node _activated_wdata_e_act_raw_adjustedExp_T_62 = mux(activated_wdata_e_act_raw_isZeroExpIn_12, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_act_raw_adjustedExp_T_63 = or(UInt<8>(0h80), _activated_wdata_e_act_raw_adjustedExp_T_62)
node _activated_wdata_e_act_raw_adjustedExp_T_64 = add(_activated_wdata_e_act_raw_adjustedExp_T_61, _activated_wdata_e_act_raw_adjustedExp_T_63)
node activated_wdata_e_act_raw_adjustedExp_12 = tail(_activated_wdata_e_act_raw_adjustedExp_T_64, 1)
node activated_wdata_e_act_raw_isZero_12 = and(activated_wdata_e_act_raw_isZeroExpIn_12, activated_wdata_e_act_raw_isZeroFractIn_12)
node _activated_wdata_e_act_raw_isSpecial_T_12 = bits(activated_wdata_e_act_raw_adjustedExp_12, 8, 7)
node activated_wdata_e_act_raw_isSpecial_12 = eq(_activated_wdata_e_act_raw_isSpecial_T_12, UInt<2>(0h3))
wire activated_wdata_e_act_raw_12 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_act_raw_out_isNaN_T_24 = eq(activated_wdata_e_act_raw_isZeroFractIn_12, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_isNaN_T_25 = and(activated_wdata_e_act_raw_isSpecial_12, _activated_wdata_e_act_raw_out_isNaN_T_24)
connect activated_wdata_e_act_raw_12.isNaN, _activated_wdata_e_act_raw_out_isNaN_T_25
node _activated_wdata_e_act_raw_out_isInf_T_12 = and(activated_wdata_e_act_raw_isSpecial_12, activated_wdata_e_act_raw_isZeroFractIn_12)
connect activated_wdata_e_act_raw_12.isInf, _activated_wdata_e_act_raw_out_isInf_T_12
connect activated_wdata_e_act_raw_12.isZero, activated_wdata_e_act_raw_isZero_12
connect activated_wdata_e_act_raw_12.sign, activated_wdata_e_act_raw_sign_12
node _activated_wdata_e_act_raw_out_sExp_T_24 = bits(activated_wdata_e_act_raw_adjustedExp_12, 8, 0)
node _activated_wdata_e_act_raw_out_sExp_T_25 = cvt(_activated_wdata_e_act_raw_out_sExp_T_24)
connect activated_wdata_e_act_raw_12.sExp, _activated_wdata_e_act_raw_out_sExp_T_25
node _activated_wdata_e_act_raw_out_sig_T_48 = eq(activated_wdata_e_act_raw_isZero_12, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_sig_T_49 = cat(UInt<1>(0h0), _activated_wdata_e_act_raw_out_sig_T_48)
node _activated_wdata_e_act_raw_out_sig_T_50 = mux(activated_wdata_e_act_raw_isZeroExpIn_12, activated_wdata_e_act_raw_subnormFract_12, activated_wdata_e_act_raw_fractIn_12)
node _activated_wdata_e_act_raw_out_sig_T_51 = cat(_activated_wdata_e_act_raw_out_sig_T_49, _activated_wdata_e_act_raw_out_sig_T_50)
connect activated_wdata_e_act_raw_12.sig, _activated_wdata_e_act_raw_out_sig_T_51
wire activated_wdata_e_act_result_12 : { bits : UInt<32>}
node _activated_wdata_e_act_result_bits_T_36 = eq(activated_wdata_e_act_raw_12.isZero, UInt<1>(0h0))
node _activated_wdata_e_act_result_bits_T_37 = and(_activated_wdata_e_act_result_bits_T_36, activated_wdata_e_act_raw_12.sign)
node _activated_wdata_e_act_result_bits_T_38 = mux(_activated_wdata_e_act_result_bits_T_37, UInt<1>(0h0), activated_wdata_e_clipped_12.bits)
connect activated_wdata_e_act_result_12.bits, _activated_wdata_e_act_result_bits_T_38
node activated_wdata_e_act_12 = mux(_activated_wdata_e_act_T_12, activated_wdata_e_act_result_12, activated_wdata_e_clipped_12)
wire _activated_wdata_WIRE_12 : { bits : UInt<32>}[1]
connect _activated_wdata_WIRE_12[0], activated_wdata_e_act_12
node activated_wdata_e_clipped_self_rec_rawIn_sign_13 = bits(mesh.io.resp.bits.data[1][0].bits, 31, 31)
node activated_wdata_e_clipped_self_rec_rawIn_expIn_13 = bits(mesh.io.resp.bits.data[1][0].bits, 30, 23)
node activated_wdata_e_clipped_self_rec_rawIn_fractIn_13 = bits(mesh.io.resp.bits.data[1][0].bits, 22, 0)
node activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_13 = eq(activated_wdata_e_clipped_self_rec_rawIn_expIn_13, UInt<1>(0h0))
node activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_13 = eq(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_572 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 0, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_573 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 1, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_574 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 2, 2)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_575 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 3, 3)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_576 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 4, 4)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_577 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 5, 5)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_578 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 6, 6)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_579 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 7, 7)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_580 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 8, 8)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_581 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 9, 9)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_582 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 10, 10)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_583 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 11, 11)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_584 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 12, 12)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_585 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 13, 13)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_586 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 14, 14)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_587 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 15, 15)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_588 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 16, 16)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_589 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 17, 17)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_590 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 18, 18)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_591 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 19, 19)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_592 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 20, 20)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_593 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 21, 21)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_594 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, 22, 22)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_595 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_573, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_596 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_574, UInt<5>(0h14), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_595)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_597 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_575, UInt<5>(0h13), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_596)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_598 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_576, UInt<5>(0h12), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_597)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_599 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_577, UInt<5>(0h11), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_598)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_600 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_578, UInt<5>(0h10), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_599)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_601 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_579, UInt<4>(0hf), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_600)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_602 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_580, UInt<4>(0he), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_601)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_603 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_581, UInt<4>(0hd), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_602)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_604 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_582, UInt<4>(0hc), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_603)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_605 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_583, UInt<4>(0hb), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_604)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_606 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_584, UInt<4>(0ha), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_605)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_607 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_585, UInt<4>(0h9), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_606)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_608 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_586, UInt<4>(0h8), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_607)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_609 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_587, UInt<3>(0h7), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_608)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_610 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_588, UInt<3>(0h6), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_609)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_611 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_589, UInt<3>(0h5), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_610)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_612 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_590, UInt<3>(0h4), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_611)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_613 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_591, UInt<2>(0h3), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_612)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_614 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_592, UInt<2>(0h2), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_613)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_615 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_593, UInt<1>(0h1), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_614)
node activated_wdata_e_clipped_self_rec_rawIn_normDist_13 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_594, UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_615)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_26 = dshl(activated_wdata_e_clipped_self_rec_rawIn_fractIn_13, activated_wdata_e_clipped_self_rec_rawIn_normDist_13)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_27 = bits(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_26, 21, 0)
node activated_wdata_e_clipped_self_rec_rawIn_subnormFract_13 = shl(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_27, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_65 = xor(activated_wdata_e_clipped_self_rec_rawIn_normDist_13, UInt<9>(0h1ff))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_66 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_13, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_65, activated_wdata_e_clipped_self_rec_rawIn_expIn_13)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_67 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_13, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_68 = or(UInt<8>(0h80), _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_67)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_69 = add(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_66, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_68)
node activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_13 = tail(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_69, 1)
node activated_wdata_e_clipped_self_rec_rawIn_isZero_13 = and(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_13, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_13)
node _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_13 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_13, 8, 7)
node activated_wdata_e_clipped_self_rec_rawIn_isSpecial_13 = eq(_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_13, UInt<2>(0h3))
wire activated_wdata_e_clipped_self_rec_rawIn_13 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_26 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_13, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_27 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_13, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_26)
connect activated_wdata_e_clipped_self_rec_rawIn_13.isNaN, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_27
node _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_13 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_13, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_13)
connect activated_wdata_e_clipped_self_rec_rawIn_13.isInf, _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_13
connect activated_wdata_e_clipped_self_rec_rawIn_13.isZero, activated_wdata_e_clipped_self_rec_rawIn_isZero_13
connect activated_wdata_e_clipped_self_rec_rawIn_13.sign, activated_wdata_e_clipped_self_rec_rawIn_sign_13
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_26 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_13, 8, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_27 = cvt(_activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_26)
connect activated_wdata_e_clipped_self_rec_rawIn_13.sExp, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_27
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_52 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZero_13, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_53 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_52)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_54 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_13, activated_wdata_e_clipped_self_rec_rawIn_subnormFract_13, activated_wdata_e_clipped_self_rec_rawIn_fractIn_13)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_55 = cat(_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_53, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_54)
connect activated_wdata_e_clipped_self_rec_rawIn_13.sig, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_55
node _activated_wdata_e_clipped_self_rec_T_104 = bits(activated_wdata_e_clipped_self_rec_rawIn_13.sExp, 8, 6)
node _activated_wdata_e_clipped_self_rec_T_105 = mux(activated_wdata_e_clipped_self_rec_rawIn_13.isZero, UInt<3>(0h0), _activated_wdata_e_clipped_self_rec_T_104)
node _activated_wdata_e_clipped_self_rec_T_106 = mux(activated_wdata_e_clipped_self_rec_rawIn_13.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_T_107 = or(_activated_wdata_e_clipped_self_rec_T_105, _activated_wdata_e_clipped_self_rec_T_106)
node _activated_wdata_e_clipped_self_rec_T_108 = cat(activated_wdata_e_clipped_self_rec_rawIn_13.sign, _activated_wdata_e_clipped_self_rec_T_107)
node _activated_wdata_e_clipped_self_rec_T_109 = bits(activated_wdata_e_clipped_self_rec_rawIn_13.sExp, 5, 0)
node _activated_wdata_e_clipped_self_rec_T_110 = cat(_activated_wdata_e_clipped_self_rec_T_108, _activated_wdata_e_clipped_self_rec_T_109)
node _activated_wdata_e_clipped_self_rec_T_111 = bits(activated_wdata_e_clipped_self_rec_rawIn_13.sig, 22, 0)
node activated_wdata_e_clipped_self_rec_13 = cat(_activated_wdata_e_clipped_self_rec_T_110, _activated_wdata_e_clipped_self_rec_T_111)
inst activated_wdata_e_clipped_resizer_13 of RecFNToRecFN_253
connect activated_wdata_e_clipped_resizer_13.io.in, activated_wdata_e_clipped_self_rec_13
connect activated_wdata_e_clipped_resizer_13.io.roundingMode, UInt<3>(0h0)
connect activated_wdata_e_clipped_resizer_13.io.detectTininess, UInt<1>(0h1)
wire activated_wdata_e_clipped_13 : { bits : UInt<32>}
node activated_wdata_e_clipped_result_bits_rawIn_exp_13 = bits(activated_wdata_e_clipped_resizer_13.io.out, 31, 23)
node _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_13 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_13, 8, 6)
node activated_wdata_e_clipped_result_bits_rawIn_isZero_13 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isZero_T_13, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_13 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_13, 8, 7)
node activated_wdata_e_clipped_result_bits_rawIn_isSpecial_13 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_13, UInt<2>(0h3))
wire activated_wdata_e_clipped_result_bits_rawIn_13 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_26 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_13, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_27 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_13, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_26)
connect activated_wdata_e_clipped_result_bits_rawIn_13.isNaN, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_27
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_39 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_13, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_40 = eq(_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_39, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_41 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_13, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_40)
connect activated_wdata_e_clipped_result_bits_rawIn_13.isInf, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_41
connect activated_wdata_e_clipped_result_bits_rawIn_13.isZero, activated_wdata_e_clipped_result_bits_rawIn_isZero_13
node _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_13 = bits(activated_wdata_e_clipped_resizer_13.io.out, 32, 32)
connect activated_wdata_e_clipped_result_bits_rawIn_13.sign, _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_13
node _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_13 = cvt(activated_wdata_e_clipped_result_bits_rawIn_exp_13)
connect activated_wdata_e_clipped_result_bits_rawIn_13.sExp, _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_13
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_52 = eq(activated_wdata_e_clipped_result_bits_rawIn_isZero_13, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_53 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_52)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_54 = bits(activated_wdata_e_clipped_resizer_13.io.out, 22, 0)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_55 = cat(_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_53, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_54)
connect activated_wdata_e_clipped_result_bits_rawIn_13.sig, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_55
node activated_wdata_e_clipped_result_bits_isSubnormal_13 = lt(activated_wdata_e_clipped_result_bits_rawIn_13.sExp, asSInt(UInt<9>(0h82)))
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_26 = bits(activated_wdata_e_clipped_result_bits_rawIn_13.sExp, 4, 0)
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_27 = sub(UInt<1>(0h1), _activated_wdata_e_clipped_result_bits_denormShiftDist_T_26)
node activated_wdata_e_clipped_result_bits_denormShiftDist_13 = tail(_activated_wdata_e_clipped_result_bits_denormShiftDist_T_27, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_26 = shr(activated_wdata_e_clipped_result_bits_rawIn_13.sig, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_27 = dshr(_activated_wdata_e_clipped_result_bits_denormFract_T_26, activated_wdata_e_clipped_result_bits_denormShiftDist_13)
node activated_wdata_e_clipped_result_bits_denormFract_13 = bits(_activated_wdata_e_clipped_result_bits_denormFract_T_27, 22, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_78 = bits(activated_wdata_e_clipped_result_bits_rawIn_13.sExp, 7, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_79 = sub(_activated_wdata_e_clipped_result_bits_expOut_T_78, UInt<8>(0h81))
node _activated_wdata_e_clipped_result_bits_expOut_T_80 = tail(_activated_wdata_e_clipped_result_bits_expOut_T_79, 1)
node _activated_wdata_e_clipped_result_bits_expOut_T_81 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_13, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_expOut_T_80)
node _activated_wdata_e_clipped_result_bits_expOut_T_82 = or(activated_wdata_e_clipped_result_bits_rawIn_13.isNaN, activated_wdata_e_clipped_result_bits_rawIn_13.isInf)
node _activated_wdata_e_clipped_result_bits_expOut_T_83 = mux(_activated_wdata_e_clipped_result_bits_expOut_T_82, UInt<8>(0hff), UInt<8>(0h0))
node activated_wdata_e_clipped_result_bits_expOut_13 = or(_activated_wdata_e_clipped_result_bits_expOut_T_81, _activated_wdata_e_clipped_result_bits_expOut_T_83)
node _activated_wdata_e_clipped_result_bits_fractOut_T_26 = bits(activated_wdata_e_clipped_result_bits_rawIn_13.sig, 22, 0)
node _activated_wdata_e_clipped_result_bits_fractOut_T_27 = mux(activated_wdata_e_clipped_result_bits_rawIn_13.isInf, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_fractOut_T_26)
node activated_wdata_e_clipped_result_bits_fractOut_13 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_13, activated_wdata_e_clipped_result_bits_denormFract_13, _activated_wdata_e_clipped_result_bits_fractOut_T_27)
node activated_wdata_e_clipped_result_bits_hi_13 = cat(activated_wdata_e_clipped_result_bits_rawIn_13.sign, activated_wdata_e_clipped_result_bits_expOut_13)
node _activated_wdata_e_clipped_result_bits_T_13 = cat(activated_wdata_e_clipped_result_bits_hi_13, activated_wdata_e_clipped_result_bits_fractOut_13)
connect activated_wdata_e_clipped_13.bits, _activated_wdata_e_clipped_result_bits_T_13
node _activated_wdata_e_act_T_13 = eq(activation, UInt<1>(0h1))
node activated_wdata_e_act_raw_sign_13 = bits(activated_wdata_e_clipped_13.bits, 31, 31)
node activated_wdata_e_act_raw_expIn_13 = bits(activated_wdata_e_clipped_13.bits, 30, 23)
node activated_wdata_e_act_raw_fractIn_13 = bits(activated_wdata_e_clipped_13.bits, 22, 0)
node activated_wdata_e_act_raw_isZeroExpIn_13 = eq(activated_wdata_e_act_raw_expIn_13, UInt<1>(0h0))
node activated_wdata_e_act_raw_isZeroFractIn_13 = eq(activated_wdata_e_act_raw_fractIn_13, UInt<1>(0h0))
node _activated_wdata_e_act_raw_normDist_T_572 = bits(activated_wdata_e_act_raw_fractIn_13, 0, 0)
node _activated_wdata_e_act_raw_normDist_T_573 = bits(activated_wdata_e_act_raw_fractIn_13, 1, 1)
node _activated_wdata_e_act_raw_normDist_T_574 = bits(activated_wdata_e_act_raw_fractIn_13, 2, 2)
node _activated_wdata_e_act_raw_normDist_T_575 = bits(activated_wdata_e_act_raw_fractIn_13, 3, 3)
node _activated_wdata_e_act_raw_normDist_T_576 = bits(activated_wdata_e_act_raw_fractIn_13, 4, 4)
node _activated_wdata_e_act_raw_normDist_T_577 = bits(activated_wdata_e_act_raw_fractIn_13, 5, 5)
node _activated_wdata_e_act_raw_normDist_T_578 = bits(activated_wdata_e_act_raw_fractIn_13, 6, 6)
node _activated_wdata_e_act_raw_normDist_T_579 = bits(activated_wdata_e_act_raw_fractIn_13, 7, 7)
node _activated_wdata_e_act_raw_normDist_T_580 = bits(activated_wdata_e_act_raw_fractIn_13, 8, 8)
node _activated_wdata_e_act_raw_normDist_T_581 = bits(activated_wdata_e_act_raw_fractIn_13, 9, 9)
node _activated_wdata_e_act_raw_normDist_T_582 = bits(activated_wdata_e_act_raw_fractIn_13, 10, 10)
node _activated_wdata_e_act_raw_normDist_T_583 = bits(activated_wdata_e_act_raw_fractIn_13, 11, 11)
node _activated_wdata_e_act_raw_normDist_T_584 = bits(activated_wdata_e_act_raw_fractIn_13, 12, 12)
node _activated_wdata_e_act_raw_normDist_T_585 = bits(activated_wdata_e_act_raw_fractIn_13, 13, 13)
node _activated_wdata_e_act_raw_normDist_T_586 = bits(activated_wdata_e_act_raw_fractIn_13, 14, 14)
node _activated_wdata_e_act_raw_normDist_T_587 = bits(activated_wdata_e_act_raw_fractIn_13, 15, 15)
node _activated_wdata_e_act_raw_normDist_T_588 = bits(activated_wdata_e_act_raw_fractIn_13, 16, 16)
node _activated_wdata_e_act_raw_normDist_T_589 = bits(activated_wdata_e_act_raw_fractIn_13, 17, 17)
node _activated_wdata_e_act_raw_normDist_T_590 = bits(activated_wdata_e_act_raw_fractIn_13, 18, 18)
node _activated_wdata_e_act_raw_normDist_T_591 = bits(activated_wdata_e_act_raw_fractIn_13, 19, 19)
node _activated_wdata_e_act_raw_normDist_T_592 = bits(activated_wdata_e_act_raw_fractIn_13, 20, 20)
node _activated_wdata_e_act_raw_normDist_T_593 = bits(activated_wdata_e_act_raw_fractIn_13, 21, 21)
node _activated_wdata_e_act_raw_normDist_T_594 = bits(activated_wdata_e_act_raw_fractIn_13, 22, 22)
node _activated_wdata_e_act_raw_normDist_T_595 = mux(_activated_wdata_e_act_raw_normDist_T_573, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_act_raw_normDist_T_596 = mux(_activated_wdata_e_act_raw_normDist_T_574, UInt<5>(0h14), _activated_wdata_e_act_raw_normDist_T_595)
node _activated_wdata_e_act_raw_normDist_T_597 = mux(_activated_wdata_e_act_raw_normDist_T_575, UInt<5>(0h13), _activated_wdata_e_act_raw_normDist_T_596)
node _activated_wdata_e_act_raw_normDist_T_598 = mux(_activated_wdata_e_act_raw_normDist_T_576, UInt<5>(0h12), _activated_wdata_e_act_raw_normDist_T_597)
node _activated_wdata_e_act_raw_normDist_T_599 = mux(_activated_wdata_e_act_raw_normDist_T_577, UInt<5>(0h11), _activated_wdata_e_act_raw_normDist_T_598)
node _activated_wdata_e_act_raw_normDist_T_600 = mux(_activated_wdata_e_act_raw_normDist_T_578, UInt<5>(0h10), _activated_wdata_e_act_raw_normDist_T_599)
node _activated_wdata_e_act_raw_normDist_T_601 = mux(_activated_wdata_e_act_raw_normDist_T_579, UInt<4>(0hf), _activated_wdata_e_act_raw_normDist_T_600)
node _activated_wdata_e_act_raw_normDist_T_602 = mux(_activated_wdata_e_act_raw_normDist_T_580, UInt<4>(0he), _activated_wdata_e_act_raw_normDist_T_601)
node _activated_wdata_e_act_raw_normDist_T_603 = mux(_activated_wdata_e_act_raw_normDist_T_581, UInt<4>(0hd), _activated_wdata_e_act_raw_normDist_T_602)
node _activated_wdata_e_act_raw_normDist_T_604 = mux(_activated_wdata_e_act_raw_normDist_T_582, UInt<4>(0hc), _activated_wdata_e_act_raw_normDist_T_603)
node _activated_wdata_e_act_raw_normDist_T_605 = mux(_activated_wdata_e_act_raw_normDist_T_583, UInt<4>(0hb), _activated_wdata_e_act_raw_normDist_T_604)
node _activated_wdata_e_act_raw_normDist_T_606 = mux(_activated_wdata_e_act_raw_normDist_T_584, UInt<4>(0ha), _activated_wdata_e_act_raw_normDist_T_605)
node _activated_wdata_e_act_raw_normDist_T_607 = mux(_activated_wdata_e_act_raw_normDist_T_585, UInt<4>(0h9), _activated_wdata_e_act_raw_normDist_T_606)
node _activated_wdata_e_act_raw_normDist_T_608 = mux(_activated_wdata_e_act_raw_normDist_T_586, UInt<4>(0h8), _activated_wdata_e_act_raw_normDist_T_607)
node _activated_wdata_e_act_raw_normDist_T_609 = mux(_activated_wdata_e_act_raw_normDist_T_587, UInt<3>(0h7), _activated_wdata_e_act_raw_normDist_T_608)
node _activated_wdata_e_act_raw_normDist_T_610 = mux(_activated_wdata_e_act_raw_normDist_T_588, UInt<3>(0h6), _activated_wdata_e_act_raw_normDist_T_609)
node _activated_wdata_e_act_raw_normDist_T_611 = mux(_activated_wdata_e_act_raw_normDist_T_589, UInt<3>(0h5), _activated_wdata_e_act_raw_normDist_T_610)
node _activated_wdata_e_act_raw_normDist_T_612 = mux(_activated_wdata_e_act_raw_normDist_T_590, UInt<3>(0h4), _activated_wdata_e_act_raw_normDist_T_611)
node _activated_wdata_e_act_raw_normDist_T_613 = mux(_activated_wdata_e_act_raw_normDist_T_591, UInt<2>(0h3), _activated_wdata_e_act_raw_normDist_T_612)
node _activated_wdata_e_act_raw_normDist_T_614 = mux(_activated_wdata_e_act_raw_normDist_T_592, UInt<2>(0h2), _activated_wdata_e_act_raw_normDist_T_613)
node _activated_wdata_e_act_raw_normDist_T_615 = mux(_activated_wdata_e_act_raw_normDist_T_593, UInt<1>(0h1), _activated_wdata_e_act_raw_normDist_T_614)
node activated_wdata_e_act_raw_normDist_13 = mux(_activated_wdata_e_act_raw_normDist_T_594, UInt<1>(0h0), _activated_wdata_e_act_raw_normDist_T_615)
node _activated_wdata_e_act_raw_subnormFract_T_26 = dshl(activated_wdata_e_act_raw_fractIn_13, activated_wdata_e_act_raw_normDist_13)
node _activated_wdata_e_act_raw_subnormFract_T_27 = bits(_activated_wdata_e_act_raw_subnormFract_T_26, 21, 0)
node activated_wdata_e_act_raw_subnormFract_13 = shl(_activated_wdata_e_act_raw_subnormFract_T_27, 1)
node _activated_wdata_e_act_raw_adjustedExp_T_65 = xor(activated_wdata_e_act_raw_normDist_13, UInt<9>(0h1ff))
node _activated_wdata_e_act_raw_adjustedExp_T_66 = mux(activated_wdata_e_act_raw_isZeroExpIn_13, _activated_wdata_e_act_raw_adjustedExp_T_65, activated_wdata_e_act_raw_expIn_13)
node _activated_wdata_e_act_raw_adjustedExp_T_67 = mux(activated_wdata_e_act_raw_isZeroExpIn_13, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_act_raw_adjustedExp_T_68 = or(UInt<8>(0h80), _activated_wdata_e_act_raw_adjustedExp_T_67)
node _activated_wdata_e_act_raw_adjustedExp_T_69 = add(_activated_wdata_e_act_raw_adjustedExp_T_66, _activated_wdata_e_act_raw_adjustedExp_T_68)
node activated_wdata_e_act_raw_adjustedExp_13 = tail(_activated_wdata_e_act_raw_adjustedExp_T_69, 1)
node activated_wdata_e_act_raw_isZero_13 = and(activated_wdata_e_act_raw_isZeroExpIn_13, activated_wdata_e_act_raw_isZeroFractIn_13)
node _activated_wdata_e_act_raw_isSpecial_T_13 = bits(activated_wdata_e_act_raw_adjustedExp_13, 8, 7)
node activated_wdata_e_act_raw_isSpecial_13 = eq(_activated_wdata_e_act_raw_isSpecial_T_13, UInt<2>(0h3))
wire activated_wdata_e_act_raw_13 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_act_raw_out_isNaN_T_26 = eq(activated_wdata_e_act_raw_isZeroFractIn_13, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_isNaN_T_27 = and(activated_wdata_e_act_raw_isSpecial_13, _activated_wdata_e_act_raw_out_isNaN_T_26)
connect activated_wdata_e_act_raw_13.isNaN, _activated_wdata_e_act_raw_out_isNaN_T_27
node _activated_wdata_e_act_raw_out_isInf_T_13 = and(activated_wdata_e_act_raw_isSpecial_13, activated_wdata_e_act_raw_isZeroFractIn_13)
connect activated_wdata_e_act_raw_13.isInf, _activated_wdata_e_act_raw_out_isInf_T_13
connect activated_wdata_e_act_raw_13.isZero, activated_wdata_e_act_raw_isZero_13
connect activated_wdata_e_act_raw_13.sign, activated_wdata_e_act_raw_sign_13
node _activated_wdata_e_act_raw_out_sExp_T_26 = bits(activated_wdata_e_act_raw_adjustedExp_13, 8, 0)
node _activated_wdata_e_act_raw_out_sExp_T_27 = cvt(_activated_wdata_e_act_raw_out_sExp_T_26)
connect activated_wdata_e_act_raw_13.sExp, _activated_wdata_e_act_raw_out_sExp_T_27
node _activated_wdata_e_act_raw_out_sig_T_52 = eq(activated_wdata_e_act_raw_isZero_13, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_sig_T_53 = cat(UInt<1>(0h0), _activated_wdata_e_act_raw_out_sig_T_52)
node _activated_wdata_e_act_raw_out_sig_T_54 = mux(activated_wdata_e_act_raw_isZeroExpIn_13, activated_wdata_e_act_raw_subnormFract_13, activated_wdata_e_act_raw_fractIn_13)
node _activated_wdata_e_act_raw_out_sig_T_55 = cat(_activated_wdata_e_act_raw_out_sig_T_53, _activated_wdata_e_act_raw_out_sig_T_54)
connect activated_wdata_e_act_raw_13.sig, _activated_wdata_e_act_raw_out_sig_T_55
wire activated_wdata_e_act_result_13 : { bits : UInt<32>}
node _activated_wdata_e_act_result_bits_T_39 = eq(activated_wdata_e_act_raw_13.isZero, UInt<1>(0h0))
node _activated_wdata_e_act_result_bits_T_40 = and(_activated_wdata_e_act_result_bits_T_39, activated_wdata_e_act_raw_13.sign)
node _activated_wdata_e_act_result_bits_T_41 = mux(_activated_wdata_e_act_result_bits_T_40, UInt<1>(0h0), activated_wdata_e_clipped_13.bits)
connect activated_wdata_e_act_result_13.bits, _activated_wdata_e_act_result_bits_T_41
node activated_wdata_e_act_13 = mux(_activated_wdata_e_act_T_13, activated_wdata_e_act_result_13, activated_wdata_e_clipped_13)
wire _activated_wdata_WIRE_13 : { bits : UInt<32>}[1]
connect _activated_wdata_WIRE_13[0], activated_wdata_e_act_13
node activated_wdata_e_clipped_self_rec_rawIn_sign_14 = bits(mesh.io.resp.bits.data[2][0].bits, 31, 31)
node activated_wdata_e_clipped_self_rec_rawIn_expIn_14 = bits(mesh.io.resp.bits.data[2][0].bits, 30, 23)
node activated_wdata_e_clipped_self_rec_rawIn_fractIn_14 = bits(mesh.io.resp.bits.data[2][0].bits, 22, 0)
node activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_14 = eq(activated_wdata_e_clipped_self_rec_rawIn_expIn_14, UInt<1>(0h0))
node activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_14 = eq(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_616 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 0, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_617 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 1, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_618 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 2, 2)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_619 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 3, 3)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_620 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 4, 4)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_621 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 5, 5)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_622 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 6, 6)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_623 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 7, 7)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_624 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 8, 8)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_625 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 9, 9)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_626 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 10, 10)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_627 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 11, 11)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_628 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 12, 12)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_629 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 13, 13)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_630 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 14, 14)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_631 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 15, 15)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_632 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 16, 16)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_633 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 17, 17)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_634 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 18, 18)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_635 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 19, 19)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_636 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 20, 20)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_637 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 21, 21)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_638 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, 22, 22)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_639 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_617, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_640 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_618, UInt<5>(0h14), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_639)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_641 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_619, UInt<5>(0h13), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_640)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_642 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_620, UInt<5>(0h12), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_641)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_643 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_621, UInt<5>(0h11), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_642)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_644 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_622, UInt<5>(0h10), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_643)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_645 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_623, UInt<4>(0hf), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_644)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_646 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_624, UInt<4>(0he), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_645)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_647 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_625, UInt<4>(0hd), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_646)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_648 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_626, UInt<4>(0hc), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_647)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_649 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_627, UInt<4>(0hb), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_648)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_650 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_628, UInt<4>(0ha), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_649)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_651 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_629, UInt<4>(0h9), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_650)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_652 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_630, UInt<4>(0h8), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_651)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_653 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_631, UInt<3>(0h7), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_652)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_654 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_632, UInt<3>(0h6), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_653)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_655 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_633, UInt<3>(0h5), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_654)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_656 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_634, UInt<3>(0h4), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_655)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_657 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_635, UInt<2>(0h3), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_656)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_658 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_636, UInt<2>(0h2), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_657)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_659 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_637, UInt<1>(0h1), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_658)
node activated_wdata_e_clipped_self_rec_rawIn_normDist_14 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_638, UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_659)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_28 = dshl(activated_wdata_e_clipped_self_rec_rawIn_fractIn_14, activated_wdata_e_clipped_self_rec_rawIn_normDist_14)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_29 = bits(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_28, 21, 0)
node activated_wdata_e_clipped_self_rec_rawIn_subnormFract_14 = shl(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_29, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_70 = xor(activated_wdata_e_clipped_self_rec_rawIn_normDist_14, UInt<9>(0h1ff))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_71 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_14, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_70, activated_wdata_e_clipped_self_rec_rawIn_expIn_14)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_72 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_14, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_73 = or(UInt<8>(0h80), _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_72)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_74 = add(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_71, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_73)
node activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_14 = tail(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_74, 1)
node activated_wdata_e_clipped_self_rec_rawIn_isZero_14 = and(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_14, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_14)
node _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_14 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_14, 8, 7)
node activated_wdata_e_clipped_self_rec_rawIn_isSpecial_14 = eq(_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_14, UInt<2>(0h3))
wire activated_wdata_e_clipped_self_rec_rawIn_14 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_28 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_14, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_29 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_14, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_28)
connect activated_wdata_e_clipped_self_rec_rawIn_14.isNaN, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_29
node _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_14 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_14, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_14)
connect activated_wdata_e_clipped_self_rec_rawIn_14.isInf, _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_14
connect activated_wdata_e_clipped_self_rec_rawIn_14.isZero, activated_wdata_e_clipped_self_rec_rawIn_isZero_14
connect activated_wdata_e_clipped_self_rec_rawIn_14.sign, activated_wdata_e_clipped_self_rec_rawIn_sign_14
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_28 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_14, 8, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_29 = cvt(_activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_28)
connect activated_wdata_e_clipped_self_rec_rawIn_14.sExp, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_29
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_56 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZero_14, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_57 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_56)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_58 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_14, activated_wdata_e_clipped_self_rec_rawIn_subnormFract_14, activated_wdata_e_clipped_self_rec_rawIn_fractIn_14)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_59 = cat(_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_57, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_58)
connect activated_wdata_e_clipped_self_rec_rawIn_14.sig, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_59
node _activated_wdata_e_clipped_self_rec_T_112 = bits(activated_wdata_e_clipped_self_rec_rawIn_14.sExp, 8, 6)
node _activated_wdata_e_clipped_self_rec_T_113 = mux(activated_wdata_e_clipped_self_rec_rawIn_14.isZero, UInt<3>(0h0), _activated_wdata_e_clipped_self_rec_T_112)
node _activated_wdata_e_clipped_self_rec_T_114 = mux(activated_wdata_e_clipped_self_rec_rawIn_14.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_T_115 = or(_activated_wdata_e_clipped_self_rec_T_113, _activated_wdata_e_clipped_self_rec_T_114)
node _activated_wdata_e_clipped_self_rec_T_116 = cat(activated_wdata_e_clipped_self_rec_rawIn_14.sign, _activated_wdata_e_clipped_self_rec_T_115)
node _activated_wdata_e_clipped_self_rec_T_117 = bits(activated_wdata_e_clipped_self_rec_rawIn_14.sExp, 5, 0)
node _activated_wdata_e_clipped_self_rec_T_118 = cat(_activated_wdata_e_clipped_self_rec_T_116, _activated_wdata_e_clipped_self_rec_T_117)
node _activated_wdata_e_clipped_self_rec_T_119 = bits(activated_wdata_e_clipped_self_rec_rawIn_14.sig, 22, 0)
node activated_wdata_e_clipped_self_rec_14 = cat(_activated_wdata_e_clipped_self_rec_T_118, _activated_wdata_e_clipped_self_rec_T_119)
inst activated_wdata_e_clipped_resizer_14 of RecFNToRecFN_254
connect activated_wdata_e_clipped_resizer_14.io.in, activated_wdata_e_clipped_self_rec_14
connect activated_wdata_e_clipped_resizer_14.io.roundingMode, UInt<3>(0h0)
connect activated_wdata_e_clipped_resizer_14.io.detectTininess, UInt<1>(0h1)
wire activated_wdata_e_clipped_14 : { bits : UInt<32>}
node activated_wdata_e_clipped_result_bits_rawIn_exp_14 = bits(activated_wdata_e_clipped_resizer_14.io.out, 31, 23)
node _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_14 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_14, 8, 6)
node activated_wdata_e_clipped_result_bits_rawIn_isZero_14 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isZero_T_14, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_14 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_14, 8, 7)
node activated_wdata_e_clipped_result_bits_rawIn_isSpecial_14 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_14, UInt<2>(0h3))
wire activated_wdata_e_clipped_result_bits_rawIn_14 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_28 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_14, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_29 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_14, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_28)
connect activated_wdata_e_clipped_result_bits_rawIn_14.isNaN, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_29
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_42 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_14, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_43 = eq(_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_42, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_44 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_14, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_43)
connect activated_wdata_e_clipped_result_bits_rawIn_14.isInf, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_44
connect activated_wdata_e_clipped_result_bits_rawIn_14.isZero, activated_wdata_e_clipped_result_bits_rawIn_isZero_14
node _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_14 = bits(activated_wdata_e_clipped_resizer_14.io.out, 32, 32)
connect activated_wdata_e_clipped_result_bits_rawIn_14.sign, _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_14
node _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_14 = cvt(activated_wdata_e_clipped_result_bits_rawIn_exp_14)
connect activated_wdata_e_clipped_result_bits_rawIn_14.sExp, _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_14
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_56 = eq(activated_wdata_e_clipped_result_bits_rawIn_isZero_14, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_57 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_56)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_58 = bits(activated_wdata_e_clipped_resizer_14.io.out, 22, 0)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_59 = cat(_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_57, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_58)
connect activated_wdata_e_clipped_result_bits_rawIn_14.sig, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_59
node activated_wdata_e_clipped_result_bits_isSubnormal_14 = lt(activated_wdata_e_clipped_result_bits_rawIn_14.sExp, asSInt(UInt<9>(0h82)))
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_28 = bits(activated_wdata_e_clipped_result_bits_rawIn_14.sExp, 4, 0)
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_29 = sub(UInt<1>(0h1), _activated_wdata_e_clipped_result_bits_denormShiftDist_T_28)
node activated_wdata_e_clipped_result_bits_denormShiftDist_14 = tail(_activated_wdata_e_clipped_result_bits_denormShiftDist_T_29, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_28 = shr(activated_wdata_e_clipped_result_bits_rawIn_14.sig, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_29 = dshr(_activated_wdata_e_clipped_result_bits_denormFract_T_28, activated_wdata_e_clipped_result_bits_denormShiftDist_14)
node activated_wdata_e_clipped_result_bits_denormFract_14 = bits(_activated_wdata_e_clipped_result_bits_denormFract_T_29, 22, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_84 = bits(activated_wdata_e_clipped_result_bits_rawIn_14.sExp, 7, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_85 = sub(_activated_wdata_e_clipped_result_bits_expOut_T_84, UInt<8>(0h81))
node _activated_wdata_e_clipped_result_bits_expOut_T_86 = tail(_activated_wdata_e_clipped_result_bits_expOut_T_85, 1)
node _activated_wdata_e_clipped_result_bits_expOut_T_87 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_14, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_expOut_T_86)
node _activated_wdata_e_clipped_result_bits_expOut_T_88 = or(activated_wdata_e_clipped_result_bits_rawIn_14.isNaN, activated_wdata_e_clipped_result_bits_rawIn_14.isInf)
node _activated_wdata_e_clipped_result_bits_expOut_T_89 = mux(_activated_wdata_e_clipped_result_bits_expOut_T_88, UInt<8>(0hff), UInt<8>(0h0))
node activated_wdata_e_clipped_result_bits_expOut_14 = or(_activated_wdata_e_clipped_result_bits_expOut_T_87, _activated_wdata_e_clipped_result_bits_expOut_T_89)
node _activated_wdata_e_clipped_result_bits_fractOut_T_28 = bits(activated_wdata_e_clipped_result_bits_rawIn_14.sig, 22, 0)
node _activated_wdata_e_clipped_result_bits_fractOut_T_29 = mux(activated_wdata_e_clipped_result_bits_rawIn_14.isInf, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_fractOut_T_28)
node activated_wdata_e_clipped_result_bits_fractOut_14 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_14, activated_wdata_e_clipped_result_bits_denormFract_14, _activated_wdata_e_clipped_result_bits_fractOut_T_29)
node activated_wdata_e_clipped_result_bits_hi_14 = cat(activated_wdata_e_clipped_result_bits_rawIn_14.sign, activated_wdata_e_clipped_result_bits_expOut_14)
node _activated_wdata_e_clipped_result_bits_T_14 = cat(activated_wdata_e_clipped_result_bits_hi_14, activated_wdata_e_clipped_result_bits_fractOut_14)
connect activated_wdata_e_clipped_14.bits, _activated_wdata_e_clipped_result_bits_T_14
node _activated_wdata_e_act_T_14 = eq(activation, UInt<1>(0h1))
node activated_wdata_e_act_raw_sign_14 = bits(activated_wdata_e_clipped_14.bits, 31, 31)
node activated_wdata_e_act_raw_expIn_14 = bits(activated_wdata_e_clipped_14.bits, 30, 23)
node activated_wdata_e_act_raw_fractIn_14 = bits(activated_wdata_e_clipped_14.bits, 22, 0)
node activated_wdata_e_act_raw_isZeroExpIn_14 = eq(activated_wdata_e_act_raw_expIn_14, UInt<1>(0h0))
node activated_wdata_e_act_raw_isZeroFractIn_14 = eq(activated_wdata_e_act_raw_fractIn_14, UInt<1>(0h0))
node _activated_wdata_e_act_raw_normDist_T_616 = bits(activated_wdata_e_act_raw_fractIn_14, 0, 0)
node _activated_wdata_e_act_raw_normDist_T_617 = bits(activated_wdata_e_act_raw_fractIn_14, 1, 1)
node _activated_wdata_e_act_raw_normDist_T_618 = bits(activated_wdata_e_act_raw_fractIn_14, 2, 2)
node _activated_wdata_e_act_raw_normDist_T_619 = bits(activated_wdata_e_act_raw_fractIn_14, 3, 3)
node _activated_wdata_e_act_raw_normDist_T_620 = bits(activated_wdata_e_act_raw_fractIn_14, 4, 4)
node _activated_wdata_e_act_raw_normDist_T_621 = bits(activated_wdata_e_act_raw_fractIn_14, 5, 5)
node _activated_wdata_e_act_raw_normDist_T_622 = bits(activated_wdata_e_act_raw_fractIn_14, 6, 6)
node _activated_wdata_e_act_raw_normDist_T_623 = bits(activated_wdata_e_act_raw_fractIn_14, 7, 7)
node _activated_wdata_e_act_raw_normDist_T_624 = bits(activated_wdata_e_act_raw_fractIn_14, 8, 8)
node _activated_wdata_e_act_raw_normDist_T_625 = bits(activated_wdata_e_act_raw_fractIn_14, 9, 9)
node _activated_wdata_e_act_raw_normDist_T_626 = bits(activated_wdata_e_act_raw_fractIn_14, 10, 10)
node _activated_wdata_e_act_raw_normDist_T_627 = bits(activated_wdata_e_act_raw_fractIn_14, 11, 11)
node _activated_wdata_e_act_raw_normDist_T_628 = bits(activated_wdata_e_act_raw_fractIn_14, 12, 12)
node _activated_wdata_e_act_raw_normDist_T_629 = bits(activated_wdata_e_act_raw_fractIn_14, 13, 13)
node _activated_wdata_e_act_raw_normDist_T_630 = bits(activated_wdata_e_act_raw_fractIn_14, 14, 14)
node _activated_wdata_e_act_raw_normDist_T_631 = bits(activated_wdata_e_act_raw_fractIn_14, 15, 15)
node _activated_wdata_e_act_raw_normDist_T_632 = bits(activated_wdata_e_act_raw_fractIn_14, 16, 16)
node _activated_wdata_e_act_raw_normDist_T_633 = bits(activated_wdata_e_act_raw_fractIn_14, 17, 17)
node _activated_wdata_e_act_raw_normDist_T_634 = bits(activated_wdata_e_act_raw_fractIn_14, 18, 18)
node _activated_wdata_e_act_raw_normDist_T_635 = bits(activated_wdata_e_act_raw_fractIn_14, 19, 19)
node _activated_wdata_e_act_raw_normDist_T_636 = bits(activated_wdata_e_act_raw_fractIn_14, 20, 20)
node _activated_wdata_e_act_raw_normDist_T_637 = bits(activated_wdata_e_act_raw_fractIn_14, 21, 21)
node _activated_wdata_e_act_raw_normDist_T_638 = bits(activated_wdata_e_act_raw_fractIn_14, 22, 22)
node _activated_wdata_e_act_raw_normDist_T_639 = mux(_activated_wdata_e_act_raw_normDist_T_617, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_act_raw_normDist_T_640 = mux(_activated_wdata_e_act_raw_normDist_T_618, UInt<5>(0h14), _activated_wdata_e_act_raw_normDist_T_639)
node _activated_wdata_e_act_raw_normDist_T_641 = mux(_activated_wdata_e_act_raw_normDist_T_619, UInt<5>(0h13), _activated_wdata_e_act_raw_normDist_T_640)
node _activated_wdata_e_act_raw_normDist_T_642 = mux(_activated_wdata_e_act_raw_normDist_T_620, UInt<5>(0h12), _activated_wdata_e_act_raw_normDist_T_641)
node _activated_wdata_e_act_raw_normDist_T_643 = mux(_activated_wdata_e_act_raw_normDist_T_621, UInt<5>(0h11), _activated_wdata_e_act_raw_normDist_T_642)
node _activated_wdata_e_act_raw_normDist_T_644 = mux(_activated_wdata_e_act_raw_normDist_T_622, UInt<5>(0h10), _activated_wdata_e_act_raw_normDist_T_643)
node _activated_wdata_e_act_raw_normDist_T_645 = mux(_activated_wdata_e_act_raw_normDist_T_623, UInt<4>(0hf), _activated_wdata_e_act_raw_normDist_T_644)
node _activated_wdata_e_act_raw_normDist_T_646 = mux(_activated_wdata_e_act_raw_normDist_T_624, UInt<4>(0he), _activated_wdata_e_act_raw_normDist_T_645)
node _activated_wdata_e_act_raw_normDist_T_647 = mux(_activated_wdata_e_act_raw_normDist_T_625, UInt<4>(0hd), _activated_wdata_e_act_raw_normDist_T_646)
node _activated_wdata_e_act_raw_normDist_T_648 = mux(_activated_wdata_e_act_raw_normDist_T_626, UInt<4>(0hc), _activated_wdata_e_act_raw_normDist_T_647)
node _activated_wdata_e_act_raw_normDist_T_649 = mux(_activated_wdata_e_act_raw_normDist_T_627, UInt<4>(0hb), _activated_wdata_e_act_raw_normDist_T_648)
node _activated_wdata_e_act_raw_normDist_T_650 = mux(_activated_wdata_e_act_raw_normDist_T_628, UInt<4>(0ha), _activated_wdata_e_act_raw_normDist_T_649)
node _activated_wdata_e_act_raw_normDist_T_651 = mux(_activated_wdata_e_act_raw_normDist_T_629, UInt<4>(0h9), _activated_wdata_e_act_raw_normDist_T_650)
node _activated_wdata_e_act_raw_normDist_T_652 = mux(_activated_wdata_e_act_raw_normDist_T_630, UInt<4>(0h8), _activated_wdata_e_act_raw_normDist_T_651)
node _activated_wdata_e_act_raw_normDist_T_653 = mux(_activated_wdata_e_act_raw_normDist_T_631, UInt<3>(0h7), _activated_wdata_e_act_raw_normDist_T_652)
node _activated_wdata_e_act_raw_normDist_T_654 = mux(_activated_wdata_e_act_raw_normDist_T_632, UInt<3>(0h6), _activated_wdata_e_act_raw_normDist_T_653)
node _activated_wdata_e_act_raw_normDist_T_655 = mux(_activated_wdata_e_act_raw_normDist_T_633, UInt<3>(0h5), _activated_wdata_e_act_raw_normDist_T_654)
node _activated_wdata_e_act_raw_normDist_T_656 = mux(_activated_wdata_e_act_raw_normDist_T_634, UInt<3>(0h4), _activated_wdata_e_act_raw_normDist_T_655)
node _activated_wdata_e_act_raw_normDist_T_657 = mux(_activated_wdata_e_act_raw_normDist_T_635, UInt<2>(0h3), _activated_wdata_e_act_raw_normDist_T_656)
node _activated_wdata_e_act_raw_normDist_T_658 = mux(_activated_wdata_e_act_raw_normDist_T_636, UInt<2>(0h2), _activated_wdata_e_act_raw_normDist_T_657)
node _activated_wdata_e_act_raw_normDist_T_659 = mux(_activated_wdata_e_act_raw_normDist_T_637, UInt<1>(0h1), _activated_wdata_e_act_raw_normDist_T_658)
node activated_wdata_e_act_raw_normDist_14 = mux(_activated_wdata_e_act_raw_normDist_T_638, UInt<1>(0h0), _activated_wdata_e_act_raw_normDist_T_659)
node _activated_wdata_e_act_raw_subnormFract_T_28 = dshl(activated_wdata_e_act_raw_fractIn_14, activated_wdata_e_act_raw_normDist_14)
node _activated_wdata_e_act_raw_subnormFract_T_29 = bits(_activated_wdata_e_act_raw_subnormFract_T_28, 21, 0)
node activated_wdata_e_act_raw_subnormFract_14 = shl(_activated_wdata_e_act_raw_subnormFract_T_29, 1)
node _activated_wdata_e_act_raw_adjustedExp_T_70 = xor(activated_wdata_e_act_raw_normDist_14, UInt<9>(0h1ff))
node _activated_wdata_e_act_raw_adjustedExp_T_71 = mux(activated_wdata_e_act_raw_isZeroExpIn_14, _activated_wdata_e_act_raw_adjustedExp_T_70, activated_wdata_e_act_raw_expIn_14)
node _activated_wdata_e_act_raw_adjustedExp_T_72 = mux(activated_wdata_e_act_raw_isZeroExpIn_14, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_act_raw_adjustedExp_T_73 = or(UInt<8>(0h80), _activated_wdata_e_act_raw_adjustedExp_T_72)
node _activated_wdata_e_act_raw_adjustedExp_T_74 = add(_activated_wdata_e_act_raw_adjustedExp_T_71, _activated_wdata_e_act_raw_adjustedExp_T_73)
node activated_wdata_e_act_raw_adjustedExp_14 = tail(_activated_wdata_e_act_raw_adjustedExp_T_74, 1)
node activated_wdata_e_act_raw_isZero_14 = and(activated_wdata_e_act_raw_isZeroExpIn_14, activated_wdata_e_act_raw_isZeroFractIn_14)
node _activated_wdata_e_act_raw_isSpecial_T_14 = bits(activated_wdata_e_act_raw_adjustedExp_14, 8, 7)
node activated_wdata_e_act_raw_isSpecial_14 = eq(_activated_wdata_e_act_raw_isSpecial_T_14, UInt<2>(0h3))
wire activated_wdata_e_act_raw_14 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_act_raw_out_isNaN_T_28 = eq(activated_wdata_e_act_raw_isZeroFractIn_14, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_isNaN_T_29 = and(activated_wdata_e_act_raw_isSpecial_14, _activated_wdata_e_act_raw_out_isNaN_T_28)
connect activated_wdata_e_act_raw_14.isNaN, _activated_wdata_e_act_raw_out_isNaN_T_29
node _activated_wdata_e_act_raw_out_isInf_T_14 = and(activated_wdata_e_act_raw_isSpecial_14, activated_wdata_e_act_raw_isZeroFractIn_14)
connect activated_wdata_e_act_raw_14.isInf, _activated_wdata_e_act_raw_out_isInf_T_14
connect activated_wdata_e_act_raw_14.isZero, activated_wdata_e_act_raw_isZero_14
connect activated_wdata_e_act_raw_14.sign, activated_wdata_e_act_raw_sign_14
node _activated_wdata_e_act_raw_out_sExp_T_28 = bits(activated_wdata_e_act_raw_adjustedExp_14, 8, 0)
node _activated_wdata_e_act_raw_out_sExp_T_29 = cvt(_activated_wdata_e_act_raw_out_sExp_T_28)
connect activated_wdata_e_act_raw_14.sExp, _activated_wdata_e_act_raw_out_sExp_T_29
node _activated_wdata_e_act_raw_out_sig_T_56 = eq(activated_wdata_e_act_raw_isZero_14, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_sig_T_57 = cat(UInt<1>(0h0), _activated_wdata_e_act_raw_out_sig_T_56)
node _activated_wdata_e_act_raw_out_sig_T_58 = mux(activated_wdata_e_act_raw_isZeroExpIn_14, activated_wdata_e_act_raw_subnormFract_14, activated_wdata_e_act_raw_fractIn_14)
node _activated_wdata_e_act_raw_out_sig_T_59 = cat(_activated_wdata_e_act_raw_out_sig_T_57, _activated_wdata_e_act_raw_out_sig_T_58)
connect activated_wdata_e_act_raw_14.sig, _activated_wdata_e_act_raw_out_sig_T_59
wire activated_wdata_e_act_result_14 : { bits : UInt<32>}
node _activated_wdata_e_act_result_bits_T_42 = eq(activated_wdata_e_act_raw_14.isZero, UInt<1>(0h0))
node _activated_wdata_e_act_result_bits_T_43 = and(_activated_wdata_e_act_result_bits_T_42, activated_wdata_e_act_raw_14.sign)
node _activated_wdata_e_act_result_bits_T_44 = mux(_activated_wdata_e_act_result_bits_T_43, UInt<1>(0h0), activated_wdata_e_clipped_14.bits)
connect activated_wdata_e_act_result_14.bits, _activated_wdata_e_act_result_bits_T_44
node activated_wdata_e_act_14 = mux(_activated_wdata_e_act_T_14, activated_wdata_e_act_result_14, activated_wdata_e_clipped_14)
wire _activated_wdata_WIRE_14 : { bits : UInt<32>}[1]
connect _activated_wdata_WIRE_14[0], activated_wdata_e_act_14
node activated_wdata_e_clipped_self_rec_rawIn_sign_15 = bits(mesh.io.resp.bits.data[3][0].bits, 31, 31)
node activated_wdata_e_clipped_self_rec_rawIn_expIn_15 = bits(mesh.io.resp.bits.data[3][0].bits, 30, 23)
node activated_wdata_e_clipped_self_rec_rawIn_fractIn_15 = bits(mesh.io.resp.bits.data[3][0].bits, 22, 0)
node activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_15 = eq(activated_wdata_e_clipped_self_rec_rawIn_expIn_15, UInt<1>(0h0))
node activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_15 = eq(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_660 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 0, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_661 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 1, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_662 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 2, 2)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_663 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 3, 3)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_664 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 4, 4)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_665 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 5, 5)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_666 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 6, 6)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_667 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 7, 7)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_668 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 8, 8)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_669 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 9, 9)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_670 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 10, 10)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_671 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 11, 11)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_672 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 12, 12)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_673 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 13, 13)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_674 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 14, 14)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_675 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 15, 15)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_676 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 16, 16)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_677 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 17, 17)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_678 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 18, 18)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_679 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 19, 19)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_680 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 20, 20)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_681 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 21, 21)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_682 = bits(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, 22, 22)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_683 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_661, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_684 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_662, UInt<5>(0h14), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_683)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_685 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_663, UInt<5>(0h13), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_684)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_686 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_664, UInt<5>(0h12), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_685)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_687 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_665, UInt<5>(0h11), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_686)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_688 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_666, UInt<5>(0h10), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_687)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_689 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_667, UInt<4>(0hf), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_688)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_690 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_668, UInt<4>(0he), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_689)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_691 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_669, UInt<4>(0hd), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_690)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_692 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_670, UInt<4>(0hc), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_691)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_693 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_671, UInt<4>(0hb), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_692)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_694 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_672, UInt<4>(0ha), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_693)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_695 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_673, UInt<4>(0h9), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_694)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_696 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_674, UInt<4>(0h8), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_695)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_697 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_675, UInt<3>(0h7), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_696)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_698 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_676, UInt<3>(0h6), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_697)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_699 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_677, UInt<3>(0h5), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_698)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_700 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_678, UInt<3>(0h4), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_699)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_701 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_679, UInt<2>(0h3), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_700)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_702 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_680, UInt<2>(0h2), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_701)
node _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_703 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_681, UInt<1>(0h1), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_702)
node activated_wdata_e_clipped_self_rec_rawIn_normDist_15 = mux(_activated_wdata_e_clipped_self_rec_rawIn_normDist_T_682, UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_703)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_30 = dshl(activated_wdata_e_clipped_self_rec_rawIn_fractIn_15, activated_wdata_e_clipped_self_rec_rawIn_normDist_15)
node _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_31 = bits(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_30, 21, 0)
node activated_wdata_e_clipped_self_rec_rawIn_subnormFract_15 = shl(_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_31, 1)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_75 = xor(activated_wdata_e_clipped_self_rec_rawIn_normDist_15, UInt<9>(0h1ff))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_76 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_15, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_75, activated_wdata_e_clipped_self_rec_rawIn_expIn_15)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_77 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_15, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_78 = or(UInt<8>(0h80), _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_77)
node _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_79 = add(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_76, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_78)
node activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_15 = tail(_activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_79, 1)
node activated_wdata_e_clipped_self_rec_rawIn_isZero_15 = and(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_15, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_15)
node _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_15 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_15, 8, 7)
node activated_wdata_e_clipped_self_rec_rawIn_isSpecial_15 = eq(_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_15, UInt<2>(0h3))
wire activated_wdata_e_clipped_self_rec_rawIn_15 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_30 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_15, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_31 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_15, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_30)
connect activated_wdata_e_clipped_self_rec_rawIn_15.isNaN, _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_31
node _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_15 = and(activated_wdata_e_clipped_self_rec_rawIn_isSpecial_15, activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_15)
connect activated_wdata_e_clipped_self_rec_rawIn_15.isInf, _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_15
connect activated_wdata_e_clipped_self_rec_rawIn_15.isZero, activated_wdata_e_clipped_self_rec_rawIn_isZero_15
connect activated_wdata_e_clipped_self_rec_rawIn_15.sign, activated_wdata_e_clipped_self_rec_rawIn_sign_15
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_30 = bits(activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_15, 8, 0)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_31 = cvt(_activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_30)
connect activated_wdata_e_clipped_self_rec_rawIn_15.sExp, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_31
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_60 = eq(activated_wdata_e_clipped_self_rec_rawIn_isZero_15, UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_61 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_60)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_62 = mux(activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_15, activated_wdata_e_clipped_self_rec_rawIn_subnormFract_15, activated_wdata_e_clipped_self_rec_rawIn_fractIn_15)
node _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_63 = cat(_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_61, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_62)
connect activated_wdata_e_clipped_self_rec_rawIn_15.sig, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_63
node _activated_wdata_e_clipped_self_rec_T_120 = bits(activated_wdata_e_clipped_self_rec_rawIn_15.sExp, 8, 6)
node _activated_wdata_e_clipped_self_rec_T_121 = mux(activated_wdata_e_clipped_self_rec_rawIn_15.isZero, UInt<3>(0h0), _activated_wdata_e_clipped_self_rec_T_120)
node _activated_wdata_e_clipped_self_rec_T_122 = mux(activated_wdata_e_clipped_self_rec_rawIn_15.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _activated_wdata_e_clipped_self_rec_T_123 = or(_activated_wdata_e_clipped_self_rec_T_121, _activated_wdata_e_clipped_self_rec_T_122)
node _activated_wdata_e_clipped_self_rec_T_124 = cat(activated_wdata_e_clipped_self_rec_rawIn_15.sign, _activated_wdata_e_clipped_self_rec_T_123)
node _activated_wdata_e_clipped_self_rec_T_125 = bits(activated_wdata_e_clipped_self_rec_rawIn_15.sExp, 5, 0)
node _activated_wdata_e_clipped_self_rec_T_126 = cat(_activated_wdata_e_clipped_self_rec_T_124, _activated_wdata_e_clipped_self_rec_T_125)
node _activated_wdata_e_clipped_self_rec_T_127 = bits(activated_wdata_e_clipped_self_rec_rawIn_15.sig, 22, 0)
node activated_wdata_e_clipped_self_rec_15 = cat(_activated_wdata_e_clipped_self_rec_T_126, _activated_wdata_e_clipped_self_rec_T_127)
inst activated_wdata_e_clipped_resizer_15 of RecFNToRecFN_255
connect activated_wdata_e_clipped_resizer_15.io.in, activated_wdata_e_clipped_self_rec_15
connect activated_wdata_e_clipped_resizer_15.io.roundingMode, UInt<3>(0h0)
connect activated_wdata_e_clipped_resizer_15.io.detectTininess, UInt<1>(0h1)
wire activated_wdata_e_clipped_15 : { bits : UInt<32>}
node activated_wdata_e_clipped_result_bits_rawIn_exp_15 = bits(activated_wdata_e_clipped_resizer_15.io.out, 31, 23)
node _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_15 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_15, 8, 6)
node activated_wdata_e_clipped_result_bits_rawIn_isZero_15 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isZero_T_15, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_15 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_15, 8, 7)
node activated_wdata_e_clipped_result_bits_rawIn_isSpecial_15 = eq(_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_15, UInt<2>(0h3))
wire activated_wdata_e_clipped_result_bits_rawIn_15 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_30 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_15, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_31 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_15, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_30)
connect activated_wdata_e_clipped_result_bits_rawIn_15.isNaN, _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_31
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_45 = bits(activated_wdata_e_clipped_result_bits_rawIn_exp_15, 6, 6)
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_46 = eq(_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_45, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_47 = and(activated_wdata_e_clipped_result_bits_rawIn_isSpecial_15, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_46)
connect activated_wdata_e_clipped_result_bits_rawIn_15.isInf, _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_47
connect activated_wdata_e_clipped_result_bits_rawIn_15.isZero, activated_wdata_e_clipped_result_bits_rawIn_isZero_15
node _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_15 = bits(activated_wdata_e_clipped_resizer_15.io.out, 32, 32)
connect activated_wdata_e_clipped_result_bits_rawIn_15.sign, _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_15
node _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_15 = cvt(activated_wdata_e_clipped_result_bits_rawIn_exp_15)
connect activated_wdata_e_clipped_result_bits_rawIn_15.sExp, _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_15
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_60 = eq(activated_wdata_e_clipped_result_bits_rawIn_isZero_15, UInt<1>(0h0))
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_61 = cat(UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_60)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_62 = bits(activated_wdata_e_clipped_resizer_15.io.out, 22, 0)
node _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_63 = cat(_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_61, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_62)
connect activated_wdata_e_clipped_result_bits_rawIn_15.sig, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_63
node activated_wdata_e_clipped_result_bits_isSubnormal_15 = lt(activated_wdata_e_clipped_result_bits_rawIn_15.sExp, asSInt(UInt<9>(0h82)))
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_30 = bits(activated_wdata_e_clipped_result_bits_rawIn_15.sExp, 4, 0)
node _activated_wdata_e_clipped_result_bits_denormShiftDist_T_31 = sub(UInt<1>(0h1), _activated_wdata_e_clipped_result_bits_denormShiftDist_T_30)
node activated_wdata_e_clipped_result_bits_denormShiftDist_15 = tail(_activated_wdata_e_clipped_result_bits_denormShiftDist_T_31, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_30 = shr(activated_wdata_e_clipped_result_bits_rawIn_15.sig, 1)
node _activated_wdata_e_clipped_result_bits_denormFract_T_31 = dshr(_activated_wdata_e_clipped_result_bits_denormFract_T_30, activated_wdata_e_clipped_result_bits_denormShiftDist_15)
node activated_wdata_e_clipped_result_bits_denormFract_15 = bits(_activated_wdata_e_clipped_result_bits_denormFract_T_31, 22, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_90 = bits(activated_wdata_e_clipped_result_bits_rawIn_15.sExp, 7, 0)
node _activated_wdata_e_clipped_result_bits_expOut_T_91 = sub(_activated_wdata_e_clipped_result_bits_expOut_T_90, UInt<8>(0h81))
node _activated_wdata_e_clipped_result_bits_expOut_T_92 = tail(_activated_wdata_e_clipped_result_bits_expOut_T_91, 1)
node _activated_wdata_e_clipped_result_bits_expOut_T_93 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_15, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_expOut_T_92)
node _activated_wdata_e_clipped_result_bits_expOut_T_94 = or(activated_wdata_e_clipped_result_bits_rawIn_15.isNaN, activated_wdata_e_clipped_result_bits_rawIn_15.isInf)
node _activated_wdata_e_clipped_result_bits_expOut_T_95 = mux(_activated_wdata_e_clipped_result_bits_expOut_T_94, UInt<8>(0hff), UInt<8>(0h0))
node activated_wdata_e_clipped_result_bits_expOut_15 = or(_activated_wdata_e_clipped_result_bits_expOut_T_93, _activated_wdata_e_clipped_result_bits_expOut_T_95)
node _activated_wdata_e_clipped_result_bits_fractOut_T_30 = bits(activated_wdata_e_clipped_result_bits_rawIn_15.sig, 22, 0)
node _activated_wdata_e_clipped_result_bits_fractOut_T_31 = mux(activated_wdata_e_clipped_result_bits_rawIn_15.isInf, UInt<1>(0h0), _activated_wdata_e_clipped_result_bits_fractOut_T_30)
node activated_wdata_e_clipped_result_bits_fractOut_15 = mux(activated_wdata_e_clipped_result_bits_isSubnormal_15, activated_wdata_e_clipped_result_bits_denormFract_15, _activated_wdata_e_clipped_result_bits_fractOut_T_31)
node activated_wdata_e_clipped_result_bits_hi_15 = cat(activated_wdata_e_clipped_result_bits_rawIn_15.sign, activated_wdata_e_clipped_result_bits_expOut_15)
node _activated_wdata_e_clipped_result_bits_T_15 = cat(activated_wdata_e_clipped_result_bits_hi_15, activated_wdata_e_clipped_result_bits_fractOut_15)
connect activated_wdata_e_clipped_15.bits, _activated_wdata_e_clipped_result_bits_T_15
node _activated_wdata_e_act_T_15 = eq(activation, UInt<1>(0h1))
node activated_wdata_e_act_raw_sign_15 = bits(activated_wdata_e_clipped_15.bits, 31, 31)
node activated_wdata_e_act_raw_expIn_15 = bits(activated_wdata_e_clipped_15.bits, 30, 23)
node activated_wdata_e_act_raw_fractIn_15 = bits(activated_wdata_e_clipped_15.bits, 22, 0)
node activated_wdata_e_act_raw_isZeroExpIn_15 = eq(activated_wdata_e_act_raw_expIn_15, UInt<1>(0h0))
node activated_wdata_e_act_raw_isZeroFractIn_15 = eq(activated_wdata_e_act_raw_fractIn_15, UInt<1>(0h0))
node _activated_wdata_e_act_raw_normDist_T_660 = bits(activated_wdata_e_act_raw_fractIn_15, 0, 0)
node _activated_wdata_e_act_raw_normDist_T_661 = bits(activated_wdata_e_act_raw_fractIn_15, 1, 1)
node _activated_wdata_e_act_raw_normDist_T_662 = bits(activated_wdata_e_act_raw_fractIn_15, 2, 2)
node _activated_wdata_e_act_raw_normDist_T_663 = bits(activated_wdata_e_act_raw_fractIn_15, 3, 3)
node _activated_wdata_e_act_raw_normDist_T_664 = bits(activated_wdata_e_act_raw_fractIn_15, 4, 4)
node _activated_wdata_e_act_raw_normDist_T_665 = bits(activated_wdata_e_act_raw_fractIn_15, 5, 5)
node _activated_wdata_e_act_raw_normDist_T_666 = bits(activated_wdata_e_act_raw_fractIn_15, 6, 6)
node _activated_wdata_e_act_raw_normDist_T_667 = bits(activated_wdata_e_act_raw_fractIn_15, 7, 7)
node _activated_wdata_e_act_raw_normDist_T_668 = bits(activated_wdata_e_act_raw_fractIn_15, 8, 8)
node _activated_wdata_e_act_raw_normDist_T_669 = bits(activated_wdata_e_act_raw_fractIn_15, 9, 9)
node _activated_wdata_e_act_raw_normDist_T_670 = bits(activated_wdata_e_act_raw_fractIn_15, 10, 10)
node _activated_wdata_e_act_raw_normDist_T_671 = bits(activated_wdata_e_act_raw_fractIn_15, 11, 11)
node _activated_wdata_e_act_raw_normDist_T_672 = bits(activated_wdata_e_act_raw_fractIn_15, 12, 12)
node _activated_wdata_e_act_raw_normDist_T_673 = bits(activated_wdata_e_act_raw_fractIn_15, 13, 13)
node _activated_wdata_e_act_raw_normDist_T_674 = bits(activated_wdata_e_act_raw_fractIn_15, 14, 14)
node _activated_wdata_e_act_raw_normDist_T_675 = bits(activated_wdata_e_act_raw_fractIn_15, 15, 15)
node _activated_wdata_e_act_raw_normDist_T_676 = bits(activated_wdata_e_act_raw_fractIn_15, 16, 16)
node _activated_wdata_e_act_raw_normDist_T_677 = bits(activated_wdata_e_act_raw_fractIn_15, 17, 17)
node _activated_wdata_e_act_raw_normDist_T_678 = bits(activated_wdata_e_act_raw_fractIn_15, 18, 18)
node _activated_wdata_e_act_raw_normDist_T_679 = bits(activated_wdata_e_act_raw_fractIn_15, 19, 19)
node _activated_wdata_e_act_raw_normDist_T_680 = bits(activated_wdata_e_act_raw_fractIn_15, 20, 20)
node _activated_wdata_e_act_raw_normDist_T_681 = bits(activated_wdata_e_act_raw_fractIn_15, 21, 21)
node _activated_wdata_e_act_raw_normDist_T_682 = bits(activated_wdata_e_act_raw_fractIn_15, 22, 22)
node _activated_wdata_e_act_raw_normDist_T_683 = mux(_activated_wdata_e_act_raw_normDist_T_661, UInt<5>(0h15), UInt<5>(0h16))
node _activated_wdata_e_act_raw_normDist_T_684 = mux(_activated_wdata_e_act_raw_normDist_T_662, UInt<5>(0h14), _activated_wdata_e_act_raw_normDist_T_683)
node _activated_wdata_e_act_raw_normDist_T_685 = mux(_activated_wdata_e_act_raw_normDist_T_663, UInt<5>(0h13), _activated_wdata_e_act_raw_normDist_T_684)
node _activated_wdata_e_act_raw_normDist_T_686 = mux(_activated_wdata_e_act_raw_normDist_T_664, UInt<5>(0h12), _activated_wdata_e_act_raw_normDist_T_685)
node _activated_wdata_e_act_raw_normDist_T_687 = mux(_activated_wdata_e_act_raw_normDist_T_665, UInt<5>(0h11), _activated_wdata_e_act_raw_normDist_T_686)
node _activated_wdata_e_act_raw_normDist_T_688 = mux(_activated_wdata_e_act_raw_normDist_T_666, UInt<5>(0h10), _activated_wdata_e_act_raw_normDist_T_687)
node _activated_wdata_e_act_raw_normDist_T_689 = mux(_activated_wdata_e_act_raw_normDist_T_667, UInt<4>(0hf), _activated_wdata_e_act_raw_normDist_T_688)
node _activated_wdata_e_act_raw_normDist_T_690 = mux(_activated_wdata_e_act_raw_normDist_T_668, UInt<4>(0he), _activated_wdata_e_act_raw_normDist_T_689)
node _activated_wdata_e_act_raw_normDist_T_691 = mux(_activated_wdata_e_act_raw_normDist_T_669, UInt<4>(0hd), _activated_wdata_e_act_raw_normDist_T_690)
node _activated_wdata_e_act_raw_normDist_T_692 = mux(_activated_wdata_e_act_raw_normDist_T_670, UInt<4>(0hc), _activated_wdata_e_act_raw_normDist_T_691)
node _activated_wdata_e_act_raw_normDist_T_693 = mux(_activated_wdata_e_act_raw_normDist_T_671, UInt<4>(0hb), _activated_wdata_e_act_raw_normDist_T_692)
node _activated_wdata_e_act_raw_normDist_T_694 = mux(_activated_wdata_e_act_raw_normDist_T_672, UInt<4>(0ha), _activated_wdata_e_act_raw_normDist_T_693)
node _activated_wdata_e_act_raw_normDist_T_695 = mux(_activated_wdata_e_act_raw_normDist_T_673, UInt<4>(0h9), _activated_wdata_e_act_raw_normDist_T_694)
node _activated_wdata_e_act_raw_normDist_T_696 = mux(_activated_wdata_e_act_raw_normDist_T_674, UInt<4>(0h8), _activated_wdata_e_act_raw_normDist_T_695)
node _activated_wdata_e_act_raw_normDist_T_697 = mux(_activated_wdata_e_act_raw_normDist_T_675, UInt<3>(0h7), _activated_wdata_e_act_raw_normDist_T_696)
node _activated_wdata_e_act_raw_normDist_T_698 = mux(_activated_wdata_e_act_raw_normDist_T_676, UInt<3>(0h6), _activated_wdata_e_act_raw_normDist_T_697)
node _activated_wdata_e_act_raw_normDist_T_699 = mux(_activated_wdata_e_act_raw_normDist_T_677, UInt<3>(0h5), _activated_wdata_e_act_raw_normDist_T_698)
node _activated_wdata_e_act_raw_normDist_T_700 = mux(_activated_wdata_e_act_raw_normDist_T_678, UInt<3>(0h4), _activated_wdata_e_act_raw_normDist_T_699)
node _activated_wdata_e_act_raw_normDist_T_701 = mux(_activated_wdata_e_act_raw_normDist_T_679, UInt<2>(0h3), _activated_wdata_e_act_raw_normDist_T_700)
node _activated_wdata_e_act_raw_normDist_T_702 = mux(_activated_wdata_e_act_raw_normDist_T_680, UInt<2>(0h2), _activated_wdata_e_act_raw_normDist_T_701)
node _activated_wdata_e_act_raw_normDist_T_703 = mux(_activated_wdata_e_act_raw_normDist_T_681, UInt<1>(0h1), _activated_wdata_e_act_raw_normDist_T_702)
node activated_wdata_e_act_raw_normDist_15 = mux(_activated_wdata_e_act_raw_normDist_T_682, UInt<1>(0h0), _activated_wdata_e_act_raw_normDist_T_703)
node _activated_wdata_e_act_raw_subnormFract_T_30 = dshl(activated_wdata_e_act_raw_fractIn_15, activated_wdata_e_act_raw_normDist_15)
node _activated_wdata_e_act_raw_subnormFract_T_31 = bits(_activated_wdata_e_act_raw_subnormFract_T_30, 21, 0)
node activated_wdata_e_act_raw_subnormFract_15 = shl(_activated_wdata_e_act_raw_subnormFract_T_31, 1)
node _activated_wdata_e_act_raw_adjustedExp_T_75 = xor(activated_wdata_e_act_raw_normDist_15, UInt<9>(0h1ff))
node _activated_wdata_e_act_raw_adjustedExp_T_76 = mux(activated_wdata_e_act_raw_isZeroExpIn_15, _activated_wdata_e_act_raw_adjustedExp_T_75, activated_wdata_e_act_raw_expIn_15)
node _activated_wdata_e_act_raw_adjustedExp_T_77 = mux(activated_wdata_e_act_raw_isZeroExpIn_15, UInt<2>(0h2), UInt<1>(0h1))
node _activated_wdata_e_act_raw_adjustedExp_T_78 = or(UInt<8>(0h80), _activated_wdata_e_act_raw_adjustedExp_T_77)
node _activated_wdata_e_act_raw_adjustedExp_T_79 = add(_activated_wdata_e_act_raw_adjustedExp_T_76, _activated_wdata_e_act_raw_adjustedExp_T_78)
node activated_wdata_e_act_raw_adjustedExp_15 = tail(_activated_wdata_e_act_raw_adjustedExp_T_79, 1)
node activated_wdata_e_act_raw_isZero_15 = and(activated_wdata_e_act_raw_isZeroExpIn_15, activated_wdata_e_act_raw_isZeroFractIn_15)
node _activated_wdata_e_act_raw_isSpecial_T_15 = bits(activated_wdata_e_act_raw_adjustedExp_15, 8, 7)
node activated_wdata_e_act_raw_isSpecial_15 = eq(_activated_wdata_e_act_raw_isSpecial_T_15, UInt<2>(0h3))
wire activated_wdata_e_act_raw_15 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _activated_wdata_e_act_raw_out_isNaN_T_30 = eq(activated_wdata_e_act_raw_isZeroFractIn_15, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_isNaN_T_31 = and(activated_wdata_e_act_raw_isSpecial_15, _activated_wdata_e_act_raw_out_isNaN_T_30)
connect activated_wdata_e_act_raw_15.isNaN, _activated_wdata_e_act_raw_out_isNaN_T_31
node _activated_wdata_e_act_raw_out_isInf_T_15 = and(activated_wdata_e_act_raw_isSpecial_15, activated_wdata_e_act_raw_isZeroFractIn_15)
connect activated_wdata_e_act_raw_15.isInf, _activated_wdata_e_act_raw_out_isInf_T_15
connect activated_wdata_e_act_raw_15.isZero, activated_wdata_e_act_raw_isZero_15
connect activated_wdata_e_act_raw_15.sign, activated_wdata_e_act_raw_sign_15
node _activated_wdata_e_act_raw_out_sExp_T_30 = bits(activated_wdata_e_act_raw_adjustedExp_15, 8, 0)
node _activated_wdata_e_act_raw_out_sExp_T_31 = cvt(_activated_wdata_e_act_raw_out_sExp_T_30)
connect activated_wdata_e_act_raw_15.sExp, _activated_wdata_e_act_raw_out_sExp_T_31
node _activated_wdata_e_act_raw_out_sig_T_60 = eq(activated_wdata_e_act_raw_isZero_15, UInt<1>(0h0))
node _activated_wdata_e_act_raw_out_sig_T_61 = cat(UInt<1>(0h0), _activated_wdata_e_act_raw_out_sig_T_60)
node _activated_wdata_e_act_raw_out_sig_T_62 = mux(activated_wdata_e_act_raw_isZeroExpIn_15, activated_wdata_e_act_raw_subnormFract_15, activated_wdata_e_act_raw_fractIn_15)
node _activated_wdata_e_act_raw_out_sig_T_63 = cat(_activated_wdata_e_act_raw_out_sig_T_61, _activated_wdata_e_act_raw_out_sig_T_62)
connect activated_wdata_e_act_raw_15.sig, _activated_wdata_e_act_raw_out_sig_T_63
wire activated_wdata_e_act_result_15 : { bits : UInt<32>}
node _activated_wdata_e_act_result_bits_T_45 = eq(activated_wdata_e_act_raw_15.isZero, UInt<1>(0h0))
node _activated_wdata_e_act_result_bits_T_46 = and(_activated_wdata_e_act_result_bits_T_45, activated_wdata_e_act_raw_15.sign)
node _activated_wdata_e_act_result_bits_T_47 = mux(_activated_wdata_e_act_result_bits_T_46, UInt<1>(0h0), activated_wdata_e_clipped_15.bits)
connect activated_wdata_e_act_result_15.bits, _activated_wdata_e_act_result_bits_T_47
node activated_wdata_e_act_15 = mux(_activated_wdata_e_act_T_15, activated_wdata_e_act_result_15, activated_wdata_e_clipped_15)
wire _activated_wdata_WIRE_15 : { bits : UInt<32>}[1]
connect _activated_wdata_WIRE_15[0], activated_wdata_e_act_15
wire activated_wdata_3 : { bits : UInt<32>}[1][4]
connect activated_wdata_3[0], _activated_wdata_WIRE_12
connect activated_wdata_3[1], _activated_wdata_WIRE_13
connect activated_wdata_3[2], _activated_wdata_WIRE_14
connect activated_wdata_3[3], _activated_wdata_WIRE_15
node _io_srams_write_3_en_T = eq(w_bank, UInt<2>(0h3))
node _io_srams_write_3_en_T_1 = and(start_array_outputting, _io_srams_write_3_en_T)
node _io_srams_write_3_en_T_2 = eq(w_address.is_acc_addr, UInt<1>(0h0))
node _io_srams_write_3_en_T_3 = and(_io_srams_write_3_en_T_1, _io_srams_write_3_en_T_2)
node _io_srams_write_3_en_T_4 = eq(is_garbage_addr, UInt<1>(0h0))
node _io_srams_write_3_en_T_5 = and(_io_srams_write_3_en_T_3, _io_srams_write_3_en_T_4)
node _io_srams_write_3_en_T_6 = and(_io_srams_write_3_en_T_5, write_this_row)
connect io.srams.write[3].en, _io_srams_write_3_en_T_6
connect io.srams.write[3].addr, w_row
node io_srams_write_3_data_lo = cat(activated_wdata_3[1][0].bits, activated_wdata_3[0][0].bits)
node io_srams_write_3_data_hi = cat(activated_wdata_3[3][0].bits, activated_wdata_3[2][0].bits)
node _io_srams_write_3_data_T = cat(io_srams_write_3_data_hi, io_srams_write_3_data_lo)
connect io.srams.write[3].data, _io_srams_write_3_data_T
connect io.srams.write[3].mask[0], w_mask_0
connect io.srams.write[3].mask[1], w_mask_0
connect io.srams.write[3].mask[2], w_mask_0
connect io.srams.write[3].mask[3], w_mask_0
connect io.srams.write[3].mask[4], w_mask_1
connect io.srams.write[3].mask[5], w_mask_1
connect io.srams.write[3].mask[6], w_mask_1
connect io.srams.write[3].mask[7], w_mask_1
connect io.srams.write[3].mask[8], w_mask_2
connect io.srams.write[3].mask[9], w_mask_2
connect io.srams.write[3].mask[10], w_mask_2
connect io.srams.write[3].mask[11], w_mask_2
connect io.srams.write[3].mask[12], w_mask_3
connect io.srams.write[3].mask[13], w_mask_3
connect io.srams.write[3].mask[14], w_mask_3
connect io.srams.write[3].mask[15], w_mask_3
node _io_acc_write_0_valid_T = eq(w_bank, UInt<1>(0h0))
node _io_acc_write_0_valid_T_1 = and(start_array_outputting, _io_acc_write_0_valid_T)
node _io_acc_write_0_valid_T_2 = and(_io_acc_write_0_valid_T_1, w_address.is_acc_addr)
node _io_acc_write_0_valid_T_3 = eq(is_garbage_addr, UInt<1>(0h0))
node _io_acc_write_0_valid_T_4 = and(_io_acc_write_0_valid_T_2, _io_acc_write_0_valid_T_3)
node _io_acc_write_0_valid_T_5 = and(_io_acc_write_0_valid_T_4, write_this_row)
connect io.acc.write[0].valid, _io_acc_write_0_valid_T_5
connect io.acc.write[0].bits.addr, w_row
node self_rec_rawIn_sign = bits(mesh.io.resp.bits.data[0][0].bits, 31, 31)
node self_rec_rawIn_expIn = bits(mesh.io.resp.bits.data[0][0].bits, 30, 23)
node self_rec_rawIn_fractIn = bits(mesh.io.resp.bits.data[0][0].bits, 22, 0)
node self_rec_rawIn_isZeroExpIn = eq(self_rec_rawIn_expIn, UInt<1>(0h0))
node self_rec_rawIn_isZeroFractIn = eq(self_rec_rawIn_fractIn, UInt<1>(0h0))
node _self_rec_rawIn_normDist_T = bits(self_rec_rawIn_fractIn, 0, 0)
node _self_rec_rawIn_normDist_T_1 = bits(self_rec_rawIn_fractIn, 1, 1)
node _self_rec_rawIn_normDist_T_2 = bits(self_rec_rawIn_fractIn, 2, 2)
node _self_rec_rawIn_normDist_T_3 = bits(self_rec_rawIn_fractIn, 3, 3)
node _self_rec_rawIn_normDist_T_4 = bits(self_rec_rawIn_fractIn, 4, 4)
node _self_rec_rawIn_normDist_T_5 = bits(self_rec_rawIn_fractIn, 5, 5)
node _self_rec_rawIn_normDist_T_6 = bits(self_rec_rawIn_fractIn, 6, 6)
node _self_rec_rawIn_normDist_T_7 = bits(self_rec_rawIn_fractIn, 7, 7)
node _self_rec_rawIn_normDist_T_8 = bits(self_rec_rawIn_fractIn, 8, 8)
node _self_rec_rawIn_normDist_T_9 = bits(self_rec_rawIn_fractIn, 9, 9)
node _self_rec_rawIn_normDist_T_10 = bits(self_rec_rawIn_fractIn, 10, 10)
node _self_rec_rawIn_normDist_T_11 = bits(self_rec_rawIn_fractIn, 11, 11)
node _self_rec_rawIn_normDist_T_12 = bits(self_rec_rawIn_fractIn, 12, 12)
node _self_rec_rawIn_normDist_T_13 = bits(self_rec_rawIn_fractIn, 13, 13)
node _self_rec_rawIn_normDist_T_14 = bits(self_rec_rawIn_fractIn, 14, 14)
node _self_rec_rawIn_normDist_T_15 = bits(self_rec_rawIn_fractIn, 15, 15)
node _self_rec_rawIn_normDist_T_16 = bits(self_rec_rawIn_fractIn, 16, 16)
node _self_rec_rawIn_normDist_T_17 = bits(self_rec_rawIn_fractIn, 17, 17)
node _self_rec_rawIn_normDist_T_18 = bits(self_rec_rawIn_fractIn, 18, 18)
node _self_rec_rawIn_normDist_T_19 = bits(self_rec_rawIn_fractIn, 19, 19)
node _self_rec_rawIn_normDist_T_20 = bits(self_rec_rawIn_fractIn, 20, 20)
node _self_rec_rawIn_normDist_T_21 = bits(self_rec_rawIn_fractIn, 21, 21)
node _self_rec_rawIn_normDist_T_22 = bits(self_rec_rawIn_fractIn, 22, 22)
node _self_rec_rawIn_normDist_T_23 = mux(_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16))
node _self_rec_rawIn_normDist_T_24 = mux(_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _self_rec_rawIn_normDist_T_23)
node _self_rec_rawIn_normDist_T_25 = mux(_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _self_rec_rawIn_normDist_T_24)
node _self_rec_rawIn_normDist_T_26 = mux(_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _self_rec_rawIn_normDist_T_25)
node _self_rec_rawIn_normDist_T_27 = mux(_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _self_rec_rawIn_normDist_T_26)
node _self_rec_rawIn_normDist_T_28 = mux(_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _self_rec_rawIn_normDist_T_27)
node _self_rec_rawIn_normDist_T_29 = mux(_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _self_rec_rawIn_normDist_T_28)
node _self_rec_rawIn_normDist_T_30 = mux(_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _self_rec_rawIn_normDist_T_29)
node _self_rec_rawIn_normDist_T_31 = mux(_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _self_rec_rawIn_normDist_T_30)
node _self_rec_rawIn_normDist_T_32 = mux(_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _self_rec_rawIn_normDist_T_31)
node _self_rec_rawIn_normDist_T_33 = mux(_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _self_rec_rawIn_normDist_T_32)
node _self_rec_rawIn_normDist_T_34 = mux(_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _self_rec_rawIn_normDist_T_33)
node _self_rec_rawIn_normDist_T_35 = mux(_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _self_rec_rawIn_normDist_T_34)
node _self_rec_rawIn_normDist_T_36 = mux(_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _self_rec_rawIn_normDist_T_35)
node _self_rec_rawIn_normDist_T_37 = mux(_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _self_rec_rawIn_normDist_T_36)
node _self_rec_rawIn_normDist_T_38 = mux(_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _self_rec_rawIn_normDist_T_37)
node _self_rec_rawIn_normDist_T_39 = mux(_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _self_rec_rawIn_normDist_T_38)
node _self_rec_rawIn_normDist_T_40 = mux(_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _self_rec_rawIn_normDist_T_39)
node _self_rec_rawIn_normDist_T_41 = mux(_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _self_rec_rawIn_normDist_T_40)
node _self_rec_rawIn_normDist_T_42 = mux(_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _self_rec_rawIn_normDist_T_41)
node _self_rec_rawIn_normDist_T_43 = mux(_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _self_rec_rawIn_normDist_T_42)
node self_rec_rawIn_normDist = mux(_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _self_rec_rawIn_normDist_T_43)
node _self_rec_rawIn_subnormFract_T = dshl(self_rec_rawIn_fractIn, self_rec_rawIn_normDist)
node _self_rec_rawIn_subnormFract_T_1 = bits(_self_rec_rawIn_subnormFract_T, 21, 0)
node self_rec_rawIn_subnormFract = shl(_self_rec_rawIn_subnormFract_T_1, 1)
node _self_rec_rawIn_adjustedExp_T = xor(self_rec_rawIn_normDist, UInt<9>(0h1ff))
node _self_rec_rawIn_adjustedExp_T_1 = mux(self_rec_rawIn_isZeroExpIn, _self_rec_rawIn_adjustedExp_T, self_rec_rawIn_expIn)
node _self_rec_rawIn_adjustedExp_T_2 = mux(self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1))
node _self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _self_rec_rawIn_adjustedExp_T_2)
node _self_rec_rawIn_adjustedExp_T_4 = add(_self_rec_rawIn_adjustedExp_T_1, _self_rec_rawIn_adjustedExp_T_3)
node self_rec_rawIn_adjustedExp = tail(_self_rec_rawIn_adjustedExp_T_4, 1)
node self_rec_rawIn_isZero = and(self_rec_rawIn_isZeroExpIn, self_rec_rawIn_isZeroFractIn)
node _self_rec_rawIn_isSpecial_T = bits(self_rec_rawIn_adjustedExp, 8, 7)
node self_rec_rawIn_isSpecial = eq(_self_rec_rawIn_isSpecial_T, UInt<2>(0h3))
wire self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _self_rec_rawIn_out_isNaN_T = eq(self_rec_rawIn_isZeroFractIn, UInt<1>(0h0))
node _self_rec_rawIn_out_isNaN_T_1 = and(self_rec_rawIn_isSpecial, _self_rec_rawIn_out_isNaN_T)
connect self_rec_rawIn.isNaN, _self_rec_rawIn_out_isNaN_T_1
node _self_rec_rawIn_out_isInf_T = and(self_rec_rawIn_isSpecial, self_rec_rawIn_isZeroFractIn)
connect self_rec_rawIn.isInf, _self_rec_rawIn_out_isInf_T
connect self_rec_rawIn.isZero, self_rec_rawIn_isZero
connect self_rec_rawIn.sign, self_rec_rawIn_sign
node _self_rec_rawIn_out_sExp_T = bits(self_rec_rawIn_adjustedExp, 8, 0)
node _self_rec_rawIn_out_sExp_T_1 = cvt(_self_rec_rawIn_out_sExp_T)
connect self_rec_rawIn.sExp, _self_rec_rawIn_out_sExp_T_1
node _self_rec_rawIn_out_sig_T = eq(self_rec_rawIn_isZero, UInt<1>(0h0))
node _self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _self_rec_rawIn_out_sig_T)
node _self_rec_rawIn_out_sig_T_2 = mux(self_rec_rawIn_isZeroExpIn, self_rec_rawIn_subnormFract, self_rec_rawIn_fractIn)
node _self_rec_rawIn_out_sig_T_3 = cat(_self_rec_rawIn_out_sig_T_1, _self_rec_rawIn_out_sig_T_2)
connect self_rec_rawIn.sig, _self_rec_rawIn_out_sig_T_3
node _self_rec_T = bits(self_rec_rawIn.sExp, 8, 6)
node _self_rec_T_1 = mux(self_rec_rawIn.isZero, UInt<3>(0h0), _self_rec_T)
node _self_rec_T_2 = mux(self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _self_rec_T_3 = or(_self_rec_T_1, _self_rec_T_2)
node _self_rec_T_4 = cat(self_rec_rawIn.sign, _self_rec_T_3)
node _self_rec_T_5 = bits(self_rec_rawIn.sExp, 5, 0)
node _self_rec_T_6 = cat(_self_rec_T_4, _self_rec_T_5)
node _self_rec_T_7 = bits(self_rec_rawIn.sig, 22, 0)
node self_rec = cat(_self_rec_T_6, _self_rec_T_7)
inst resizer of RecFNToRecFN_256
connect resizer.io.in, self_rec
connect resizer.io.roundingMode, UInt<3>(0h0)
connect resizer.io.detectTininess, UInt<1>(0h1)
wire result : { bits : UInt<32>}
node result_bits_rawIn_exp = bits(resizer.io.out, 31, 23)
node _result_bits_rawIn_isZero_T = bits(result_bits_rawIn_exp, 8, 6)
node result_bits_rawIn_isZero = eq(_result_bits_rawIn_isZero_T, UInt<1>(0h0))
node _result_bits_rawIn_isSpecial_T = bits(result_bits_rawIn_exp, 8, 7)
node result_bits_rawIn_isSpecial = eq(_result_bits_rawIn_isSpecial_T, UInt<2>(0h3))
wire result_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _result_bits_rawIn_out_isNaN_T = bits(result_bits_rawIn_exp, 6, 6)
node _result_bits_rawIn_out_isNaN_T_1 = and(result_bits_rawIn_isSpecial, _result_bits_rawIn_out_isNaN_T)
connect result_bits_rawIn.isNaN, _result_bits_rawIn_out_isNaN_T_1
node _result_bits_rawIn_out_isInf_T = bits(result_bits_rawIn_exp, 6, 6)
node _result_bits_rawIn_out_isInf_T_1 = eq(_result_bits_rawIn_out_isInf_T, UInt<1>(0h0))
node _result_bits_rawIn_out_isInf_T_2 = and(result_bits_rawIn_isSpecial, _result_bits_rawIn_out_isInf_T_1)
connect result_bits_rawIn.isInf, _result_bits_rawIn_out_isInf_T_2
connect result_bits_rawIn.isZero, result_bits_rawIn_isZero
node _result_bits_rawIn_out_sign_T = bits(resizer.io.out, 32, 32)
connect result_bits_rawIn.sign, _result_bits_rawIn_out_sign_T
node _result_bits_rawIn_out_sExp_T = cvt(result_bits_rawIn_exp)
connect result_bits_rawIn.sExp, _result_bits_rawIn_out_sExp_T
node _result_bits_rawIn_out_sig_T = eq(result_bits_rawIn_isZero, UInt<1>(0h0))
node _result_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _result_bits_rawIn_out_sig_T)
node _result_bits_rawIn_out_sig_T_2 = bits(resizer.io.out, 22, 0)
node _result_bits_rawIn_out_sig_T_3 = cat(_result_bits_rawIn_out_sig_T_1, _result_bits_rawIn_out_sig_T_2)
connect result_bits_rawIn.sig, _result_bits_rawIn_out_sig_T_3
node result_bits_isSubnormal = lt(result_bits_rawIn.sExp, asSInt(UInt<9>(0h82)))
node _result_bits_denormShiftDist_T = bits(result_bits_rawIn.sExp, 4, 0)
node _result_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _result_bits_denormShiftDist_T)
node result_bits_denormShiftDist = tail(_result_bits_denormShiftDist_T_1, 1)
node _result_bits_denormFract_T = shr(result_bits_rawIn.sig, 1)
node _result_bits_denormFract_T_1 = dshr(_result_bits_denormFract_T, result_bits_denormShiftDist)
node result_bits_denormFract = bits(_result_bits_denormFract_T_1, 22, 0)
node _result_bits_expOut_T = bits(result_bits_rawIn.sExp, 7, 0)
node _result_bits_expOut_T_1 = sub(_result_bits_expOut_T, UInt<8>(0h81))
node _result_bits_expOut_T_2 = tail(_result_bits_expOut_T_1, 1)
node _result_bits_expOut_T_3 = mux(result_bits_isSubnormal, UInt<1>(0h0), _result_bits_expOut_T_2)
node _result_bits_expOut_T_4 = or(result_bits_rawIn.isNaN, result_bits_rawIn.isInf)
node _result_bits_expOut_T_5 = mux(_result_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0))
node result_bits_expOut = or(_result_bits_expOut_T_3, _result_bits_expOut_T_5)
node _result_bits_fractOut_T = bits(result_bits_rawIn.sig, 22, 0)
node _result_bits_fractOut_T_1 = mux(result_bits_rawIn.isInf, UInt<1>(0h0), _result_bits_fractOut_T)
node result_bits_fractOut = mux(result_bits_isSubnormal, result_bits_denormFract, _result_bits_fractOut_T_1)
node result_bits_hi = cat(result_bits_rawIn.sign, result_bits_expOut)
node _result_bits_T = cat(result_bits_hi, result_bits_fractOut)
connect result.bits, _result_bits_T
wire _WIRE_17 : { bits : UInt<32>}[1]
connect _WIRE_17[0], result
node self_rec_rawIn_sign_1 = bits(mesh.io.resp.bits.data[1][0].bits, 31, 31)
node self_rec_rawIn_expIn_1 = bits(mesh.io.resp.bits.data[1][0].bits, 30, 23)
node self_rec_rawIn_fractIn_1 = bits(mesh.io.resp.bits.data[1][0].bits, 22, 0)
node self_rec_rawIn_isZeroExpIn_1 = eq(self_rec_rawIn_expIn_1, UInt<1>(0h0))
node self_rec_rawIn_isZeroFractIn_1 = eq(self_rec_rawIn_fractIn_1, UInt<1>(0h0))
node _self_rec_rawIn_normDist_T_44 = bits(self_rec_rawIn_fractIn_1, 0, 0)
node _self_rec_rawIn_normDist_T_45 = bits(self_rec_rawIn_fractIn_1, 1, 1)
node _self_rec_rawIn_normDist_T_46 = bits(self_rec_rawIn_fractIn_1, 2, 2)
node _self_rec_rawIn_normDist_T_47 = bits(self_rec_rawIn_fractIn_1, 3, 3)
node _self_rec_rawIn_normDist_T_48 = bits(self_rec_rawIn_fractIn_1, 4, 4)
node _self_rec_rawIn_normDist_T_49 = bits(self_rec_rawIn_fractIn_1, 5, 5)
node _self_rec_rawIn_normDist_T_50 = bits(self_rec_rawIn_fractIn_1, 6, 6)
node _self_rec_rawIn_normDist_T_51 = bits(self_rec_rawIn_fractIn_1, 7, 7)
node _self_rec_rawIn_normDist_T_52 = bits(self_rec_rawIn_fractIn_1, 8, 8)
node _self_rec_rawIn_normDist_T_53 = bits(self_rec_rawIn_fractIn_1, 9, 9)
node _self_rec_rawIn_normDist_T_54 = bits(self_rec_rawIn_fractIn_1, 10, 10)
node _self_rec_rawIn_normDist_T_55 = bits(self_rec_rawIn_fractIn_1, 11, 11)
node _self_rec_rawIn_normDist_T_56 = bits(self_rec_rawIn_fractIn_1, 12, 12)
node _self_rec_rawIn_normDist_T_57 = bits(self_rec_rawIn_fractIn_1, 13, 13)
node _self_rec_rawIn_normDist_T_58 = bits(self_rec_rawIn_fractIn_1, 14, 14)
node _self_rec_rawIn_normDist_T_59 = bits(self_rec_rawIn_fractIn_1, 15, 15)
node _self_rec_rawIn_normDist_T_60 = bits(self_rec_rawIn_fractIn_1, 16, 16)
node _self_rec_rawIn_normDist_T_61 = bits(self_rec_rawIn_fractIn_1, 17, 17)
node _self_rec_rawIn_normDist_T_62 = bits(self_rec_rawIn_fractIn_1, 18, 18)
node _self_rec_rawIn_normDist_T_63 = bits(self_rec_rawIn_fractIn_1, 19, 19)
node _self_rec_rawIn_normDist_T_64 = bits(self_rec_rawIn_fractIn_1, 20, 20)
node _self_rec_rawIn_normDist_T_65 = bits(self_rec_rawIn_fractIn_1, 21, 21)
node _self_rec_rawIn_normDist_T_66 = bits(self_rec_rawIn_fractIn_1, 22, 22)
node _self_rec_rawIn_normDist_T_67 = mux(_self_rec_rawIn_normDist_T_45, UInt<5>(0h15), UInt<5>(0h16))
node _self_rec_rawIn_normDist_T_68 = mux(_self_rec_rawIn_normDist_T_46, UInt<5>(0h14), _self_rec_rawIn_normDist_T_67)
node _self_rec_rawIn_normDist_T_69 = mux(_self_rec_rawIn_normDist_T_47, UInt<5>(0h13), _self_rec_rawIn_normDist_T_68)
node _self_rec_rawIn_normDist_T_70 = mux(_self_rec_rawIn_normDist_T_48, UInt<5>(0h12), _self_rec_rawIn_normDist_T_69)
node _self_rec_rawIn_normDist_T_71 = mux(_self_rec_rawIn_normDist_T_49, UInt<5>(0h11), _self_rec_rawIn_normDist_T_70)
node _self_rec_rawIn_normDist_T_72 = mux(_self_rec_rawIn_normDist_T_50, UInt<5>(0h10), _self_rec_rawIn_normDist_T_71)
node _self_rec_rawIn_normDist_T_73 = mux(_self_rec_rawIn_normDist_T_51, UInt<4>(0hf), _self_rec_rawIn_normDist_T_72)
node _self_rec_rawIn_normDist_T_74 = mux(_self_rec_rawIn_normDist_T_52, UInt<4>(0he), _self_rec_rawIn_normDist_T_73)
node _self_rec_rawIn_normDist_T_75 = mux(_self_rec_rawIn_normDist_T_53, UInt<4>(0hd), _self_rec_rawIn_normDist_T_74)
node _self_rec_rawIn_normDist_T_76 = mux(_self_rec_rawIn_normDist_T_54, UInt<4>(0hc), _self_rec_rawIn_normDist_T_75)
node _self_rec_rawIn_normDist_T_77 = mux(_self_rec_rawIn_normDist_T_55, UInt<4>(0hb), _self_rec_rawIn_normDist_T_76)
node _self_rec_rawIn_normDist_T_78 = mux(_self_rec_rawIn_normDist_T_56, UInt<4>(0ha), _self_rec_rawIn_normDist_T_77)
node _self_rec_rawIn_normDist_T_79 = mux(_self_rec_rawIn_normDist_T_57, UInt<4>(0h9), _self_rec_rawIn_normDist_T_78)
node _self_rec_rawIn_normDist_T_80 = mux(_self_rec_rawIn_normDist_T_58, UInt<4>(0h8), _self_rec_rawIn_normDist_T_79)
node _self_rec_rawIn_normDist_T_81 = mux(_self_rec_rawIn_normDist_T_59, UInt<3>(0h7), _self_rec_rawIn_normDist_T_80)
node _self_rec_rawIn_normDist_T_82 = mux(_self_rec_rawIn_normDist_T_60, UInt<3>(0h6), _self_rec_rawIn_normDist_T_81)
node _self_rec_rawIn_normDist_T_83 = mux(_self_rec_rawIn_normDist_T_61, UInt<3>(0h5), _self_rec_rawIn_normDist_T_82)
node _self_rec_rawIn_normDist_T_84 = mux(_self_rec_rawIn_normDist_T_62, UInt<3>(0h4), _self_rec_rawIn_normDist_T_83)
node _self_rec_rawIn_normDist_T_85 = mux(_self_rec_rawIn_normDist_T_63, UInt<2>(0h3), _self_rec_rawIn_normDist_T_84)
node _self_rec_rawIn_normDist_T_86 = mux(_self_rec_rawIn_normDist_T_64, UInt<2>(0h2), _self_rec_rawIn_normDist_T_85)
node _self_rec_rawIn_normDist_T_87 = mux(_self_rec_rawIn_normDist_T_65, UInt<1>(0h1), _self_rec_rawIn_normDist_T_86)
node self_rec_rawIn_normDist_1 = mux(_self_rec_rawIn_normDist_T_66, UInt<1>(0h0), _self_rec_rawIn_normDist_T_87)
node _self_rec_rawIn_subnormFract_T_2 = dshl(self_rec_rawIn_fractIn_1, self_rec_rawIn_normDist_1)
node _self_rec_rawIn_subnormFract_T_3 = bits(_self_rec_rawIn_subnormFract_T_2, 21, 0)
node self_rec_rawIn_subnormFract_1 = shl(_self_rec_rawIn_subnormFract_T_3, 1)
node _self_rec_rawIn_adjustedExp_T_5 = xor(self_rec_rawIn_normDist_1, UInt<9>(0h1ff))
node _self_rec_rawIn_adjustedExp_T_6 = mux(self_rec_rawIn_isZeroExpIn_1, _self_rec_rawIn_adjustedExp_T_5, self_rec_rawIn_expIn_1)
node _self_rec_rawIn_adjustedExp_T_7 = mux(self_rec_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1))
node _self_rec_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _self_rec_rawIn_adjustedExp_T_7)
node _self_rec_rawIn_adjustedExp_T_9 = add(_self_rec_rawIn_adjustedExp_T_6, _self_rec_rawIn_adjustedExp_T_8)
node self_rec_rawIn_adjustedExp_1 = tail(_self_rec_rawIn_adjustedExp_T_9, 1)
node self_rec_rawIn_isZero_1 = and(self_rec_rawIn_isZeroExpIn_1, self_rec_rawIn_isZeroFractIn_1)
node _self_rec_rawIn_isSpecial_T_1 = bits(self_rec_rawIn_adjustedExp_1, 8, 7)
node self_rec_rawIn_isSpecial_1 = eq(_self_rec_rawIn_isSpecial_T_1, UInt<2>(0h3))
wire self_rec_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _self_rec_rawIn_out_isNaN_T_2 = eq(self_rec_rawIn_isZeroFractIn_1, UInt<1>(0h0))
node _self_rec_rawIn_out_isNaN_T_3 = and(self_rec_rawIn_isSpecial_1, _self_rec_rawIn_out_isNaN_T_2)
connect self_rec_rawIn_1.isNaN, _self_rec_rawIn_out_isNaN_T_3
node _self_rec_rawIn_out_isInf_T_1 = and(self_rec_rawIn_isSpecial_1, self_rec_rawIn_isZeroFractIn_1)
connect self_rec_rawIn_1.isInf, _self_rec_rawIn_out_isInf_T_1
connect self_rec_rawIn_1.isZero, self_rec_rawIn_isZero_1
connect self_rec_rawIn_1.sign, self_rec_rawIn_sign_1
node _self_rec_rawIn_out_sExp_T_2 = bits(self_rec_rawIn_adjustedExp_1, 8, 0)
node _self_rec_rawIn_out_sExp_T_3 = cvt(_self_rec_rawIn_out_sExp_T_2)
connect self_rec_rawIn_1.sExp, _self_rec_rawIn_out_sExp_T_3
node _self_rec_rawIn_out_sig_T_4 = eq(self_rec_rawIn_isZero_1, UInt<1>(0h0))
node _self_rec_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _self_rec_rawIn_out_sig_T_4)
node _self_rec_rawIn_out_sig_T_6 = mux(self_rec_rawIn_isZeroExpIn_1, self_rec_rawIn_subnormFract_1, self_rec_rawIn_fractIn_1)
node _self_rec_rawIn_out_sig_T_7 = cat(_self_rec_rawIn_out_sig_T_5, _self_rec_rawIn_out_sig_T_6)
connect self_rec_rawIn_1.sig, _self_rec_rawIn_out_sig_T_7
node _self_rec_T_8 = bits(self_rec_rawIn_1.sExp, 8, 6)
node _self_rec_T_9 = mux(self_rec_rawIn_1.isZero, UInt<3>(0h0), _self_rec_T_8)
node _self_rec_T_10 = mux(self_rec_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _self_rec_T_11 = or(_self_rec_T_9, _self_rec_T_10)
node _self_rec_T_12 = cat(self_rec_rawIn_1.sign, _self_rec_T_11)
node _self_rec_T_13 = bits(self_rec_rawIn_1.sExp, 5, 0)
node _self_rec_T_14 = cat(_self_rec_T_12, _self_rec_T_13)
node _self_rec_T_15 = bits(self_rec_rawIn_1.sig, 22, 0)
node self_rec_1 = cat(_self_rec_T_14, _self_rec_T_15)
inst resizer_1 of RecFNToRecFN_257
connect resizer_1.io.in, self_rec_1
connect resizer_1.io.roundingMode, UInt<3>(0h0)
connect resizer_1.io.detectTininess, UInt<1>(0h1)
wire result_1 : { bits : UInt<32>}
node result_bits_rawIn_exp_1 = bits(resizer_1.io.out, 31, 23)
node _result_bits_rawIn_isZero_T_1 = bits(result_bits_rawIn_exp_1, 8, 6)
node result_bits_rawIn_isZero_1 = eq(_result_bits_rawIn_isZero_T_1, UInt<1>(0h0))
node _result_bits_rawIn_isSpecial_T_1 = bits(result_bits_rawIn_exp_1, 8, 7)
node result_bits_rawIn_isSpecial_1 = eq(_result_bits_rawIn_isSpecial_T_1, UInt<2>(0h3))
wire result_bits_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _result_bits_rawIn_out_isNaN_T_2 = bits(result_bits_rawIn_exp_1, 6, 6)
node _result_bits_rawIn_out_isNaN_T_3 = and(result_bits_rawIn_isSpecial_1, _result_bits_rawIn_out_isNaN_T_2)
connect result_bits_rawIn_1.isNaN, _result_bits_rawIn_out_isNaN_T_3
node _result_bits_rawIn_out_isInf_T_3 = bits(result_bits_rawIn_exp_1, 6, 6)
node _result_bits_rawIn_out_isInf_T_4 = eq(_result_bits_rawIn_out_isInf_T_3, UInt<1>(0h0))
node _result_bits_rawIn_out_isInf_T_5 = and(result_bits_rawIn_isSpecial_1, _result_bits_rawIn_out_isInf_T_4)
connect result_bits_rawIn_1.isInf, _result_bits_rawIn_out_isInf_T_5
connect result_bits_rawIn_1.isZero, result_bits_rawIn_isZero_1
node _result_bits_rawIn_out_sign_T_1 = bits(resizer_1.io.out, 32, 32)
connect result_bits_rawIn_1.sign, _result_bits_rawIn_out_sign_T_1
node _result_bits_rawIn_out_sExp_T_1 = cvt(result_bits_rawIn_exp_1)
connect result_bits_rawIn_1.sExp, _result_bits_rawIn_out_sExp_T_1
node _result_bits_rawIn_out_sig_T_4 = eq(result_bits_rawIn_isZero_1, UInt<1>(0h0))
node _result_bits_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _result_bits_rawIn_out_sig_T_4)
node _result_bits_rawIn_out_sig_T_6 = bits(resizer_1.io.out, 22, 0)
node _result_bits_rawIn_out_sig_T_7 = cat(_result_bits_rawIn_out_sig_T_5, _result_bits_rawIn_out_sig_T_6)
connect result_bits_rawIn_1.sig, _result_bits_rawIn_out_sig_T_7
node result_bits_isSubnormal_1 = lt(result_bits_rawIn_1.sExp, asSInt(UInt<9>(0h82)))
node _result_bits_denormShiftDist_T_2 = bits(result_bits_rawIn_1.sExp, 4, 0)
node _result_bits_denormShiftDist_T_3 = sub(UInt<1>(0h1), _result_bits_denormShiftDist_T_2)
node result_bits_denormShiftDist_1 = tail(_result_bits_denormShiftDist_T_3, 1)
node _result_bits_denormFract_T_2 = shr(result_bits_rawIn_1.sig, 1)
node _result_bits_denormFract_T_3 = dshr(_result_bits_denormFract_T_2, result_bits_denormShiftDist_1)
node result_bits_denormFract_1 = bits(_result_bits_denormFract_T_3, 22, 0)
node _result_bits_expOut_T_6 = bits(result_bits_rawIn_1.sExp, 7, 0)
node _result_bits_expOut_T_7 = sub(_result_bits_expOut_T_6, UInt<8>(0h81))
node _result_bits_expOut_T_8 = tail(_result_bits_expOut_T_7, 1)
node _result_bits_expOut_T_9 = mux(result_bits_isSubnormal_1, UInt<1>(0h0), _result_bits_expOut_T_8)
node _result_bits_expOut_T_10 = or(result_bits_rawIn_1.isNaN, result_bits_rawIn_1.isInf)
node _result_bits_expOut_T_11 = mux(_result_bits_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0))
node result_bits_expOut_1 = or(_result_bits_expOut_T_9, _result_bits_expOut_T_11)
node _result_bits_fractOut_T_2 = bits(result_bits_rawIn_1.sig, 22, 0)
node _result_bits_fractOut_T_3 = mux(result_bits_rawIn_1.isInf, UInt<1>(0h0), _result_bits_fractOut_T_2)
node result_bits_fractOut_1 = mux(result_bits_isSubnormal_1, result_bits_denormFract_1, _result_bits_fractOut_T_3)
node result_bits_hi_1 = cat(result_bits_rawIn_1.sign, result_bits_expOut_1)
node _result_bits_T_1 = cat(result_bits_hi_1, result_bits_fractOut_1)
connect result_1.bits, _result_bits_T_1
wire _WIRE_18 : { bits : UInt<32>}[1]
connect _WIRE_18[0], result_1
node self_rec_rawIn_sign_2 = bits(mesh.io.resp.bits.data[2][0].bits, 31, 31)
node self_rec_rawIn_expIn_2 = bits(mesh.io.resp.bits.data[2][0].bits, 30, 23)
node self_rec_rawIn_fractIn_2 = bits(mesh.io.resp.bits.data[2][0].bits, 22, 0)
node self_rec_rawIn_isZeroExpIn_2 = eq(self_rec_rawIn_expIn_2, UInt<1>(0h0))
node self_rec_rawIn_isZeroFractIn_2 = eq(self_rec_rawIn_fractIn_2, UInt<1>(0h0))
node _self_rec_rawIn_normDist_T_88 = bits(self_rec_rawIn_fractIn_2, 0, 0)
node _self_rec_rawIn_normDist_T_89 = bits(self_rec_rawIn_fractIn_2, 1, 1)
node _self_rec_rawIn_normDist_T_90 = bits(self_rec_rawIn_fractIn_2, 2, 2)
node _self_rec_rawIn_normDist_T_91 = bits(self_rec_rawIn_fractIn_2, 3, 3)
node _self_rec_rawIn_normDist_T_92 = bits(self_rec_rawIn_fractIn_2, 4, 4)
node _self_rec_rawIn_normDist_T_93 = bits(self_rec_rawIn_fractIn_2, 5, 5)
node _self_rec_rawIn_normDist_T_94 = bits(self_rec_rawIn_fractIn_2, 6, 6)
node _self_rec_rawIn_normDist_T_95 = bits(self_rec_rawIn_fractIn_2, 7, 7)
node _self_rec_rawIn_normDist_T_96 = bits(self_rec_rawIn_fractIn_2, 8, 8)
node _self_rec_rawIn_normDist_T_97 = bits(self_rec_rawIn_fractIn_2, 9, 9)
node _self_rec_rawIn_normDist_T_98 = bits(self_rec_rawIn_fractIn_2, 10, 10)
node _self_rec_rawIn_normDist_T_99 = bits(self_rec_rawIn_fractIn_2, 11, 11)
node _self_rec_rawIn_normDist_T_100 = bits(self_rec_rawIn_fractIn_2, 12, 12)
node _self_rec_rawIn_normDist_T_101 = bits(self_rec_rawIn_fractIn_2, 13, 13)
node _self_rec_rawIn_normDist_T_102 = bits(self_rec_rawIn_fractIn_2, 14, 14)
node _self_rec_rawIn_normDist_T_103 = bits(self_rec_rawIn_fractIn_2, 15, 15)
node _self_rec_rawIn_normDist_T_104 = bits(self_rec_rawIn_fractIn_2, 16, 16)
node _self_rec_rawIn_normDist_T_105 = bits(self_rec_rawIn_fractIn_2, 17, 17)
node _self_rec_rawIn_normDist_T_106 = bits(self_rec_rawIn_fractIn_2, 18, 18)
node _self_rec_rawIn_normDist_T_107 = bits(self_rec_rawIn_fractIn_2, 19, 19)
node _self_rec_rawIn_normDist_T_108 = bits(self_rec_rawIn_fractIn_2, 20, 20)
node _self_rec_rawIn_normDist_T_109 = bits(self_rec_rawIn_fractIn_2, 21, 21)
node _self_rec_rawIn_normDist_T_110 = bits(self_rec_rawIn_fractIn_2, 22, 22)
node _self_rec_rawIn_normDist_T_111 = mux(_self_rec_rawIn_normDist_T_89, UInt<5>(0h15), UInt<5>(0h16))
node _self_rec_rawIn_normDist_T_112 = mux(_self_rec_rawIn_normDist_T_90, UInt<5>(0h14), _self_rec_rawIn_normDist_T_111)
node _self_rec_rawIn_normDist_T_113 = mux(_self_rec_rawIn_normDist_T_91, UInt<5>(0h13), _self_rec_rawIn_normDist_T_112)
node _self_rec_rawIn_normDist_T_114 = mux(_self_rec_rawIn_normDist_T_92, UInt<5>(0h12), _self_rec_rawIn_normDist_T_113)
node _self_rec_rawIn_normDist_T_115 = mux(_self_rec_rawIn_normDist_T_93, UInt<5>(0h11), _self_rec_rawIn_normDist_T_114)
node _self_rec_rawIn_normDist_T_116 = mux(_self_rec_rawIn_normDist_T_94, UInt<5>(0h10), _self_rec_rawIn_normDist_T_115)
node _self_rec_rawIn_normDist_T_117 = mux(_self_rec_rawIn_normDist_T_95, UInt<4>(0hf), _self_rec_rawIn_normDist_T_116)
node _self_rec_rawIn_normDist_T_118 = mux(_self_rec_rawIn_normDist_T_96, UInt<4>(0he), _self_rec_rawIn_normDist_T_117)
node _self_rec_rawIn_normDist_T_119 = mux(_self_rec_rawIn_normDist_T_97, UInt<4>(0hd), _self_rec_rawIn_normDist_T_118)
node _self_rec_rawIn_normDist_T_120 = mux(_self_rec_rawIn_normDist_T_98, UInt<4>(0hc), _self_rec_rawIn_normDist_T_119)
node _self_rec_rawIn_normDist_T_121 = mux(_self_rec_rawIn_normDist_T_99, UInt<4>(0hb), _self_rec_rawIn_normDist_T_120)
node _self_rec_rawIn_normDist_T_122 = mux(_self_rec_rawIn_normDist_T_100, UInt<4>(0ha), _self_rec_rawIn_normDist_T_121)
node _self_rec_rawIn_normDist_T_123 = mux(_self_rec_rawIn_normDist_T_101, UInt<4>(0h9), _self_rec_rawIn_normDist_T_122)
node _self_rec_rawIn_normDist_T_124 = mux(_self_rec_rawIn_normDist_T_102, UInt<4>(0h8), _self_rec_rawIn_normDist_T_123)
node _self_rec_rawIn_normDist_T_125 = mux(_self_rec_rawIn_normDist_T_103, UInt<3>(0h7), _self_rec_rawIn_normDist_T_124)
node _self_rec_rawIn_normDist_T_126 = mux(_self_rec_rawIn_normDist_T_104, UInt<3>(0h6), _self_rec_rawIn_normDist_T_125)
node _self_rec_rawIn_normDist_T_127 = mux(_self_rec_rawIn_normDist_T_105, UInt<3>(0h5), _self_rec_rawIn_normDist_T_126)
node _self_rec_rawIn_normDist_T_128 = mux(_self_rec_rawIn_normDist_T_106, UInt<3>(0h4), _self_rec_rawIn_normDist_T_127)
node _self_rec_rawIn_normDist_T_129 = mux(_self_rec_rawIn_normDist_T_107, UInt<2>(0h3), _self_rec_rawIn_normDist_T_128)
node _self_rec_rawIn_normDist_T_130 = mux(_self_rec_rawIn_normDist_T_108, UInt<2>(0h2), _self_rec_rawIn_normDist_T_129)
node _self_rec_rawIn_normDist_T_131 = mux(_self_rec_rawIn_normDist_T_109, UInt<1>(0h1), _self_rec_rawIn_normDist_T_130)
node self_rec_rawIn_normDist_2 = mux(_self_rec_rawIn_normDist_T_110, UInt<1>(0h0), _self_rec_rawIn_normDist_T_131)
node _self_rec_rawIn_subnormFract_T_4 = dshl(self_rec_rawIn_fractIn_2, self_rec_rawIn_normDist_2)
node _self_rec_rawIn_subnormFract_T_5 = bits(_self_rec_rawIn_subnormFract_T_4, 21, 0)
node self_rec_rawIn_subnormFract_2 = shl(_self_rec_rawIn_subnormFract_T_5, 1)
node _self_rec_rawIn_adjustedExp_T_10 = xor(self_rec_rawIn_normDist_2, UInt<9>(0h1ff))
node _self_rec_rawIn_adjustedExp_T_11 = mux(self_rec_rawIn_isZeroExpIn_2, _self_rec_rawIn_adjustedExp_T_10, self_rec_rawIn_expIn_2)
node _self_rec_rawIn_adjustedExp_T_12 = mux(self_rec_rawIn_isZeroExpIn_2, UInt<2>(0h2), UInt<1>(0h1))
node _self_rec_rawIn_adjustedExp_T_13 = or(UInt<8>(0h80), _self_rec_rawIn_adjustedExp_T_12)
node _self_rec_rawIn_adjustedExp_T_14 = add(_self_rec_rawIn_adjustedExp_T_11, _self_rec_rawIn_adjustedExp_T_13)
node self_rec_rawIn_adjustedExp_2 = tail(_self_rec_rawIn_adjustedExp_T_14, 1)
node self_rec_rawIn_isZero_2 = and(self_rec_rawIn_isZeroExpIn_2, self_rec_rawIn_isZeroFractIn_2)
node _self_rec_rawIn_isSpecial_T_2 = bits(self_rec_rawIn_adjustedExp_2, 8, 7)
node self_rec_rawIn_isSpecial_2 = eq(_self_rec_rawIn_isSpecial_T_2, UInt<2>(0h3))
wire self_rec_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _self_rec_rawIn_out_isNaN_T_4 = eq(self_rec_rawIn_isZeroFractIn_2, UInt<1>(0h0))
node _self_rec_rawIn_out_isNaN_T_5 = and(self_rec_rawIn_isSpecial_2, _self_rec_rawIn_out_isNaN_T_4)
connect self_rec_rawIn_2.isNaN, _self_rec_rawIn_out_isNaN_T_5
node _self_rec_rawIn_out_isInf_T_2 = and(self_rec_rawIn_isSpecial_2, self_rec_rawIn_isZeroFractIn_2)
connect self_rec_rawIn_2.isInf, _self_rec_rawIn_out_isInf_T_2
connect self_rec_rawIn_2.isZero, self_rec_rawIn_isZero_2
connect self_rec_rawIn_2.sign, self_rec_rawIn_sign_2
node _self_rec_rawIn_out_sExp_T_4 = bits(self_rec_rawIn_adjustedExp_2, 8, 0)
node _self_rec_rawIn_out_sExp_T_5 = cvt(_self_rec_rawIn_out_sExp_T_4)
connect self_rec_rawIn_2.sExp, _self_rec_rawIn_out_sExp_T_5
node _self_rec_rawIn_out_sig_T_8 = eq(self_rec_rawIn_isZero_2, UInt<1>(0h0))
node _self_rec_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _self_rec_rawIn_out_sig_T_8)
node _self_rec_rawIn_out_sig_T_10 = mux(self_rec_rawIn_isZeroExpIn_2, self_rec_rawIn_subnormFract_2, self_rec_rawIn_fractIn_2)
node _self_rec_rawIn_out_sig_T_11 = cat(_self_rec_rawIn_out_sig_T_9, _self_rec_rawIn_out_sig_T_10)
connect self_rec_rawIn_2.sig, _self_rec_rawIn_out_sig_T_11
node _self_rec_T_16 = bits(self_rec_rawIn_2.sExp, 8, 6)
node _self_rec_T_17 = mux(self_rec_rawIn_2.isZero, UInt<3>(0h0), _self_rec_T_16)
node _self_rec_T_18 = mux(self_rec_rawIn_2.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _self_rec_T_19 = or(_self_rec_T_17, _self_rec_T_18)
node _self_rec_T_20 = cat(self_rec_rawIn_2.sign, _self_rec_T_19)
node _self_rec_T_21 = bits(self_rec_rawIn_2.sExp, 5, 0)
node _self_rec_T_22 = cat(_self_rec_T_20, _self_rec_T_21)
node _self_rec_T_23 = bits(self_rec_rawIn_2.sig, 22, 0)
node self_rec_2 = cat(_self_rec_T_22, _self_rec_T_23)
inst resizer_2 of RecFNToRecFN_258
connect resizer_2.io.in, self_rec_2
connect resizer_2.io.roundingMode, UInt<3>(0h0)
connect resizer_2.io.detectTininess, UInt<1>(0h1)
wire result_2 : { bits : UInt<32>}
node result_bits_rawIn_exp_2 = bits(resizer_2.io.out, 31, 23)
node _result_bits_rawIn_isZero_T_2 = bits(result_bits_rawIn_exp_2, 8, 6)
node result_bits_rawIn_isZero_2 = eq(_result_bits_rawIn_isZero_T_2, UInt<1>(0h0))
node _result_bits_rawIn_isSpecial_T_2 = bits(result_bits_rawIn_exp_2, 8, 7)
node result_bits_rawIn_isSpecial_2 = eq(_result_bits_rawIn_isSpecial_T_2, UInt<2>(0h3))
wire result_bits_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _result_bits_rawIn_out_isNaN_T_4 = bits(result_bits_rawIn_exp_2, 6, 6)
node _result_bits_rawIn_out_isNaN_T_5 = and(result_bits_rawIn_isSpecial_2, _result_bits_rawIn_out_isNaN_T_4)
connect result_bits_rawIn_2.isNaN, _result_bits_rawIn_out_isNaN_T_5
node _result_bits_rawIn_out_isInf_T_6 = bits(result_bits_rawIn_exp_2, 6, 6)
node _result_bits_rawIn_out_isInf_T_7 = eq(_result_bits_rawIn_out_isInf_T_6, UInt<1>(0h0))
node _result_bits_rawIn_out_isInf_T_8 = and(result_bits_rawIn_isSpecial_2, _result_bits_rawIn_out_isInf_T_7)
connect result_bits_rawIn_2.isInf, _result_bits_rawIn_out_isInf_T_8
connect result_bits_rawIn_2.isZero, result_bits_rawIn_isZero_2
node _result_bits_rawIn_out_sign_T_2 = bits(resizer_2.io.out, 32, 32)
connect result_bits_rawIn_2.sign, _result_bits_rawIn_out_sign_T_2
node _result_bits_rawIn_out_sExp_T_2 = cvt(result_bits_rawIn_exp_2)
connect result_bits_rawIn_2.sExp, _result_bits_rawIn_out_sExp_T_2
node _result_bits_rawIn_out_sig_T_8 = eq(result_bits_rawIn_isZero_2, UInt<1>(0h0))
node _result_bits_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _result_bits_rawIn_out_sig_T_8)
node _result_bits_rawIn_out_sig_T_10 = bits(resizer_2.io.out, 22, 0)
node _result_bits_rawIn_out_sig_T_11 = cat(_result_bits_rawIn_out_sig_T_9, _result_bits_rawIn_out_sig_T_10)
connect result_bits_rawIn_2.sig, _result_bits_rawIn_out_sig_T_11
node result_bits_isSubnormal_2 = lt(result_bits_rawIn_2.sExp, asSInt(UInt<9>(0h82)))
node _result_bits_denormShiftDist_T_4 = bits(result_bits_rawIn_2.sExp, 4, 0)
node _result_bits_denormShiftDist_T_5 = sub(UInt<1>(0h1), _result_bits_denormShiftDist_T_4)
node result_bits_denormShiftDist_2 = tail(_result_bits_denormShiftDist_T_5, 1)
node _result_bits_denormFract_T_4 = shr(result_bits_rawIn_2.sig, 1)
node _result_bits_denormFract_T_5 = dshr(_result_bits_denormFract_T_4, result_bits_denormShiftDist_2)
node result_bits_denormFract_2 = bits(_result_bits_denormFract_T_5, 22, 0)
node _result_bits_expOut_T_12 = bits(result_bits_rawIn_2.sExp, 7, 0)
node _result_bits_expOut_T_13 = sub(_result_bits_expOut_T_12, UInt<8>(0h81))
node _result_bits_expOut_T_14 = tail(_result_bits_expOut_T_13, 1)
node _result_bits_expOut_T_15 = mux(result_bits_isSubnormal_2, UInt<1>(0h0), _result_bits_expOut_T_14)
node _result_bits_expOut_T_16 = or(result_bits_rawIn_2.isNaN, result_bits_rawIn_2.isInf)
node _result_bits_expOut_T_17 = mux(_result_bits_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0))
node result_bits_expOut_2 = or(_result_bits_expOut_T_15, _result_bits_expOut_T_17)
node _result_bits_fractOut_T_4 = bits(result_bits_rawIn_2.sig, 22, 0)
node _result_bits_fractOut_T_5 = mux(result_bits_rawIn_2.isInf, UInt<1>(0h0), _result_bits_fractOut_T_4)
node result_bits_fractOut_2 = mux(result_bits_isSubnormal_2, result_bits_denormFract_2, _result_bits_fractOut_T_5)
node result_bits_hi_2 = cat(result_bits_rawIn_2.sign, result_bits_expOut_2)
node _result_bits_T_2 = cat(result_bits_hi_2, result_bits_fractOut_2)
connect result_2.bits, _result_bits_T_2
wire _WIRE_19 : { bits : UInt<32>}[1]
connect _WIRE_19[0], result_2
node self_rec_rawIn_sign_3 = bits(mesh.io.resp.bits.data[3][0].bits, 31, 31)
node self_rec_rawIn_expIn_3 = bits(mesh.io.resp.bits.data[3][0].bits, 30, 23)
node self_rec_rawIn_fractIn_3 = bits(mesh.io.resp.bits.data[3][0].bits, 22, 0)
node self_rec_rawIn_isZeroExpIn_3 = eq(self_rec_rawIn_expIn_3, UInt<1>(0h0))
node self_rec_rawIn_isZeroFractIn_3 = eq(self_rec_rawIn_fractIn_3, UInt<1>(0h0))
node _self_rec_rawIn_normDist_T_132 = bits(self_rec_rawIn_fractIn_3, 0, 0)
node _self_rec_rawIn_normDist_T_133 = bits(self_rec_rawIn_fractIn_3, 1, 1)
node _self_rec_rawIn_normDist_T_134 = bits(self_rec_rawIn_fractIn_3, 2, 2)
node _self_rec_rawIn_normDist_T_135 = bits(self_rec_rawIn_fractIn_3, 3, 3)
node _self_rec_rawIn_normDist_T_136 = bits(self_rec_rawIn_fractIn_3, 4, 4)
node _self_rec_rawIn_normDist_T_137 = bits(self_rec_rawIn_fractIn_3, 5, 5)
node _self_rec_rawIn_normDist_T_138 = bits(self_rec_rawIn_fractIn_3, 6, 6)
node _self_rec_rawIn_normDist_T_139 = bits(self_rec_rawIn_fractIn_3, 7, 7)
node _self_rec_rawIn_normDist_T_140 = bits(self_rec_rawIn_fractIn_3, 8, 8)
node _self_rec_rawIn_normDist_T_141 = bits(self_rec_rawIn_fractIn_3, 9, 9)
node _self_rec_rawIn_normDist_T_142 = bits(self_rec_rawIn_fractIn_3, 10, 10)
node _self_rec_rawIn_normDist_T_143 = bits(self_rec_rawIn_fractIn_3, 11, 11)
node _self_rec_rawIn_normDist_T_144 = bits(self_rec_rawIn_fractIn_3, 12, 12)
node _self_rec_rawIn_normDist_T_145 = bits(self_rec_rawIn_fractIn_3, 13, 13)
node _self_rec_rawIn_normDist_T_146 = bits(self_rec_rawIn_fractIn_3, 14, 14)
node _self_rec_rawIn_normDist_T_147 = bits(self_rec_rawIn_fractIn_3, 15, 15)
node _self_rec_rawIn_normDist_T_148 = bits(self_rec_rawIn_fractIn_3, 16, 16)
node _self_rec_rawIn_normDist_T_149 = bits(self_rec_rawIn_fractIn_3, 17, 17)
node _self_rec_rawIn_normDist_T_150 = bits(self_rec_rawIn_fractIn_3, 18, 18)
node _self_rec_rawIn_normDist_T_151 = bits(self_rec_rawIn_fractIn_3, 19, 19)
node _self_rec_rawIn_normDist_T_152 = bits(self_rec_rawIn_fractIn_3, 20, 20)
node _self_rec_rawIn_normDist_T_153 = bits(self_rec_rawIn_fractIn_3, 21, 21)
node _self_rec_rawIn_normDist_T_154 = bits(self_rec_rawIn_fractIn_3, 22, 22)
node _self_rec_rawIn_normDist_T_155 = mux(_self_rec_rawIn_normDist_T_133, UInt<5>(0h15), UInt<5>(0h16))
node _self_rec_rawIn_normDist_T_156 = mux(_self_rec_rawIn_normDist_T_134, UInt<5>(0h14), _self_rec_rawIn_normDist_T_155)
node _self_rec_rawIn_normDist_T_157 = mux(_self_rec_rawIn_normDist_T_135, UInt<5>(0h13), _self_rec_rawIn_normDist_T_156)
node _self_rec_rawIn_normDist_T_158 = mux(_self_rec_rawIn_normDist_T_136, UInt<5>(0h12), _self_rec_rawIn_normDist_T_157)
node _self_rec_rawIn_normDist_T_159 = mux(_self_rec_rawIn_normDist_T_137, UInt<5>(0h11), _self_rec_rawIn_normDist_T_158)
node _self_rec_rawIn_normDist_T_160 = mux(_self_rec_rawIn_normDist_T_138, UInt<5>(0h10), _self_rec_rawIn_normDist_T_159)
node _self_rec_rawIn_normDist_T_161 = mux(_self_rec_rawIn_normDist_T_139, UInt<4>(0hf), _self_rec_rawIn_normDist_T_160)
node _self_rec_rawIn_normDist_T_162 = mux(_self_rec_rawIn_normDist_T_140, UInt<4>(0he), _self_rec_rawIn_normDist_T_161)
node _self_rec_rawIn_normDist_T_163 = mux(_self_rec_rawIn_normDist_T_141, UInt<4>(0hd), _self_rec_rawIn_normDist_T_162)
node _self_rec_rawIn_normDist_T_164 = mux(_self_rec_rawIn_normDist_T_142, UInt<4>(0hc), _self_rec_rawIn_normDist_T_163)
node _self_rec_rawIn_normDist_T_165 = mux(_self_rec_rawIn_normDist_T_143, UInt<4>(0hb), _self_rec_rawIn_normDist_T_164)
node _self_rec_rawIn_normDist_T_166 = mux(_self_rec_rawIn_normDist_T_144, UInt<4>(0ha), _self_rec_rawIn_normDist_T_165)
node _self_rec_rawIn_normDist_T_167 = mux(_self_rec_rawIn_normDist_T_145, UInt<4>(0h9), _self_rec_rawIn_normDist_T_166)
node _self_rec_rawIn_normDist_T_168 = mux(_self_rec_rawIn_normDist_T_146, UInt<4>(0h8), _self_rec_rawIn_normDist_T_167)
node _self_rec_rawIn_normDist_T_169 = mux(_self_rec_rawIn_normDist_T_147, UInt<3>(0h7), _self_rec_rawIn_normDist_T_168)
node _self_rec_rawIn_normDist_T_170 = mux(_self_rec_rawIn_normDist_T_148, UInt<3>(0h6), _self_rec_rawIn_normDist_T_169)
node _self_rec_rawIn_normDist_T_171 = mux(_self_rec_rawIn_normDist_T_149, UInt<3>(0h5), _self_rec_rawIn_normDist_T_170)
node _self_rec_rawIn_normDist_T_172 = mux(_self_rec_rawIn_normDist_T_150, UInt<3>(0h4), _self_rec_rawIn_normDist_T_171)
node _self_rec_rawIn_normDist_T_173 = mux(_self_rec_rawIn_normDist_T_151, UInt<2>(0h3), _self_rec_rawIn_normDist_T_172)
node _self_rec_rawIn_normDist_T_174 = mux(_self_rec_rawIn_normDist_T_152, UInt<2>(0h2), _self_rec_rawIn_normDist_T_173)
node _self_rec_rawIn_normDist_T_175 = mux(_self_rec_rawIn_normDist_T_153, UInt<1>(0h1), _self_rec_rawIn_normDist_T_174)
node self_rec_rawIn_normDist_3 = mux(_self_rec_rawIn_normDist_T_154, UInt<1>(0h0), _self_rec_rawIn_normDist_T_175)
node _self_rec_rawIn_subnormFract_T_6 = dshl(self_rec_rawIn_fractIn_3, self_rec_rawIn_normDist_3)
node _self_rec_rawIn_subnormFract_T_7 = bits(_self_rec_rawIn_subnormFract_T_6, 21, 0)
node self_rec_rawIn_subnormFract_3 = shl(_self_rec_rawIn_subnormFract_T_7, 1)
node _self_rec_rawIn_adjustedExp_T_15 = xor(self_rec_rawIn_normDist_3, UInt<9>(0h1ff))
node _self_rec_rawIn_adjustedExp_T_16 = mux(self_rec_rawIn_isZeroExpIn_3, _self_rec_rawIn_adjustedExp_T_15, self_rec_rawIn_expIn_3)
node _self_rec_rawIn_adjustedExp_T_17 = mux(self_rec_rawIn_isZeroExpIn_3, UInt<2>(0h2), UInt<1>(0h1))
node _self_rec_rawIn_adjustedExp_T_18 = or(UInt<8>(0h80), _self_rec_rawIn_adjustedExp_T_17)
node _self_rec_rawIn_adjustedExp_T_19 = add(_self_rec_rawIn_adjustedExp_T_16, _self_rec_rawIn_adjustedExp_T_18)
node self_rec_rawIn_adjustedExp_3 = tail(_self_rec_rawIn_adjustedExp_T_19, 1)
node self_rec_rawIn_isZero_3 = and(self_rec_rawIn_isZeroExpIn_3, self_rec_rawIn_isZeroFractIn_3)
node _self_rec_rawIn_isSpecial_T_3 = bits(self_rec_rawIn_adjustedExp_3, 8, 7)
node self_rec_rawIn_isSpecial_3 = eq(_self_rec_rawIn_isSpecial_T_3, UInt<2>(0h3))
wire self_rec_rawIn_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _self_rec_rawIn_out_isNaN_T_6 = eq(self_rec_rawIn_isZeroFractIn_3, UInt<1>(0h0))
node _self_rec_rawIn_out_isNaN_T_7 = and(self_rec_rawIn_isSpecial_3, _self_rec_rawIn_out_isNaN_T_6)
connect self_rec_rawIn_3.isNaN, _self_rec_rawIn_out_isNaN_T_7
node _self_rec_rawIn_out_isInf_T_3 = and(self_rec_rawIn_isSpecial_3, self_rec_rawIn_isZeroFractIn_3)
connect self_rec_rawIn_3.isInf, _self_rec_rawIn_out_isInf_T_3
connect self_rec_rawIn_3.isZero, self_rec_rawIn_isZero_3
connect self_rec_rawIn_3.sign, self_rec_rawIn_sign_3
node _self_rec_rawIn_out_sExp_T_6 = bits(self_rec_rawIn_adjustedExp_3, 8, 0)
node _self_rec_rawIn_out_sExp_T_7 = cvt(_self_rec_rawIn_out_sExp_T_6)
connect self_rec_rawIn_3.sExp, _self_rec_rawIn_out_sExp_T_7
node _self_rec_rawIn_out_sig_T_12 = eq(self_rec_rawIn_isZero_3, UInt<1>(0h0))
node _self_rec_rawIn_out_sig_T_13 = cat(UInt<1>(0h0), _self_rec_rawIn_out_sig_T_12)
node _self_rec_rawIn_out_sig_T_14 = mux(self_rec_rawIn_isZeroExpIn_3, self_rec_rawIn_subnormFract_3, self_rec_rawIn_fractIn_3)
node _self_rec_rawIn_out_sig_T_15 = cat(_self_rec_rawIn_out_sig_T_13, _self_rec_rawIn_out_sig_T_14)
connect self_rec_rawIn_3.sig, _self_rec_rawIn_out_sig_T_15
node _self_rec_T_24 = bits(self_rec_rawIn_3.sExp, 8, 6)
node _self_rec_T_25 = mux(self_rec_rawIn_3.isZero, UInt<3>(0h0), _self_rec_T_24)
node _self_rec_T_26 = mux(self_rec_rawIn_3.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _self_rec_T_27 = or(_self_rec_T_25, _self_rec_T_26)
node _self_rec_T_28 = cat(self_rec_rawIn_3.sign, _self_rec_T_27)
node _self_rec_T_29 = bits(self_rec_rawIn_3.sExp, 5, 0)
node _self_rec_T_30 = cat(_self_rec_T_28, _self_rec_T_29)
node _self_rec_T_31 = bits(self_rec_rawIn_3.sig, 22, 0)
node self_rec_3 = cat(_self_rec_T_30, _self_rec_T_31)
inst resizer_3 of RecFNToRecFN_259
connect resizer_3.io.in, self_rec_3
connect resizer_3.io.roundingMode, UInt<3>(0h0)
connect resizer_3.io.detectTininess, UInt<1>(0h1)
wire result_3 : { bits : UInt<32>}
node result_bits_rawIn_exp_3 = bits(resizer_3.io.out, 31, 23)
node _result_bits_rawIn_isZero_T_3 = bits(result_bits_rawIn_exp_3, 8, 6)
node result_bits_rawIn_isZero_3 = eq(_result_bits_rawIn_isZero_T_3, UInt<1>(0h0))
node _result_bits_rawIn_isSpecial_T_3 = bits(result_bits_rawIn_exp_3, 8, 7)
node result_bits_rawIn_isSpecial_3 = eq(_result_bits_rawIn_isSpecial_T_3, UInt<2>(0h3))
wire result_bits_rawIn_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _result_bits_rawIn_out_isNaN_T_6 = bits(result_bits_rawIn_exp_3, 6, 6)
node _result_bits_rawIn_out_isNaN_T_7 = and(result_bits_rawIn_isSpecial_3, _result_bits_rawIn_out_isNaN_T_6)
connect result_bits_rawIn_3.isNaN, _result_bits_rawIn_out_isNaN_T_7
node _result_bits_rawIn_out_isInf_T_9 = bits(result_bits_rawIn_exp_3, 6, 6)
node _result_bits_rawIn_out_isInf_T_10 = eq(_result_bits_rawIn_out_isInf_T_9, UInt<1>(0h0))
node _result_bits_rawIn_out_isInf_T_11 = and(result_bits_rawIn_isSpecial_3, _result_bits_rawIn_out_isInf_T_10)
connect result_bits_rawIn_3.isInf, _result_bits_rawIn_out_isInf_T_11
connect result_bits_rawIn_3.isZero, result_bits_rawIn_isZero_3
node _result_bits_rawIn_out_sign_T_3 = bits(resizer_3.io.out, 32, 32)
connect result_bits_rawIn_3.sign, _result_bits_rawIn_out_sign_T_3
node _result_bits_rawIn_out_sExp_T_3 = cvt(result_bits_rawIn_exp_3)
connect result_bits_rawIn_3.sExp, _result_bits_rawIn_out_sExp_T_3
node _result_bits_rawIn_out_sig_T_12 = eq(result_bits_rawIn_isZero_3, UInt<1>(0h0))
node _result_bits_rawIn_out_sig_T_13 = cat(UInt<1>(0h0), _result_bits_rawIn_out_sig_T_12)
node _result_bits_rawIn_out_sig_T_14 = bits(resizer_3.io.out, 22, 0)
node _result_bits_rawIn_out_sig_T_15 = cat(_result_bits_rawIn_out_sig_T_13, _result_bits_rawIn_out_sig_T_14)
connect result_bits_rawIn_3.sig, _result_bits_rawIn_out_sig_T_15
node result_bits_isSubnormal_3 = lt(result_bits_rawIn_3.sExp, asSInt(UInt<9>(0h82)))
node _result_bits_denormShiftDist_T_6 = bits(result_bits_rawIn_3.sExp, 4, 0)
node _result_bits_denormShiftDist_T_7 = sub(UInt<1>(0h1), _result_bits_denormShiftDist_T_6)
node result_bits_denormShiftDist_3 = tail(_result_bits_denormShiftDist_T_7, 1)
node _result_bits_denormFract_T_6 = shr(result_bits_rawIn_3.sig, 1)
node _result_bits_denormFract_T_7 = dshr(_result_bits_denormFract_T_6, result_bits_denormShiftDist_3)
node result_bits_denormFract_3 = bits(_result_bits_denormFract_T_7, 22, 0)
node _result_bits_expOut_T_18 = bits(result_bits_rawIn_3.sExp, 7, 0)
node _result_bits_expOut_T_19 = sub(_result_bits_expOut_T_18, UInt<8>(0h81))
node _result_bits_expOut_T_20 = tail(_result_bits_expOut_T_19, 1)
node _result_bits_expOut_T_21 = mux(result_bits_isSubnormal_3, UInt<1>(0h0), _result_bits_expOut_T_20)
node _result_bits_expOut_T_22 = or(result_bits_rawIn_3.isNaN, result_bits_rawIn_3.isInf)
node _result_bits_expOut_T_23 = mux(_result_bits_expOut_T_22, UInt<8>(0hff), UInt<8>(0h0))
node result_bits_expOut_3 = or(_result_bits_expOut_T_21, _result_bits_expOut_T_23)
node _result_bits_fractOut_T_6 = bits(result_bits_rawIn_3.sig, 22, 0)
node _result_bits_fractOut_T_7 = mux(result_bits_rawIn_3.isInf, UInt<1>(0h0), _result_bits_fractOut_T_6)
node result_bits_fractOut_3 = mux(result_bits_isSubnormal_3, result_bits_denormFract_3, _result_bits_fractOut_T_7)
node result_bits_hi_3 = cat(result_bits_rawIn_3.sign, result_bits_expOut_3)
node _result_bits_T_3 = cat(result_bits_hi_3, result_bits_fractOut_3)
connect result_3.bits, _result_bits_T_3
wire _WIRE_20 : { bits : UInt<32>}[1]
connect _WIRE_20[0], result_3
wire _WIRE_21 : { bits : UInt<32>}[1][4]
connect _WIRE_21[0], _WIRE_17
connect _WIRE_21[1], _WIRE_18
connect _WIRE_21[2], _WIRE_19
connect _WIRE_21[3], _WIRE_20
connect io.acc.write[0].bits.data, _WIRE_21
connect io.acc.write[0].bits.acc, w_address.accumulate
connect io.acc.write[0].bits.mask[0], w_mask_0
connect io.acc.write[0].bits.mask[1], w_mask_0
connect io.acc.write[0].bits.mask[2], w_mask_0
connect io.acc.write[0].bits.mask[3], w_mask_0
connect io.acc.write[0].bits.mask[4], w_mask_1
connect io.acc.write[0].bits.mask[5], w_mask_1
connect io.acc.write[0].bits.mask[6], w_mask_1
connect io.acc.write[0].bits.mask[7], w_mask_1
connect io.acc.write[0].bits.mask[8], w_mask_2
connect io.acc.write[0].bits.mask[9], w_mask_2
connect io.acc.write[0].bits.mask[10], w_mask_2
connect io.acc.write[0].bits.mask[11], w_mask_2
connect io.acc.write[0].bits.mask[12], w_mask_3
connect io.acc.write[0].bits.mask[13], w_mask_3
connect io.acc.write[0].bits.mask[14], w_mask_3
connect io.acc.write[0].bits.mask[15], w_mask_3
node _T_191 = eq(io.acc.write[0].ready, UInt<1>(0h0))
node _T_192 = and(io.acc.write[0].valid, _T_191)
node _T_193 = eq(_T_192, UInt<1>(0h0))
node _T_194 = asUInt(reset)
node _T_195 = eq(_T_194, UInt<1>(0h0))
when _T_195 :
node _T_196 = eq(_T_193, UInt<1>(0h0))
when _T_196 :
printf(clock, UInt<1>(0h1), "Assertion failed: Execute controller write to AccumulatorMem was skipped\n at ExecuteController.scala:962 assert(!(io.acc.write(i).valid && !io.acc.write(i).ready), \"Execute controller write to AccumulatorMem was skipped\")\n") : printf_1
assert(clock, _T_193, UInt<1>(0h1), "") : assert_1
wire mesh_completed_rob_id_fire : UInt<1>
connect mesh_completed_rob_id_fire, UInt<1>(0h0)
node _T_197 = and(mesh.io.resp.valid, mesh.io.resp.bits.tag.rob_id.valid)
when _T_197 :
node _output_counter_max_T = sub(mesh.io.resp.bits.total_rows, UInt<1>(0h1))
node output_counter_max = tail(_output_counter_max_T, 1)
node _output_counter_T = leq(UInt<1>(0h1), output_counter_max)
node _output_counter_T_1 = eq(output_counter_max, UInt<1>(0h0))
node _output_counter_T_2 = or(_output_counter_T, _output_counter_T_1)
node _output_counter_T_3 = asUInt(reset)
node _output_counter_T_4 = eq(_output_counter_T_3, UInt<1>(0h0))
when _output_counter_T_4 :
node _output_counter_T_5 = eq(_output_counter_T_2, UInt<1>(0h0))
when _output_counter_T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed: cannot wrapAdd when n is larger than max, unless max is 0\n at Util.scala:19 assert(n <= max || max === 0.U, \"cannot wrapAdd when n is larger than max, unless max is 0\")\n") : output_counter_printf
assert(clock, _output_counter_T_2, UInt<1>(0h1), "") : output_counter_assert
node _output_counter_T_6 = add(output_counter, UInt<1>(0h1))
node _output_counter_T_7 = tail(_output_counter_T_6, 1)
node _output_counter_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _output_counter_T_9 = eq(output_counter_max, UInt<1>(0h0))
node _output_counter_T_10 = sub(output_counter_max, UInt<1>(0h1))
node _output_counter_T_11 = tail(_output_counter_T_10, 1)
node _output_counter_T_12 = add(_output_counter_T_11, UInt<1>(0h1))
node _output_counter_T_13 = tail(_output_counter_T_12, 1)
node _output_counter_T_14 = geq(output_counter, _output_counter_T_13)
node _output_counter_T_15 = neq(UInt<1>(0h1), UInt<1>(0h0))
node _output_counter_T_16 = and(_output_counter_T_14, _output_counter_T_15)
node _output_counter_T_17 = sub(output_counter_max, output_counter)
node _output_counter_T_18 = tail(_output_counter_T_17, 1)
node _output_counter_T_19 = sub(UInt<1>(0h1), _output_counter_T_18)
node _output_counter_T_20 = tail(_output_counter_T_19, 1)
node _output_counter_T_21 = sub(_output_counter_T_20, UInt<1>(0h1))
node _output_counter_T_22 = tail(_output_counter_T_21, 1)
node _output_counter_T_23 = mux(_output_counter_T_16, _output_counter_T_22, _output_counter_T_7)
node _output_counter_T_24 = mux(_output_counter_T_9, UInt<1>(0h0), _output_counter_T_23)
node _output_counter_T_25 = mux(_output_counter_T_8, output_counter, _output_counter_T_24)
connect output_counter, _output_counter_T_25
when mesh.io.resp.bits.last :
connect mesh_completed_rob_id_fire, UInt<1>(0h1)
connect io.completed.valid, UInt<1>(0h1)
connect io.completed.bits, mesh.io.resp.bits.tag.rob_id.bits
node _start_array_outputting_T = eq(is_garbage_addr, UInt<1>(0h0))
connect start_array_outputting, _start_array_outputting_T
node _T_198 = eq(mesh_completed_rob_id_fire, UInt<1>(0h0))
when _T_198 :
when pending_completed_rob_ids[0].valid :
connect io.completed.valid, UInt<1>(0h1)
connect pending_completed_rob_ids[0].valid, UInt<1>(0h0)
connect io.completed.bits, pending_completed_rob_ids[0].bits
else :
when pending_completed_rob_ids[1].valid :
connect io.completed.valid, UInt<1>(0h1)
connect pending_completed_rob_ids[1].valid, UInt<1>(0h0)
connect io.completed.bits, pending_completed_rob_ids[1].bits
regreset complete_bits_count : UInt<15>, clock, reset, UInt<15>(0h0)
when io.completed.valid :
node _complete_bits_count_T = add(complete_bits_count, UInt<1>(0h1))
node _complete_bits_count_T_1 = tail(_complete_bits_count_T, 1)
connect complete_bits_count, _complete_bits_count_T_1
node _T_199 = asUInt(reset)
when _T_199 :
connect pending_completed_rob_ids[0].valid, UInt<1>(0h0)
connect pending_completed_rob_ids[1].valid, UInt<1>(0h0)
wire _WIRE_22 : UInt<1>[45]
connect _WIRE_22[0], UInt<1>(0h0)
connect _WIRE_22[1], UInt<1>(0h0)
connect _WIRE_22[2], UInt<1>(0h0)
connect _WIRE_22[3], UInt<1>(0h0)
connect _WIRE_22[4], UInt<1>(0h0)
connect _WIRE_22[5], UInt<1>(0h0)
connect _WIRE_22[6], UInt<1>(0h0)
connect _WIRE_22[7], UInt<1>(0h0)
connect _WIRE_22[8], UInt<1>(0h0)
connect _WIRE_22[9], UInt<1>(0h0)
connect _WIRE_22[10], UInt<1>(0h0)
connect _WIRE_22[11], UInt<1>(0h0)
connect _WIRE_22[12], UInt<1>(0h0)
connect _WIRE_22[13], UInt<1>(0h0)
connect _WIRE_22[14], UInt<1>(0h0)
connect _WIRE_22[15], UInt<1>(0h0)
connect _WIRE_22[16], UInt<1>(0h0)
connect _WIRE_22[17], UInt<1>(0h0)
connect _WIRE_22[18], UInt<1>(0h0)
connect _WIRE_22[19], UInt<1>(0h0)
connect _WIRE_22[20], UInt<1>(0h0)
connect _WIRE_22[21], UInt<1>(0h0)
connect _WIRE_22[22], UInt<1>(0h0)
connect _WIRE_22[23], UInt<1>(0h0)
connect _WIRE_22[24], UInt<1>(0h0)
connect _WIRE_22[25], UInt<1>(0h0)
connect _WIRE_22[26], UInt<1>(0h0)
connect _WIRE_22[27], UInt<1>(0h0)
connect _WIRE_22[28], UInt<1>(0h0)
connect _WIRE_22[29], UInt<1>(0h0)
connect _WIRE_22[30], UInt<1>(0h0)
connect _WIRE_22[31], UInt<1>(0h0)
connect _WIRE_22[32], UInt<1>(0h0)
connect _WIRE_22[33], UInt<1>(0h0)
connect _WIRE_22[34], UInt<1>(0h0)
connect _WIRE_22[35], UInt<1>(0h0)
connect _WIRE_22[36], UInt<1>(0h0)
connect _WIRE_22[37], UInt<1>(0h0)
connect _WIRE_22[38], UInt<1>(0h0)
connect _WIRE_22[39], UInt<1>(0h0)
connect _WIRE_22[40], UInt<1>(0h0)
connect _WIRE_22[41], UInt<1>(0h0)
connect _WIRE_22[42], UInt<1>(0h0)
connect _WIRE_22[43], UInt<1>(0h0)
connect _WIRE_22[44], UInt<1>(0h0)
connect io.counter.event_signal, _WIRE_22
wire _WIRE_23 : UInt<32>[8]
connect _WIRE_23[0], UInt<32>(0h0)
connect _WIRE_23[1], UInt<32>(0h0)
connect _WIRE_23[2], UInt<32>(0h0)
connect _WIRE_23[3], UInt<32>(0h0)
connect _WIRE_23[4], UInt<32>(0h0)
connect _WIRE_23[5], UInt<32>(0h0)
connect _WIRE_23[6], UInt<32>(0h0)
connect _WIRE_23[7], UInt<32>(0h0)
connect io.counter.external_values, _WIRE_23
node _T_200 = eq(control_state, UInt<2>(0h1))
connect io.counter.event_signal[24], _T_200
node _T_201 = eq(control_state, UInt<2>(0h3))
node _T_202 = eq(control_state, UInt<2>(0h2))
node _T_203 = or(_T_201, _T_202)
connect io.counter.event_signal[25], _T_203
node _T_204 = eq(mesh_cntl_signals_q.io.enq.ready, UInt<1>(0h0))
node _T_205 = and(_T_204, mesh_cntl_signals_q.io.enq.valid)
connect io.counter.event_signal[26], _T_205
node _T_206 = and(cmd_q.io.deq.valid[0], DoPreloads_0)
node _T_207 = and(_T_206, cmd_q.io.deq.valid[1])
node _T_208 = and(_T_207, raw_hazard_pre)
connect io.counter.event_signal[27], _T_208
node _T_209 = and(cmd_q.io.deq.valid[0], DoPreloads_1)
node _T_210 = and(_T_209, cmd_q.io.deq.valid[1])
node _T_211 = and(_T_210, DoComputes_0)
node _T_212 = and(_T_211, cmd_q.io.deq.valid[2])
node _T_213 = and(_T_212, raw_hazard_mulpre)
connect io.counter.event_signal[28], _T_213
connect io.counter.event_signal[35], mesh_cntl_signals_q.io.deq.bits.a_garbage
connect io.counter.event_signal[36], mesh_cntl_signals_q.io.deq.bits.b_garbage
connect io.counter.event_signal[37], mesh_cntl_signals_q.io.deq.bits.d_garbage
node _T_214 = eq(mesh_cntl_signals_q.io.deq.bits.a_fire, UInt<1>(0h0))
node _T_215 = and(mesh.io.a.ready, mesh.io.a.valid)
node _T_216 = or(_T_214, _T_215)
node _T_217 = eq(mesh.io.a.ready, UInt<1>(0h0))
node _T_218 = or(_T_216, _T_217)
node _T_219 = eq(_T_218, UInt<1>(0h0))
node _T_220 = and(_T_219, mesh_cntl_signals_q.io.deq.bits.a_read_from_acc)
node _T_221 = eq(mesh_cntl_signals_q.io.deq.bits.im2colling, UInt<1>(0h0))
node _T_222 = and(_T_220, _T_221)
connect io.counter.event_signal[32], _T_222
node _T_223 = eq(mesh_cntl_signals_q.io.deq.bits.b_fire, UInt<1>(0h0))
node _T_224 = and(mesh.io.b.ready, mesh.io.b.valid)
node _T_225 = or(_T_223, _T_224)
node _T_226 = eq(mesh.io.b.ready, UInt<1>(0h0))
node _T_227 = or(_T_225, _T_226)
node _T_228 = eq(_T_227, UInt<1>(0h0))
node _T_229 = and(_T_228, mesh_cntl_signals_q.io.deq.bits.b_read_from_acc)
connect io.counter.event_signal[33], _T_229
node _T_230 = eq(mesh_cntl_signals_q.io.deq.bits.d_fire, UInt<1>(0h0))
node _T_231 = and(mesh.io.d.ready, mesh.io.d.valid)
node _T_232 = or(_T_230, _T_231)
node _T_233 = eq(mesh.io.d.ready, UInt<1>(0h0))
node _T_234 = or(_T_232, _T_233)
node _T_235 = eq(_T_234, UInt<1>(0h0))
node _T_236 = and(_T_235, mesh_cntl_signals_q.io.deq.bits.d_read_from_acc)
connect io.counter.event_signal[34], _T_236
node _T_237 = eq(mesh_cntl_signals_q.io.deq.bits.a_fire, UInt<1>(0h0))
node _T_238 = and(mesh.io.a.ready, mesh.io.a.valid)
node _T_239 = or(_T_237, _T_238)
node _T_240 = eq(mesh.io.a.ready, UInt<1>(0h0))
node _T_241 = or(_T_239, _T_240)
node _T_242 = eq(_T_241, UInt<1>(0h0))
node _T_243 = eq(mesh_cntl_signals_q.io.deq.bits.a_read_from_acc, UInt<1>(0h0))
node _T_244 = and(_T_242, _T_243)
node _T_245 = eq(mesh_cntl_signals_q.io.deq.bits.im2colling, UInt<1>(0h0))
node _T_246 = and(_T_244, _T_245)
connect io.counter.event_signal[29], _T_246
node _T_247 = eq(mesh_cntl_signals_q.io.deq.bits.b_fire, UInt<1>(0h0))
node _T_248 = and(mesh.io.b.ready, mesh.io.b.valid)
node _T_249 = or(_T_247, _T_248)
node _T_250 = eq(mesh.io.b.ready, UInt<1>(0h0))
node _T_251 = or(_T_249, _T_250)
node _T_252 = eq(_T_251, UInt<1>(0h0))
node _T_253 = eq(mesh_cntl_signals_q.io.deq.bits.b_read_from_acc, UInt<1>(0h0))
node _T_254 = and(_T_252, _T_253)
connect io.counter.event_signal[30], _T_254
node _T_255 = eq(mesh_cntl_signals_q.io.deq.bits.d_fire, UInt<1>(0h0))
node _T_256 = and(mesh.io.d.ready, mesh.io.d.valid)
node _T_257 = or(_T_255, _T_256)
node _T_258 = eq(mesh.io.d.ready, UInt<1>(0h0))
node _T_259 = or(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = eq(mesh_cntl_signals_q.io.deq.bits.d_read_from_acc, UInt<1>(0h0))
node _T_262 = and(_T_260, _T_261)
connect io.counter.event_signal[31], _T_262 | module ExecuteController( // @[ExecuteController.scala:12:7]
input clock, // @[ExecuteController.scala:12:7]
input reset, // @[ExecuteController.scala:12:7]
output io_cmd_ready, // @[ExecuteController.scala:17:14]
input io_cmd_valid, // @[ExecuteController.scala:17:14]
input [6:0] io_cmd_bits_cmd_inst_funct, // @[ExecuteController.scala:17:14]
input [4:0] io_cmd_bits_cmd_inst_rs2, // @[ExecuteController.scala:17:14]
input [4:0] io_cmd_bits_cmd_inst_rs1, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_inst_xd, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_inst_xs1, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_inst_xs2, // @[ExecuteController.scala:17:14]
input [4:0] io_cmd_bits_cmd_inst_rd, // @[ExecuteController.scala:17:14]
input [6:0] io_cmd_bits_cmd_inst_opcode, // @[ExecuteController.scala:17:14]
input [63:0] io_cmd_bits_cmd_rs1, // @[ExecuteController.scala:17:14]
input [63:0] io_cmd_bits_cmd_rs2, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_debug, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_cease, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_wfi, // @[ExecuteController.scala:17:14]
input [31:0] io_cmd_bits_cmd_status_isa, // @[ExecuteController.scala:17:14]
input [1:0] io_cmd_bits_cmd_status_dprv, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_dv, // @[ExecuteController.scala:17:14]
input [1:0] io_cmd_bits_cmd_status_prv, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_v, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_sd, // @[ExecuteController.scala:17:14]
input [22:0] io_cmd_bits_cmd_status_zero2, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_mpv, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_gva, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_mbe, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_sbe, // @[ExecuteController.scala:17:14]
input [1:0] io_cmd_bits_cmd_status_sxl, // @[ExecuteController.scala:17:14]
input [1:0] io_cmd_bits_cmd_status_uxl, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_sd_rv32, // @[ExecuteController.scala:17:14]
input [7:0] io_cmd_bits_cmd_status_zero1, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_tsr, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_tw, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_tvm, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_mxr, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_sum, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_mprv, // @[ExecuteController.scala:17:14]
input [1:0] io_cmd_bits_cmd_status_xs, // @[ExecuteController.scala:17:14]
input [1:0] io_cmd_bits_cmd_status_fs, // @[ExecuteController.scala:17:14]
input [1:0] io_cmd_bits_cmd_status_mpp, // @[ExecuteController.scala:17:14]
input [1:0] io_cmd_bits_cmd_status_vs, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_spp, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_mpie, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_ube, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_spie, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_upie, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_mie, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_hie, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_sie, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_uie, // @[ExecuteController.scala:17:14]
input [5:0] io_cmd_bits_rob_id_bits, // @[ExecuteController.scala:17:14]
input io_cmd_bits_from_matmul_fsm, // @[ExecuteController.scala:17:14]
input io_cmd_bits_from_conv_fsm, // @[ExecuteController.scala:17:14]
output io_im2col_req_bits_addr_is_acc_addr, // @[ExecuteController.scala:17:14]
output io_im2col_req_bits_addr_accumulate, // @[ExecuteController.scala:17:14]
output io_im2col_req_bits_addr_read_full_acc_row, // @[ExecuteController.scala:17:14]
output [2:0] io_im2col_req_bits_addr_norm_cmd, // @[ExecuteController.scala:17:14]
output [10:0] io_im2col_req_bits_addr_garbage, // @[ExecuteController.scala:17:14]
output io_im2col_req_bits_addr_garbage_bit, // @[ExecuteController.scala:17:14]
output [13:0] io_im2col_req_bits_addr_data, // @[ExecuteController.scala:17:14]
output [7:0] io_im2col_req_bits_ocol, // @[ExecuteController.scala:17:14]
output [3:0] io_im2col_req_bits_krow, // @[ExecuteController.scala:17:14]
output [8:0] io_im2col_req_bits_icol, // @[ExecuteController.scala:17:14]
output [8:0] io_im2col_req_bits_irow, // @[ExecuteController.scala:17:14]
output [2:0] io_im2col_req_bits_stride, // @[ExecuteController.scala:17:14]
output [8:0] io_im2col_req_bits_channel, // @[ExecuteController.scala:17:14]
output [10:0] io_im2col_req_bits_row_turn, // @[ExecuteController.scala:17:14]
output [7:0] io_im2col_req_bits_kdim2, // @[ExecuteController.scala:17:14]
output [3:0] io_im2col_req_bits_row_left, // @[ExecuteController.scala:17:14]
output io_im2col_req_bits_weight_double_bank, // @[ExecuteController.scala:17:14]
output io_im2col_req_bits_weight_triple_bank, // @[ExecuteController.scala:17:14]
output io_im2col_req_bits_start_inputting, // @[ExecuteController.scala:17:14]
output io_im2col_resp_ready, // @[ExecuteController.scala:17:14]
input [31:0] io_im2col_resp_bits_a_im2col_0_bits, // @[ExecuteController.scala:17:14]
input [31:0] io_im2col_resp_bits_a_im2col_1_bits, // @[ExecuteController.scala:17:14]
input [31:0] io_im2col_resp_bits_a_im2col_2_bits, // @[ExecuteController.scala:17:14]
input [31:0] io_im2col_resp_bits_a_im2col_3_bits, // @[ExecuteController.scala:17:14]
input io_im2col_resp_bits_im2col_end, // @[ExecuteController.scala:17:14]
input [8:0] io_im2col_resp_bits_im2col_turn, // @[ExecuteController.scala:17:14]
input [6:0] io_im2col_resp_bits_row_turn, // @[ExecuteController.scala:17:14]
input io_srams_read_0_req_ready, // @[ExecuteController.scala:17:14]
output io_srams_read_0_req_valid, // @[ExecuteController.scala:17:14]
output [11:0] io_srams_read_0_req_bits_addr, // @[ExecuteController.scala:17:14]
output io_srams_read_0_resp_ready, // @[ExecuteController.scala:17:14]
input io_srams_read_0_resp_valid, // @[ExecuteController.scala:17:14]
input [127:0] io_srams_read_0_resp_bits_data, // @[ExecuteController.scala:17:14]
input io_srams_read_0_resp_bits_fromDMA, // @[ExecuteController.scala:17:14]
input io_srams_read_1_req_ready, // @[ExecuteController.scala:17:14]
output io_srams_read_1_req_valid, // @[ExecuteController.scala:17:14]
output [11:0] io_srams_read_1_req_bits_addr, // @[ExecuteController.scala:17:14]
output io_srams_read_1_resp_ready, // @[ExecuteController.scala:17:14]
input io_srams_read_1_resp_valid, // @[ExecuteController.scala:17:14]
input [127:0] io_srams_read_1_resp_bits_data, // @[ExecuteController.scala:17:14]
input io_srams_read_1_resp_bits_fromDMA, // @[ExecuteController.scala:17:14]
input io_srams_read_2_req_ready, // @[ExecuteController.scala:17:14]
output io_srams_read_2_req_valid, // @[ExecuteController.scala:17:14]
output [11:0] io_srams_read_2_req_bits_addr, // @[ExecuteController.scala:17:14]
output io_srams_read_2_resp_ready, // @[ExecuteController.scala:17:14]
input io_srams_read_2_resp_valid, // @[ExecuteController.scala:17:14]
input [127:0] io_srams_read_2_resp_bits_data, // @[ExecuteController.scala:17:14]
input io_srams_read_2_resp_bits_fromDMA, // @[ExecuteController.scala:17:14]
input io_srams_read_3_req_ready, // @[ExecuteController.scala:17:14]
output io_srams_read_3_req_valid, // @[ExecuteController.scala:17:14]
output [11:0] io_srams_read_3_req_bits_addr, // @[ExecuteController.scala:17:14]
output io_srams_read_3_resp_ready, // @[ExecuteController.scala:17:14]
input io_srams_read_3_resp_valid, // @[ExecuteController.scala:17:14]
input [127:0] io_srams_read_3_resp_bits_data, // @[ExecuteController.scala:17:14]
input io_srams_read_3_resp_bits_fromDMA, // @[ExecuteController.scala:17:14]
output io_srams_write_0_en, // @[ExecuteController.scala:17:14]
output [11:0] io_srams_write_0_addr, // @[ExecuteController.scala:17:14]
output io_srams_write_0_mask_0, // @[ExecuteController.scala:17:14]
output io_srams_write_0_mask_1, // @[ExecuteController.scala:17:14]
output io_srams_write_0_mask_2, // @[ExecuteController.scala:17:14]
output io_srams_write_0_mask_3, // @[ExecuteController.scala:17:14]
output io_srams_write_0_mask_4, // @[ExecuteController.scala:17:14]
output io_srams_write_0_mask_5, // @[ExecuteController.scala:17:14]
output io_srams_write_0_mask_6, // @[ExecuteController.scala:17:14]
output io_srams_write_0_mask_7, // @[ExecuteController.scala:17:14]
output io_srams_write_0_mask_8, // @[ExecuteController.scala:17:14]
output io_srams_write_0_mask_9, // @[ExecuteController.scala:17:14]
output io_srams_write_0_mask_10, // @[ExecuteController.scala:17:14]
output io_srams_write_0_mask_11, // @[ExecuteController.scala:17:14]
output io_srams_write_0_mask_12, // @[ExecuteController.scala:17:14]
output io_srams_write_0_mask_13, // @[ExecuteController.scala:17:14]
output io_srams_write_0_mask_14, // @[ExecuteController.scala:17:14]
output io_srams_write_0_mask_15, // @[ExecuteController.scala:17:14]
output [127:0] io_srams_write_0_data, // @[ExecuteController.scala:17:14]
output io_srams_write_1_en, // @[ExecuteController.scala:17:14]
output [11:0] io_srams_write_1_addr, // @[ExecuteController.scala:17:14]
output io_srams_write_1_mask_0, // @[ExecuteController.scala:17:14]
output io_srams_write_1_mask_1, // @[ExecuteController.scala:17:14]
output io_srams_write_1_mask_2, // @[ExecuteController.scala:17:14]
output io_srams_write_1_mask_3, // @[ExecuteController.scala:17:14]
output io_srams_write_1_mask_4, // @[ExecuteController.scala:17:14]
output io_srams_write_1_mask_5, // @[ExecuteController.scala:17:14]
output io_srams_write_1_mask_6, // @[ExecuteController.scala:17:14]
output io_srams_write_1_mask_7, // @[ExecuteController.scala:17:14]
output io_srams_write_1_mask_8, // @[ExecuteController.scala:17:14]
output io_srams_write_1_mask_9, // @[ExecuteController.scala:17:14]
output io_srams_write_1_mask_10, // @[ExecuteController.scala:17:14]
output io_srams_write_1_mask_11, // @[ExecuteController.scala:17:14]
output io_srams_write_1_mask_12, // @[ExecuteController.scala:17:14]
output io_srams_write_1_mask_13, // @[ExecuteController.scala:17:14]
output io_srams_write_1_mask_14, // @[ExecuteController.scala:17:14]
output io_srams_write_1_mask_15, // @[ExecuteController.scala:17:14]
output [127:0] io_srams_write_1_data, // @[ExecuteController.scala:17:14]
output io_srams_write_2_en, // @[ExecuteController.scala:17:14]
output [11:0] io_srams_write_2_addr, // @[ExecuteController.scala:17:14]
output io_srams_write_2_mask_0, // @[ExecuteController.scala:17:14]
output io_srams_write_2_mask_1, // @[ExecuteController.scala:17:14]
output io_srams_write_2_mask_2, // @[ExecuteController.scala:17:14]
output io_srams_write_2_mask_3, // @[ExecuteController.scala:17:14]
output io_srams_write_2_mask_4, // @[ExecuteController.scala:17:14]
output io_srams_write_2_mask_5, // @[ExecuteController.scala:17:14]
output io_srams_write_2_mask_6, // @[ExecuteController.scala:17:14]
output io_srams_write_2_mask_7, // @[ExecuteController.scala:17:14]
output io_srams_write_2_mask_8, // @[ExecuteController.scala:17:14]
output io_srams_write_2_mask_9, // @[ExecuteController.scala:17:14]
output io_srams_write_2_mask_10, // @[ExecuteController.scala:17:14]
output io_srams_write_2_mask_11, // @[ExecuteController.scala:17:14]
output io_srams_write_2_mask_12, // @[ExecuteController.scala:17:14]
output io_srams_write_2_mask_13, // @[ExecuteController.scala:17:14]
output io_srams_write_2_mask_14, // @[ExecuteController.scala:17:14]
output io_srams_write_2_mask_15, // @[ExecuteController.scala:17:14]
output [127:0] io_srams_write_2_data, // @[ExecuteController.scala:17:14]
output io_srams_write_3_en, // @[ExecuteController.scala:17:14]
output [11:0] io_srams_write_3_addr, // @[ExecuteController.scala:17:14]
output io_srams_write_3_mask_0, // @[ExecuteController.scala:17:14]
output io_srams_write_3_mask_1, // @[ExecuteController.scala:17:14]
output io_srams_write_3_mask_2, // @[ExecuteController.scala:17:14]
output io_srams_write_3_mask_3, // @[ExecuteController.scala:17:14]
output io_srams_write_3_mask_4, // @[ExecuteController.scala:17:14]
output io_srams_write_3_mask_5, // @[ExecuteController.scala:17:14]
output io_srams_write_3_mask_6, // @[ExecuteController.scala:17:14]
output io_srams_write_3_mask_7, // @[ExecuteController.scala:17:14]
output io_srams_write_3_mask_8, // @[ExecuteController.scala:17:14]
output io_srams_write_3_mask_9, // @[ExecuteController.scala:17:14]
output io_srams_write_3_mask_10, // @[ExecuteController.scala:17:14]
output io_srams_write_3_mask_11, // @[ExecuteController.scala:17:14]
output io_srams_write_3_mask_12, // @[ExecuteController.scala:17:14]
output io_srams_write_3_mask_13, // @[ExecuteController.scala:17:14]
output io_srams_write_3_mask_14, // @[ExecuteController.scala:17:14]
output io_srams_write_3_mask_15, // @[ExecuteController.scala:17:14]
output [127:0] io_srams_write_3_data, // @[ExecuteController.scala:17:14]
input io_acc_read_req_0_ready, // @[ExecuteController.scala:17:14]
output io_acc_read_req_0_valid, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_read_req_0_bits_scale_bits, // @[ExecuteController.scala:17:14]
output [11:0] io_acc_read_req_0_bits_addr, // @[ExecuteController.scala:17:14]
output [2:0] io_acc_read_req_0_bits_act, // @[ExecuteController.scala:17:14]
output io_acc_read_resp_0_ready, // @[ExecuteController.scala:17:14]
input io_acc_read_resp_0_valid, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_full_data_0_0_bits, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_full_data_1_0_bits, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_full_data_2_0_bits, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_full_data_3_0_bits, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_data_0_0_bits, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_data_1_0_bits, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_data_2_0_bits, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_data_3_0_bits, // @[ExecuteController.scala:17:14]
input [1:0] io_acc_read_resp_0_bits_acc_bank_id, // @[ExecuteController.scala:17:14]
input io_acc_read_resp_0_bits_fromDMA, // @[ExecuteController.scala:17:14]
output io_acc_write_0_valid, // @[ExecuteController.scala:17:14]
output [11:0] io_acc_write_0_bits_addr, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_0_bits_data_0_0_bits, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_0_bits_data_1_0_bits, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_0_bits_data_2_0_bits, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_0_bits_data_3_0_bits, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_acc, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_0, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_1, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_2, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_3, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_4, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_5, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_6, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_7, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_8, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_9, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_10, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_11, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_12, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_13, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_14, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_15, // @[ExecuteController.scala:17:14]
output io_completed_valid, // @[ExecuteController.scala:17:14]
output [5:0] io_completed_bits, // @[ExecuteController.scala:17:14]
output io_busy, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_24, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_25, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_26, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_27, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_28, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_29, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_30, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_31, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_32, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_33, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_34, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_35, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_36, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_37, // @[ExecuteController.scala:17:14]
input io_counter_external_reset // @[ExecuteController.scala:17:14]
);
wire self_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19]
wire self_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19]
wire self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19]
wire self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_15_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_14_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_13_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_12_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_11_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_10_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_9_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_8_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_7_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_6_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_5_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_4_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire mesh_io_d_valid; // @[ExecuteController.scala:191:19, :873:21, :877:21]
wire mesh_io_b_valid; // @[ExecuteController.scala:190:19, :873:21, :876:21]
wire mesh_io_a_valid; // @[ExecuteController.scala:189:19, :873:21, :875:21]
wire in_prop_flush_qual2_garbage_bit; // @[ExecuteController.scala:666:47]
wire in_prop_flush_qual1_garbage_bit; // @[ExecuteController.scala:647:47]
wire c_address_rs2_garbage_bit; // @[ExecuteController.scala:142:55]
wire d_address_rs1_garbage_bit; // @[ExecuteController.scala:141:55]
wire [10:0] d_address_rs1_garbage; // @[ExecuteController.scala:141:55]
wire [2:0] d_address_rs1_norm_cmd; // @[ExecuteController.scala:141:55]
wire d_address_rs1_read_full_acc_row; // @[ExecuteController.scala:141:55]
wire d_address_rs1_accumulate; // @[ExecuteController.scala:141:55]
wire d_address_rs1_is_acc_addr; // @[ExecuteController.scala:141:55]
wire b_address_rs2_garbage_bit; // @[ExecuteController.scala:140:53]
wire [10:0] b_address_rs2_garbage; // @[ExecuteController.scala:140:53]
wire [2:0] b_address_rs2_norm_cmd; // @[ExecuteController.scala:140:53]
wire b_address_rs2_read_full_acc_row; // @[ExecuteController.scala:140:53]
wire b_address_rs2_accumulate; // @[ExecuteController.scala:140:53]
wire b_address_rs2_is_acc_addr; // @[ExecuteController.scala:140:53]
wire [63:0] rs2s_0; // @[ExecuteController.scala:81:21]
wire [63:0] rs1s_0; // @[ExecuteController.scala:80:21]
wire [32:0] _resizer_3_io_out; // @[Arithmetic.scala:486:29]
wire [32:0] _resizer_2_io_out; // @[Arithmetic.scala:486:29]
wire [32:0] _resizer_1_io_out; // @[Arithmetic.scala:486:29]
wire [32:0] _resizer_io_out; // @[Arithmetic.scala:486:29]
wire [32:0] _activated_wdata_e_clipped_resizer_15_io_out; // @[Arithmetic.scala:500:29]
wire [32:0] _activated_wdata_e_clipped_resizer_14_io_out; // @[Arithmetic.scala:500:29]
wire [32:0] _activated_wdata_e_clipped_resizer_13_io_out; // @[Arithmetic.scala:500:29]
wire [32:0] _activated_wdata_e_clipped_resizer_12_io_out; // @[Arithmetic.scala:500:29]
wire [32:0] _activated_wdata_e_clipped_resizer_11_io_out; // @[Arithmetic.scala:500:29]
wire [32:0] _activated_wdata_e_clipped_resizer_10_io_out; // @[Arithmetic.scala:500:29]
wire [32:0] _activated_wdata_e_clipped_resizer_9_io_out; // @[Arithmetic.scala:500:29]
wire [32:0] _activated_wdata_e_clipped_resizer_8_io_out; // @[Arithmetic.scala:500:29]
wire [32:0] _activated_wdata_e_clipped_resizer_7_io_out; // @[Arithmetic.scala:500:29]
wire [32:0] _activated_wdata_e_clipped_resizer_6_io_out; // @[Arithmetic.scala:500:29]
wire [32:0] _activated_wdata_e_clipped_resizer_5_io_out; // @[Arithmetic.scala:500:29]
wire [32:0] _activated_wdata_e_clipped_resizer_4_io_out; // @[Arithmetic.scala:500:29]
wire [32:0] _activated_wdata_e_clipped_resizer_3_io_out; // @[Arithmetic.scala:500:29]
wire [32:0] _activated_wdata_e_clipped_resizer_2_io_out; // @[Arithmetic.scala:500:29]
wire [32:0] _activated_wdata_e_clipped_resizer_1_io_out; // @[Arithmetic.scala:500:29]
wire [32:0] _activated_wdata_e_clipped_resizer_io_out; // @[Arithmetic.scala:500:29]
wire _mesh_io_a_ready; // @[ExecuteController.scala:186:20]
wire _mesh_io_b_ready; // @[ExecuteController.scala:186:20]
wire _mesh_io_d_ready; // @[ExecuteController.scala:186:20]
wire _mesh_io_req_ready; // @[ExecuteController.scala:186:20]
wire _mesh_io_resp_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_resp_bits_tag_rob_id_valid; // @[ExecuteController.scala:186:20]
wire [5:0] _mesh_io_resp_bits_tag_rob_id_bits; // @[ExecuteController.scala:186:20]
wire _mesh_io_resp_bits_tag_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_resp_bits_tag_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_resp_bits_tag_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire [2:0] _mesh_io_resp_bits_tag_addr_norm_cmd; // @[ExecuteController.scala:186:20]
wire [10:0] _mesh_io_resp_bits_tag_addr_garbage; // @[ExecuteController.scala:186:20]
wire _mesh_io_resp_bits_tag_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_resp_bits_tag_addr_data; // @[ExecuteController.scala:186:20]
wire [2:0] _mesh_io_resp_bits_tag_rows; // @[ExecuteController.scala:186:20]
wire [2:0] _mesh_io_resp_bits_tag_cols; // @[ExecuteController.scala:186:20]
wire [31:0] _mesh_io_resp_bits_data_0_0_bits; // @[ExecuteController.scala:186:20]
wire [31:0] _mesh_io_resp_bits_data_1_0_bits; // @[ExecuteController.scala:186:20]
wire [31:0] _mesh_io_resp_bits_data_2_0_bits; // @[ExecuteController.scala:186:20]
wire [31:0] _mesh_io_resp_bits_data_3_0_bits; // @[ExecuteController.scala:186:20]
wire [2:0] _mesh_io_resp_bits_total_rows; // @[ExecuteController.scala:186:20]
wire _mesh_io_resp_bits_last; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_0_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_0_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_0_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_0_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_0_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_0_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_1_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_1_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_1_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_1_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_1_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_1_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_2_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_2_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_2_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_2_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_2_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_2_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_3_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_3_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_3_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_3_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_3_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_3_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_4_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_4_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_4_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_4_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_4_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_4_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_5_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_5_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_5_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_5_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_5_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_5_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_6_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_6_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_6_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_6_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_6_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_6_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_7_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_7_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_7_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_7_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_7_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_7_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_8_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_8_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_8_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_8_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_8_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_8_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_9_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_9_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_9_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_9_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_9_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_9_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_10_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_10_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_10_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_10_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_10_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_10_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_11_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_11_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_11_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_11_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_11_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_11_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_12_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_12_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_12_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_12_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_12_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_12_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_13_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_13_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_13_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_13_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_13_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_13_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_14_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_14_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_14_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_14_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_14_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_14_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_15_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_15_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_15_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_15_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_15_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_15_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_cntl_signals_q_io_enq_ready; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_valid; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_perform_mul_pre; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_perform_single_mul; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_perform_single_preload; // @[ExecuteController.scala:178:35]
wire [1:0] _mesh_cntl_signals_q_io_deq_bits_a_bank; // @[ExecuteController.scala:178:35]
wire [1:0] _mesh_cntl_signals_q_io_deq_bits_b_bank; // @[ExecuteController.scala:178:35]
wire [1:0] _mesh_cntl_signals_q_io_deq_bits_d_bank; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_a_read_from_acc; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_b_read_from_acc; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_d_read_from_acc; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_a_garbage; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_b_garbage; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_d_garbage; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_accumulate_zeros; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_preload_zeros; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_a_fire; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_b_fire; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_d_fire; // @[ExecuteController.scala:178:35]
wire [2:0] _mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols; // @[ExecuteController.scala:178:35]
wire [2:0] _mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols; // @[ExecuteController.scala:178:35]
wire [2:0] _mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_c_addr_is_acc_addr; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_c_addr_accumulate; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_c_addr_read_full_acc_row; // @[ExecuteController.scala:178:35]
wire [2:0] _mesh_cntl_signals_q_io_deq_bits_c_addr_norm_cmd; // @[ExecuteController.scala:178:35]
wire [10:0] _mesh_cntl_signals_q_io_deq_bits_c_addr_garbage; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_c_addr_garbage_bit; // @[ExecuteController.scala:178:35]
wire [13:0] _mesh_cntl_signals_q_io_deq_bits_c_addr_data; // @[ExecuteController.scala:178:35]
wire [2:0] _mesh_cntl_signals_q_io_deq_bits_c_rows; // @[ExecuteController.scala:178:35]
wire [2:0] _mesh_cntl_signals_q_io_deq_bits_c_cols; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_a_transpose; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_bd_transpose; // @[ExecuteController.scala:178:35]
wire [2:0] _mesh_cntl_signals_q_io_deq_bits_total_rows; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_rob_id_valid; // @[ExecuteController.scala:178:35]
wire [5:0] _mesh_cntl_signals_q_io_deq_bits_rob_id_bits; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_dataflow; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_prop; // @[ExecuteController.scala:178:35]
wire [4:0] _mesh_cntl_signals_q_io_deq_bits_shift; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_im2colling; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_first; // @[ExecuteController.scala:178:35]
wire _cmd_q_io_enq_ready; // @[MultiHeadedQueue.scala:53:19]
wire _cmd_q_io_deq_valid_0; // @[MultiHeadedQueue.scala:53:19]
wire _cmd_q_io_deq_valid_1; // @[MultiHeadedQueue.scala:53:19]
wire _cmd_q_io_deq_valid_2; // @[MultiHeadedQueue.scala:53:19]
wire [6:0] _cmd_q_io_deq_bits_0_cmd_inst_funct; // @[MultiHeadedQueue.scala:53:19]
wire [63:0] _cmd_q_io_deq_bits_0_cmd_rs1; // @[MultiHeadedQueue.scala:53:19]
wire [63:0] _cmd_q_io_deq_bits_0_cmd_rs2; // @[MultiHeadedQueue.scala:53:19]
wire _cmd_q_io_deq_bits_0_rob_id_valid; // @[MultiHeadedQueue.scala:53:19]
wire [5:0] _cmd_q_io_deq_bits_0_rob_id_bits; // @[MultiHeadedQueue.scala:53:19]
wire [6:0] _cmd_q_io_deq_bits_1_cmd_inst_funct; // @[MultiHeadedQueue.scala:53:19]
wire _cmd_q_io_deq_bits_1_rob_id_valid; // @[MultiHeadedQueue.scala:53:19]
wire [5:0] _cmd_q_io_deq_bits_1_rob_id_bits; // @[MultiHeadedQueue.scala:53:19]
wire [6:0] _cmd_q_io_deq_bits_2_cmd_inst_funct; // @[MultiHeadedQueue.scala:53:19]
wire [5:0] _cmd_q_io_deq_bits_2_rob_id_bits; // @[MultiHeadedQueue.scala:53:19]
wire _unrolled_cmd_mod_io_out_valid; // @[TransposePreloadUnroller.scala:88:21]
wire [6:0] _unrolled_cmd_mod_io_out_bits_cmd_inst_funct; // @[TransposePreloadUnroller.scala:88:21]
wire [4:0] _unrolled_cmd_mod_io_out_bits_cmd_inst_rs2; // @[TransposePreloadUnroller.scala:88:21]
wire [4:0] _unrolled_cmd_mod_io_out_bits_cmd_inst_rs1; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_inst_xd; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_inst_xs1; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_inst_xs2; // @[TransposePreloadUnroller.scala:88:21]
wire [4:0] _unrolled_cmd_mod_io_out_bits_cmd_inst_rd; // @[TransposePreloadUnroller.scala:88:21]
wire [6:0] _unrolled_cmd_mod_io_out_bits_cmd_inst_opcode; // @[TransposePreloadUnroller.scala:88:21]
wire [63:0] _unrolled_cmd_mod_io_out_bits_cmd_rs1; // @[TransposePreloadUnroller.scala:88:21]
wire [63:0] _unrolled_cmd_mod_io_out_bits_cmd_rs2; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_debug; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_cease; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_wfi; // @[TransposePreloadUnroller.scala:88:21]
wire [31:0] _unrolled_cmd_mod_io_out_bits_cmd_status_isa; // @[TransposePreloadUnroller.scala:88:21]
wire [1:0] _unrolled_cmd_mod_io_out_bits_cmd_status_dprv; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_dv; // @[TransposePreloadUnroller.scala:88:21]
wire [1:0] _unrolled_cmd_mod_io_out_bits_cmd_status_prv; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_v; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_sd; // @[TransposePreloadUnroller.scala:88:21]
wire [22:0] _unrolled_cmd_mod_io_out_bits_cmd_status_zero2; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_mpv; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_gva; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_mbe; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_sbe; // @[TransposePreloadUnroller.scala:88:21]
wire [1:0] _unrolled_cmd_mod_io_out_bits_cmd_status_sxl; // @[TransposePreloadUnroller.scala:88:21]
wire [1:0] _unrolled_cmd_mod_io_out_bits_cmd_status_uxl; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_sd_rv32; // @[TransposePreloadUnroller.scala:88:21]
wire [7:0] _unrolled_cmd_mod_io_out_bits_cmd_status_zero1; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_tsr; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_tw; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_tvm; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_mxr; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_sum; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_mprv; // @[TransposePreloadUnroller.scala:88:21]
wire [1:0] _unrolled_cmd_mod_io_out_bits_cmd_status_xs; // @[TransposePreloadUnroller.scala:88:21]
wire [1:0] _unrolled_cmd_mod_io_out_bits_cmd_status_fs; // @[TransposePreloadUnroller.scala:88:21]
wire [1:0] _unrolled_cmd_mod_io_out_bits_cmd_status_mpp; // @[TransposePreloadUnroller.scala:88:21]
wire [1:0] _unrolled_cmd_mod_io_out_bits_cmd_status_vs; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_spp; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_mpie; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_ube; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_spie; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_upie; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_mie; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_hie; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_sie; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_uie; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_rob_id_valid; // @[TransposePreloadUnroller.scala:88:21]
wire [5:0] _unrolled_cmd_mod_io_out_bits_rob_id_bits; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_from_matmul_fsm; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_from_conv_fsm; // @[TransposePreloadUnroller.scala:88:21]
wire io_cmd_valid_0 = io_cmd_valid; // @[ExecuteController.scala:12:7]
wire [6:0] io_cmd_bits_cmd_inst_funct_0 = io_cmd_bits_cmd_inst_funct; // @[ExecuteController.scala:12:7]
wire [4:0] io_cmd_bits_cmd_inst_rs2_0 = io_cmd_bits_cmd_inst_rs2; // @[ExecuteController.scala:12:7]
wire [4:0] io_cmd_bits_cmd_inst_rs1_0 = io_cmd_bits_cmd_inst_rs1; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_inst_xd_0 = io_cmd_bits_cmd_inst_xd; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_inst_xs1_0 = io_cmd_bits_cmd_inst_xs1; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_inst_xs2_0 = io_cmd_bits_cmd_inst_xs2; // @[ExecuteController.scala:12:7]
wire [4:0] io_cmd_bits_cmd_inst_rd_0 = io_cmd_bits_cmd_inst_rd; // @[ExecuteController.scala:12:7]
wire [6:0] io_cmd_bits_cmd_inst_opcode_0 = io_cmd_bits_cmd_inst_opcode; // @[ExecuteController.scala:12:7]
wire [63:0] io_cmd_bits_cmd_rs1_0 = io_cmd_bits_cmd_rs1; // @[ExecuteController.scala:12:7]
wire [63:0] io_cmd_bits_cmd_rs2_0 = io_cmd_bits_cmd_rs2; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_debug_0 = io_cmd_bits_cmd_status_debug; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_cease_0 = io_cmd_bits_cmd_status_cease; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_wfi_0 = io_cmd_bits_cmd_status_wfi; // @[ExecuteController.scala:12:7]
wire [31:0] io_cmd_bits_cmd_status_isa_0 = io_cmd_bits_cmd_status_isa; // @[ExecuteController.scala:12:7]
wire [1:0] io_cmd_bits_cmd_status_dprv_0 = io_cmd_bits_cmd_status_dprv; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_dv_0 = io_cmd_bits_cmd_status_dv; // @[ExecuteController.scala:12:7]
wire [1:0] io_cmd_bits_cmd_status_prv_0 = io_cmd_bits_cmd_status_prv; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_v_0 = io_cmd_bits_cmd_status_v; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_sd_0 = io_cmd_bits_cmd_status_sd; // @[ExecuteController.scala:12:7]
wire [22:0] io_cmd_bits_cmd_status_zero2_0 = io_cmd_bits_cmd_status_zero2; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_mpv_0 = io_cmd_bits_cmd_status_mpv; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_gva_0 = io_cmd_bits_cmd_status_gva; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_mbe_0 = io_cmd_bits_cmd_status_mbe; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_sbe_0 = io_cmd_bits_cmd_status_sbe; // @[ExecuteController.scala:12:7]
wire [1:0] io_cmd_bits_cmd_status_sxl_0 = io_cmd_bits_cmd_status_sxl; // @[ExecuteController.scala:12:7]
wire [1:0] io_cmd_bits_cmd_status_uxl_0 = io_cmd_bits_cmd_status_uxl; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_sd_rv32_0 = io_cmd_bits_cmd_status_sd_rv32; // @[ExecuteController.scala:12:7]
wire [7:0] io_cmd_bits_cmd_status_zero1_0 = io_cmd_bits_cmd_status_zero1; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_tsr_0 = io_cmd_bits_cmd_status_tsr; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_tw_0 = io_cmd_bits_cmd_status_tw; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_tvm_0 = io_cmd_bits_cmd_status_tvm; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_mxr_0 = io_cmd_bits_cmd_status_mxr; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_sum_0 = io_cmd_bits_cmd_status_sum; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_mprv_0 = io_cmd_bits_cmd_status_mprv; // @[ExecuteController.scala:12:7]
wire [1:0] io_cmd_bits_cmd_status_xs_0 = io_cmd_bits_cmd_status_xs; // @[ExecuteController.scala:12:7]
wire [1:0] io_cmd_bits_cmd_status_fs_0 = io_cmd_bits_cmd_status_fs; // @[ExecuteController.scala:12:7]
wire [1:0] io_cmd_bits_cmd_status_mpp_0 = io_cmd_bits_cmd_status_mpp; // @[ExecuteController.scala:12:7]
wire [1:0] io_cmd_bits_cmd_status_vs_0 = io_cmd_bits_cmd_status_vs; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_spp_0 = io_cmd_bits_cmd_status_spp; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_mpie_0 = io_cmd_bits_cmd_status_mpie; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_ube_0 = io_cmd_bits_cmd_status_ube; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_spie_0 = io_cmd_bits_cmd_status_spie; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_upie_0 = io_cmd_bits_cmd_status_upie; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_mie_0 = io_cmd_bits_cmd_status_mie; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_hie_0 = io_cmd_bits_cmd_status_hie; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_sie_0 = io_cmd_bits_cmd_status_sie; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_uie_0 = io_cmd_bits_cmd_status_uie; // @[ExecuteController.scala:12:7]
wire [5:0] io_cmd_bits_rob_id_bits_0 = io_cmd_bits_rob_id_bits; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_from_matmul_fsm_0 = io_cmd_bits_from_matmul_fsm; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_from_conv_fsm_0 = io_cmd_bits_from_conv_fsm; // @[ExecuteController.scala:12:7]
wire [31:0] io_im2col_resp_bits_a_im2col_0_bits_0 = io_im2col_resp_bits_a_im2col_0_bits; // @[ExecuteController.scala:12:7]
wire [31:0] io_im2col_resp_bits_a_im2col_1_bits_0 = io_im2col_resp_bits_a_im2col_1_bits; // @[ExecuteController.scala:12:7]
wire [31:0] io_im2col_resp_bits_a_im2col_2_bits_0 = io_im2col_resp_bits_a_im2col_2_bits; // @[ExecuteController.scala:12:7]
wire [31:0] io_im2col_resp_bits_a_im2col_3_bits_0 = io_im2col_resp_bits_a_im2col_3_bits; // @[ExecuteController.scala:12:7]
wire io_im2col_resp_bits_im2col_end_0 = io_im2col_resp_bits_im2col_end; // @[ExecuteController.scala:12:7]
wire [8:0] io_im2col_resp_bits_im2col_turn_0 = io_im2col_resp_bits_im2col_turn; // @[ExecuteController.scala:12:7]
wire [6:0] io_im2col_resp_bits_row_turn_0 = io_im2col_resp_bits_row_turn; // @[ExecuteController.scala:12:7]
wire io_srams_read_0_req_ready_0 = io_srams_read_0_req_ready; // @[ExecuteController.scala:12:7]
wire io_srams_read_0_resp_valid_0 = io_srams_read_0_resp_valid; // @[ExecuteController.scala:12:7]
wire [127:0] io_srams_read_0_resp_bits_data_0 = io_srams_read_0_resp_bits_data; // @[ExecuteController.scala:12:7]
wire io_srams_read_0_resp_bits_fromDMA_0 = io_srams_read_0_resp_bits_fromDMA; // @[ExecuteController.scala:12:7]
wire io_srams_read_1_req_ready_0 = io_srams_read_1_req_ready; // @[ExecuteController.scala:12:7]
wire io_srams_read_1_resp_valid_0 = io_srams_read_1_resp_valid; // @[ExecuteController.scala:12:7]
wire [127:0] io_srams_read_1_resp_bits_data_0 = io_srams_read_1_resp_bits_data; // @[ExecuteController.scala:12:7]
wire io_srams_read_1_resp_bits_fromDMA_0 = io_srams_read_1_resp_bits_fromDMA; // @[ExecuteController.scala:12:7]
wire io_srams_read_2_req_ready_0 = io_srams_read_2_req_ready; // @[ExecuteController.scala:12:7]
wire io_srams_read_2_resp_valid_0 = io_srams_read_2_resp_valid; // @[ExecuteController.scala:12:7]
wire [127:0] io_srams_read_2_resp_bits_data_0 = io_srams_read_2_resp_bits_data; // @[ExecuteController.scala:12:7]
wire io_srams_read_2_resp_bits_fromDMA_0 = io_srams_read_2_resp_bits_fromDMA; // @[ExecuteController.scala:12:7]
wire io_srams_read_3_req_ready_0 = io_srams_read_3_req_ready; // @[ExecuteController.scala:12:7]
wire io_srams_read_3_resp_valid_0 = io_srams_read_3_resp_valid; // @[ExecuteController.scala:12:7]
wire [127:0] io_srams_read_3_resp_bits_data_0 = io_srams_read_3_resp_bits_data; // @[ExecuteController.scala:12:7]
wire io_srams_read_3_resp_bits_fromDMA_0 = io_srams_read_3_resp_bits_fromDMA; // @[ExecuteController.scala:12:7]
wire io_acc_read_req_0_ready_0 = io_acc_read_req_0_ready; // @[ExecuteController.scala:12:7]
wire io_acc_read_resp_0_valid_0 = io_acc_read_resp_0_valid; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_full_data_0_0_bits_0 = io_acc_read_resp_0_bits_full_data_0_0_bits; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_full_data_1_0_bits_0 = io_acc_read_resp_0_bits_full_data_1_0_bits; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_full_data_2_0_bits_0 = io_acc_read_resp_0_bits_full_data_2_0_bits; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_full_data_3_0_bits_0 = io_acc_read_resp_0_bits_full_data_3_0_bits; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_data_0_0_bits_0 = io_acc_read_resp_0_bits_data_0_0_bits; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_data_1_0_bits_0 = io_acc_read_resp_0_bits_data_1_0_bits; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_data_2_0_bits_0 = io_acc_read_resp_0_bits_data_2_0_bits; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_data_3_0_bits_0 = io_acc_read_resp_0_bits_data_3_0_bits; // @[ExecuteController.scala:12:7]
wire [1:0] io_acc_read_resp_0_bits_acc_bank_id_0 = io_acc_read_resp_0_bits_acc_bank_id; // @[ExecuteController.scala:12:7]
wire io_acc_read_resp_0_bits_fromDMA_0 = io_acc_read_resp_0_bits_fromDMA; // @[ExecuteController.scala:12:7]
wire io_counter_external_reset_0 = io_counter_external_reset; // @[ExecuteController.scala:12:7]
wire _one_ahead_T_3 = reset; // @[Util.scala:19:11]
wire _one_ahead_T_30 = reset; // @[Util.scala:19:11]
wire _one_ahead_T_57 = reset; // @[Util.scala:19:11]
wire _one_ahead_T_84 = reset; // @[Util.scala:19:11]
wire _one_ahead_T_111 = reset; // @[Util.scala:19:11]
wire _one_ahead_T_138 = reset; // @[Util.scala:19:11]
wire _a_fire_counter_T_3 = reset; // @[Util.scala:19:11]
wire _b_fire_counter_T_3 = reset; // @[Util.scala:19:11]
wire _d_fire_counter_T_3 = reset; // @[Util.scala:19:11]
wire _preload_zero_counter_T_7 = reset; // @[Util.scala:19:11]
wire _output_counter_T_3 = reset; // @[Util.scala:19:11]
wire [7:0] _irow_T_1 = 8'hFF; // @[ExecuteController.scala:112:18]
wire [8:0] _irow_T = 9'h1FF; // @[ExecuteController.scala:112:18]
wire io_cmd_bits_rob_id_valid = 1'h1; // @[ExecuteController.scala:12:7]
wire io_im2col_req_ready = 1'h1; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_ready = 1'h1; // @[ExecuteController.scala:12:7]
wire _raw_hazard_pre_T_3 = 1'h1; // @[ExecuteController.scala:217:52]
wire _raw_hazard_pre_T_8 = 1'h1; // @[ExecuteController.scala:217:52]
wire _raw_hazard_pre_T_13 = 1'h1; // @[ExecuteController.scala:217:52]
wire _raw_hazard_pre_T_18 = 1'h1; // @[ExecuteController.scala:217:52]
wire _raw_hazard_pre_T_23 = 1'h1; // @[ExecuteController.scala:217:52]
wire _raw_hazard_pre_T_28 = 1'h1; // @[ExecuteController.scala:217:52]
wire _raw_hazard_pre_T_33 = 1'h1; // @[ExecuteController.scala:217:52]
wire _raw_hazard_pre_T_38 = 1'h1; // @[ExecuteController.scala:217:52]
wire _raw_hazard_pre_T_43 = 1'h1; // @[ExecuteController.scala:217:52]
wire _raw_hazard_pre_T_48 = 1'h1; // @[ExecuteController.scala:217:52]
wire _raw_hazard_pre_T_53 = 1'h1; // @[ExecuteController.scala:217:52]
wire _raw_hazard_pre_T_58 = 1'h1; // @[ExecuteController.scala:217:52]
wire _raw_hazard_pre_T_63 = 1'h1; // @[ExecuteController.scala:217:52]
wire _raw_hazard_pre_T_68 = 1'h1; // @[ExecuteController.scala:217:52]
wire _raw_hazard_pre_T_73 = 1'h1; // @[ExecuteController.scala:217:52]
wire _raw_hazard_pre_T_78 = 1'h1; // @[ExecuteController.scala:217:52]
wire _raw_hazard_mulpre_T_3 = 1'h1; // @[ExecuteController.scala:225:52]
wire _raw_hazard_mulpre_T_8 = 1'h1; // @[ExecuteController.scala:225:52]
wire _raw_hazard_mulpre_T_13 = 1'h1; // @[ExecuteController.scala:225:52]
wire _raw_hazard_mulpre_T_18 = 1'h1; // @[ExecuteController.scala:225:52]
wire _raw_hazard_mulpre_T_23 = 1'h1; // @[ExecuteController.scala:225:52]
wire _raw_hazard_mulpre_T_28 = 1'h1; // @[ExecuteController.scala:225:52]
wire _raw_hazard_mulpre_T_33 = 1'h1; // @[ExecuteController.scala:225:52]
wire _raw_hazard_mulpre_T_38 = 1'h1; // @[ExecuteController.scala:225:52]
wire _raw_hazard_mulpre_T_43 = 1'h1; // @[ExecuteController.scala:225:52]
wire _raw_hazard_mulpre_T_48 = 1'h1; // @[ExecuteController.scala:225:52]
wire _raw_hazard_mulpre_T_53 = 1'h1; // @[ExecuteController.scala:225:52]
wire _raw_hazard_mulpre_T_58 = 1'h1; // @[ExecuteController.scala:225:52]
wire _raw_hazard_mulpre_T_63 = 1'h1; // @[ExecuteController.scala:225:52]
wire _raw_hazard_mulpre_T_68 = 1'h1; // @[ExecuteController.scala:225:52]
wire _raw_hazard_mulpre_T_73 = 1'h1; // @[ExecuteController.scala:225:52]
wire _raw_hazard_mulpre_T_78 = 1'h1; // @[ExecuteController.scala:225:52]
wire _third_instruction_needed_T_5 = 1'h1; // @[ExecuteController.scala:228:111]
wire third_instruction_needed = 1'h1; // @[ExecuteController.scala:228:108]
wire _same_banks_is_being_im2colled_T = 1'h1; // @[ExecuteController.scala:323:49]
wire _same_banks_T_1 = 1'h1; // @[ExecuteController.scala:325:20]
wire _same_banks_is_being_im2colled_T_1 = 1'h1; // @[ExecuteController.scala:323:49]
wire _same_banks_T_13 = 1'h1; // @[ExecuteController.scala:325:20]
wire _one_ahead_T_15 = 1'h1; // @[Util.scala:30:32]
wire _one_ahead_T_42 = 1'h1; // @[Util.scala:30:32]
wire _same_banks_is_being_im2colled_T_2 = 1'h1; // @[ExecuteController.scala:323:49]
wire _same_banks_T_25 = 1'h1; // @[ExecuteController.scala:325:20]
wire _same_banks_T_37 = 1'h1; // @[ExecuteController.scala:325:20]
wire _one_ahead_T_69 = 1'h1; // @[Util.scala:30:32]
wire _one_ahead_T_96 = 1'h1; // @[Util.scala:30:32]
wire _same_banks_is_being_im2colled_T_4 = 1'h1; // @[ExecuteController.scala:323:49]
wire _same_banks_T_49 = 1'h1; // @[ExecuteController.scala:325:20]
wire _same_banks_T_61 = 1'h1; // @[ExecuteController.scala:325:20]
wire _one_ahead_T_123 = 1'h1; // @[Util.scala:30:32]
wire _one_ahead_T_150 = 1'h1; // @[Util.scala:30:32]
wire _a_fire_counter_T_15 = 1'h1; // @[Util.scala:30:32]
wire _b_fire_counter_T_15 = 1'h1; // @[Util.scala:30:32]
wire _d_fire_counter_T_15 = 1'h1; // @[Util.scala:30:32]
wire _read_a_T_9 = 1'h1; // @[ExecuteController.scala:424:138]
wire _read_a_T_19 = 1'h1; // @[ExecuteController.scala:424:138]
wire _read_a_T_29 = 1'h1; // @[ExecuteController.scala:424:138]
wire _read_a_T_39 = 1'h1; // @[ExecuteController.scala:424:138]
wire _read_a_from_acc_T_1 = 1'h1; // @[ExecuteController.scala:458:70]
wire _read_a_from_acc_T_8 = 1'h1; // @[ExecuteController.scala:458:149]
wire _read_b_from_acc_T_1 = 1'h1; // @[ExecuteController.scala:459:70]
wire _read_d_from_acc_T_1 = 1'h1; // @[ExecuteController.scala:460:70]
wire _preload_zero_counter_T_4 = 1'h1; // @[Util.scala:19:14]
wire _preload_zero_counter_T_6 = 1'h1; // @[Util.scala:19:21]
wire _preload_zero_counter_T_19 = 1'h1; // @[Util.scala:30:32]
wire _output_counter_T_15 = 1'h1; // @[Util.scala:30:32]
wire io_im2col_req_valid = 1'h0; // @[ExecuteController.scala:12:7]
wire io_im2col_req_bits_im2col_cmd = 1'h0; // @[ExecuteController.scala:12:7]
wire io_im2col_resp_valid = 1'h0; // @[ExecuteController.scala:12:7]
wire io_im2col_resp_bits_im2col_delay = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_read_0_req_bits_fromDMA = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_read_1_req_bits_fromDMA = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_read_2_req_bits_fromDMA = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_read_3_req_bits_fromDMA = 1'h0; // @[ExecuteController.scala:12:7]
wire io_acc_read_req_0_bits_full = 1'h0; // @[ExecuteController.scala:12:7]
wire io_acc_read_req_0_bits_fromDMA = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_0 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_1 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_2 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_3 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_4 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_5 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_6 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_7 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_8 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_9 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_10 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_11 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_12 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_13 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_14 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_15 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_16 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_17 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_18 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_19 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_20 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_21 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_22 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_23 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_38 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_39 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_40 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_41 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_42 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_43 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_44 = 1'h0; // @[ExecuteController.scala:12:7]
wire im2col_en = 1'h0; // @[ExecuteController.scala:136:38]
wire _third_instruction_needed_T_3 = 1'h0; // @[ExecuteController.scala:228:102]
wire same_banks_is_being_im2colled = 1'h0; // @[ExecuteController.scala:323:64]
wire same_banks_is_being_im2colled_1 = 1'h0; // @[ExecuteController.scala:323:64]
wire _one_ahead_T_8 = 1'h0; // @[Util.scala:28:8]
wire _one_ahead_T_35 = 1'h0; // @[Util.scala:28:8]
wire _must_wait_for_T = 1'h0; // @[ExecuteController.scala:353:13]
wire _must_wait_for_T_1 = 1'h0; // @[ExecuteController.scala:353:19]
wire _must_wait_for_T_2 = 1'h0; // @[ExecuteController.scala:353:13]
wire _must_wait_for_T_3 = 1'h0; // @[ExecuteController.scala:353:19]
wire same_banks_is_being_im2colled_2 = 1'h0; // @[ExecuteController.scala:323:64]
wire _same_banks_is_being_im2colled_T_3 = 1'h0; // @[ExecuteController.scala:323:49]
wire same_banks_is_being_im2colled_3 = 1'h0; // @[ExecuteController.scala:323:64]
wire _one_ahead_T_62 = 1'h0; // @[Util.scala:28:8]
wire _one_ahead_T_89 = 1'h0; // @[Util.scala:28:8]
wire _must_wait_for_T_6 = 1'h0; // @[ExecuteController.scala:353:13]
wire _must_wait_for_T_7 = 1'h0; // @[ExecuteController.scala:353:19]
wire same_banks_is_being_im2colled_4 = 1'h0; // @[ExecuteController.scala:323:64]
wire _same_banks_is_being_im2colled_T_5 = 1'h0; // @[ExecuteController.scala:323:49]
wire same_banks_is_being_im2colled_5 = 1'h0; // @[ExecuteController.scala:323:64]
wire _one_ahead_T_116 = 1'h0; // @[Util.scala:28:8]
wire _one_ahead_T_143 = 1'h0; // @[Util.scala:28:8]
wire _a_fire_counter_T_8 = 1'h0; // @[Util.scala:28:8]
wire _b_fire_counter_T_8 = 1'h0; // @[Util.scala:28:8]
wire _d_fire_counter_T_8 = 1'h0; // @[Util.scala:28:8]
wire _read_a_T_8 = 1'h0; // @[ExecuteController.scala:424:151]
wire _read_a_T_18 = 1'h0; // @[ExecuteController.scala:424:151]
wire _read_a_T_28 = 1'h0; // @[ExecuteController.scala:424:151]
wire _read_a_T_38 = 1'h0; // @[ExecuteController.scala:424:151]
wire _read_a_from_acc_T_7 = 1'h0; // @[ExecuteController.scala:458:162]
wire read_a_4 = 1'h0; // @[ExecuteController.scala:506:82]
wire _mesh_cntl_signals_q_io_enq_bits_im2colling_T = 1'h0; // @[ExecuteController.scala:799:61]
wire _dataA_valid_WIRE = 1'h0;
wire _dataB_valid_WIRE = 1'h0;
wire _dataD_valid_WIRE = 1'h0;
wire _preload_zero_counter_T_5 = 1'h0; // @[Util.scala:19:28]
wire _preload_zero_counter_T_9 = 1'h0; // @[Util.scala:19:11]
wire _preload_zero_counter_T_13 = 1'h0; // @[Util.scala:29:12]
wire _dataA_unpadded_WIRE = 1'h0;
wire _dataB_unpadded_WIRE = 1'h0;
wire _dataD_unpadded_WIRE = 1'h0;
wire _io_acc_read_resp_ready_WIRE = 1'h0;
wire _io_acc_read_resp_ready_WIRE_1 = 1'h0;
wire _io_acc_read_resp_ready_WIRE_2 = 1'h0;
wire _output_counter_T_8 = 1'h0; // @[Util.scala:28:8]
wire [31:0] io_acc_read_req_0_bits_igelu_qb_bits = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_req_0_bits_igelu_qc_bits = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_req_0_bits_iexp_qln2_bits = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_req_0_bits_iexp_qln2_inv_bits = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_counter_external_values_0 = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_counter_external_values_1 = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_counter_external_values_2 = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_counter_external_values_3 = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_counter_external_values_4 = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_counter_external_values_5 = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_counter_external_values_6 = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_counter_external_values_7 = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] _dataA_WIRE_2_bits = 32'h0; // @[Arithmetic.scala:518:46]
wire [31:0] _dataA_WIRE_3_bits = 32'h0; // @[Arithmetic.scala:518:46]
wire [31:0] _dataA_WIRE_4_bits = 32'h0; // @[Arithmetic.scala:518:46]
wire [31:0] _dataA_WIRE_5_bits = 32'h0; // @[Arithmetic.scala:518:46]
wire [31:0] _dataB_WIRE_2_bits = 32'h0; // @[Arithmetic.scala:518:46]
wire [31:0] _dataB_WIRE_3_bits = 32'h0; // @[Arithmetic.scala:518:46]
wire [31:0] _dataB_WIRE_4_bits = 32'h0; // @[Arithmetic.scala:518:46]
wire [31:0] _dataB_WIRE_5_bits = 32'h0; // @[Arithmetic.scala:518:46]
wire [31:0] _dataD_WIRE_2_bits = 32'h0; // @[Arithmetic.scala:518:46]
wire [31:0] _dataD_WIRE_3_bits = 32'h0; // @[Arithmetic.scala:518:46]
wire [31:0] _dataD_WIRE_4_bits = 32'h0; // @[Arithmetic.scala:518:46]
wire [31:0] _dataD_WIRE_5_bits = 32'h0; // @[Arithmetic.scala:518:46]
wire [13:0] _mesh_io_req_bits_tag_addr_data_T = 14'h3FFF; // @[LocalAddr.scala:99:13]
wire [2:0] _d_address_T_1 = 3'h3; // @[ExecuteController.scala:253:49]
wire [2:0] _d_row_is_not_all_zeros_T_1 = 3'h3; // @[ExecuteController.scala:312:45]
wire [2:0] preload_zero_counter_max = 3'h3; // @[Util.scala:18:28]
wire [2:0] _preload_zero_counter_T_17 = 3'h3; // @[Util.scala:30:21]
wire [3:0] _d_address_T = 4'h3; // @[ExecuteController.scala:253:49]
wire [3:0] _d_row_is_not_all_zeros_T = 4'h3; // @[ExecuteController.scala:312:45]
wire [3:0] _preload_zero_counter_max_T = 4'h3; // @[Util.scala:18:28]
wire [3:0] _preload_zero_counter_T_16 = 4'h3; // @[Util.scala:30:21]
wire [2:0] _preload_zero_counter_T_15 = 3'h2; // @[Util.scala:30:17]
wire [3:0] _preload_zero_counter_T_14 = 4'h2; // @[Util.scala:30:17]
wire [8:0] im2col_turn = 9'h0; // @[ExecuteController.scala:114:29]
wire a_address_rs1_is_acc_addr; // @[ExecuteController.scala:139:53]
wire a_address_rs1_accumulate; // @[ExecuteController.scala:139:53]
wire a_address_rs1_read_full_acc_row; // @[ExecuteController.scala:139:53]
wire [2:0] a_address_rs1_norm_cmd; // @[ExecuteController.scala:139:53]
wire [10:0] a_address_rs1_garbage; // @[ExecuteController.scala:139:53]
wire a_address_rs1_garbage_bit; // @[ExecuteController.scala:139:53]
wire [13:0] a_address_rs1_data; // @[ExecuteController.scala:139:53]
wire [8:0] icol; // @[ExecuteController.scala:108:22]
wire [8:0] irow; // @[ExecuteController.scala:109:22]
wire start_inputting_a; // @[ExecuteController.scala:267:35]
wire _io_srams_read_0_req_valid_T_2; // @[ExecuteController.scala:435:66]
wire [11:0] _io_srams_read_0_req_bits_addr_T_19; // @[Mux.scala:126:16]
wire _readValid_T = io_srams_read_0_resp_valid_0; // @[ExecuteController.scala:12:7, :807:73]
wire [127:0] readData_0 = io_srams_read_0_resp_bits_data_0; // @[ExecuteController.scala:12:7, :803:25]
wire _io_srams_read_1_req_valid_T_2; // @[ExecuteController.scala:435:66]
wire [11:0] _io_srams_read_1_req_bits_addr_T_19; // @[Mux.scala:126:16]
wire _readValid_T_3 = io_srams_read_1_resp_valid_0; // @[ExecuteController.scala:12:7, :807:73]
wire [127:0] readData_1 = io_srams_read_1_resp_bits_data_0; // @[ExecuteController.scala:12:7, :803:25]
wire _io_srams_read_2_req_valid_T_2; // @[ExecuteController.scala:435:66]
wire [11:0] _io_srams_read_2_req_bits_addr_T_19; // @[Mux.scala:126:16]
wire _readValid_T_6 = io_srams_read_2_resp_valid_0; // @[ExecuteController.scala:12:7, :807:73]
wire [127:0] readData_2 = io_srams_read_2_resp_bits_data_0; // @[ExecuteController.scala:12:7, :803:25]
wire _io_srams_read_3_req_valid_T_2; // @[ExecuteController.scala:435:66]
wire [11:0] _io_srams_read_3_req_bits_addr_T_19; // @[Mux.scala:126:16]
wire _readValid_T_9 = io_srams_read_3_resp_valid_0; // @[ExecuteController.scala:12:7, :807:73]
wire [127:0] readData_3 = io_srams_read_3_resp_bits_data_0; // @[ExecuteController.scala:12:7, :803:25]
wire _io_srams_write_0_en_T_6; // @[ExecuteController.scala:934:109]
wire [11:0] w_row; // @[ExecuteController.scala:912:18]
wire w_mask_0; // @[ExecuteController.scala:921:45]
wire w_mask_1; // @[ExecuteController.scala:921:45]
wire w_mask_2; // @[ExecuteController.scala:921:45]
wire w_mask_3; // @[ExecuteController.scala:921:45]
wire [127:0] _io_srams_write_0_data_T; // @[ExecuteController.scala:936:49]
wire _io_srams_write_1_en_T_6; // @[ExecuteController.scala:934:109]
wire [127:0] _io_srams_write_1_data_T; // @[ExecuteController.scala:936:49]
wire _io_srams_write_2_en_T_6; // @[ExecuteController.scala:934:109]
wire [127:0] _io_srams_write_2_data_T; // @[ExecuteController.scala:936:49]
wire _io_srams_write_3_en_T_6; // @[ExecuteController.scala:934:109]
wire [127:0] _io_srams_write_3_data_T; // @[ExecuteController.scala:936:49]
wire _io_acc_read_req_0_valid_T_1; // @[ExecuteController.scala:469:70]
wire [11:0] _io_acc_read_req_0_bits_addr_T_19; // @[Mux.scala:126:16]
wire _accReadValid_T = io_acc_read_resp_0_valid_0; // @[ExecuteController.scala:12:7, :808:78]
wire _io_acc_write_0_valid_T_5; // @[ExecuteController.scala:949:109]
wire [31:0] result_bits; // @[Arithmetic.scala:491:26]
wire [31:0] result_1_bits; // @[Arithmetic.scala:491:26]
wire [31:0] result_2_bits; // @[Arithmetic.scala:491:26]
wire [31:0] result_3_bits; // @[Arithmetic.scala:491:26]
wire w_address_accumulate; // @[ExecuteController.scala:907:22]
wire _io_busy_T; // @[ExecuteController.scala:232:27]
wire io_cmd_ready_0; // @[ExecuteController.scala:12:7]
wire io_im2col_req_bits_addr_is_acc_addr_0; // @[ExecuteController.scala:12:7]
wire io_im2col_req_bits_addr_accumulate_0; // @[ExecuteController.scala:12:7]
wire io_im2col_req_bits_addr_read_full_acc_row_0; // @[ExecuteController.scala:12:7]
wire [2:0] io_im2col_req_bits_addr_norm_cmd_0; // @[ExecuteController.scala:12:7]
wire [10:0] io_im2col_req_bits_addr_garbage_0; // @[ExecuteController.scala:12:7]
wire io_im2col_req_bits_addr_garbage_bit_0; // @[ExecuteController.scala:12:7]
wire [13:0] io_im2col_req_bits_addr_data_0; // @[ExecuteController.scala:12:7]
wire [7:0] io_im2col_req_bits_ocol_0; // @[ExecuteController.scala:12:7]
wire [3:0] io_im2col_req_bits_krow_0; // @[ExecuteController.scala:12:7]
wire [8:0] io_im2col_req_bits_icol_0; // @[ExecuteController.scala:12:7]
wire [8:0] io_im2col_req_bits_irow_0; // @[ExecuteController.scala:12:7]
wire [2:0] io_im2col_req_bits_stride_0; // @[ExecuteController.scala:12:7]
wire [8:0] io_im2col_req_bits_channel_0; // @[ExecuteController.scala:12:7]
wire [10:0] io_im2col_req_bits_row_turn_0; // @[ExecuteController.scala:12:7]
wire [7:0] io_im2col_req_bits_kdim2_0; // @[ExecuteController.scala:12:7]
wire [3:0] io_im2col_req_bits_row_left_0; // @[ExecuteController.scala:12:7]
wire io_im2col_req_bits_weight_double_bank_0; // @[ExecuteController.scala:12:7]
wire io_im2col_req_bits_weight_triple_bank_0; // @[ExecuteController.scala:12:7]
wire io_im2col_req_bits_start_inputting_0; // @[ExecuteController.scala:12:7]
wire io_im2col_resp_ready_0; // @[ExecuteController.scala:12:7]
wire [11:0] io_srams_read_0_req_bits_addr_0; // @[ExecuteController.scala:12:7]
wire io_srams_read_0_req_valid_0; // @[ExecuteController.scala:12:7]
wire io_srams_read_0_resp_ready_0; // @[ExecuteController.scala:12:7]
wire [11:0] io_srams_read_1_req_bits_addr_0; // @[ExecuteController.scala:12:7]
wire io_srams_read_1_req_valid_0; // @[ExecuteController.scala:12:7]
wire io_srams_read_1_resp_ready_0; // @[ExecuteController.scala:12:7]
wire [11:0] io_srams_read_2_req_bits_addr_0; // @[ExecuteController.scala:12:7]
wire io_srams_read_2_req_valid_0; // @[ExecuteController.scala:12:7]
wire io_srams_read_2_resp_ready_0; // @[ExecuteController.scala:12:7]
wire [11:0] io_srams_read_3_req_bits_addr_0; // @[ExecuteController.scala:12:7]
wire io_srams_read_3_req_valid_0; // @[ExecuteController.scala:12:7]
wire io_srams_read_3_resp_ready_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_0_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_1_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_2_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_3_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_4_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_5_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_6_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_7_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_8_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_9_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_10_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_11_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_12_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_13_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_14_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_15_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_en_0; // @[ExecuteController.scala:12:7]
wire [11:0] io_srams_write_0_addr_0; // @[ExecuteController.scala:12:7]
wire [127:0] io_srams_write_0_data_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_0_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_1_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_2_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_3_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_4_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_5_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_6_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_7_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_8_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_9_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_10_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_11_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_12_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_13_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_14_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_15_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_en_0; // @[ExecuteController.scala:12:7]
wire [11:0] io_srams_write_1_addr_0; // @[ExecuteController.scala:12:7]
wire [127:0] io_srams_write_1_data_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_0_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_1_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_2_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_3_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_4_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_5_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_6_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_7_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_8_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_9_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_10_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_11_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_12_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_13_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_14_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_15_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_en_0; // @[ExecuteController.scala:12:7]
wire [11:0] io_srams_write_2_addr_0; // @[ExecuteController.scala:12:7]
wire [127:0] io_srams_write_2_data_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_0_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_1_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_2_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_3_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_4_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_5_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_6_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_7_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_8_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_9_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_10_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_11_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_12_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_13_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_14_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_15_0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_en_0; // @[ExecuteController.scala:12:7]
wire [11:0] io_srams_write_3_addr_0; // @[ExecuteController.scala:12:7]
wire [127:0] io_srams_write_3_data_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_req_0_bits_scale_bits_0; // @[ExecuteController.scala:12:7]
wire [11:0] io_acc_read_req_0_bits_addr_0; // @[ExecuteController.scala:12:7]
wire [2:0] io_acc_read_req_0_bits_act_0; // @[ExecuteController.scala:12:7]
wire io_acc_read_req_0_valid_0; // @[ExecuteController.scala:12:7]
wire io_acc_read_resp_0_ready_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_0_bits_data_0_0_bits_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_0_bits_data_1_0_bits_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_0_bits_data_2_0_bits_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_0_bits_data_3_0_bits_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_0_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_1_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_2_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_3_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_4_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_5_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_6_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_7_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_8_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_9_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_10_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_11_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_12_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_13_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_14_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_15_0; // @[ExecuteController.scala:12:7]
wire [11:0] io_acc_write_0_bits_addr_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_acc_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_valid_0; // @[ExecuteController.scala:12:7]
wire io_completed_valid_0; // @[ExecuteController.scala:12:7]
wire [5:0] io_completed_bits_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_24_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_25_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_26_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_27_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_28_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_29_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_30_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_31_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_32_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_33_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_34_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_35_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_36_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_37_0; // @[ExecuteController.scala:12:7]
wire io_busy_0; // @[ExecuteController.scala:12:7]
reg [1:0] control_state; // @[ExecuteController.scala:74:30]
reg current_dataflow; // @[ExecuteController.scala:77:60]
wire _d_should_be_fed_into_transposer_T = current_dataflow; // @[ExecuteController.scala:77:60, :129:58]
wire _d_cols_T = current_dataflow; // @[ExecuteController.scala:77:60, :165:37]
wire _d_rows_T = current_dataflow; // @[ExecuteController.scala:77:60, :166:37]
wire _w_address_T = current_dataflow; // @[ExecuteController.scala:77:60, :907:40]
wire _write_this_row_T = current_dataflow; // @[ExecuteController.scala:77:60, :919:45]
wire [63:0] _config_ex_rs1_WIRE = rs1s_0; // @[ExecuteController.scala:80:21, :542:47]
wire [63:0] rs1s_1; // @[ExecuteController.scala:80:21]
wire [63:0] rs1s_2; // @[ExecuteController.scala:80:21]
wire [63:0] _config_ex_rs2_WIRE = rs2s_0; // @[ExecuteController.scala:81:21, :543:47]
wire [63:0] rs2s_1; // @[ExecuteController.scala:81:21]
wire [63:0] rs2s_2; // @[ExecuteController.scala:81:21]
wire DoConfig = _cmd_q_io_deq_bits_0_cmd_inst_funct == 7'h0; // @[MultiHeadedQueue.scala:53:19]
wire _GEN = _cmd_q_io_deq_bits_0_cmd_inst_funct == 7'h4; // @[MultiHeadedQueue.scala:53:19]
wire _DoComputes_T; // @[ExecuteController.scala:84:38]
assign _DoComputes_T = _GEN; // @[ExecuteController.scala:84:38]
wire in_prop; // @[ExecuteController.scala:90:27]
assign in_prop = _GEN; // @[ExecuteController.scala:84:38, :90:27]
wire _DoComputes_T_1 = _cmd_q_io_deq_bits_0_cmd_inst_funct == 7'h5; // @[MultiHeadedQueue.scala:53:19]
wire DoComputes_0 = _DoComputes_T | _DoComputes_T_1; // @[ExecuteController.scala:84:{38,63,68}]
wire _DoComputes_T_2 = _cmd_q_io_deq_bits_1_cmd_inst_funct == 7'h4; // @[MultiHeadedQueue.scala:53:19]
wire _DoComputes_T_3 = _cmd_q_io_deq_bits_1_cmd_inst_funct == 7'h5; // @[MultiHeadedQueue.scala:53:19]
wire DoComputes_1 = _DoComputes_T_2 | _DoComputes_T_3; // @[ExecuteController.scala:84:{38,63,68}]
wire _DoComputes_T_4 = _cmd_q_io_deq_bits_2_cmd_inst_funct == 7'h4; // @[MultiHeadedQueue.scala:53:19]
wire _DoComputes_T_5 = _cmd_q_io_deq_bits_2_cmd_inst_funct == 7'h5; // @[MultiHeadedQueue.scala:53:19]
wire DoComputes_2 = _DoComputes_T_4 | _DoComputes_T_5; // @[ExecuteController.scala:84:{38,63,68}]
wire DoPreloads_0 = _cmd_q_io_deq_bits_0_cmd_inst_funct == 7'h6; // @[MultiHeadedQueue.scala:53:19]
wire DoPreloads_1 = _cmd_q_io_deq_bits_1_cmd_inst_funct == 7'h6; // @[MultiHeadedQueue.scala:53:19]
wire DoPreloads_2 = _cmd_q_io_deq_bits_2_cmd_inst_funct == 7'h6; // @[MultiHeadedQueue.scala:53:19]
wire preload_cmd_place = ~DoPreloads_0; // @[ExecuteController.scala:85:33, :87:30]
reg in_prop_flush; // @[ExecuteController.scala:92:26]
reg [7:0] ocol; // @[ExecuteController.scala:97:21]
assign io_im2col_req_bits_ocol_0 = ocol; // @[ExecuteController.scala:12:7, :97:21]
reg [3:0] krow; // @[ExecuteController.scala:99:21]
assign io_im2col_req_bits_krow_0 = krow; // @[ExecuteController.scala:12:7, :99:21]
reg [2:0] weight_stride; // @[ExecuteController.scala:100:30]
assign io_im2col_req_bits_stride_0 = weight_stride; // @[ExecuteController.scala:12:7, :100:30]
reg [8:0] channel; // @[ExecuteController.scala:101:24]
assign io_im2col_req_bits_channel_0 = channel; // @[ExecuteController.scala:12:7, :101:24]
reg [10:0] row_turn; // @[ExecuteController.scala:102:25]
assign io_im2col_req_bits_row_turn_0 = row_turn; // @[ExecuteController.scala:12:7, :102:25]
reg [3:0] row_left; // @[ExecuteController.scala:103:25]
assign io_im2col_req_bits_row_left_0 = row_left; // @[ExecuteController.scala:12:7, :103:25]
reg [7:0] kdim2; // @[ExecuteController.scala:104:22]
assign io_im2col_req_bits_kdim2_0 = kdim2; // @[ExecuteController.scala:12:7, :104:22]
reg weight_double_bank; // @[ExecuteController.scala:105:35]
assign io_im2col_req_bits_weight_double_bank_0 = weight_double_bank; // @[ExecuteController.scala:12:7, :105:35]
reg weight_triple_bank; // @[ExecuteController.scala:106:35]
assign io_im2col_req_bits_weight_triple_bank_0 = weight_triple_bank; // @[ExecuteController.scala:12:7, :106:35]
assign io_im2col_req_bits_icol_0 = icol; // @[ExecuteController.scala:12:7, :108:22]
assign io_im2col_req_bits_irow_0 = irow; // @[ExecuteController.scala:12:7, :109:22]
wire [8:0] _icol_T = {1'h0, ocol} - 9'h1; // @[ExecuteController.scala:97:21, :111:18]
wire [7:0] _icol_T_1 = _icol_T[7:0]; // @[ExecuteController.scala:111:18]
wire [10:0] _GEN_0 = {8'h0, weight_stride}; // @[ExecuteController.scala:100:30, :111:25]
wire [10:0] _icol_T_2 = {3'h0, _icol_T_1} * _GEN_0; // @[ExecuteController.scala:111:{18,25}]
wire [11:0] _GEN_1 = {8'h0, krow}; // @[ExecuteController.scala:99:21, :111:41]
wire [11:0] _icol_T_3 = {1'h0, _icol_T_2} + _GEN_1; // @[ExecuteController.scala:111:{25,41}]
wire [10:0] _icol_T_4 = _icol_T_3[10:0]; // @[ExecuteController.scala:111:41]
assign icol = _icol_T_4[8:0]; // @[ExecuteController.scala:108:22, :111:{8,41}]
wire [10:0] _irow_T_2 = _GEN_0 * 11'hFF; // @[ExecuteController.scala:111:25, :112:25]
wire [11:0] _irow_T_3 = {1'h0, _irow_T_2} + _GEN_1; // @[ExecuteController.scala:111:41, :112:{25,41}]
wire [10:0] _irow_T_4 = _irow_T_3[10:0]; // @[ExecuteController.scala:112:41]
assign irow = _irow_T_4[8:0]; // @[ExecuteController.scala:109:22, :112:{8,41}]
reg [4:0] in_shift; // @[ExecuteController.scala:116:21]
reg [31:0] acc_scale_bits; // @[ExecuteController.scala:117:22]
assign io_acc_read_req_0_bits_scale_bits_0 = acc_scale_bits; // @[ExecuteController.scala:12:7, :117:22]
reg [2:0] activation; // @[ExecuteController.scala:118:54]
assign io_acc_read_req_0_bits_act_0 = activation; // @[ExecuteController.scala:12:7, :118:54]
reg a_transpose; // @[ExecuteController.scala:119:24]
reg bd_transpose; // @[ExecuteController.scala:120:25]
reg config_initialized; // @[ExecuteController.scala:121:35]
wire _a_should_be_fed_into_transposer_T = ~current_dataflow; // @[ExecuteController.scala:77:60, :123:62]
wire _a_should_be_fed_into_transposer_T_1 = ~a_transpose; // @[ExecuteController.scala:119:24, :123:84]
wire a_should_be_fed_into_transposer = _a_should_be_fed_into_transposer_T ? _a_should_be_fed_into_transposer_T_1 : a_transpose; // @[ExecuteController.scala:119:24, :123:{44,62,84}]
wire _a_address_place_T = ~preload_cmd_place; // @[ExecuteController.scala:87:30, :124:47]
wire [1:0] _a_address_place_T_1 = {a_should_be_fed_into_transposer, 1'h0}; // @[ExecuteController.scala:123:44, :124:64]
wire [1:0] a_address_place = _a_address_place_T ? 2'h1 : _a_address_place_T_1; // @[ExecuteController.scala:124:{28,47,64}]
wire _b_should_be_fed_into_transposer_T = ~current_dataflow; // @[ExecuteController.scala:77:60, :123:62, :126:58]
wire b_should_be_fed_into_transposer = _b_should_be_fed_into_transposer_T & bd_transpose; // @[ExecuteController.scala:120:25, :126:{58,79}]
wire _b_address_place_T = ~preload_cmd_place; // @[ExecuteController.scala:87:30, :124:47, :127:47]
wire [1:0] _b_address_place_T_1 = {b_should_be_fed_into_transposer, 1'h0}; // @[ExecuteController.scala:126:79, :127:64]
wire [1:0] b_address_place = _b_address_place_T ? 2'h1 : _b_address_place_T_1; // @[ExecuteController.scala:127:{28,47,64}]
wire d_should_be_fed_into_transposer = _d_should_be_fed_into_transposer_T & bd_transpose; // @[ExecuteController.scala:120:25, :129:{58,79}]
wire _im2col_en_T = |weight_stride; // @[ExecuteController.scala:100:30, :136:55]
wire _a_address_rs1_T_6; // @[ExecuteController.scala:139:53]
assign io_im2col_req_bits_addr_is_acc_addr_0 = a_address_rs1_is_acc_addr; // @[ExecuteController.scala:12:7, :139:53]
wire _a_address_rs1_T_5; // @[ExecuteController.scala:139:53]
wire a_address_is_acc_addr = a_address_rs1_is_acc_addr; // @[LocalAddr.scala:50:26]
wire a_read_from_acc = a_address_rs1_is_acc_addr; // @[ExecuteController.scala:139:53, :263:44]
assign io_im2col_req_bits_addr_accumulate_0 = a_address_rs1_accumulate; // @[ExecuteController.scala:12:7, :139:53]
wire _a_address_rs1_T_4; // @[ExecuteController.scala:139:53]
wire a_address_accumulate = a_address_rs1_accumulate; // @[LocalAddr.scala:50:26]
assign io_im2col_req_bits_addr_read_full_acc_row_0 = a_address_rs1_read_full_acc_row; // @[ExecuteController.scala:12:7, :139:53]
wire [2:0] _a_address_rs1_WIRE_2; // @[ExecuteController.scala:139:53]
wire a_address_read_full_acc_row = a_address_rs1_read_full_acc_row; // @[LocalAddr.scala:50:26]
assign io_im2col_req_bits_addr_norm_cmd_0 = a_address_rs1_norm_cmd; // @[ExecuteController.scala:12:7, :139:53]
wire [10:0] _a_address_rs1_T_2; // @[ExecuteController.scala:139:53]
wire [2:0] a_address_norm_cmd = a_address_rs1_norm_cmd; // @[LocalAddr.scala:50:26]
assign io_im2col_req_bits_addr_garbage_0 = a_address_rs1_garbage; // @[ExecuteController.scala:12:7, :139:53]
wire _a_address_rs1_T_1; // @[ExecuteController.scala:139:53]
wire [10:0] a_address_garbage = a_address_rs1_garbage; // @[LocalAddr.scala:50:26]
assign io_im2col_req_bits_addr_garbage_bit_0 = a_address_rs1_garbage_bit; // @[ExecuteController.scala:12:7, :139:53]
wire [13:0] _a_address_rs1_T; // @[ExecuteController.scala:139:53]
wire _multiply_garbage_T_4 = a_address_rs1_garbage_bit; // @[LocalAddr.scala:44:48]
wire a_address_garbage_bit = a_address_rs1_garbage_bit; // @[LocalAddr.scala:50:26]
wire _a_garbage_T_4 = a_address_rs1_garbage_bit; // @[LocalAddr.scala:44:48]
assign io_im2col_req_bits_addr_data_0 = a_address_rs1_data; // @[ExecuteController.scala:12:7, :139:53]
wire [3:0][63:0] _GEN_2 = {{rs1s_0}, {rs1s_2}, {rs1s_1}, {rs1s_0}}; // @[ExecuteController.scala:80:21, :139:53]
wire [31:0] _a_address_rs1_WIRE = _GEN_2[a_address_place][31:0]; // @[ExecuteController.scala:124:28, :139:53]
assign _a_address_rs1_T = _a_address_rs1_WIRE[13:0]; // @[ExecuteController.scala:139:53]
assign a_address_rs1_data = _a_address_rs1_T; // @[ExecuteController.scala:139:53]
assign _a_address_rs1_T_1 = _a_address_rs1_WIRE[14]; // @[ExecuteController.scala:139:53]
assign a_address_rs1_garbage_bit = _a_address_rs1_T_1; // @[ExecuteController.scala:139:53]
assign _a_address_rs1_T_2 = _a_address_rs1_WIRE[25:15]; // @[ExecuteController.scala:139:53]
assign a_address_rs1_garbage = _a_address_rs1_T_2; // @[ExecuteController.scala:139:53]
wire [2:0] _a_address_rs1_T_3 = _a_address_rs1_WIRE[28:26]; // @[ExecuteController.scala:139:53]
wire [2:0] _a_address_rs1_WIRE_1 = _a_address_rs1_T_3; // @[ExecuteController.scala:139:53]
assign _a_address_rs1_WIRE_2 = _a_address_rs1_WIRE_1; // @[ExecuteController.scala:139:53]
assign a_address_rs1_norm_cmd = _a_address_rs1_WIRE_2; // @[ExecuteController.scala:139:53]
assign _a_address_rs1_T_4 = _a_address_rs1_WIRE[29]; // @[ExecuteController.scala:139:53]
assign a_address_rs1_read_full_acc_row = _a_address_rs1_T_4; // @[ExecuteController.scala:139:53]
assign _a_address_rs1_T_5 = _a_address_rs1_WIRE[30]; // @[ExecuteController.scala:139:53]
assign a_address_rs1_accumulate = _a_address_rs1_T_5; // @[ExecuteController.scala:139:53]
assign _a_address_rs1_T_6 = _a_address_rs1_WIRE[31]; // @[ExecuteController.scala:139:53]
assign a_address_rs1_is_acc_addr = _a_address_rs1_T_6; // @[ExecuteController.scala:139:53]
wire _b_address_rs2_T_6; // @[ExecuteController.scala:140:53]
wire _b_address_rs2_T_5; // @[ExecuteController.scala:140:53]
wire b_address_is_acc_addr = b_address_rs2_is_acc_addr; // @[LocalAddr.scala:50:26]
wire b_read_from_acc = b_address_rs2_is_acc_addr; // @[ExecuteController.scala:140:53, :264:44]
wire _b_address_rs2_T_4; // @[ExecuteController.scala:140:53]
wire b_address_accumulate = b_address_rs2_accumulate; // @[LocalAddr.scala:50:26]
wire [2:0] _b_address_rs2_WIRE_2; // @[ExecuteController.scala:140:53]
wire b_address_read_full_acc_row = b_address_rs2_read_full_acc_row; // @[LocalAddr.scala:50:26]
wire [10:0] _b_address_rs2_T_2; // @[ExecuteController.scala:140:53]
wire [2:0] b_address_norm_cmd = b_address_rs2_norm_cmd; // @[LocalAddr.scala:50:26]
wire _b_address_rs2_T_1; // @[ExecuteController.scala:140:53]
wire [10:0] b_address_garbage = b_address_rs2_garbage; // @[LocalAddr.scala:50:26]
wire [13:0] _b_address_rs2_T; // @[ExecuteController.scala:140:53]
wire _accumulate_zeros_T_4 = b_address_rs2_garbage_bit; // @[LocalAddr.scala:44:48]
wire b_address_garbage_bit = b_address_rs2_garbage_bit; // @[LocalAddr.scala:50:26]
wire _b_garbage_T_4 = b_address_rs2_garbage_bit; // @[LocalAddr.scala:44:48]
wire [13:0] b_address_rs2_data; // @[ExecuteController.scala:140:53]
wire [3:0][63:0] _GEN_3 = {{rs2s_0}, {rs2s_2}, {rs2s_1}, {rs2s_0}}; // @[ExecuteController.scala:81:21, :140:53]
wire [31:0] _b_address_rs2_WIRE = _GEN_3[b_address_place][31:0]; // @[ExecuteController.scala:127:28, :140:53]
assign _b_address_rs2_T = _b_address_rs2_WIRE[13:0]; // @[ExecuteController.scala:140:53]
assign b_address_rs2_data = _b_address_rs2_T; // @[ExecuteController.scala:140:53]
assign _b_address_rs2_T_1 = _b_address_rs2_WIRE[14]; // @[ExecuteController.scala:140:53]
assign b_address_rs2_garbage_bit = _b_address_rs2_T_1; // @[ExecuteController.scala:140:53]
assign _b_address_rs2_T_2 = _b_address_rs2_WIRE[25:15]; // @[ExecuteController.scala:140:53]
assign b_address_rs2_garbage = _b_address_rs2_T_2; // @[ExecuteController.scala:140:53]
wire [2:0] _b_address_rs2_T_3 = _b_address_rs2_WIRE[28:26]; // @[ExecuteController.scala:140:53]
wire [2:0] _b_address_rs2_WIRE_1 = _b_address_rs2_T_3; // @[ExecuteController.scala:140:53]
assign _b_address_rs2_WIRE_2 = _b_address_rs2_WIRE_1; // @[ExecuteController.scala:140:53]
assign b_address_rs2_norm_cmd = _b_address_rs2_WIRE_2; // @[ExecuteController.scala:140:53]
assign _b_address_rs2_T_4 = _b_address_rs2_WIRE[29]; // @[ExecuteController.scala:140:53]
assign b_address_rs2_read_full_acc_row = _b_address_rs2_T_4; // @[ExecuteController.scala:140:53]
assign _b_address_rs2_T_5 = _b_address_rs2_WIRE[30]; // @[ExecuteController.scala:140:53]
assign b_address_rs2_accumulate = _b_address_rs2_T_5; // @[ExecuteController.scala:140:53]
assign _b_address_rs2_T_6 = _b_address_rs2_WIRE[31]; // @[ExecuteController.scala:140:53]
assign b_address_rs2_is_acc_addr = _b_address_rs2_T_6; // @[ExecuteController.scala:140:53]
wire _d_address_rs1_T_6; // @[ExecuteController.scala:141:55]
wire _d_address_rs1_T_5; // @[ExecuteController.scala:141:55]
wire d_address_is_acc_addr = d_address_rs1_is_acc_addr; // @[LocalAddr.scala:50:26]
wire d_read_from_acc = d_address_rs1_is_acc_addr; // @[ExecuteController.scala:141:55, :265:44]
wire _d_address_rs1_T_4; // @[ExecuteController.scala:141:55]
wire d_address_accumulate = d_address_rs1_accumulate; // @[LocalAddr.scala:50:26]
wire [2:0] _d_address_rs1_WIRE_2; // @[ExecuteController.scala:141:55]
wire d_address_read_full_acc_row = d_address_rs1_read_full_acc_row; // @[LocalAddr.scala:50:26]
wire [10:0] _d_address_rs1_T_2; // @[ExecuteController.scala:141:55]
wire [2:0] d_address_norm_cmd = d_address_rs1_norm_cmd; // @[LocalAddr.scala:50:26]
wire _d_address_rs1_T_1; // @[ExecuteController.scala:141:55]
wire [10:0] d_address_garbage = d_address_rs1_garbage; // @[LocalAddr.scala:50:26]
wire [13:0] _d_address_rs1_T; // @[ExecuteController.scala:141:55]
wire _preload_zeros_T_4 = d_address_rs1_garbage_bit; // @[LocalAddr.scala:44:48]
wire d_address_garbage_bit = d_address_rs1_garbage_bit; // @[LocalAddr.scala:50:26]
wire _d_garbage_T_4 = d_address_rs1_garbage_bit; // @[LocalAddr.scala:44:48]
wire [13:0] d_address_rs1_data; // @[ExecuteController.scala:141:55]
wire [1:0] _GEN_4 = {1'h0, preload_cmd_place}; // @[ExecuteController.scala:87:30, :141:55]
wire [31:0] _d_address_rs1_WIRE = _GEN_2[_GEN_4][31:0]; // @[ExecuteController.scala:139:53, :141:55]
assign _d_address_rs1_T = _d_address_rs1_WIRE[13:0]; // @[ExecuteController.scala:141:55]
assign d_address_rs1_data = _d_address_rs1_T; // @[ExecuteController.scala:141:55]
assign _d_address_rs1_T_1 = _d_address_rs1_WIRE[14]; // @[ExecuteController.scala:141:55]
assign d_address_rs1_garbage_bit = _d_address_rs1_T_1; // @[ExecuteController.scala:141:55]
assign _d_address_rs1_T_2 = _d_address_rs1_WIRE[25:15]; // @[ExecuteController.scala:141:55]
assign d_address_rs1_garbage = _d_address_rs1_T_2; // @[ExecuteController.scala:141:55]
wire [2:0] _d_address_rs1_T_3 = _d_address_rs1_WIRE[28:26]; // @[ExecuteController.scala:141:55]
wire [2:0] _d_address_rs1_WIRE_1 = _d_address_rs1_T_3; // @[ExecuteController.scala:141:55]
assign _d_address_rs1_WIRE_2 = _d_address_rs1_WIRE_1; // @[ExecuteController.scala:141:55]
assign d_address_rs1_norm_cmd = _d_address_rs1_WIRE_2; // @[ExecuteController.scala:141:55]
assign _d_address_rs1_T_4 = _d_address_rs1_WIRE[29]; // @[ExecuteController.scala:141:55]
assign d_address_rs1_read_full_acc_row = _d_address_rs1_T_4; // @[ExecuteController.scala:141:55]
assign _d_address_rs1_T_5 = _d_address_rs1_WIRE[30]; // @[ExecuteController.scala:141:55]
assign d_address_rs1_accumulate = _d_address_rs1_T_5; // @[ExecuteController.scala:141:55]
assign _d_address_rs1_T_6 = _d_address_rs1_WIRE[31]; // @[ExecuteController.scala:141:55]
assign d_address_rs1_is_acc_addr = _d_address_rs1_T_6; // @[ExecuteController.scala:141:55]
wire _c_address_rs2_T_6; // @[ExecuteController.scala:142:55]
wire _c_address_rs2_T_5; // @[ExecuteController.scala:142:55]
wire _c_address_rs2_T_4; // @[ExecuteController.scala:142:55]
wire [2:0] _c_address_rs2_WIRE_2; // @[ExecuteController.scala:142:55]
wire [10:0] _c_address_rs2_T_2; // @[ExecuteController.scala:142:55]
wire _c_address_rs2_T_1; // @[ExecuteController.scala:142:55]
wire [13:0] _c_address_rs2_T; // @[ExecuteController.scala:142:55]
wire _pending_completed_rob_ids_0_valid_T_4 = c_address_rs2_garbage_bit; // @[LocalAddr.scala:44:48]
wire _pending_completed_rob_ids_1_valid_T_4 = c_address_rs2_garbage_bit; // @[LocalAddr.scala:44:48]
wire _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_5 = c_address_rs2_garbage_bit; // @[LocalAddr.scala:44:48]
wire c_address_rs2_is_acc_addr; // @[ExecuteController.scala:142:55]
wire c_address_rs2_accumulate; // @[ExecuteController.scala:142:55]
wire c_address_rs2_read_full_acc_row; // @[ExecuteController.scala:142:55]
wire [2:0] c_address_rs2_norm_cmd; // @[ExecuteController.scala:142:55]
wire [10:0] c_address_rs2_garbage; // @[ExecuteController.scala:142:55]
wire [13:0] c_address_rs2_data; // @[ExecuteController.scala:142:55]
wire [31:0] _c_address_rs2_WIRE = _GEN_3[_GEN_4][31:0]; // @[ExecuteController.scala:140:53, :141:55, :142:55]
assign _c_address_rs2_T = _c_address_rs2_WIRE[13:0]; // @[ExecuteController.scala:142:55]
assign c_address_rs2_data = _c_address_rs2_T; // @[ExecuteController.scala:142:55]
assign _c_address_rs2_T_1 = _c_address_rs2_WIRE[14]; // @[ExecuteController.scala:142:55]
assign c_address_rs2_garbage_bit = _c_address_rs2_T_1; // @[ExecuteController.scala:142:55]
assign _c_address_rs2_T_2 = _c_address_rs2_WIRE[25:15]; // @[ExecuteController.scala:142:55]
assign c_address_rs2_garbage = _c_address_rs2_T_2; // @[ExecuteController.scala:142:55]
wire [2:0] _c_address_rs2_T_3 = _c_address_rs2_WIRE[28:26]; // @[ExecuteController.scala:142:55]
wire [2:0] _c_address_rs2_WIRE_1 = _c_address_rs2_T_3; // @[ExecuteController.scala:142:55]
assign _c_address_rs2_WIRE_2 = _c_address_rs2_WIRE_1; // @[ExecuteController.scala:142:55]
assign c_address_rs2_norm_cmd = _c_address_rs2_WIRE_2; // @[ExecuteController.scala:142:55]
assign _c_address_rs2_T_4 = _c_address_rs2_WIRE[29]; // @[ExecuteController.scala:142:55]
assign c_address_rs2_read_full_acc_row = _c_address_rs2_T_4; // @[ExecuteController.scala:142:55]
assign _c_address_rs2_T_5 = _c_address_rs2_WIRE[30]; // @[ExecuteController.scala:142:55]
assign c_address_rs2_accumulate = _c_address_rs2_T_5; // @[ExecuteController.scala:142:55]
assign _c_address_rs2_T_6 = _c_address_rs2_WIRE[31]; // @[ExecuteController.scala:142:55]
assign c_address_rs2_is_acc_addr = _c_address_rs2_T_6; // @[ExecuteController.scala:142:55]
wire _T_17 = a_address_rs1_is_acc_addr & a_address_rs1_accumulate; // @[LocalAddr.scala:43:48]
wire _multiply_garbage_T; // @[LocalAddr.scala:43:48]
assign _multiply_garbage_T = _T_17; // @[LocalAddr.scala:43:48]
wire _a_garbage_T; // @[LocalAddr.scala:43:48]
assign _a_garbage_T = _T_17; // @[LocalAddr.scala:43:48]
wire _multiply_garbage_T_1 = _multiply_garbage_T & a_address_rs1_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _multiply_garbage_T_2 = &a_address_rs1_data; // @[LocalAddr.scala:43:91]
wire _multiply_garbage_T_3 = _multiply_garbage_T_1 & _multiply_garbage_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire multiply_garbage = _multiply_garbage_T_3 & _multiply_garbage_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _T_23 = b_address_rs2_is_acc_addr & b_address_rs2_accumulate; // @[LocalAddr.scala:43:48]
wire _accumulate_zeros_T; // @[LocalAddr.scala:43:48]
assign _accumulate_zeros_T = _T_23; // @[LocalAddr.scala:43:48]
wire _b_garbage_T; // @[LocalAddr.scala:43:48]
assign _b_garbage_T = _T_23; // @[LocalAddr.scala:43:48]
wire _accumulate_zeros_T_1 = _accumulate_zeros_T & b_address_rs2_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _accumulate_zeros_T_2 = &b_address_rs2_data; // @[LocalAddr.scala:43:91]
wire _accumulate_zeros_T_3 = _accumulate_zeros_T_1 & _accumulate_zeros_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire accumulate_zeros = _accumulate_zeros_T_3 & _accumulate_zeros_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _T_29 = d_address_rs1_is_acc_addr & d_address_rs1_accumulate; // @[LocalAddr.scala:43:48]
wire _preload_zeros_T; // @[LocalAddr.scala:43:48]
assign _preload_zeros_T = _T_29; // @[LocalAddr.scala:43:48]
wire _d_garbage_T; // @[LocalAddr.scala:43:48]
assign _d_garbage_T = _T_29; // @[LocalAddr.scala:43:48]
wire _preload_zeros_T_1 = _preload_zeros_T & d_address_rs1_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _preload_zeros_T_2 = &d_address_rs1_data; // @[LocalAddr.scala:43:91]
wire _preload_zeros_T_3 = _preload_zeros_T_1 & _preload_zeros_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire preload_zeros = _preload_zeros_T_3 & _preload_zeros_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire [2:0] a_cols_default = _GEN_2[a_address_place][34:32]; // @[ExecuteController.scala:124:28, :139:53, :154:45]
wire [2:0] a_rows_default = _GEN_2[a_address_place][50:48]; // @[ExecuteController.scala:124:28, :139:53, :155:45]
wire [2:0] b_cols_default = _GEN_3[b_address_place][34:32]; // @[ExecuteController.scala:127:28, :140:53, :156:45]
wire [2:0] b_rows_default = _GEN_3[b_address_place][50:48]; // @[ExecuteController.scala:127:28, :140:53, :157:45]
wire [2:0] d_cols_default = _GEN_2[_GEN_4][34:32]; // @[ExecuteController.scala:139:53, :141:55, :158:47]
wire [2:0] d_rows_default = _GEN_2[_GEN_4][50:48]; // @[ExecuteController.scala:139:53, :141:55, :159:47]
wire [2:0] a_cols = a_transpose ? a_rows_default : a_cols_default; // @[ExecuteController.scala:119:24, :154:45, :155:45, :161:19]
wire [2:0] a_rows = a_transpose ? a_cols_default : a_rows_default; // @[ExecuteController.scala:119:24, :154:45, :155:45, :162:19]
wire _b_cols_T = ~current_dataflow; // @[ExecuteController.scala:77:60, :123:62, :163:37]
wire _b_cols_T_1 = _b_cols_T & bd_transpose; // @[ExecuteController.scala:120:25, :163:{37,58}]
wire [2:0] b_cols = _b_cols_T_1 ? b_rows_default : b_cols_default; // @[ExecuteController.scala:156:45, :157:45, :163:{19,58}]
wire _b_rows_T = ~current_dataflow; // @[ExecuteController.scala:77:60, :123:62, :164:37]
wire _b_rows_T_1 = _b_rows_T & bd_transpose; // @[ExecuteController.scala:120:25, :164:{37,58}]
wire [2:0] b_rows = _b_rows_T_1 ? b_cols_default : b_rows_default; // @[ExecuteController.scala:156:45, :157:45, :164:{19,58}]
wire _d_cols_T_1 = _d_cols_T & bd_transpose; // @[ExecuteController.scala:120:25, :165:{37,58}]
wire [2:0] d_cols = _d_cols_T_1 ? d_rows_default : d_cols_default; // @[ExecuteController.scala:158:47, :159:47, :165:{19,58}]
wire _d_rows_T_1 = _d_rows_T & bd_transpose; // @[ExecuteController.scala:120:25, :166:{37,58}]
wire [2:0] d_rows = _d_rows_T_1 ? d_cols_default : d_rows_default; // @[ExecuteController.scala:158:47, :159:47, :166:{19,58}]
wire [2:0] c_cols = _GEN_3[_GEN_4][34:32]; // @[ExecuteController.scala:140:53, :141:55, :142:55, :167:39]
wire [2:0] c_rows = _GEN_3[_GEN_4][50:48]; // @[ExecuteController.scala:140:53, :141:55, :142:55, :168:39]
reg pending_completed_rob_ids_0_valid; // @[ExecuteController.scala:175:38]
reg [5:0] pending_completed_rob_ids_0_bits; // @[ExecuteController.scala:175:38]
reg pending_completed_rob_ids_1_valid; // @[ExecuteController.scala:175:38]
reg [5:0] pending_completed_rob_ids_1_bits; // @[ExecuteController.scala:175:38]
wire _T_202 = control_state == 2'h2; // @[ExecuteController.scala:74:30, :192:38]
wire _mesh_io_req_valid_T; // @[ExecuteController.scala:192:38]
assign _mesh_io_req_valid_T = _T_202; // @[ExecuteController.scala:192:38]
wire _mesh_io_req_bits_pe_control_propagate_T; // @[ExecuteController.scala:201:62]
assign _mesh_io_req_bits_pe_control_propagate_T = _T_202; // @[ExecuteController.scala:192:38, :201:62]
wire _mesh_io_req_bits_flush_T; // @[ExecuteController.scala:207:47]
assign _mesh_io_req_bits_flush_T = _T_202; // @[ExecuteController.scala:192:38, :207:47]
wire _mesh_io_req_bits_pe_control_propagate_T_1 = _mesh_io_req_bits_pe_control_propagate_T ? in_prop_flush : _mesh_cntl_signals_q_io_deq_bits_prop; // @[ExecuteController.scala:92:26, :178:35, :201:{47,62}]
wire _mesh_io_req_bits_flush_T_1 = ~_mesh_cntl_signals_q_io_deq_valid; // @[ExecuteController.scala:178:35, :207:60]
wire _mesh_io_req_bits_flush_T_2 = _mesh_io_req_bits_flush_T & _mesh_io_req_bits_flush_T_1; // @[ExecuteController.scala:207:{47,57,60}]
wire _mesh_io_req_bits_flush_T_3 = _mesh_io_req_bits_flush_T_2; // @[ExecuteController.scala:207:{32,57}]
wire _GEN_5 = _mesh_io_tags_in_progress_0_addr_is_acc_addr & _mesh_io_tags_in_progress_0_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T = _GEN_5; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T = _GEN_5; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_1 = _raw_hazard_pre_is_garbage_T & _mesh_io_tags_in_progress_0_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_2 = &_mesh_io_tags_in_progress_0_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_3 = _raw_hazard_pre_is_garbage_T_1 & _raw_hazard_pre_is_garbage_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_4; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage = _raw_hazard_pre_is_garbage_T_3 & _raw_hazard_pre_is_garbage_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_6; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_5; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_4; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_3; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_2; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_1; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_1 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_5 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_9 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_13 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_17 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_21 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_25 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_29 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_33 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_37 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_41 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_45 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_49 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_53 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_57 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_61 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T = _raw_hazard_pre_pre_raw_haz_WIRE_1[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_data = _raw_hazard_pre_pre_raw_haz_T; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_1 = _raw_hazard_pre_pre_raw_haz_WIRE_1[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_1; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_2 = _raw_hazard_pre_pre_raw_haz_WIRE_1[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_garbage = _raw_hazard_pre_pre_raw_haz_T_2; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_3 = _raw_hazard_pre_pre_raw_haz_WIRE_1[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_2 = _raw_hazard_pre_pre_raw_haz_T_3; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_3 = _raw_hazard_pre_pre_raw_haz_WIRE_2; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_3; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_4 = _raw_hazard_pre_pre_raw_haz_WIRE_1[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_4; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_5 = _raw_hazard_pre_pre_raw_haz_WIRE_1[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_accumulate = _raw_hazard_pre_pre_raw_haz_T_5; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_6 = _raw_hazard_pre_pre_raw_haz_WIRE_1[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_6; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_7 = _mesh_io_tags_in_progress_0_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_8 = _mesh_io_tags_in_progress_0_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz = _raw_hazard_pre_pre_raw_haz_T_7 & _raw_hazard_pre_pre_raw_haz_T_8; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_6; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_5; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_4; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_3; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_2; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_1; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_1 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_9 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_17 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_25 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_33 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_41 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_49 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_57 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_65 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_73 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_81 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_89 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_97 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_105 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_113 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_121 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_1 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_5 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_9 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_13 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_17 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_21 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_25 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_29 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_33 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_37 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_41 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_45 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_49 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_53 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_57 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_61 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T = _raw_hazard_pre_mul_raw_haz_WIRE_1[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_data = _raw_hazard_pre_mul_raw_haz_T; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_1 = _raw_hazard_pre_mul_raw_haz_WIRE_1[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_1; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_2 = _raw_hazard_pre_mul_raw_haz_WIRE_1[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_garbage = _raw_hazard_pre_mul_raw_haz_T_2; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_3 = _raw_hazard_pre_mul_raw_haz_WIRE_1[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_2 = _raw_hazard_pre_mul_raw_haz_T_3; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_3 = _raw_hazard_pre_mul_raw_haz_WIRE_2; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_3; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_4 = _raw_hazard_pre_mul_raw_haz_WIRE_1[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_4; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_5 = _raw_hazard_pre_mul_raw_haz_WIRE_1[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_accumulate = _raw_hazard_pre_mul_raw_haz_T_5; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_6 = _raw_hazard_pre_mul_raw_haz_WIRE_1[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_6; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_7 = _mesh_io_tags_in_progress_0_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_8 = _mesh_io_tags_in_progress_0_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_9 = _raw_hazard_pre_mul_raw_haz_T_7 & _raw_hazard_pre_mul_raw_haz_T_8; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_16; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_15; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_14; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_7; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_12; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_11; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_10; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_5 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_13 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_21 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_29 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_37 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_45 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_53 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_61 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_69 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_77 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_85 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_93 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_101 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_109 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_117 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_125 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _in_prop_flush_qual2_WIRE = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_10 = _raw_hazard_pre_mul_raw_haz_WIRE_5[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_4_data = _raw_hazard_pre_mul_raw_haz_T_10; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_11 = _raw_hazard_pre_mul_raw_haz_WIRE_5[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_4_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_11; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_12 = _raw_hazard_pre_mul_raw_haz_WIRE_5[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_4_garbage = _raw_hazard_pre_mul_raw_haz_T_12; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_13 = _raw_hazard_pre_mul_raw_haz_WIRE_5[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_6 = _raw_hazard_pre_mul_raw_haz_T_13; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_7 = _raw_hazard_pre_mul_raw_haz_WIRE_6; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_4_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_7; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_14 = _raw_hazard_pre_mul_raw_haz_WIRE_5[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_4_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_14; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_15 = _raw_hazard_pre_mul_raw_haz_WIRE_5[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_4_accumulate = _raw_hazard_pre_mul_raw_haz_T_15; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_16 = _raw_hazard_pre_mul_raw_haz_WIRE_5[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_4_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_16; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_17 = _mesh_io_tags_in_progress_0_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_4_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_18 = _mesh_io_tags_in_progress_0_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_4_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_19 = _raw_hazard_pre_mul_raw_haz_T_17 & _raw_hazard_pre_mul_raw_haz_T_18; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz = _raw_hazard_pre_mul_raw_haz_T_9 | _raw_hazard_pre_mul_raw_haz_T_19; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T = ~raw_hazard_pre_is_garbage; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_1 = raw_hazard_pre_pre_raw_haz | raw_hazard_pre_mul_raw_haz; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_2 = _raw_hazard_pre_T & _raw_hazard_pre_T_1; // @[ExecuteController.scala:217:{5,17,33}]
wire _raw_hazard_pre_T_4 = _raw_hazard_pre_T_2; // @[ExecuteController.scala:217:{17,49}]
wire _GEN_6 = _mesh_io_tags_in_progress_1_addr_is_acc_addr & _mesh_io_tags_in_progress_1_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_5; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T_5 = _GEN_6; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T_5; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T_5 = _GEN_6; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_6 = _raw_hazard_pre_is_garbage_T_5 & _mesh_io_tags_in_progress_1_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_7 = &_mesh_io_tags_in_progress_1_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_8 = _raw_hazard_pre_is_garbage_T_6 & _raw_hazard_pre_is_garbage_T_7; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_9; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage_1 = _raw_hazard_pre_is_garbage_T_8 & _raw_hazard_pre_is_garbage_T_9; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_15; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_14; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_13; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_7; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_11; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_10; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T_9; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_9 = _raw_hazard_pre_pre_raw_haz_WIRE_5[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_4_data = _raw_hazard_pre_pre_raw_haz_T_9; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_10 = _raw_hazard_pre_pre_raw_haz_WIRE_5[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_4_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_10; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_11 = _raw_hazard_pre_pre_raw_haz_WIRE_5[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_4_garbage = _raw_hazard_pre_pre_raw_haz_T_11; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_12 = _raw_hazard_pre_pre_raw_haz_WIRE_5[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_6 = _raw_hazard_pre_pre_raw_haz_T_12; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_7 = _raw_hazard_pre_pre_raw_haz_WIRE_6; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_4_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_7; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_13 = _raw_hazard_pre_pre_raw_haz_WIRE_5[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_4_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_13; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_14 = _raw_hazard_pre_pre_raw_haz_WIRE_5[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_4_accumulate = _raw_hazard_pre_pre_raw_haz_T_14; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_15 = _raw_hazard_pre_pre_raw_haz_WIRE_5[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_4_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_15; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_16 = _mesh_io_tags_in_progress_1_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_4_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_17 = _mesh_io_tags_in_progress_1_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_4_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz_1 = _raw_hazard_pre_pre_raw_haz_T_16 & _raw_hazard_pre_pre_raw_haz_T_17; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_26; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_25; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_24; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_11; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_22; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_21; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_20; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_20 = _raw_hazard_pre_mul_raw_haz_WIRE_9[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_8_data = _raw_hazard_pre_mul_raw_haz_T_20; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_21 = _raw_hazard_pre_mul_raw_haz_WIRE_9[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_8_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_21; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_22 = _raw_hazard_pre_mul_raw_haz_WIRE_9[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_8_garbage = _raw_hazard_pre_mul_raw_haz_T_22; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_23 = _raw_hazard_pre_mul_raw_haz_WIRE_9[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_10 = _raw_hazard_pre_mul_raw_haz_T_23; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_11 = _raw_hazard_pre_mul_raw_haz_WIRE_10; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_8_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_11; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_24 = _raw_hazard_pre_mul_raw_haz_WIRE_9[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_8_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_24; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_25 = _raw_hazard_pre_mul_raw_haz_WIRE_9[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_8_accumulate = _raw_hazard_pre_mul_raw_haz_T_25; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_26 = _raw_hazard_pre_mul_raw_haz_WIRE_9[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_8_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_26; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_27 = _mesh_io_tags_in_progress_1_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_8_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_28 = _mesh_io_tags_in_progress_1_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_8_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_29 = _raw_hazard_pre_mul_raw_haz_T_27 & _raw_hazard_pre_mul_raw_haz_T_28; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_36; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_35; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_34; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_15; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_32; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_31; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_30; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_30 = _raw_hazard_pre_mul_raw_haz_WIRE_13[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_12_data = _raw_hazard_pre_mul_raw_haz_T_30; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_31 = _raw_hazard_pre_mul_raw_haz_WIRE_13[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_12_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_31; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_32 = _raw_hazard_pre_mul_raw_haz_WIRE_13[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_12_garbage = _raw_hazard_pre_mul_raw_haz_T_32; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_33 = _raw_hazard_pre_mul_raw_haz_WIRE_13[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_14 = _raw_hazard_pre_mul_raw_haz_T_33; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_15 = _raw_hazard_pre_mul_raw_haz_WIRE_14; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_12_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_15; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_34 = _raw_hazard_pre_mul_raw_haz_WIRE_13[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_12_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_34; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_35 = _raw_hazard_pre_mul_raw_haz_WIRE_13[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_12_accumulate = _raw_hazard_pre_mul_raw_haz_T_35; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_36 = _raw_hazard_pre_mul_raw_haz_WIRE_13[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_12_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_36; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_37 = _mesh_io_tags_in_progress_1_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_12_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_38 = _mesh_io_tags_in_progress_1_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_12_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_39 = _raw_hazard_pre_mul_raw_haz_T_37 & _raw_hazard_pre_mul_raw_haz_T_38; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz_1 = _raw_hazard_pre_mul_raw_haz_T_29 | _raw_hazard_pre_mul_raw_haz_T_39; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_5 = ~raw_hazard_pre_is_garbage_1; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_6 = raw_hazard_pre_pre_raw_haz_1 | raw_hazard_pre_mul_raw_haz_1; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_7 = _raw_hazard_pre_T_5 & _raw_hazard_pre_T_6; // @[ExecuteController.scala:217:{5,17,33}]
wire _raw_hazard_pre_T_9 = _raw_hazard_pre_T_7; // @[ExecuteController.scala:217:{17,49}]
wire _GEN_7 = _mesh_io_tags_in_progress_2_addr_is_acc_addr & _mesh_io_tags_in_progress_2_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_10; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T_10 = _GEN_7; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T_10; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T_10 = _GEN_7; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_11 = _raw_hazard_pre_is_garbage_T_10 & _mesh_io_tags_in_progress_2_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_12 = &_mesh_io_tags_in_progress_2_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_13 = _raw_hazard_pre_is_garbage_T_11 & _raw_hazard_pre_is_garbage_T_12; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_14; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage_2 = _raw_hazard_pre_is_garbage_T_13 & _raw_hazard_pre_is_garbage_T_14; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_24; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_23; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_22; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_11; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_20; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_19; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T_18; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_18 = _raw_hazard_pre_pre_raw_haz_WIRE_9[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_8_data = _raw_hazard_pre_pre_raw_haz_T_18; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_19 = _raw_hazard_pre_pre_raw_haz_WIRE_9[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_8_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_19; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_20 = _raw_hazard_pre_pre_raw_haz_WIRE_9[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_8_garbage = _raw_hazard_pre_pre_raw_haz_T_20; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_21 = _raw_hazard_pre_pre_raw_haz_WIRE_9[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_10 = _raw_hazard_pre_pre_raw_haz_T_21; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_11 = _raw_hazard_pre_pre_raw_haz_WIRE_10; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_8_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_11; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_22 = _raw_hazard_pre_pre_raw_haz_WIRE_9[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_8_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_22; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_23 = _raw_hazard_pre_pre_raw_haz_WIRE_9[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_8_accumulate = _raw_hazard_pre_pre_raw_haz_T_23; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_24 = _raw_hazard_pre_pre_raw_haz_WIRE_9[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_8_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_24; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_25 = _mesh_io_tags_in_progress_2_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_8_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_26 = _mesh_io_tags_in_progress_2_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_8_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz_2 = _raw_hazard_pre_pre_raw_haz_T_25 & _raw_hazard_pre_pre_raw_haz_T_26; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_46; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_45; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_44; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_19; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_42; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_41; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_40; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_40 = _raw_hazard_pre_mul_raw_haz_WIRE_17[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_16_data = _raw_hazard_pre_mul_raw_haz_T_40; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_41 = _raw_hazard_pre_mul_raw_haz_WIRE_17[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_16_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_41; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_42 = _raw_hazard_pre_mul_raw_haz_WIRE_17[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_16_garbage = _raw_hazard_pre_mul_raw_haz_T_42; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_43 = _raw_hazard_pre_mul_raw_haz_WIRE_17[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_18 = _raw_hazard_pre_mul_raw_haz_T_43; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_19 = _raw_hazard_pre_mul_raw_haz_WIRE_18; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_16_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_19; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_44 = _raw_hazard_pre_mul_raw_haz_WIRE_17[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_16_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_44; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_45 = _raw_hazard_pre_mul_raw_haz_WIRE_17[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_16_accumulate = _raw_hazard_pre_mul_raw_haz_T_45; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_46 = _raw_hazard_pre_mul_raw_haz_WIRE_17[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_16_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_46; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_47 = _mesh_io_tags_in_progress_2_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_16_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_48 = _mesh_io_tags_in_progress_2_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_16_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_49 = _raw_hazard_pre_mul_raw_haz_T_47 & _raw_hazard_pre_mul_raw_haz_T_48; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_56; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_55; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_54; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_23; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_52; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_51; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_50; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_50 = _raw_hazard_pre_mul_raw_haz_WIRE_21[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_20_data = _raw_hazard_pre_mul_raw_haz_T_50; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_51 = _raw_hazard_pre_mul_raw_haz_WIRE_21[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_20_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_51; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_52 = _raw_hazard_pre_mul_raw_haz_WIRE_21[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_20_garbage = _raw_hazard_pre_mul_raw_haz_T_52; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_53 = _raw_hazard_pre_mul_raw_haz_WIRE_21[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_22 = _raw_hazard_pre_mul_raw_haz_T_53; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_23 = _raw_hazard_pre_mul_raw_haz_WIRE_22; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_20_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_23; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_54 = _raw_hazard_pre_mul_raw_haz_WIRE_21[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_20_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_54; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_55 = _raw_hazard_pre_mul_raw_haz_WIRE_21[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_20_accumulate = _raw_hazard_pre_mul_raw_haz_T_55; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_56 = _raw_hazard_pre_mul_raw_haz_WIRE_21[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_20_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_56; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_57 = _mesh_io_tags_in_progress_2_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_20_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_58 = _mesh_io_tags_in_progress_2_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_20_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_59 = _raw_hazard_pre_mul_raw_haz_T_57 & _raw_hazard_pre_mul_raw_haz_T_58; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz_2 = _raw_hazard_pre_mul_raw_haz_T_49 | _raw_hazard_pre_mul_raw_haz_T_59; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_10 = ~raw_hazard_pre_is_garbage_2; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_11 = raw_hazard_pre_pre_raw_haz_2 | raw_hazard_pre_mul_raw_haz_2; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_12 = _raw_hazard_pre_T_10 & _raw_hazard_pre_T_11; // @[ExecuteController.scala:217:{5,17,33}]
wire _raw_hazard_pre_T_14 = _raw_hazard_pre_T_12; // @[ExecuteController.scala:217:{17,49}]
wire _GEN_8 = _mesh_io_tags_in_progress_3_addr_is_acc_addr & _mesh_io_tags_in_progress_3_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_15; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T_15 = _GEN_8; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T_15; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T_15 = _GEN_8; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_16 = _raw_hazard_pre_is_garbage_T_15 & _mesh_io_tags_in_progress_3_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_17 = &_mesh_io_tags_in_progress_3_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_18 = _raw_hazard_pre_is_garbage_T_16 & _raw_hazard_pre_is_garbage_T_17; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_19; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage_3 = _raw_hazard_pre_is_garbage_T_18 & _raw_hazard_pre_is_garbage_T_19; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_33; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_32; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_31; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_15; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_29; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_28; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T_27; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_27 = _raw_hazard_pre_pre_raw_haz_WIRE_13[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_12_data = _raw_hazard_pre_pre_raw_haz_T_27; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_28 = _raw_hazard_pre_pre_raw_haz_WIRE_13[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_12_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_28; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_29 = _raw_hazard_pre_pre_raw_haz_WIRE_13[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_12_garbage = _raw_hazard_pre_pre_raw_haz_T_29; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_30 = _raw_hazard_pre_pre_raw_haz_WIRE_13[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_14 = _raw_hazard_pre_pre_raw_haz_T_30; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_15 = _raw_hazard_pre_pre_raw_haz_WIRE_14; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_12_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_15; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_31 = _raw_hazard_pre_pre_raw_haz_WIRE_13[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_12_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_31; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_32 = _raw_hazard_pre_pre_raw_haz_WIRE_13[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_12_accumulate = _raw_hazard_pre_pre_raw_haz_T_32; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_33 = _raw_hazard_pre_pre_raw_haz_WIRE_13[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_12_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_33; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_34 = _mesh_io_tags_in_progress_3_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_12_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_35 = _mesh_io_tags_in_progress_3_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_12_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz_3 = _raw_hazard_pre_pre_raw_haz_T_34 & _raw_hazard_pre_pre_raw_haz_T_35; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_66; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_65; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_64; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_27; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_62; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_61; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_60; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_60 = _raw_hazard_pre_mul_raw_haz_WIRE_25[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_24_data = _raw_hazard_pre_mul_raw_haz_T_60; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_61 = _raw_hazard_pre_mul_raw_haz_WIRE_25[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_24_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_61; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_62 = _raw_hazard_pre_mul_raw_haz_WIRE_25[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_24_garbage = _raw_hazard_pre_mul_raw_haz_T_62; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_63 = _raw_hazard_pre_mul_raw_haz_WIRE_25[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_26 = _raw_hazard_pre_mul_raw_haz_T_63; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_27 = _raw_hazard_pre_mul_raw_haz_WIRE_26; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_24_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_27; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_64 = _raw_hazard_pre_mul_raw_haz_WIRE_25[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_24_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_64; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_65 = _raw_hazard_pre_mul_raw_haz_WIRE_25[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_24_accumulate = _raw_hazard_pre_mul_raw_haz_T_65; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_66 = _raw_hazard_pre_mul_raw_haz_WIRE_25[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_24_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_66; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_67 = _mesh_io_tags_in_progress_3_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_24_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_68 = _mesh_io_tags_in_progress_3_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_24_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_69 = _raw_hazard_pre_mul_raw_haz_T_67 & _raw_hazard_pre_mul_raw_haz_T_68; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_76; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_75; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_74; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_31; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_72; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_71; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_70; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_70 = _raw_hazard_pre_mul_raw_haz_WIRE_29[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_28_data = _raw_hazard_pre_mul_raw_haz_T_70; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_71 = _raw_hazard_pre_mul_raw_haz_WIRE_29[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_28_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_71; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_72 = _raw_hazard_pre_mul_raw_haz_WIRE_29[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_28_garbage = _raw_hazard_pre_mul_raw_haz_T_72; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_73 = _raw_hazard_pre_mul_raw_haz_WIRE_29[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_30 = _raw_hazard_pre_mul_raw_haz_T_73; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_31 = _raw_hazard_pre_mul_raw_haz_WIRE_30; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_28_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_31; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_74 = _raw_hazard_pre_mul_raw_haz_WIRE_29[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_28_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_74; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_75 = _raw_hazard_pre_mul_raw_haz_WIRE_29[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_28_accumulate = _raw_hazard_pre_mul_raw_haz_T_75; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_76 = _raw_hazard_pre_mul_raw_haz_WIRE_29[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_28_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_76; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_77 = _mesh_io_tags_in_progress_3_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_28_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_78 = _mesh_io_tags_in_progress_3_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_28_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_79 = _raw_hazard_pre_mul_raw_haz_T_77 & _raw_hazard_pre_mul_raw_haz_T_78; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz_3 = _raw_hazard_pre_mul_raw_haz_T_69 | _raw_hazard_pre_mul_raw_haz_T_79; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_15 = ~raw_hazard_pre_is_garbage_3; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_16 = raw_hazard_pre_pre_raw_haz_3 | raw_hazard_pre_mul_raw_haz_3; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_17 = _raw_hazard_pre_T_15 & _raw_hazard_pre_T_16; // @[ExecuteController.scala:217:{5,17,33}]
wire _raw_hazard_pre_T_19 = _raw_hazard_pre_T_17; // @[ExecuteController.scala:217:{17,49}]
wire _GEN_9 = _mesh_io_tags_in_progress_4_addr_is_acc_addr & _mesh_io_tags_in_progress_4_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_20; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T_20 = _GEN_9; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T_20; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T_20 = _GEN_9; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_21 = _raw_hazard_pre_is_garbage_T_20 & _mesh_io_tags_in_progress_4_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_22 = &_mesh_io_tags_in_progress_4_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_23 = _raw_hazard_pre_is_garbage_T_21 & _raw_hazard_pre_is_garbage_T_22; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_24; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage_4 = _raw_hazard_pre_is_garbage_T_23 & _raw_hazard_pre_is_garbage_T_24; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_42; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_41; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_40; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_19; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_38; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_37; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T_36; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_36 = _raw_hazard_pre_pre_raw_haz_WIRE_17[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_16_data = _raw_hazard_pre_pre_raw_haz_T_36; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_37 = _raw_hazard_pre_pre_raw_haz_WIRE_17[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_16_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_37; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_38 = _raw_hazard_pre_pre_raw_haz_WIRE_17[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_16_garbage = _raw_hazard_pre_pre_raw_haz_T_38; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_39 = _raw_hazard_pre_pre_raw_haz_WIRE_17[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_18 = _raw_hazard_pre_pre_raw_haz_T_39; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_19 = _raw_hazard_pre_pre_raw_haz_WIRE_18; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_16_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_19; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_40 = _raw_hazard_pre_pre_raw_haz_WIRE_17[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_16_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_40; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_41 = _raw_hazard_pre_pre_raw_haz_WIRE_17[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_16_accumulate = _raw_hazard_pre_pre_raw_haz_T_41; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_42 = _raw_hazard_pre_pre_raw_haz_WIRE_17[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_16_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_42; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_43 = _mesh_io_tags_in_progress_4_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_16_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_44 = _mesh_io_tags_in_progress_4_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_16_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz_4 = _raw_hazard_pre_pre_raw_haz_T_43 & _raw_hazard_pre_pre_raw_haz_T_44; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_86; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_85; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_84; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_35; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_82; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_81; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_80; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_80 = _raw_hazard_pre_mul_raw_haz_WIRE_33[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_32_data = _raw_hazard_pre_mul_raw_haz_T_80; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_81 = _raw_hazard_pre_mul_raw_haz_WIRE_33[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_32_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_81; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_82 = _raw_hazard_pre_mul_raw_haz_WIRE_33[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_32_garbage = _raw_hazard_pre_mul_raw_haz_T_82; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_83 = _raw_hazard_pre_mul_raw_haz_WIRE_33[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_34 = _raw_hazard_pre_mul_raw_haz_T_83; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_35 = _raw_hazard_pre_mul_raw_haz_WIRE_34; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_32_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_35; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_84 = _raw_hazard_pre_mul_raw_haz_WIRE_33[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_32_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_84; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_85 = _raw_hazard_pre_mul_raw_haz_WIRE_33[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_32_accumulate = _raw_hazard_pre_mul_raw_haz_T_85; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_86 = _raw_hazard_pre_mul_raw_haz_WIRE_33[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_32_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_86; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_87 = _mesh_io_tags_in_progress_4_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_32_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_88 = _mesh_io_tags_in_progress_4_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_32_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_89 = _raw_hazard_pre_mul_raw_haz_T_87 & _raw_hazard_pre_mul_raw_haz_T_88; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_96; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_95; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_94; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_39; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_92; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_91; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_90; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_90 = _raw_hazard_pre_mul_raw_haz_WIRE_37[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_36_data = _raw_hazard_pre_mul_raw_haz_T_90; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_91 = _raw_hazard_pre_mul_raw_haz_WIRE_37[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_36_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_91; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_92 = _raw_hazard_pre_mul_raw_haz_WIRE_37[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_36_garbage = _raw_hazard_pre_mul_raw_haz_T_92; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_93 = _raw_hazard_pre_mul_raw_haz_WIRE_37[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_38 = _raw_hazard_pre_mul_raw_haz_T_93; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_39 = _raw_hazard_pre_mul_raw_haz_WIRE_38; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_36_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_39; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_94 = _raw_hazard_pre_mul_raw_haz_WIRE_37[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_36_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_94; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_95 = _raw_hazard_pre_mul_raw_haz_WIRE_37[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_36_accumulate = _raw_hazard_pre_mul_raw_haz_T_95; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_96 = _raw_hazard_pre_mul_raw_haz_WIRE_37[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_36_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_96; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_97 = _mesh_io_tags_in_progress_4_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_36_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_98 = _mesh_io_tags_in_progress_4_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_36_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_99 = _raw_hazard_pre_mul_raw_haz_T_97 & _raw_hazard_pre_mul_raw_haz_T_98; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz_4 = _raw_hazard_pre_mul_raw_haz_T_89 | _raw_hazard_pre_mul_raw_haz_T_99; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_20 = ~raw_hazard_pre_is_garbage_4; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_21 = raw_hazard_pre_pre_raw_haz_4 | raw_hazard_pre_mul_raw_haz_4; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_22 = _raw_hazard_pre_T_20 & _raw_hazard_pre_T_21; // @[ExecuteController.scala:217:{5,17,33}]
wire _raw_hazard_pre_T_24 = _raw_hazard_pre_T_22; // @[ExecuteController.scala:217:{17,49}]
wire _GEN_10 = _mesh_io_tags_in_progress_5_addr_is_acc_addr & _mesh_io_tags_in_progress_5_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_25; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T_25 = _GEN_10; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T_25; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T_25 = _GEN_10; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_26 = _raw_hazard_pre_is_garbage_T_25 & _mesh_io_tags_in_progress_5_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_27 = &_mesh_io_tags_in_progress_5_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_28 = _raw_hazard_pre_is_garbage_T_26 & _raw_hazard_pre_is_garbage_T_27; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_29; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage_5 = _raw_hazard_pre_is_garbage_T_28 & _raw_hazard_pre_is_garbage_T_29; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_51; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_50; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_49; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_23; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_47; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_46; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T_45; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_45 = _raw_hazard_pre_pre_raw_haz_WIRE_21[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_20_data = _raw_hazard_pre_pre_raw_haz_T_45; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_46 = _raw_hazard_pre_pre_raw_haz_WIRE_21[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_20_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_46; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_47 = _raw_hazard_pre_pre_raw_haz_WIRE_21[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_20_garbage = _raw_hazard_pre_pre_raw_haz_T_47; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_48 = _raw_hazard_pre_pre_raw_haz_WIRE_21[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_22 = _raw_hazard_pre_pre_raw_haz_T_48; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_23 = _raw_hazard_pre_pre_raw_haz_WIRE_22; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_20_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_23; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_49 = _raw_hazard_pre_pre_raw_haz_WIRE_21[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_20_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_49; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_50 = _raw_hazard_pre_pre_raw_haz_WIRE_21[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_20_accumulate = _raw_hazard_pre_pre_raw_haz_T_50; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_51 = _raw_hazard_pre_pre_raw_haz_WIRE_21[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_20_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_51; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_52 = _mesh_io_tags_in_progress_5_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_20_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_53 = _mesh_io_tags_in_progress_5_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_20_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz_5 = _raw_hazard_pre_pre_raw_haz_T_52 & _raw_hazard_pre_pre_raw_haz_T_53; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_106; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_105; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_104; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_43; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_102; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_101; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_100; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_100 = _raw_hazard_pre_mul_raw_haz_WIRE_41[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_40_data = _raw_hazard_pre_mul_raw_haz_T_100; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_101 = _raw_hazard_pre_mul_raw_haz_WIRE_41[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_40_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_101; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_102 = _raw_hazard_pre_mul_raw_haz_WIRE_41[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_40_garbage = _raw_hazard_pre_mul_raw_haz_T_102; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_103 = _raw_hazard_pre_mul_raw_haz_WIRE_41[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_42 = _raw_hazard_pre_mul_raw_haz_T_103; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_43 = _raw_hazard_pre_mul_raw_haz_WIRE_42; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_40_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_43; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_104 = _raw_hazard_pre_mul_raw_haz_WIRE_41[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_40_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_104; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_105 = _raw_hazard_pre_mul_raw_haz_WIRE_41[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_40_accumulate = _raw_hazard_pre_mul_raw_haz_T_105; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_106 = _raw_hazard_pre_mul_raw_haz_WIRE_41[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_40_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_106; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_107 = _mesh_io_tags_in_progress_5_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_40_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_108 = _mesh_io_tags_in_progress_5_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_40_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_109 = _raw_hazard_pre_mul_raw_haz_T_107 & _raw_hazard_pre_mul_raw_haz_T_108; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_116; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_115; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_114; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_47; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_112; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_111; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_110; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_110 = _raw_hazard_pre_mul_raw_haz_WIRE_45[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_44_data = _raw_hazard_pre_mul_raw_haz_T_110; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_111 = _raw_hazard_pre_mul_raw_haz_WIRE_45[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_44_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_111; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_112 = _raw_hazard_pre_mul_raw_haz_WIRE_45[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_44_garbage = _raw_hazard_pre_mul_raw_haz_T_112; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_113 = _raw_hazard_pre_mul_raw_haz_WIRE_45[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_46 = _raw_hazard_pre_mul_raw_haz_T_113; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_47 = _raw_hazard_pre_mul_raw_haz_WIRE_46; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_44_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_47; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_114 = _raw_hazard_pre_mul_raw_haz_WIRE_45[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_44_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_114; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_115 = _raw_hazard_pre_mul_raw_haz_WIRE_45[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_44_accumulate = _raw_hazard_pre_mul_raw_haz_T_115; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_116 = _raw_hazard_pre_mul_raw_haz_WIRE_45[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_44_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_116; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_117 = _mesh_io_tags_in_progress_5_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_44_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_118 = _mesh_io_tags_in_progress_5_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_44_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_119 = _raw_hazard_pre_mul_raw_haz_T_117 & _raw_hazard_pre_mul_raw_haz_T_118; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz_5 = _raw_hazard_pre_mul_raw_haz_T_109 | _raw_hazard_pre_mul_raw_haz_T_119; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_25 = ~raw_hazard_pre_is_garbage_5; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_26 = raw_hazard_pre_pre_raw_haz_5 | raw_hazard_pre_mul_raw_haz_5; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_27 = _raw_hazard_pre_T_25 & _raw_hazard_pre_T_26; // @[ExecuteController.scala:217:{5,17,33}]
wire _raw_hazard_pre_T_29 = _raw_hazard_pre_T_27; // @[ExecuteController.scala:217:{17,49}]
wire _GEN_11 = _mesh_io_tags_in_progress_6_addr_is_acc_addr & _mesh_io_tags_in_progress_6_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_30; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T_30 = _GEN_11; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T_30; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T_30 = _GEN_11; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_31 = _raw_hazard_pre_is_garbage_T_30 & _mesh_io_tags_in_progress_6_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_32 = &_mesh_io_tags_in_progress_6_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_33 = _raw_hazard_pre_is_garbage_T_31 & _raw_hazard_pre_is_garbage_T_32; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_34; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage_6 = _raw_hazard_pre_is_garbage_T_33 & _raw_hazard_pre_is_garbage_T_34; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_60; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_59; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_58; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_27; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_56; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_55; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T_54; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_54 = _raw_hazard_pre_pre_raw_haz_WIRE_25[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_24_data = _raw_hazard_pre_pre_raw_haz_T_54; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_55 = _raw_hazard_pre_pre_raw_haz_WIRE_25[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_24_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_55; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_56 = _raw_hazard_pre_pre_raw_haz_WIRE_25[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_24_garbage = _raw_hazard_pre_pre_raw_haz_T_56; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_57 = _raw_hazard_pre_pre_raw_haz_WIRE_25[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_26 = _raw_hazard_pre_pre_raw_haz_T_57; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_27 = _raw_hazard_pre_pre_raw_haz_WIRE_26; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_24_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_27; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_58 = _raw_hazard_pre_pre_raw_haz_WIRE_25[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_24_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_58; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_59 = _raw_hazard_pre_pre_raw_haz_WIRE_25[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_24_accumulate = _raw_hazard_pre_pre_raw_haz_T_59; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_60 = _raw_hazard_pre_pre_raw_haz_WIRE_25[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_24_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_60; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_61 = _mesh_io_tags_in_progress_6_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_24_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_62 = _mesh_io_tags_in_progress_6_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_24_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz_6 = _raw_hazard_pre_pre_raw_haz_T_61 & _raw_hazard_pre_pre_raw_haz_T_62; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_126; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_125; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_124; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_51; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_122; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_121; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_120; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_120 = _raw_hazard_pre_mul_raw_haz_WIRE_49[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_48_data = _raw_hazard_pre_mul_raw_haz_T_120; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_121 = _raw_hazard_pre_mul_raw_haz_WIRE_49[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_48_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_121; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_122 = _raw_hazard_pre_mul_raw_haz_WIRE_49[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_48_garbage = _raw_hazard_pre_mul_raw_haz_T_122; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_123 = _raw_hazard_pre_mul_raw_haz_WIRE_49[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_50 = _raw_hazard_pre_mul_raw_haz_T_123; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_51 = _raw_hazard_pre_mul_raw_haz_WIRE_50; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_48_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_51; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_124 = _raw_hazard_pre_mul_raw_haz_WIRE_49[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_48_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_124; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_125 = _raw_hazard_pre_mul_raw_haz_WIRE_49[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_48_accumulate = _raw_hazard_pre_mul_raw_haz_T_125; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_126 = _raw_hazard_pre_mul_raw_haz_WIRE_49[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_48_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_126; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_127 = _mesh_io_tags_in_progress_6_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_48_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_128 = _mesh_io_tags_in_progress_6_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_48_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_129 = _raw_hazard_pre_mul_raw_haz_T_127 & _raw_hazard_pre_mul_raw_haz_T_128; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_136; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_135; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_134; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_55; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_132; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_131; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_130; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_130 = _raw_hazard_pre_mul_raw_haz_WIRE_53[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_52_data = _raw_hazard_pre_mul_raw_haz_T_130; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_131 = _raw_hazard_pre_mul_raw_haz_WIRE_53[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_52_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_131; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_132 = _raw_hazard_pre_mul_raw_haz_WIRE_53[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_52_garbage = _raw_hazard_pre_mul_raw_haz_T_132; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_133 = _raw_hazard_pre_mul_raw_haz_WIRE_53[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_54 = _raw_hazard_pre_mul_raw_haz_T_133; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_55 = _raw_hazard_pre_mul_raw_haz_WIRE_54; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_52_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_55; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_134 = _raw_hazard_pre_mul_raw_haz_WIRE_53[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_52_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_134; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_135 = _raw_hazard_pre_mul_raw_haz_WIRE_53[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_52_accumulate = _raw_hazard_pre_mul_raw_haz_T_135; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_136 = _raw_hazard_pre_mul_raw_haz_WIRE_53[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_52_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_136; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_137 = _mesh_io_tags_in_progress_6_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_52_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_138 = _mesh_io_tags_in_progress_6_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_52_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_139 = _raw_hazard_pre_mul_raw_haz_T_137 & _raw_hazard_pre_mul_raw_haz_T_138; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz_6 = _raw_hazard_pre_mul_raw_haz_T_129 | _raw_hazard_pre_mul_raw_haz_T_139; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_30 = ~raw_hazard_pre_is_garbage_6; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_31 = raw_hazard_pre_pre_raw_haz_6 | raw_hazard_pre_mul_raw_haz_6; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_32 = _raw_hazard_pre_T_30 & _raw_hazard_pre_T_31; // @[ExecuteController.scala:217:{5,17,33}]
wire _raw_hazard_pre_T_34 = _raw_hazard_pre_T_32; // @[ExecuteController.scala:217:{17,49}]
wire _GEN_12 = _mesh_io_tags_in_progress_7_addr_is_acc_addr & _mesh_io_tags_in_progress_7_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_35; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T_35 = _GEN_12; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T_35; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T_35 = _GEN_12; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_36 = _raw_hazard_pre_is_garbage_T_35 & _mesh_io_tags_in_progress_7_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_37 = &_mesh_io_tags_in_progress_7_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_38 = _raw_hazard_pre_is_garbage_T_36 & _raw_hazard_pre_is_garbage_T_37; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_39; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage_7 = _raw_hazard_pre_is_garbage_T_38 & _raw_hazard_pre_is_garbage_T_39; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_69; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_68; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_67; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_31; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_65; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_64; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T_63; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_63 = _raw_hazard_pre_pre_raw_haz_WIRE_29[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_28_data = _raw_hazard_pre_pre_raw_haz_T_63; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_64 = _raw_hazard_pre_pre_raw_haz_WIRE_29[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_28_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_64; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_65 = _raw_hazard_pre_pre_raw_haz_WIRE_29[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_28_garbage = _raw_hazard_pre_pre_raw_haz_T_65; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_66 = _raw_hazard_pre_pre_raw_haz_WIRE_29[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_30 = _raw_hazard_pre_pre_raw_haz_T_66; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_31 = _raw_hazard_pre_pre_raw_haz_WIRE_30; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_28_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_31; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_67 = _raw_hazard_pre_pre_raw_haz_WIRE_29[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_28_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_67; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_68 = _raw_hazard_pre_pre_raw_haz_WIRE_29[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_28_accumulate = _raw_hazard_pre_pre_raw_haz_T_68; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_69 = _raw_hazard_pre_pre_raw_haz_WIRE_29[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_28_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_69; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_70 = _mesh_io_tags_in_progress_7_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_28_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_71 = _mesh_io_tags_in_progress_7_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_28_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz_7 = _raw_hazard_pre_pre_raw_haz_T_70 & _raw_hazard_pre_pre_raw_haz_T_71; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_146; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_145; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_144; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_59; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_142; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_141; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_140; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_140 = _raw_hazard_pre_mul_raw_haz_WIRE_57[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_56_data = _raw_hazard_pre_mul_raw_haz_T_140; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_141 = _raw_hazard_pre_mul_raw_haz_WIRE_57[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_56_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_141; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_142 = _raw_hazard_pre_mul_raw_haz_WIRE_57[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_56_garbage = _raw_hazard_pre_mul_raw_haz_T_142; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_143 = _raw_hazard_pre_mul_raw_haz_WIRE_57[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_58 = _raw_hazard_pre_mul_raw_haz_T_143; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_59 = _raw_hazard_pre_mul_raw_haz_WIRE_58; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_56_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_59; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_144 = _raw_hazard_pre_mul_raw_haz_WIRE_57[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_56_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_144; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_145 = _raw_hazard_pre_mul_raw_haz_WIRE_57[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_56_accumulate = _raw_hazard_pre_mul_raw_haz_T_145; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_146 = _raw_hazard_pre_mul_raw_haz_WIRE_57[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_56_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_146; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_147 = _mesh_io_tags_in_progress_7_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_56_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_148 = _mesh_io_tags_in_progress_7_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_56_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_149 = _raw_hazard_pre_mul_raw_haz_T_147 & _raw_hazard_pre_mul_raw_haz_T_148; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_156; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_155; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_154; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_63; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_152; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_151; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_150; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_150 = _raw_hazard_pre_mul_raw_haz_WIRE_61[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_60_data = _raw_hazard_pre_mul_raw_haz_T_150; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_151 = _raw_hazard_pre_mul_raw_haz_WIRE_61[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_60_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_151; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_152 = _raw_hazard_pre_mul_raw_haz_WIRE_61[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_60_garbage = _raw_hazard_pre_mul_raw_haz_T_152; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_153 = _raw_hazard_pre_mul_raw_haz_WIRE_61[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_62 = _raw_hazard_pre_mul_raw_haz_T_153; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_63 = _raw_hazard_pre_mul_raw_haz_WIRE_62; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_60_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_63; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_154 = _raw_hazard_pre_mul_raw_haz_WIRE_61[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_60_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_154; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_155 = _raw_hazard_pre_mul_raw_haz_WIRE_61[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_60_accumulate = _raw_hazard_pre_mul_raw_haz_T_155; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_156 = _raw_hazard_pre_mul_raw_haz_WIRE_61[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_60_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_156; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_157 = _mesh_io_tags_in_progress_7_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_60_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_158 = _mesh_io_tags_in_progress_7_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_60_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_159 = _raw_hazard_pre_mul_raw_haz_T_157 & _raw_hazard_pre_mul_raw_haz_T_158; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz_7 = _raw_hazard_pre_mul_raw_haz_T_149 | _raw_hazard_pre_mul_raw_haz_T_159; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_35 = ~raw_hazard_pre_is_garbage_7; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_36 = raw_hazard_pre_pre_raw_haz_7 | raw_hazard_pre_mul_raw_haz_7; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_37 = _raw_hazard_pre_T_35 & _raw_hazard_pre_T_36; // @[ExecuteController.scala:217:{5,17,33}]
wire _raw_hazard_pre_T_39 = _raw_hazard_pre_T_37; // @[ExecuteController.scala:217:{17,49}]
wire _GEN_13 = _mesh_io_tags_in_progress_8_addr_is_acc_addr & _mesh_io_tags_in_progress_8_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_40; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T_40 = _GEN_13; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T_40; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T_40 = _GEN_13; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_41 = _raw_hazard_pre_is_garbage_T_40 & _mesh_io_tags_in_progress_8_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_42 = &_mesh_io_tags_in_progress_8_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_43 = _raw_hazard_pre_is_garbage_T_41 & _raw_hazard_pre_is_garbage_T_42; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_44; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage_8 = _raw_hazard_pre_is_garbage_T_43 & _raw_hazard_pre_is_garbage_T_44; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_78; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_77; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_76; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_35; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_74; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_73; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T_72; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_72 = _raw_hazard_pre_pre_raw_haz_WIRE_33[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_32_data = _raw_hazard_pre_pre_raw_haz_T_72; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_73 = _raw_hazard_pre_pre_raw_haz_WIRE_33[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_32_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_73; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_74 = _raw_hazard_pre_pre_raw_haz_WIRE_33[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_32_garbage = _raw_hazard_pre_pre_raw_haz_T_74; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_75 = _raw_hazard_pre_pre_raw_haz_WIRE_33[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_34 = _raw_hazard_pre_pre_raw_haz_T_75; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_35 = _raw_hazard_pre_pre_raw_haz_WIRE_34; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_32_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_35; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_76 = _raw_hazard_pre_pre_raw_haz_WIRE_33[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_32_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_76; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_77 = _raw_hazard_pre_pre_raw_haz_WIRE_33[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_32_accumulate = _raw_hazard_pre_pre_raw_haz_T_77; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_78 = _raw_hazard_pre_pre_raw_haz_WIRE_33[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_32_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_78; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_79 = _mesh_io_tags_in_progress_8_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_32_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_80 = _mesh_io_tags_in_progress_8_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_32_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz_8 = _raw_hazard_pre_pre_raw_haz_T_79 & _raw_hazard_pre_pre_raw_haz_T_80; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_166; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_165; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_164; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_67; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_162; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_161; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_160; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_160 = _raw_hazard_pre_mul_raw_haz_WIRE_65[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_64_data = _raw_hazard_pre_mul_raw_haz_T_160; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_161 = _raw_hazard_pre_mul_raw_haz_WIRE_65[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_64_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_161; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_162 = _raw_hazard_pre_mul_raw_haz_WIRE_65[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_64_garbage = _raw_hazard_pre_mul_raw_haz_T_162; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_163 = _raw_hazard_pre_mul_raw_haz_WIRE_65[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_66 = _raw_hazard_pre_mul_raw_haz_T_163; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_67 = _raw_hazard_pre_mul_raw_haz_WIRE_66; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_64_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_67; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_164 = _raw_hazard_pre_mul_raw_haz_WIRE_65[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_64_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_164; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_165 = _raw_hazard_pre_mul_raw_haz_WIRE_65[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_64_accumulate = _raw_hazard_pre_mul_raw_haz_T_165; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_166 = _raw_hazard_pre_mul_raw_haz_WIRE_65[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_64_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_166; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_167 = _mesh_io_tags_in_progress_8_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_64_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_168 = _mesh_io_tags_in_progress_8_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_64_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_169 = _raw_hazard_pre_mul_raw_haz_T_167 & _raw_hazard_pre_mul_raw_haz_T_168; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_176; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_175; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_174; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_71; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_172; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_171; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_170; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_170 = _raw_hazard_pre_mul_raw_haz_WIRE_69[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_68_data = _raw_hazard_pre_mul_raw_haz_T_170; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_171 = _raw_hazard_pre_mul_raw_haz_WIRE_69[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_68_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_171; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_172 = _raw_hazard_pre_mul_raw_haz_WIRE_69[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_68_garbage = _raw_hazard_pre_mul_raw_haz_T_172; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_173 = _raw_hazard_pre_mul_raw_haz_WIRE_69[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_70 = _raw_hazard_pre_mul_raw_haz_T_173; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_71 = _raw_hazard_pre_mul_raw_haz_WIRE_70; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_68_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_71; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_174 = _raw_hazard_pre_mul_raw_haz_WIRE_69[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_68_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_174; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_175 = _raw_hazard_pre_mul_raw_haz_WIRE_69[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_68_accumulate = _raw_hazard_pre_mul_raw_haz_T_175; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_176 = _raw_hazard_pre_mul_raw_haz_WIRE_69[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_68_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_176; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_177 = _mesh_io_tags_in_progress_8_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_68_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_178 = _mesh_io_tags_in_progress_8_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_68_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_179 = _raw_hazard_pre_mul_raw_haz_T_177 & _raw_hazard_pre_mul_raw_haz_T_178; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz_8 = _raw_hazard_pre_mul_raw_haz_T_169 | _raw_hazard_pre_mul_raw_haz_T_179; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_40 = ~raw_hazard_pre_is_garbage_8; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_41 = raw_hazard_pre_pre_raw_haz_8 | raw_hazard_pre_mul_raw_haz_8; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_42 = _raw_hazard_pre_T_40 & _raw_hazard_pre_T_41; // @[ExecuteController.scala:217:{5,17,33}]
wire _raw_hazard_pre_T_44 = _raw_hazard_pre_T_42; // @[ExecuteController.scala:217:{17,49}]
wire _GEN_14 = _mesh_io_tags_in_progress_9_addr_is_acc_addr & _mesh_io_tags_in_progress_9_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_45; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T_45 = _GEN_14; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T_45; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T_45 = _GEN_14; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_46 = _raw_hazard_pre_is_garbage_T_45 & _mesh_io_tags_in_progress_9_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_47 = &_mesh_io_tags_in_progress_9_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_48 = _raw_hazard_pre_is_garbage_T_46 & _raw_hazard_pre_is_garbage_T_47; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_49; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage_9 = _raw_hazard_pre_is_garbage_T_48 & _raw_hazard_pre_is_garbage_T_49; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_87; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_86; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_85; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_39; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_83; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_82; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T_81; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_81 = _raw_hazard_pre_pre_raw_haz_WIRE_37[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_36_data = _raw_hazard_pre_pre_raw_haz_T_81; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_82 = _raw_hazard_pre_pre_raw_haz_WIRE_37[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_36_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_82; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_83 = _raw_hazard_pre_pre_raw_haz_WIRE_37[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_36_garbage = _raw_hazard_pre_pre_raw_haz_T_83; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_84 = _raw_hazard_pre_pre_raw_haz_WIRE_37[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_38 = _raw_hazard_pre_pre_raw_haz_T_84; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_39 = _raw_hazard_pre_pre_raw_haz_WIRE_38; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_36_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_39; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_85 = _raw_hazard_pre_pre_raw_haz_WIRE_37[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_36_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_85; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_86 = _raw_hazard_pre_pre_raw_haz_WIRE_37[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_36_accumulate = _raw_hazard_pre_pre_raw_haz_T_86; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_87 = _raw_hazard_pre_pre_raw_haz_WIRE_37[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_36_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_87; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_88 = _mesh_io_tags_in_progress_9_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_36_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_89 = _mesh_io_tags_in_progress_9_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_36_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz_9 = _raw_hazard_pre_pre_raw_haz_T_88 & _raw_hazard_pre_pre_raw_haz_T_89; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_186; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_185; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_184; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_75; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_182; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_181; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_180; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_180 = _raw_hazard_pre_mul_raw_haz_WIRE_73[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_72_data = _raw_hazard_pre_mul_raw_haz_T_180; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_181 = _raw_hazard_pre_mul_raw_haz_WIRE_73[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_72_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_181; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_182 = _raw_hazard_pre_mul_raw_haz_WIRE_73[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_72_garbage = _raw_hazard_pre_mul_raw_haz_T_182; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_183 = _raw_hazard_pre_mul_raw_haz_WIRE_73[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_74 = _raw_hazard_pre_mul_raw_haz_T_183; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_75 = _raw_hazard_pre_mul_raw_haz_WIRE_74; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_72_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_75; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_184 = _raw_hazard_pre_mul_raw_haz_WIRE_73[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_72_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_184; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_185 = _raw_hazard_pre_mul_raw_haz_WIRE_73[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_72_accumulate = _raw_hazard_pre_mul_raw_haz_T_185; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_186 = _raw_hazard_pre_mul_raw_haz_WIRE_73[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_72_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_186; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_187 = _mesh_io_tags_in_progress_9_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_72_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_188 = _mesh_io_tags_in_progress_9_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_72_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_189 = _raw_hazard_pre_mul_raw_haz_T_187 & _raw_hazard_pre_mul_raw_haz_T_188; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_196; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_195; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_194; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_79; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_192; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_191; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_190; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_190 = _raw_hazard_pre_mul_raw_haz_WIRE_77[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_76_data = _raw_hazard_pre_mul_raw_haz_T_190; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_191 = _raw_hazard_pre_mul_raw_haz_WIRE_77[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_76_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_191; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_192 = _raw_hazard_pre_mul_raw_haz_WIRE_77[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_76_garbage = _raw_hazard_pre_mul_raw_haz_T_192; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_193 = _raw_hazard_pre_mul_raw_haz_WIRE_77[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_78 = _raw_hazard_pre_mul_raw_haz_T_193; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_79 = _raw_hazard_pre_mul_raw_haz_WIRE_78; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_76_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_79; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_194 = _raw_hazard_pre_mul_raw_haz_WIRE_77[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_76_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_194; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_195 = _raw_hazard_pre_mul_raw_haz_WIRE_77[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_76_accumulate = _raw_hazard_pre_mul_raw_haz_T_195; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_196 = _raw_hazard_pre_mul_raw_haz_WIRE_77[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_76_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_196; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_197 = _mesh_io_tags_in_progress_9_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_76_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_198 = _mesh_io_tags_in_progress_9_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_76_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_199 = _raw_hazard_pre_mul_raw_haz_T_197 & _raw_hazard_pre_mul_raw_haz_T_198; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz_9 = _raw_hazard_pre_mul_raw_haz_T_189 | _raw_hazard_pre_mul_raw_haz_T_199; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_45 = ~raw_hazard_pre_is_garbage_9; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_46 = raw_hazard_pre_pre_raw_haz_9 | raw_hazard_pre_mul_raw_haz_9; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_47 = _raw_hazard_pre_T_45 & _raw_hazard_pre_T_46; // @[ExecuteController.scala:217:{5,17,33}]
wire _raw_hazard_pre_T_49 = _raw_hazard_pre_T_47; // @[ExecuteController.scala:217:{17,49}]
wire _GEN_15 = _mesh_io_tags_in_progress_10_addr_is_acc_addr & _mesh_io_tags_in_progress_10_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_50; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T_50 = _GEN_15; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T_50; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T_50 = _GEN_15; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_51 = _raw_hazard_pre_is_garbage_T_50 & _mesh_io_tags_in_progress_10_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_52 = &_mesh_io_tags_in_progress_10_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_53 = _raw_hazard_pre_is_garbage_T_51 & _raw_hazard_pre_is_garbage_T_52; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_54; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage_10 = _raw_hazard_pre_is_garbage_T_53 & _raw_hazard_pre_is_garbage_T_54; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_96; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_95; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_94; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_43; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_92; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_91; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T_90; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_90 = _raw_hazard_pre_pre_raw_haz_WIRE_41[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_40_data = _raw_hazard_pre_pre_raw_haz_T_90; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_91 = _raw_hazard_pre_pre_raw_haz_WIRE_41[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_40_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_91; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_92 = _raw_hazard_pre_pre_raw_haz_WIRE_41[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_40_garbage = _raw_hazard_pre_pre_raw_haz_T_92; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_93 = _raw_hazard_pre_pre_raw_haz_WIRE_41[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_42 = _raw_hazard_pre_pre_raw_haz_T_93; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_43 = _raw_hazard_pre_pre_raw_haz_WIRE_42; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_40_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_43; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_94 = _raw_hazard_pre_pre_raw_haz_WIRE_41[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_40_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_94; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_95 = _raw_hazard_pre_pre_raw_haz_WIRE_41[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_40_accumulate = _raw_hazard_pre_pre_raw_haz_T_95; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_96 = _raw_hazard_pre_pre_raw_haz_WIRE_41[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_40_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_96; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_97 = _mesh_io_tags_in_progress_10_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_40_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_98 = _mesh_io_tags_in_progress_10_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_40_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz_10 = _raw_hazard_pre_pre_raw_haz_T_97 & _raw_hazard_pre_pre_raw_haz_T_98; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_206; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_205; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_204; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_83; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_202; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_201; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_200; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_200 = _raw_hazard_pre_mul_raw_haz_WIRE_81[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_80_data = _raw_hazard_pre_mul_raw_haz_T_200; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_201 = _raw_hazard_pre_mul_raw_haz_WIRE_81[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_80_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_201; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_202 = _raw_hazard_pre_mul_raw_haz_WIRE_81[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_80_garbage = _raw_hazard_pre_mul_raw_haz_T_202; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_203 = _raw_hazard_pre_mul_raw_haz_WIRE_81[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_82 = _raw_hazard_pre_mul_raw_haz_T_203; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_83 = _raw_hazard_pre_mul_raw_haz_WIRE_82; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_80_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_83; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_204 = _raw_hazard_pre_mul_raw_haz_WIRE_81[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_80_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_204; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_205 = _raw_hazard_pre_mul_raw_haz_WIRE_81[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_80_accumulate = _raw_hazard_pre_mul_raw_haz_T_205; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_206 = _raw_hazard_pre_mul_raw_haz_WIRE_81[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_80_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_206; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_207 = _mesh_io_tags_in_progress_10_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_80_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_208 = _mesh_io_tags_in_progress_10_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_80_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_209 = _raw_hazard_pre_mul_raw_haz_T_207 & _raw_hazard_pre_mul_raw_haz_T_208; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_216; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_215; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_214; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_87; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_212; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_211; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_210; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_210 = _raw_hazard_pre_mul_raw_haz_WIRE_85[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_84_data = _raw_hazard_pre_mul_raw_haz_T_210; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_211 = _raw_hazard_pre_mul_raw_haz_WIRE_85[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_84_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_211; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_212 = _raw_hazard_pre_mul_raw_haz_WIRE_85[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_84_garbage = _raw_hazard_pre_mul_raw_haz_T_212; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_213 = _raw_hazard_pre_mul_raw_haz_WIRE_85[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_86 = _raw_hazard_pre_mul_raw_haz_T_213; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_87 = _raw_hazard_pre_mul_raw_haz_WIRE_86; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_84_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_87; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_214 = _raw_hazard_pre_mul_raw_haz_WIRE_85[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_84_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_214; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_215 = _raw_hazard_pre_mul_raw_haz_WIRE_85[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_84_accumulate = _raw_hazard_pre_mul_raw_haz_T_215; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_216 = _raw_hazard_pre_mul_raw_haz_WIRE_85[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_84_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_216; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_217 = _mesh_io_tags_in_progress_10_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_84_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_218 = _mesh_io_tags_in_progress_10_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_84_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_219 = _raw_hazard_pre_mul_raw_haz_T_217 & _raw_hazard_pre_mul_raw_haz_T_218; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz_10 = _raw_hazard_pre_mul_raw_haz_T_209 | _raw_hazard_pre_mul_raw_haz_T_219; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_50 = ~raw_hazard_pre_is_garbage_10; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_51 = raw_hazard_pre_pre_raw_haz_10 | raw_hazard_pre_mul_raw_haz_10; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_52 = _raw_hazard_pre_T_50 & _raw_hazard_pre_T_51; // @[ExecuteController.scala:217:{5,17,33}]
wire _raw_hazard_pre_T_54 = _raw_hazard_pre_T_52; // @[ExecuteController.scala:217:{17,49}]
wire _GEN_16 = _mesh_io_tags_in_progress_11_addr_is_acc_addr & _mesh_io_tags_in_progress_11_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_55; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T_55 = _GEN_16; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T_55; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T_55 = _GEN_16; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_56 = _raw_hazard_pre_is_garbage_T_55 & _mesh_io_tags_in_progress_11_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_57 = &_mesh_io_tags_in_progress_11_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_58 = _raw_hazard_pre_is_garbage_T_56 & _raw_hazard_pre_is_garbage_T_57; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_59; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage_11 = _raw_hazard_pre_is_garbage_T_58 & _raw_hazard_pre_is_garbage_T_59; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_105; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_104; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_103; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_47; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_101; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_100; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T_99; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_99 = _raw_hazard_pre_pre_raw_haz_WIRE_45[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_44_data = _raw_hazard_pre_pre_raw_haz_T_99; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_100 = _raw_hazard_pre_pre_raw_haz_WIRE_45[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_44_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_100; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_101 = _raw_hazard_pre_pre_raw_haz_WIRE_45[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_44_garbage = _raw_hazard_pre_pre_raw_haz_T_101; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_102 = _raw_hazard_pre_pre_raw_haz_WIRE_45[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_46 = _raw_hazard_pre_pre_raw_haz_T_102; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_47 = _raw_hazard_pre_pre_raw_haz_WIRE_46; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_44_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_47; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_103 = _raw_hazard_pre_pre_raw_haz_WIRE_45[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_44_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_103; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_104 = _raw_hazard_pre_pre_raw_haz_WIRE_45[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_44_accumulate = _raw_hazard_pre_pre_raw_haz_T_104; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_105 = _raw_hazard_pre_pre_raw_haz_WIRE_45[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_44_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_105; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_106 = _mesh_io_tags_in_progress_11_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_44_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_107 = _mesh_io_tags_in_progress_11_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_44_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz_11 = _raw_hazard_pre_pre_raw_haz_T_106 & _raw_hazard_pre_pre_raw_haz_T_107; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_226; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_225; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_224; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_91; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_222; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_221; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_220; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_220 = _raw_hazard_pre_mul_raw_haz_WIRE_89[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_88_data = _raw_hazard_pre_mul_raw_haz_T_220; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_221 = _raw_hazard_pre_mul_raw_haz_WIRE_89[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_88_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_221; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_222 = _raw_hazard_pre_mul_raw_haz_WIRE_89[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_88_garbage = _raw_hazard_pre_mul_raw_haz_T_222; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_223 = _raw_hazard_pre_mul_raw_haz_WIRE_89[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_90 = _raw_hazard_pre_mul_raw_haz_T_223; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_91 = _raw_hazard_pre_mul_raw_haz_WIRE_90; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_88_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_91; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_224 = _raw_hazard_pre_mul_raw_haz_WIRE_89[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_88_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_224; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_225 = _raw_hazard_pre_mul_raw_haz_WIRE_89[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_88_accumulate = _raw_hazard_pre_mul_raw_haz_T_225; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_226 = _raw_hazard_pre_mul_raw_haz_WIRE_89[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_88_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_226; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_227 = _mesh_io_tags_in_progress_11_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_88_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_228 = _mesh_io_tags_in_progress_11_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_88_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_229 = _raw_hazard_pre_mul_raw_haz_T_227 & _raw_hazard_pre_mul_raw_haz_T_228; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_236; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_235; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_234; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_95; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_232; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_231; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_230; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_230 = _raw_hazard_pre_mul_raw_haz_WIRE_93[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_92_data = _raw_hazard_pre_mul_raw_haz_T_230; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_231 = _raw_hazard_pre_mul_raw_haz_WIRE_93[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_92_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_231; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_232 = _raw_hazard_pre_mul_raw_haz_WIRE_93[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_92_garbage = _raw_hazard_pre_mul_raw_haz_T_232; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_233 = _raw_hazard_pre_mul_raw_haz_WIRE_93[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_94 = _raw_hazard_pre_mul_raw_haz_T_233; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_95 = _raw_hazard_pre_mul_raw_haz_WIRE_94; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_92_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_95; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_234 = _raw_hazard_pre_mul_raw_haz_WIRE_93[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_92_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_234; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_235 = _raw_hazard_pre_mul_raw_haz_WIRE_93[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_92_accumulate = _raw_hazard_pre_mul_raw_haz_T_235; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_236 = _raw_hazard_pre_mul_raw_haz_WIRE_93[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_92_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_236; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_237 = _mesh_io_tags_in_progress_11_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_92_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_238 = _mesh_io_tags_in_progress_11_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_92_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_239 = _raw_hazard_pre_mul_raw_haz_T_237 & _raw_hazard_pre_mul_raw_haz_T_238; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz_11 = _raw_hazard_pre_mul_raw_haz_T_229 | _raw_hazard_pre_mul_raw_haz_T_239; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_55 = ~raw_hazard_pre_is_garbage_11; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_56 = raw_hazard_pre_pre_raw_haz_11 | raw_hazard_pre_mul_raw_haz_11; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_57 = _raw_hazard_pre_T_55 & _raw_hazard_pre_T_56; // @[ExecuteController.scala:217:{5,17,33}]
wire _raw_hazard_pre_T_59 = _raw_hazard_pre_T_57; // @[ExecuteController.scala:217:{17,49}]
wire _GEN_17 = _mesh_io_tags_in_progress_12_addr_is_acc_addr & _mesh_io_tags_in_progress_12_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_60; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T_60 = _GEN_17; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T_60; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T_60 = _GEN_17; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_61 = _raw_hazard_pre_is_garbage_T_60 & _mesh_io_tags_in_progress_12_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_62 = &_mesh_io_tags_in_progress_12_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_63 = _raw_hazard_pre_is_garbage_T_61 & _raw_hazard_pre_is_garbage_T_62; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_64; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage_12 = _raw_hazard_pre_is_garbage_T_63 & _raw_hazard_pre_is_garbage_T_64; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_114; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_113; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_112; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_51; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_110; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_109; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T_108; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_108 = _raw_hazard_pre_pre_raw_haz_WIRE_49[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_48_data = _raw_hazard_pre_pre_raw_haz_T_108; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_109 = _raw_hazard_pre_pre_raw_haz_WIRE_49[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_48_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_109; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_110 = _raw_hazard_pre_pre_raw_haz_WIRE_49[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_48_garbage = _raw_hazard_pre_pre_raw_haz_T_110; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_111 = _raw_hazard_pre_pre_raw_haz_WIRE_49[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_50 = _raw_hazard_pre_pre_raw_haz_T_111; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_51 = _raw_hazard_pre_pre_raw_haz_WIRE_50; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_48_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_51; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_112 = _raw_hazard_pre_pre_raw_haz_WIRE_49[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_48_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_112; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_113 = _raw_hazard_pre_pre_raw_haz_WIRE_49[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_48_accumulate = _raw_hazard_pre_pre_raw_haz_T_113; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_114 = _raw_hazard_pre_pre_raw_haz_WIRE_49[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_48_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_114; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_115 = _mesh_io_tags_in_progress_12_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_48_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_116 = _mesh_io_tags_in_progress_12_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_48_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz_12 = _raw_hazard_pre_pre_raw_haz_T_115 & _raw_hazard_pre_pre_raw_haz_T_116; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_246; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_245; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_244; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_99; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_242; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_241; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_240; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_240 = _raw_hazard_pre_mul_raw_haz_WIRE_97[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_96_data = _raw_hazard_pre_mul_raw_haz_T_240; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_241 = _raw_hazard_pre_mul_raw_haz_WIRE_97[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_96_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_241; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_242 = _raw_hazard_pre_mul_raw_haz_WIRE_97[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_96_garbage = _raw_hazard_pre_mul_raw_haz_T_242; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_243 = _raw_hazard_pre_mul_raw_haz_WIRE_97[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_98 = _raw_hazard_pre_mul_raw_haz_T_243; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_99 = _raw_hazard_pre_mul_raw_haz_WIRE_98; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_96_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_99; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_244 = _raw_hazard_pre_mul_raw_haz_WIRE_97[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_96_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_244; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_245 = _raw_hazard_pre_mul_raw_haz_WIRE_97[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_96_accumulate = _raw_hazard_pre_mul_raw_haz_T_245; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_246 = _raw_hazard_pre_mul_raw_haz_WIRE_97[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_96_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_246; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_247 = _mesh_io_tags_in_progress_12_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_96_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_248 = _mesh_io_tags_in_progress_12_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_96_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_249 = _raw_hazard_pre_mul_raw_haz_T_247 & _raw_hazard_pre_mul_raw_haz_T_248; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_256; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_255; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_254; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_103; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_252; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_251; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_250; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_250 = _raw_hazard_pre_mul_raw_haz_WIRE_101[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_100_data = _raw_hazard_pre_mul_raw_haz_T_250; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_251 = _raw_hazard_pre_mul_raw_haz_WIRE_101[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_100_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_251; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_252 = _raw_hazard_pre_mul_raw_haz_WIRE_101[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_100_garbage = _raw_hazard_pre_mul_raw_haz_T_252; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_253 = _raw_hazard_pre_mul_raw_haz_WIRE_101[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_102 = _raw_hazard_pre_mul_raw_haz_T_253; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_103 = _raw_hazard_pre_mul_raw_haz_WIRE_102; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_100_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_103; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_254 = _raw_hazard_pre_mul_raw_haz_WIRE_101[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_100_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_254; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_255 = _raw_hazard_pre_mul_raw_haz_WIRE_101[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_100_accumulate = _raw_hazard_pre_mul_raw_haz_T_255; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_256 = _raw_hazard_pre_mul_raw_haz_WIRE_101[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_100_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_256; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_257 = _mesh_io_tags_in_progress_12_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_100_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_258 = _mesh_io_tags_in_progress_12_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_100_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_259 = _raw_hazard_pre_mul_raw_haz_T_257 & _raw_hazard_pre_mul_raw_haz_T_258; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz_12 = _raw_hazard_pre_mul_raw_haz_T_249 | _raw_hazard_pre_mul_raw_haz_T_259; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_60 = ~raw_hazard_pre_is_garbage_12; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_61 = raw_hazard_pre_pre_raw_haz_12 | raw_hazard_pre_mul_raw_haz_12; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_62 = _raw_hazard_pre_T_60 & _raw_hazard_pre_T_61; // @[ExecuteController.scala:217:{5,17,33}]
wire _raw_hazard_pre_T_64 = _raw_hazard_pre_T_62; // @[ExecuteController.scala:217:{17,49}]
wire _GEN_18 = _mesh_io_tags_in_progress_13_addr_is_acc_addr & _mesh_io_tags_in_progress_13_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_65; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T_65 = _GEN_18; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T_65; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T_65 = _GEN_18; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_66 = _raw_hazard_pre_is_garbage_T_65 & _mesh_io_tags_in_progress_13_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_67 = &_mesh_io_tags_in_progress_13_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_68 = _raw_hazard_pre_is_garbage_T_66 & _raw_hazard_pre_is_garbage_T_67; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_69; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage_13 = _raw_hazard_pre_is_garbage_T_68 & _raw_hazard_pre_is_garbage_T_69; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_123; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_122; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_121; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_55; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_119; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_118; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T_117; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_117 = _raw_hazard_pre_pre_raw_haz_WIRE_53[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_52_data = _raw_hazard_pre_pre_raw_haz_T_117; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_118 = _raw_hazard_pre_pre_raw_haz_WIRE_53[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_52_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_118; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_119 = _raw_hazard_pre_pre_raw_haz_WIRE_53[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_52_garbage = _raw_hazard_pre_pre_raw_haz_T_119; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_120 = _raw_hazard_pre_pre_raw_haz_WIRE_53[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_54 = _raw_hazard_pre_pre_raw_haz_T_120; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_55 = _raw_hazard_pre_pre_raw_haz_WIRE_54; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_52_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_55; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_121 = _raw_hazard_pre_pre_raw_haz_WIRE_53[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_52_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_121; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_122 = _raw_hazard_pre_pre_raw_haz_WIRE_53[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_52_accumulate = _raw_hazard_pre_pre_raw_haz_T_122; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_123 = _raw_hazard_pre_pre_raw_haz_WIRE_53[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_52_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_123; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_124 = _mesh_io_tags_in_progress_13_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_52_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_125 = _mesh_io_tags_in_progress_13_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_52_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz_13 = _raw_hazard_pre_pre_raw_haz_T_124 & _raw_hazard_pre_pre_raw_haz_T_125; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_266; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_265; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_264; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_107; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_262; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_261; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_260; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_260 = _raw_hazard_pre_mul_raw_haz_WIRE_105[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_104_data = _raw_hazard_pre_mul_raw_haz_T_260; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_261 = _raw_hazard_pre_mul_raw_haz_WIRE_105[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_104_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_261; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_262 = _raw_hazard_pre_mul_raw_haz_WIRE_105[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_104_garbage = _raw_hazard_pre_mul_raw_haz_T_262; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_263 = _raw_hazard_pre_mul_raw_haz_WIRE_105[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_106 = _raw_hazard_pre_mul_raw_haz_T_263; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_107 = _raw_hazard_pre_mul_raw_haz_WIRE_106; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_104_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_107; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_264 = _raw_hazard_pre_mul_raw_haz_WIRE_105[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_104_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_264; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_265 = _raw_hazard_pre_mul_raw_haz_WIRE_105[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_104_accumulate = _raw_hazard_pre_mul_raw_haz_T_265; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_266 = _raw_hazard_pre_mul_raw_haz_WIRE_105[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_104_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_266; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_267 = _mesh_io_tags_in_progress_13_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_104_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_268 = _mesh_io_tags_in_progress_13_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_104_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_269 = _raw_hazard_pre_mul_raw_haz_T_267 & _raw_hazard_pre_mul_raw_haz_T_268; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_276; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_275; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_274; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_111; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_272; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_271; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_270; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_270 = _raw_hazard_pre_mul_raw_haz_WIRE_109[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_108_data = _raw_hazard_pre_mul_raw_haz_T_270; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_271 = _raw_hazard_pre_mul_raw_haz_WIRE_109[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_108_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_271; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_272 = _raw_hazard_pre_mul_raw_haz_WIRE_109[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_108_garbage = _raw_hazard_pre_mul_raw_haz_T_272; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_273 = _raw_hazard_pre_mul_raw_haz_WIRE_109[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_110 = _raw_hazard_pre_mul_raw_haz_T_273; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_111 = _raw_hazard_pre_mul_raw_haz_WIRE_110; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_108_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_111; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_274 = _raw_hazard_pre_mul_raw_haz_WIRE_109[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_108_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_274; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_275 = _raw_hazard_pre_mul_raw_haz_WIRE_109[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_108_accumulate = _raw_hazard_pre_mul_raw_haz_T_275; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_276 = _raw_hazard_pre_mul_raw_haz_WIRE_109[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_108_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_276; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_277 = _mesh_io_tags_in_progress_13_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_108_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_278 = _mesh_io_tags_in_progress_13_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_108_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_279 = _raw_hazard_pre_mul_raw_haz_T_277 & _raw_hazard_pre_mul_raw_haz_T_278; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz_13 = _raw_hazard_pre_mul_raw_haz_T_269 | _raw_hazard_pre_mul_raw_haz_T_279; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_65 = ~raw_hazard_pre_is_garbage_13; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_66 = raw_hazard_pre_pre_raw_haz_13 | raw_hazard_pre_mul_raw_haz_13; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_67 = _raw_hazard_pre_T_65 & _raw_hazard_pre_T_66; // @[ExecuteController.scala:217:{5,17,33}]
wire _raw_hazard_pre_T_69 = _raw_hazard_pre_T_67; // @[ExecuteController.scala:217:{17,49}]
wire _GEN_19 = _mesh_io_tags_in_progress_14_addr_is_acc_addr & _mesh_io_tags_in_progress_14_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_70; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T_70 = _GEN_19; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T_70; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T_70 = _GEN_19; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_71 = _raw_hazard_pre_is_garbage_T_70 & _mesh_io_tags_in_progress_14_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_72 = &_mesh_io_tags_in_progress_14_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_73 = _raw_hazard_pre_is_garbage_T_71 & _raw_hazard_pre_is_garbage_T_72; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_74; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage_14 = _raw_hazard_pre_is_garbage_T_73 & _raw_hazard_pre_is_garbage_T_74; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_132; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_131; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_130; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_59; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_128; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_127; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T_126; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_126 = _raw_hazard_pre_pre_raw_haz_WIRE_57[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_56_data = _raw_hazard_pre_pre_raw_haz_T_126; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_127 = _raw_hazard_pre_pre_raw_haz_WIRE_57[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_56_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_127; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_128 = _raw_hazard_pre_pre_raw_haz_WIRE_57[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_56_garbage = _raw_hazard_pre_pre_raw_haz_T_128; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_129 = _raw_hazard_pre_pre_raw_haz_WIRE_57[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_58 = _raw_hazard_pre_pre_raw_haz_T_129; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_59 = _raw_hazard_pre_pre_raw_haz_WIRE_58; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_56_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_59; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_130 = _raw_hazard_pre_pre_raw_haz_WIRE_57[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_56_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_130; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_131 = _raw_hazard_pre_pre_raw_haz_WIRE_57[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_56_accumulate = _raw_hazard_pre_pre_raw_haz_T_131; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_132 = _raw_hazard_pre_pre_raw_haz_WIRE_57[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_56_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_132; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_133 = _mesh_io_tags_in_progress_14_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_56_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_134 = _mesh_io_tags_in_progress_14_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_56_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz_14 = _raw_hazard_pre_pre_raw_haz_T_133 & _raw_hazard_pre_pre_raw_haz_T_134; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_286; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_285; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_284; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_115; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_282; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_281; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_280; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_280 = _raw_hazard_pre_mul_raw_haz_WIRE_113[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_112_data = _raw_hazard_pre_mul_raw_haz_T_280; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_281 = _raw_hazard_pre_mul_raw_haz_WIRE_113[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_112_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_281; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_282 = _raw_hazard_pre_mul_raw_haz_WIRE_113[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_112_garbage = _raw_hazard_pre_mul_raw_haz_T_282; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_283 = _raw_hazard_pre_mul_raw_haz_WIRE_113[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_114 = _raw_hazard_pre_mul_raw_haz_T_283; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_115 = _raw_hazard_pre_mul_raw_haz_WIRE_114; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_112_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_115; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_284 = _raw_hazard_pre_mul_raw_haz_WIRE_113[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_112_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_284; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_285 = _raw_hazard_pre_mul_raw_haz_WIRE_113[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_112_accumulate = _raw_hazard_pre_mul_raw_haz_T_285; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_286 = _raw_hazard_pre_mul_raw_haz_WIRE_113[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_112_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_286; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_287 = _mesh_io_tags_in_progress_14_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_112_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_288 = _mesh_io_tags_in_progress_14_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_112_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_289 = _raw_hazard_pre_mul_raw_haz_T_287 & _raw_hazard_pre_mul_raw_haz_T_288; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_296; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_295; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_294; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_119; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_292; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_291; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_290; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_290 = _raw_hazard_pre_mul_raw_haz_WIRE_117[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_116_data = _raw_hazard_pre_mul_raw_haz_T_290; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_291 = _raw_hazard_pre_mul_raw_haz_WIRE_117[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_116_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_291; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_292 = _raw_hazard_pre_mul_raw_haz_WIRE_117[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_116_garbage = _raw_hazard_pre_mul_raw_haz_T_292; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_293 = _raw_hazard_pre_mul_raw_haz_WIRE_117[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_118 = _raw_hazard_pre_mul_raw_haz_T_293; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_119 = _raw_hazard_pre_mul_raw_haz_WIRE_118; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_116_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_119; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_294 = _raw_hazard_pre_mul_raw_haz_WIRE_117[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_116_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_294; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_295 = _raw_hazard_pre_mul_raw_haz_WIRE_117[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_116_accumulate = _raw_hazard_pre_mul_raw_haz_T_295; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_296 = _raw_hazard_pre_mul_raw_haz_WIRE_117[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_116_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_296; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_297 = _mesh_io_tags_in_progress_14_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_116_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_298 = _mesh_io_tags_in_progress_14_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_116_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_299 = _raw_hazard_pre_mul_raw_haz_T_297 & _raw_hazard_pre_mul_raw_haz_T_298; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz_14 = _raw_hazard_pre_mul_raw_haz_T_289 | _raw_hazard_pre_mul_raw_haz_T_299; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_70 = ~raw_hazard_pre_is_garbage_14; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_71 = raw_hazard_pre_pre_raw_haz_14 | raw_hazard_pre_mul_raw_haz_14; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_72 = _raw_hazard_pre_T_70 & _raw_hazard_pre_T_71; // @[ExecuteController.scala:217:{5,17,33}]
wire _raw_hazard_pre_T_74 = _raw_hazard_pre_T_72; // @[ExecuteController.scala:217:{17,49}]
wire _GEN_20 = _mesh_io_tags_in_progress_15_addr_is_acc_addr & _mesh_io_tags_in_progress_15_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_75; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T_75 = _GEN_20; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T_75; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T_75 = _GEN_20; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_76 = _raw_hazard_pre_is_garbage_T_75 & _mesh_io_tags_in_progress_15_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_77 = &_mesh_io_tags_in_progress_15_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_78 = _raw_hazard_pre_is_garbage_T_76 & _raw_hazard_pre_is_garbage_T_77; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_79; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage_15 = _raw_hazard_pre_is_garbage_T_78 & _raw_hazard_pre_is_garbage_T_79; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_141; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_140; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_139; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_63; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_137; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_136; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T_135; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_135 = _raw_hazard_pre_pre_raw_haz_WIRE_61[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_60_data = _raw_hazard_pre_pre_raw_haz_T_135; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_136 = _raw_hazard_pre_pre_raw_haz_WIRE_61[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_60_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_136; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_137 = _raw_hazard_pre_pre_raw_haz_WIRE_61[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_60_garbage = _raw_hazard_pre_pre_raw_haz_T_137; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_138 = _raw_hazard_pre_pre_raw_haz_WIRE_61[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_62 = _raw_hazard_pre_pre_raw_haz_T_138; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_63 = _raw_hazard_pre_pre_raw_haz_WIRE_62; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_60_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_63; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_139 = _raw_hazard_pre_pre_raw_haz_WIRE_61[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_60_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_139; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_140 = _raw_hazard_pre_pre_raw_haz_WIRE_61[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_60_accumulate = _raw_hazard_pre_pre_raw_haz_T_140; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_141 = _raw_hazard_pre_pre_raw_haz_WIRE_61[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_60_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_141; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_142 = _mesh_io_tags_in_progress_15_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_60_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_143 = _mesh_io_tags_in_progress_15_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_60_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz_15 = _raw_hazard_pre_pre_raw_haz_T_142 & _raw_hazard_pre_pre_raw_haz_T_143; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_306; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_305; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_304; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_123; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_302; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_301; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_300; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_300 = _raw_hazard_pre_mul_raw_haz_WIRE_121[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_120_data = _raw_hazard_pre_mul_raw_haz_T_300; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_301 = _raw_hazard_pre_mul_raw_haz_WIRE_121[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_120_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_301; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_302 = _raw_hazard_pre_mul_raw_haz_WIRE_121[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_120_garbage = _raw_hazard_pre_mul_raw_haz_T_302; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_303 = _raw_hazard_pre_mul_raw_haz_WIRE_121[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_122 = _raw_hazard_pre_mul_raw_haz_T_303; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_123 = _raw_hazard_pre_mul_raw_haz_WIRE_122; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_120_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_123; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_304 = _raw_hazard_pre_mul_raw_haz_WIRE_121[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_120_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_304; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_305 = _raw_hazard_pre_mul_raw_haz_WIRE_121[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_120_accumulate = _raw_hazard_pre_mul_raw_haz_T_305; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_306 = _raw_hazard_pre_mul_raw_haz_WIRE_121[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_120_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_306; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_307 = _mesh_io_tags_in_progress_15_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_120_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_308 = _mesh_io_tags_in_progress_15_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_120_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_309 = _raw_hazard_pre_mul_raw_haz_T_307 & _raw_hazard_pre_mul_raw_haz_T_308; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_316; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_315; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_314; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_127; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_312; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_311; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_310; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_310 = _raw_hazard_pre_mul_raw_haz_WIRE_125[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_124_data = _raw_hazard_pre_mul_raw_haz_T_310; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_311 = _raw_hazard_pre_mul_raw_haz_WIRE_125[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_124_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_311; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_312 = _raw_hazard_pre_mul_raw_haz_WIRE_125[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_124_garbage = _raw_hazard_pre_mul_raw_haz_T_312; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_313 = _raw_hazard_pre_mul_raw_haz_WIRE_125[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_126 = _raw_hazard_pre_mul_raw_haz_T_313; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_127 = _raw_hazard_pre_mul_raw_haz_WIRE_126; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_124_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_127; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_314 = _raw_hazard_pre_mul_raw_haz_WIRE_125[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_124_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_314; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_315 = _raw_hazard_pre_mul_raw_haz_WIRE_125[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_124_accumulate = _raw_hazard_pre_mul_raw_haz_T_315; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_316 = _raw_hazard_pre_mul_raw_haz_WIRE_125[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_124_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_316; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_317 = _mesh_io_tags_in_progress_15_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_124_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_318 = _mesh_io_tags_in_progress_15_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_124_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_319 = _raw_hazard_pre_mul_raw_haz_T_317 & _raw_hazard_pre_mul_raw_haz_T_318; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz_15 = _raw_hazard_pre_mul_raw_haz_T_309 | _raw_hazard_pre_mul_raw_haz_T_319; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_75 = ~raw_hazard_pre_is_garbage_15; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_76 = raw_hazard_pre_pre_raw_haz_15 | raw_hazard_pre_mul_raw_haz_15; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_77 = _raw_hazard_pre_T_75 & _raw_hazard_pre_T_76; // @[ExecuteController.scala:217:{5,17,33}]
wire _raw_hazard_pre_T_79 = _raw_hazard_pre_T_77; // @[ExecuteController.scala:217:{17,49}]
wire _raw_hazard_pre_T_80 = _raw_hazard_pre_T_4 | _raw_hazard_pre_T_9; // @[ExecuteController.scala:217:49, :218:14]
wire _raw_hazard_pre_T_81 = _raw_hazard_pre_T_80 | _raw_hazard_pre_T_14; // @[ExecuteController.scala:217:49, :218:14]
wire _raw_hazard_pre_T_82 = _raw_hazard_pre_T_81 | _raw_hazard_pre_T_19; // @[ExecuteController.scala:217:49, :218:14]
wire _raw_hazard_pre_T_83 = _raw_hazard_pre_T_82 | _raw_hazard_pre_T_24; // @[ExecuteController.scala:217:49, :218:14]
wire _raw_hazard_pre_T_84 = _raw_hazard_pre_T_83 | _raw_hazard_pre_T_29; // @[ExecuteController.scala:217:49, :218:14]
wire _raw_hazard_pre_T_85 = _raw_hazard_pre_T_84 | _raw_hazard_pre_T_34; // @[ExecuteController.scala:217:49, :218:14]
wire _raw_hazard_pre_T_86 = _raw_hazard_pre_T_85 | _raw_hazard_pre_T_39; // @[ExecuteController.scala:217:49, :218:14]
wire _raw_hazard_pre_T_87 = _raw_hazard_pre_T_86 | _raw_hazard_pre_T_44; // @[ExecuteController.scala:217:49, :218:14]
wire _raw_hazard_pre_T_88 = _raw_hazard_pre_T_87 | _raw_hazard_pre_T_49; // @[ExecuteController.scala:217:49, :218:14]
wire _raw_hazard_pre_T_89 = _raw_hazard_pre_T_88 | _raw_hazard_pre_T_54; // @[ExecuteController.scala:217:49, :218:14]
wire _raw_hazard_pre_T_90 = _raw_hazard_pre_T_89 | _raw_hazard_pre_T_59; // @[ExecuteController.scala:217:49, :218:14]
wire _raw_hazard_pre_T_91 = _raw_hazard_pre_T_90 | _raw_hazard_pre_T_64; // @[ExecuteController.scala:217:49, :218:14]
wire _raw_hazard_pre_T_92 = _raw_hazard_pre_T_91 | _raw_hazard_pre_T_69; // @[ExecuteController.scala:217:49, :218:14]
wire _raw_hazard_pre_T_93 = _raw_hazard_pre_T_92 | _raw_hazard_pre_T_74; // @[ExecuteController.scala:217:49, :218:14]
wire raw_hazard_pre = _raw_hazard_pre_T_93 | _raw_hazard_pre_T_79; // @[ExecuteController.scala:217:49, :218:14]
wire _raw_hazard_mulpre_is_garbage_T_1 = _raw_hazard_mulpre_is_garbage_T & _mesh_io_tags_in_progress_0_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_2 = &_mesh_io_tags_in_progress_0_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_3 = _raw_hazard_mulpre_is_garbage_T_1 & _raw_hazard_mulpre_is_garbage_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_4; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage = _raw_hazard_mulpre_is_garbage_T_3 & _raw_hazard_mulpre_is_garbage_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_6; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_5; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_4; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_3; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_2; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_1; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T = _raw_hazard_mulpre_pre_raw_haz_WIRE_1[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_data = _raw_hazard_mulpre_pre_raw_haz_T; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_1 = _raw_hazard_mulpre_pre_raw_haz_WIRE_1[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_1; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_2 = _raw_hazard_mulpre_pre_raw_haz_WIRE_1[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_garbage = _raw_hazard_mulpre_pre_raw_haz_T_2; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_3 = _raw_hazard_mulpre_pre_raw_haz_WIRE_1[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_2 = _raw_hazard_mulpre_pre_raw_haz_T_3; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_3 = _raw_hazard_mulpre_pre_raw_haz_WIRE_2; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_3; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_4 = _raw_hazard_mulpre_pre_raw_haz_WIRE_1[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_4; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_5 = _raw_hazard_mulpre_pre_raw_haz_WIRE_1[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_5; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_6 = _raw_hazard_mulpre_pre_raw_haz_WIRE_1[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_6; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_7 = _mesh_io_tags_in_progress_0_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_8 = _mesh_io_tags_in_progress_0_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz = _raw_hazard_mulpre_pre_raw_haz_T_7 & _raw_hazard_mulpre_pre_raw_haz_T_8; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_6; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_5; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_4; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_3; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_2; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_1; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_1 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_9 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_17 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_25 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_33 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_41 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_49 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_57 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_65 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_73 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_81 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_89 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_97 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_105 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_113 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_121 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T = _raw_hazard_mulpre_mul_raw_haz_WIRE_1[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_data = _raw_hazard_mulpre_mul_raw_haz_T; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_1 = _raw_hazard_mulpre_mul_raw_haz_WIRE_1[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_1; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_2 = _raw_hazard_mulpre_mul_raw_haz_WIRE_1[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_garbage = _raw_hazard_mulpre_mul_raw_haz_T_2; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_3 = _raw_hazard_mulpre_mul_raw_haz_WIRE_1[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_2 = _raw_hazard_mulpre_mul_raw_haz_T_3; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_3 = _raw_hazard_mulpre_mul_raw_haz_WIRE_2; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_3; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_4 = _raw_hazard_mulpre_mul_raw_haz_WIRE_1[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_4; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_5 = _raw_hazard_mulpre_mul_raw_haz_WIRE_1[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_5; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_6 = _raw_hazard_mulpre_mul_raw_haz_WIRE_1[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_6; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_7 = _mesh_io_tags_in_progress_0_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_8 = _mesh_io_tags_in_progress_0_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_9 = _raw_hazard_mulpre_mul_raw_haz_T_7 & _raw_hazard_mulpre_mul_raw_haz_T_8; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_16; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_15; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_14; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_7; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_12; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_11; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_10; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_5 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_13 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_21 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_29 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_37 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_45 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_53 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_61 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_69 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_77 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_85 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_93 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_101 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_109 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_117 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_125 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_10 = _raw_hazard_mulpre_mul_raw_haz_WIRE_5[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_4_data = _raw_hazard_mulpre_mul_raw_haz_T_10; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_11 = _raw_hazard_mulpre_mul_raw_haz_WIRE_5[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_4_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_11; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_12 = _raw_hazard_mulpre_mul_raw_haz_WIRE_5[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_4_garbage = _raw_hazard_mulpre_mul_raw_haz_T_12; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_13 = _raw_hazard_mulpre_mul_raw_haz_WIRE_5[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_6 = _raw_hazard_mulpre_mul_raw_haz_T_13; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_7 = _raw_hazard_mulpre_mul_raw_haz_WIRE_6; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_4_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_7; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_14 = _raw_hazard_mulpre_mul_raw_haz_WIRE_5[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_4_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_14; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_15 = _raw_hazard_mulpre_mul_raw_haz_WIRE_5[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_4_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_15; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_16 = _raw_hazard_mulpre_mul_raw_haz_WIRE_5[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_4_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_16; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_17 = _mesh_io_tags_in_progress_0_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_4_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_18 = _mesh_io_tags_in_progress_0_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_4_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_19 = _raw_hazard_mulpre_mul_raw_haz_T_17 & _raw_hazard_mulpre_mul_raw_haz_T_18; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz = _raw_hazard_mulpre_mul_raw_haz_T_9 | _raw_hazard_mulpre_mul_raw_haz_T_19; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T = ~raw_hazard_mulpre_is_garbage; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_1 = raw_hazard_mulpre_mul_raw_haz | raw_hazard_mulpre_pre_raw_haz; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_2 = _raw_hazard_mulpre_T & _raw_hazard_mulpre_T_1; // @[ExecuteController.scala:225:{5,17,33}]
wire _raw_hazard_mulpre_T_4 = _raw_hazard_mulpre_T_2; // @[ExecuteController.scala:225:{17,49}]
wire _raw_hazard_mulpre_is_garbage_T_6 = _raw_hazard_mulpre_is_garbage_T_5 & _mesh_io_tags_in_progress_1_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_7 = &_mesh_io_tags_in_progress_1_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_8 = _raw_hazard_mulpre_is_garbage_T_6 & _raw_hazard_mulpre_is_garbage_T_7; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_9; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage_1 = _raw_hazard_mulpre_is_garbage_T_8 & _raw_hazard_mulpre_is_garbage_T_9; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_15; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_14; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_13; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_7; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_11; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_10; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T_9; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_9 = _raw_hazard_mulpre_pre_raw_haz_WIRE_5[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_4_data = _raw_hazard_mulpre_pre_raw_haz_T_9; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_10 = _raw_hazard_mulpre_pre_raw_haz_WIRE_5[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_4_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_10; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_11 = _raw_hazard_mulpre_pre_raw_haz_WIRE_5[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_4_garbage = _raw_hazard_mulpre_pre_raw_haz_T_11; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_12 = _raw_hazard_mulpre_pre_raw_haz_WIRE_5[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_6 = _raw_hazard_mulpre_pre_raw_haz_T_12; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_7 = _raw_hazard_mulpre_pre_raw_haz_WIRE_6; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_4_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_7; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_13 = _raw_hazard_mulpre_pre_raw_haz_WIRE_5[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_4_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_13; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_14 = _raw_hazard_mulpre_pre_raw_haz_WIRE_5[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_4_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_14; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_15 = _raw_hazard_mulpre_pre_raw_haz_WIRE_5[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_4_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_15; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_16 = _mesh_io_tags_in_progress_1_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_4_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_17 = _mesh_io_tags_in_progress_1_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_4_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz_1 = _raw_hazard_mulpre_pre_raw_haz_T_16 & _raw_hazard_mulpre_pre_raw_haz_T_17; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_26; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_25; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_24; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_11; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_22; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_21; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_20; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_20 = _raw_hazard_mulpre_mul_raw_haz_WIRE_9[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_8_data = _raw_hazard_mulpre_mul_raw_haz_T_20; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_21 = _raw_hazard_mulpre_mul_raw_haz_WIRE_9[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_8_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_21; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_22 = _raw_hazard_mulpre_mul_raw_haz_WIRE_9[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_8_garbage = _raw_hazard_mulpre_mul_raw_haz_T_22; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_23 = _raw_hazard_mulpre_mul_raw_haz_WIRE_9[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_10 = _raw_hazard_mulpre_mul_raw_haz_T_23; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_11 = _raw_hazard_mulpre_mul_raw_haz_WIRE_10; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_8_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_11; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_24 = _raw_hazard_mulpre_mul_raw_haz_WIRE_9[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_8_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_24; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_25 = _raw_hazard_mulpre_mul_raw_haz_WIRE_9[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_8_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_25; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_26 = _raw_hazard_mulpre_mul_raw_haz_WIRE_9[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_8_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_26; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_27 = _mesh_io_tags_in_progress_1_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_8_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_28 = _mesh_io_tags_in_progress_1_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_8_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_29 = _raw_hazard_mulpre_mul_raw_haz_T_27 & _raw_hazard_mulpre_mul_raw_haz_T_28; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_36; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_35; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_34; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_15; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_32; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_31; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_30; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_30 = _raw_hazard_mulpre_mul_raw_haz_WIRE_13[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_12_data = _raw_hazard_mulpre_mul_raw_haz_T_30; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_31 = _raw_hazard_mulpre_mul_raw_haz_WIRE_13[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_12_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_31; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_32 = _raw_hazard_mulpre_mul_raw_haz_WIRE_13[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_12_garbage = _raw_hazard_mulpre_mul_raw_haz_T_32; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_33 = _raw_hazard_mulpre_mul_raw_haz_WIRE_13[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_14 = _raw_hazard_mulpre_mul_raw_haz_T_33; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_15 = _raw_hazard_mulpre_mul_raw_haz_WIRE_14; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_12_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_15; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_34 = _raw_hazard_mulpre_mul_raw_haz_WIRE_13[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_12_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_34; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_35 = _raw_hazard_mulpre_mul_raw_haz_WIRE_13[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_12_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_35; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_36 = _raw_hazard_mulpre_mul_raw_haz_WIRE_13[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_12_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_36; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_37 = _mesh_io_tags_in_progress_1_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_12_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_38 = _mesh_io_tags_in_progress_1_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_12_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_39 = _raw_hazard_mulpre_mul_raw_haz_T_37 & _raw_hazard_mulpre_mul_raw_haz_T_38; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz_1 = _raw_hazard_mulpre_mul_raw_haz_T_29 | _raw_hazard_mulpre_mul_raw_haz_T_39; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_5 = ~raw_hazard_mulpre_is_garbage_1; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_6 = raw_hazard_mulpre_mul_raw_haz_1 | raw_hazard_mulpre_pre_raw_haz_1; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_7 = _raw_hazard_mulpre_T_5 & _raw_hazard_mulpre_T_6; // @[ExecuteController.scala:225:{5,17,33}]
wire _raw_hazard_mulpre_T_9 = _raw_hazard_mulpre_T_7; // @[ExecuteController.scala:225:{17,49}]
wire _raw_hazard_mulpre_is_garbage_T_11 = _raw_hazard_mulpre_is_garbage_T_10 & _mesh_io_tags_in_progress_2_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_12 = &_mesh_io_tags_in_progress_2_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_13 = _raw_hazard_mulpre_is_garbage_T_11 & _raw_hazard_mulpre_is_garbage_T_12; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_14; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage_2 = _raw_hazard_mulpre_is_garbage_T_13 & _raw_hazard_mulpre_is_garbage_T_14; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_24; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_23; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_22; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_11; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_20; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_19; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T_18; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_18 = _raw_hazard_mulpre_pre_raw_haz_WIRE_9[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_8_data = _raw_hazard_mulpre_pre_raw_haz_T_18; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_19 = _raw_hazard_mulpre_pre_raw_haz_WIRE_9[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_8_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_19; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_20 = _raw_hazard_mulpre_pre_raw_haz_WIRE_9[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_8_garbage = _raw_hazard_mulpre_pre_raw_haz_T_20; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_21 = _raw_hazard_mulpre_pre_raw_haz_WIRE_9[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_10 = _raw_hazard_mulpre_pre_raw_haz_T_21; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_11 = _raw_hazard_mulpre_pre_raw_haz_WIRE_10; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_8_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_11; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_22 = _raw_hazard_mulpre_pre_raw_haz_WIRE_9[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_8_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_22; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_23 = _raw_hazard_mulpre_pre_raw_haz_WIRE_9[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_8_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_23; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_24 = _raw_hazard_mulpre_pre_raw_haz_WIRE_9[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_8_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_24; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_25 = _mesh_io_tags_in_progress_2_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_8_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_26 = _mesh_io_tags_in_progress_2_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_8_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz_2 = _raw_hazard_mulpre_pre_raw_haz_T_25 & _raw_hazard_mulpre_pre_raw_haz_T_26; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_46; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_45; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_44; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_19; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_42; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_41; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_40; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_40 = _raw_hazard_mulpre_mul_raw_haz_WIRE_17[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_16_data = _raw_hazard_mulpre_mul_raw_haz_T_40; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_41 = _raw_hazard_mulpre_mul_raw_haz_WIRE_17[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_16_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_41; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_42 = _raw_hazard_mulpre_mul_raw_haz_WIRE_17[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_16_garbage = _raw_hazard_mulpre_mul_raw_haz_T_42; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_43 = _raw_hazard_mulpre_mul_raw_haz_WIRE_17[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_18 = _raw_hazard_mulpre_mul_raw_haz_T_43; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_19 = _raw_hazard_mulpre_mul_raw_haz_WIRE_18; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_16_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_19; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_44 = _raw_hazard_mulpre_mul_raw_haz_WIRE_17[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_16_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_44; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_45 = _raw_hazard_mulpre_mul_raw_haz_WIRE_17[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_16_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_45; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_46 = _raw_hazard_mulpre_mul_raw_haz_WIRE_17[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_16_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_46; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_47 = _mesh_io_tags_in_progress_2_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_16_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_48 = _mesh_io_tags_in_progress_2_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_16_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_49 = _raw_hazard_mulpre_mul_raw_haz_T_47 & _raw_hazard_mulpre_mul_raw_haz_T_48; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_56; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_55; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_54; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_23; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_52; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_51; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_50; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_50 = _raw_hazard_mulpre_mul_raw_haz_WIRE_21[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_20_data = _raw_hazard_mulpre_mul_raw_haz_T_50; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_51 = _raw_hazard_mulpre_mul_raw_haz_WIRE_21[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_20_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_51; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_52 = _raw_hazard_mulpre_mul_raw_haz_WIRE_21[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_20_garbage = _raw_hazard_mulpre_mul_raw_haz_T_52; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_53 = _raw_hazard_mulpre_mul_raw_haz_WIRE_21[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_22 = _raw_hazard_mulpre_mul_raw_haz_T_53; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_23 = _raw_hazard_mulpre_mul_raw_haz_WIRE_22; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_20_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_23; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_54 = _raw_hazard_mulpre_mul_raw_haz_WIRE_21[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_20_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_54; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_55 = _raw_hazard_mulpre_mul_raw_haz_WIRE_21[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_20_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_55; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_56 = _raw_hazard_mulpre_mul_raw_haz_WIRE_21[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_20_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_56; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_57 = _mesh_io_tags_in_progress_2_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_20_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_58 = _mesh_io_tags_in_progress_2_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_20_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_59 = _raw_hazard_mulpre_mul_raw_haz_T_57 & _raw_hazard_mulpre_mul_raw_haz_T_58; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz_2 = _raw_hazard_mulpre_mul_raw_haz_T_49 | _raw_hazard_mulpre_mul_raw_haz_T_59; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_10 = ~raw_hazard_mulpre_is_garbage_2; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_11 = raw_hazard_mulpre_mul_raw_haz_2 | raw_hazard_mulpre_pre_raw_haz_2; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_12 = _raw_hazard_mulpre_T_10 & _raw_hazard_mulpre_T_11; // @[ExecuteController.scala:225:{5,17,33}]
wire _raw_hazard_mulpre_T_14 = _raw_hazard_mulpre_T_12; // @[ExecuteController.scala:225:{17,49}]
wire _raw_hazard_mulpre_is_garbage_T_16 = _raw_hazard_mulpre_is_garbage_T_15 & _mesh_io_tags_in_progress_3_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_17 = &_mesh_io_tags_in_progress_3_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_18 = _raw_hazard_mulpre_is_garbage_T_16 & _raw_hazard_mulpre_is_garbage_T_17; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_19; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage_3 = _raw_hazard_mulpre_is_garbage_T_18 & _raw_hazard_mulpre_is_garbage_T_19; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_33; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_32; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_31; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_15; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_29; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_28; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T_27; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_27 = _raw_hazard_mulpre_pre_raw_haz_WIRE_13[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_12_data = _raw_hazard_mulpre_pre_raw_haz_T_27; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_28 = _raw_hazard_mulpre_pre_raw_haz_WIRE_13[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_12_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_28; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_29 = _raw_hazard_mulpre_pre_raw_haz_WIRE_13[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_12_garbage = _raw_hazard_mulpre_pre_raw_haz_T_29; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_30 = _raw_hazard_mulpre_pre_raw_haz_WIRE_13[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_14 = _raw_hazard_mulpre_pre_raw_haz_T_30; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_15 = _raw_hazard_mulpre_pre_raw_haz_WIRE_14; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_12_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_15; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_31 = _raw_hazard_mulpre_pre_raw_haz_WIRE_13[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_12_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_31; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_32 = _raw_hazard_mulpre_pre_raw_haz_WIRE_13[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_12_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_32; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_33 = _raw_hazard_mulpre_pre_raw_haz_WIRE_13[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_12_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_33; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_34 = _mesh_io_tags_in_progress_3_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_12_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_35 = _mesh_io_tags_in_progress_3_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_12_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz_3 = _raw_hazard_mulpre_pre_raw_haz_T_34 & _raw_hazard_mulpre_pre_raw_haz_T_35; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_66; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_65; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_64; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_27; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_62; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_61; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_60; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_60 = _raw_hazard_mulpre_mul_raw_haz_WIRE_25[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_24_data = _raw_hazard_mulpre_mul_raw_haz_T_60; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_61 = _raw_hazard_mulpre_mul_raw_haz_WIRE_25[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_24_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_61; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_62 = _raw_hazard_mulpre_mul_raw_haz_WIRE_25[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_24_garbage = _raw_hazard_mulpre_mul_raw_haz_T_62; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_63 = _raw_hazard_mulpre_mul_raw_haz_WIRE_25[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_26 = _raw_hazard_mulpre_mul_raw_haz_T_63; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_27 = _raw_hazard_mulpre_mul_raw_haz_WIRE_26; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_24_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_27; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_64 = _raw_hazard_mulpre_mul_raw_haz_WIRE_25[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_24_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_64; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_65 = _raw_hazard_mulpre_mul_raw_haz_WIRE_25[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_24_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_65; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_66 = _raw_hazard_mulpre_mul_raw_haz_WIRE_25[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_24_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_66; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_67 = _mesh_io_tags_in_progress_3_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_24_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_68 = _mesh_io_tags_in_progress_3_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_24_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_69 = _raw_hazard_mulpre_mul_raw_haz_T_67 & _raw_hazard_mulpre_mul_raw_haz_T_68; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_76; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_75; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_74; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_31; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_72; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_71; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_70; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_70 = _raw_hazard_mulpre_mul_raw_haz_WIRE_29[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_28_data = _raw_hazard_mulpre_mul_raw_haz_T_70; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_71 = _raw_hazard_mulpre_mul_raw_haz_WIRE_29[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_28_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_71; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_72 = _raw_hazard_mulpre_mul_raw_haz_WIRE_29[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_28_garbage = _raw_hazard_mulpre_mul_raw_haz_T_72; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_73 = _raw_hazard_mulpre_mul_raw_haz_WIRE_29[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_30 = _raw_hazard_mulpre_mul_raw_haz_T_73; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_31 = _raw_hazard_mulpre_mul_raw_haz_WIRE_30; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_28_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_31; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_74 = _raw_hazard_mulpre_mul_raw_haz_WIRE_29[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_28_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_74; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_75 = _raw_hazard_mulpre_mul_raw_haz_WIRE_29[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_28_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_75; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_76 = _raw_hazard_mulpre_mul_raw_haz_WIRE_29[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_28_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_76; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_77 = _mesh_io_tags_in_progress_3_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_28_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_78 = _mesh_io_tags_in_progress_3_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_28_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_79 = _raw_hazard_mulpre_mul_raw_haz_T_77 & _raw_hazard_mulpre_mul_raw_haz_T_78; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz_3 = _raw_hazard_mulpre_mul_raw_haz_T_69 | _raw_hazard_mulpre_mul_raw_haz_T_79; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_15 = ~raw_hazard_mulpre_is_garbage_3; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_16 = raw_hazard_mulpre_mul_raw_haz_3 | raw_hazard_mulpre_pre_raw_haz_3; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_17 = _raw_hazard_mulpre_T_15 & _raw_hazard_mulpre_T_16; // @[ExecuteController.scala:225:{5,17,33}]
wire _raw_hazard_mulpre_T_19 = _raw_hazard_mulpre_T_17; // @[ExecuteController.scala:225:{17,49}]
wire _raw_hazard_mulpre_is_garbage_T_21 = _raw_hazard_mulpre_is_garbage_T_20 & _mesh_io_tags_in_progress_4_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_22 = &_mesh_io_tags_in_progress_4_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_23 = _raw_hazard_mulpre_is_garbage_T_21 & _raw_hazard_mulpre_is_garbage_T_22; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_24; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage_4 = _raw_hazard_mulpre_is_garbage_T_23 & _raw_hazard_mulpre_is_garbage_T_24; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_42; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_41; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_40; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_19; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_38; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_37; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T_36; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_36 = _raw_hazard_mulpre_pre_raw_haz_WIRE_17[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_16_data = _raw_hazard_mulpre_pre_raw_haz_T_36; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_37 = _raw_hazard_mulpre_pre_raw_haz_WIRE_17[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_16_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_37; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_38 = _raw_hazard_mulpre_pre_raw_haz_WIRE_17[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_16_garbage = _raw_hazard_mulpre_pre_raw_haz_T_38; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_39 = _raw_hazard_mulpre_pre_raw_haz_WIRE_17[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_18 = _raw_hazard_mulpre_pre_raw_haz_T_39; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_19 = _raw_hazard_mulpre_pre_raw_haz_WIRE_18; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_16_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_19; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_40 = _raw_hazard_mulpre_pre_raw_haz_WIRE_17[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_16_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_40; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_41 = _raw_hazard_mulpre_pre_raw_haz_WIRE_17[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_16_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_41; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_42 = _raw_hazard_mulpre_pre_raw_haz_WIRE_17[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_16_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_42; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_43 = _mesh_io_tags_in_progress_4_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_16_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_44 = _mesh_io_tags_in_progress_4_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_16_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz_4 = _raw_hazard_mulpre_pre_raw_haz_T_43 & _raw_hazard_mulpre_pre_raw_haz_T_44; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_86; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_85; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_84; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_35; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_82; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_81; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_80; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_80 = _raw_hazard_mulpre_mul_raw_haz_WIRE_33[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_32_data = _raw_hazard_mulpre_mul_raw_haz_T_80; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_81 = _raw_hazard_mulpre_mul_raw_haz_WIRE_33[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_32_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_81; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_82 = _raw_hazard_mulpre_mul_raw_haz_WIRE_33[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_32_garbage = _raw_hazard_mulpre_mul_raw_haz_T_82; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_83 = _raw_hazard_mulpre_mul_raw_haz_WIRE_33[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_34 = _raw_hazard_mulpre_mul_raw_haz_T_83; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_35 = _raw_hazard_mulpre_mul_raw_haz_WIRE_34; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_32_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_35; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_84 = _raw_hazard_mulpre_mul_raw_haz_WIRE_33[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_32_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_84; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_85 = _raw_hazard_mulpre_mul_raw_haz_WIRE_33[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_32_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_85; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_86 = _raw_hazard_mulpre_mul_raw_haz_WIRE_33[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_32_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_86; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_87 = _mesh_io_tags_in_progress_4_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_32_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_88 = _mesh_io_tags_in_progress_4_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_32_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_89 = _raw_hazard_mulpre_mul_raw_haz_T_87 & _raw_hazard_mulpre_mul_raw_haz_T_88; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_96; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_95; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_94; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_39; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_92; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_91; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_90; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_90 = _raw_hazard_mulpre_mul_raw_haz_WIRE_37[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_36_data = _raw_hazard_mulpre_mul_raw_haz_T_90; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_91 = _raw_hazard_mulpre_mul_raw_haz_WIRE_37[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_36_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_91; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_92 = _raw_hazard_mulpre_mul_raw_haz_WIRE_37[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_36_garbage = _raw_hazard_mulpre_mul_raw_haz_T_92; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_93 = _raw_hazard_mulpre_mul_raw_haz_WIRE_37[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_38 = _raw_hazard_mulpre_mul_raw_haz_T_93; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_39 = _raw_hazard_mulpre_mul_raw_haz_WIRE_38; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_36_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_39; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_94 = _raw_hazard_mulpre_mul_raw_haz_WIRE_37[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_36_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_94; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_95 = _raw_hazard_mulpre_mul_raw_haz_WIRE_37[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_36_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_95; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_96 = _raw_hazard_mulpre_mul_raw_haz_WIRE_37[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_36_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_96; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_97 = _mesh_io_tags_in_progress_4_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_36_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_98 = _mesh_io_tags_in_progress_4_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_36_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_99 = _raw_hazard_mulpre_mul_raw_haz_T_97 & _raw_hazard_mulpre_mul_raw_haz_T_98; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz_4 = _raw_hazard_mulpre_mul_raw_haz_T_89 | _raw_hazard_mulpre_mul_raw_haz_T_99; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_20 = ~raw_hazard_mulpre_is_garbage_4; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_21 = raw_hazard_mulpre_mul_raw_haz_4 | raw_hazard_mulpre_pre_raw_haz_4; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_22 = _raw_hazard_mulpre_T_20 & _raw_hazard_mulpre_T_21; // @[ExecuteController.scala:225:{5,17,33}]
wire _raw_hazard_mulpre_T_24 = _raw_hazard_mulpre_T_22; // @[ExecuteController.scala:225:{17,49}]
wire _raw_hazard_mulpre_is_garbage_T_26 = _raw_hazard_mulpre_is_garbage_T_25 & _mesh_io_tags_in_progress_5_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_27 = &_mesh_io_tags_in_progress_5_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_28 = _raw_hazard_mulpre_is_garbage_T_26 & _raw_hazard_mulpre_is_garbage_T_27; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_29; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage_5 = _raw_hazard_mulpre_is_garbage_T_28 & _raw_hazard_mulpre_is_garbage_T_29; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_51; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_50; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_49; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_23; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_47; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_46; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T_45; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_45 = _raw_hazard_mulpre_pre_raw_haz_WIRE_21[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_20_data = _raw_hazard_mulpre_pre_raw_haz_T_45; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_46 = _raw_hazard_mulpre_pre_raw_haz_WIRE_21[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_20_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_46; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_47 = _raw_hazard_mulpre_pre_raw_haz_WIRE_21[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_20_garbage = _raw_hazard_mulpre_pre_raw_haz_T_47; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_48 = _raw_hazard_mulpre_pre_raw_haz_WIRE_21[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_22 = _raw_hazard_mulpre_pre_raw_haz_T_48; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_23 = _raw_hazard_mulpre_pre_raw_haz_WIRE_22; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_20_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_23; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_49 = _raw_hazard_mulpre_pre_raw_haz_WIRE_21[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_20_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_49; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_50 = _raw_hazard_mulpre_pre_raw_haz_WIRE_21[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_20_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_50; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_51 = _raw_hazard_mulpre_pre_raw_haz_WIRE_21[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_20_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_51; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_52 = _mesh_io_tags_in_progress_5_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_20_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_53 = _mesh_io_tags_in_progress_5_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_20_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz_5 = _raw_hazard_mulpre_pre_raw_haz_T_52 & _raw_hazard_mulpre_pre_raw_haz_T_53; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_106; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_105; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_104; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_43; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_102; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_101; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_100; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_100 = _raw_hazard_mulpre_mul_raw_haz_WIRE_41[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_40_data = _raw_hazard_mulpre_mul_raw_haz_T_100; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_101 = _raw_hazard_mulpre_mul_raw_haz_WIRE_41[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_40_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_101; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_102 = _raw_hazard_mulpre_mul_raw_haz_WIRE_41[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_40_garbage = _raw_hazard_mulpre_mul_raw_haz_T_102; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_103 = _raw_hazard_mulpre_mul_raw_haz_WIRE_41[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_42 = _raw_hazard_mulpre_mul_raw_haz_T_103; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_43 = _raw_hazard_mulpre_mul_raw_haz_WIRE_42; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_40_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_43; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_104 = _raw_hazard_mulpre_mul_raw_haz_WIRE_41[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_40_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_104; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_105 = _raw_hazard_mulpre_mul_raw_haz_WIRE_41[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_40_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_105; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_106 = _raw_hazard_mulpre_mul_raw_haz_WIRE_41[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_40_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_106; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_107 = _mesh_io_tags_in_progress_5_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_40_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_108 = _mesh_io_tags_in_progress_5_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_40_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_109 = _raw_hazard_mulpre_mul_raw_haz_T_107 & _raw_hazard_mulpre_mul_raw_haz_T_108; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_116; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_115; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_114; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_47; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_112; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_111; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_110; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_110 = _raw_hazard_mulpre_mul_raw_haz_WIRE_45[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_44_data = _raw_hazard_mulpre_mul_raw_haz_T_110; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_111 = _raw_hazard_mulpre_mul_raw_haz_WIRE_45[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_44_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_111; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_112 = _raw_hazard_mulpre_mul_raw_haz_WIRE_45[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_44_garbage = _raw_hazard_mulpre_mul_raw_haz_T_112; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_113 = _raw_hazard_mulpre_mul_raw_haz_WIRE_45[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_46 = _raw_hazard_mulpre_mul_raw_haz_T_113; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_47 = _raw_hazard_mulpre_mul_raw_haz_WIRE_46; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_44_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_47; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_114 = _raw_hazard_mulpre_mul_raw_haz_WIRE_45[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_44_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_114; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_115 = _raw_hazard_mulpre_mul_raw_haz_WIRE_45[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_44_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_115; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_116 = _raw_hazard_mulpre_mul_raw_haz_WIRE_45[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_44_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_116; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_117 = _mesh_io_tags_in_progress_5_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_44_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_118 = _mesh_io_tags_in_progress_5_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_44_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_119 = _raw_hazard_mulpre_mul_raw_haz_T_117 & _raw_hazard_mulpre_mul_raw_haz_T_118; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz_5 = _raw_hazard_mulpre_mul_raw_haz_T_109 | _raw_hazard_mulpre_mul_raw_haz_T_119; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_25 = ~raw_hazard_mulpre_is_garbage_5; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_26 = raw_hazard_mulpre_mul_raw_haz_5 | raw_hazard_mulpre_pre_raw_haz_5; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_27 = _raw_hazard_mulpre_T_25 & _raw_hazard_mulpre_T_26; // @[ExecuteController.scala:225:{5,17,33}]
wire _raw_hazard_mulpre_T_29 = _raw_hazard_mulpre_T_27; // @[ExecuteController.scala:225:{17,49}]
wire _raw_hazard_mulpre_is_garbage_T_31 = _raw_hazard_mulpre_is_garbage_T_30 & _mesh_io_tags_in_progress_6_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_32 = &_mesh_io_tags_in_progress_6_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_33 = _raw_hazard_mulpre_is_garbage_T_31 & _raw_hazard_mulpre_is_garbage_T_32; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_34; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage_6 = _raw_hazard_mulpre_is_garbage_T_33 & _raw_hazard_mulpre_is_garbage_T_34; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_60; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_59; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_58; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_27; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_56; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_55; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T_54; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_54 = _raw_hazard_mulpre_pre_raw_haz_WIRE_25[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_24_data = _raw_hazard_mulpre_pre_raw_haz_T_54; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_55 = _raw_hazard_mulpre_pre_raw_haz_WIRE_25[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_24_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_55; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_56 = _raw_hazard_mulpre_pre_raw_haz_WIRE_25[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_24_garbage = _raw_hazard_mulpre_pre_raw_haz_T_56; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_57 = _raw_hazard_mulpre_pre_raw_haz_WIRE_25[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_26 = _raw_hazard_mulpre_pre_raw_haz_T_57; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_27 = _raw_hazard_mulpre_pre_raw_haz_WIRE_26; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_24_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_27; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_58 = _raw_hazard_mulpre_pre_raw_haz_WIRE_25[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_24_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_58; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_59 = _raw_hazard_mulpre_pre_raw_haz_WIRE_25[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_24_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_59; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_60 = _raw_hazard_mulpre_pre_raw_haz_WIRE_25[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_24_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_60; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_61 = _mesh_io_tags_in_progress_6_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_24_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_62 = _mesh_io_tags_in_progress_6_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_24_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz_6 = _raw_hazard_mulpre_pre_raw_haz_T_61 & _raw_hazard_mulpre_pre_raw_haz_T_62; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_126; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_125; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_124; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_51; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_122; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_121; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_120; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_120 = _raw_hazard_mulpre_mul_raw_haz_WIRE_49[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_48_data = _raw_hazard_mulpre_mul_raw_haz_T_120; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_121 = _raw_hazard_mulpre_mul_raw_haz_WIRE_49[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_48_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_121; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_122 = _raw_hazard_mulpre_mul_raw_haz_WIRE_49[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_48_garbage = _raw_hazard_mulpre_mul_raw_haz_T_122; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_123 = _raw_hazard_mulpre_mul_raw_haz_WIRE_49[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_50 = _raw_hazard_mulpre_mul_raw_haz_T_123; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_51 = _raw_hazard_mulpre_mul_raw_haz_WIRE_50; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_48_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_51; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_124 = _raw_hazard_mulpre_mul_raw_haz_WIRE_49[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_48_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_124; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_125 = _raw_hazard_mulpre_mul_raw_haz_WIRE_49[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_48_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_125; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_126 = _raw_hazard_mulpre_mul_raw_haz_WIRE_49[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_48_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_126; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_127 = _mesh_io_tags_in_progress_6_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_48_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_128 = _mesh_io_tags_in_progress_6_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_48_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_129 = _raw_hazard_mulpre_mul_raw_haz_T_127 & _raw_hazard_mulpre_mul_raw_haz_T_128; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_136; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_135; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_134; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_55; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_132; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_131; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_130; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_130 = _raw_hazard_mulpre_mul_raw_haz_WIRE_53[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_52_data = _raw_hazard_mulpre_mul_raw_haz_T_130; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_131 = _raw_hazard_mulpre_mul_raw_haz_WIRE_53[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_52_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_131; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_132 = _raw_hazard_mulpre_mul_raw_haz_WIRE_53[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_52_garbage = _raw_hazard_mulpre_mul_raw_haz_T_132; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_133 = _raw_hazard_mulpre_mul_raw_haz_WIRE_53[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_54 = _raw_hazard_mulpre_mul_raw_haz_T_133; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_55 = _raw_hazard_mulpre_mul_raw_haz_WIRE_54; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_52_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_55; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_134 = _raw_hazard_mulpre_mul_raw_haz_WIRE_53[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_52_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_134; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_135 = _raw_hazard_mulpre_mul_raw_haz_WIRE_53[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_52_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_135; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_136 = _raw_hazard_mulpre_mul_raw_haz_WIRE_53[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_52_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_136; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_137 = _mesh_io_tags_in_progress_6_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_52_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_138 = _mesh_io_tags_in_progress_6_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_52_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_139 = _raw_hazard_mulpre_mul_raw_haz_T_137 & _raw_hazard_mulpre_mul_raw_haz_T_138; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz_6 = _raw_hazard_mulpre_mul_raw_haz_T_129 | _raw_hazard_mulpre_mul_raw_haz_T_139; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_30 = ~raw_hazard_mulpre_is_garbage_6; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_31 = raw_hazard_mulpre_mul_raw_haz_6 | raw_hazard_mulpre_pre_raw_haz_6; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_32 = _raw_hazard_mulpre_T_30 & _raw_hazard_mulpre_T_31; // @[ExecuteController.scala:225:{5,17,33}]
wire _raw_hazard_mulpre_T_34 = _raw_hazard_mulpre_T_32; // @[ExecuteController.scala:225:{17,49}]
wire _raw_hazard_mulpre_is_garbage_T_36 = _raw_hazard_mulpre_is_garbage_T_35 & _mesh_io_tags_in_progress_7_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_37 = &_mesh_io_tags_in_progress_7_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_38 = _raw_hazard_mulpre_is_garbage_T_36 & _raw_hazard_mulpre_is_garbage_T_37; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_39; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage_7 = _raw_hazard_mulpre_is_garbage_T_38 & _raw_hazard_mulpre_is_garbage_T_39; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_69; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_68; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_67; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_31; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_65; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_64; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T_63; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_63 = _raw_hazard_mulpre_pre_raw_haz_WIRE_29[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_28_data = _raw_hazard_mulpre_pre_raw_haz_T_63; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_64 = _raw_hazard_mulpre_pre_raw_haz_WIRE_29[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_28_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_64; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_65 = _raw_hazard_mulpre_pre_raw_haz_WIRE_29[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_28_garbage = _raw_hazard_mulpre_pre_raw_haz_T_65; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_66 = _raw_hazard_mulpre_pre_raw_haz_WIRE_29[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_30 = _raw_hazard_mulpre_pre_raw_haz_T_66; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_31 = _raw_hazard_mulpre_pre_raw_haz_WIRE_30; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_28_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_31; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_67 = _raw_hazard_mulpre_pre_raw_haz_WIRE_29[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_28_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_67; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_68 = _raw_hazard_mulpre_pre_raw_haz_WIRE_29[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_28_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_68; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_69 = _raw_hazard_mulpre_pre_raw_haz_WIRE_29[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_28_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_69; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_70 = _mesh_io_tags_in_progress_7_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_28_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_71 = _mesh_io_tags_in_progress_7_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_28_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz_7 = _raw_hazard_mulpre_pre_raw_haz_T_70 & _raw_hazard_mulpre_pre_raw_haz_T_71; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_146; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_145; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_144; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_59; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_142; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_141; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_140; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_140 = _raw_hazard_mulpre_mul_raw_haz_WIRE_57[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_56_data = _raw_hazard_mulpre_mul_raw_haz_T_140; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_141 = _raw_hazard_mulpre_mul_raw_haz_WIRE_57[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_56_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_141; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_142 = _raw_hazard_mulpre_mul_raw_haz_WIRE_57[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_56_garbage = _raw_hazard_mulpre_mul_raw_haz_T_142; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_143 = _raw_hazard_mulpre_mul_raw_haz_WIRE_57[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_58 = _raw_hazard_mulpre_mul_raw_haz_T_143; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_59 = _raw_hazard_mulpre_mul_raw_haz_WIRE_58; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_56_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_59; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_144 = _raw_hazard_mulpre_mul_raw_haz_WIRE_57[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_56_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_144; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_145 = _raw_hazard_mulpre_mul_raw_haz_WIRE_57[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_56_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_145; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_146 = _raw_hazard_mulpre_mul_raw_haz_WIRE_57[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_56_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_146; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_147 = _mesh_io_tags_in_progress_7_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_56_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_148 = _mesh_io_tags_in_progress_7_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_56_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_149 = _raw_hazard_mulpre_mul_raw_haz_T_147 & _raw_hazard_mulpre_mul_raw_haz_T_148; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_156; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_155; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_154; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_63; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_152; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_151; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_150; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_150 = _raw_hazard_mulpre_mul_raw_haz_WIRE_61[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_60_data = _raw_hazard_mulpre_mul_raw_haz_T_150; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_151 = _raw_hazard_mulpre_mul_raw_haz_WIRE_61[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_60_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_151; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_152 = _raw_hazard_mulpre_mul_raw_haz_WIRE_61[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_60_garbage = _raw_hazard_mulpre_mul_raw_haz_T_152; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_153 = _raw_hazard_mulpre_mul_raw_haz_WIRE_61[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_62 = _raw_hazard_mulpre_mul_raw_haz_T_153; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_63 = _raw_hazard_mulpre_mul_raw_haz_WIRE_62; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_60_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_63; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_154 = _raw_hazard_mulpre_mul_raw_haz_WIRE_61[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_60_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_154; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_155 = _raw_hazard_mulpre_mul_raw_haz_WIRE_61[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_60_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_155; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_156 = _raw_hazard_mulpre_mul_raw_haz_WIRE_61[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_60_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_156; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_157 = _mesh_io_tags_in_progress_7_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_60_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_158 = _mesh_io_tags_in_progress_7_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_60_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_159 = _raw_hazard_mulpre_mul_raw_haz_T_157 & _raw_hazard_mulpre_mul_raw_haz_T_158; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz_7 = _raw_hazard_mulpre_mul_raw_haz_T_149 | _raw_hazard_mulpre_mul_raw_haz_T_159; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_35 = ~raw_hazard_mulpre_is_garbage_7; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_36 = raw_hazard_mulpre_mul_raw_haz_7 | raw_hazard_mulpre_pre_raw_haz_7; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_37 = _raw_hazard_mulpre_T_35 & _raw_hazard_mulpre_T_36; // @[ExecuteController.scala:225:{5,17,33}]
wire _raw_hazard_mulpre_T_39 = _raw_hazard_mulpre_T_37; // @[ExecuteController.scala:225:{17,49}]
wire _raw_hazard_mulpre_is_garbage_T_41 = _raw_hazard_mulpre_is_garbage_T_40 & _mesh_io_tags_in_progress_8_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_42 = &_mesh_io_tags_in_progress_8_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_43 = _raw_hazard_mulpre_is_garbage_T_41 & _raw_hazard_mulpre_is_garbage_T_42; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_44; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage_8 = _raw_hazard_mulpre_is_garbage_T_43 & _raw_hazard_mulpre_is_garbage_T_44; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_78; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_77; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_76; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_35; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_74; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_73; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T_72; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_72 = _raw_hazard_mulpre_pre_raw_haz_WIRE_33[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_32_data = _raw_hazard_mulpre_pre_raw_haz_T_72; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_73 = _raw_hazard_mulpre_pre_raw_haz_WIRE_33[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_32_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_73; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_74 = _raw_hazard_mulpre_pre_raw_haz_WIRE_33[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_32_garbage = _raw_hazard_mulpre_pre_raw_haz_T_74; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_75 = _raw_hazard_mulpre_pre_raw_haz_WIRE_33[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_34 = _raw_hazard_mulpre_pre_raw_haz_T_75; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_35 = _raw_hazard_mulpre_pre_raw_haz_WIRE_34; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_32_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_35; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_76 = _raw_hazard_mulpre_pre_raw_haz_WIRE_33[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_32_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_76; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_77 = _raw_hazard_mulpre_pre_raw_haz_WIRE_33[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_32_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_77; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_78 = _raw_hazard_mulpre_pre_raw_haz_WIRE_33[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_32_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_78; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_79 = _mesh_io_tags_in_progress_8_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_32_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_80 = _mesh_io_tags_in_progress_8_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_32_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz_8 = _raw_hazard_mulpre_pre_raw_haz_T_79 & _raw_hazard_mulpre_pre_raw_haz_T_80; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_166; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_165; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_164; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_67; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_162; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_161; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_160; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_160 = _raw_hazard_mulpre_mul_raw_haz_WIRE_65[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_64_data = _raw_hazard_mulpre_mul_raw_haz_T_160; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_161 = _raw_hazard_mulpre_mul_raw_haz_WIRE_65[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_64_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_161; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_162 = _raw_hazard_mulpre_mul_raw_haz_WIRE_65[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_64_garbage = _raw_hazard_mulpre_mul_raw_haz_T_162; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_163 = _raw_hazard_mulpre_mul_raw_haz_WIRE_65[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_66 = _raw_hazard_mulpre_mul_raw_haz_T_163; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_67 = _raw_hazard_mulpre_mul_raw_haz_WIRE_66; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_64_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_67; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_164 = _raw_hazard_mulpre_mul_raw_haz_WIRE_65[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_64_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_164; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_165 = _raw_hazard_mulpre_mul_raw_haz_WIRE_65[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_64_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_165; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_166 = _raw_hazard_mulpre_mul_raw_haz_WIRE_65[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_64_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_166; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_167 = _mesh_io_tags_in_progress_8_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_64_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_168 = _mesh_io_tags_in_progress_8_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_64_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_169 = _raw_hazard_mulpre_mul_raw_haz_T_167 & _raw_hazard_mulpre_mul_raw_haz_T_168; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_176; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_175; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_174; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_71; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_172; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_171; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_170; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_170 = _raw_hazard_mulpre_mul_raw_haz_WIRE_69[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_68_data = _raw_hazard_mulpre_mul_raw_haz_T_170; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_171 = _raw_hazard_mulpre_mul_raw_haz_WIRE_69[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_68_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_171; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_172 = _raw_hazard_mulpre_mul_raw_haz_WIRE_69[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_68_garbage = _raw_hazard_mulpre_mul_raw_haz_T_172; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_173 = _raw_hazard_mulpre_mul_raw_haz_WIRE_69[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_70 = _raw_hazard_mulpre_mul_raw_haz_T_173; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_71 = _raw_hazard_mulpre_mul_raw_haz_WIRE_70; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_68_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_71; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_174 = _raw_hazard_mulpre_mul_raw_haz_WIRE_69[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_68_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_174; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_175 = _raw_hazard_mulpre_mul_raw_haz_WIRE_69[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_68_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_175; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_176 = _raw_hazard_mulpre_mul_raw_haz_WIRE_69[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_68_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_176; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_177 = _mesh_io_tags_in_progress_8_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_68_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_178 = _mesh_io_tags_in_progress_8_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_68_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_179 = _raw_hazard_mulpre_mul_raw_haz_T_177 & _raw_hazard_mulpre_mul_raw_haz_T_178; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz_8 = _raw_hazard_mulpre_mul_raw_haz_T_169 | _raw_hazard_mulpre_mul_raw_haz_T_179; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_40 = ~raw_hazard_mulpre_is_garbage_8; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_41 = raw_hazard_mulpre_mul_raw_haz_8 | raw_hazard_mulpre_pre_raw_haz_8; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_42 = _raw_hazard_mulpre_T_40 & _raw_hazard_mulpre_T_41; // @[ExecuteController.scala:225:{5,17,33}]
wire _raw_hazard_mulpre_T_44 = _raw_hazard_mulpre_T_42; // @[ExecuteController.scala:225:{17,49}]
wire _raw_hazard_mulpre_is_garbage_T_46 = _raw_hazard_mulpre_is_garbage_T_45 & _mesh_io_tags_in_progress_9_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_47 = &_mesh_io_tags_in_progress_9_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_48 = _raw_hazard_mulpre_is_garbage_T_46 & _raw_hazard_mulpre_is_garbage_T_47; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_49; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage_9 = _raw_hazard_mulpre_is_garbage_T_48 & _raw_hazard_mulpre_is_garbage_T_49; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_87; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_86; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_85; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_39; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_83; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_82; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T_81; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_81 = _raw_hazard_mulpre_pre_raw_haz_WIRE_37[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_36_data = _raw_hazard_mulpre_pre_raw_haz_T_81; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_82 = _raw_hazard_mulpre_pre_raw_haz_WIRE_37[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_36_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_82; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_83 = _raw_hazard_mulpre_pre_raw_haz_WIRE_37[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_36_garbage = _raw_hazard_mulpre_pre_raw_haz_T_83; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_84 = _raw_hazard_mulpre_pre_raw_haz_WIRE_37[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_38 = _raw_hazard_mulpre_pre_raw_haz_T_84; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_39 = _raw_hazard_mulpre_pre_raw_haz_WIRE_38; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_36_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_39; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_85 = _raw_hazard_mulpre_pre_raw_haz_WIRE_37[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_36_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_85; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_86 = _raw_hazard_mulpre_pre_raw_haz_WIRE_37[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_36_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_86; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_87 = _raw_hazard_mulpre_pre_raw_haz_WIRE_37[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_36_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_87; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_88 = _mesh_io_tags_in_progress_9_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_36_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_89 = _mesh_io_tags_in_progress_9_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_36_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz_9 = _raw_hazard_mulpre_pre_raw_haz_T_88 & _raw_hazard_mulpre_pre_raw_haz_T_89; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_186; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_185; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_184; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_75; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_182; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_181; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_180; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_180 = _raw_hazard_mulpre_mul_raw_haz_WIRE_73[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_72_data = _raw_hazard_mulpre_mul_raw_haz_T_180; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_181 = _raw_hazard_mulpre_mul_raw_haz_WIRE_73[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_72_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_181; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_182 = _raw_hazard_mulpre_mul_raw_haz_WIRE_73[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_72_garbage = _raw_hazard_mulpre_mul_raw_haz_T_182; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_183 = _raw_hazard_mulpre_mul_raw_haz_WIRE_73[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_74 = _raw_hazard_mulpre_mul_raw_haz_T_183; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_75 = _raw_hazard_mulpre_mul_raw_haz_WIRE_74; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_72_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_75; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_184 = _raw_hazard_mulpre_mul_raw_haz_WIRE_73[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_72_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_184; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_185 = _raw_hazard_mulpre_mul_raw_haz_WIRE_73[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_72_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_185; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_186 = _raw_hazard_mulpre_mul_raw_haz_WIRE_73[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_72_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_186; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_187 = _mesh_io_tags_in_progress_9_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_72_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_188 = _mesh_io_tags_in_progress_9_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_72_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_189 = _raw_hazard_mulpre_mul_raw_haz_T_187 & _raw_hazard_mulpre_mul_raw_haz_T_188; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_196; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_195; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_194; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_79; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_192; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_191; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_190; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_190 = _raw_hazard_mulpre_mul_raw_haz_WIRE_77[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_76_data = _raw_hazard_mulpre_mul_raw_haz_T_190; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_191 = _raw_hazard_mulpre_mul_raw_haz_WIRE_77[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_76_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_191; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_192 = _raw_hazard_mulpre_mul_raw_haz_WIRE_77[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_76_garbage = _raw_hazard_mulpre_mul_raw_haz_T_192; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_193 = _raw_hazard_mulpre_mul_raw_haz_WIRE_77[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_78 = _raw_hazard_mulpre_mul_raw_haz_T_193; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_79 = _raw_hazard_mulpre_mul_raw_haz_WIRE_78; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_76_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_79; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_194 = _raw_hazard_mulpre_mul_raw_haz_WIRE_77[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_76_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_194; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_195 = _raw_hazard_mulpre_mul_raw_haz_WIRE_77[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_76_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_195; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_196 = _raw_hazard_mulpre_mul_raw_haz_WIRE_77[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_76_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_196; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_197 = _mesh_io_tags_in_progress_9_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_76_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_198 = _mesh_io_tags_in_progress_9_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_76_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_199 = _raw_hazard_mulpre_mul_raw_haz_T_197 & _raw_hazard_mulpre_mul_raw_haz_T_198; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz_9 = _raw_hazard_mulpre_mul_raw_haz_T_189 | _raw_hazard_mulpre_mul_raw_haz_T_199; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_45 = ~raw_hazard_mulpre_is_garbage_9; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_46 = raw_hazard_mulpre_mul_raw_haz_9 | raw_hazard_mulpre_pre_raw_haz_9; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_47 = _raw_hazard_mulpre_T_45 & _raw_hazard_mulpre_T_46; // @[ExecuteController.scala:225:{5,17,33}]
wire _raw_hazard_mulpre_T_49 = _raw_hazard_mulpre_T_47; // @[ExecuteController.scala:225:{17,49}]
wire _raw_hazard_mulpre_is_garbage_T_51 = _raw_hazard_mulpre_is_garbage_T_50 & _mesh_io_tags_in_progress_10_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_52 = &_mesh_io_tags_in_progress_10_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_53 = _raw_hazard_mulpre_is_garbage_T_51 & _raw_hazard_mulpre_is_garbage_T_52; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_54; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage_10 = _raw_hazard_mulpre_is_garbage_T_53 & _raw_hazard_mulpre_is_garbage_T_54; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_96; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_95; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_94; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_43; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_92; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_91; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T_90; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_90 = _raw_hazard_mulpre_pre_raw_haz_WIRE_41[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_40_data = _raw_hazard_mulpre_pre_raw_haz_T_90; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_91 = _raw_hazard_mulpre_pre_raw_haz_WIRE_41[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_40_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_91; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_92 = _raw_hazard_mulpre_pre_raw_haz_WIRE_41[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_40_garbage = _raw_hazard_mulpre_pre_raw_haz_T_92; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_93 = _raw_hazard_mulpre_pre_raw_haz_WIRE_41[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_42 = _raw_hazard_mulpre_pre_raw_haz_T_93; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_43 = _raw_hazard_mulpre_pre_raw_haz_WIRE_42; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_40_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_43; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_94 = _raw_hazard_mulpre_pre_raw_haz_WIRE_41[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_40_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_94; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_95 = _raw_hazard_mulpre_pre_raw_haz_WIRE_41[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_40_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_95; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_96 = _raw_hazard_mulpre_pre_raw_haz_WIRE_41[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_40_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_96; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_97 = _mesh_io_tags_in_progress_10_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_40_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_98 = _mesh_io_tags_in_progress_10_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_40_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz_10 = _raw_hazard_mulpre_pre_raw_haz_T_97 & _raw_hazard_mulpre_pre_raw_haz_T_98; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_206; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_205; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_204; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_83; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_202; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_201; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_200; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_200 = _raw_hazard_mulpre_mul_raw_haz_WIRE_81[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_80_data = _raw_hazard_mulpre_mul_raw_haz_T_200; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_201 = _raw_hazard_mulpre_mul_raw_haz_WIRE_81[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_80_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_201; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_202 = _raw_hazard_mulpre_mul_raw_haz_WIRE_81[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_80_garbage = _raw_hazard_mulpre_mul_raw_haz_T_202; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_203 = _raw_hazard_mulpre_mul_raw_haz_WIRE_81[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_82 = _raw_hazard_mulpre_mul_raw_haz_T_203; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_83 = _raw_hazard_mulpre_mul_raw_haz_WIRE_82; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_80_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_83; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_204 = _raw_hazard_mulpre_mul_raw_haz_WIRE_81[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_80_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_204; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_205 = _raw_hazard_mulpre_mul_raw_haz_WIRE_81[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_80_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_205; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_206 = _raw_hazard_mulpre_mul_raw_haz_WIRE_81[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_80_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_206; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_207 = _mesh_io_tags_in_progress_10_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_80_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_208 = _mesh_io_tags_in_progress_10_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_80_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_209 = _raw_hazard_mulpre_mul_raw_haz_T_207 & _raw_hazard_mulpre_mul_raw_haz_T_208; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_216; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_215; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_214; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_87; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_212; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_211; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_210; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_210 = _raw_hazard_mulpre_mul_raw_haz_WIRE_85[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_84_data = _raw_hazard_mulpre_mul_raw_haz_T_210; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_211 = _raw_hazard_mulpre_mul_raw_haz_WIRE_85[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_84_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_211; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_212 = _raw_hazard_mulpre_mul_raw_haz_WIRE_85[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_84_garbage = _raw_hazard_mulpre_mul_raw_haz_T_212; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_213 = _raw_hazard_mulpre_mul_raw_haz_WIRE_85[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_86 = _raw_hazard_mulpre_mul_raw_haz_T_213; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_87 = _raw_hazard_mulpre_mul_raw_haz_WIRE_86; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_84_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_87; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_214 = _raw_hazard_mulpre_mul_raw_haz_WIRE_85[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_84_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_214; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_215 = _raw_hazard_mulpre_mul_raw_haz_WIRE_85[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_84_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_215; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_216 = _raw_hazard_mulpre_mul_raw_haz_WIRE_85[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_84_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_216; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_217 = _mesh_io_tags_in_progress_10_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_84_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_218 = _mesh_io_tags_in_progress_10_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_84_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_219 = _raw_hazard_mulpre_mul_raw_haz_T_217 & _raw_hazard_mulpre_mul_raw_haz_T_218; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz_10 = _raw_hazard_mulpre_mul_raw_haz_T_209 | _raw_hazard_mulpre_mul_raw_haz_T_219; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_50 = ~raw_hazard_mulpre_is_garbage_10; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_51 = raw_hazard_mulpre_mul_raw_haz_10 | raw_hazard_mulpre_pre_raw_haz_10; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_52 = _raw_hazard_mulpre_T_50 & _raw_hazard_mulpre_T_51; // @[ExecuteController.scala:225:{5,17,33}]
wire _raw_hazard_mulpre_T_54 = _raw_hazard_mulpre_T_52; // @[ExecuteController.scala:225:{17,49}]
wire _raw_hazard_mulpre_is_garbage_T_56 = _raw_hazard_mulpre_is_garbage_T_55 & _mesh_io_tags_in_progress_11_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_57 = &_mesh_io_tags_in_progress_11_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_58 = _raw_hazard_mulpre_is_garbage_T_56 & _raw_hazard_mulpre_is_garbage_T_57; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_59; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage_11 = _raw_hazard_mulpre_is_garbage_T_58 & _raw_hazard_mulpre_is_garbage_T_59; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_105; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_104; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_103; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_47; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_101; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_100; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T_99; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_99 = _raw_hazard_mulpre_pre_raw_haz_WIRE_45[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_44_data = _raw_hazard_mulpre_pre_raw_haz_T_99; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_100 = _raw_hazard_mulpre_pre_raw_haz_WIRE_45[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_44_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_100; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_101 = _raw_hazard_mulpre_pre_raw_haz_WIRE_45[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_44_garbage = _raw_hazard_mulpre_pre_raw_haz_T_101; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_102 = _raw_hazard_mulpre_pre_raw_haz_WIRE_45[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_46 = _raw_hazard_mulpre_pre_raw_haz_T_102; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_47 = _raw_hazard_mulpre_pre_raw_haz_WIRE_46; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_44_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_47; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_103 = _raw_hazard_mulpre_pre_raw_haz_WIRE_45[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_44_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_103; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_104 = _raw_hazard_mulpre_pre_raw_haz_WIRE_45[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_44_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_104; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_105 = _raw_hazard_mulpre_pre_raw_haz_WIRE_45[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_44_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_105; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_106 = _mesh_io_tags_in_progress_11_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_44_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_107 = _mesh_io_tags_in_progress_11_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_44_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz_11 = _raw_hazard_mulpre_pre_raw_haz_T_106 & _raw_hazard_mulpre_pre_raw_haz_T_107; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_226; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_225; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_224; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_91; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_222; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_221; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_220; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_220 = _raw_hazard_mulpre_mul_raw_haz_WIRE_89[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_88_data = _raw_hazard_mulpre_mul_raw_haz_T_220; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_221 = _raw_hazard_mulpre_mul_raw_haz_WIRE_89[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_88_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_221; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_222 = _raw_hazard_mulpre_mul_raw_haz_WIRE_89[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_88_garbage = _raw_hazard_mulpre_mul_raw_haz_T_222; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_223 = _raw_hazard_mulpre_mul_raw_haz_WIRE_89[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_90 = _raw_hazard_mulpre_mul_raw_haz_T_223; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_91 = _raw_hazard_mulpre_mul_raw_haz_WIRE_90; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_88_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_91; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_224 = _raw_hazard_mulpre_mul_raw_haz_WIRE_89[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_88_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_224; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_225 = _raw_hazard_mulpre_mul_raw_haz_WIRE_89[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_88_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_225; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_226 = _raw_hazard_mulpre_mul_raw_haz_WIRE_89[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_88_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_226; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_227 = _mesh_io_tags_in_progress_11_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_88_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_228 = _mesh_io_tags_in_progress_11_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_88_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_229 = _raw_hazard_mulpre_mul_raw_haz_T_227 & _raw_hazard_mulpre_mul_raw_haz_T_228; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_236; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_235; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_234; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_95; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_232; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_231; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_230; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_230 = _raw_hazard_mulpre_mul_raw_haz_WIRE_93[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_92_data = _raw_hazard_mulpre_mul_raw_haz_T_230; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_231 = _raw_hazard_mulpre_mul_raw_haz_WIRE_93[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_92_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_231; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_232 = _raw_hazard_mulpre_mul_raw_haz_WIRE_93[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_92_garbage = _raw_hazard_mulpre_mul_raw_haz_T_232; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_233 = _raw_hazard_mulpre_mul_raw_haz_WIRE_93[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_94 = _raw_hazard_mulpre_mul_raw_haz_T_233; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_95 = _raw_hazard_mulpre_mul_raw_haz_WIRE_94; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_92_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_95; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_234 = _raw_hazard_mulpre_mul_raw_haz_WIRE_93[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_92_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_234; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_235 = _raw_hazard_mulpre_mul_raw_haz_WIRE_93[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_92_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_235; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_236 = _raw_hazard_mulpre_mul_raw_haz_WIRE_93[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_92_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_236; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_237 = _mesh_io_tags_in_progress_11_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_92_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_238 = _mesh_io_tags_in_progress_11_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_92_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_239 = _raw_hazard_mulpre_mul_raw_haz_T_237 & _raw_hazard_mulpre_mul_raw_haz_T_238; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz_11 = _raw_hazard_mulpre_mul_raw_haz_T_229 | _raw_hazard_mulpre_mul_raw_haz_T_239; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_55 = ~raw_hazard_mulpre_is_garbage_11; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_56 = raw_hazard_mulpre_mul_raw_haz_11 | raw_hazard_mulpre_pre_raw_haz_11; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_57 = _raw_hazard_mulpre_T_55 & _raw_hazard_mulpre_T_56; // @[ExecuteController.scala:225:{5,17,33}]
wire _raw_hazard_mulpre_T_59 = _raw_hazard_mulpre_T_57; // @[ExecuteController.scala:225:{17,49}]
wire _raw_hazard_mulpre_is_garbage_T_61 = _raw_hazard_mulpre_is_garbage_T_60 & _mesh_io_tags_in_progress_12_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_62 = &_mesh_io_tags_in_progress_12_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_63 = _raw_hazard_mulpre_is_garbage_T_61 & _raw_hazard_mulpre_is_garbage_T_62; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_64; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage_12 = _raw_hazard_mulpre_is_garbage_T_63 & _raw_hazard_mulpre_is_garbage_T_64; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_114; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_113; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_112; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_51; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_110; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_109; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T_108; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_108 = _raw_hazard_mulpre_pre_raw_haz_WIRE_49[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_48_data = _raw_hazard_mulpre_pre_raw_haz_T_108; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_109 = _raw_hazard_mulpre_pre_raw_haz_WIRE_49[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_48_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_109; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_110 = _raw_hazard_mulpre_pre_raw_haz_WIRE_49[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_48_garbage = _raw_hazard_mulpre_pre_raw_haz_T_110; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_111 = _raw_hazard_mulpre_pre_raw_haz_WIRE_49[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_50 = _raw_hazard_mulpre_pre_raw_haz_T_111; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_51 = _raw_hazard_mulpre_pre_raw_haz_WIRE_50; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_48_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_51; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_112 = _raw_hazard_mulpre_pre_raw_haz_WIRE_49[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_48_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_112; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_113 = _raw_hazard_mulpre_pre_raw_haz_WIRE_49[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_48_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_113; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_114 = _raw_hazard_mulpre_pre_raw_haz_WIRE_49[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_48_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_114; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_115 = _mesh_io_tags_in_progress_12_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_48_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_116 = _mesh_io_tags_in_progress_12_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_48_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz_12 = _raw_hazard_mulpre_pre_raw_haz_T_115 & _raw_hazard_mulpre_pre_raw_haz_T_116; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_246; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_245; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_244; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_99; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_242; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_241; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_240; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_240 = _raw_hazard_mulpre_mul_raw_haz_WIRE_97[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_96_data = _raw_hazard_mulpre_mul_raw_haz_T_240; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_241 = _raw_hazard_mulpre_mul_raw_haz_WIRE_97[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_96_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_241; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_242 = _raw_hazard_mulpre_mul_raw_haz_WIRE_97[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_96_garbage = _raw_hazard_mulpre_mul_raw_haz_T_242; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_243 = _raw_hazard_mulpre_mul_raw_haz_WIRE_97[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_98 = _raw_hazard_mulpre_mul_raw_haz_T_243; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_99 = _raw_hazard_mulpre_mul_raw_haz_WIRE_98; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_96_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_99; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_244 = _raw_hazard_mulpre_mul_raw_haz_WIRE_97[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_96_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_244; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_245 = _raw_hazard_mulpre_mul_raw_haz_WIRE_97[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_96_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_245; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_246 = _raw_hazard_mulpre_mul_raw_haz_WIRE_97[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_96_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_246; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_247 = _mesh_io_tags_in_progress_12_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_96_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_248 = _mesh_io_tags_in_progress_12_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_96_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_249 = _raw_hazard_mulpre_mul_raw_haz_T_247 & _raw_hazard_mulpre_mul_raw_haz_T_248; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_256; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_255; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_254; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_103; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_252; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_251; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_250; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_250 = _raw_hazard_mulpre_mul_raw_haz_WIRE_101[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_100_data = _raw_hazard_mulpre_mul_raw_haz_T_250; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_251 = _raw_hazard_mulpre_mul_raw_haz_WIRE_101[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_100_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_251; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_252 = _raw_hazard_mulpre_mul_raw_haz_WIRE_101[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_100_garbage = _raw_hazard_mulpre_mul_raw_haz_T_252; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_253 = _raw_hazard_mulpre_mul_raw_haz_WIRE_101[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_102 = _raw_hazard_mulpre_mul_raw_haz_T_253; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_103 = _raw_hazard_mulpre_mul_raw_haz_WIRE_102; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_100_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_103; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_254 = _raw_hazard_mulpre_mul_raw_haz_WIRE_101[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_100_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_254; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_255 = _raw_hazard_mulpre_mul_raw_haz_WIRE_101[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_100_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_255; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_256 = _raw_hazard_mulpre_mul_raw_haz_WIRE_101[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_100_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_256; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_257 = _mesh_io_tags_in_progress_12_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_100_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_258 = _mesh_io_tags_in_progress_12_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_100_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_259 = _raw_hazard_mulpre_mul_raw_haz_T_257 & _raw_hazard_mulpre_mul_raw_haz_T_258; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz_12 = _raw_hazard_mulpre_mul_raw_haz_T_249 | _raw_hazard_mulpre_mul_raw_haz_T_259; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_60 = ~raw_hazard_mulpre_is_garbage_12; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_61 = raw_hazard_mulpre_mul_raw_haz_12 | raw_hazard_mulpre_pre_raw_haz_12; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_62 = _raw_hazard_mulpre_T_60 & _raw_hazard_mulpre_T_61; // @[ExecuteController.scala:225:{5,17,33}]
wire _raw_hazard_mulpre_T_64 = _raw_hazard_mulpre_T_62; // @[ExecuteController.scala:225:{17,49}]
wire _raw_hazard_mulpre_is_garbage_T_66 = _raw_hazard_mulpre_is_garbage_T_65 & _mesh_io_tags_in_progress_13_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_67 = &_mesh_io_tags_in_progress_13_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_68 = _raw_hazard_mulpre_is_garbage_T_66 & _raw_hazard_mulpre_is_garbage_T_67; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_69; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage_13 = _raw_hazard_mulpre_is_garbage_T_68 & _raw_hazard_mulpre_is_garbage_T_69; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_123; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_122; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_121; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_55; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_119; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_118; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T_117; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_117 = _raw_hazard_mulpre_pre_raw_haz_WIRE_53[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_52_data = _raw_hazard_mulpre_pre_raw_haz_T_117; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_118 = _raw_hazard_mulpre_pre_raw_haz_WIRE_53[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_52_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_118; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_119 = _raw_hazard_mulpre_pre_raw_haz_WIRE_53[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_52_garbage = _raw_hazard_mulpre_pre_raw_haz_T_119; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_120 = _raw_hazard_mulpre_pre_raw_haz_WIRE_53[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_54 = _raw_hazard_mulpre_pre_raw_haz_T_120; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_55 = _raw_hazard_mulpre_pre_raw_haz_WIRE_54; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_52_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_55; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_121 = _raw_hazard_mulpre_pre_raw_haz_WIRE_53[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_52_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_121; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_122 = _raw_hazard_mulpre_pre_raw_haz_WIRE_53[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_52_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_122; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_123 = _raw_hazard_mulpre_pre_raw_haz_WIRE_53[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_52_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_123; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_124 = _mesh_io_tags_in_progress_13_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_52_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_125 = _mesh_io_tags_in_progress_13_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_52_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz_13 = _raw_hazard_mulpre_pre_raw_haz_T_124 & _raw_hazard_mulpre_pre_raw_haz_T_125; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_266; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_265; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_264; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_107; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_262; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_261; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_260; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_260 = _raw_hazard_mulpre_mul_raw_haz_WIRE_105[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_104_data = _raw_hazard_mulpre_mul_raw_haz_T_260; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_261 = _raw_hazard_mulpre_mul_raw_haz_WIRE_105[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_104_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_261; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_262 = _raw_hazard_mulpre_mul_raw_haz_WIRE_105[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_104_garbage = _raw_hazard_mulpre_mul_raw_haz_T_262; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_263 = _raw_hazard_mulpre_mul_raw_haz_WIRE_105[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_106 = _raw_hazard_mulpre_mul_raw_haz_T_263; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_107 = _raw_hazard_mulpre_mul_raw_haz_WIRE_106; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_104_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_107; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_264 = _raw_hazard_mulpre_mul_raw_haz_WIRE_105[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_104_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_264; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_265 = _raw_hazard_mulpre_mul_raw_haz_WIRE_105[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_104_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_265; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_266 = _raw_hazard_mulpre_mul_raw_haz_WIRE_105[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_104_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_266; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_267 = _mesh_io_tags_in_progress_13_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_104_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_268 = _mesh_io_tags_in_progress_13_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_104_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_269 = _raw_hazard_mulpre_mul_raw_haz_T_267 & _raw_hazard_mulpre_mul_raw_haz_T_268; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_276; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_275; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_274; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_111; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_272; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_271; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_270; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_270 = _raw_hazard_mulpre_mul_raw_haz_WIRE_109[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_108_data = _raw_hazard_mulpre_mul_raw_haz_T_270; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_271 = _raw_hazard_mulpre_mul_raw_haz_WIRE_109[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_108_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_271; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_272 = _raw_hazard_mulpre_mul_raw_haz_WIRE_109[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_108_garbage = _raw_hazard_mulpre_mul_raw_haz_T_272; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_273 = _raw_hazard_mulpre_mul_raw_haz_WIRE_109[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_110 = _raw_hazard_mulpre_mul_raw_haz_T_273; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_111 = _raw_hazard_mulpre_mul_raw_haz_WIRE_110; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_108_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_111; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_274 = _raw_hazard_mulpre_mul_raw_haz_WIRE_109[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_108_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_274; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_275 = _raw_hazard_mulpre_mul_raw_haz_WIRE_109[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_108_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_275; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_276 = _raw_hazard_mulpre_mul_raw_haz_WIRE_109[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_108_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_276; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_277 = _mesh_io_tags_in_progress_13_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_108_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_278 = _mesh_io_tags_in_progress_13_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_108_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_279 = _raw_hazard_mulpre_mul_raw_haz_T_277 & _raw_hazard_mulpre_mul_raw_haz_T_278; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz_13 = _raw_hazard_mulpre_mul_raw_haz_T_269 | _raw_hazard_mulpre_mul_raw_haz_T_279; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_65 = ~raw_hazard_mulpre_is_garbage_13; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_66 = raw_hazard_mulpre_mul_raw_haz_13 | raw_hazard_mulpre_pre_raw_haz_13; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_67 = _raw_hazard_mulpre_T_65 & _raw_hazard_mulpre_T_66; // @[ExecuteController.scala:225:{5,17,33}]
wire _raw_hazard_mulpre_T_69 = _raw_hazard_mulpre_T_67; // @[ExecuteController.scala:225:{17,49}]
wire _raw_hazard_mulpre_is_garbage_T_71 = _raw_hazard_mulpre_is_garbage_T_70 & _mesh_io_tags_in_progress_14_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_72 = &_mesh_io_tags_in_progress_14_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_73 = _raw_hazard_mulpre_is_garbage_T_71 & _raw_hazard_mulpre_is_garbage_T_72; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_74; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage_14 = _raw_hazard_mulpre_is_garbage_T_73 & _raw_hazard_mulpre_is_garbage_T_74; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_132; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_131; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_130; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_59; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_128; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_127; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T_126; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_126 = _raw_hazard_mulpre_pre_raw_haz_WIRE_57[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_56_data = _raw_hazard_mulpre_pre_raw_haz_T_126; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_127 = _raw_hazard_mulpre_pre_raw_haz_WIRE_57[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_56_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_127; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_128 = _raw_hazard_mulpre_pre_raw_haz_WIRE_57[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_56_garbage = _raw_hazard_mulpre_pre_raw_haz_T_128; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_129 = _raw_hazard_mulpre_pre_raw_haz_WIRE_57[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_58 = _raw_hazard_mulpre_pre_raw_haz_T_129; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_59 = _raw_hazard_mulpre_pre_raw_haz_WIRE_58; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_56_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_59; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_130 = _raw_hazard_mulpre_pre_raw_haz_WIRE_57[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_56_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_130; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_131 = _raw_hazard_mulpre_pre_raw_haz_WIRE_57[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_56_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_131; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_132 = _raw_hazard_mulpre_pre_raw_haz_WIRE_57[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_56_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_132; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_133 = _mesh_io_tags_in_progress_14_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_56_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_134 = _mesh_io_tags_in_progress_14_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_56_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz_14 = _raw_hazard_mulpre_pre_raw_haz_T_133 & _raw_hazard_mulpre_pre_raw_haz_T_134; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_286; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_285; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_284; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_115; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_282; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_281; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_280; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_280 = _raw_hazard_mulpre_mul_raw_haz_WIRE_113[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_112_data = _raw_hazard_mulpre_mul_raw_haz_T_280; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_281 = _raw_hazard_mulpre_mul_raw_haz_WIRE_113[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_112_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_281; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_282 = _raw_hazard_mulpre_mul_raw_haz_WIRE_113[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_112_garbage = _raw_hazard_mulpre_mul_raw_haz_T_282; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_283 = _raw_hazard_mulpre_mul_raw_haz_WIRE_113[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_114 = _raw_hazard_mulpre_mul_raw_haz_T_283; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_115 = _raw_hazard_mulpre_mul_raw_haz_WIRE_114; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_112_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_115; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_284 = _raw_hazard_mulpre_mul_raw_haz_WIRE_113[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_112_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_284; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_285 = _raw_hazard_mulpre_mul_raw_haz_WIRE_113[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_112_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_285; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_286 = _raw_hazard_mulpre_mul_raw_haz_WIRE_113[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_112_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_286; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_287 = _mesh_io_tags_in_progress_14_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_112_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_288 = _mesh_io_tags_in_progress_14_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_112_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_289 = _raw_hazard_mulpre_mul_raw_haz_T_287 & _raw_hazard_mulpre_mul_raw_haz_T_288; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_296; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_295; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_294; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_119; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_292; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_291; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_290; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_290 = _raw_hazard_mulpre_mul_raw_haz_WIRE_117[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_116_data = _raw_hazard_mulpre_mul_raw_haz_T_290; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_291 = _raw_hazard_mulpre_mul_raw_haz_WIRE_117[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_116_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_291; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_292 = _raw_hazard_mulpre_mul_raw_haz_WIRE_117[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_116_garbage = _raw_hazard_mulpre_mul_raw_haz_T_292; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_293 = _raw_hazard_mulpre_mul_raw_haz_WIRE_117[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_118 = _raw_hazard_mulpre_mul_raw_haz_T_293; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_119 = _raw_hazard_mulpre_mul_raw_haz_WIRE_118; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_116_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_119; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_294 = _raw_hazard_mulpre_mul_raw_haz_WIRE_117[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_116_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_294; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_295 = _raw_hazard_mulpre_mul_raw_haz_WIRE_117[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_116_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_295; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_296 = _raw_hazard_mulpre_mul_raw_haz_WIRE_117[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_116_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_296; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_297 = _mesh_io_tags_in_progress_14_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_116_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_298 = _mesh_io_tags_in_progress_14_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_116_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_299 = _raw_hazard_mulpre_mul_raw_haz_T_297 & _raw_hazard_mulpre_mul_raw_haz_T_298; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz_14 = _raw_hazard_mulpre_mul_raw_haz_T_289 | _raw_hazard_mulpre_mul_raw_haz_T_299; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_70 = ~raw_hazard_mulpre_is_garbage_14; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_71 = raw_hazard_mulpre_mul_raw_haz_14 | raw_hazard_mulpre_pre_raw_haz_14; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_72 = _raw_hazard_mulpre_T_70 & _raw_hazard_mulpre_T_71; // @[ExecuteController.scala:225:{5,17,33}]
wire _raw_hazard_mulpre_T_74 = _raw_hazard_mulpre_T_72; // @[ExecuteController.scala:225:{17,49}]
wire _raw_hazard_mulpre_is_garbage_T_76 = _raw_hazard_mulpre_is_garbage_T_75 & _mesh_io_tags_in_progress_15_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_77 = &_mesh_io_tags_in_progress_15_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_78 = _raw_hazard_mulpre_is_garbage_T_76 & _raw_hazard_mulpre_is_garbage_T_77; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_79; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage_15 = _raw_hazard_mulpre_is_garbage_T_78 & _raw_hazard_mulpre_is_garbage_T_79; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_141; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_140; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_139; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_63; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_137; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_136; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T_135; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_135 = _raw_hazard_mulpre_pre_raw_haz_WIRE_61[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_60_data = _raw_hazard_mulpre_pre_raw_haz_T_135; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_136 = _raw_hazard_mulpre_pre_raw_haz_WIRE_61[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_60_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_136; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_137 = _raw_hazard_mulpre_pre_raw_haz_WIRE_61[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_60_garbage = _raw_hazard_mulpre_pre_raw_haz_T_137; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_138 = _raw_hazard_mulpre_pre_raw_haz_WIRE_61[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_62 = _raw_hazard_mulpre_pre_raw_haz_T_138; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_63 = _raw_hazard_mulpre_pre_raw_haz_WIRE_62; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_60_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_63; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_139 = _raw_hazard_mulpre_pre_raw_haz_WIRE_61[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_60_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_139; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_140 = _raw_hazard_mulpre_pre_raw_haz_WIRE_61[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_60_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_140; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_141 = _raw_hazard_mulpre_pre_raw_haz_WIRE_61[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_60_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_141; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_142 = _mesh_io_tags_in_progress_15_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_60_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_143 = _mesh_io_tags_in_progress_15_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_60_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz_15 = _raw_hazard_mulpre_pre_raw_haz_T_142 & _raw_hazard_mulpre_pre_raw_haz_T_143; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_306; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_305; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_304; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_123; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_302; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_301; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_300; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_300 = _raw_hazard_mulpre_mul_raw_haz_WIRE_121[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_120_data = _raw_hazard_mulpre_mul_raw_haz_T_300; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_301 = _raw_hazard_mulpre_mul_raw_haz_WIRE_121[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_120_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_301; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_302 = _raw_hazard_mulpre_mul_raw_haz_WIRE_121[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_120_garbage = _raw_hazard_mulpre_mul_raw_haz_T_302; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_303 = _raw_hazard_mulpre_mul_raw_haz_WIRE_121[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_122 = _raw_hazard_mulpre_mul_raw_haz_T_303; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_123 = _raw_hazard_mulpre_mul_raw_haz_WIRE_122; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_120_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_123; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_304 = _raw_hazard_mulpre_mul_raw_haz_WIRE_121[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_120_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_304; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_305 = _raw_hazard_mulpre_mul_raw_haz_WIRE_121[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_120_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_305; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_306 = _raw_hazard_mulpre_mul_raw_haz_WIRE_121[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_120_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_306; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_307 = _mesh_io_tags_in_progress_15_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_120_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_308 = _mesh_io_tags_in_progress_15_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_120_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_309 = _raw_hazard_mulpre_mul_raw_haz_T_307 & _raw_hazard_mulpre_mul_raw_haz_T_308; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_316; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_315; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_314; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_127; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_312; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_311; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_310; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_310 = _raw_hazard_mulpre_mul_raw_haz_WIRE_125[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_124_data = _raw_hazard_mulpre_mul_raw_haz_T_310; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_311 = _raw_hazard_mulpre_mul_raw_haz_WIRE_125[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_124_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_311; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_312 = _raw_hazard_mulpre_mul_raw_haz_WIRE_125[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_124_garbage = _raw_hazard_mulpre_mul_raw_haz_T_312; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_313 = _raw_hazard_mulpre_mul_raw_haz_WIRE_125[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_126 = _raw_hazard_mulpre_mul_raw_haz_T_313; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_127 = _raw_hazard_mulpre_mul_raw_haz_WIRE_126; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_124_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_127; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_314 = _raw_hazard_mulpre_mul_raw_haz_WIRE_125[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_124_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_314; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_315 = _raw_hazard_mulpre_mul_raw_haz_WIRE_125[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_124_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_315; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_316 = _raw_hazard_mulpre_mul_raw_haz_WIRE_125[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_124_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_316; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_317 = _mesh_io_tags_in_progress_15_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_124_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_318 = _mesh_io_tags_in_progress_15_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_124_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_319 = _raw_hazard_mulpre_mul_raw_haz_T_317 & _raw_hazard_mulpre_mul_raw_haz_T_318; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz_15 = _raw_hazard_mulpre_mul_raw_haz_T_309 | _raw_hazard_mulpre_mul_raw_haz_T_319; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_75 = ~raw_hazard_mulpre_is_garbage_15; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_76 = raw_hazard_mulpre_mul_raw_haz_15 | raw_hazard_mulpre_pre_raw_haz_15; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_77 = _raw_hazard_mulpre_T_75 & _raw_hazard_mulpre_T_76; // @[ExecuteController.scala:225:{5,17,33}]
wire _raw_hazard_mulpre_T_79 = _raw_hazard_mulpre_T_77; // @[ExecuteController.scala:225:{17,49}]
wire _raw_hazard_mulpre_T_80 = _raw_hazard_mulpre_T_4 | _raw_hazard_mulpre_T_9; // @[ExecuteController.scala:225:49, :226:14]
wire _raw_hazard_mulpre_T_81 = _raw_hazard_mulpre_T_80 | _raw_hazard_mulpre_T_14; // @[ExecuteController.scala:225:49, :226:14]
wire _raw_hazard_mulpre_T_82 = _raw_hazard_mulpre_T_81 | _raw_hazard_mulpre_T_19; // @[ExecuteController.scala:225:49, :226:14]
wire _raw_hazard_mulpre_T_83 = _raw_hazard_mulpre_T_82 | _raw_hazard_mulpre_T_24; // @[ExecuteController.scala:225:49, :226:14]
wire _raw_hazard_mulpre_T_84 = _raw_hazard_mulpre_T_83 | _raw_hazard_mulpre_T_29; // @[ExecuteController.scala:225:49, :226:14]
wire _raw_hazard_mulpre_T_85 = _raw_hazard_mulpre_T_84 | _raw_hazard_mulpre_T_34; // @[ExecuteController.scala:225:49, :226:14]
wire _raw_hazard_mulpre_T_86 = _raw_hazard_mulpre_T_85 | _raw_hazard_mulpre_T_39; // @[ExecuteController.scala:225:49, :226:14]
wire _raw_hazard_mulpre_T_87 = _raw_hazard_mulpre_T_86 | _raw_hazard_mulpre_T_44; // @[ExecuteController.scala:225:49, :226:14]
wire _raw_hazard_mulpre_T_88 = _raw_hazard_mulpre_T_87 | _raw_hazard_mulpre_T_49; // @[ExecuteController.scala:225:49, :226:14]
wire _raw_hazard_mulpre_T_89 = _raw_hazard_mulpre_T_88 | _raw_hazard_mulpre_T_54; // @[ExecuteController.scala:225:49, :226:14]
wire _raw_hazard_mulpre_T_90 = _raw_hazard_mulpre_T_89 | _raw_hazard_mulpre_T_59; // @[ExecuteController.scala:225:49, :226:14]
wire _raw_hazard_mulpre_T_91 = _raw_hazard_mulpre_T_90 | _raw_hazard_mulpre_T_64; // @[ExecuteController.scala:225:49, :226:14]
wire _raw_hazard_mulpre_T_92 = _raw_hazard_mulpre_T_91 | _raw_hazard_mulpre_T_69; // @[ExecuteController.scala:225:49, :226:14]
wire _raw_hazard_mulpre_T_93 = _raw_hazard_mulpre_T_92 | _raw_hazard_mulpre_T_74; // @[ExecuteController.scala:225:49, :226:14]
wire raw_hazard_mulpre = _raw_hazard_mulpre_T_93 | _raw_hazard_mulpre_T_79; // @[ExecuteController.scala:225:49, :226:14]
wire _third_instruction_needed_T = a_address_place[1]; // @[ExecuteController.scala:124:28, :228:50]
wire _third_instruction_needed_T_1 = b_address_place[1]; // @[ExecuteController.scala:127:28, :228:75]
wire _third_instruction_needed_T_2 = _third_instruction_needed_T | _third_instruction_needed_T_1; // @[ExecuteController.scala:228:{50,56,75}]
wire _third_instruction_needed_T_4 = _third_instruction_needed_T_2; // @[ExecuteController.scala:228:{56,81}]
wire _matmul_in_progress_T = _mesh_io_tags_in_progress_0_rob_id_valid | _mesh_io_tags_in_progress_1_rob_id_valid; // @[ExecuteController.scala:186:20, :230:82]
wire _matmul_in_progress_T_1 = _matmul_in_progress_T | _mesh_io_tags_in_progress_2_rob_id_valid; // @[ExecuteController.scala:186:20, :230:82]
wire _matmul_in_progress_T_2 = _matmul_in_progress_T_1 | _mesh_io_tags_in_progress_3_rob_id_valid; // @[ExecuteController.scala:186:20, :230:82]
wire _matmul_in_progress_T_3 = _matmul_in_progress_T_2 | _mesh_io_tags_in_progress_4_rob_id_valid; // @[ExecuteController.scala:186:20, :230:82]
wire _matmul_in_progress_T_4 = _matmul_in_progress_T_3 | _mesh_io_tags_in_progress_5_rob_id_valid; // @[ExecuteController.scala:186:20, :230:82]
wire _matmul_in_progress_T_5 = _matmul_in_progress_T_4 | _mesh_io_tags_in_progress_6_rob_id_valid; // @[ExecuteController.scala:186:20, :230:82]
wire _matmul_in_progress_T_6 = _matmul_in_progress_T_5 | _mesh_io_tags_in_progress_7_rob_id_valid; // @[ExecuteController.scala:186:20, :230:82]
wire _matmul_in_progress_T_7 = _matmul_in_progress_T_6 | _mesh_io_tags_in_progress_8_rob_id_valid; // @[ExecuteController.scala:186:20, :230:82]
wire _matmul_in_progress_T_8 = _matmul_in_progress_T_7 | _mesh_io_tags_in_progress_9_rob_id_valid; // @[ExecuteController.scala:186:20, :230:82]
wire _matmul_in_progress_T_9 = _matmul_in_progress_T_8 | _mesh_io_tags_in_progress_10_rob_id_valid; // @[ExecuteController.scala:186:20, :230:82]
wire _matmul_in_progress_T_10 = _matmul_in_progress_T_9 | _mesh_io_tags_in_progress_11_rob_id_valid; // @[ExecuteController.scala:186:20, :230:82]
wire _matmul_in_progress_T_11 = _matmul_in_progress_T_10 | _mesh_io_tags_in_progress_12_rob_id_valid; // @[ExecuteController.scala:186:20, :230:82]
wire _matmul_in_progress_T_12 = _matmul_in_progress_T_11 | _mesh_io_tags_in_progress_13_rob_id_valid; // @[ExecuteController.scala:186:20, :230:82]
wire _matmul_in_progress_T_13 = _matmul_in_progress_T_12 | _mesh_io_tags_in_progress_14_rob_id_valid; // @[ExecuteController.scala:186:20, :230:82]
wire matmul_in_progress = _matmul_in_progress_T_13 | _mesh_io_tags_in_progress_15_rob_id_valid; // @[ExecuteController.scala:186:20, :230:82]
assign _io_busy_T = _cmd_q_io_deq_valid_0 | matmul_in_progress; // @[MultiHeadedQueue.scala:53:19]
assign io_busy_0 = _io_busy_T; // @[ExecuteController.scala:12:7, :232:27]
reg [1:0] a_fire_counter; // @[ExecuteController.scala:236:27]
reg [1:0] b_fire_counter; // @[ExecuteController.scala:237:27]
reg [1:0] d_fire_counter; // @[ExecuteController.scala:238:27]
reg a_fire_started; // @[ExecuteController.scala:240:31]
reg d_fire_started; // @[ExecuteController.scala:241:31]
reg b_fire_started; // @[ExecuteController.scala:242:31]
reg [17:0] a_addr_offset; // @[ExecuteController.scala:245:26]
reg [15:0] a_addr_stride; // @[ExecuteController.scala:246:26]
reg [15:0] c_addr_stride; // @[ExecuteController.scala:249:26]
wire [13:0] a_address_data; // @[LocalAddr.scala:50:26]
wire [18:0] _GEN_21 = {1'h0, a_addr_offset}; // @[LocalAddr.scala:51:25]
wire [18:0] _a_address_result_data_T = {5'h0, a_address_rs1_data} + _GEN_21; // @[LocalAddr.scala:51:25]
wire [17:0] _a_address_result_data_T_1 = _a_address_result_data_T[17:0]; // @[LocalAddr.scala:51:25]
assign a_address_data = _a_address_result_data_T_1[13:0]; // @[LocalAddr.scala:50:26, :51:{17,25}]
wire [13:0] _b_address_result_data_T_1; // @[LocalAddr.scala:51:25]
wire [13:0] b_address_data; // @[LocalAddr.scala:50:26]
wire [14:0] _b_address_result_data_T = {1'h0, b_address_rs2_data} + {13'h0, b_fire_counter}; // @[LocalAddr.scala:51:25]
assign _b_address_result_data_T_1 = _b_address_result_data_T[13:0]; // @[LocalAddr.scala:51:25]
assign b_address_data = _b_address_result_data_T_1; // @[LocalAddr.scala:50:26, :51:25]
wire [3:0] _GEN_22 = {2'h0, d_fire_counter}; // @[ExecuteController.scala:238:27, :253:55]
wire [3:0] _GEN_23 = 4'h3 - _GEN_22; // @[ExecuteController.scala:253:55]
wire [3:0] _d_address_T_2; // @[ExecuteController.scala:253:55]
assign _d_address_T_2 = _GEN_23; // @[ExecuteController.scala:253:55]
wire [3:0] _d_row_is_not_all_zeros_T_2; // @[ExecuteController.scala:312:51]
assign _d_row_is_not_all_zeros_T_2 = _GEN_23; // @[ExecuteController.scala:253:55, :312:51]
wire [2:0] _d_address_T_3 = _d_address_T_2[2:0]; // @[ExecuteController.scala:253:55]
wire [13:0] _d_address_result_data_T_1; // @[LocalAddr.scala:51:25]
wire [13:0] d_address_data; // @[LocalAddr.scala:50:26]
wire [14:0] _d_address_result_data_T = {1'h0, d_address_rs1_data} + {12'h0, _d_address_T_3}; // @[LocalAddr.scala:51:25]
assign _d_address_result_data_T_1 = _d_address_result_data_T[13:0]; // @[LocalAddr.scala:51:25]
assign d_address_data = _d_address_result_data_T_1; // @[LocalAddr.scala:50:26, :51:25]
wire [1:0] dataAbank = a_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_7 = a_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_19 = a_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_32 = a_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_56 = a_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] dataBbank = b_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_8 = b_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_31 = b_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_43 = b_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_68 = b_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] dataDbank = d_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_20 = d_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_44 = d_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_55 = d_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_67 = d_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
assign io_im2col_req_bits_start_inputting_0 = start_inputting_a; // @[ExecuteController.scala:12:7, :267:35]
wire start_inputting_b; // @[ExecuteController.scala:268:35]
wire start_inputting_d; // @[ExecuteController.scala:269:35]
wire start_array_outputting; // @[ExecuteController.scala:270:40]
wire _a_garbage_T_1 = _a_garbage_T & a_address_rs1_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _a_garbage_T_2 = &a_address_rs1_data; // @[LocalAddr.scala:43:91]
wire _a_garbage_T_3 = _a_garbage_T_1 & _a_garbage_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire _a_garbage_T_5 = _a_garbage_T_3 & _a_garbage_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _a_garbage_T_6 = ~start_inputting_a; // @[ExecuteController.scala:267:35, :272:49]
wire a_garbage = _a_garbage_T_5 | _a_garbage_T_6; // @[LocalAddr.scala:43:96]
wire _b_garbage_T_1 = _b_garbage_T & b_address_rs2_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _b_garbage_T_2 = &b_address_rs2_data; // @[LocalAddr.scala:43:91]
wire _b_garbage_T_3 = _b_garbage_T_1 & _b_garbage_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire _b_garbage_T_5 = _b_garbage_T_3 & _b_garbage_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _b_garbage_T_6 = ~start_inputting_b; // @[ExecuteController.scala:268:35, :273:49]
wire b_garbage = _b_garbage_T_5 | _b_garbage_T_6; // @[LocalAddr.scala:43:96]
wire _d_garbage_T_1 = _d_garbage_T & d_address_rs1_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _d_garbage_T_2 = &d_address_rs1_data; // @[LocalAddr.scala:43:91]
wire _d_garbage_T_3 = _d_garbage_T_1 & _d_garbage_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire _d_garbage_T_5 = _d_garbage_T_3 & _d_garbage_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _d_garbage_T_6 = ~start_inputting_d; // @[ExecuteController.scala:269:35, :274:49]
wire d_garbage = _d_garbage_T_5 | _d_garbage_T_6; // @[LocalAddr.scala:43:96]
reg perform_single_preload; // @[ExecuteController.scala:277:39]
reg perform_single_mul; // @[ExecuteController.scala:278:35]
reg perform_mul_pre; // @[ExecuteController.scala:279:32]
wire _T_200 = control_state == 2'h1; // @[ExecuteController.scala:74:30, :281:84]
assign io_counter_event_signal_24_0 = _T_200; // @[ExecuteController.scala:12:7, :281:84]
wire _performing_single_preload_T; // @[ExecuteController.scala:281:84]
assign _performing_single_preload_T = _T_200; // @[ExecuteController.scala:281:84]
wire _performing_single_mul_T; // @[ExecuteController.scala:282:76]
assign _performing_single_mul_T = _T_200; // @[ExecuteController.scala:281:84, :282:76]
wire _performing_mul_pre_T; // @[ExecuteController.scala:283:70]
assign _performing_mul_pre_T = _T_200; // @[ExecuteController.scala:281:84, :283:70]
wire _performing_single_preload_T_1 = perform_single_preload & _performing_single_preload_T; // @[ExecuteController.scala:277:39, :281:{67,84}]
wire performing_single_preload; // @[ExecuteController.scala:281:43]
wire _performing_single_mul_T_1 = perform_single_mul & _performing_single_mul_T; // @[ExecuteController.scala:278:35, :282:{59,76}]
wire performing_single_mul; // @[ExecuteController.scala:282:39]
wire _performing_mul_pre_T_1 = perform_mul_pre & _performing_mul_pre_T; // @[ExecuteController.scala:279:32, :283:{53,70}]
wire performing_mul_pre; // @[ExecuteController.scala:283:36]
wire [2:0] total_rows; // @[ExecuteController.scala:285:28]
wire [2:0] rows_a = a_garbage ? 3'h1 : a_rows; // @[ExecuteController.scala:162:19, :272:46, :290:21]
wire [2:0] rows_b = b_garbage ? 3'h1 : b_rows; // @[ExecuteController.scala:164:19, :273:46, :291:21]
wire _total_rows_T = rows_a > rows_b; // @[Util.scala:100:12]
wire [2:0] _total_rows_T_1 = _total_rows_T ? rows_a : rows_b; // @[Util.scala:100:{8,12}]
wire _total_rows_T_2 = _total_rows_T_1 > 3'h4; // @[Util.scala:100:{8,12}]
wire [2:0] _total_rows_T_3 = _total_rows_T_2 ? _total_rows_T_1 : 3'h4; // @[Util.scala:100:{8,12}]
assign total_rows = current_dataflow & d_garbage & ~a_should_be_fed_into_transposer & ~b_should_be_fed_into_transposer & ~d_should_be_fed_into_transposer ? _total_rows_T_3 : 3'h4; // @[Util.scala:100:8]
reg [2:0] mul_pre_counter_sub; // @[ExecuteController.scala:305:36]
reg [2:0] mul_pre_counter_count; // @[ExecuteController.scala:306:38]
reg mul_pre_counter_lock; // @[ExecuteController.scala:307:37]
wire [2:0] _GEN_24 = {1'h0, a_fire_counter}; // @[ExecuteController.scala:236:27, :310:47]
wire a_row_is_not_all_zeros = _GEN_24 < a_rows; // @[ExecuteController.scala:162:19, :310:47]
wire [2:0] _GEN_25 = {1'h0, b_fire_counter}; // @[ExecuteController.scala:237:27, :311:47]
wire b_row_is_not_all_zeros = _GEN_25 < b_rows; // @[ExecuteController.scala:164:19, :311:47]
wire [2:0] _d_row_is_not_all_zeros_T_3 = _d_row_is_not_all_zeros_T_2[2:0]; // @[ExecuteController.scala:312:51]
wire d_row_is_not_all_zeros = _d_row_is_not_all_zeros_T_3 < d_rows; // @[ExecuteController.scala:166:19, :312:{51,68}]
wire a_ready; // @[ExecuteController.scala:329:25]
wire b_ready; // @[ExecuteController.scala:330:25]
wire d_ready; // @[ExecuteController.scala:331:25]
wire _T_22 = _T_17 & a_address_rs1_read_full_acc_row & (&a_address_rs1_data) & a_address_rs1_garbage_bit; // @[LocalAddr.scala:43:{48,62,83,91,96}]
wire _GEN_26 = a_fire_counter == 2'h0; // @[ExecuteController.scala:236:27, :334:24]
wire _done_T; // @[ExecuteController.scala:334:24]
assign _done_T = _GEN_26; // @[ExecuteController.scala:334:24]
wire _about_to_fire_all_rows_T_4; // @[ExecuteController.scala:405:99]
assign _about_to_fire_all_rows_T_4 = _GEN_26; // @[ExecuteController.scala:334:24, :405:99]
wire done = _done_T & a_fire_started; // @[ExecuteController.scala:240:31, :334:{24,32}]
wire _T_28 = _T_23 & b_address_rs2_read_full_acc_row & (&b_address_rs2_data) & b_address_rs2_garbage_bit; // @[LocalAddr.scala:43:{48,62,83,91,96}]
wire _GEN_27 = b_fire_counter == 2'h0; // @[ExecuteController.scala:237:27, :334:24]
wire _done_T_1; // @[ExecuteController.scala:334:24]
assign _done_T_1 = _GEN_27; // @[ExecuteController.scala:334:24]
wire _about_to_fire_all_rows_T_10; // @[ExecuteController.scala:406:72]
assign _about_to_fire_all_rows_T_10 = _GEN_27; // @[ExecuteController.scala:334:24, :406:72]
wire done_1 = _done_T_1 & b_fire_started; // @[ExecuteController.scala:242:31, :334:{24,32}]
wire _T_34 = _T_29 & d_address_rs1_read_full_acc_row & (&d_address_rs1_data) & d_address_rs1_garbage_bit; // @[LocalAddr.scala:43:{48,62,83,91,96}]
wire _GEN_28 = d_fire_counter == 2'h0; // @[ExecuteController.scala:238:27, :334:24]
wire _done_T_2; // @[ExecuteController.scala:334:24]
assign _done_T_2 = _GEN_28; // @[ExecuteController.scala:334:24]
wire _about_to_fire_all_rows_T_17; // @[ExecuteController.scala:407:72]
assign _about_to_fire_all_rows_T_17 = _GEN_28; // @[ExecuteController.scala:334:24, :407:72]
wire done_2 = _done_T_2 & d_fire_started; // @[ExecuteController.scala:241:31, :334:{24,32}]
wire _GEN_29 = _T_22 | _T_28; // @[LocalAddr.scala:43:{62,83,96}]
wire _same_banks_is_garbage_T; // @[ExecuteController.scala:320:34]
assign _same_banks_is_garbage_T = _GEN_29; // @[ExecuteController.scala:320:34]
wire _same_banks_is_garbage_T_8; // @[ExecuteController.scala:320:34]
assign _same_banks_is_garbage_T_8 = _GEN_29; // @[ExecuteController.scala:320:34]
wire _same_banks_is_garbage_T_1 = ~start_inputting_a; // @[ExecuteController.scala:267:35, :272:49, :321:7]
wire _same_banks_is_garbage_T_2 = _same_banks_is_garbage_T | _same_banks_is_garbage_T_1; // @[ExecuteController.scala:320:{34,49}, :321:7]
wire _same_banks_is_garbage_T_3 = ~start_inputting_b; // @[ExecuteController.scala:268:35, :273:49, :321:28]
wire same_banks_is_garbage = _same_banks_is_garbage_T_2 | _same_banks_is_garbage_T_3; // @[ExecuteController.scala:320:49, :321:{25,28}]
wire _same_banks_T = ~same_banks_is_garbage; // @[ExecuteController.scala:321:25, :325:5]
wire _same_banks_T_2 = _same_banks_T; // @[ExecuteController.scala:325:{5,17}]
wire _GEN_30 = a_address_is_acc_addr & b_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_3; // @[ExecuteController.scala:325:65]
assign _same_banks_T_3 = _GEN_30; // @[ExecuteController.scala:325:65]
wire _same_banks_T_27; // @[ExecuteController.scala:325:65]
assign _same_banks_T_27 = _GEN_30; // @[ExecuteController.scala:325:65]
wire _same_banks_T_4 = ~a_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_5 = ~b_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_6 = _same_banks_T_4 & _same_banks_T_5; // @[ExecuteController.scala:326:{8,29,32}]
wire _same_banks_T_9 = _same_banks_T_7 == _same_banks_T_8; // @[LocalAddr.scala:33:79]
wire _same_banks_T_10 = _same_banks_T_6 & _same_banks_T_9; // @[ExecuteController.scala:326:{29,53,72}]
wire _same_banks_T_11 = _same_banks_T_3 | _same_banks_T_10; // @[ExecuteController.scala:325:{65,89}, :326:53]
wire same_banks_0 = _same_banks_T_2 & _same_banks_T_11; // @[ExecuteController.scala:325:{17,40,89}]
wire _GEN_31 = _T_22 | _T_34; // @[LocalAddr.scala:43:{62,83,96}]
wire _same_banks_is_garbage_T_4; // @[ExecuteController.scala:320:34]
assign _same_banks_is_garbage_T_4 = _GEN_31; // @[ExecuteController.scala:320:34]
wire _same_banks_is_garbage_T_16; // @[ExecuteController.scala:320:34]
assign _same_banks_is_garbage_T_16 = _GEN_31; // @[ExecuteController.scala:320:34]
wire _same_banks_is_garbage_T_5 = ~start_inputting_a; // @[ExecuteController.scala:267:35, :272:49, :321:7]
wire _same_banks_is_garbage_T_6 = _same_banks_is_garbage_T_4 | _same_banks_is_garbage_T_5; // @[ExecuteController.scala:320:{34,49}, :321:7]
wire _same_banks_is_garbage_T_7 = ~start_inputting_d; // @[ExecuteController.scala:269:35, :274:49, :321:28]
wire same_banks_is_garbage_1 = _same_banks_is_garbage_T_6 | _same_banks_is_garbage_T_7; // @[ExecuteController.scala:320:49, :321:{25,28}]
wire _same_banks_T_12 = ~same_banks_is_garbage_1; // @[ExecuteController.scala:321:25, :325:5]
wire _same_banks_T_14 = _same_banks_T_12; // @[ExecuteController.scala:325:{5,17}]
wire _GEN_32 = a_address_is_acc_addr & d_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_15; // @[ExecuteController.scala:325:65]
assign _same_banks_T_15 = _GEN_32; // @[ExecuteController.scala:325:65]
wire _same_banks_T_51; // @[ExecuteController.scala:325:65]
assign _same_banks_T_51 = _GEN_32; // @[ExecuteController.scala:325:65]
wire _same_banks_T_16 = ~a_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_17 = ~d_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_18 = _same_banks_T_16 & _same_banks_T_17; // @[ExecuteController.scala:326:{8,29,32}]
wire _same_banks_T_21 = _same_banks_T_19 == _same_banks_T_20; // @[LocalAddr.scala:33:79]
wire _same_banks_T_22 = _same_banks_T_18 & _same_banks_T_21; // @[ExecuteController.scala:326:{29,53,72}]
wire _same_banks_T_23 = _same_banks_T_15 | _same_banks_T_22; // @[ExecuteController.scala:325:{65,89}, :326:53]
wire same_banks_1 = _same_banks_T_14 & _same_banks_T_23; // @[ExecuteController.scala:325:{17,40,89}]
wire _GEN_33 = a_fire_started == b_fire_started; // @[ExecuteController.scala:240:31, :242:31, :345:48]
wire _same_counter_T; // @[ExecuteController.scala:345:48]
assign _same_counter_T = _GEN_33; // @[ExecuteController.scala:345:48]
wire _same_counter_T_4; // @[ExecuteController.scala:345:48]
assign _same_counter_T_4 = _GEN_33; // @[ExecuteController.scala:345:48]
wire _GEN_34 = a_fire_counter == b_fire_counter; // @[ExecuteController.scala:236:27, :237:27, :345:73]
wire _same_counter_T_1; // @[ExecuteController.scala:345:73]
assign _same_counter_T_1 = _GEN_34; // @[ExecuteController.scala:345:73]
wire _same_counter_T_5; // @[ExecuteController.scala:345:73]
assign _same_counter_T_5 = _GEN_34; // @[ExecuteController.scala:345:73]
wire same_counter_0 = _same_counter_T & _same_counter_T_1; // @[ExecuteController.scala:345:{48,62,73}]
wire _GEN_35 = a_fire_started == d_fire_started; // @[ExecuteController.scala:240:31, :241:31, :345:48]
wire _same_counter_T_2; // @[ExecuteController.scala:345:48]
assign _same_counter_T_2 = _GEN_35; // @[ExecuteController.scala:345:48]
wire _same_counter_T_8; // @[ExecuteController.scala:345:48]
assign _same_counter_T_8 = _GEN_35; // @[ExecuteController.scala:345:48]
wire _GEN_36 = a_fire_counter == d_fire_counter; // @[ExecuteController.scala:236:27, :238:27, :345:73]
wire _same_counter_T_3; // @[ExecuteController.scala:345:73]
assign _same_counter_T_3 = _GEN_36; // @[ExecuteController.scala:345:73]
wire _same_counter_T_9; // @[ExecuteController.scala:345:73]
assign _same_counter_T_9 = _GEN_36; // @[ExecuteController.scala:345:73]
wire same_counter_1 = _same_counter_T_2 & _same_counter_T_3; // @[ExecuteController.scala:345:{48,62,73}]
wire [3:0] _GEN_37 = {1'h0, total_rows} - 4'h1; // @[Util.scala:18:28]
wire [3:0] _one_ahead_max_T; // @[Util.scala:18:28]
assign _one_ahead_max_T = _GEN_37; // @[Util.scala:18:28]
wire [3:0] _one_ahead_max_T_1; // @[Util.scala:18:28]
assign _one_ahead_max_T_1 = _GEN_37; // @[Util.scala:18:28]
wire [3:0] _one_ahead_max_T_2; // @[Util.scala:18:28]
assign _one_ahead_max_T_2 = _GEN_37; // @[Util.scala:18:28]
wire [3:0] _one_ahead_max_T_3; // @[Util.scala:18:28]
assign _one_ahead_max_T_3 = _GEN_37; // @[Util.scala:18:28]
wire [3:0] _one_ahead_max_T_4; // @[Util.scala:18:28]
assign _one_ahead_max_T_4 = _GEN_37; // @[Util.scala:18:28]
wire [3:0] _one_ahead_max_T_5; // @[Util.scala:18:28]
assign _one_ahead_max_T_5 = _GEN_37; // @[Util.scala:18:28]
wire [3:0] _a_fire_counter_max_T; // @[Util.scala:18:28]
assign _a_fire_counter_max_T = _GEN_37; // @[Util.scala:18:28]
wire [3:0] _a_addr_offset_T; // @[ExecuteController.scala:370:56]
assign _a_addr_offset_T = _GEN_37; // @[Util.scala:18:28]
wire [3:0] _b_fire_counter_max_T; // @[Util.scala:18:28]
assign _b_fire_counter_max_T = _GEN_37; // @[Util.scala:18:28]
wire [3:0] _d_fire_counter_max_T; // @[Util.scala:18:28]
assign _d_fire_counter_max_T = _GEN_37; // @[Util.scala:18:28]
wire [3:0] _about_to_fire_all_rows_T; // @[ExecuteController.scala:405:64]
assign _about_to_fire_all_rows_T = _GEN_37; // @[Util.scala:18:28]
wire [3:0] _about_to_fire_all_rows_T_6; // @[ExecuteController.scala:406:37]
assign _about_to_fire_all_rows_T_6 = _GEN_37; // @[Util.scala:18:28]
wire [3:0] _about_to_fire_all_rows_T_13; // @[ExecuteController.scala:407:37]
assign _about_to_fire_all_rows_T_13 = _GEN_37; // @[Util.scala:18:28]
wire [2:0] one_ahead_max = _one_ahead_max_T[2:0]; // @[Util.scala:18:28]
wire _one_ahead_T = |one_ahead_max; // @[Util.scala:18:28, :19:14]
wire _GEN_38 = one_ahead_max == 3'h0; // @[Util.scala:18:28, :19:28]
wire _one_ahead_T_1; // @[Util.scala:19:28]
assign _one_ahead_T_1 = _GEN_38; // @[Util.scala:19:28]
wire _one_ahead_T_9; // @[Util.scala:29:12]
assign _one_ahead_T_9 = _GEN_38; // @[Util.scala:19:28, :29:12]
wire _one_ahead_T_2 = _one_ahead_T | _one_ahead_T_1; // @[Util.scala:19:{14,21,28}]
wire _one_ahead_T_4 = ~_one_ahead_T_3; // @[Util.scala:19:11]
wire _one_ahead_T_5 = ~_one_ahead_T_2; // @[Util.scala:19:{11,21}]
wire [2:0] _GEN_39 = _GEN_25 + 3'h1; // @[Util.scala:27:15]
wire [2:0] _one_ahead_T_6; // @[Util.scala:27:15]
assign _one_ahead_T_6 = _GEN_39; // @[Util.scala:27:15]
wire [2:0] _one_ahead_T_141; // @[Util.scala:27:15]
assign _one_ahead_T_141 = _GEN_39; // @[Util.scala:27:15]
wire [2:0] _b_fire_counter_T_6; // @[Util.scala:27:15]
assign _b_fire_counter_T_6 = _GEN_39; // @[Util.scala:27:15]
wire [1:0] _one_ahead_T_7 = _one_ahead_T_6[1:0]; // @[Util.scala:27:15]
wire [3:0] _GEN_40 = {1'h0, one_ahead_max}; // @[Util.scala:18:28, :30:17]
wire [3:0] _one_ahead_T_10 = _GEN_40 - 4'h1; // @[Util.scala:30:17]
wire [2:0] _one_ahead_T_11 = _one_ahead_T_10[2:0]; // @[Util.scala:30:17]
wire [3:0] _one_ahead_T_12 = {1'h0, _one_ahead_T_11} + 4'h1; // @[Util.scala:30:{17,21}]
wire [2:0] _one_ahead_T_13 = _one_ahead_T_12[2:0]; // @[Util.scala:30:21]
wire _one_ahead_T_14 = _GEN_25 >= _one_ahead_T_13; // @[Util.scala:30:{10,21}]
wire _one_ahead_T_16 = _one_ahead_T_14; // @[Util.scala:30:{10,27}]
wire [3:0] _GEN_41 = {2'h0, b_fire_counter}; // @[Util.scala:30:54]
wire [3:0] _one_ahead_T_17 = _GEN_40 - _GEN_41; // @[Util.scala:30:{17,54}]
wire [2:0] _one_ahead_T_18 = _one_ahead_T_17[2:0]; // @[Util.scala:30:54]
wire [3:0] _one_ahead_T_19 = 4'h1 - {1'h0, _one_ahead_T_18}; // @[Util.scala:30:{47,54}]
wire [2:0] _one_ahead_T_20 = _one_ahead_T_19[2:0]; // @[Util.scala:30:47]
wire [3:0] _one_ahead_T_21 = {1'h0, _one_ahead_T_20} - 4'h1; // @[Util.scala:30:{47,59}]
wire [2:0] _one_ahead_T_22 = _one_ahead_T_21[2:0]; // @[Util.scala:30:59]
wire [2:0] _one_ahead_T_23 = _one_ahead_T_16 ? _one_ahead_T_22 : {1'h0, _one_ahead_T_7}; // @[Mux.scala:126:16]
wire [2:0] _one_ahead_T_24 = _one_ahead_T_9 ? 3'h0 : _one_ahead_T_23; // @[Mux.scala:126:16]
wire [2:0] _one_ahead_T_25 = _one_ahead_T_24; // @[Mux.scala:126:16]
wire _one_ahead_T_26 = _GEN_24 == _one_ahead_T_25; // @[Mux.scala:126:16]
wire one_ahead_0 = a_fire_started & _one_ahead_T_26; // @[ExecuteController.scala:240:31, :347:{45,56}]
wire must_wait_for_0 = one_ahead_0; // @[ExecuteController.scala:347:45, :353:26]
wire [2:0] one_ahead_max_1 = _one_ahead_max_T_1[2:0]; // @[Util.scala:18:28]
wire _one_ahead_T_27 = |one_ahead_max_1; // @[Util.scala:18:28, :19:14]
wire _GEN_42 = one_ahead_max_1 == 3'h0; // @[Util.scala:18:28, :19:28]
wire _one_ahead_T_28; // @[Util.scala:19:28]
assign _one_ahead_T_28 = _GEN_42; // @[Util.scala:19:28]
wire _one_ahead_T_36; // @[Util.scala:29:12]
assign _one_ahead_T_36 = _GEN_42; // @[Util.scala:19:28, :29:12]
wire _one_ahead_T_29 = _one_ahead_T_27 | _one_ahead_T_28; // @[Util.scala:19:{14,21,28}]
wire _one_ahead_T_31 = ~_one_ahead_T_30; // @[Util.scala:19:11]
wire _one_ahead_T_32 = ~_one_ahead_T_29; // @[Util.scala:19:{11,21}]
wire [2:0] d_fire_counter_mulpre = {1'h0, d_fire_counter}; // @[Util.scala:27:15]
wire [2:0] _GEN_43 = d_fire_counter_mulpre + 3'h1; // @[Util.scala:27:15]
wire [2:0] _one_ahead_T_33; // @[Util.scala:27:15]
assign _one_ahead_T_33 = _GEN_43; // @[Util.scala:27:15]
wire [2:0] _one_ahead_T_87; // @[Util.scala:27:15]
assign _one_ahead_T_87 = _GEN_43; // @[Util.scala:27:15]
wire [2:0] _d_fire_counter_T_6; // @[Util.scala:27:15]
assign _d_fire_counter_T_6 = _GEN_43; // @[Util.scala:27:15]
wire [1:0] _one_ahead_T_34 = _one_ahead_T_33[1:0]; // @[Util.scala:27:15]
wire [3:0] _GEN_44 = {1'h0, one_ahead_max_1}; // @[Util.scala:18:28, :30:17]
wire [3:0] _one_ahead_T_37 = _GEN_44 - 4'h1; // @[Util.scala:30:17]
wire [2:0] _one_ahead_T_38 = _one_ahead_T_37[2:0]; // @[Util.scala:30:17]
wire [3:0] _one_ahead_T_39 = {1'h0, _one_ahead_T_38} + 4'h1; // @[Util.scala:30:{17,21}]
wire [2:0] _one_ahead_T_40 = _one_ahead_T_39[2:0]; // @[Util.scala:30:21]
wire _one_ahead_T_41 = d_fire_counter_mulpre >= _one_ahead_T_40; // @[Util.scala:30:{10,21}]
wire _one_ahead_T_43 = _one_ahead_T_41; // @[Util.scala:30:{10,27}]
wire [3:0] _one_ahead_T_44 = _GEN_44 - _GEN_22; // @[Util.scala:30:{17,54}]
wire [2:0] _one_ahead_T_45 = _one_ahead_T_44[2:0]; // @[Util.scala:30:54]
wire [3:0] _one_ahead_T_46 = 4'h1 - {1'h0, _one_ahead_T_45}; // @[Util.scala:30:{47,54}]
wire [2:0] _one_ahead_T_47 = _one_ahead_T_46[2:0]; // @[Util.scala:30:47]
wire [3:0] _one_ahead_T_48 = {1'h0, _one_ahead_T_47} - 4'h1; // @[Util.scala:30:{47,59}]
wire [2:0] _one_ahead_T_49 = _one_ahead_T_48[2:0]; // @[Util.scala:30:59]
wire [2:0] _one_ahead_T_50 = _one_ahead_T_43 ? _one_ahead_T_49 : {1'h0, _one_ahead_T_34}; // @[Mux.scala:126:16]
wire [2:0] _one_ahead_T_51 = _one_ahead_T_36 ? 3'h0 : _one_ahead_T_50; // @[Mux.scala:126:16]
wire [2:0] _one_ahead_T_52 = _one_ahead_T_51; // @[Mux.scala:126:16]
wire _one_ahead_T_53 = _GEN_24 == _one_ahead_T_52; // @[Mux.scala:126:16]
wire one_ahead_1 = a_fire_started & _one_ahead_T_53; // @[ExecuteController.scala:240:31, :347:{45,56}]
wire must_wait_for_1 = one_ahead_1; // @[ExecuteController.scala:347:45, :353:26]
wire a_valid = ~(must_wait_for_0 | must_wait_for_1); // @[ExecuteController.scala:353:26, :356:{5,29}]
wire _same_banks_is_garbage_T_9 = ~start_inputting_b; // @[ExecuteController.scala:268:35, :273:49, :321:7]
wire _same_banks_is_garbage_T_10 = _same_banks_is_garbage_T_8 | _same_banks_is_garbage_T_9; // @[ExecuteController.scala:320:{34,49}, :321:7]
wire _same_banks_is_garbage_T_11 = ~start_inputting_a; // @[ExecuteController.scala:267:35, :272:49, :321:28]
wire same_banks_is_garbage_2 = _same_banks_is_garbage_T_10 | _same_banks_is_garbage_T_11; // @[ExecuteController.scala:320:49, :321:{25,28}]
wire _same_banks_T_24 = ~same_banks_is_garbage_2; // @[ExecuteController.scala:321:25, :325:5]
wire _same_banks_T_26 = _same_banks_T_24; // @[ExecuteController.scala:325:{5,17}]
wire _same_banks_T_28 = ~b_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_29 = ~a_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_30 = _same_banks_T_28 & _same_banks_T_29; // @[ExecuteController.scala:326:{8,29,32}]
wire _same_banks_T_33 = _same_banks_T_31 == _same_banks_T_32; // @[LocalAddr.scala:33:79]
wire _same_banks_T_34 = _same_banks_T_30 & _same_banks_T_33; // @[ExecuteController.scala:326:{29,53,72}]
wire _same_banks_T_35 = _same_banks_T_27 | _same_banks_T_34; // @[ExecuteController.scala:325:{65,89}, :326:53]
wire same_banks_0_1 = _same_banks_T_26 & _same_banks_T_35; // @[ExecuteController.scala:325:{17,40,89}]
wire _must_wait_for_T_4 = same_banks_0_1; // @[ExecuteController.scala:325:40, :353:13]
wire _GEN_45 = _T_28 | _T_34; // @[LocalAddr.scala:43:{62,83,96}]
wire _same_banks_is_garbage_T_12; // @[ExecuteController.scala:320:34]
assign _same_banks_is_garbage_T_12 = _GEN_45; // @[ExecuteController.scala:320:34]
wire _same_banks_is_garbage_T_20; // @[ExecuteController.scala:320:34]
assign _same_banks_is_garbage_T_20 = _GEN_45; // @[ExecuteController.scala:320:34]
wire _same_banks_is_garbage_T_13 = ~start_inputting_b; // @[ExecuteController.scala:268:35, :273:49, :321:7]
wire _same_banks_is_garbage_T_14 = _same_banks_is_garbage_T_12 | _same_banks_is_garbage_T_13; // @[ExecuteController.scala:320:{34,49}, :321:7]
wire _same_banks_is_garbage_T_15 = ~start_inputting_d; // @[ExecuteController.scala:269:35, :274:49, :321:28]
wire same_banks_is_garbage_3 = _same_banks_is_garbage_T_14 | _same_banks_is_garbage_T_15; // @[ExecuteController.scala:320:49, :321:{25,28}]
wire _same_banks_T_36 = ~same_banks_is_garbage_3; // @[ExecuteController.scala:321:25, :325:5]
wire _same_banks_T_38 = _same_banks_T_36; // @[ExecuteController.scala:325:{5,17}]
wire _GEN_46 = b_address_is_acc_addr & d_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_39; // @[ExecuteController.scala:325:65]
assign _same_banks_T_39 = _GEN_46; // @[ExecuteController.scala:325:65]
wire _same_banks_T_63; // @[ExecuteController.scala:325:65]
assign _same_banks_T_63 = _GEN_46; // @[ExecuteController.scala:325:65]
wire _same_banks_T_40 = ~b_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_41 = ~d_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_42 = _same_banks_T_40 & _same_banks_T_41; // @[ExecuteController.scala:326:{8,29,32}]
wire _same_banks_T_45 = _same_banks_T_43 == _same_banks_T_44; // @[LocalAddr.scala:33:79]
wire _same_banks_T_46 = _same_banks_T_42 & _same_banks_T_45; // @[ExecuteController.scala:326:{29,53,72}]
wire _same_banks_T_47 = _same_banks_T_39 | _same_banks_T_46; // @[ExecuteController.scala:325:{65,89}, :326:53]
wire same_banks_1_1 = _same_banks_T_38 & _same_banks_T_47; // @[ExecuteController.scala:325:{17,40,89}]
wire same_counter_0_1 = _same_counter_T_4 & _same_counter_T_5; // @[ExecuteController.scala:345:{48,62,73}]
wire _GEN_47 = b_fire_started == d_fire_started; // @[ExecuteController.scala:241:31, :242:31, :345:48]
wire _same_counter_T_6; // @[ExecuteController.scala:345:48]
assign _same_counter_T_6 = _GEN_47; // @[ExecuteController.scala:345:48]
wire _same_counter_T_10; // @[ExecuteController.scala:345:48]
assign _same_counter_T_10 = _GEN_47; // @[ExecuteController.scala:345:48]
wire _GEN_48 = b_fire_counter == d_fire_counter; // @[ExecuteController.scala:237:27, :238:27, :345:73]
wire _same_counter_T_7; // @[ExecuteController.scala:345:73]
assign _same_counter_T_7 = _GEN_48; // @[ExecuteController.scala:345:73]
wire _same_counter_T_11; // @[ExecuteController.scala:345:73]
assign _same_counter_T_11 = _GEN_48; // @[ExecuteController.scala:345:73]
wire same_counter_1_1 = _same_counter_T_6 & _same_counter_T_7; // @[ExecuteController.scala:345:{48,62,73}]
wire [2:0] one_ahead_max_2 = _one_ahead_max_T_2[2:0]; // @[Util.scala:18:28]
wire _one_ahead_T_54 = |one_ahead_max_2; // @[Util.scala:18:28, :19:14]
wire _GEN_49 = one_ahead_max_2 == 3'h0; // @[Util.scala:18:28, :19:28]
wire _one_ahead_T_55; // @[Util.scala:19:28]
assign _one_ahead_T_55 = _GEN_49; // @[Util.scala:19:28]
wire _one_ahead_T_63; // @[Util.scala:29:12]
assign _one_ahead_T_63 = _GEN_49; // @[Util.scala:19:28, :29:12]
wire _one_ahead_T_56 = _one_ahead_T_54 | _one_ahead_T_55; // @[Util.scala:19:{14,21,28}]
wire _one_ahead_T_58 = ~_one_ahead_T_57; // @[Util.scala:19:11]
wire _one_ahead_T_59 = ~_one_ahead_T_56; // @[Util.scala:19:{11,21}]
wire [2:0] _GEN_50 = _GEN_24 + 3'h1; // @[Util.scala:27:15]
wire [2:0] _one_ahead_T_60; // @[Util.scala:27:15]
assign _one_ahead_T_60 = _GEN_50; // @[Util.scala:27:15]
wire [2:0] _one_ahead_T_114; // @[Util.scala:27:15]
assign _one_ahead_T_114 = _GEN_50; // @[Util.scala:27:15]
wire [2:0] _a_fire_counter_T_6; // @[Util.scala:27:15]
assign _a_fire_counter_T_6 = _GEN_50; // @[Util.scala:27:15]
wire [1:0] _one_ahead_T_61 = _one_ahead_T_60[1:0]; // @[Util.scala:27:15]
wire [3:0] _GEN_51 = {1'h0, one_ahead_max_2}; // @[Util.scala:18:28, :30:17]
wire [3:0] _one_ahead_T_64 = _GEN_51 - 4'h1; // @[Util.scala:30:17]
wire [2:0] _one_ahead_T_65 = _one_ahead_T_64[2:0]; // @[Util.scala:30:17]
wire [3:0] _one_ahead_T_66 = {1'h0, _one_ahead_T_65} + 4'h1; // @[Util.scala:30:{17,21}]
wire [2:0] _one_ahead_T_67 = _one_ahead_T_66[2:0]; // @[Util.scala:30:21]
wire _one_ahead_T_68 = _GEN_24 >= _one_ahead_T_67; // @[Util.scala:30:{10,21}]
wire _one_ahead_T_70 = _one_ahead_T_68; // @[Util.scala:30:{10,27}]
wire [3:0] _GEN_52 = {2'h0, a_fire_counter}; // @[Util.scala:30:54]
wire [3:0] _one_ahead_T_71 = _GEN_51 - _GEN_52; // @[Util.scala:30:{17,54}]
wire [2:0] _one_ahead_T_72 = _one_ahead_T_71[2:0]; // @[Util.scala:30:54]
wire [3:0] _one_ahead_T_73 = 4'h1 - {1'h0, _one_ahead_T_72}; // @[Util.scala:30:{47,54}]
wire [2:0] _one_ahead_T_74 = _one_ahead_T_73[2:0]; // @[Util.scala:30:47]
wire [3:0] _one_ahead_T_75 = {1'h0, _one_ahead_T_74} - 4'h1; // @[Util.scala:30:{47,59}]
wire [2:0] _one_ahead_T_76 = _one_ahead_T_75[2:0]; // @[Util.scala:30:59]
wire [2:0] _one_ahead_T_77 = _one_ahead_T_70 ? _one_ahead_T_76 : {1'h0, _one_ahead_T_61}; // @[Mux.scala:126:16]
wire [2:0] _one_ahead_T_78 = _one_ahead_T_63 ? 3'h0 : _one_ahead_T_77; // @[Mux.scala:126:16]
wire [2:0] _one_ahead_T_79 = _one_ahead_T_78; // @[Mux.scala:126:16]
wire _one_ahead_T_80 = _GEN_25 == _one_ahead_T_79; // @[Mux.scala:126:16]
wire one_ahead_0_1 = b_fire_started & _one_ahead_T_80; // @[ExecuteController.scala:242:31, :347:{45,56}]
wire [2:0] one_ahead_max_3 = _one_ahead_max_T_3[2:0]; // @[Util.scala:18:28]
wire _one_ahead_T_81 = |one_ahead_max_3; // @[Util.scala:18:28, :19:14]
wire _GEN_53 = one_ahead_max_3 == 3'h0; // @[Util.scala:18:28, :19:28]
wire _one_ahead_T_82; // @[Util.scala:19:28]
assign _one_ahead_T_82 = _GEN_53; // @[Util.scala:19:28]
wire _one_ahead_T_90; // @[Util.scala:29:12]
assign _one_ahead_T_90 = _GEN_53; // @[Util.scala:19:28, :29:12]
wire _one_ahead_T_83 = _one_ahead_T_81 | _one_ahead_T_82; // @[Util.scala:19:{14,21,28}]
wire _one_ahead_T_85 = ~_one_ahead_T_84; // @[Util.scala:19:11]
wire _one_ahead_T_86 = ~_one_ahead_T_83; // @[Util.scala:19:{11,21}]
wire [1:0] _one_ahead_T_88 = _one_ahead_T_87[1:0]; // @[Util.scala:27:15]
wire [3:0] _GEN_54 = {1'h0, one_ahead_max_3}; // @[Util.scala:18:28, :30:17]
wire [3:0] _one_ahead_T_91 = _GEN_54 - 4'h1; // @[Util.scala:30:17]
wire [2:0] _one_ahead_T_92 = _one_ahead_T_91[2:0]; // @[Util.scala:30:17]
wire [3:0] _one_ahead_T_93 = {1'h0, _one_ahead_T_92} + 4'h1; // @[Util.scala:30:{17,21}]
wire [2:0] _one_ahead_T_94 = _one_ahead_T_93[2:0]; // @[Util.scala:30:21]
wire _one_ahead_T_95 = d_fire_counter_mulpre >= _one_ahead_T_94; // @[Util.scala:30:{10,21}]
wire _one_ahead_T_97 = _one_ahead_T_95; // @[Util.scala:30:{10,27}]
wire [3:0] _one_ahead_T_98 = _GEN_54 - _GEN_22; // @[Util.scala:30:{17,54}]
wire [2:0] _one_ahead_T_99 = _one_ahead_T_98[2:0]; // @[Util.scala:30:54]
wire [3:0] _one_ahead_T_100 = 4'h1 - {1'h0, _one_ahead_T_99}; // @[Util.scala:30:{47,54}]
wire [2:0] _one_ahead_T_101 = _one_ahead_T_100[2:0]; // @[Util.scala:30:47]
wire [3:0] _one_ahead_T_102 = {1'h0, _one_ahead_T_101} - 4'h1; // @[Util.scala:30:{47,59}]
wire [2:0] _one_ahead_T_103 = _one_ahead_T_102[2:0]; // @[Util.scala:30:59]
wire [2:0] _one_ahead_T_104 = _one_ahead_T_97 ? _one_ahead_T_103 : {1'h0, _one_ahead_T_88}; // @[Mux.scala:126:16]
wire [2:0] _one_ahead_T_105 = _one_ahead_T_90 ? 3'h0 : _one_ahead_T_104; // @[Mux.scala:126:16]
wire [2:0] _one_ahead_T_106 = _one_ahead_T_105; // @[Mux.scala:126:16]
wire _one_ahead_T_107 = _GEN_25 == _one_ahead_T_106; // @[Mux.scala:126:16]
wire one_ahead_1_1 = b_fire_started & _one_ahead_T_107; // @[ExecuteController.scala:242:31, :347:{45,56}]
wire must_wait_for_1_1 = one_ahead_1_1; // @[ExecuteController.scala:347:45, :353:26]
wire _must_wait_for_T_5 = _must_wait_for_T_4 & same_counter_0_1; // @[ExecuteController.scala:345:62, :353:{13,19}]
wire must_wait_for_0_1 = _must_wait_for_T_5 | one_ahead_0_1; // @[ExecuteController.scala:347:45, :353:{19,26}]
wire b_valid = ~(must_wait_for_0_1 | must_wait_for_1_1); // @[ExecuteController.scala:353:26, :356:{5,29}]
wire _same_banks_is_garbage_T_17 = ~start_inputting_d; // @[ExecuteController.scala:269:35, :274:49, :321:7]
wire _same_banks_is_garbage_T_18 = _same_banks_is_garbage_T_16 | _same_banks_is_garbage_T_17; // @[ExecuteController.scala:320:{34,49}, :321:7]
wire _same_banks_is_garbage_T_19 = ~start_inputting_a; // @[ExecuteController.scala:267:35, :272:49, :321:28]
wire same_banks_is_garbage_4 = _same_banks_is_garbage_T_18 | _same_banks_is_garbage_T_19; // @[ExecuteController.scala:320:49, :321:{25,28}]
wire _same_banks_T_48 = ~same_banks_is_garbage_4; // @[ExecuteController.scala:321:25, :325:5]
wire _same_banks_T_50 = _same_banks_T_48; // @[ExecuteController.scala:325:{5,17}]
wire _same_banks_T_52 = ~d_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_53 = ~a_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_54 = _same_banks_T_52 & _same_banks_T_53; // @[ExecuteController.scala:326:{8,29,32}]
wire _same_banks_T_57 = _same_banks_T_55 == _same_banks_T_56; // @[LocalAddr.scala:33:79]
wire _same_banks_T_58 = _same_banks_T_54 & _same_banks_T_57; // @[ExecuteController.scala:326:{29,53,72}]
wire _same_banks_T_59 = _same_banks_T_51 | _same_banks_T_58; // @[ExecuteController.scala:325:{65,89}, :326:53]
wire same_banks_0_2 = _same_banks_T_50 & _same_banks_T_59; // @[ExecuteController.scala:325:{17,40,89}]
wire _must_wait_for_T_8 = same_banks_0_2; // @[ExecuteController.scala:325:40, :353:13]
wire _same_banks_is_garbage_T_21 = ~start_inputting_d; // @[ExecuteController.scala:269:35, :274:49, :321:7]
wire _same_banks_is_garbage_T_22 = _same_banks_is_garbage_T_20 | _same_banks_is_garbage_T_21; // @[ExecuteController.scala:320:{34,49}, :321:7]
wire _same_banks_is_garbage_T_23 = ~start_inputting_b; // @[ExecuteController.scala:268:35, :273:49, :321:28]
wire same_banks_is_garbage_5 = _same_banks_is_garbage_T_22 | _same_banks_is_garbage_T_23; // @[ExecuteController.scala:320:49, :321:{25,28}]
wire _same_banks_T_60 = ~same_banks_is_garbage_5; // @[ExecuteController.scala:321:25, :325:5]
wire _same_banks_T_62 = _same_banks_T_60; // @[ExecuteController.scala:325:{5,17}]
wire _same_banks_T_64 = ~d_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_65 = ~b_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_66 = _same_banks_T_64 & _same_banks_T_65; // @[ExecuteController.scala:326:{8,29,32}]
wire _same_banks_T_69 = _same_banks_T_67 == _same_banks_T_68; // @[LocalAddr.scala:33:79]
wire _same_banks_T_70 = _same_banks_T_66 & _same_banks_T_69; // @[ExecuteController.scala:326:{29,53,72}]
wire _same_banks_T_71 = _same_banks_T_63 | _same_banks_T_70; // @[ExecuteController.scala:325:{65,89}, :326:53]
wire same_banks_1_2 = _same_banks_T_62 & _same_banks_T_71; // @[ExecuteController.scala:325:{17,40,89}]
wire _must_wait_for_T_10 = same_banks_1_2; // @[ExecuteController.scala:325:40, :353:13]
wire same_counter_0_2 = _same_counter_T_8 & _same_counter_T_9; // @[ExecuteController.scala:345:{48,62,73}]
wire same_counter_1_2 = _same_counter_T_10 & _same_counter_T_11; // @[ExecuteController.scala:345:{48,62,73}]
wire [2:0] one_ahead_max_4 = _one_ahead_max_T_4[2:0]; // @[Util.scala:18:28]
wire _one_ahead_T_108 = |one_ahead_max_4; // @[Util.scala:18:28, :19:14]
wire _GEN_55 = one_ahead_max_4 == 3'h0; // @[Util.scala:18:28, :19:28]
wire _one_ahead_T_109; // @[Util.scala:19:28]
assign _one_ahead_T_109 = _GEN_55; // @[Util.scala:19:28]
wire _one_ahead_T_117; // @[Util.scala:29:12]
assign _one_ahead_T_117 = _GEN_55; // @[Util.scala:19:28, :29:12]
wire _one_ahead_T_110 = _one_ahead_T_108 | _one_ahead_T_109; // @[Util.scala:19:{14,21,28}]
wire _one_ahead_T_112 = ~_one_ahead_T_111; // @[Util.scala:19:11]
wire _one_ahead_T_113 = ~_one_ahead_T_110; // @[Util.scala:19:{11,21}]
wire [1:0] _one_ahead_T_115 = _one_ahead_T_114[1:0]; // @[Util.scala:27:15]
wire [3:0] _GEN_56 = {1'h0, one_ahead_max_4}; // @[Util.scala:18:28, :30:17]
wire [3:0] _one_ahead_T_118 = _GEN_56 - 4'h1; // @[Util.scala:30:17]
wire [2:0] _one_ahead_T_119 = _one_ahead_T_118[2:0]; // @[Util.scala:30:17]
wire [3:0] _one_ahead_T_120 = {1'h0, _one_ahead_T_119} + 4'h1; // @[Util.scala:30:{17,21}]
wire [2:0] _one_ahead_T_121 = _one_ahead_T_120[2:0]; // @[Util.scala:30:21]
wire _one_ahead_T_122 = _GEN_24 >= _one_ahead_T_121; // @[Util.scala:30:{10,21}]
wire _one_ahead_T_124 = _one_ahead_T_122; // @[Util.scala:30:{10,27}]
wire [3:0] _one_ahead_T_125 = _GEN_56 - _GEN_52; // @[Util.scala:30:{17,54}]
wire [2:0] _one_ahead_T_126 = _one_ahead_T_125[2:0]; // @[Util.scala:30:54]
wire [3:0] _one_ahead_T_127 = 4'h1 - {1'h0, _one_ahead_T_126}; // @[Util.scala:30:{47,54}]
wire [2:0] _one_ahead_T_128 = _one_ahead_T_127[2:0]; // @[Util.scala:30:47]
wire [3:0] _one_ahead_T_129 = {1'h0, _one_ahead_T_128} - 4'h1; // @[Util.scala:30:{47,59}]
wire [2:0] _one_ahead_T_130 = _one_ahead_T_129[2:0]; // @[Util.scala:30:59]
wire [2:0] _one_ahead_T_131 = _one_ahead_T_124 ? _one_ahead_T_130 : {1'h0, _one_ahead_T_115}; // @[Mux.scala:126:16]
wire [2:0] _one_ahead_T_132 = _one_ahead_T_117 ? 3'h0 : _one_ahead_T_131; // @[Mux.scala:126:16]
wire [2:0] _one_ahead_T_133 = _one_ahead_T_132; // @[Mux.scala:126:16]
wire _one_ahead_T_134 = d_fire_counter_mulpre == _one_ahead_T_133; // @[Mux.scala:126:16]
wire one_ahead_0_2 = d_fire_started & _one_ahead_T_134; // @[ExecuteController.scala:241:31, :347:{45,56}]
wire [2:0] one_ahead_max_5 = _one_ahead_max_T_5[2:0]; // @[Util.scala:18:28]
wire _one_ahead_T_135 = |one_ahead_max_5; // @[Util.scala:18:28, :19:14]
wire _GEN_57 = one_ahead_max_5 == 3'h0; // @[Util.scala:18:28, :19:28]
wire _one_ahead_T_136; // @[Util.scala:19:28]
assign _one_ahead_T_136 = _GEN_57; // @[Util.scala:19:28]
wire _one_ahead_T_144; // @[Util.scala:29:12]
assign _one_ahead_T_144 = _GEN_57; // @[Util.scala:19:28, :29:12]
wire _one_ahead_T_137 = _one_ahead_T_135 | _one_ahead_T_136; // @[Util.scala:19:{14,21,28}]
wire _one_ahead_T_139 = ~_one_ahead_T_138; // @[Util.scala:19:11]
wire _one_ahead_T_140 = ~_one_ahead_T_137; // @[Util.scala:19:{11,21}]
wire [1:0] _one_ahead_T_142 = _one_ahead_T_141[1:0]; // @[Util.scala:27:15]
wire [3:0] _GEN_58 = {1'h0, one_ahead_max_5}; // @[Util.scala:18:28, :30:17]
wire [3:0] _one_ahead_T_145 = _GEN_58 - 4'h1; // @[Util.scala:30:17]
wire [2:0] _one_ahead_T_146 = _one_ahead_T_145[2:0]; // @[Util.scala:30:17]
wire [3:0] _one_ahead_T_147 = {1'h0, _one_ahead_T_146} + 4'h1; // @[Util.scala:30:{17,21}]
wire [2:0] _one_ahead_T_148 = _one_ahead_T_147[2:0]; // @[Util.scala:30:21]
wire _one_ahead_T_149 = _GEN_25 >= _one_ahead_T_148; // @[Util.scala:30:{10,21}]
wire _one_ahead_T_151 = _one_ahead_T_149; // @[Util.scala:30:{10,27}]
wire [3:0] _one_ahead_T_152 = _GEN_58 - _GEN_41; // @[Util.scala:30:{17,54}]
wire [2:0] _one_ahead_T_153 = _one_ahead_T_152[2:0]; // @[Util.scala:30:54]
wire [3:0] _one_ahead_T_154 = 4'h1 - {1'h0, _one_ahead_T_153}; // @[Util.scala:30:{47,54}]
wire [2:0] _one_ahead_T_155 = _one_ahead_T_154[2:0]; // @[Util.scala:30:47]
wire [3:0] _one_ahead_T_156 = {1'h0, _one_ahead_T_155} - 4'h1; // @[Util.scala:30:{47,59}]
wire [2:0] _one_ahead_T_157 = _one_ahead_T_156[2:0]; // @[Util.scala:30:59]
wire [2:0] _one_ahead_T_158 = _one_ahead_T_151 ? _one_ahead_T_157 : {1'h0, _one_ahead_T_142}; // @[Mux.scala:126:16]
wire [2:0] _one_ahead_T_159 = _one_ahead_T_144 ? 3'h0 : _one_ahead_T_158; // @[Mux.scala:126:16]
wire [2:0] _one_ahead_T_160 = _one_ahead_T_159; // @[Mux.scala:126:16]
wire _one_ahead_T_161 = d_fire_counter_mulpre == _one_ahead_T_160; // @[Mux.scala:126:16]
wire one_ahead_1_2 = d_fire_started & _one_ahead_T_161; // @[ExecuteController.scala:241:31, :347:{45,56}]
wire _must_wait_for_T_9 = _must_wait_for_T_8 & same_counter_0_2; // @[ExecuteController.scala:345:62, :353:{13,19}]
wire must_wait_for_0_2 = _must_wait_for_T_9 | one_ahead_0_2; // @[ExecuteController.scala:347:45, :353:{19,26}]
wire _must_wait_for_T_11 = _must_wait_for_T_10 & same_counter_1_2; // @[ExecuteController.scala:345:62, :353:{13,19}]
wire must_wait_for_1_2 = _must_wait_for_T_11 | one_ahead_1_2; // @[ExecuteController.scala:347:45, :353:{19,26}]
wire d_valid = ~(must_wait_for_0_2 | must_wait_for_1_2); // @[ExecuteController.scala:353:26, :356:{5,29}]
wire a_fire = a_valid & a_ready; // @[ExecuteController.scala:329:25, :356:5, :359:24]
wire b_fire = b_valid & b_ready; // @[ExecuteController.scala:330:25, :356:5, :360:24]
wire d_fire = d_valid & d_ready; // @[ExecuteController.scala:331:25, :356:5, :361:24]
wire _firing_T = start_inputting_a | start_inputting_b; // @[ExecuteController.scala:267:35, :268:35, :363:34]
wire firing = _firing_T | start_inputting_d; // @[ExecuteController.scala:269:35, :363:{34,55}]
wire _T_40 = firing & a_fire & _mesh_cntl_signals_q_io_enq_ready; // @[ExecuteController.scala:178:35, :359:24, :363:55, :368:{22,32}]
wire [2:0] a_fire_counter_max = _a_fire_counter_max_T[2:0]; // @[Util.scala:18:28]
wire _a_fire_counter_T = |a_fire_counter_max; // @[Util.scala:18:28, :19:14]
wire _GEN_59 = a_fire_counter_max == 3'h0; // @[Util.scala:18:28, :19:28]
wire _a_fire_counter_T_1; // @[Util.scala:19:28]
assign _a_fire_counter_T_1 = _GEN_59; // @[Util.scala:19:28]
wire _a_fire_counter_T_9; // @[Util.scala:29:12]
assign _a_fire_counter_T_9 = _GEN_59; // @[Util.scala:19:28, :29:12]
wire _a_fire_counter_T_2 = _a_fire_counter_T | _a_fire_counter_T_1; // @[Util.scala:19:{14,21,28}]
wire _a_fire_counter_T_4 = ~_a_fire_counter_T_3; // @[Util.scala:19:11]
wire _a_fire_counter_T_5 = ~_a_fire_counter_T_2; // @[Util.scala:19:{11,21}]
wire [1:0] _a_fire_counter_T_7 = _a_fire_counter_T_6[1:0]; // @[Util.scala:27:15]
wire [3:0] _GEN_60 = {1'h0, a_fire_counter_max}; // @[Util.scala:18:28, :30:17]
wire [3:0] _a_fire_counter_T_10 = _GEN_60 - 4'h1; // @[Util.scala:30:17]
wire [2:0] _a_fire_counter_T_11 = _a_fire_counter_T_10[2:0]; // @[Util.scala:30:17]
wire [3:0] _a_fire_counter_T_12 = {1'h0, _a_fire_counter_T_11} + 4'h1; // @[Util.scala:30:{17,21}]
wire [2:0] _a_fire_counter_T_13 = _a_fire_counter_T_12[2:0]; // @[Util.scala:30:21]
wire _a_fire_counter_T_14 = _GEN_24 >= _a_fire_counter_T_13; // @[Util.scala:30:{10,21}]
wire _a_fire_counter_T_16 = _a_fire_counter_T_14; // @[Util.scala:30:{10,27}]
wire [3:0] _a_fire_counter_T_17 = _GEN_60 - _GEN_52; // @[Util.scala:30:{17,54}]
wire [2:0] _a_fire_counter_T_18 = _a_fire_counter_T_17[2:0]; // @[Util.scala:30:54]
wire [3:0] _a_fire_counter_T_19 = 4'h1 - {1'h0, _a_fire_counter_T_18}; // @[Util.scala:30:{47,54}]
wire [2:0] _a_fire_counter_T_20 = _a_fire_counter_T_19[2:0]; // @[Util.scala:30:47]
wire [3:0] _a_fire_counter_T_21 = {1'h0, _a_fire_counter_T_20} - 4'h1; // @[Util.scala:30:{47,59}]
wire [2:0] _a_fire_counter_T_22 = _a_fire_counter_T_21[2:0]; // @[Util.scala:30:59]
wire [2:0] _a_fire_counter_T_23 = _a_fire_counter_T_16 ? _a_fire_counter_T_22 : {1'h0, _a_fire_counter_T_7}; // @[Mux.scala:126:16]
wire [2:0] _a_fire_counter_T_24 = _a_fire_counter_T_9 ? 3'h0 : _a_fire_counter_T_23; // @[Mux.scala:126:16]
wire [2:0] _a_fire_counter_T_25 = _a_fire_counter_T_24; // @[Mux.scala:126:16]
wire [2:0] _a_addr_offset_T_1 = _a_addr_offset_T[2:0]; // @[ExecuteController.scala:370:56]
wire _a_addr_offset_T_2 = _GEN_24 == _a_addr_offset_T_1; // @[ExecuteController.scala:310:47, :370:{41,56}]
wire [18:0] _a_addr_offset_T_3 = _GEN_21 + {3'h0, a_addr_stride}; // @[LocalAddr.scala:51:25]
wire [17:0] _a_addr_offset_T_4 = _a_addr_offset_T_3[17:0]; // @[ExecuteController.scala:370:82]
wire [17:0] _a_addr_offset_T_5 = _a_addr_offset_T_2 ? 18'h0 : _a_addr_offset_T_4; // @[ExecuteController.scala:370:{25,41,82}]
wire _T_43 = firing & b_fire & _mesh_cntl_signals_q_io_enq_ready; // @[ExecuteController.scala:178:35, :360:24, :363:55, :376:{22,32}]
wire [2:0] b_fire_counter_max = _b_fire_counter_max_T[2:0]; // @[Util.scala:18:28]
wire _b_fire_counter_T = |b_fire_counter_max; // @[Util.scala:18:28, :19:14]
wire _GEN_61 = b_fire_counter_max == 3'h0; // @[Util.scala:18:28, :19:28]
wire _b_fire_counter_T_1; // @[Util.scala:19:28]
assign _b_fire_counter_T_1 = _GEN_61; // @[Util.scala:19:28]
wire _b_fire_counter_T_9; // @[Util.scala:29:12]
assign _b_fire_counter_T_9 = _GEN_61; // @[Util.scala:19:28, :29:12]
wire _b_fire_counter_T_2 = _b_fire_counter_T | _b_fire_counter_T_1; // @[Util.scala:19:{14,21,28}]
wire _b_fire_counter_T_4 = ~_b_fire_counter_T_3; // @[Util.scala:19:11]
wire _b_fire_counter_T_5 = ~_b_fire_counter_T_2; // @[Util.scala:19:{11,21}]
wire [1:0] _b_fire_counter_T_7 = _b_fire_counter_T_6[1:0]; // @[Util.scala:27:15]
wire [3:0] _GEN_62 = {1'h0, b_fire_counter_max}; // @[Util.scala:18:28, :30:17]
wire [3:0] _b_fire_counter_T_10 = _GEN_62 - 4'h1; // @[Util.scala:30:17]
wire [2:0] _b_fire_counter_T_11 = _b_fire_counter_T_10[2:0]; // @[Util.scala:30:17]
wire [3:0] _b_fire_counter_T_12 = {1'h0, _b_fire_counter_T_11} + 4'h1; // @[Util.scala:30:{17,21}]
wire [2:0] _b_fire_counter_T_13 = _b_fire_counter_T_12[2:0]; // @[Util.scala:30:21]
wire _b_fire_counter_T_14 = _GEN_25 >= _b_fire_counter_T_13; // @[Util.scala:30:{10,21}]
wire _b_fire_counter_T_16 = _b_fire_counter_T_14; // @[Util.scala:30:{10,27}]
wire [3:0] _b_fire_counter_T_17 = _GEN_62 - _GEN_41; // @[Util.scala:30:{17,54}]
wire [2:0] _b_fire_counter_T_18 = _b_fire_counter_T_17[2:0]; // @[Util.scala:30:54]
wire [3:0] _b_fire_counter_T_19 = 4'h1 - {1'h0, _b_fire_counter_T_18}; // @[Util.scala:30:{47,54}]
wire [2:0] _b_fire_counter_T_20 = _b_fire_counter_T_19[2:0]; // @[Util.scala:30:47]
wire [3:0] _b_fire_counter_T_21 = {1'h0, _b_fire_counter_T_20} - 4'h1; // @[Util.scala:30:{47,59}]
wire [2:0] _b_fire_counter_T_22 = _b_fire_counter_T_21[2:0]; // @[Util.scala:30:59]
wire [2:0] _b_fire_counter_T_23 = _b_fire_counter_T_16 ? _b_fire_counter_T_22 : {1'h0, _b_fire_counter_T_7}; // @[Mux.scala:126:16]
wire [2:0] _b_fire_counter_T_24 = _b_fire_counter_T_9 ? 3'h0 : _b_fire_counter_T_23; // @[Mux.scala:126:16]
wire [2:0] _b_fire_counter_T_25 = _b_fire_counter_T_24; // @[Mux.scala:126:16]
wire _T_46 = firing & d_fire & _mesh_cntl_signals_q_io_enq_ready; // @[ExecuteController.scala:178:35, :361:24, :363:55, :383:{22,32}]
wire [2:0] d_fire_counter_max = _d_fire_counter_max_T[2:0]; // @[Util.scala:18:28]
wire _d_fire_counter_T = |d_fire_counter_max; // @[Util.scala:18:28, :19:14]
wire _GEN_63 = d_fire_counter_max == 3'h0; // @[Util.scala:18:28, :19:28]
wire _d_fire_counter_T_1; // @[Util.scala:19:28]
assign _d_fire_counter_T_1 = _GEN_63; // @[Util.scala:19:28]
wire _d_fire_counter_T_9; // @[Util.scala:29:12]
assign _d_fire_counter_T_9 = _GEN_63; // @[Util.scala:19:28, :29:12]
wire _d_fire_counter_T_2 = _d_fire_counter_T | _d_fire_counter_T_1; // @[Util.scala:19:{14,21,28}]
wire _d_fire_counter_T_4 = ~_d_fire_counter_T_3; // @[Util.scala:19:11]
wire _d_fire_counter_T_5 = ~_d_fire_counter_T_2; // @[Util.scala:19:{11,21}]
wire [1:0] _d_fire_counter_T_7 = _d_fire_counter_T_6[1:0]; // @[Util.scala:27:15]
wire [3:0] _GEN_64 = {1'h0, d_fire_counter_max}; // @[Util.scala:18:28, :30:17]
wire [3:0] _d_fire_counter_T_10 = _GEN_64 - 4'h1; // @[Util.scala:30:17]
wire [2:0] _d_fire_counter_T_11 = _d_fire_counter_T_10[2:0]; // @[Util.scala:30:17]
wire [3:0] _d_fire_counter_T_12 = {1'h0, _d_fire_counter_T_11} + 4'h1; // @[Util.scala:30:{17,21}]
wire [2:0] _d_fire_counter_T_13 = _d_fire_counter_T_12[2:0]; // @[Util.scala:30:21]
wire _d_fire_counter_T_14 = d_fire_counter_mulpre >= _d_fire_counter_T_13; // @[Util.scala:30:{10,21}]
wire _d_fire_counter_T_16 = _d_fire_counter_T_14; // @[Util.scala:30:{10,27}]
wire [3:0] _d_fire_counter_T_17 = _GEN_64 - _GEN_22; // @[Util.scala:30:{17,54}]
wire [2:0] _d_fire_counter_T_18 = _d_fire_counter_T_17[2:0]; // @[Util.scala:30:54]
wire [3:0] _d_fire_counter_T_19 = 4'h1 - {1'h0, _d_fire_counter_T_18}; // @[Util.scala:30:{47,54}]
wire [2:0] _d_fire_counter_T_20 = _d_fire_counter_T_19[2:0]; // @[Util.scala:30:47]
wire [3:0] _d_fire_counter_T_21 = {1'h0, _d_fire_counter_T_20} - 4'h1; // @[Util.scala:30:{47,59}]
wire [2:0] _d_fire_counter_T_22 = _d_fire_counter_T_21[2:0]; // @[Util.scala:30:59]
wire [2:0] _d_fire_counter_T_23 = _d_fire_counter_T_16 ? _d_fire_counter_T_22 : {1'h0, _d_fire_counter_T_7}; // @[Mux.scala:126:16]
wire [2:0] _d_fire_counter_T_24 = _d_fire_counter_T_9 ? 3'h0 : _d_fire_counter_T_23; // @[Mux.scala:126:16]
wire [2:0] _d_fire_counter_T_25 = _d_fire_counter_T_24; // @[Mux.scala:126:16]
wire _mul_pre_counter_sub_T = |mul_pre_counter_sub; // @[ExecuteController.scala:305:36, :398:52]
wire [3:0] _GEN_65 = {1'h0, mul_pre_counter_sub}; // @[ExecuteController.scala:305:36, :398:80]
wire [3:0] _mul_pre_counter_sub_T_1 = _GEN_65 - 4'h1; // @[ExecuteController.scala:398:80]
wire [2:0] _mul_pre_counter_sub_T_2 = _mul_pre_counter_sub_T_1[2:0]; // @[ExecuteController.scala:398:80]
wire [2:0] _mul_pre_counter_sub_T_3 = _mul_pre_counter_sub_T ? _mul_pre_counter_sub_T_2 : 3'h0; // @[ExecuteController.scala:398:{31,52,80}]
wire [2:0] _about_to_fire_all_rows_T_1 = _about_to_fire_all_rows_T[2:0]; // @[ExecuteController.scala:405:64]
wire _about_to_fire_all_rows_T_2 = _GEN_24 == _about_to_fire_all_rows_T_1; // @[ExecuteController.scala:310:47, :405:{49,64}]
wire _about_to_fire_all_rows_T_3 = _about_to_fire_all_rows_T_2 & a_fire; // @[ExecuteController.scala:359:24, :405:{49,70}]
wire _about_to_fire_all_rows_T_5 = _about_to_fire_all_rows_T_3 | _about_to_fire_all_rows_T_4; // @[ExecuteController.scala:405:{70,81,99}]
wire [2:0] _about_to_fire_all_rows_T_7 = _about_to_fire_all_rows_T_6[2:0]; // @[ExecuteController.scala:406:37]
wire _about_to_fire_all_rows_T_8 = _GEN_25 == _about_to_fire_all_rows_T_7; // @[ExecuteController.scala:311:47, :406:{22,37}]
wire _about_to_fire_all_rows_T_9 = _about_to_fire_all_rows_T_8 & b_fire; // @[ExecuteController.scala:360:24, :406:{22,43}]
wire _about_to_fire_all_rows_T_11 = _about_to_fire_all_rows_T_9 | _about_to_fire_all_rows_T_10; // @[ExecuteController.scala:406:{43,54,72}]
wire _about_to_fire_all_rows_T_12 = _about_to_fire_all_rows_T_5 & _about_to_fire_all_rows_T_11; // @[ExecuteController.scala:405:{81,108}, :406:54]
wire [2:0] _about_to_fire_all_rows_T_14 = _about_to_fire_all_rows_T_13[2:0]; // @[ExecuteController.scala:407:37]
wire _about_to_fire_all_rows_T_15 = d_fire_counter_mulpre == _about_to_fire_all_rows_T_14; // @[ExecuteController.scala:407:{22,37}, :417:39]
wire _about_to_fire_all_rows_T_16 = _about_to_fire_all_rows_T_15 & d_fire; // @[ExecuteController.scala:361:24, :407:{22,43}]
wire _about_to_fire_all_rows_T_18 = _about_to_fire_all_rows_T_16 | _about_to_fire_all_rows_T_17; // @[ExecuteController.scala:407:{43,54,72}]
wire _about_to_fire_all_rows_T_19 = _about_to_fire_all_rows_T_12 & _about_to_fire_all_rows_T_18; // @[ExecuteController.scala:405:108, :406:81, :407:54]
wire _about_to_fire_all_rows_T_20 = a_fire_started | b_fire_started; // @[ExecuteController.scala:240:31, :242:31, :408:21]
wire _about_to_fire_all_rows_T_21 = _about_to_fire_all_rows_T_20 | d_fire_started; // @[ExecuteController.scala:241:31, :408:{21,39}]
wire _about_to_fire_all_rows_T_22 = _about_to_fire_all_rows_T_19 & _about_to_fire_all_rows_T_21; // @[ExecuteController.scala:406:81, :407:81, :408:39]
wire about_to_fire_all_rows = _about_to_fire_all_rows_T_22 & _mesh_cntl_signals_q_io_enq_ready; // @[ExecuteController.scala:178:35, :407:81, :408:58]
wire [3:0] _d_fire_counter_mulpre_T = _GEN_22 - _GEN_65; // @[ExecuteController.scala:253:55, :398:80, :419:45]
wire [2:0] _d_fire_counter_mulpre_T_1 = _d_fire_counter_mulpre_T[2:0]; // @[ExecuteController.scala:419:45]
wire _read_a_T = ~a_read_from_acc; // @[ExecuteController.scala:263:44, :424:29]
wire _read_a_T_1 = a_valid & _read_a_T; // @[ExecuteController.scala:356:5, :424:{26,29}]
wire _read_a_T_2 = dataAbank == 2'h0; // @[LocalAddr.scala:33:79]
wire _read_a_T_3 = _read_a_T_1 & _read_a_T_2; // @[ExecuteController.scala:424:{26,46,59}]
wire _read_a_T_4 = _read_a_T_3 & start_inputting_a; // @[ExecuteController.scala:267:35, :424:{46,67}]
wire _read_a_T_5 = ~multiply_garbage; // @[LocalAddr.scala:43:96]
wire _read_a_T_6 = _read_a_T_4 & _read_a_T_5; // @[ExecuteController.scala:424:{67,88,91}]
wire _read_a_T_7 = _read_a_T_6 & a_row_is_not_all_zeros; // @[ExecuteController.scala:310:47, :424:{88,109}]
wire read_a = _read_a_T_7; // @[ExecuteController.scala:424:{109,135}]
wire _read_b_T = ~b_read_from_acc; // @[ExecuteController.scala:264:44, :425:29]
wire _read_b_T_1 = b_valid & _read_b_T; // @[ExecuteController.scala:356:5, :425:{26,29}]
wire _read_b_T_2 = dataBbank == 2'h0; // @[LocalAddr.scala:33:79]
wire _read_b_T_3 = _read_b_T_1 & _read_b_T_2; // @[ExecuteController.scala:425:{26,46,59}]
wire _read_b_T_4 = _read_b_T_3 & start_inputting_b; // @[ExecuteController.scala:268:35, :425:{46,67}]
wire _read_b_T_5 = ~accumulate_zeros; // @[LocalAddr.scala:43:96]
wire _read_b_T_6 = _read_b_T_4 & _read_b_T_5; // @[ExecuteController.scala:425:{67,88,91}]
wire read_b = _read_b_T_6 & b_row_is_not_all_zeros; // @[ExecuteController.scala:311:47, :425:{88,109}]
wire _read_d_T = ~d_read_from_acc; // @[ExecuteController.scala:265:44, :426:29]
wire _read_d_T_1 = d_valid & _read_d_T; // @[ExecuteController.scala:356:5, :426:{26,29}]
wire _read_d_T_2 = dataDbank == 2'h0; // @[LocalAddr.scala:33:79]
wire _read_d_T_3 = _read_d_T_1 & _read_d_T_2; // @[ExecuteController.scala:426:{26,46,59}]
wire _read_d_T_4 = _read_d_T_3 & start_inputting_d; // @[ExecuteController.scala:269:35, :426:{46,67}]
wire _read_d_T_5 = ~preload_zeros; // @[LocalAddr.scala:43:96]
wire _read_d_T_6 = _read_d_T_4 & _read_d_T_5; // @[ExecuteController.scala:426:{67,88,91}]
wire read_d = _read_d_T_6 & d_row_is_not_all_zeros; // @[ExecuteController.scala:312:68, :426:{88,106}]
wire _io_srams_read_0_req_valid_T = read_a | read_b; // @[ExecuteController.scala:424:135, :425:109, :435:45]
wire _io_srams_read_0_req_valid_T_1 = _io_srams_read_0_req_valid_T | read_d; // @[ExecuteController.scala:426:106, :435:{45,55}]
assign _io_srams_read_0_req_valid_T_2 = _io_srams_read_0_req_valid_T_1 & _mesh_cntl_signals_q_io_enq_ready; // @[ExecuteController.scala:178:35, :435:{55,66}]
assign io_srams_read_0_req_valid_0 = _io_srams_read_0_req_valid_T_2; // @[ExecuteController.scala:12:7, :435:66]
wire [11:0] _io_srams_read_0_req_bits_addr_T = a_address_rs1_data[11:0]; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_1_req_bits_addr_T = a_address_rs1_data[11:0]; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_2_req_bits_addr_T = a_address_rs1_data[11:0]; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_3_req_bits_addr_T = a_address_rs1_data[11:0]; // @[LocalAddr.scala:34:36]
wire [11:0] _io_acc_read_req_0_bits_addr_T = a_address_rs1_data[11:0]; // @[LocalAddr.scala:34:36, :36:37]
wire [12:0] _GEN_66 = {11'h0, a_fire_counter}; // @[ExecuteController.scala:236:27, :437:72]
wire [12:0] _io_srams_read_0_req_bits_addr_T_1 = {1'h0, _io_srams_read_0_req_bits_addr_T} + _GEN_66; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_0_req_bits_addr_T_2 = _io_srams_read_0_req_bits_addr_T_1[11:0]; // @[ExecuteController.scala:437:72]
wire [11:0] _io_srams_read_0_req_bits_addr_T_3 = b_address_rs2_data[11:0]; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_1_req_bits_addr_T_3 = b_address_rs2_data[11:0]; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_2_req_bits_addr_T_3 = b_address_rs2_data[11:0]; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_3_req_bits_addr_T_3 = b_address_rs2_data[11:0]; // @[LocalAddr.scala:34:36]
wire [11:0] _io_acc_read_req_0_bits_addr_T_3 = b_address_rs2_data[11:0]; // @[LocalAddr.scala:34:36, :36:37]
wire [12:0] _GEN_67 = {11'h0, b_fire_counter}; // @[ExecuteController.scala:237:27, :438:47]
wire [12:0] _io_srams_read_0_req_bits_addr_T_4 = {1'h0, _io_srams_read_0_req_bits_addr_T_3} + _GEN_67; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_0_req_bits_addr_T_5 = _io_srams_read_0_req_bits_addr_T_4[11:0]; // @[ExecuteController.scala:438:47]
wire [11:0] _io_srams_read_0_req_bits_addr_T_6 = d_address_rs1_data[11:0]; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_1_req_bits_addr_T_6 = d_address_rs1_data[11:0]; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_2_req_bits_addr_T_6 = d_address_rs1_data[11:0]; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_3_req_bits_addr_T_6 = d_address_rs1_data[11:0]; // @[LocalAddr.scala:34:36]
wire [11:0] _io_acc_read_req_0_bits_addr_T_6 = d_address_rs1_data[11:0]; // @[LocalAddr.scala:34:36, :36:37]
wire [12:0] _io_srams_read_0_req_bits_addr_T_7 = {1'h0, _io_srams_read_0_req_bits_addr_T_6} + 13'h4; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_0_req_bits_addr_T_8 = _io_srams_read_0_req_bits_addr_T_7[11:0]; // @[ExecuteController.scala:439:45]
wire [12:0] _io_srams_read_0_req_bits_addr_T_9 = {1'h0, _io_srams_read_0_req_bits_addr_T_8} - 13'h1; // @[ExecuteController.scala:439:{45,60}]
wire [11:0] _io_srams_read_0_req_bits_addr_T_10 = _io_srams_read_0_req_bits_addr_T_9[11:0]; // @[ExecuteController.scala:439:60]
wire [12:0] _GEN_68 = {10'h0, d_fire_counter_mulpre}; // @[ExecuteController.scala:417:39, :439:{45,66}]
wire [12:0] _io_srams_read_0_req_bits_addr_T_11 = {1'h0, _io_srams_read_0_req_bits_addr_T_10} - _GEN_68; // @[ExecuteController.scala:439:{60,66}]
wire [11:0] _io_srams_read_0_req_bits_addr_T_12 = _io_srams_read_0_req_bits_addr_T_11[11:0]; // @[ExecuteController.scala:439:66]
wire [11:0] _io_srams_read_0_req_bits_addr_T_13 = read_d ? _io_srams_read_0_req_bits_addr_T_12 : _io_srams_read_0_req_bits_addr_T_2; // @[Mux.scala:126:16]
wire [11:0] _io_srams_read_0_req_bits_addr_T_14 = read_b ? _io_srams_read_0_req_bits_addr_T_5 : _io_srams_read_0_req_bits_addr_T_13; // @[Mux.scala:126:16]
wire [11:0] _io_srams_read_0_req_bits_addr_T_15 = a_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_srams_read_1_req_bits_addr_T_15 = a_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_srams_read_2_req_bits_addr_T_15 = a_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_srams_read_3_req_bits_addr_T_15 = a_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_acc_read_req_0_bits_addr_T_15 = a_address_data[11:0]; // @[LocalAddr.scala:34:36, :36:37, :50:26]
wire [11:0] _io_srams_read_0_req_bits_addr_T_16 = b_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_srams_read_1_req_bits_addr_T_16 = b_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_srams_read_2_req_bits_addr_T_16 = b_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_srams_read_3_req_bits_addr_T_16 = b_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_acc_read_req_0_bits_addr_T_16 = b_address_data[11:0]; // @[LocalAddr.scala:34:36, :36:37, :50:26]
wire [11:0] _io_srams_read_0_req_bits_addr_T_17 = d_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_srams_read_1_req_bits_addr_T_17 = d_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_srams_read_2_req_bits_addr_T_17 = d_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_srams_read_3_req_bits_addr_T_17 = d_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_acc_read_req_0_bits_addr_T_17 = d_address_data[11:0]; // @[LocalAddr.scala:34:36, :36:37, :50:26]
wire [11:0] _io_srams_read_0_req_bits_addr_T_18 = read_d ? _io_srams_read_0_req_bits_addr_T_17 : _io_srams_read_0_req_bits_addr_T_15; // @[Mux.scala:126:16]
assign _io_srams_read_0_req_bits_addr_T_19 = read_b ? _io_srams_read_0_req_bits_addr_T_16 : _io_srams_read_0_req_bits_addr_T_18; // @[Mux.scala:126:16]
assign io_srams_read_0_req_bits_addr_0 = _io_srams_read_0_req_bits_addr_T_19; // @[Mux.scala:126:16]
wire _read_a_T_10 = ~a_read_from_acc; // @[ExecuteController.scala:263:44, :424:29]
wire _read_a_T_11 = a_valid & _read_a_T_10; // @[ExecuteController.scala:356:5, :424:{26,29}]
wire _read_a_T_12 = dataAbank == 2'h1; // @[LocalAddr.scala:33:79]
wire _read_a_T_13 = _read_a_T_11 & _read_a_T_12; // @[ExecuteController.scala:424:{26,46,59}]
wire _read_a_T_14 = _read_a_T_13 & start_inputting_a; // @[ExecuteController.scala:267:35, :424:{46,67}]
wire _read_a_T_15 = ~multiply_garbage; // @[LocalAddr.scala:43:96]
wire _read_a_T_16 = _read_a_T_14 & _read_a_T_15; // @[ExecuteController.scala:424:{67,88,91}]
wire _read_a_T_17 = _read_a_T_16 & a_row_is_not_all_zeros; // @[ExecuteController.scala:310:47, :424:{88,109}]
wire read_a_1 = _read_a_T_17; // @[ExecuteController.scala:424:{109,135}]
wire _read_b_T_7 = ~b_read_from_acc; // @[ExecuteController.scala:264:44, :425:29]
wire _read_b_T_8 = b_valid & _read_b_T_7; // @[ExecuteController.scala:356:5, :425:{26,29}]
wire _read_b_T_9 = dataBbank == 2'h1; // @[LocalAddr.scala:33:79]
wire _read_b_T_10 = _read_b_T_8 & _read_b_T_9; // @[ExecuteController.scala:425:{26,46,59}]
wire _read_b_T_11 = _read_b_T_10 & start_inputting_b; // @[ExecuteController.scala:268:35, :425:{46,67}]
wire _read_b_T_12 = ~accumulate_zeros; // @[LocalAddr.scala:43:96]
wire _read_b_T_13 = _read_b_T_11 & _read_b_T_12; // @[ExecuteController.scala:425:{67,88,91}]
wire read_b_1 = _read_b_T_13 & b_row_is_not_all_zeros; // @[ExecuteController.scala:311:47, :425:{88,109}]
wire _read_d_T_7 = ~d_read_from_acc; // @[ExecuteController.scala:265:44, :426:29]
wire _read_d_T_8 = d_valid & _read_d_T_7; // @[ExecuteController.scala:356:5, :426:{26,29}]
wire _read_d_T_9 = dataDbank == 2'h1; // @[LocalAddr.scala:33:79]
wire _read_d_T_10 = _read_d_T_8 & _read_d_T_9; // @[ExecuteController.scala:426:{26,46,59}]
wire _read_d_T_11 = _read_d_T_10 & start_inputting_d; // @[ExecuteController.scala:269:35, :426:{46,67}]
wire _read_d_T_12 = ~preload_zeros; // @[LocalAddr.scala:43:96]
wire _read_d_T_13 = _read_d_T_11 & _read_d_T_12; // @[ExecuteController.scala:426:{67,88,91}]
wire read_d_1 = _read_d_T_13 & d_row_is_not_all_zeros; // @[ExecuteController.scala:312:68, :426:{88,106}]
wire _io_srams_read_1_req_valid_T = read_a_1 | read_b_1; // @[ExecuteController.scala:424:135, :425:109, :435:45]
wire _io_srams_read_1_req_valid_T_1 = _io_srams_read_1_req_valid_T | read_d_1; // @[ExecuteController.scala:426:106, :435:{45,55}]
assign _io_srams_read_1_req_valid_T_2 = _io_srams_read_1_req_valid_T_1 & _mesh_cntl_signals_q_io_enq_ready; // @[ExecuteController.scala:178:35, :435:{55,66}]
assign io_srams_read_1_req_valid_0 = _io_srams_read_1_req_valid_T_2; // @[ExecuteController.scala:12:7, :435:66]
wire [12:0] _io_srams_read_1_req_bits_addr_T_1 = {1'h0, _io_srams_read_1_req_bits_addr_T} + _GEN_66; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_1_req_bits_addr_T_2 = _io_srams_read_1_req_bits_addr_T_1[11:0]; // @[ExecuteController.scala:437:72]
wire [12:0] _io_srams_read_1_req_bits_addr_T_4 = {1'h0, _io_srams_read_1_req_bits_addr_T_3} + _GEN_67; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_1_req_bits_addr_T_5 = _io_srams_read_1_req_bits_addr_T_4[11:0]; // @[ExecuteController.scala:438:47]
wire [12:0] _io_srams_read_1_req_bits_addr_T_7 = {1'h0, _io_srams_read_1_req_bits_addr_T_6} + 13'h4; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_1_req_bits_addr_T_8 = _io_srams_read_1_req_bits_addr_T_7[11:0]; // @[ExecuteController.scala:439:45]
wire [12:0] _io_srams_read_1_req_bits_addr_T_9 = {1'h0, _io_srams_read_1_req_bits_addr_T_8} - 13'h1; // @[ExecuteController.scala:439:{45,60}]
wire [11:0] _io_srams_read_1_req_bits_addr_T_10 = _io_srams_read_1_req_bits_addr_T_9[11:0]; // @[ExecuteController.scala:439:60]
wire [12:0] _io_srams_read_1_req_bits_addr_T_11 = {1'h0, _io_srams_read_1_req_bits_addr_T_10} - _GEN_68; // @[ExecuteController.scala:439:{60,66}]
wire [11:0] _io_srams_read_1_req_bits_addr_T_12 = _io_srams_read_1_req_bits_addr_T_11[11:0]; // @[ExecuteController.scala:439:66]
wire [11:0] _io_srams_read_1_req_bits_addr_T_13 = read_d_1 ? _io_srams_read_1_req_bits_addr_T_12 : _io_srams_read_1_req_bits_addr_T_2; // @[Mux.scala:126:16]
wire [11:0] _io_srams_read_1_req_bits_addr_T_14 = read_b_1 ? _io_srams_read_1_req_bits_addr_T_5 : _io_srams_read_1_req_bits_addr_T_13; // @[Mux.scala:126:16]
wire [11:0] _io_srams_read_1_req_bits_addr_T_18 = read_d_1 ? _io_srams_read_1_req_bits_addr_T_17 : _io_srams_read_1_req_bits_addr_T_15; // @[Mux.scala:126:16]
assign _io_srams_read_1_req_bits_addr_T_19 = read_b_1 ? _io_srams_read_1_req_bits_addr_T_16 : _io_srams_read_1_req_bits_addr_T_18; // @[Mux.scala:126:16]
assign io_srams_read_1_req_bits_addr_0 = _io_srams_read_1_req_bits_addr_T_19; // @[Mux.scala:126:16]
wire _read_a_T_20 = ~a_read_from_acc; // @[ExecuteController.scala:263:44, :424:29]
wire _read_a_T_21 = a_valid & _read_a_T_20; // @[ExecuteController.scala:356:5, :424:{26,29}]
wire _read_a_T_22 = dataAbank == 2'h2; // @[LocalAddr.scala:33:79]
wire _read_a_T_23 = _read_a_T_21 & _read_a_T_22; // @[ExecuteController.scala:424:{26,46,59}]
wire _read_a_T_24 = _read_a_T_23 & start_inputting_a; // @[ExecuteController.scala:267:35, :424:{46,67}]
wire _read_a_T_25 = ~multiply_garbage; // @[LocalAddr.scala:43:96]
wire _read_a_T_26 = _read_a_T_24 & _read_a_T_25; // @[ExecuteController.scala:424:{67,88,91}]
wire _read_a_T_27 = _read_a_T_26 & a_row_is_not_all_zeros; // @[ExecuteController.scala:310:47, :424:{88,109}]
wire read_a_2 = _read_a_T_27; // @[ExecuteController.scala:424:{109,135}]
wire _read_b_T_14 = ~b_read_from_acc; // @[ExecuteController.scala:264:44, :425:29]
wire _read_b_T_15 = b_valid & _read_b_T_14; // @[ExecuteController.scala:356:5, :425:{26,29}]
wire _read_b_T_16 = dataBbank == 2'h2; // @[LocalAddr.scala:33:79]
wire _read_b_T_17 = _read_b_T_15 & _read_b_T_16; // @[ExecuteController.scala:425:{26,46,59}]
wire _read_b_T_18 = _read_b_T_17 & start_inputting_b; // @[ExecuteController.scala:268:35, :425:{46,67}]
wire _read_b_T_19 = ~accumulate_zeros; // @[LocalAddr.scala:43:96]
wire _read_b_T_20 = _read_b_T_18 & _read_b_T_19; // @[ExecuteController.scala:425:{67,88,91}]
wire read_b_2 = _read_b_T_20 & b_row_is_not_all_zeros; // @[ExecuteController.scala:311:47, :425:{88,109}]
wire _read_d_T_14 = ~d_read_from_acc; // @[ExecuteController.scala:265:44, :426:29]
wire _read_d_T_15 = d_valid & _read_d_T_14; // @[ExecuteController.scala:356:5, :426:{26,29}]
wire _read_d_T_16 = dataDbank == 2'h2; // @[LocalAddr.scala:33:79]
wire _read_d_T_17 = _read_d_T_15 & _read_d_T_16; // @[ExecuteController.scala:426:{26,46,59}]
wire _read_d_T_18 = _read_d_T_17 & start_inputting_d; // @[ExecuteController.scala:269:35, :426:{46,67}]
wire _read_d_T_19 = ~preload_zeros; // @[LocalAddr.scala:43:96]
wire _read_d_T_20 = _read_d_T_18 & _read_d_T_19; // @[ExecuteController.scala:426:{67,88,91}]
wire read_d_2 = _read_d_T_20 & d_row_is_not_all_zeros; // @[ExecuteController.scala:312:68, :426:{88,106}]
wire _io_srams_read_2_req_valid_T = read_a_2 | read_b_2; // @[ExecuteController.scala:424:135, :425:109, :435:45]
wire _io_srams_read_2_req_valid_T_1 = _io_srams_read_2_req_valid_T | read_d_2; // @[ExecuteController.scala:426:106, :435:{45,55}]
assign _io_srams_read_2_req_valid_T_2 = _io_srams_read_2_req_valid_T_1 & _mesh_cntl_signals_q_io_enq_ready; // @[ExecuteController.scala:178:35, :435:{55,66}]
assign io_srams_read_2_req_valid_0 = _io_srams_read_2_req_valid_T_2; // @[ExecuteController.scala:12:7, :435:66]
wire [12:0] _io_srams_read_2_req_bits_addr_T_1 = {1'h0, _io_srams_read_2_req_bits_addr_T} + _GEN_66; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_2_req_bits_addr_T_2 = _io_srams_read_2_req_bits_addr_T_1[11:0]; // @[ExecuteController.scala:437:72]
wire [12:0] _io_srams_read_2_req_bits_addr_T_4 = {1'h0, _io_srams_read_2_req_bits_addr_T_3} + _GEN_67; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_2_req_bits_addr_T_5 = _io_srams_read_2_req_bits_addr_T_4[11:0]; // @[ExecuteController.scala:438:47]
wire [12:0] _io_srams_read_2_req_bits_addr_T_7 = {1'h0, _io_srams_read_2_req_bits_addr_T_6} + 13'h4; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_2_req_bits_addr_T_8 = _io_srams_read_2_req_bits_addr_T_7[11:0]; // @[ExecuteController.scala:439:45]
wire [12:0] _io_srams_read_2_req_bits_addr_T_9 = {1'h0, _io_srams_read_2_req_bits_addr_T_8} - 13'h1; // @[ExecuteController.scala:439:{45,60}]
wire [11:0] _io_srams_read_2_req_bits_addr_T_10 = _io_srams_read_2_req_bits_addr_T_9[11:0]; // @[ExecuteController.scala:439:60]
wire [12:0] _io_srams_read_2_req_bits_addr_T_11 = {1'h0, _io_srams_read_2_req_bits_addr_T_10} - _GEN_68; // @[ExecuteController.scala:439:{60,66}]
wire [11:0] _io_srams_read_2_req_bits_addr_T_12 = _io_srams_read_2_req_bits_addr_T_11[11:0]; // @[ExecuteController.scala:439:66]
wire [11:0] _io_srams_read_2_req_bits_addr_T_13 = read_d_2 ? _io_srams_read_2_req_bits_addr_T_12 : _io_srams_read_2_req_bits_addr_T_2; // @[Mux.scala:126:16]
wire [11:0] _io_srams_read_2_req_bits_addr_T_14 = read_b_2 ? _io_srams_read_2_req_bits_addr_T_5 : _io_srams_read_2_req_bits_addr_T_13; // @[Mux.scala:126:16]
wire [11:0] _io_srams_read_2_req_bits_addr_T_18 = read_d_2 ? _io_srams_read_2_req_bits_addr_T_17 : _io_srams_read_2_req_bits_addr_T_15; // @[Mux.scala:126:16]
assign _io_srams_read_2_req_bits_addr_T_19 = read_b_2 ? _io_srams_read_2_req_bits_addr_T_16 : _io_srams_read_2_req_bits_addr_T_18; // @[Mux.scala:126:16]
assign io_srams_read_2_req_bits_addr_0 = _io_srams_read_2_req_bits_addr_T_19; // @[Mux.scala:126:16]
wire _read_a_T_30 = ~a_read_from_acc; // @[ExecuteController.scala:263:44, :424:29]
wire _read_a_T_31 = a_valid & _read_a_T_30; // @[ExecuteController.scala:356:5, :424:{26,29}]
wire _read_a_T_32 = &dataAbank; // @[LocalAddr.scala:33:79]
wire _read_a_T_33 = _read_a_T_31 & _read_a_T_32; // @[ExecuteController.scala:424:{26,46,59}]
wire _read_a_T_34 = _read_a_T_33 & start_inputting_a; // @[ExecuteController.scala:267:35, :424:{46,67}]
wire _read_a_T_35 = ~multiply_garbage; // @[LocalAddr.scala:43:96]
wire _read_a_T_36 = _read_a_T_34 & _read_a_T_35; // @[ExecuteController.scala:424:{67,88,91}]
wire _read_a_T_37 = _read_a_T_36 & a_row_is_not_all_zeros; // @[ExecuteController.scala:310:47, :424:{88,109}]
wire read_a_3 = _read_a_T_37; // @[ExecuteController.scala:424:{109,135}]
wire _read_b_T_21 = ~b_read_from_acc; // @[ExecuteController.scala:264:44, :425:29]
wire _read_b_T_22 = b_valid & _read_b_T_21; // @[ExecuteController.scala:356:5, :425:{26,29}]
wire _read_b_T_23 = &dataBbank; // @[LocalAddr.scala:33:79]
wire _read_b_T_24 = _read_b_T_22 & _read_b_T_23; // @[ExecuteController.scala:425:{26,46,59}]
wire _read_b_T_25 = _read_b_T_24 & start_inputting_b; // @[ExecuteController.scala:268:35, :425:{46,67}]
wire _read_b_T_26 = ~accumulate_zeros; // @[LocalAddr.scala:43:96]
wire _read_b_T_27 = _read_b_T_25 & _read_b_T_26; // @[ExecuteController.scala:425:{67,88,91}]
wire read_b_3 = _read_b_T_27 & b_row_is_not_all_zeros; // @[ExecuteController.scala:311:47, :425:{88,109}]
wire _read_d_T_21 = ~d_read_from_acc; // @[ExecuteController.scala:265:44, :426:29]
wire _read_d_T_22 = d_valid & _read_d_T_21; // @[ExecuteController.scala:356:5, :426:{26,29}]
wire _read_d_T_23 = &dataDbank; // @[LocalAddr.scala:33:79]
wire _read_d_T_24 = _read_d_T_22 & _read_d_T_23; // @[ExecuteController.scala:426:{26,46,59}]
wire _read_d_T_25 = _read_d_T_24 & start_inputting_d; // @[ExecuteController.scala:269:35, :426:{46,67}]
wire _read_d_T_26 = ~preload_zeros; // @[LocalAddr.scala:43:96]
wire _read_d_T_27 = _read_d_T_25 & _read_d_T_26; // @[ExecuteController.scala:426:{67,88,91}]
wire read_d_3 = _read_d_T_27 & d_row_is_not_all_zeros; // @[ExecuteController.scala:312:68, :426:{88,106}]
wire _io_srams_read_3_req_valid_T = read_a_3 | read_b_3; // @[ExecuteController.scala:424:135, :425:109, :435:45]
wire _io_srams_read_3_req_valid_T_1 = _io_srams_read_3_req_valid_T | read_d_3; // @[ExecuteController.scala:426:106, :435:{45,55}]
assign _io_srams_read_3_req_valid_T_2 = _io_srams_read_3_req_valid_T_1 & _mesh_cntl_signals_q_io_enq_ready; // @[ExecuteController.scala:178:35, :435:{55,66}]
assign io_srams_read_3_req_valid_0 = _io_srams_read_3_req_valid_T_2; // @[ExecuteController.scala:12:7, :435:66]
wire [12:0] _io_srams_read_3_req_bits_addr_T_1 = {1'h0, _io_srams_read_3_req_bits_addr_T} + _GEN_66; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_3_req_bits_addr_T_2 = _io_srams_read_3_req_bits_addr_T_1[11:0]; // @[ExecuteController.scala:437:72]
wire [12:0] _io_srams_read_3_req_bits_addr_T_4 = {1'h0, _io_srams_read_3_req_bits_addr_T_3} + _GEN_67; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_3_req_bits_addr_T_5 = _io_srams_read_3_req_bits_addr_T_4[11:0]; // @[ExecuteController.scala:438:47]
wire [12:0] _io_srams_read_3_req_bits_addr_T_7 = {1'h0, _io_srams_read_3_req_bits_addr_T_6} + 13'h4; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_3_req_bits_addr_T_8 = _io_srams_read_3_req_bits_addr_T_7[11:0]; // @[ExecuteController.scala:439:45]
wire [12:0] _io_srams_read_3_req_bits_addr_T_9 = {1'h0, _io_srams_read_3_req_bits_addr_T_8} - 13'h1; // @[ExecuteController.scala:439:{45,60}]
wire [11:0] _io_srams_read_3_req_bits_addr_T_10 = _io_srams_read_3_req_bits_addr_T_9[11:0]; // @[ExecuteController.scala:439:60]
wire [12:0] _io_srams_read_3_req_bits_addr_T_11 = {1'h0, _io_srams_read_3_req_bits_addr_T_10} - _GEN_68; // @[ExecuteController.scala:439:{60,66}]
wire [11:0] _io_srams_read_3_req_bits_addr_T_12 = _io_srams_read_3_req_bits_addr_T_11[11:0]; // @[ExecuteController.scala:439:66]
wire [11:0] _io_srams_read_3_req_bits_addr_T_13 = read_d_3 ? _io_srams_read_3_req_bits_addr_T_12 : _io_srams_read_3_req_bits_addr_T_2; // @[Mux.scala:126:16]
wire [11:0] _io_srams_read_3_req_bits_addr_T_14 = read_b_3 ? _io_srams_read_3_req_bits_addr_T_5 : _io_srams_read_3_req_bits_addr_T_13; // @[Mux.scala:126:16]
wire [11:0] _io_srams_read_3_req_bits_addr_T_18 = read_d_3 ? _io_srams_read_3_req_bits_addr_T_17 : _io_srams_read_3_req_bits_addr_T_15; // @[Mux.scala:126:16]
assign _io_srams_read_3_req_bits_addr_T_19 = read_b_3 ? _io_srams_read_3_req_bits_addr_T_16 : _io_srams_read_3_req_bits_addr_T_18; // @[Mux.scala:126:16]
assign io_srams_read_3_req_bits_addr_0 = _io_srams_read_3_req_bits_addr_T_19; // @[Mux.scala:126:16]
wire _read_a_from_acc_T = a_valid & a_read_from_acc; // @[ExecuteController.scala:263:44, :356:5, :458:35]
wire _read_a_from_acc_T_2 = _read_a_from_acc_T; // @[ExecuteController.scala:458:{35,54}]
wire _read_a_from_acc_T_3 = _read_a_from_acc_T_2 & start_inputting_a; // @[ExecuteController.scala:267:35, :458:{54,78}]
wire _read_a_from_acc_T_4 = ~multiply_garbage; // @[LocalAddr.scala:43:96]
wire _read_a_from_acc_T_5 = _read_a_from_acc_T_3 & _read_a_from_acc_T_4; // @[ExecuteController.scala:458:{78,99,102}]
wire _read_a_from_acc_T_6 = _read_a_from_acc_T_5 & a_row_is_not_all_zeros; // @[ExecuteController.scala:310:47, :458:{99,120}]
wire read_a_from_acc = _read_a_from_acc_T_6; // @[ExecuteController.scala:458:{120,146}]
wire _read_b_from_acc_T = b_valid & b_read_from_acc; // @[ExecuteController.scala:264:44, :356:5, :459:35]
wire _read_b_from_acc_T_2 = _read_b_from_acc_T; // @[ExecuteController.scala:459:{35,54}]
wire _read_b_from_acc_T_3 = _read_b_from_acc_T_2 & start_inputting_b; // @[ExecuteController.scala:268:35, :459:{54,78}]
wire _read_b_from_acc_T_4 = ~accumulate_zeros; // @[LocalAddr.scala:43:96]
wire _read_b_from_acc_T_5 = _read_b_from_acc_T_3 & _read_b_from_acc_T_4; // @[ExecuteController.scala:459:{78,99,102}]
wire read_b_from_acc = _read_b_from_acc_T_5 & b_row_is_not_all_zeros; // @[ExecuteController.scala:311:47, :459:{99,120}]
wire _read_d_from_acc_T = d_valid & d_read_from_acc; // @[ExecuteController.scala:265:44, :356:5, :460:35]
wire _read_d_from_acc_T_2 = _read_d_from_acc_T; // @[ExecuteController.scala:460:{35,54}]
wire _read_d_from_acc_T_3 = _read_d_from_acc_T_2 & start_inputting_d; // @[ExecuteController.scala:269:35, :460:{54,78}]
wire _read_d_from_acc_T_4 = ~preload_zeros; // @[LocalAddr.scala:43:96]
wire _read_d_from_acc_T_5 = _read_d_from_acc_T_3 & _read_d_from_acc_T_4; // @[ExecuteController.scala:460:{78,99,102}]
wire read_d_from_acc = _read_d_from_acc_T_5 & d_row_is_not_all_zeros; // @[ExecuteController.scala:312:68, :460:{99,117}]
assign b_ready = ~(read_b_from_acc & ~io_acc_read_req_0_ready_0 | read_b_3 & ~io_srams_read_3_req_ready_0 | read_b_2 & ~io_srams_read_2_req_ready_0 | read_b_1 & ~io_srams_read_1_req_ready_0) & ~(read_b & ~io_srams_read_0_req_ready_0); // @[ExecuteController.scala:12:7, :330:25, :425:109, :429:{16,19,48}, :430:11, :459:120, :463:{15,18,45}, :464:11]
assign d_ready = ~(read_d_from_acc & ~io_acc_read_req_0_ready_0 | read_d_3 & ~io_srams_read_3_req_ready_0 | read_d_2 & ~io_srams_read_2_req_ready_0 | read_d_1 & ~io_srams_read_1_req_ready_0) & ~(read_d & ~io_srams_read_0_req_ready_0); // @[ExecuteController.scala:12:7, :331:25, :426:106, :429:{16,19,48}, :430:11, :460:117, :463:{15,18,45}, :464:11]
wire _io_acc_read_req_0_valid_T = read_a_from_acc | read_b_from_acc; // @[ExecuteController.scala:458:146, :459:120, :469:51]
assign _io_acc_read_req_0_valid_T_1 = _io_acc_read_req_0_valid_T | read_d_from_acc; // @[ExecuteController.scala:460:117, :469:{51,70}]
assign io_acc_read_req_0_valid_0 = _io_acc_read_req_0_valid_T_1; // @[ExecuteController.scala:12:7, :469:70]
wire [12:0] _io_acc_read_req_0_bits_addr_T_1 = {1'h0, _io_acc_read_req_0_bits_addr_T} + _GEN_66; // @[LocalAddr.scala:36:37]
wire [11:0] _io_acc_read_req_0_bits_addr_T_2 = _io_acc_read_req_0_bits_addr_T_1[11:0]; // @[ExecuteController.scala:478:71]
wire [12:0] _io_acc_read_req_0_bits_addr_T_4 = {1'h0, _io_acc_read_req_0_bits_addr_T_3} + _GEN_67; // @[LocalAddr.scala:36:37]
wire [11:0] _io_acc_read_req_0_bits_addr_T_5 = _io_acc_read_req_0_bits_addr_T_4[11:0]; // @[ExecuteController.scala:479:57]
wire [12:0] _io_acc_read_req_0_bits_addr_T_7 = {1'h0, _io_acc_read_req_0_bits_addr_T_6} + 13'h4; // @[LocalAddr.scala:36:37]
wire [11:0] _io_acc_read_req_0_bits_addr_T_8 = _io_acc_read_req_0_bits_addr_T_7[11:0]; // @[ExecuteController.scala:480:55]
wire [12:0] _io_acc_read_req_0_bits_addr_T_9 = {1'h0, _io_acc_read_req_0_bits_addr_T_8} - 13'h1; // @[ExecuteController.scala:480:{55,70}]
wire [11:0] _io_acc_read_req_0_bits_addr_T_10 = _io_acc_read_req_0_bits_addr_T_9[11:0]; // @[ExecuteController.scala:480:70]
wire [12:0] _io_acc_read_req_0_bits_addr_T_11 = {1'h0, _io_acc_read_req_0_bits_addr_T_10} - {11'h0, d_fire_counter}; // @[ExecuteController.scala:238:27, :480:{70,76}]
wire [11:0] _io_acc_read_req_0_bits_addr_T_12 = _io_acc_read_req_0_bits_addr_T_11[11:0]; // @[ExecuteController.scala:480:76]
wire [11:0] _io_acc_read_req_0_bits_addr_T_13 = read_d_from_acc ? _io_acc_read_req_0_bits_addr_T_12 : _io_acc_read_req_0_bits_addr_T_2; // @[Mux.scala:126:16]
wire [11:0] _io_acc_read_req_0_bits_addr_T_14 = read_b_from_acc ? _io_acc_read_req_0_bits_addr_T_5 : _io_acc_read_req_0_bits_addr_T_13; // @[Mux.scala:126:16]
wire [11:0] _io_acc_read_req_0_bits_addr_T_18 = read_d_from_acc ? _io_acc_read_req_0_bits_addr_T_17 : _io_acc_read_req_0_bits_addr_T_15; // @[Mux.scala:126:16]
assign _io_acc_read_req_0_bits_addr_T_19 = read_b_from_acc ? _io_acc_read_req_0_bits_addr_T_16 : _io_acc_read_req_0_bits_addr_T_18; // @[Mux.scala:126:16]
assign io_acc_read_req_0_bits_addr_0 = _io_acc_read_req_0_bits_addr_T_19; // @[Mux.scala:126:16]
wire _read_a_T_40 = a_valid & start_inputting_a; // @[ExecuteController.scala:267:35, :356:5, :506:26]
wire _read_a_T_41 = ~multiply_garbage; // @[LocalAddr.scala:43:96]
wire _read_a_T_42 = _read_a_T_40 & _read_a_T_41; // @[ExecuteController.scala:506:{26,47,50}]
wire _read_a_T_43 = _read_a_T_42; // @[ExecuteController.scala:506:{47,68}]
assign a_ready = ~(read_a_from_acc & ~io_acc_read_req_0_ready_0 | read_a_3 & ~io_srams_read_3_req_ready_0 | read_a_2 & ~io_srams_read_2_req_ready_0 | read_a_1 & ~io_srams_read_1_req_ready_0) & ~(read_a & ~io_srams_read_0_req_ready_0); // @[ExecuteController.scala:12:7, :329:25, :424:135, :429:{16,19,48}, :430:11, :458:146, :463:{15,18,45}, :464:11, :508:43, :509:15]
wire _T_95 = control_state == 2'h0; // @[ExecuteController.scala:74:30, :532:26]
wire _T_100 = DoConfig & ~matmul_in_progress & ~(pending_completed_rob_ids_0_valid | pending_completed_rob_ids_1_valid); // @[ExecuteController.scala:83:28, :175:38, :230:82, :541:{23,26,46,49,98}]
wire [31:0] _config_ex_rs1_T_9; // @[ExecuteController.scala:542:47]
wire [15:0] _config_ex_rs1_T_8; // @[ExecuteController.scala:542:47]
wire [5:0] _config_ex_rs1_T_7; // @[ExecuteController.scala:542:47]
wire _config_ex_rs1_T_6; // @[ExecuteController.scala:542:47]
wire _config_ex_rs1_T_5; // @[ExecuteController.scala:542:47]
wire _config_ex_rs1_T_4; // @[ExecuteController.scala:542:47]
wire [1:0] _config_ex_rs1_T_3; // @[ExecuteController.scala:542:47]
wire [1:0] _config_ex_rs1_T_2; // @[ExecuteController.scala:542:47]
wire _config_ex_rs1_T_1; // @[ExecuteController.scala:542:47]
wire [1:0] _config_ex_rs1_T; // @[ExecuteController.scala:542:47]
wire [31:0] config_ex_rs1_acc_scale; // @[ExecuteController.scala:542:47]
wire [15:0] config_ex_rs1_a_stride; // @[ExecuteController.scala:542:47]
wire [5:0] config_ex_rs1__spacer1; // @[ExecuteController.scala:542:47]
wire config_ex_rs1_b_transpose; // @[ExecuteController.scala:542:47]
wire config_ex_rs1_a_transpose; // @[ExecuteController.scala:542:47]
wire config_ex_rs1_set_only_strides; // @[ExecuteController.scala:542:47]
wire [1:0] config_ex_rs1__spacer0; // @[ExecuteController.scala:542:47]
wire [1:0] config_ex_rs1_activation; // @[ExecuteController.scala:542:47]
wire config_ex_rs1_dataflow; // @[ExecuteController.scala:542:47]
wire [1:0] config_ex_rs1_cmd_type; // @[ExecuteController.scala:542:47]
assign _config_ex_rs1_T = _config_ex_rs1_WIRE[1:0]; // @[ExecuteController.scala:542:47]
assign config_ex_rs1_cmd_type = _config_ex_rs1_T; // @[ExecuteController.scala:542:47]
assign _config_ex_rs1_T_1 = _config_ex_rs1_WIRE[2]; // @[ExecuteController.scala:542:47]
assign config_ex_rs1_dataflow = _config_ex_rs1_T_1; // @[ExecuteController.scala:542:47]
assign _config_ex_rs1_T_2 = _config_ex_rs1_WIRE[4:3]; // @[ExecuteController.scala:542:47]
assign config_ex_rs1_activation = _config_ex_rs1_T_2; // @[ExecuteController.scala:542:47]
assign _config_ex_rs1_T_3 = _config_ex_rs1_WIRE[6:5]; // @[ExecuteController.scala:542:47]
assign config_ex_rs1__spacer0 = _config_ex_rs1_T_3; // @[ExecuteController.scala:542:47]
assign _config_ex_rs1_T_4 = _config_ex_rs1_WIRE[7]; // @[ExecuteController.scala:542:47]
assign config_ex_rs1_set_only_strides = _config_ex_rs1_T_4; // @[ExecuteController.scala:542:47]
assign _config_ex_rs1_T_5 = _config_ex_rs1_WIRE[8]; // @[ExecuteController.scala:542:47]
assign config_ex_rs1_a_transpose = _config_ex_rs1_T_5; // @[ExecuteController.scala:542:47]
assign _config_ex_rs1_T_6 = _config_ex_rs1_WIRE[9]; // @[ExecuteController.scala:542:47]
assign config_ex_rs1_b_transpose = _config_ex_rs1_T_6; // @[ExecuteController.scala:542:47]
assign _config_ex_rs1_T_7 = _config_ex_rs1_WIRE[15:10]; // @[ExecuteController.scala:542:47]
assign config_ex_rs1__spacer1 = _config_ex_rs1_T_7; // @[ExecuteController.scala:542:47]
assign _config_ex_rs1_T_8 = _config_ex_rs1_WIRE[31:16]; // @[ExecuteController.scala:542:47]
assign config_ex_rs1_a_stride = _config_ex_rs1_T_8; // @[ExecuteController.scala:542:47]
assign _config_ex_rs1_T_9 = _config_ex_rs1_WIRE[63:32]; // @[ExecuteController.scala:542:47]
assign config_ex_rs1_acc_scale = _config_ex_rs1_T_9; // @[ExecuteController.scala:542:47]
wire [15:0] _config_ex_rs2_T_2; // @[ExecuteController.scala:543:47]
wire [15:0] _config_ex_rs2_T_1; // @[ExecuteController.scala:543:47]
wire [31:0] _config_ex_rs2_T; // @[ExecuteController.scala:543:47]
wire [15:0] config_ex_rs2_c_stride; // @[ExecuteController.scala:543:47]
wire [15:0] config_ex_rs2_relu6_shift; // @[ExecuteController.scala:543:47]
wire [31:0] config_ex_rs2_in_shift; // @[ExecuteController.scala:543:47]
assign _config_ex_rs2_T = _config_ex_rs2_WIRE[31:0]; // @[ExecuteController.scala:543:47]
assign config_ex_rs2_in_shift = _config_ex_rs2_T; // @[ExecuteController.scala:543:47]
assign _config_ex_rs2_T_1 = _config_ex_rs2_WIRE[47:32]; // @[ExecuteController.scala:543:47]
assign config_ex_rs2_relu6_shift = _config_ex_rs2_T_1; // @[ExecuteController.scala:543:47]
assign _config_ex_rs2_T_2 = _config_ex_rs2_WIRE[63:48]; // @[ExecuteController.scala:543:47]
assign config_ex_rs2_c_stride = _config_ex_rs2_T_2; // @[ExecuteController.scala:543:47]
wire [1:0] config_cmd_type = rs1s_0[1:0]; // @[ExecuteController.scala:80:21, :545:40]
wire [31:0] _acc_scale_T = rs1s_0[63:32]; // @[ExecuteController.scala:80:21, :555:35]
wire [31:0] _acc_scale_WIRE_1 = _acc_scale_T; // @[ExecuteController.scala:555:{35,58}]
wire [31:0] _acc_scale_T_1; // @[ExecuteController.scala:555:58]
assign _acc_scale_T_1 = _acc_scale_WIRE_1; // @[ExecuteController.scala:555:58]
wire [31:0] _acc_scale_WIRE_bits = _acc_scale_T_1; // @[ExecuteController.scala:555:58]
wire [7:0] _ocol_T = _cmd_q_io_deq_bits_0_cmd_rs2[63:56]; // @[MultiHeadedQueue.scala:53:19]
wire _GEN_69 = _cmd_q_io_deq_valid_0 & _T_100; // @[MultiHeadedQueue.scala:53:19]
wire _GEN_70 = _T_95 & _GEN_69; // @[ExecuteController.scala:97:21, :532:26, :540:7, :541:105, :547:48]
wire [7:0] _kdim2_T = _cmd_q_io_deq_bits_0_cmd_rs2[55:48]; // @[MultiHeadedQueue.scala:53:19]
wire [3:0] _krow_T = _cmd_q_io_deq_bits_0_cmd_rs2[47:44]; // @[MultiHeadedQueue.scala:53:19]
wire [8:0] _channel_T = _cmd_q_io_deq_bits_0_cmd_rs2[31:23]; // @[MultiHeadedQueue.scala:53:19]
wire [2:0] _weight_stride_T = _cmd_q_io_deq_bits_0_cmd_rs2[22:20]; // @[MultiHeadedQueue.scala:53:19]
wire _weight_double_bank_T = _cmd_q_io_deq_bits_0_cmd_rs1[58]; // @[MultiHeadedQueue.scala:53:19]
wire _weight_triple_bank_T = _cmd_q_io_deq_bits_0_cmd_rs1[59]; // @[MultiHeadedQueue.scala:53:19]
wire [3:0] _row_left_T = _cmd_q_io_deq_bits_0_cmd_rs1[57:54]; // @[MultiHeadedQueue.scala:53:19]
wire [11:0] _row_turn_T = _cmd_q_io_deq_bits_0_cmd_rs1[53:42]; // @[MultiHeadedQueue.scala:53:19]
wire _GEN_71 = _GEN_70 & _cmd_q_io_deq_bits_0_rob_id_valid; // @[MultiHeadedQueue.scala:53:19]
wire _T_106 = DoPreloads_0 & _cmd_q_io_deq_valid_1 & ~raw_hazard_pre; // @[MultiHeadedQueue.scala:53:19]
wire _GEN_72 = _T_95 & _cmd_q_io_deq_valid_0; // @[MultiHeadedQueue.scala:53:19]
assign performing_single_preload = _GEN_72 & ~_T_100 & _T_106 | _performing_single_preload_T_1; // @[ExecuteController.scala:281:{43,67}, :532:26, :535:30, :540:7, :541:{23,46,105}, :585:{33,49,103}]
wire _T_113 = DoComputes_0 & _cmd_q_io_deq_valid_1 & DoPreloads_1 & _cmd_q_io_deq_valid_2 & ~raw_hazard_mulpre; // @[MultiHeadedQueue.scala:53:19]
wire _GEN_73 = _T_100 | _T_106; // @[ExecuteController.scala:536:23, :541:{23,46,105}, :585:{33,49,103}, :601:9]
assign performing_mul_pre = _GEN_72 & ~_GEN_73 & _T_113 | _performing_mul_pre_T_1; // @[ExecuteController.scala:281:43, :283:{36,53}, :532:26, :536:23, :540:7, :541:105, :585:103, :600:{33,49,66,113}, :601:9]
wire _GEN_74 = _T_100 | _T_106 | _T_113; // @[ExecuteController.scala:537:26, :541:{23,46,105}, :585:{33,49,103}, :600:{33,49,66,113}, :601:9, :613:34]
assign performing_single_mul = _GEN_72 & ~_GEN_74 & DoComputes_0 | _performing_single_mul_T_1; // @[ExecuteController.scala:84:63, :281:43, :282:{39,59}, :532:26, :537:26, :540:7, :541:105, :585:103, :601:9, :613:34]
wire _start_inputting_a_T = ~a_should_be_fed_into_transposer; // @[ExecuteController.scala:123:44, :289:5, :617:32]
wire _start_inputting_b_T = ~b_should_be_fed_into_transposer; // @[ExecuteController.scala:126:79, :289:41, :618:32]
wire _GEN_75 = c_address_rs2_is_acc_addr & c_address_rs2_accumulate; // @[LocalAddr.scala:43:48]
wire _pending_completed_rob_ids_0_valid_T; // @[LocalAddr.scala:43:48]
assign _pending_completed_rob_ids_0_valid_T = _GEN_75; // @[LocalAddr.scala:43:48]
wire _pending_completed_rob_ids_1_valid_T; // @[LocalAddr.scala:43:48]
assign _pending_completed_rob_ids_1_valid_T = _GEN_75; // @[LocalAddr.scala:43:48]
wire _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_1; // @[LocalAddr.scala:43:48]
assign _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_1 = _GEN_75; // @[LocalAddr.scala:43:48]
wire _pending_completed_rob_ids_0_valid_T_1 = _pending_completed_rob_ids_0_valid_T & c_address_rs2_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _pending_completed_rob_ids_0_valid_T_2 = &c_address_rs2_data; // @[LocalAddr.scala:43:91]
wire _pending_completed_rob_ids_0_valid_T_3 = _pending_completed_rob_ids_0_valid_T_1 & _pending_completed_rob_ids_0_valid_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire _pending_completed_rob_ids_0_valid_T_5 = _pending_completed_rob_ids_0_valid_T_3 & _pending_completed_rob_ids_0_valid_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _pending_completed_rob_ids_0_valid_T_6 = _cmd_q_io_deq_bits_0_rob_id_valid & _pending_completed_rob_ids_0_valid_T_5; // @[MultiHeadedQueue.scala:53:19]
wire _in_prop_flush_qual1_T_6; // @[ExecuteController.scala:647:47]
wire _in_prop_flush_qual1_T_5; // @[ExecuteController.scala:647:47]
wire _in_prop_flush_qual1_T_4; // @[ExecuteController.scala:647:47]
wire [2:0] _in_prop_flush_qual1_WIRE_2; // @[ExecuteController.scala:647:47]
wire [10:0] _in_prop_flush_qual1_T_2; // @[ExecuteController.scala:647:47]
wire _in_prop_flush_qual1_T_1; // @[ExecuteController.scala:647:47]
wire [13:0] _in_prop_flush_qual1_T; // @[ExecuteController.scala:647:47]
wire _in_prop_flush_T_4 = in_prop_flush_qual1_garbage_bit; // @[LocalAddr.scala:44:48]
wire in_prop_flush_qual1_is_acc_addr; // @[ExecuteController.scala:647:47]
wire in_prop_flush_qual1_accumulate; // @[ExecuteController.scala:647:47]
wire in_prop_flush_qual1_read_full_acc_row; // @[ExecuteController.scala:647:47]
wire [2:0] in_prop_flush_qual1_norm_cmd; // @[ExecuteController.scala:647:47]
wire [10:0] in_prop_flush_qual1_garbage; // @[ExecuteController.scala:647:47]
wire [13:0] in_prop_flush_qual1_data; // @[ExecuteController.scala:647:47]
wire [31:0] _in_prop_flush_qual1_WIRE = rs2s_0[31:0]; // @[ExecuteController.scala:81:21, :647:47]
assign _in_prop_flush_qual1_T = _in_prop_flush_qual1_WIRE[13:0]; // @[ExecuteController.scala:647:47]
assign in_prop_flush_qual1_data = _in_prop_flush_qual1_T; // @[ExecuteController.scala:647:47]
assign _in_prop_flush_qual1_T_1 = _in_prop_flush_qual1_WIRE[14]; // @[ExecuteController.scala:647:47]
assign in_prop_flush_qual1_garbage_bit = _in_prop_flush_qual1_T_1; // @[ExecuteController.scala:647:47]
assign _in_prop_flush_qual1_T_2 = _in_prop_flush_qual1_WIRE[25:15]; // @[ExecuteController.scala:647:47]
assign in_prop_flush_qual1_garbage = _in_prop_flush_qual1_T_2; // @[ExecuteController.scala:647:47]
wire [2:0] _in_prop_flush_qual1_T_3 = _in_prop_flush_qual1_WIRE[28:26]; // @[ExecuteController.scala:647:47]
wire [2:0] _in_prop_flush_qual1_WIRE_1 = _in_prop_flush_qual1_T_3; // @[ExecuteController.scala:647:47]
assign _in_prop_flush_qual1_WIRE_2 = _in_prop_flush_qual1_WIRE_1; // @[ExecuteController.scala:647:47]
assign in_prop_flush_qual1_norm_cmd = _in_prop_flush_qual1_WIRE_2; // @[ExecuteController.scala:647:47]
assign _in_prop_flush_qual1_T_4 = _in_prop_flush_qual1_WIRE[29]; // @[ExecuteController.scala:647:47]
assign in_prop_flush_qual1_read_full_acc_row = _in_prop_flush_qual1_T_4; // @[ExecuteController.scala:647:47]
assign _in_prop_flush_qual1_T_5 = _in_prop_flush_qual1_WIRE[30]; // @[ExecuteController.scala:647:47]
assign in_prop_flush_qual1_accumulate = _in_prop_flush_qual1_T_5; // @[ExecuteController.scala:647:47]
assign _in_prop_flush_qual1_T_6 = _in_prop_flush_qual1_WIRE[31]; // @[ExecuteController.scala:647:47]
assign in_prop_flush_qual1_is_acc_addr = _in_prop_flush_qual1_T_6; // @[ExecuteController.scala:647:47]
wire _in_prop_flush_T = in_prop_flush_qual1_is_acc_addr & in_prop_flush_qual1_accumulate; // @[LocalAddr.scala:43:48]
wire _in_prop_flush_T_1 = _in_prop_flush_T & in_prop_flush_qual1_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _in_prop_flush_T_2 = &in_prop_flush_qual1_data; // @[LocalAddr.scala:43:91]
wire _in_prop_flush_T_3 = _in_prop_flush_T_1 & _in_prop_flush_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire _in_prop_flush_T_5 = _in_prop_flush_T_3 & _in_prop_flush_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _in_prop_flush_T_6 = ~_in_prop_flush_T_5; // @[LocalAddr.scala:43:96]
assign start_inputting_d = _T_95 ? _cmd_q_io_deq_valid_0 & ~_T_100 & (_T_106 | _T_113) : _T_200 & (perform_single_preload | perform_mul_pre); // @[MultiHeadedQueue.scala:53:19]
wire _pending_completed_rob_ids_1_valid_T_1 = _pending_completed_rob_ids_1_valid_T & c_address_rs2_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _pending_completed_rob_ids_1_valid_T_2 = &c_address_rs2_data; // @[LocalAddr.scala:43:91]
wire _pending_completed_rob_ids_1_valid_T_3 = _pending_completed_rob_ids_1_valid_T_1 & _pending_completed_rob_ids_1_valid_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire _pending_completed_rob_ids_1_valid_T_5 = _pending_completed_rob_ids_1_valid_T_3 & _pending_completed_rob_ids_1_valid_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _pending_completed_rob_ids_1_valid_T_6 = _cmd_q_io_deq_bits_1_rob_id_valid & _pending_completed_rob_ids_1_valid_T_5; // @[MultiHeadedQueue.scala:53:19]
wire _in_prop_flush_qual2_T_6; // @[ExecuteController.scala:666:47]
wire _in_prop_flush_qual2_T_5; // @[ExecuteController.scala:666:47]
wire _in_prop_flush_qual2_T_4; // @[ExecuteController.scala:666:47]
wire [2:0] _in_prop_flush_qual2_WIRE_2; // @[ExecuteController.scala:666:47]
wire [10:0] _in_prop_flush_qual2_T_2; // @[ExecuteController.scala:666:47]
wire _in_prop_flush_qual2_T_1; // @[ExecuteController.scala:666:47]
wire [13:0] _in_prop_flush_qual2_T; // @[ExecuteController.scala:666:47]
wire _in_prop_flush_T_11 = in_prop_flush_qual2_garbage_bit; // @[LocalAddr.scala:44:48]
wire in_prop_flush_qual2_is_acc_addr; // @[ExecuteController.scala:666:47]
wire in_prop_flush_qual2_accumulate; // @[ExecuteController.scala:666:47]
wire in_prop_flush_qual2_read_full_acc_row; // @[ExecuteController.scala:666:47]
wire [2:0] in_prop_flush_qual2_norm_cmd; // @[ExecuteController.scala:666:47]
wire [10:0] in_prop_flush_qual2_garbage; // @[ExecuteController.scala:666:47]
wire [13:0] in_prop_flush_qual2_data; // @[ExecuteController.scala:666:47]
assign _in_prop_flush_qual2_T = _in_prop_flush_qual2_WIRE[13:0]; // @[ExecuteController.scala:666:47]
assign in_prop_flush_qual2_data = _in_prop_flush_qual2_T; // @[ExecuteController.scala:666:47]
assign _in_prop_flush_qual2_T_1 = _in_prop_flush_qual2_WIRE[14]; // @[ExecuteController.scala:666:47]
assign in_prop_flush_qual2_garbage_bit = _in_prop_flush_qual2_T_1; // @[ExecuteController.scala:666:47]
assign _in_prop_flush_qual2_T_2 = _in_prop_flush_qual2_WIRE[25:15]; // @[ExecuteController.scala:666:47]
assign in_prop_flush_qual2_garbage = _in_prop_flush_qual2_T_2; // @[ExecuteController.scala:666:47]
wire [2:0] _in_prop_flush_qual2_T_3 = _in_prop_flush_qual2_WIRE[28:26]; // @[ExecuteController.scala:666:47]
wire [2:0] _in_prop_flush_qual2_WIRE_1 = _in_prop_flush_qual2_T_3; // @[ExecuteController.scala:666:47]
assign _in_prop_flush_qual2_WIRE_2 = _in_prop_flush_qual2_WIRE_1; // @[ExecuteController.scala:666:47]
assign in_prop_flush_qual2_norm_cmd = _in_prop_flush_qual2_WIRE_2; // @[ExecuteController.scala:666:47]
assign _in_prop_flush_qual2_T_4 = _in_prop_flush_qual2_WIRE[29]; // @[ExecuteController.scala:666:47]
assign in_prop_flush_qual2_read_full_acc_row = _in_prop_flush_qual2_T_4; // @[ExecuteController.scala:666:47]
assign _in_prop_flush_qual2_T_5 = _in_prop_flush_qual2_WIRE[30]; // @[ExecuteController.scala:666:47]
assign in_prop_flush_qual2_accumulate = _in_prop_flush_qual2_T_5; // @[ExecuteController.scala:666:47]
assign _in_prop_flush_qual2_T_6 = _in_prop_flush_qual2_WIRE[31]; // @[ExecuteController.scala:666:47]
assign in_prop_flush_qual2_is_acc_addr = _in_prop_flush_qual2_T_6; // @[ExecuteController.scala:666:47]
wire _in_prop_flush_T_7 = in_prop_flush_qual2_is_acc_addr & in_prop_flush_qual2_accumulate; // @[LocalAddr.scala:43:48]
wire _in_prop_flush_T_8 = _in_prop_flush_T_7 & in_prop_flush_qual2_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _in_prop_flush_T_9 = &in_prop_flush_qual2_data; // @[LocalAddr.scala:43:91]
wire _in_prop_flush_T_10 = _in_prop_flush_T_8 & _in_prop_flush_T_9; // @[LocalAddr.scala:43:{62,83,91}]
wire _in_prop_flush_T_12 = _in_prop_flush_T_10 & _in_prop_flush_T_11; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _in_prop_flush_T_13 = ~_in_prop_flush_T_12; // @[LocalAddr.scala:43:96]
wire _start_inputting_a_T_1 = ~a_should_be_fed_into_transposer; // @[ExecuteController.scala:123:44, :289:5, :672:30]
assign start_inputting_a = _T_95 ? _cmd_q_io_deq_valid_0 & ~_T_100 & (_T_106 ? a_should_be_fed_into_transposer : _T_113 | DoComputes_0 & _start_inputting_a_T) : _T_200 & (perform_single_preload ? a_should_be_fed_into_transposer : perform_mul_pre | perform_single_mul & _start_inputting_a_T_1); // @[MultiHeadedQueue.scala:53:19]
wire _start_inputting_b_T_1 = ~b_should_be_fed_into_transposer; // @[ExecuteController.scala:126:79, :289:41, :673:30]
assign start_inputting_b = _T_95 ? _cmd_q_io_deq_valid_0 & ~_T_100 & (_T_106 ? b_should_be_fed_into_transposer : _T_113 | DoComputes_0 & _start_inputting_b_T) : _T_200 & (perform_single_preload ? b_should_be_fed_into_transposer : perform_mul_pre | perform_single_mul & _start_inputting_b_T_1); // @[MultiHeadedQueue.scala:53:19]
wire _computing_T = performing_mul_pre | performing_single_mul; // @[ExecuteController.scala:282:39, :283:36, :696:38]
wire computing = _computing_T | performing_single_preload; // @[ExecuteController.scala:281:43, :696:{38,63}]
wire [2:0] _mesh_cntl_signals_q_io_enq_bits_a_unpadded_cols_T = a_row_is_not_all_zeros ? a_cols : 3'h0; // @[ExecuteController.scala:161:19, :310:47, :775:57]
wire [2:0] _mesh_cntl_signals_q_io_enq_bits_b_unpadded_cols_T = b_row_is_not_all_zeros ? b_cols : 3'h0; // @[ExecuteController.scala:163:19, :311:47, :776:57]
wire [2:0] _mesh_cntl_signals_q_io_enq_bits_d_unpadded_cols_T = d_row_is_not_all_zeros ? d_cols : 3'h0; // @[ExecuteController.scala:165:19, :312:68, :777:57]
wire _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T = ~performing_single_mul; // @[ExecuteController.scala:282:39, :792:51]
wire _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_2 = _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_1 & c_address_rs2_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_3 = &c_address_rs2_data; // @[LocalAddr.scala:43:91]
wire _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_4 = _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_2 & _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_3; // @[LocalAddr.scala:43:{62,83,91}]
wire _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_6 = _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_4 & _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_5; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_7 = ~_mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_6; // @[LocalAddr.scala:43:96]
wire _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_8 = _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T & _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_7; // @[ExecuteController.scala:792:{51,74,77}]
wire [3:0][5:0] _GEN_76 = {{_cmd_q_io_deq_bits_0_rob_id_bits}, {_cmd_q_io_deq_bits_2_rob_id_bits}, {_cmd_q_io_deq_bits_1_rob_id_bits}, {_cmd_q_io_deq_bits_0_rob_id_bits}}; // @[MultiHeadedQueue.scala:53:19]
wire _mesh_cntl_signals_q_io_enq_bits_prop_T = performing_single_preload ? in_prop_flush : in_prop; // @[ExecuteController.scala:90:27, :92:26, :281:43, :796:46]
wire _mesh_cntl_signals_q_io_enq_bits_first_T = ~a_fire_started; // @[ExecuteController.scala:240:31, :801:44]
wire _mesh_cntl_signals_q_io_enq_bits_first_T_1 = ~b_fire_started; // @[ExecuteController.scala:242:31, :801:63]
wire _mesh_cntl_signals_q_io_enq_bits_first_T_2 = _mesh_cntl_signals_q_io_enq_bits_first_T & _mesh_cntl_signals_q_io_enq_bits_first_T_1; // @[ExecuteController.scala:801:{44,60,63}]
wire _mesh_cntl_signals_q_io_enq_bits_first_T_3 = ~d_fire_started; // @[ExecuteController.scala:241:31, :801:82]
wire _mesh_cntl_signals_q_io_enq_bits_first_T_4 = _mesh_cntl_signals_q_io_enq_bits_first_T_2 & _mesh_cntl_signals_q_io_enq_bits_first_T_3; // @[ExecuteController.scala:801:{60,79,82}]
wire [63:0] accReadData_lo = {io_acc_read_resp_0_bits_data_1_0_bits_0, io_acc_read_resp_0_bits_data_0_0_bits_0}; // @[ExecuteController.scala:12:7, :804:84]
wire [63:0] accReadData_hi = {io_acc_read_resp_0_bits_data_3_0_bits_0, io_acc_read_resp_0_bits_data_2_0_bits_0}; // @[ExecuteController.scala:12:7, :804:84]
wire [127:0] _accReadData_T = {accReadData_hi, accReadData_lo}; // @[ExecuteController.scala:804:84]
wire [127:0] accReadData_0 = _accReadData_T; // @[ExecuteController.scala:804:{50,84}]
wire [63:0] im2ColData_lo = {io_im2col_resp_bits_a_im2col_1_bits_0, io_im2col_resp_bits_a_im2col_0_bits_0}; // @[ExecuteController.scala:12:7, :805:49]
wire [63:0] im2ColData_hi = {io_im2col_resp_bits_a_im2col_3_bits_0, io_im2col_resp_bits_a_im2col_2_bits_0}; // @[ExecuteController.scala:12:7, :805:49]
wire [127:0] im2ColData = {im2ColData_hi, im2ColData_lo}; // @[ExecuteController.scala:805:49]
wire _readValid_T_1 = ~io_srams_read_0_resp_bits_fromDMA_0; // @[ExecuteController.scala:12:7, :807:95]
wire _readValid_T_2 = _readValid_T & _readValid_T_1; // @[ExecuteController.scala:807:{73,92,95}]
wire readValid_0 = _readValid_T_2; // @[ExecuteController.scala:807:{26,92}]
wire _readValid_T_4 = ~io_srams_read_1_resp_bits_fromDMA_0; // @[ExecuteController.scala:12:7, :807:95]
wire _readValid_T_5 = _readValid_T_3 & _readValid_T_4; // @[ExecuteController.scala:807:{73,92,95}]
wire readValid_1 = _readValid_T_5; // @[ExecuteController.scala:807:{26,92}]
wire _readValid_T_7 = ~io_srams_read_2_resp_bits_fromDMA_0; // @[ExecuteController.scala:12:7, :807:95]
wire _readValid_T_8 = _readValid_T_6 & _readValid_T_7; // @[ExecuteController.scala:807:{73,92,95}]
wire readValid_2 = _readValid_T_8; // @[ExecuteController.scala:807:{26,92}]
wire _readValid_T_10 = ~io_srams_read_3_resp_bits_fromDMA_0; // @[ExecuteController.scala:12:7, :807:95]
wire _readValid_T_11 = _readValid_T_9 & _readValid_T_10; // @[ExecuteController.scala:807:{73,92,95}]
wire readValid_3 = _readValid_T_11; // @[ExecuteController.scala:807:{26,92}]
wire _accReadValid_T_1 = ~io_acc_read_resp_0_bits_fromDMA_0; // @[ExecuteController.scala:12:7, :808:95]
wire _accReadValid_T_2 = _accReadValid_T & _accReadValid_T_1; // @[ExecuteController.scala:808:{78,92,95}]
wire accReadValid_0 = _accReadValid_T_2; // @[ExecuteController.scala:808:{29,92}]
wire _mesh_cntl_signals_q_io_deq_ready_T = ~_mesh_cntl_signals_q_io_deq_bits_a_fire; // @[ExecuteController.scala:178:35, :811:40]
wire _mesh_cntl_signals_q_io_deq_ready_T_1 = _mesh_io_a_ready & mesh_io_a_valid; // @[Decoupled.scala:51:35]
wire _mesh_cntl_signals_q_io_deq_ready_T_2 = _mesh_cntl_signals_q_io_deq_ready_T | _mesh_cntl_signals_q_io_deq_ready_T_1; // @[Decoupled.scala:51:35]
wire _mesh_cntl_signals_q_io_deq_ready_T_3 = ~_mesh_io_a_ready; // @[ExecuteController.scala:186:20, :811:74]
wire _mesh_cntl_signals_q_io_deq_ready_T_4 = _mesh_cntl_signals_q_io_deq_ready_T_2 | _mesh_cntl_signals_q_io_deq_ready_T_3; // @[ExecuteController.scala:811:{53,71,74}]
wire _mesh_cntl_signals_q_io_deq_ready_T_5 = ~_mesh_cntl_signals_q_io_deq_bits_b_fire; // @[ExecuteController.scala:178:35, :812:6]
wire _mesh_cntl_signals_q_io_deq_ready_T_6 = _mesh_io_b_ready & mesh_io_b_valid; // @[Decoupled.scala:51:35]
wire _mesh_cntl_signals_q_io_deq_ready_T_7 = _mesh_cntl_signals_q_io_deq_ready_T_5 | _mesh_cntl_signals_q_io_deq_ready_T_6; // @[Decoupled.scala:51:35]
wire _mesh_cntl_signals_q_io_deq_ready_T_8 = ~_mesh_io_b_ready; // @[ExecuteController.scala:186:20, :812:40]
wire _mesh_cntl_signals_q_io_deq_ready_T_9 = _mesh_cntl_signals_q_io_deq_ready_T_7 | _mesh_cntl_signals_q_io_deq_ready_T_8; // @[ExecuteController.scala:812:{19,37,40}]
wire _mesh_cntl_signals_q_io_deq_ready_T_10 = _mesh_cntl_signals_q_io_deq_ready_T_4 & _mesh_cntl_signals_q_io_deq_ready_T_9; // @[ExecuteController.scala:811:{71,92}, :812:37]
wire _mesh_cntl_signals_q_io_deq_ready_T_11 = ~_mesh_cntl_signals_q_io_deq_bits_d_fire; // @[ExecuteController.scala:178:35, :813:6]
wire _mesh_cntl_signals_q_io_deq_ready_T_12 = _mesh_io_d_ready & mesh_io_d_valid; // @[Decoupled.scala:51:35]
wire _mesh_cntl_signals_q_io_deq_ready_T_13 = _mesh_cntl_signals_q_io_deq_ready_T_11 | _mesh_cntl_signals_q_io_deq_ready_T_12; // @[Decoupled.scala:51:35]
wire _mesh_cntl_signals_q_io_deq_ready_T_14 = ~_mesh_io_d_ready; // @[ExecuteController.scala:186:20, :813:40]
wire _mesh_cntl_signals_q_io_deq_ready_T_15 = _mesh_cntl_signals_q_io_deq_ready_T_13 | _mesh_cntl_signals_q_io_deq_ready_T_14; // @[ExecuteController.scala:813:{19,37,40}]
wire _mesh_cntl_signals_q_io_deq_ready_T_16 = _mesh_cntl_signals_q_io_deq_ready_T_10 & _mesh_cntl_signals_q_io_deq_ready_T_15; // @[ExecuteController.scala:811:92, :812:58, :813:37]
wire _mesh_cntl_signals_q_io_deq_ready_T_17 = ~_mesh_cntl_signals_q_io_deq_bits_first; // @[ExecuteController.scala:178:35, :814:6]
wire _mesh_cntl_signals_q_io_deq_ready_T_18 = _mesh_cntl_signals_q_io_deq_ready_T_17 | _mesh_io_req_ready; // @[ExecuteController.scala:186:20, :814:{6,18}]
wire _mesh_cntl_signals_q_io_deq_ready_T_19 = _mesh_cntl_signals_q_io_deq_ready_T_16 & _mesh_cntl_signals_q_io_deq_ready_T_18; // @[ExecuteController.scala:812:58, :813:58, :814:18]
wire _dataA_valid_T = _mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols == 3'h0; // @[ExecuteController.scala:178:35, :816:60]
wire _dataA_valid_T_1 = _mesh_cntl_signals_q_io_deq_bits_a_garbage | _dataA_valid_T; // @[ExecuteController.scala:178:35, :816:{36,60}]
wire [3:0] _GEN_77 = {{readValid_3}, {readValid_2}, {readValid_1}, {readValid_0}}; // @[ExecuteController.scala:807:26, :816:108]
wire _dataA_valid_T_2 = _mesh_cntl_signals_q_io_deq_bits_a_read_from_acc ? accReadValid_0 : _GEN_77[_mesh_cntl_signals_q_io_deq_bits_a_bank]; // @[ExecuteController.scala:178:35, :808:29, :816:108]
wire _dataA_valid_T_3 = ~_mesh_cntl_signals_q_io_deq_bits_im2colling & _dataA_valid_T_2; // @[ExecuteController.scala:178:35, :816:{74,108}]
wire dataA_valid = _dataA_valid_T_1 | _dataA_valid_T_3; // @[ExecuteController.scala:816:{36,68,74}]
wire _dataB_valid_T = _mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols == 3'h0; // @[ExecuteController.scala:178:35, :818:60]
wire _dataB_valid_T_1 = _mesh_cntl_signals_q_io_deq_bits_b_garbage | _dataB_valid_T; // @[ExecuteController.scala:178:35, :818:{36,60}]
wire _dataB_valid_T_2 = _mesh_cntl_signals_q_io_deq_bits_b_read_from_acc ? accReadValid_0 : _GEN_77[_mesh_cntl_signals_q_io_deq_bits_b_bank]; // @[Mux.scala:126:16]
wire _dataB_valid_T_3 = ~_mesh_cntl_signals_q_io_deq_bits_accumulate_zeros & _dataB_valid_T_2; // @[Mux.scala:126:16]
wire dataB_valid = _dataB_valid_T_1 | _dataB_valid_T_3; // @[Mux.scala:126:16]
wire _dataD_valid_T = _mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols == 3'h0; // @[ExecuteController.scala:178:35, :822:60]
wire _dataD_valid_T_1 = _mesh_cntl_signals_q_io_deq_bits_d_garbage | _dataD_valid_T; // @[ExecuteController.scala:178:35, :822:{36,60}]
wire _dataD_valid_T_2 = _mesh_cntl_signals_q_io_deq_bits_d_read_from_acc ? accReadValid_0 : _GEN_77[_mesh_cntl_signals_q_io_deq_bits_d_bank]; // @[Mux.scala:126:16]
wire _dataD_valid_T_3 = ~_mesh_cntl_signals_q_io_deq_bits_preload_zeros & _dataD_valid_T_2; // @[Mux.scala:126:16]
wire dataD_valid = _dataD_valid_T_1 | _dataD_valid_T_3; // @[Mux.scala:126:16]
reg [4:0] preload_zero_counter; // @[ExecuteController.scala:828:37]
wire _preload_zero_counter_T = dataA_valid & dataD_valid; // @[ExecuteController.scala:816:68, :822:68, :830:92]
wire _preload_zero_counter_T_1 = _preload_zero_counter_T & _mesh_cntl_signals_q_io_deq_bits_preload_zeros; // @[ExecuteController.scala:178:35, :830:{92,107}]
wire _preload_zero_counter_T_2 = _mesh_cntl_signals_q_io_deq_bits_perform_single_preload | _mesh_cntl_signals_q_io_deq_bits_perform_mul_pre; // @[ExecuteController.scala:178:35, :830:161]
wire _preload_zero_counter_T_3 = _preload_zero_counter_T_1 & _preload_zero_counter_T_2; // @[ExecuteController.scala:830:{107,129,161}]
wire _preload_zero_counter_T_8 = ~_preload_zero_counter_T_7; // @[Util.scala:19:11]
wire [5:0] _GEN_78 = {1'h0, preload_zero_counter}; // @[Util.scala:27:15]
wire [5:0] _preload_zero_counter_T_10 = _GEN_78 + 6'h1; // @[Util.scala:27:15]
wire [4:0] _preload_zero_counter_T_11 = _preload_zero_counter_T_10[4:0]; // @[Util.scala:27:15]
wire _preload_zero_counter_T_12 = ~_preload_zero_counter_T_3; // @[Util.scala:28:8]
wire _preload_zero_counter_T_18 = preload_zero_counter > 5'h2; // @[Util.scala:30:10]
wire _preload_zero_counter_T_20 = _preload_zero_counter_T_18; // @[Util.scala:30:{10,27}]
wire [5:0] _preload_zero_counter_T_21 = 6'h3 - _GEN_78; // @[Util.scala:27:15, :30:54]
wire [4:0] _preload_zero_counter_T_22 = _preload_zero_counter_T_21[4:0]; // @[Util.scala:30:54]
wire [5:0] _preload_zero_counter_T_23 = 6'h1 - {1'h0, _preload_zero_counter_T_22}; // @[Util.scala:30:{47,54}]
wire [4:0] _preload_zero_counter_T_24 = _preload_zero_counter_T_23[4:0]; // @[Util.scala:30:47]
wire [5:0] _preload_zero_counter_T_25 = {1'h0, _preload_zero_counter_T_24} - 6'h1; // @[Util.scala:30:{47,59}]
wire [4:0] _preload_zero_counter_T_26 = _preload_zero_counter_T_25[4:0]; // @[Util.scala:30:59]
wire [4:0] _preload_zero_counter_T_27 = _preload_zero_counter_T_20 ? _preload_zero_counter_T_26 : _preload_zero_counter_T_11; // @[Mux.scala:126:16]
wire [4:0] _preload_zero_counter_T_28 = _preload_zero_counter_T_27; // @[Mux.scala:126:16]
wire [4:0] _preload_zero_counter_T_29 = _preload_zero_counter_T_12 ? preload_zero_counter : _preload_zero_counter_T_28; // @[Mux.scala:126:16]
wire [3:0][127:0] _GEN_79 = {{readData_3}, {readData_2}, {readData_1}, {readData_0}}; // @[ExecuteController.scala:803:25, :832:60]
wire [127:0] _dataA_unpadded_T = _mesh_cntl_signals_q_io_deq_bits_a_read_from_acc ? accReadData_0 : _GEN_79[_mesh_cntl_signals_q_io_deq_bits_a_bank]; // @[ExecuteController.scala:178:35, :804:50, :832:60]
wire [127:0] dataA_unpadded = _mesh_cntl_signals_q_io_deq_bits_im2colling ? im2ColData : _dataA_unpadded_T; // @[ExecuteController.scala:178:35, :805:49, :832:{27,60}]
wire [127:0] _dataA_WIRE_1 = dataA_unpadded; // @[ExecuteController.scala:832:27, :836:46]
wire [127:0] _dataB_unpadded_T = _mesh_cntl_signals_q_io_deq_bits_b_read_from_acc ? accReadData_0 : _GEN_79[_mesh_cntl_signals_q_io_deq_bits_b_bank]; // @[Mux.scala:126:16]
wire [127:0] dataB_unpadded = _mesh_cntl_signals_q_io_deq_bits_accumulate_zeros ? 128'h0 : _dataB_unpadded_T; // @[Mux.scala:126:16]
wire [127:0] _dataB_WIRE_1 = dataB_unpadded; // @[Mux.scala:126:16]
wire [127:0] _dataD_unpadded_T = _mesh_cntl_signals_q_io_deq_bits_d_read_from_acc ? accReadData_0 : _GEN_79[_mesh_cntl_signals_q_io_deq_bits_d_bank]; // @[Mux.scala:126:16]
wire [127:0] dataD_unpadded = _mesh_cntl_signals_q_io_deq_bits_preload_zeros ? 128'h0 : _dataD_unpadded_T; // @[Mux.scala:126:16]
wire [127:0] _dataD_WIRE_1 = dataD_unpadded; // @[Mux.scala:126:16]
wire [31:0] _dataA_T; // @[ExecuteController.scala:836:46]
wire [31:0] _dataA_T_1; // @[ExecuteController.scala:836:46]
wire [31:0] _dataA_T_2; // @[ExecuteController.scala:836:46]
wire [31:0] _dataA_T_3; // @[ExecuteController.scala:836:46]
assign _dataA_T = _dataA_WIRE_1[31:0]; // @[ExecuteController.scala:836:46]
wire [31:0] _dataA_WIRE_0_bits = _dataA_T; // @[ExecuteController.scala:836:46]
assign _dataA_T_1 = _dataA_WIRE_1[63:32]; // @[ExecuteController.scala:836:46]
wire [31:0] _dataA_WIRE_1_bits = _dataA_T_1; // @[ExecuteController.scala:836:46]
assign _dataA_T_2 = _dataA_WIRE_1[95:64]; // @[ExecuteController.scala:836:46]
wire [31:0] _dataA_WIRE_2_bits_0 = _dataA_T_2; // @[ExecuteController.scala:836:46]
assign _dataA_T_3 = _dataA_WIRE_1[127:96]; // @[ExecuteController.scala:836:46]
wire [31:0] _dataA_WIRE_3_bits_0 = _dataA_T_3; // @[ExecuteController.scala:836:46]
wire _dataA_T_4 = |_mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols; // @[ExecuteController.scala:178:35, :836:117]
wire [31:0] _dataA_T_5_bits = _dataA_T_4 ? _dataA_WIRE_0_bits : 32'h0; // @[ExecuteController.scala:836:{46,112,117}]
wire [31:0] dataA_0_bits = _dataA_T_5_bits; // @[ExecuteController.scala:836:{22,112}]
wire _dataA_T_6 = |(_mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols[2:1]); // @[ExecuteController.scala:178:35, :836:117]
wire [31:0] _dataA_T_7_bits = _dataA_T_6 ? _dataA_WIRE_1_bits : 32'h0; // @[ExecuteController.scala:836:{46,112,117}]
wire [31:0] dataA_1_bits = _dataA_T_7_bits; // @[ExecuteController.scala:836:{22,112}]
wire _dataA_T_8 = _mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols > 3'h2; // @[ExecuteController.scala:178:35, :836:117]
wire [31:0] _dataA_T_9_bits = _dataA_T_8 ? _dataA_WIRE_2_bits_0 : 32'h0; // @[ExecuteController.scala:836:{46,112,117}]
wire [31:0] dataA_2_bits = _dataA_T_9_bits; // @[ExecuteController.scala:836:{22,112}]
wire _dataA_T_10 = _mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols[2]; // @[ExecuteController.scala:178:35, :836:117]
wire [31:0] _dataA_T_11_bits = _dataA_T_10 ? _dataA_WIRE_3_bits_0 : 32'h0; // @[ExecuteController.scala:836:{46,112,117}]
wire [31:0] dataA_3_bits = _dataA_T_11_bits; // @[ExecuteController.scala:836:{22,112}]
wire [31:0] _dataB_T; // @[ExecuteController.scala:837:46]
wire [31:0] _dataB_T_1; // @[ExecuteController.scala:837:46]
wire [31:0] _dataB_T_2; // @[ExecuteController.scala:837:46]
wire [31:0] _dataB_T_3; // @[ExecuteController.scala:837:46]
assign _dataB_T = _dataB_WIRE_1[31:0]; // @[ExecuteController.scala:837:46]
wire [31:0] _dataB_WIRE_0_bits = _dataB_T; // @[ExecuteController.scala:837:46]
assign _dataB_T_1 = _dataB_WIRE_1[63:32]; // @[ExecuteController.scala:837:46]
wire [31:0] _dataB_WIRE_1_bits = _dataB_T_1; // @[ExecuteController.scala:837:46]
assign _dataB_T_2 = _dataB_WIRE_1[95:64]; // @[ExecuteController.scala:837:46]
wire [31:0] _dataB_WIRE_2_bits_0 = _dataB_T_2; // @[ExecuteController.scala:837:46]
assign _dataB_T_3 = _dataB_WIRE_1[127:96]; // @[ExecuteController.scala:837:46]
wire [31:0] _dataB_WIRE_3_bits_0 = _dataB_T_3; // @[ExecuteController.scala:837:46]
wire _dataB_T_4 = |_mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols; // @[ExecuteController.scala:178:35, :837:117]
wire [31:0] _dataB_T_5_bits = _dataB_T_4 ? _dataB_WIRE_0_bits : 32'h0; // @[ExecuteController.scala:837:{46,112,117}]
wire [31:0] dataB_0_bits = _dataB_T_5_bits; // @[ExecuteController.scala:837:{22,112}]
wire _dataB_T_6 = |(_mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols[2:1]); // @[ExecuteController.scala:178:35, :837:117]
wire [31:0] _dataB_T_7_bits = _dataB_T_6 ? _dataB_WIRE_1_bits : 32'h0; // @[ExecuteController.scala:837:{46,112,117}]
wire [31:0] dataB_1_bits = _dataB_T_7_bits; // @[ExecuteController.scala:837:{22,112}]
wire _dataB_T_8 = _mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols > 3'h2; // @[ExecuteController.scala:178:35, :837:117]
wire [31:0] _dataB_T_9_bits = _dataB_T_8 ? _dataB_WIRE_2_bits_0 : 32'h0; // @[ExecuteController.scala:837:{46,112,117}]
wire [31:0] dataB_2_bits = _dataB_T_9_bits; // @[ExecuteController.scala:837:{22,112}]
wire _dataB_T_10 = _mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols[2]; // @[ExecuteController.scala:178:35, :837:117]
wire [31:0] _dataB_T_11_bits = _dataB_T_10 ? _dataB_WIRE_3_bits_0 : 32'h0; // @[ExecuteController.scala:837:{46,112,117}]
wire [31:0] dataB_3_bits = _dataB_T_11_bits; // @[ExecuteController.scala:837:{22,112}]
wire [31:0] _dataD_T; // @[ExecuteController.scala:838:46]
wire [31:0] _dataD_T_1; // @[ExecuteController.scala:838:46]
wire [31:0] _dataD_T_2; // @[ExecuteController.scala:838:46]
wire [31:0] _dataD_T_3; // @[ExecuteController.scala:838:46]
assign _dataD_T = _dataD_WIRE_1[31:0]; // @[ExecuteController.scala:838:46]
wire [31:0] _dataD_WIRE_0_bits = _dataD_T; // @[ExecuteController.scala:838:46]
assign _dataD_T_1 = _dataD_WIRE_1[63:32]; // @[ExecuteController.scala:838:46]
wire [31:0] _dataD_WIRE_1_bits = _dataD_T_1; // @[ExecuteController.scala:838:46]
assign _dataD_T_2 = _dataD_WIRE_1[95:64]; // @[ExecuteController.scala:838:46]
wire [31:0] _dataD_WIRE_2_bits_0 = _dataD_T_2; // @[ExecuteController.scala:838:46]
assign _dataD_T_3 = _dataD_WIRE_1[127:96]; // @[ExecuteController.scala:838:46]
wire [31:0] _dataD_WIRE_3_bits_0 = _dataD_T_3; // @[ExecuteController.scala:838:46]
wire _dataD_T_4 = |_mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols; // @[ExecuteController.scala:178:35, :838:117]
wire [31:0] _dataD_T_5_bits = _dataD_T_4 ? _dataD_WIRE_0_bits : 32'h0; // @[ExecuteController.scala:838:{46,112,117}]
wire [31:0] dataD_0_bits = _dataD_T_5_bits; // @[ExecuteController.scala:838:{22,112}]
wire _dataD_T_6 = |(_mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols[2:1]); // @[ExecuteController.scala:178:35, :838:117]
wire [31:0] _dataD_T_7_bits = _dataD_T_6 ? _dataD_WIRE_1_bits : 32'h0; // @[ExecuteController.scala:838:{46,112,117}]
wire [31:0] dataD_1_bits = _dataD_T_7_bits; // @[ExecuteController.scala:838:{22,112}]
wire _dataD_T_8 = _mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols > 3'h2; // @[ExecuteController.scala:178:35, :838:117]
wire [31:0] _dataD_T_9_bits = _dataD_T_8 ? _dataD_WIRE_2_bits_0 : 32'h0; // @[ExecuteController.scala:838:{46,112,117}]
wire [31:0] dataD_2_bits = _dataD_T_9_bits; // @[ExecuteController.scala:838:{22,112}]
wire _dataD_T_10 = _mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols[2]; // @[ExecuteController.scala:178:35, :838:117]
wire [31:0] _dataD_T_11_bits = _dataD_T_10 ? _dataD_WIRE_3_bits_0 : 32'h0; // @[ExecuteController.scala:838:{46,112,117}]
wire [31:0] dataD_3_bits = _dataD_T_11_bits; // @[ExecuteController.scala:838:{22,112}]
wire _mesh_io_req_valid_T_1 = _mesh_cntl_signals_q_io_deq_ready_T_19 & _mesh_cntl_signals_q_io_deq_valid; // @[Decoupled.scala:51:35]
wire _T_133 = _mesh_cntl_signals_q_io_deq_bits_a_fire & _mesh_cntl_signals_q_io_deq_ready_T_1 & ~_mesh_cntl_signals_q_io_deq_bits_a_garbage & (|_mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols) & ~_mesh_cntl_signals_q_io_deq_bits_im2colling; // @[Decoupled.scala:51:35]
wire _io_acc_read_resp_ready_T = ~io_acc_read_resp_0_bits_fromDMA_0; // @[ExecuteController.scala:12:7, :808:95, :844:52]
wire [3:0] _GEN_80 = {{io_srams_read_3_resp_bits_fromDMA_0}, {io_srams_read_2_resp_bits_fromDMA_0}, {io_srams_read_1_resp_bits_fromDMA_0}, {io_srams_read_0_resp_bits_fromDMA_0}}; // @[ExecuteController.scala:12:7, :846:50]
wire _io_srams_read_resp_ready_T = ~_GEN_80[_mesh_cntl_signals_q_io_deq_bits_a_bank]; // @[ExecuteController.scala:178:35, :846:50]
wire _T_141 = _mesh_cntl_signals_q_io_deq_bits_b_fire & _mesh_cntl_signals_q_io_deq_ready_T_6 & ~_mesh_cntl_signals_q_io_deq_bits_b_garbage & ~_mesh_cntl_signals_q_io_deq_bits_accumulate_zeros & (|_mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols); // @[Decoupled.scala:51:35]
wire _io_acc_read_resp_ready_T_1 = ~io_acc_read_resp_0_bits_fromDMA_0; // @[ExecuteController.scala:12:7, :808:95, :852:52]
wire _io_srams_read_resp_ready_T_1 = ~_GEN_80[_mesh_cntl_signals_q_io_deq_bits_b_bank]; // @[ExecuteController.scala:178:35, :846:50, :854:50]
wire _T_149 = _mesh_cntl_signals_q_io_deq_bits_d_fire & _mesh_cntl_signals_q_io_deq_ready_T_12 & ~_mesh_cntl_signals_q_io_deq_bits_d_garbage & ~_mesh_cntl_signals_q_io_deq_bits_preload_zeros & (|_mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols); // @[Decoupled.scala:51:35]
wire _io_acc_read_resp_ready_T_2 = ~io_acc_read_resp_0_bits_fromDMA_0; // @[ExecuteController.scala:12:7, :808:95, :860:52]
assign io_acc_read_resp_0_ready_0 = _mesh_io_req_valid_T_1 & (_T_149 & _mesh_cntl_signals_q_io_deq_bits_d_read_from_acc ? _io_acc_read_resp_ready_T_2 : _T_141 & _mesh_cntl_signals_q_io_deq_bits_b_read_from_acc ? _io_acc_read_resp_ready_T_1 : _T_133 & _mesh_cntl_signals_q_io_deq_bits_a_read_from_acc & _io_acc_read_resp_ready_T); // @[Decoupled.scala:51:35]
wire _io_srams_read_resp_ready_T_2 = ~_GEN_80[_mesh_cntl_signals_q_io_deq_bits_d_bank]; // @[ExecuteController.scala:178:35, :846:50, :862:50]
assign io_srams_read_0_resp_ready_0 = _mesh_io_req_valid_T_1 & (~_T_149 | _mesh_cntl_signals_q_io_deq_bits_d_read_from_acc | (|_mesh_cntl_signals_q_io_deq_bits_d_bank) ? (~_T_141 | _mesh_cntl_signals_q_io_deq_bits_b_read_from_acc | (|_mesh_cntl_signals_q_io_deq_bits_b_bank) ? _T_133 & ~_mesh_cntl_signals_q_io_deq_bits_a_read_from_acc & _mesh_cntl_signals_q_io_deq_bits_a_bank == 2'h0 & _io_srams_read_resp_ready_T : _io_srams_read_resp_ready_T_1) : _io_srams_read_resp_ready_T_2); // @[Decoupled.scala:51:35]
assign io_srams_read_1_resp_ready_0 = _mesh_io_req_valid_T_1 & (~_T_149 | _mesh_cntl_signals_q_io_deq_bits_d_read_from_acc | _mesh_cntl_signals_q_io_deq_bits_d_bank != 2'h1 ? (~_T_141 | _mesh_cntl_signals_q_io_deq_bits_b_read_from_acc | _mesh_cntl_signals_q_io_deq_bits_b_bank != 2'h1 ? _T_133 & ~_mesh_cntl_signals_q_io_deq_bits_a_read_from_acc & _mesh_cntl_signals_q_io_deq_bits_a_bank == 2'h1 & _io_srams_read_resp_ready_T : _io_srams_read_resp_ready_T_1) : _io_srams_read_resp_ready_T_2); // @[Decoupled.scala:51:35]
assign io_srams_read_2_resp_ready_0 = _mesh_io_req_valid_T_1 & (~_T_149 | _mesh_cntl_signals_q_io_deq_bits_d_read_from_acc | _mesh_cntl_signals_q_io_deq_bits_d_bank != 2'h2 ? (~_T_141 | _mesh_cntl_signals_q_io_deq_bits_b_read_from_acc | _mesh_cntl_signals_q_io_deq_bits_b_bank != 2'h2 ? _T_133 & ~_mesh_cntl_signals_q_io_deq_bits_a_read_from_acc & _mesh_cntl_signals_q_io_deq_bits_a_bank == 2'h2 & _io_srams_read_resp_ready_T : _io_srams_read_resp_ready_T_1) : _io_srams_read_resp_ready_T_2); // @[Decoupled.scala:51:35]
assign io_srams_read_3_resp_ready_0 = _mesh_io_req_valid_T_1 & (~_T_149 | _mesh_cntl_signals_q_io_deq_bits_d_read_from_acc | _mesh_cntl_signals_q_io_deq_bits_d_bank != 2'h3 ? (~_T_141 | _mesh_cntl_signals_q_io_deq_bits_b_read_from_acc | _mesh_cntl_signals_q_io_deq_bits_b_bank != 2'h3 ? _T_133 & ~_mesh_cntl_signals_q_io_deq_bits_a_read_from_acc & (&_mesh_cntl_signals_q_io_deq_bits_a_bank) & _io_srams_read_resp_ready_T : _io_srams_read_resp_ready_T_1) : _io_srams_read_resp_ready_T_2); // @[Decoupled.scala:51:35]
wire _mesh_io_a_valid_T = _mesh_cntl_signals_q_io_deq_bits_a_fire & dataA_valid; // @[ExecuteController.scala:178:35, :816:68, :875:36]
assign mesh_io_a_valid = _mesh_cntl_signals_q_io_deq_valid & _mesh_io_a_valid_T; // @[ExecuteController.scala:178:35, :189:19, :873:21, :875:{21,36}]
wire _mesh_io_b_valid_T = _mesh_cntl_signals_q_io_deq_bits_b_fire & dataB_valid; // @[ExecuteController.scala:178:35, :818:68, :876:36]
assign mesh_io_b_valid = _mesh_cntl_signals_q_io_deq_valid & _mesh_io_b_valid_T; // @[ExecuteController.scala:178:35, :190:19, :873:21, :876:{21,36}]
wire _mesh_io_d_valid_T = _mesh_cntl_signals_q_io_deq_bits_d_fire & dataD_valid; // @[ExecuteController.scala:178:35, :822:68, :877:36]
assign mesh_io_d_valid = _mesh_cntl_signals_q_io_deq_valid & _mesh_io_d_valid_T; // @[ExecuteController.scala:178:35, :191:19, :873:21, :877:{21,36}]
wire [63:0] _GEN_81 = {dataA_1_bits, dataA_0_bits}; // @[ExecuteController.scala:836:22, :879:37]
wire [63:0] lo; // @[ExecuteController.scala:879:37]
assign lo = _GEN_81; // @[ExecuteController.scala:879:37]
wire [63:0] lo_3; // @[ExecuteController.scala:891:66]
assign lo_3 = _GEN_81; // @[ExecuteController.scala:879:37, :891:66]
wire [63:0] lo_5; // @[ExecuteController.scala:896:71]
assign lo_5 = _GEN_81; // @[ExecuteController.scala:879:37, :896:71]
wire [63:0] _GEN_82 = {dataA_3_bits, dataA_2_bits}; // @[ExecuteController.scala:836:22, :879:37]
wire [63:0] hi; // @[ExecuteController.scala:879:37]
assign hi = _GEN_82; // @[ExecuteController.scala:879:37]
wire [63:0] hi_3; // @[ExecuteController.scala:891:66]
assign hi_3 = _GEN_82; // @[ExecuteController.scala:879:37, :891:66]
wire [63:0] hi_5; // @[ExecuteController.scala:896:71]
assign hi_5 = _GEN_82; // @[ExecuteController.scala:879:37, :896:71]
wire [63:0] _GEN_83 = {dataB_1_bits, dataB_0_bits}; // @[ExecuteController.scala:837:22, :880:37]
wire [63:0] lo_1; // @[ExecuteController.scala:880:37]
assign lo_1 = _GEN_83; // @[ExecuteController.scala:880:37]
wire [63:0] lo_4; // @[ExecuteController.scala:892:66]
assign lo_4 = _GEN_83; // @[ExecuteController.scala:880:37, :892:66]
wire [63:0] lo_6; // @[ExecuteController.scala:897:71]
assign lo_6 = _GEN_83; // @[ExecuteController.scala:880:37, :897:71]
wire [63:0] _GEN_84 = {dataB_3_bits, dataB_2_bits}; // @[ExecuteController.scala:837:22, :880:37]
wire [63:0] hi_1; // @[ExecuteController.scala:880:37]
assign hi_1 = _GEN_84; // @[ExecuteController.scala:880:37]
wire [63:0] hi_4; // @[ExecuteController.scala:892:66]
assign hi_4 = _GEN_84; // @[ExecuteController.scala:880:37, :892:66]
wire [63:0] hi_6; // @[ExecuteController.scala:897:71]
assign hi_6 = _GEN_84; // @[ExecuteController.scala:880:37, :897:71]
wire [63:0] lo_2 = {dataD_1_bits, dataD_0_bits}; // @[ExecuteController.scala:838:22, :881:37]
wire [63:0] hi_2 = {dataD_3_bits, dataD_2_bits}; // @[ExecuteController.scala:838:22, :881:37]
wire _mesh_io_req_valid_T_2 = _mesh_cntl_signals_q_io_deq_bits_a_fire | _mesh_cntl_signals_q_io_deq_bits_b_fire; // @[ExecuteController.scala:178:35, :883:74]
wire _mesh_io_req_valid_T_3 = _mesh_io_req_valid_T_2 | _mesh_cntl_signals_q_io_deq_bits_d_fire; // @[ExecuteController.scala:178:35, :883:{74,89}]
wire _mesh_io_req_valid_T_4 = _mesh_io_req_valid_T_1 & _mesh_io_req_valid_T_3; // @[Decoupled.scala:51:35]
wire mesh_io_req_valid = _mesh_cntl_signals_q_io_deq_valid ? _mesh_io_req_valid_T_4 : _mesh_io_req_valid_T; // @[ExecuteController.scala:178:35, :192:{21,38}, :873:21, :883:{23,58}]
wire _T_165 = _mesh_cntl_signals_q_io_deq_valid & _mesh_cntl_signals_q_io_deq_bits_perform_single_preload; // @[ExecuteController.scala:178:35, :890:20]
wire [127:0] _T_167 = a_should_be_fed_into_transposer ? {hi_3, lo_3} : 128'h0; // @[ExecuteController.scala:123:44, :891:{26,66}]
wire [127:0] _T_173 = b_should_be_fed_into_transposer ? {hi_4, lo_4} : 128'h0; // @[ExecuteController.scala:126:79, :892:{26,66}]
wire _T_178 = _mesh_cntl_signals_q_io_deq_valid & _mesh_cntl_signals_q_io_deq_bits_perform_single_mul; // @[ExecuteController.scala:178:35, :895:20]
wire [127:0] _T_180 = a_should_be_fed_into_transposer ? 128'h0 : {hi_5, lo_5}; // @[ExecuteController.scala:123:44, :896:{26,71}]
wire [127:0] _T_186 = b_should_be_fed_into_transposer ? 128'h0 : {hi_6, lo_6}; // @[ExecuteController.scala:126:79, :897:{26,71}]
reg [1:0] output_counter; // @[ExecuteController.scala:903:31]
wire [17:0] _GEN_85 = {16'h0, output_counter} * {2'h0, c_addr_stride}; // @[ExecuteController.scala:249:26, :903:31, :907:106]
wire [17:0] _w_address_T_1; // @[ExecuteController.scala:907:106]
assign _w_address_T_1 = _GEN_85; // @[ExecuteController.scala:907:106]
wire [17:0] _w_address_T_4; // @[ExecuteController.scala:908:78]
assign _w_address_T_4 = _GEN_85; // @[ExecuteController.scala:907:106, :908:78]
wire w_address_result_is_acc_addr; // @[LocalAddr.scala:50:26]
wire w_address_result_accumulate; // @[LocalAddr.scala:50:26]
wire w_address_result_read_full_acc_row; // @[LocalAddr.scala:50:26]
wire [2:0] w_address_result_norm_cmd; // @[LocalAddr.scala:50:26]
wire [10:0] w_address_result_garbage; // @[LocalAddr.scala:50:26]
wire w_address_result_garbage_bit; // @[LocalAddr.scala:50:26]
wire [13:0] w_address_result_data; // @[LocalAddr.scala:50:26]
wire [18:0] _GEN_86 = {5'h0, _mesh_io_resp_bits_tag_addr_data}; // @[LocalAddr.scala:51:25]
wire [18:0] _w_address_result_data_T = _GEN_86 + {1'h0, _w_address_T_1}; // @[LocalAddr.scala:51:25]
wire [17:0] _w_address_result_data_T_1 = _w_address_result_data_T[17:0]; // @[LocalAddr.scala:51:25]
assign w_address_result_data = _w_address_result_data_T_1[13:0]; // @[LocalAddr.scala:50:26, :51:{17,25}]
wire [3:0] _GEN_87 = {1'h0, _mesh_io_resp_bits_total_rows} - 4'h1; // @[ExecuteController.scala:186:20, :908:55]
wire [3:0] _w_address_T_2; // @[ExecuteController.scala:908:55]
assign _w_address_T_2 = _GEN_87; // @[ExecuteController.scala:908:55]
wire [3:0] _write_this_row_T_2; // @[ExecuteController.scala:920:25]
assign _write_this_row_T_2 = _GEN_87; // @[ExecuteController.scala:908:55, :920:25]
wire [3:0] _output_counter_max_T; // @[Util.scala:18:28]
assign _output_counter_max_T = _GEN_87; // @[Util.scala:18:28]
wire [2:0] _w_address_T_3 = _w_address_T_2[2:0]; // @[ExecuteController.scala:908:55]
wire [18:0] _w_address_T_5 = {16'h0, _w_address_T_3} - {1'h0, _w_address_T_4}; // @[ExecuteController.scala:907:106, :908:{55,61,78}]
wire [17:0] _w_address_T_6 = _w_address_T_5[17:0]; // @[ExecuteController.scala:908:61]
wire w_address_result_1_is_acc_addr; // @[LocalAddr.scala:50:26]
wire w_address_result_1_accumulate; // @[LocalAddr.scala:50:26]
wire w_address_result_1_read_full_acc_row; // @[LocalAddr.scala:50:26]
wire [2:0] w_address_result_1_norm_cmd; // @[LocalAddr.scala:50:26]
wire [10:0] w_address_result_1_garbage; // @[LocalAddr.scala:50:26]
wire w_address_result_1_garbage_bit; // @[LocalAddr.scala:50:26]
wire [13:0] w_address_result_1_data; // @[LocalAddr.scala:50:26]
wire [18:0] _w_address_result_data_T_2 = _GEN_86 + {1'h0, _w_address_T_6}; // @[LocalAddr.scala:51:25]
wire [17:0] _w_address_result_data_T_3 = _w_address_result_data_T_2[17:0]; // @[LocalAddr.scala:51:25]
assign w_address_result_1_data = _w_address_result_data_T_3[13:0]; // @[LocalAddr.scala:50:26, :51:{17,25}]
wire w_address_is_acc_addr = _w_address_T ? w_address_result_is_acc_addr : w_address_result_1_is_acc_addr; // @[LocalAddr.scala:50:26]
assign w_address_accumulate = _w_address_T ? w_address_result_accumulate : w_address_result_1_accumulate; // @[LocalAddr.scala:50:26]
wire w_address_read_full_acc_row = _w_address_T ? w_address_result_read_full_acc_row : w_address_result_1_read_full_acc_row; // @[LocalAddr.scala:50:26]
wire [2:0] w_address_norm_cmd = _w_address_T ? w_address_result_norm_cmd : w_address_result_1_norm_cmd; // @[LocalAddr.scala:50:26]
wire [10:0] w_address_garbage = _w_address_T ? w_address_result_garbage : w_address_result_1_garbage; // @[LocalAddr.scala:50:26]
wire w_address_garbage_bit = _w_address_T ? w_address_result_garbage_bit : w_address_result_1_garbage_bit; // @[LocalAddr.scala:50:26]
wire [13:0] w_address_data = _w_address_T ? w_address_result_data : w_address_result_1_data; // @[LocalAddr.scala:50:26]
assign io_acc_write_0_bits_acc_0 = w_address_accumulate; // @[ExecuteController.scala:12:7, :907:22]
wire [1:0] _w_bank_T = w_address_data[13:12]; // @[LocalAddr.scala:33:79]
wire [1:0] w_bank = w_address_is_acc_addr ? 2'h0 : _w_bank_T; // @[LocalAddr.scala:33:79]
wire [11:0] _w_row_T = w_address_data[11:0]; // @[LocalAddr.scala:36:37]
wire [11:0] _w_row_T_1 = w_address_data[11:0]; // @[LocalAddr.scala:34:36, :36:37]
assign w_row = w_address_is_acc_addr ? _w_row_T : _w_row_T_1; // @[LocalAddr.scala:34:36, :36:37]
assign io_srams_write_0_addr_0 = w_row; // @[ExecuteController.scala:12:7, :912:18]
assign io_srams_write_1_addr_0 = w_row; // @[ExecuteController.scala:12:7, :912:18]
assign io_srams_write_2_addr_0 = w_row; // @[ExecuteController.scala:12:7, :912:18]
assign io_srams_write_3_addr_0 = w_row; // @[ExecuteController.scala:12:7, :912:18]
assign io_acc_write_0_bits_addr_0 = w_row; // @[ExecuteController.scala:12:7, :912:18]
wire _is_garbage_addr_T = _mesh_io_resp_bits_tag_addr_is_acc_addr & _mesh_io_resp_bits_tag_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _is_garbage_addr_T_1 = _is_garbage_addr_T & _mesh_io_resp_bits_tag_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _is_garbage_addr_T_2 = &_mesh_io_resp_bits_tag_addr_data; // @[LocalAddr.scala:43:91]
wire _is_garbage_addr_T_3 = _is_garbage_addr_T_1 & _is_garbage_addr_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire _is_garbage_addr_T_4; // @[LocalAddr.scala:44:48]
wire is_garbage_addr = _is_garbage_addr_T_3 & _is_garbage_addr_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire [2:0] _GEN_88 = {1'h0, output_counter}; // @[ExecuteController.scala:903:31, :919:82]
wire _write_this_row_T_1 = _GEN_88 < _mesh_io_resp_bits_tag_rows; // @[ExecuteController.scala:186:20, :919:82]
wire [2:0] _write_this_row_T_3 = _write_this_row_T_2[2:0]; // @[ExecuteController.scala:920:25]
wire [3:0] _GEN_89 = {2'h0, output_counter}; // @[ExecuteController.scala:903:31, :920:31]
wire [3:0] _write_this_row_T_4 = {1'h0, _write_this_row_T_3} - _GEN_89; // @[ExecuteController.scala:920:{25,31}]
wire [2:0] _write_this_row_T_5 = _write_this_row_T_4[2:0]; // @[ExecuteController.scala:920:31]
wire _write_this_row_T_6 = _write_this_row_T_5 < _mesh_io_resp_bits_tag_rows; // @[ExecuteController.scala:186:20, :920:{31,48}]
wire write_this_row = _write_this_row_T ? _write_this_row_T_1 : _write_this_row_T_6; // @[ExecuteController.scala:919:{27,45,82}, :920:48]
assign w_mask_0 = |_mesh_io_resp_bits_tag_cols; // @[ExecuteController.scala:186:20, :921:45]
assign io_srams_write_0_mask_0_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_0_mask_1_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_0_mask_2_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_0_mask_3_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_1_mask_0_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_1_mask_1_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_1_mask_2_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_1_mask_3_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_2_mask_0_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_2_mask_1_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_2_mask_2_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_2_mask_3_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_3_mask_0_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_3_mask_1_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_3_mask_2_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_3_mask_3_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_0_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_1_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_2_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_3_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign w_mask_1 = |(_mesh_io_resp_bits_tag_cols[2:1]); // @[ExecuteController.scala:186:20, :921:45]
assign io_srams_write_0_mask_4_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_0_mask_5_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_0_mask_6_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_0_mask_7_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_1_mask_4_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_1_mask_5_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_1_mask_6_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_1_mask_7_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_2_mask_4_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_2_mask_5_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_2_mask_6_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_2_mask_7_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_3_mask_4_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_3_mask_5_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_3_mask_6_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_3_mask_7_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_4_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_5_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_6_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_7_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign w_mask_2 = _mesh_io_resp_bits_tag_cols > 3'h2; // @[ExecuteController.scala:186:20, :921:45]
assign io_srams_write_0_mask_8_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_0_mask_9_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_0_mask_10_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_0_mask_11_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_1_mask_8_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_1_mask_9_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_1_mask_10_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_1_mask_11_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_2_mask_8_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_2_mask_9_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_2_mask_10_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_2_mask_11_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_3_mask_8_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_3_mask_9_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_3_mask_10_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_3_mask_11_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_8_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_9_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_10_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_11_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign w_mask_3 = _mesh_io_resp_bits_tag_cols[2]; // @[ExecuteController.scala:186:20, :921:45]
assign io_srams_write_0_mask_12_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_0_mask_13_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_0_mask_14_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_0_mask_15_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_1_mask_12_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_1_mask_13_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_1_mask_14_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_1_mask_15_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_2_mask_12_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_2_mask_13_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_2_mask_14_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_2_mask_15_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_3_mask_12_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_3_mask_13_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_3_mask_14_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_srams_write_3_mask_15_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_12_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_13_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_14_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_15_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
wire activated_wdata_e_clipped_self_rec_rawIn_sign = _mesh_io_resp_bits_data_0_0_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_clipped_self_rec_rawIn_sign_4 = _mesh_io_resp_bits_data_0_0_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_clipped_self_rec_rawIn_sign_8 = _mesh_io_resp_bits_data_0_0_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_clipped_self_rec_rawIn_sign_12 = _mesh_io_resp_bits_data_0_0_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire self_rec_rawIn_sign = _mesh_io_resp_bits_data_0_0_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_clipped_self_rec_rawIn_sign_0 = activated_wdata_e_clipped_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_wdata_e_clipped_self_rec_rawIn_expIn = _mesh_io_resp_bits_data_0_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [7:0] activated_wdata_e_clipped_self_rec_rawIn_expIn_4 = _mesh_io_resp_bits_data_0_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [7:0] activated_wdata_e_clipped_self_rec_rawIn_expIn_8 = _mesh_io_resp_bits_data_0_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [7:0] activated_wdata_e_clipped_self_rec_rawIn_expIn_12 = _mesh_io_resp_bits_data_0_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [7:0] self_rec_rawIn_expIn = _mesh_io_resp_bits_data_0_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_fractIn = _mesh_io_resp_bits_data_0_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_fractIn_4 = _mesh_io_resp_bits_data_0_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_fractIn_8 = _mesh_io_resp_bits_data_0_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_fractIn_12 = _mesh_io_resp_bits_data_0_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire [22:0] self_rec_rawIn_fractIn = _mesh_io_resp_bits_data_0_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn = activated_wdata_e_clipped_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn = activated_wdata_e_clipped_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T = activated_wdata_e_clipped_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_1 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_2 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_3 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_4 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_5 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_6 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_7 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_8 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_9 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_10 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_11 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_12 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_13 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_14 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_15 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_16 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_17 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_18 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_19 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_20 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_21 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_22 = activated_wdata_e_clipped_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_23 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_24 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_25 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_26 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_27 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_28 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_29 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_7 ? 5'hF : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_30 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_8 ? 5'hE : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_31 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_9 ? 5'hD : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_32 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_10 ? 5'hC : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_33 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_11 ? 5'hB : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_34 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_12 ? 5'hA : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_35 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_36 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_37 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_38 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_39 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_40 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_41 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_42 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_43 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_clipped_self_rec_rawIn_normDist = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T = {31'h0, activated_wdata_e_clipped_self_rec_rawIn_fractIn} << activated_wdata_e_clipped_self_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_1 = _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_subnormFract = {_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T = {4'hF, ~activated_wdata_e_clipped_self_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_1 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn ? _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T : {1'h0, activated_wdata_e_clipped_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_2 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_clipped_self_rec_rawIn_adjustedExp = _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_clipped_self_rec_rawIn_isZero = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_clipped_self_rec_rawIn_isZero_0 = activated_wdata_e_clipped_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_clipped_self_rec_rawIn_isSpecial = &_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _activated_wdata_e_clipped_self_rec_T_2 = activated_wdata_e_clipped_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_clipped_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_clipped_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_clipped_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T = ~activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_1 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial & _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_clipped_self_rec_rawIn_isNaN = _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T = activated_wdata_e_clipped_self_rec_rawIn_isSpecial & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_clipped_self_rec_rawIn_isInf = _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_clipped_self_rec_rawIn_sExp = _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T = ~activated_wdata_e_clipped_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_1 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_2 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn ? activated_wdata_e_clipped_self_rec_rawIn_subnormFract : activated_wdata_e_clipped_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_3 = {_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_1, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_clipped_self_rec_rawIn_sig = _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_wdata_e_clipped_self_rec_T = activated_wdata_e_clipped_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_1 = activated_wdata_e_clipped_self_rec_rawIn_isZero_0 ? 3'h0 : _activated_wdata_e_clipped_self_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_3 = {_activated_wdata_e_clipped_self_rec_T_1[2:1], _activated_wdata_e_clipped_self_rec_T_1[0] | _activated_wdata_e_clipped_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_wdata_e_clipped_self_rec_T_4 = {activated_wdata_e_clipped_self_rec_rawIn_sign_0, _activated_wdata_e_clipped_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_wdata_e_clipped_self_rec_T_5 = activated_wdata_e_clipped_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_wdata_e_clipped_self_rec_T_6 = {_activated_wdata_e_clipped_self_rec_T_4, _activated_wdata_e_clipped_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_wdata_e_clipped_self_rec_T_7 = activated_wdata_e_clipped_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_wdata_e_clipped_self_rec = {_activated_wdata_e_clipped_self_rec_T_6, _activated_wdata_e_clipped_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_wdata_e_clipped_result_bits_T; // @[fNFromRecFN.scala:66:12]
wire [31:0] activated_wdata_e_clipped_bits; // @[Arithmetic.scala:505:26]
wire [8:0] activated_wdata_e_clipped_result_bits_rawIn_exp = _activated_wdata_e_clipped_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_wdata_e_clipped_result_bits_rawIn_isZero_T = activated_wdata_e_clipped_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isZero = _activated_wdata_e_clipped_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_wdata_e_clipped_result_bits_rawIn_isZero_0 = activated_wdata_e_clipped_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T = activated_wdata_e_clipped_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isSpecial = &_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire activated_wdata_e_clipped_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_wdata_e_clipped_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_wdata_e_clipped_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T = activated_wdata_e_clipped_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T = activated_wdata_e_clipped_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_1 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial & _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_wdata_e_clipped_result_bits_rawIn_isNaN = _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_1 = ~_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_2 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial & _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_wdata_e_clipped_result_bits_rawIn_isInf = _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T = _activated_wdata_e_clipped_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_wdata_e_clipped_result_bits_rawIn_sign = _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T = {1'h0, activated_wdata_e_clipped_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_wdata_e_clipped_result_bits_rawIn_sExp = _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T = ~activated_wdata_e_clipped_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_1 = {1'h0, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_2 = _activated_wdata_e_clipped_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_3 = {_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_1, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_wdata_e_clipped_result_bits_rawIn_sig = _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire activated_wdata_e_clipped_result_bits_isSubnormal = $signed(activated_wdata_e_clipped_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T = activated_wdata_e_clipped_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _activated_wdata_e_clipped_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] activated_wdata_e_clipped_result_bits_denormShiftDist = _activated_wdata_e_clipped_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T = activated_wdata_e_clipped_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_1 = _activated_wdata_e_clipped_result_bits_denormFract_T >> activated_wdata_e_clipped_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] activated_wdata_e_clipped_result_bits_denormFract = _activated_wdata_e_clipped_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T = activated_wdata_e_clipped_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _activated_wdata_e_clipped_result_bits_expOut_T_1 = {1'h0, _activated_wdata_e_clipped_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_2 = _activated_wdata_e_clipped_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_3 = activated_wdata_e_clipped_result_bits_isSubnormal ? 8'h0 : _activated_wdata_e_clipped_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _activated_wdata_e_clipped_result_bits_expOut_T_4 = activated_wdata_e_clipped_result_bits_rawIn_isNaN | activated_wdata_e_clipped_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_5 = {8{_activated_wdata_e_clipped_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] activated_wdata_e_clipped_result_bits_expOut = _activated_wdata_e_clipped_result_bits_expOut_T_3 | _activated_wdata_e_clipped_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T = activated_wdata_e_clipped_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_1 = activated_wdata_e_clipped_result_bits_rawIn_isInf ? 23'h0 : _activated_wdata_e_clipped_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] activated_wdata_e_clipped_result_bits_fractOut = activated_wdata_e_clipped_result_bits_isSubnormal ? activated_wdata_e_clipped_result_bits_denormFract : _activated_wdata_e_clipped_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] activated_wdata_e_clipped_result_bits_hi = {activated_wdata_e_clipped_result_bits_rawIn_sign, activated_wdata_e_clipped_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23]
assign _activated_wdata_e_clipped_result_bits_T = {activated_wdata_e_clipped_result_bits_hi, activated_wdata_e_clipped_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
assign activated_wdata_e_clipped_bits = _activated_wdata_e_clipped_result_bits_T; // @[fNFromRecFN.scala:66:12]
wire _GEN_90 = activation == 3'h1; // @[ExecuteController.scala:118:54, :928:21]
wire _activated_wdata_e_act_T; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T = _GEN_90; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_1; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_1 = _GEN_90; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_2; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_2 = _GEN_90; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_3; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_3 = _GEN_90; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_4; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_4 = _GEN_90; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_5; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_5 = _GEN_90; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_6; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_6 = _GEN_90; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_7; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_7 = _GEN_90; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_8; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_8 = _GEN_90; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_9; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_9 = _GEN_90; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_10; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_10 = _GEN_90; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_11; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_11 = _GEN_90; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_12; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_12 = _GEN_90; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_13; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_13 = _GEN_90; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_14; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_14 = _GEN_90; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_15; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_15 = _GEN_90; // @[ExecuteController.scala:928:21]
wire activated_wdata_e_act_raw_sign = activated_wdata_e_clipped_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_act_raw_sign_0 = activated_wdata_e_act_raw_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_wdata_e_act_raw_expIn = activated_wdata_e_clipped_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_wdata_e_act_raw_fractIn = activated_wdata_e_clipped_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_wdata_e_act_raw_isZeroExpIn = activated_wdata_e_act_raw_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_act_raw_isZeroFractIn = activated_wdata_e_act_raw_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_act_raw_normDist_T = activated_wdata_e_act_raw_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_1 = activated_wdata_e_act_raw_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_2 = activated_wdata_e_act_raw_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_3 = activated_wdata_e_act_raw_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_4 = activated_wdata_e_act_raw_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_5 = activated_wdata_e_act_raw_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_6 = activated_wdata_e_act_raw_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_7 = activated_wdata_e_act_raw_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_8 = activated_wdata_e_act_raw_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_9 = activated_wdata_e_act_raw_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_10 = activated_wdata_e_act_raw_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_11 = activated_wdata_e_act_raw_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_12 = activated_wdata_e_act_raw_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_13 = activated_wdata_e_act_raw_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_14 = activated_wdata_e_act_raw_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_15 = activated_wdata_e_act_raw_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_16 = activated_wdata_e_act_raw_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_17 = activated_wdata_e_act_raw_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_18 = activated_wdata_e_act_raw_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_19 = activated_wdata_e_act_raw_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_20 = activated_wdata_e_act_raw_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_21 = activated_wdata_e_act_raw_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_22 = activated_wdata_e_act_raw_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_23 = _activated_wdata_e_act_raw_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_24 = _activated_wdata_e_act_raw_normDist_T_2 ? 5'h14 : _activated_wdata_e_act_raw_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_25 = _activated_wdata_e_act_raw_normDist_T_3 ? 5'h13 : _activated_wdata_e_act_raw_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_26 = _activated_wdata_e_act_raw_normDist_T_4 ? 5'h12 : _activated_wdata_e_act_raw_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_27 = _activated_wdata_e_act_raw_normDist_T_5 ? 5'h11 : _activated_wdata_e_act_raw_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_28 = _activated_wdata_e_act_raw_normDist_T_6 ? 5'h10 : _activated_wdata_e_act_raw_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_29 = _activated_wdata_e_act_raw_normDist_T_7 ? 5'hF : _activated_wdata_e_act_raw_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_30 = _activated_wdata_e_act_raw_normDist_T_8 ? 5'hE : _activated_wdata_e_act_raw_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_31 = _activated_wdata_e_act_raw_normDist_T_9 ? 5'hD : _activated_wdata_e_act_raw_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_32 = _activated_wdata_e_act_raw_normDist_T_10 ? 5'hC : _activated_wdata_e_act_raw_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_33 = _activated_wdata_e_act_raw_normDist_T_11 ? 5'hB : _activated_wdata_e_act_raw_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_34 = _activated_wdata_e_act_raw_normDist_T_12 ? 5'hA : _activated_wdata_e_act_raw_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_35 = _activated_wdata_e_act_raw_normDist_T_13 ? 5'h9 : _activated_wdata_e_act_raw_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_36 = _activated_wdata_e_act_raw_normDist_T_14 ? 5'h8 : _activated_wdata_e_act_raw_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_37 = _activated_wdata_e_act_raw_normDist_T_15 ? 5'h7 : _activated_wdata_e_act_raw_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_38 = _activated_wdata_e_act_raw_normDist_T_16 ? 5'h6 : _activated_wdata_e_act_raw_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_39 = _activated_wdata_e_act_raw_normDist_T_17 ? 5'h5 : _activated_wdata_e_act_raw_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_40 = _activated_wdata_e_act_raw_normDist_T_18 ? 5'h4 : _activated_wdata_e_act_raw_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_41 = _activated_wdata_e_act_raw_normDist_T_19 ? 5'h3 : _activated_wdata_e_act_raw_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_42 = _activated_wdata_e_act_raw_normDist_T_20 ? 5'h2 : _activated_wdata_e_act_raw_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_43 = _activated_wdata_e_act_raw_normDist_T_21 ? 5'h1 : _activated_wdata_e_act_raw_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_act_raw_normDist = _activated_wdata_e_act_raw_normDist_T_22 ? 5'h0 : _activated_wdata_e_act_raw_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_act_raw_subnormFract_T = {31'h0, activated_wdata_e_act_raw_fractIn} << activated_wdata_e_act_raw_normDist; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_act_raw_subnormFract_T_1 = _activated_wdata_e_act_raw_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_act_raw_subnormFract = {_activated_wdata_e_act_raw_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T = {4'hF, ~activated_wdata_e_act_raw_normDist}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_1 = activated_wdata_e_act_raw_isZeroExpIn ? _activated_wdata_e_act_raw_adjustedExp_T : {1'h0, activated_wdata_e_act_raw_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_act_raw_adjustedExp_T_2 = activated_wdata_e_act_raw_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_act_raw_adjustedExp_T_3 = {6'h20, _activated_wdata_e_act_raw_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_act_raw_adjustedExp_T_4 = {1'h0, _activated_wdata_e_act_raw_adjustedExp_T_1} + {2'h0, _activated_wdata_e_act_raw_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_act_raw_adjustedExp = _activated_wdata_e_act_raw_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_act_raw_out_sExp_T = activated_wdata_e_act_raw_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_act_raw_isZero = activated_wdata_e_act_raw_isZeroExpIn & activated_wdata_e_act_raw_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_act_raw_isZero_0 = activated_wdata_e_act_raw_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_act_raw_isSpecial_T = activated_wdata_e_act_raw_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_act_raw_isSpecial = &_activated_wdata_e_act_raw_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_act_raw_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_act_raw_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire [9:0] _activated_wdata_e_act_raw_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_act_raw_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_act_raw_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_act_raw_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_act_raw_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_act_raw_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_raw_out_isNaN_T = ~activated_wdata_e_act_raw_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_act_raw_out_isNaN_T_1 = activated_wdata_e_act_raw_isSpecial & _activated_wdata_e_act_raw_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_act_raw_isNaN = _activated_wdata_e_act_raw_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_act_raw_out_isInf_T = activated_wdata_e_act_raw_isSpecial & activated_wdata_e_act_raw_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_act_raw_isInf = _activated_wdata_e_act_raw_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_act_raw_out_sExp_T_1 = {1'h0, _activated_wdata_e_act_raw_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_act_raw_sExp = _activated_wdata_e_act_raw_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_act_raw_out_sig_T = ~activated_wdata_e_act_raw_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_act_raw_out_sig_T_1 = {1'h0, _activated_wdata_e_act_raw_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_act_raw_out_sig_T_2 = activated_wdata_e_act_raw_isZeroExpIn ? activated_wdata_e_act_raw_subnormFract : activated_wdata_e_act_raw_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_act_raw_out_sig_T_3 = {_activated_wdata_e_act_raw_out_sig_T_1, _activated_wdata_e_act_raw_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_act_raw_sig = _activated_wdata_e_act_raw_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [31:0] _activated_wdata_e_act_result_bits_T_2; // @[Arithmetic.scala:514:27]
wire [31:0] activated_wdata_e_act_result_bits; // @[Arithmetic.scala:513:26]
wire _activated_wdata_e_act_result_bits_T = ~activated_wdata_e_act_raw_isZero_0; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_result_bits_T_1 = _activated_wdata_e_act_result_bits_T & activated_wdata_e_act_raw_sign_0; // @[rawFloatFromFN.scala:63:19]
assign _activated_wdata_e_act_result_bits_T_2 = _activated_wdata_e_act_result_bits_T_1 ? 32'h0 : activated_wdata_e_clipped_bits; // @[Arithmetic.scala:505:26, :514:{27,40}]
assign activated_wdata_e_act_result_bits = _activated_wdata_e_act_result_bits_T_2; // @[Arithmetic.scala:513:26, :514:27]
wire [31:0] activated_wdata_e_act_bits = _activated_wdata_e_act_T ? activated_wdata_e_act_result_bits : activated_wdata_e_clipped_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_wdata_WIRE_0_bits = activated_wdata_e_act_bits; // @[Mux.scala:126:16]
wire [31:0] activated_wdata_0_0_bits = _activated_wdata_WIRE_0_bits; // @[ExecuteController.scala:925:{34,74}]
wire activated_wdata_e_clipped_self_rec_rawIn_sign_1 = _mesh_io_resp_bits_data_1_0_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_clipped_self_rec_rawIn_sign_5 = _mesh_io_resp_bits_data_1_0_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_clipped_self_rec_rawIn_sign_9 = _mesh_io_resp_bits_data_1_0_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_clipped_self_rec_rawIn_sign_13 = _mesh_io_resp_bits_data_1_0_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire self_rec_rawIn_sign_1 = _mesh_io_resp_bits_data_1_0_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_clipped_self_rec_rawIn_1_sign = activated_wdata_e_clipped_self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_wdata_e_clipped_self_rec_rawIn_expIn_1 = _mesh_io_resp_bits_data_1_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [7:0] activated_wdata_e_clipped_self_rec_rawIn_expIn_5 = _mesh_io_resp_bits_data_1_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [7:0] activated_wdata_e_clipped_self_rec_rawIn_expIn_9 = _mesh_io_resp_bits_data_1_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [7:0] activated_wdata_e_clipped_self_rec_rawIn_expIn_13 = _mesh_io_resp_bits_data_1_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [7:0] self_rec_rawIn_expIn_1 = _mesh_io_resp_bits_data_1_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_fractIn_1 = _mesh_io_resp_bits_data_1_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_fractIn_5 = _mesh_io_resp_bits_data_1_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_fractIn_9 = _mesh_io_resp_bits_data_1_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_fractIn_13 = _mesh_io_resp_bits_data_1_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire [22:0] self_rec_rawIn_fractIn_1 = _mesh_io_resp_bits_data_1_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_1 = activated_wdata_e_clipped_self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_1 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_44 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_45 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_46 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_47 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_48 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_49 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_50 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_51 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_52 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_53 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_54 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_55 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_56 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_57 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_58 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_59 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_60 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_61 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_62 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_63 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_64 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_65 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_66 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_67 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_68 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_69 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_70 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_71 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_72 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_73 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_51 ? 5'hF : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_74 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_52 ? 5'hE : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_75 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_53 ? 5'hD : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_76 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_54 ? 5'hC : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_77 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_55 ? 5'hB : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_78 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_56 ? 5'hA : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_79 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_80 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_81 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_82 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_83 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_84 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_85 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_86 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_87 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_clipped_self_rec_rawIn_normDist_1 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_2 = {31'h0, activated_wdata_e_clipped_self_rec_rawIn_fractIn_1} << activated_wdata_e_clipped_self_rec_rawIn_normDist_1; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_3 = _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_subnormFract_1 = {_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_wdata_e_clipped_self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_6 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_1 ? _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_wdata_e_clipped_self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_7 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_1 = _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_2 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_clipped_self_rec_rawIn_isZero_1 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_1 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_clipped_self_rec_rawIn_1_isZero = activated_wdata_e_clipped_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_1 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_clipped_self_rec_rawIn_isSpecial_1 = &_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28]
wire _activated_wdata_e_clipped_self_rec_T_10 = activated_wdata_e_clipped_self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_clipped_self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_clipped_self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_clipped_self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_2 = ~activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_3 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_1 & _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_clipped_self_rec_rawIn_1_isNaN = _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_1 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_1 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_clipped_self_rec_rawIn_1_isInf = _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_clipped_self_rec_rawIn_1_sExp = _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_4 = ~activated_wdata_e_clipped_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_5 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_6 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_1 ? activated_wdata_e_clipped_self_rec_rawIn_subnormFract_1 : activated_wdata_e_clipped_self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_7 = {_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_5, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_clipped_self_rec_rawIn_1_sig = _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_8 = activated_wdata_e_clipped_self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_9 = activated_wdata_e_clipped_self_rec_rawIn_1_isZero ? 3'h0 : _activated_wdata_e_clipped_self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_11 = {_activated_wdata_e_clipped_self_rec_T_9[2:1], _activated_wdata_e_clipped_self_rec_T_9[0] | _activated_wdata_e_clipped_self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_wdata_e_clipped_self_rec_T_12 = {activated_wdata_e_clipped_self_rec_rawIn_1_sign, _activated_wdata_e_clipped_self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_wdata_e_clipped_self_rec_T_13 = activated_wdata_e_clipped_self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_wdata_e_clipped_self_rec_T_14 = {_activated_wdata_e_clipped_self_rec_T_12, _activated_wdata_e_clipped_self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_wdata_e_clipped_self_rec_T_15 = activated_wdata_e_clipped_self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_wdata_e_clipped_self_rec_1 = {_activated_wdata_e_clipped_self_rec_T_14, _activated_wdata_e_clipped_self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_wdata_e_clipped_result_bits_T_1; // @[fNFromRecFN.scala:66:12]
wire [31:0] activated_wdata_e_clipped_1_bits; // @[Arithmetic.scala:505:26]
wire [8:0] activated_wdata_e_clipped_result_bits_rawIn_exp_1 = _activated_wdata_e_clipped_resizer_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_1 = activated_wdata_e_clipped_result_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isZero_1 = _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_wdata_e_clipped_result_bits_rawIn_1_isZero = activated_wdata_e_clipped_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_1 = activated_wdata_e_clipped_result_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isSpecial_1 = &_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44]
wire activated_wdata_e_clipped_result_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_wdata_e_clipped_result_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_wdata_e_clipped_result_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_2 = activated_wdata_e_clipped_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_3 = activated_wdata_e_clipped_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_3 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_1 & _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_wdata_e_clipped_result_bits_rawIn_1_isNaN = _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_4 = ~_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_5 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_1 & _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_wdata_e_clipped_result_bits_rawIn_1_isInf = _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_1 = _activated_wdata_e_clipped_resizer_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_wdata_e_clipped_result_bits_rawIn_1_sign = _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_1 = {1'h0, activated_wdata_e_clipped_result_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_wdata_e_clipped_result_bits_rawIn_1_sExp = _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_4 = ~activated_wdata_e_clipped_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_5 = {1'h0, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_6 = _activated_wdata_e_clipped_resizer_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_7 = {_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_5, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_wdata_e_clipped_result_bits_rawIn_1_sig = _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire activated_wdata_e_clipped_result_bits_isSubnormal_1 = $signed(activated_wdata_e_clipped_result_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_2 = activated_wdata_e_clipped_result_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _activated_wdata_e_clipped_result_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] activated_wdata_e_clipped_result_bits_denormShiftDist_1 = _activated_wdata_e_clipped_result_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_2 = activated_wdata_e_clipped_result_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_3 = _activated_wdata_e_clipped_result_bits_denormFract_T_2 >> activated_wdata_e_clipped_result_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] activated_wdata_e_clipped_result_bits_denormFract_1 = _activated_wdata_e_clipped_result_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_6 = activated_wdata_e_clipped_result_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _activated_wdata_e_clipped_result_bits_expOut_T_7 = {1'h0, _activated_wdata_e_clipped_result_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_8 = _activated_wdata_e_clipped_result_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_9 = activated_wdata_e_clipped_result_bits_isSubnormal_1 ? 8'h0 : _activated_wdata_e_clipped_result_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _activated_wdata_e_clipped_result_bits_expOut_T_10 = activated_wdata_e_clipped_result_bits_rawIn_1_isNaN | activated_wdata_e_clipped_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_11 = {8{_activated_wdata_e_clipped_result_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] activated_wdata_e_clipped_result_bits_expOut_1 = _activated_wdata_e_clipped_result_bits_expOut_T_9 | _activated_wdata_e_clipped_result_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_2 = activated_wdata_e_clipped_result_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_3 = activated_wdata_e_clipped_result_bits_rawIn_1_isInf ? 23'h0 : _activated_wdata_e_clipped_result_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] activated_wdata_e_clipped_result_bits_fractOut_1 = activated_wdata_e_clipped_result_bits_isSubnormal_1 ? activated_wdata_e_clipped_result_bits_denormFract_1 : _activated_wdata_e_clipped_result_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] activated_wdata_e_clipped_result_bits_hi_1 = {activated_wdata_e_clipped_result_bits_rawIn_1_sign, activated_wdata_e_clipped_result_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23]
assign _activated_wdata_e_clipped_result_bits_T_1 = {activated_wdata_e_clipped_result_bits_hi_1, activated_wdata_e_clipped_result_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12]
assign activated_wdata_e_clipped_1_bits = _activated_wdata_e_clipped_result_bits_T_1; // @[fNFromRecFN.scala:66:12]
wire activated_wdata_e_act_raw_sign_1 = activated_wdata_e_clipped_1_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_act_raw_1_sign = activated_wdata_e_act_raw_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_wdata_e_act_raw_expIn_1 = activated_wdata_e_clipped_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_wdata_e_act_raw_fractIn_1 = activated_wdata_e_clipped_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_wdata_e_act_raw_isZeroExpIn_1 = activated_wdata_e_act_raw_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_act_raw_isZeroFractIn_1 = activated_wdata_e_act_raw_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_act_raw_normDist_T_44 = activated_wdata_e_act_raw_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_45 = activated_wdata_e_act_raw_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_46 = activated_wdata_e_act_raw_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_47 = activated_wdata_e_act_raw_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_48 = activated_wdata_e_act_raw_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_49 = activated_wdata_e_act_raw_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_50 = activated_wdata_e_act_raw_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_51 = activated_wdata_e_act_raw_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_52 = activated_wdata_e_act_raw_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_53 = activated_wdata_e_act_raw_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_54 = activated_wdata_e_act_raw_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_55 = activated_wdata_e_act_raw_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_56 = activated_wdata_e_act_raw_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_57 = activated_wdata_e_act_raw_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_58 = activated_wdata_e_act_raw_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_59 = activated_wdata_e_act_raw_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_60 = activated_wdata_e_act_raw_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_61 = activated_wdata_e_act_raw_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_62 = activated_wdata_e_act_raw_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_63 = activated_wdata_e_act_raw_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_64 = activated_wdata_e_act_raw_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_65 = activated_wdata_e_act_raw_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_66 = activated_wdata_e_act_raw_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_67 = _activated_wdata_e_act_raw_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_68 = _activated_wdata_e_act_raw_normDist_T_46 ? 5'h14 : _activated_wdata_e_act_raw_normDist_T_67; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_69 = _activated_wdata_e_act_raw_normDist_T_47 ? 5'h13 : _activated_wdata_e_act_raw_normDist_T_68; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_70 = _activated_wdata_e_act_raw_normDist_T_48 ? 5'h12 : _activated_wdata_e_act_raw_normDist_T_69; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_71 = _activated_wdata_e_act_raw_normDist_T_49 ? 5'h11 : _activated_wdata_e_act_raw_normDist_T_70; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_72 = _activated_wdata_e_act_raw_normDist_T_50 ? 5'h10 : _activated_wdata_e_act_raw_normDist_T_71; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_73 = _activated_wdata_e_act_raw_normDist_T_51 ? 5'hF : _activated_wdata_e_act_raw_normDist_T_72; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_74 = _activated_wdata_e_act_raw_normDist_T_52 ? 5'hE : _activated_wdata_e_act_raw_normDist_T_73; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_75 = _activated_wdata_e_act_raw_normDist_T_53 ? 5'hD : _activated_wdata_e_act_raw_normDist_T_74; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_76 = _activated_wdata_e_act_raw_normDist_T_54 ? 5'hC : _activated_wdata_e_act_raw_normDist_T_75; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_77 = _activated_wdata_e_act_raw_normDist_T_55 ? 5'hB : _activated_wdata_e_act_raw_normDist_T_76; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_78 = _activated_wdata_e_act_raw_normDist_T_56 ? 5'hA : _activated_wdata_e_act_raw_normDist_T_77; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_79 = _activated_wdata_e_act_raw_normDist_T_57 ? 5'h9 : _activated_wdata_e_act_raw_normDist_T_78; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_80 = _activated_wdata_e_act_raw_normDist_T_58 ? 5'h8 : _activated_wdata_e_act_raw_normDist_T_79; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_81 = _activated_wdata_e_act_raw_normDist_T_59 ? 5'h7 : _activated_wdata_e_act_raw_normDist_T_80; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_82 = _activated_wdata_e_act_raw_normDist_T_60 ? 5'h6 : _activated_wdata_e_act_raw_normDist_T_81; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_83 = _activated_wdata_e_act_raw_normDist_T_61 ? 5'h5 : _activated_wdata_e_act_raw_normDist_T_82; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_84 = _activated_wdata_e_act_raw_normDist_T_62 ? 5'h4 : _activated_wdata_e_act_raw_normDist_T_83; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_85 = _activated_wdata_e_act_raw_normDist_T_63 ? 5'h3 : _activated_wdata_e_act_raw_normDist_T_84; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_86 = _activated_wdata_e_act_raw_normDist_T_64 ? 5'h2 : _activated_wdata_e_act_raw_normDist_T_85; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_87 = _activated_wdata_e_act_raw_normDist_T_65 ? 5'h1 : _activated_wdata_e_act_raw_normDist_T_86; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_act_raw_normDist_1 = _activated_wdata_e_act_raw_normDist_T_66 ? 5'h0 : _activated_wdata_e_act_raw_normDist_T_87; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_act_raw_subnormFract_T_2 = {31'h0, activated_wdata_e_act_raw_fractIn_1} << activated_wdata_e_act_raw_normDist_1; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_act_raw_subnormFract_T_3 = _activated_wdata_e_act_raw_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_act_raw_subnormFract_1 = {_activated_wdata_e_act_raw_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_5 = {4'hF, ~activated_wdata_e_act_raw_normDist_1}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_6 = activated_wdata_e_act_raw_isZeroExpIn_1 ? _activated_wdata_e_act_raw_adjustedExp_T_5 : {1'h0, activated_wdata_e_act_raw_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_act_raw_adjustedExp_T_7 = activated_wdata_e_act_raw_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_act_raw_adjustedExp_T_8 = {6'h20, _activated_wdata_e_act_raw_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_act_raw_adjustedExp_T_9 = {1'h0, _activated_wdata_e_act_raw_adjustedExp_T_6} + {2'h0, _activated_wdata_e_act_raw_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_act_raw_adjustedExp_1 = _activated_wdata_e_act_raw_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_act_raw_out_sExp_T_2 = activated_wdata_e_act_raw_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_act_raw_isZero_1 = activated_wdata_e_act_raw_isZeroExpIn_1 & activated_wdata_e_act_raw_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_act_raw_1_isZero = activated_wdata_e_act_raw_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_act_raw_isSpecial_T_1 = activated_wdata_e_act_raw_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_act_raw_isSpecial_1 = &_activated_wdata_e_act_raw_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_act_raw_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_act_raw_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28]
wire [9:0] _activated_wdata_e_act_raw_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_act_raw_out_sig_T_7; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_act_raw_1_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_act_raw_1_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_act_raw_1_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_act_raw_1_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_raw_out_isNaN_T_2 = ~activated_wdata_e_act_raw_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_act_raw_out_isNaN_T_3 = activated_wdata_e_act_raw_isSpecial_1 & _activated_wdata_e_act_raw_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_act_raw_1_isNaN = _activated_wdata_e_act_raw_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_act_raw_out_isInf_T_1 = activated_wdata_e_act_raw_isSpecial_1 & activated_wdata_e_act_raw_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_act_raw_1_isInf = _activated_wdata_e_act_raw_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_act_raw_out_sExp_T_3 = {1'h0, _activated_wdata_e_act_raw_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_act_raw_1_sExp = _activated_wdata_e_act_raw_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_act_raw_out_sig_T_4 = ~activated_wdata_e_act_raw_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_act_raw_out_sig_T_5 = {1'h0, _activated_wdata_e_act_raw_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_act_raw_out_sig_T_6 = activated_wdata_e_act_raw_isZeroExpIn_1 ? activated_wdata_e_act_raw_subnormFract_1 : activated_wdata_e_act_raw_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_act_raw_out_sig_T_7 = {_activated_wdata_e_act_raw_out_sig_T_5, _activated_wdata_e_act_raw_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_act_raw_1_sig = _activated_wdata_e_act_raw_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [31:0] _activated_wdata_e_act_result_bits_T_5; // @[Arithmetic.scala:514:27]
wire [31:0] activated_wdata_e_act_result_1_bits; // @[Arithmetic.scala:513:26]
wire _activated_wdata_e_act_result_bits_T_3 = ~activated_wdata_e_act_raw_1_isZero; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_result_bits_T_4 = _activated_wdata_e_act_result_bits_T_3 & activated_wdata_e_act_raw_1_sign; // @[rawFloatFromFN.scala:63:19]
assign _activated_wdata_e_act_result_bits_T_5 = _activated_wdata_e_act_result_bits_T_4 ? 32'h0 : activated_wdata_e_clipped_1_bits; // @[Arithmetic.scala:505:26, :514:{27,40}]
assign activated_wdata_e_act_result_1_bits = _activated_wdata_e_act_result_bits_T_5; // @[Arithmetic.scala:513:26, :514:27]
wire [31:0] activated_wdata_e_act_1_bits = _activated_wdata_e_act_T_1 ? activated_wdata_e_act_result_1_bits : activated_wdata_e_clipped_1_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_wdata_WIRE_1_0_bits = activated_wdata_e_act_1_bits; // @[Mux.scala:126:16]
wire [31:0] activated_wdata_1_0_bits = _activated_wdata_WIRE_1_0_bits; // @[ExecuteController.scala:925:{34,74}]
wire activated_wdata_e_clipped_self_rec_rawIn_sign_2 = _mesh_io_resp_bits_data_2_0_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_clipped_self_rec_rawIn_sign_6 = _mesh_io_resp_bits_data_2_0_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_clipped_self_rec_rawIn_sign_10 = _mesh_io_resp_bits_data_2_0_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_clipped_self_rec_rawIn_sign_14 = _mesh_io_resp_bits_data_2_0_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire self_rec_rawIn_sign_2 = _mesh_io_resp_bits_data_2_0_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_clipped_self_rec_rawIn_2_sign = activated_wdata_e_clipped_self_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_wdata_e_clipped_self_rec_rawIn_expIn_2 = _mesh_io_resp_bits_data_2_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [7:0] activated_wdata_e_clipped_self_rec_rawIn_expIn_6 = _mesh_io_resp_bits_data_2_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [7:0] activated_wdata_e_clipped_self_rec_rawIn_expIn_10 = _mesh_io_resp_bits_data_2_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [7:0] activated_wdata_e_clipped_self_rec_rawIn_expIn_14 = _mesh_io_resp_bits_data_2_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [7:0] self_rec_rawIn_expIn_2 = _mesh_io_resp_bits_data_2_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_fractIn_2 = _mesh_io_resp_bits_data_2_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_fractIn_6 = _mesh_io_resp_bits_data_2_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_fractIn_10 = _mesh_io_resp_bits_data_2_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_fractIn_14 = _mesh_io_resp_bits_data_2_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire [22:0] self_rec_rawIn_fractIn_2 = _mesh_io_resp_bits_data_2_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_2 = activated_wdata_e_clipped_self_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_2 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_88 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_89 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_90 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_91 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_92 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_93 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_94 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_95 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_96 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_97 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_98 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_99 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_100 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_101 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_102 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_103 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_104 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_105 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_106 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_107 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_108 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_109 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_110 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_111 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_112 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_113 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_114 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_115 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_116 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_117 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_95 ? 5'hF : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_118 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_96 ? 5'hE : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_119 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_97 ? 5'hD : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_120 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_98 ? 5'hC : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_121 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_99 ? 5'hB : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_122 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_100 ? 5'hA : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_123 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_124 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_125 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_126 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_127 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_128 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_129 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_130 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_131 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_clipped_self_rec_rawIn_normDist_2 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_4 = {31'h0, activated_wdata_e_clipped_self_rec_rawIn_fractIn_2} << activated_wdata_e_clipped_self_rec_rawIn_normDist_2; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_5 = _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_subnormFract_2 = {_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_wdata_e_clipped_self_rec_rawIn_normDist_2}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_11 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_2 ? _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_wdata_e_clipped_self_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_12 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_2 = _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_4 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_clipped_self_rec_rawIn_isZero_2 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_2 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_clipped_self_rec_rawIn_2_isZero = activated_wdata_e_clipped_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_2 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_clipped_self_rec_rawIn_isSpecial_2 = &_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28]
wire _activated_wdata_e_clipped_self_rec_T_18 = activated_wdata_e_clipped_self_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_clipped_self_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_clipped_self_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_clipped_self_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_4 = ~activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_5 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_2 & _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_clipped_self_rec_rawIn_2_isNaN = _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_2 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_2 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_clipped_self_rec_rawIn_2_isInf = _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_clipped_self_rec_rawIn_2_sExp = _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_8 = ~activated_wdata_e_clipped_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_9 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_10 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_2 ? activated_wdata_e_clipped_self_rec_rawIn_subnormFract_2 : activated_wdata_e_clipped_self_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_11 = {_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_9, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_clipped_self_rec_rawIn_2_sig = _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_16 = activated_wdata_e_clipped_self_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_17 = activated_wdata_e_clipped_self_rec_rawIn_2_isZero ? 3'h0 : _activated_wdata_e_clipped_self_rec_T_16; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_19 = {_activated_wdata_e_clipped_self_rec_T_17[2:1], _activated_wdata_e_clipped_self_rec_T_17[0] | _activated_wdata_e_clipped_self_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_wdata_e_clipped_self_rec_T_20 = {activated_wdata_e_clipped_self_rec_rawIn_2_sign, _activated_wdata_e_clipped_self_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_wdata_e_clipped_self_rec_T_21 = activated_wdata_e_clipped_self_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_wdata_e_clipped_self_rec_T_22 = {_activated_wdata_e_clipped_self_rec_T_20, _activated_wdata_e_clipped_self_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_wdata_e_clipped_self_rec_T_23 = activated_wdata_e_clipped_self_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_wdata_e_clipped_self_rec_2 = {_activated_wdata_e_clipped_self_rec_T_22, _activated_wdata_e_clipped_self_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_wdata_e_clipped_result_bits_T_2; // @[fNFromRecFN.scala:66:12]
wire [31:0] activated_wdata_e_clipped_2_bits; // @[Arithmetic.scala:505:26]
wire [8:0] activated_wdata_e_clipped_result_bits_rawIn_exp_2 = _activated_wdata_e_clipped_resizer_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_2 = activated_wdata_e_clipped_result_bits_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isZero_2 = _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_wdata_e_clipped_result_bits_rawIn_2_isZero = activated_wdata_e_clipped_result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_2 = activated_wdata_e_clipped_result_bits_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isSpecial_2 = &_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44]
wire activated_wdata_e_clipped_result_bits_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_wdata_e_clipped_result_bits_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_wdata_e_clipped_result_bits_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_4 = activated_wdata_e_clipped_result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_6 = activated_wdata_e_clipped_result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_5 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_2 & _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_wdata_e_clipped_result_bits_rawIn_2_isNaN = _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_7 = ~_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_8 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_2 & _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_wdata_e_clipped_result_bits_rawIn_2_isInf = _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_2 = _activated_wdata_e_clipped_resizer_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_wdata_e_clipped_result_bits_rawIn_2_sign = _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_2 = {1'h0, activated_wdata_e_clipped_result_bits_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_wdata_e_clipped_result_bits_rawIn_2_sExp = _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_8 = ~activated_wdata_e_clipped_result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_9 = {1'h0, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_10 = _activated_wdata_e_clipped_resizer_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_11 = {_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_9, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_wdata_e_clipped_result_bits_rawIn_2_sig = _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire activated_wdata_e_clipped_result_bits_isSubnormal_2 = $signed(activated_wdata_e_clipped_result_bits_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_4 = activated_wdata_e_clipped_result_bits_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_5 = 6'h1 - {1'h0, _activated_wdata_e_clipped_result_bits_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] activated_wdata_e_clipped_result_bits_denormShiftDist_2 = _activated_wdata_e_clipped_result_bits_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_4 = activated_wdata_e_clipped_result_bits_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_5 = _activated_wdata_e_clipped_result_bits_denormFract_T_4 >> activated_wdata_e_clipped_result_bits_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] activated_wdata_e_clipped_result_bits_denormFract_2 = _activated_wdata_e_clipped_result_bits_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_12 = activated_wdata_e_clipped_result_bits_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _activated_wdata_e_clipped_result_bits_expOut_T_13 = {1'h0, _activated_wdata_e_clipped_result_bits_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_14 = _activated_wdata_e_clipped_result_bits_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_15 = activated_wdata_e_clipped_result_bits_isSubnormal_2 ? 8'h0 : _activated_wdata_e_clipped_result_bits_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _activated_wdata_e_clipped_result_bits_expOut_T_16 = activated_wdata_e_clipped_result_bits_rawIn_2_isNaN | activated_wdata_e_clipped_result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_17 = {8{_activated_wdata_e_clipped_result_bits_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] activated_wdata_e_clipped_result_bits_expOut_2 = _activated_wdata_e_clipped_result_bits_expOut_T_15 | _activated_wdata_e_clipped_result_bits_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_4 = activated_wdata_e_clipped_result_bits_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_5 = activated_wdata_e_clipped_result_bits_rawIn_2_isInf ? 23'h0 : _activated_wdata_e_clipped_result_bits_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] activated_wdata_e_clipped_result_bits_fractOut_2 = activated_wdata_e_clipped_result_bits_isSubnormal_2 ? activated_wdata_e_clipped_result_bits_denormFract_2 : _activated_wdata_e_clipped_result_bits_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] activated_wdata_e_clipped_result_bits_hi_2 = {activated_wdata_e_clipped_result_bits_rawIn_2_sign, activated_wdata_e_clipped_result_bits_expOut_2}; // @[rawFloatFromRecFN.scala:55:23]
assign _activated_wdata_e_clipped_result_bits_T_2 = {activated_wdata_e_clipped_result_bits_hi_2, activated_wdata_e_clipped_result_bits_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12]
assign activated_wdata_e_clipped_2_bits = _activated_wdata_e_clipped_result_bits_T_2; // @[fNFromRecFN.scala:66:12]
wire activated_wdata_e_act_raw_sign_2 = activated_wdata_e_clipped_2_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_act_raw_2_sign = activated_wdata_e_act_raw_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_wdata_e_act_raw_expIn_2 = activated_wdata_e_clipped_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_wdata_e_act_raw_fractIn_2 = activated_wdata_e_clipped_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_wdata_e_act_raw_isZeroExpIn_2 = activated_wdata_e_act_raw_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_act_raw_isZeroFractIn_2 = activated_wdata_e_act_raw_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_act_raw_normDist_T_88 = activated_wdata_e_act_raw_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_89 = activated_wdata_e_act_raw_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_90 = activated_wdata_e_act_raw_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_91 = activated_wdata_e_act_raw_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_92 = activated_wdata_e_act_raw_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_93 = activated_wdata_e_act_raw_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_94 = activated_wdata_e_act_raw_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_95 = activated_wdata_e_act_raw_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_96 = activated_wdata_e_act_raw_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_97 = activated_wdata_e_act_raw_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_98 = activated_wdata_e_act_raw_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_99 = activated_wdata_e_act_raw_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_100 = activated_wdata_e_act_raw_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_101 = activated_wdata_e_act_raw_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_102 = activated_wdata_e_act_raw_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_103 = activated_wdata_e_act_raw_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_104 = activated_wdata_e_act_raw_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_105 = activated_wdata_e_act_raw_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_106 = activated_wdata_e_act_raw_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_107 = activated_wdata_e_act_raw_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_108 = activated_wdata_e_act_raw_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_109 = activated_wdata_e_act_raw_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_110 = activated_wdata_e_act_raw_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_111 = _activated_wdata_e_act_raw_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_112 = _activated_wdata_e_act_raw_normDist_T_90 ? 5'h14 : _activated_wdata_e_act_raw_normDist_T_111; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_113 = _activated_wdata_e_act_raw_normDist_T_91 ? 5'h13 : _activated_wdata_e_act_raw_normDist_T_112; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_114 = _activated_wdata_e_act_raw_normDist_T_92 ? 5'h12 : _activated_wdata_e_act_raw_normDist_T_113; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_115 = _activated_wdata_e_act_raw_normDist_T_93 ? 5'h11 : _activated_wdata_e_act_raw_normDist_T_114; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_116 = _activated_wdata_e_act_raw_normDist_T_94 ? 5'h10 : _activated_wdata_e_act_raw_normDist_T_115; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_117 = _activated_wdata_e_act_raw_normDist_T_95 ? 5'hF : _activated_wdata_e_act_raw_normDist_T_116; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_118 = _activated_wdata_e_act_raw_normDist_T_96 ? 5'hE : _activated_wdata_e_act_raw_normDist_T_117; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_119 = _activated_wdata_e_act_raw_normDist_T_97 ? 5'hD : _activated_wdata_e_act_raw_normDist_T_118; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_120 = _activated_wdata_e_act_raw_normDist_T_98 ? 5'hC : _activated_wdata_e_act_raw_normDist_T_119; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_121 = _activated_wdata_e_act_raw_normDist_T_99 ? 5'hB : _activated_wdata_e_act_raw_normDist_T_120; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_122 = _activated_wdata_e_act_raw_normDist_T_100 ? 5'hA : _activated_wdata_e_act_raw_normDist_T_121; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_123 = _activated_wdata_e_act_raw_normDist_T_101 ? 5'h9 : _activated_wdata_e_act_raw_normDist_T_122; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_124 = _activated_wdata_e_act_raw_normDist_T_102 ? 5'h8 : _activated_wdata_e_act_raw_normDist_T_123; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_125 = _activated_wdata_e_act_raw_normDist_T_103 ? 5'h7 : _activated_wdata_e_act_raw_normDist_T_124; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_126 = _activated_wdata_e_act_raw_normDist_T_104 ? 5'h6 : _activated_wdata_e_act_raw_normDist_T_125; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_127 = _activated_wdata_e_act_raw_normDist_T_105 ? 5'h5 : _activated_wdata_e_act_raw_normDist_T_126; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_128 = _activated_wdata_e_act_raw_normDist_T_106 ? 5'h4 : _activated_wdata_e_act_raw_normDist_T_127; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_129 = _activated_wdata_e_act_raw_normDist_T_107 ? 5'h3 : _activated_wdata_e_act_raw_normDist_T_128; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_130 = _activated_wdata_e_act_raw_normDist_T_108 ? 5'h2 : _activated_wdata_e_act_raw_normDist_T_129; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_131 = _activated_wdata_e_act_raw_normDist_T_109 ? 5'h1 : _activated_wdata_e_act_raw_normDist_T_130; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_act_raw_normDist_2 = _activated_wdata_e_act_raw_normDist_T_110 ? 5'h0 : _activated_wdata_e_act_raw_normDist_T_131; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_act_raw_subnormFract_T_4 = {31'h0, activated_wdata_e_act_raw_fractIn_2} << activated_wdata_e_act_raw_normDist_2; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_act_raw_subnormFract_T_5 = _activated_wdata_e_act_raw_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_act_raw_subnormFract_2 = {_activated_wdata_e_act_raw_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_10 = {4'hF, ~activated_wdata_e_act_raw_normDist_2}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_11 = activated_wdata_e_act_raw_isZeroExpIn_2 ? _activated_wdata_e_act_raw_adjustedExp_T_10 : {1'h0, activated_wdata_e_act_raw_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_act_raw_adjustedExp_T_12 = activated_wdata_e_act_raw_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_act_raw_adjustedExp_T_13 = {6'h20, _activated_wdata_e_act_raw_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_act_raw_adjustedExp_T_14 = {1'h0, _activated_wdata_e_act_raw_adjustedExp_T_11} + {2'h0, _activated_wdata_e_act_raw_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_act_raw_adjustedExp_2 = _activated_wdata_e_act_raw_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_act_raw_out_sExp_T_4 = activated_wdata_e_act_raw_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_act_raw_isZero_2 = activated_wdata_e_act_raw_isZeroExpIn_2 & activated_wdata_e_act_raw_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_act_raw_2_isZero = activated_wdata_e_act_raw_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_act_raw_isSpecial_T_2 = activated_wdata_e_act_raw_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_act_raw_isSpecial_2 = &_activated_wdata_e_act_raw_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_act_raw_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_act_raw_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28]
wire [9:0] _activated_wdata_e_act_raw_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_act_raw_out_sig_T_11; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_act_raw_2_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_act_raw_2_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_act_raw_2_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_act_raw_2_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_raw_out_isNaN_T_4 = ~activated_wdata_e_act_raw_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_act_raw_out_isNaN_T_5 = activated_wdata_e_act_raw_isSpecial_2 & _activated_wdata_e_act_raw_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_act_raw_2_isNaN = _activated_wdata_e_act_raw_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_act_raw_out_isInf_T_2 = activated_wdata_e_act_raw_isSpecial_2 & activated_wdata_e_act_raw_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_act_raw_2_isInf = _activated_wdata_e_act_raw_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_act_raw_out_sExp_T_5 = {1'h0, _activated_wdata_e_act_raw_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_act_raw_2_sExp = _activated_wdata_e_act_raw_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_act_raw_out_sig_T_8 = ~activated_wdata_e_act_raw_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_act_raw_out_sig_T_9 = {1'h0, _activated_wdata_e_act_raw_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_act_raw_out_sig_T_10 = activated_wdata_e_act_raw_isZeroExpIn_2 ? activated_wdata_e_act_raw_subnormFract_2 : activated_wdata_e_act_raw_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_act_raw_out_sig_T_11 = {_activated_wdata_e_act_raw_out_sig_T_9, _activated_wdata_e_act_raw_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_act_raw_2_sig = _activated_wdata_e_act_raw_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [31:0] _activated_wdata_e_act_result_bits_T_8; // @[Arithmetic.scala:514:27]
wire [31:0] activated_wdata_e_act_result_2_bits; // @[Arithmetic.scala:513:26]
wire _activated_wdata_e_act_result_bits_T_6 = ~activated_wdata_e_act_raw_2_isZero; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_result_bits_T_7 = _activated_wdata_e_act_result_bits_T_6 & activated_wdata_e_act_raw_2_sign; // @[rawFloatFromFN.scala:63:19]
assign _activated_wdata_e_act_result_bits_T_8 = _activated_wdata_e_act_result_bits_T_7 ? 32'h0 : activated_wdata_e_clipped_2_bits; // @[Arithmetic.scala:505:26, :514:{27,40}]
assign activated_wdata_e_act_result_2_bits = _activated_wdata_e_act_result_bits_T_8; // @[Arithmetic.scala:513:26, :514:27]
wire [31:0] activated_wdata_e_act_2_bits = _activated_wdata_e_act_T_2 ? activated_wdata_e_act_result_2_bits : activated_wdata_e_clipped_2_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_wdata_WIRE_2_0_bits = activated_wdata_e_act_2_bits; // @[Mux.scala:126:16]
wire [31:0] activated_wdata_2_0_bits = _activated_wdata_WIRE_2_0_bits; // @[ExecuteController.scala:925:{34,74}]
wire activated_wdata_e_clipped_self_rec_rawIn_sign_3 = _mesh_io_resp_bits_data_3_0_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_clipped_self_rec_rawIn_sign_7 = _mesh_io_resp_bits_data_3_0_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_clipped_self_rec_rawIn_sign_11 = _mesh_io_resp_bits_data_3_0_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_clipped_self_rec_rawIn_sign_15 = _mesh_io_resp_bits_data_3_0_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire self_rec_rawIn_sign_3 = _mesh_io_resp_bits_data_3_0_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_clipped_self_rec_rawIn_3_sign = activated_wdata_e_clipped_self_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_wdata_e_clipped_self_rec_rawIn_expIn_3 = _mesh_io_resp_bits_data_3_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [7:0] activated_wdata_e_clipped_self_rec_rawIn_expIn_7 = _mesh_io_resp_bits_data_3_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [7:0] activated_wdata_e_clipped_self_rec_rawIn_expIn_11 = _mesh_io_resp_bits_data_3_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [7:0] activated_wdata_e_clipped_self_rec_rawIn_expIn_15 = _mesh_io_resp_bits_data_3_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [7:0] self_rec_rawIn_expIn_3 = _mesh_io_resp_bits_data_3_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_fractIn_3 = _mesh_io_resp_bits_data_3_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_fractIn_7 = _mesh_io_resp_bits_data_3_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_fractIn_11 = _mesh_io_resp_bits_data_3_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_fractIn_15 = _mesh_io_resp_bits_data_3_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire [22:0] self_rec_rawIn_fractIn_3 = _mesh_io_resp_bits_data_3_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_3 = activated_wdata_e_clipped_self_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_3 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_132 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_133 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_134 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_135 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_136 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_137 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_138 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_139 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_140 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_141 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_142 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_143 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_144 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_145 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_146 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_147 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_148 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_149 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_150 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_151 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_152 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_153 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_154 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_155 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_156 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_157 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_158 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_159 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_160 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_161 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_139 ? 5'hF : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_162 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_140 ? 5'hE : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_163 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_141 ? 5'hD : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_164 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_142 ? 5'hC : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_165 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_143 ? 5'hB : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_166 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_144 ? 5'hA : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_167 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_168 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_169 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_170 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_171 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_172 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_173 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_174 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_175 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_clipped_self_rec_rawIn_normDist_3 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_6 = {31'h0, activated_wdata_e_clipped_self_rec_rawIn_fractIn_3} << activated_wdata_e_clipped_self_rec_rawIn_normDist_3; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_7 = _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_subnormFract_3 = {_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_wdata_e_clipped_self_rec_rawIn_normDist_3}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_16 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_3 ? _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_wdata_e_clipped_self_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_17 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_3 = _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_6 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_clipped_self_rec_rawIn_isZero_3 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_3 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_clipped_self_rec_rawIn_3_isZero = activated_wdata_e_clipped_self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_3 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_clipped_self_rec_rawIn_isSpecial_3 = &_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28]
wire _activated_wdata_e_clipped_self_rec_T_26 = activated_wdata_e_clipped_self_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_clipped_self_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_clipped_self_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_clipped_self_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_6 = ~activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_7 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_3 & _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_clipped_self_rec_rawIn_3_isNaN = _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_3 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_3 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_clipped_self_rec_rawIn_3_isInf = _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_clipped_self_rec_rawIn_3_sExp = _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_12 = ~activated_wdata_e_clipped_self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_13 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_14 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_3 ? activated_wdata_e_clipped_self_rec_rawIn_subnormFract_3 : activated_wdata_e_clipped_self_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_15 = {_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_13, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_clipped_self_rec_rawIn_3_sig = _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_24 = activated_wdata_e_clipped_self_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_25 = activated_wdata_e_clipped_self_rec_rawIn_3_isZero ? 3'h0 : _activated_wdata_e_clipped_self_rec_T_24; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_27 = {_activated_wdata_e_clipped_self_rec_T_25[2:1], _activated_wdata_e_clipped_self_rec_T_25[0] | _activated_wdata_e_clipped_self_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_wdata_e_clipped_self_rec_T_28 = {activated_wdata_e_clipped_self_rec_rawIn_3_sign, _activated_wdata_e_clipped_self_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_wdata_e_clipped_self_rec_T_29 = activated_wdata_e_clipped_self_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_wdata_e_clipped_self_rec_T_30 = {_activated_wdata_e_clipped_self_rec_T_28, _activated_wdata_e_clipped_self_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_wdata_e_clipped_self_rec_T_31 = activated_wdata_e_clipped_self_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_wdata_e_clipped_self_rec_3 = {_activated_wdata_e_clipped_self_rec_T_30, _activated_wdata_e_clipped_self_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_wdata_e_clipped_result_bits_T_3; // @[fNFromRecFN.scala:66:12]
wire [31:0] activated_wdata_e_clipped_3_bits; // @[Arithmetic.scala:505:26]
wire [8:0] activated_wdata_e_clipped_result_bits_rawIn_exp_3 = _activated_wdata_e_clipped_resizer_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_3 = activated_wdata_e_clipped_result_bits_rawIn_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isZero_3 = _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_wdata_e_clipped_result_bits_rawIn_3_isZero = activated_wdata_e_clipped_result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_3 = activated_wdata_e_clipped_result_bits_rawIn_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isSpecial_3 = &_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44]
wire activated_wdata_e_clipped_result_bits_rawIn_3_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_3_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_wdata_e_clipped_result_bits_rawIn_3_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_wdata_e_clipped_result_bits_rawIn_3_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_6 = activated_wdata_e_clipped_result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_9 = activated_wdata_e_clipped_result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_7 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_3 & _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_wdata_e_clipped_result_bits_rawIn_3_isNaN = _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_10 = ~_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_11 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_3 & _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_wdata_e_clipped_result_bits_rawIn_3_isInf = _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_3 = _activated_wdata_e_clipped_resizer_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_wdata_e_clipped_result_bits_rawIn_3_sign = _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_3 = {1'h0, activated_wdata_e_clipped_result_bits_rawIn_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_wdata_e_clipped_result_bits_rawIn_3_sExp = _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_12 = ~activated_wdata_e_clipped_result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_13 = {1'h0, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_14 = _activated_wdata_e_clipped_resizer_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_15 = {_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_13, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_wdata_e_clipped_result_bits_rawIn_3_sig = _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire activated_wdata_e_clipped_result_bits_isSubnormal_3 = $signed(activated_wdata_e_clipped_result_bits_rawIn_3_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_6 = activated_wdata_e_clipped_result_bits_rawIn_3_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_7 = 6'h1 - {1'h0, _activated_wdata_e_clipped_result_bits_denormShiftDist_T_6}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] activated_wdata_e_clipped_result_bits_denormShiftDist_3 = _activated_wdata_e_clipped_result_bits_denormShiftDist_T_7[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_6 = activated_wdata_e_clipped_result_bits_rawIn_3_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_7 = _activated_wdata_e_clipped_result_bits_denormFract_T_6 >> activated_wdata_e_clipped_result_bits_denormShiftDist_3; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] activated_wdata_e_clipped_result_bits_denormFract_3 = _activated_wdata_e_clipped_result_bits_denormFract_T_7[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_18 = activated_wdata_e_clipped_result_bits_rawIn_3_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _activated_wdata_e_clipped_result_bits_expOut_T_19 = {1'h0, _activated_wdata_e_clipped_result_bits_expOut_T_18} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_20 = _activated_wdata_e_clipped_result_bits_expOut_T_19[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_21 = activated_wdata_e_clipped_result_bits_isSubnormal_3 ? 8'h0 : _activated_wdata_e_clipped_result_bits_expOut_T_20; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _activated_wdata_e_clipped_result_bits_expOut_T_22 = activated_wdata_e_clipped_result_bits_rawIn_3_isNaN | activated_wdata_e_clipped_result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_23 = {8{_activated_wdata_e_clipped_result_bits_expOut_T_22}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] activated_wdata_e_clipped_result_bits_expOut_3 = _activated_wdata_e_clipped_result_bits_expOut_T_21 | _activated_wdata_e_clipped_result_bits_expOut_T_23; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_6 = activated_wdata_e_clipped_result_bits_rawIn_3_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_7 = activated_wdata_e_clipped_result_bits_rawIn_3_isInf ? 23'h0 : _activated_wdata_e_clipped_result_bits_fractOut_T_6; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] activated_wdata_e_clipped_result_bits_fractOut_3 = activated_wdata_e_clipped_result_bits_isSubnormal_3 ? activated_wdata_e_clipped_result_bits_denormFract_3 : _activated_wdata_e_clipped_result_bits_fractOut_T_7; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] activated_wdata_e_clipped_result_bits_hi_3 = {activated_wdata_e_clipped_result_bits_rawIn_3_sign, activated_wdata_e_clipped_result_bits_expOut_3}; // @[rawFloatFromRecFN.scala:55:23]
assign _activated_wdata_e_clipped_result_bits_T_3 = {activated_wdata_e_clipped_result_bits_hi_3, activated_wdata_e_clipped_result_bits_fractOut_3}; // @[fNFromRecFN.scala:62:16, :66:12]
assign activated_wdata_e_clipped_3_bits = _activated_wdata_e_clipped_result_bits_T_3; // @[fNFromRecFN.scala:66:12]
wire activated_wdata_e_act_raw_sign_3 = activated_wdata_e_clipped_3_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_act_raw_3_sign = activated_wdata_e_act_raw_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_wdata_e_act_raw_expIn_3 = activated_wdata_e_clipped_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_wdata_e_act_raw_fractIn_3 = activated_wdata_e_clipped_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_wdata_e_act_raw_isZeroExpIn_3 = activated_wdata_e_act_raw_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_act_raw_isZeroFractIn_3 = activated_wdata_e_act_raw_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_act_raw_normDist_T_132 = activated_wdata_e_act_raw_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_133 = activated_wdata_e_act_raw_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_134 = activated_wdata_e_act_raw_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_135 = activated_wdata_e_act_raw_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_136 = activated_wdata_e_act_raw_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_137 = activated_wdata_e_act_raw_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_138 = activated_wdata_e_act_raw_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_139 = activated_wdata_e_act_raw_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_140 = activated_wdata_e_act_raw_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_141 = activated_wdata_e_act_raw_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_142 = activated_wdata_e_act_raw_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_143 = activated_wdata_e_act_raw_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_144 = activated_wdata_e_act_raw_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_145 = activated_wdata_e_act_raw_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_146 = activated_wdata_e_act_raw_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_147 = activated_wdata_e_act_raw_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_148 = activated_wdata_e_act_raw_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_149 = activated_wdata_e_act_raw_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_150 = activated_wdata_e_act_raw_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_151 = activated_wdata_e_act_raw_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_152 = activated_wdata_e_act_raw_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_153 = activated_wdata_e_act_raw_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_154 = activated_wdata_e_act_raw_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_155 = _activated_wdata_e_act_raw_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_156 = _activated_wdata_e_act_raw_normDist_T_134 ? 5'h14 : _activated_wdata_e_act_raw_normDist_T_155; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_157 = _activated_wdata_e_act_raw_normDist_T_135 ? 5'h13 : _activated_wdata_e_act_raw_normDist_T_156; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_158 = _activated_wdata_e_act_raw_normDist_T_136 ? 5'h12 : _activated_wdata_e_act_raw_normDist_T_157; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_159 = _activated_wdata_e_act_raw_normDist_T_137 ? 5'h11 : _activated_wdata_e_act_raw_normDist_T_158; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_160 = _activated_wdata_e_act_raw_normDist_T_138 ? 5'h10 : _activated_wdata_e_act_raw_normDist_T_159; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_161 = _activated_wdata_e_act_raw_normDist_T_139 ? 5'hF : _activated_wdata_e_act_raw_normDist_T_160; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_162 = _activated_wdata_e_act_raw_normDist_T_140 ? 5'hE : _activated_wdata_e_act_raw_normDist_T_161; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_163 = _activated_wdata_e_act_raw_normDist_T_141 ? 5'hD : _activated_wdata_e_act_raw_normDist_T_162; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_164 = _activated_wdata_e_act_raw_normDist_T_142 ? 5'hC : _activated_wdata_e_act_raw_normDist_T_163; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_165 = _activated_wdata_e_act_raw_normDist_T_143 ? 5'hB : _activated_wdata_e_act_raw_normDist_T_164; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_166 = _activated_wdata_e_act_raw_normDist_T_144 ? 5'hA : _activated_wdata_e_act_raw_normDist_T_165; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_167 = _activated_wdata_e_act_raw_normDist_T_145 ? 5'h9 : _activated_wdata_e_act_raw_normDist_T_166; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_168 = _activated_wdata_e_act_raw_normDist_T_146 ? 5'h8 : _activated_wdata_e_act_raw_normDist_T_167; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_169 = _activated_wdata_e_act_raw_normDist_T_147 ? 5'h7 : _activated_wdata_e_act_raw_normDist_T_168; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_170 = _activated_wdata_e_act_raw_normDist_T_148 ? 5'h6 : _activated_wdata_e_act_raw_normDist_T_169; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_171 = _activated_wdata_e_act_raw_normDist_T_149 ? 5'h5 : _activated_wdata_e_act_raw_normDist_T_170; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_172 = _activated_wdata_e_act_raw_normDist_T_150 ? 5'h4 : _activated_wdata_e_act_raw_normDist_T_171; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_173 = _activated_wdata_e_act_raw_normDist_T_151 ? 5'h3 : _activated_wdata_e_act_raw_normDist_T_172; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_174 = _activated_wdata_e_act_raw_normDist_T_152 ? 5'h2 : _activated_wdata_e_act_raw_normDist_T_173; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_175 = _activated_wdata_e_act_raw_normDist_T_153 ? 5'h1 : _activated_wdata_e_act_raw_normDist_T_174; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_act_raw_normDist_3 = _activated_wdata_e_act_raw_normDist_T_154 ? 5'h0 : _activated_wdata_e_act_raw_normDist_T_175; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_act_raw_subnormFract_T_6 = {31'h0, activated_wdata_e_act_raw_fractIn_3} << activated_wdata_e_act_raw_normDist_3; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_act_raw_subnormFract_T_7 = _activated_wdata_e_act_raw_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_act_raw_subnormFract_3 = {_activated_wdata_e_act_raw_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_15 = {4'hF, ~activated_wdata_e_act_raw_normDist_3}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_16 = activated_wdata_e_act_raw_isZeroExpIn_3 ? _activated_wdata_e_act_raw_adjustedExp_T_15 : {1'h0, activated_wdata_e_act_raw_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_act_raw_adjustedExp_T_17 = activated_wdata_e_act_raw_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_act_raw_adjustedExp_T_18 = {6'h20, _activated_wdata_e_act_raw_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_act_raw_adjustedExp_T_19 = {1'h0, _activated_wdata_e_act_raw_adjustedExp_T_16} + {2'h0, _activated_wdata_e_act_raw_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_act_raw_adjustedExp_3 = _activated_wdata_e_act_raw_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_act_raw_out_sExp_T_6 = activated_wdata_e_act_raw_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_act_raw_isZero_3 = activated_wdata_e_act_raw_isZeroExpIn_3 & activated_wdata_e_act_raw_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_act_raw_3_isZero = activated_wdata_e_act_raw_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_act_raw_isSpecial_T_3 = activated_wdata_e_act_raw_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_act_raw_isSpecial_3 = &_activated_wdata_e_act_raw_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_act_raw_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_act_raw_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28]
wire [9:0] _activated_wdata_e_act_raw_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_act_raw_out_sig_T_15; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_act_raw_3_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_act_raw_3_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_act_raw_3_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_act_raw_3_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_raw_out_isNaN_T_6 = ~activated_wdata_e_act_raw_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_act_raw_out_isNaN_T_7 = activated_wdata_e_act_raw_isSpecial_3 & _activated_wdata_e_act_raw_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_act_raw_3_isNaN = _activated_wdata_e_act_raw_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_act_raw_out_isInf_T_3 = activated_wdata_e_act_raw_isSpecial_3 & activated_wdata_e_act_raw_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_act_raw_3_isInf = _activated_wdata_e_act_raw_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_act_raw_out_sExp_T_7 = {1'h0, _activated_wdata_e_act_raw_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_act_raw_3_sExp = _activated_wdata_e_act_raw_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_act_raw_out_sig_T_12 = ~activated_wdata_e_act_raw_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_act_raw_out_sig_T_13 = {1'h0, _activated_wdata_e_act_raw_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_act_raw_out_sig_T_14 = activated_wdata_e_act_raw_isZeroExpIn_3 ? activated_wdata_e_act_raw_subnormFract_3 : activated_wdata_e_act_raw_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_act_raw_out_sig_T_15 = {_activated_wdata_e_act_raw_out_sig_T_13, _activated_wdata_e_act_raw_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_act_raw_3_sig = _activated_wdata_e_act_raw_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [31:0] _activated_wdata_e_act_result_bits_T_11; // @[Arithmetic.scala:514:27]
wire [31:0] activated_wdata_e_act_result_3_bits; // @[Arithmetic.scala:513:26]
wire _activated_wdata_e_act_result_bits_T_9 = ~activated_wdata_e_act_raw_3_isZero; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_result_bits_T_10 = _activated_wdata_e_act_result_bits_T_9 & activated_wdata_e_act_raw_3_sign; // @[rawFloatFromFN.scala:63:19]
assign _activated_wdata_e_act_result_bits_T_11 = _activated_wdata_e_act_result_bits_T_10 ? 32'h0 : activated_wdata_e_clipped_3_bits; // @[Arithmetic.scala:505:26, :514:{27,40}]
assign activated_wdata_e_act_result_3_bits = _activated_wdata_e_act_result_bits_T_11; // @[Arithmetic.scala:513:26, :514:27]
wire [31:0] activated_wdata_e_act_3_bits = _activated_wdata_e_act_T_3 ? activated_wdata_e_act_result_3_bits : activated_wdata_e_clipped_3_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_wdata_WIRE_3_0_bits = activated_wdata_e_act_3_bits; // @[Mux.scala:126:16]
wire [31:0] activated_wdata_3_0_bits = _activated_wdata_WIRE_3_0_bits; // @[ExecuteController.scala:925:{34,74}]
wire _GEN_91 = w_bank == 2'h0; // @[ExecuteController.scala:911:19, :934:64]
wire _io_srams_write_0_en_T; // @[ExecuteController.scala:934:64]
assign _io_srams_write_0_en_T = _GEN_91; // @[ExecuteController.scala:934:64]
wire _io_acc_write_0_valid_T; // @[ExecuteController.scala:949:65]
assign _io_acc_write_0_valid_T = _GEN_91; // @[ExecuteController.scala:934:64, :949:65]
wire _io_srams_write_0_en_T_1 = start_array_outputting & _io_srams_write_0_en_T; // @[ExecuteController.scala:270:40, :934:{54,64}]
wire _io_srams_write_0_en_T_2 = ~w_address_is_acc_addr; // @[ExecuteController.scala:907:22, :934:75]
wire _io_srams_write_0_en_T_3 = _io_srams_write_0_en_T_1 & _io_srams_write_0_en_T_2; // @[ExecuteController.scala:934:{54,72,75}]
wire _io_srams_write_0_en_T_4 = ~is_garbage_addr; // @[LocalAddr.scala:43:96]
wire _io_srams_write_0_en_T_5 = _io_srams_write_0_en_T_3 & _io_srams_write_0_en_T_4; // @[ExecuteController.scala:934:{72,89,92}]
assign _io_srams_write_0_en_T_6 = _io_srams_write_0_en_T_5 & write_this_row; // @[ExecuteController.scala:919:27, :934:{89,109}]
assign io_srams_write_0_en_0 = _io_srams_write_0_en_T_6; // @[ExecuteController.scala:12:7, :934:109]
wire [63:0] io_srams_write_0_data_lo = {activated_wdata_1_0_bits, activated_wdata_0_0_bits}; // @[ExecuteController.scala:925:34, :936:49]
wire [63:0] io_srams_write_0_data_hi = {activated_wdata_3_0_bits, activated_wdata_2_0_bits}; // @[ExecuteController.scala:925:34, :936:49]
assign _io_srams_write_0_data_T = {io_srams_write_0_data_hi, io_srams_write_0_data_lo}; // @[ExecuteController.scala:936:49]
assign io_srams_write_0_data_0 = _io_srams_write_0_data_T; // @[ExecuteController.scala:12:7, :936:49]
wire activated_wdata_e_clipped_self_rec_rawIn_4_sign = activated_wdata_e_clipped_self_rec_rawIn_sign_4; // @[rawFloatFromFN.scala:44:18, :63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_4 = activated_wdata_e_clipped_self_rec_rawIn_expIn_4 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_4 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_176 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_177 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_178 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_179 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_180 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_181 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_182 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_183 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_184 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_185 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_186 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_187 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_188 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_189 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_190 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_191 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_192 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_193 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_194 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_195 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_196 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_197 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_198 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_4[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_199 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_177 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_200 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_178 ? 5'h14 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_199; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_201 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_179 ? 5'h13 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_200; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_202 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_180 ? 5'h12 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_201; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_203 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_181 ? 5'h11 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_202; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_204 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_182 ? 5'h10 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_203; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_205 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_183 ? 5'hF : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_204; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_206 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_184 ? 5'hE : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_205; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_207 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_185 ? 5'hD : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_206; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_208 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_186 ? 5'hC : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_207; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_209 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_187 ? 5'hB : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_208; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_210 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_188 ? 5'hA : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_209; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_211 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_189 ? 5'h9 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_210; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_212 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_190 ? 5'h8 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_211; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_213 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_191 ? 5'h7 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_212; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_214 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_192 ? 5'h6 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_213; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_215 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_193 ? 5'h5 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_214; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_216 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_194 ? 5'h4 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_215; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_217 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_195 ? 5'h3 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_216; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_218 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_196 ? 5'h2 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_217; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_219 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_197 ? 5'h1 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_218; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_clipped_self_rec_rawIn_normDist_4 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_198 ? 5'h0 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_219; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_8 = {31'h0, activated_wdata_e_clipped_self_rec_rawIn_fractIn_4} << activated_wdata_e_clipped_self_rec_rawIn_normDist_4; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_9 = _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_8[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_subnormFract_4 = {_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_9, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_20 = {4'hF, ~activated_wdata_e_clipped_self_rec_rawIn_normDist_4}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_21 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_4 ? _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_20 : {1'h0, activated_wdata_e_clipped_self_rec_rawIn_expIn_4}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_22 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_4 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_23 = {6'h20, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_22}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_24 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_21} + {2'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_23}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_4 = _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_24[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_8 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_4; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_clipped_self_rec_rawIn_isZero_4 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_4 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_clipped_self_rec_rawIn_4_isZero = activated_wdata_e_clipped_self_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_4 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_4[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_clipped_self_rec_rawIn_isSpecial_4 = &_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_4; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:65:28]
wire _activated_wdata_e_clipped_self_rec_T_34 = activated_wdata_e_clipped_self_rec_rawIn_4_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_clipped_self_rec_rawIn_4_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_clipped_self_rec_rawIn_4_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_clipped_self_rec_rawIn_4_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_8 = ~activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_9 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_4 & _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_8; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_clipped_self_rec_rawIn_4_isNaN = _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_4 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_4 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_clipped_self_rec_rawIn_4_isInf = _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_9 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_8}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_clipped_self_rec_rawIn_4_sExp = _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_16 = ~activated_wdata_e_clipped_self_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_17 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_16}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_18 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_4 ? activated_wdata_e_clipped_self_rec_rawIn_subnormFract_4 : activated_wdata_e_clipped_self_rec_rawIn_fractIn_4; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_19 = {_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_17, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_18}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_clipped_self_rec_rawIn_4_sig = _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_32 = activated_wdata_e_clipped_self_rec_rawIn_4_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_33 = activated_wdata_e_clipped_self_rec_rawIn_4_isZero ? 3'h0 : _activated_wdata_e_clipped_self_rec_T_32; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_35 = {_activated_wdata_e_clipped_self_rec_T_33[2:1], _activated_wdata_e_clipped_self_rec_T_33[0] | _activated_wdata_e_clipped_self_rec_T_34}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_wdata_e_clipped_self_rec_T_36 = {activated_wdata_e_clipped_self_rec_rawIn_4_sign, _activated_wdata_e_clipped_self_rec_T_35}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_wdata_e_clipped_self_rec_T_37 = activated_wdata_e_clipped_self_rec_rawIn_4_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_wdata_e_clipped_self_rec_T_38 = {_activated_wdata_e_clipped_self_rec_T_36, _activated_wdata_e_clipped_self_rec_T_37}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_wdata_e_clipped_self_rec_T_39 = activated_wdata_e_clipped_self_rec_rawIn_4_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_wdata_e_clipped_self_rec_4 = {_activated_wdata_e_clipped_self_rec_T_38, _activated_wdata_e_clipped_self_rec_T_39}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_wdata_e_clipped_result_bits_T_4; // @[fNFromRecFN.scala:66:12]
wire [31:0] activated_wdata_e_clipped_4_bits; // @[Arithmetic.scala:505:26]
wire [8:0] activated_wdata_e_clipped_result_bits_rawIn_exp_4 = _activated_wdata_e_clipped_resizer_4_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_4 = activated_wdata_e_clipped_result_bits_rawIn_exp_4[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isZero_4 = _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_4 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_wdata_e_clipped_result_bits_rawIn_4_isZero = activated_wdata_e_clipped_result_bits_rawIn_isZero_4; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_4 = activated_wdata_e_clipped_result_bits_rawIn_exp_4[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isSpecial_4 = &_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_4; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_9; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_14; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_4; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_4; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_19; // @[rawFloatFromRecFN.scala:61:44]
wire activated_wdata_e_clipped_result_bits_rawIn_4_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_4_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_4_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_wdata_e_clipped_result_bits_rawIn_4_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_wdata_e_clipped_result_bits_rawIn_4_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_8 = activated_wdata_e_clipped_result_bits_rawIn_exp_4[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_12 = activated_wdata_e_clipped_result_bits_rawIn_exp_4[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_9 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_4 & _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_8; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_wdata_e_clipped_result_bits_rawIn_4_isNaN = _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_9; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_13 = ~_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_12; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_14 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_4 & _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_13; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_wdata_e_clipped_result_bits_rawIn_4_isInf = _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_14; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_4 = _activated_wdata_e_clipped_resizer_4_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_wdata_e_clipped_result_bits_rawIn_4_sign = _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_4; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_4 = {1'h0, activated_wdata_e_clipped_result_bits_rawIn_exp_4}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_wdata_e_clipped_result_bits_rawIn_4_sExp = _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_4; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_16 = ~activated_wdata_e_clipped_result_bits_rawIn_isZero_4; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_17 = {1'h0, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_16}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_18 = _activated_wdata_e_clipped_resizer_4_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_19 = {_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_17, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_18}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_wdata_e_clipped_result_bits_rawIn_4_sig = _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_19; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire activated_wdata_e_clipped_result_bits_isSubnormal_4 = $signed(activated_wdata_e_clipped_result_bits_rawIn_4_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_8 = activated_wdata_e_clipped_result_bits_rawIn_4_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_9 = 6'h1 - {1'h0, _activated_wdata_e_clipped_result_bits_denormShiftDist_T_8}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] activated_wdata_e_clipped_result_bits_denormShiftDist_4 = _activated_wdata_e_clipped_result_bits_denormShiftDist_T_9[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_8 = activated_wdata_e_clipped_result_bits_rawIn_4_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_9 = _activated_wdata_e_clipped_result_bits_denormFract_T_8 >> activated_wdata_e_clipped_result_bits_denormShiftDist_4; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] activated_wdata_e_clipped_result_bits_denormFract_4 = _activated_wdata_e_clipped_result_bits_denormFract_T_9[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_24 = activated_wdata_e_clipped_result_bits_rawIn_4_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _activated_wdata_e_clipped_result_bits_expOut_T_25 = {1'h0, _activated_wdata_e_clipped_result_bits_expOut_T_24} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_26 = _activated_wdata_e_clipped_result_bits_expOut_T_25[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_27 = activated_wdata_e_clipped_result_bits_isSubnormal_4 ? 8'h0 : _activated_wdata_e_clipped_result_bits_expOut_T_26; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _activated_wdata_e_clipped_result_bits_expOut_T_28 = activated_wdata_e_clipped_result_bits_rawIn_4_isNaN | activated_wdata_e_clipped_result_bits_rawIn_4_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_29 = {8{_activated_wdata_e_clipped_result_bits_expOut_T_28}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] activated_wdata_e_clipped_result_bits_expOut_4 = _activated_wdata_e_clipped_result_bits_expOut_T_27 | _activated_wdata_e_clipped_result_bits_expOut_T_29; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_8 = activated_wdata_e_clipped_result_bits_rawIn_4_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_9 = activated_wdata_e_clipped_result_bits_rawIn_4_isInf ? 23'h0 : _activated_wdata_e_clipped_result_bits_fractOut_T_8; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] activated_wdata_e_clipped_result_bits_fractOut_4 = activated_wdata_e_clipped_result_bits_isSubnormal_4 ? activated_wdata_e_clipped_result_bits_denormFract_4 : _activated_wdata_e_clipped_result_bits_fractOut_T_9; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] activated_wdata_e_clipped_result_bits_hi_4 = {activated_wdata_e_clipped_result_bits_rawIn_4_sign, activated_wdata_e_clipped_result_bits_expOut_4}; // @[rawFloatFromRecFN.scala:55:23]
assign _activated_wdata_e_clipped_result_bits_T_4 = {activated_wdata_e_clipped_result_bits_hi_4, activated_wdata_e_clipped_result_bits_fractOut_4}; // @[fNFromRecFN.scala:62:16, :66:12]
assign activated_wdata_e_clipped_4_bits = _activated_wdata_e_clipped_result_bits_T_4; // @[fNFromRecFN.scala:66:12]
wire activated_wdata_e_act_raw_sign_4 = activated_wdata_e_clipped_4_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_act_raw_4_sign = activated_wdata_e_act_raw_sign_4; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_wdata_e_act_raw_expIn_4 = activated_wdata_e_clipped_4_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_wdata_e_act_raw_fractIn_4 = activated_wdata_e_clipped_4_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_wdata_e_act_raw_isZeroExpIn_4 = activated_wdata_e_act_raw_expIn_4 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_act_raw_isZeroFractIn_4 = activated_wdata_e_act_raw_fractIn_4 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_act_raw_normDist_T_176 = activated_wdata_e_act_raw_fractIn_4[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_177 = activated_wdata_e_act_raw_fractIn_4[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_178 = activated_wdata_e_act_raw_fractIn_4[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_179 = activated_wdata_e_act_raw_fractIn_4[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_180 = activated_wdata_e_act_raw_fractIn_4[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_181 = activated_wdata_e_act_raw_fractIn_4[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_182 = activated_wdata_e_act_raw_fractIn_4[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_183 = activated_wdata_e_act_raw_fractIn_4[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_184 = activated_wdata_e_act_raw_fractIn_4[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_185 = activated_wdata_e_act_raw_fractIn_4[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_186 = activated_wdata_e_act_raw_fractIn_4[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_187 = activated_wdata_e_act_raw_fractIn_4[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_188 = activated_wdata_e_act_raw_fractIn_4[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_189 = activated_wdata_e_act_raw_fractIn_4[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_190 = activated_wdata_e_act_raw_fractIn_4[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_191 = activated_wdata_e_act_raw_fractIn_4[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_192 = activated_wdata_e_act_raw_fractIn_4[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_193 = activated_wdata_e_act_raw_fractIn_4[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_194 = activated_wdata_e_act_raw_fractIn_4[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_195 = activated_wdata_e_act_raw_fractIn_4[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_196 = activated_wdata_e_act_raw_fractIn_4[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_197 = activated_wdata_e_act_raw_fractIn_4[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_198 = activated_wdata_e_act_raw_fractIn_4[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_199 = _activated_wdata_e_act_raw_normDist_T_177 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_200 = _activated_wdata_e_act_raw_normDist_T_178 ? 5'h14 : _activated_wdata_e_act_raw_normDist_T_199; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_201 = _activated_wdata_e_act_raw_normDist_T_179 ? 5'h13 : _activated_wdata_e_act_raw_normDist_T_200; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_202 = _activated_wdata_e_act_raw_normDist_T_180 ? 5'h12 : _activated_wdata_e_act_raw_normDist_T_201; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_203 = _activated_wdata_e_act_raw_normDist_T_181 ? 5'h11 : _activated_wdata_e_act_raw_normDist_T_202; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_204 = _activated_wdata_e_act_raw_normDist_T_182 ? 5'h10 : _activated_wdata_e_act_raw_normDist_T_203; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_205 = _activated_wdata_e_act_raw_normDist_T_183 ? 5'hF : _activated_wdata_e_act_raw_normDist_T_204; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_206 = _activated_wdata_e_act_raw_normDist_T_184 ? 5'hE : _activated_wdata_e_act_raw_normDist_T_205; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_207 = _activated_wdata_e_act_raw_normDist_T_185 ? 5'hD : _activated_wdata_e_act_raw_normDist_T_206; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_208 = _activated_wdata_e_act_raw_normDist_T_186 ? 5'hC : _activated_wdata_e_act_raw_normDist_T_207; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_209 = _activated_wdata_e_act_raw_normDist_T_187 ? 5'hB : _activated_wdata_e_act_raw_normDist_T_208; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_210 = _activated_wdata_e_act_raw_normDist_T_188 ? 5'hA : _activated_wdata_e_act_raw_normDist_T_209; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_211 = _activated_wdata_e_act_raw_normDist_T_189 ? 5'h9 : _activated_wdata_e_act_raw_normDist_T_210; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_212 = _activated_wdata_e_act_raw_normDist_T_190 ? 5'h8 : _activated_wdata_e_act_raw_normDist_T_211; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_213 = _activated_wdata_e_act_raw_normDist_T_191 ? 5'h7 : _activated_wdata_e_act_raw_normDist_T_212; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_214 = _activated_wdata_e_act_raw_normDist_T_192 ? 5'h6 : _activated_wdata_e_act_raw_normDist_T_213; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_215 = _activated_wdata_e_act_raw_normDist_T_193 ? 5'h5 : _activated_wdata_e_act_raw_normDist_T_214; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_216 = _activated_wdata_e_act_raw_normDist_T_194 ? 5'h4 : _activated_wdata_e_act_raw_normDist_T_215; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_217 = _activated_wdata_e_act_raw_normDist_T_195 ? 5'h3 : _activated_wdata_e_act_raw_normDist_T_216; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_218 = _activated_wdata_e_act_raw_normDist_T_196 ? 5'h2 : _activated_wdata_e_act_raw_normDist_T_217; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_219 = _activated_wdata_e_act_raw_normDist_T_197 ? 5'h1 : _activated_wdata_e_act_raw_normDist_T_218; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_act_raw_normDist_4 = _activated_wdata_e_act_raw_normDist_T_198 ? 5'h0 : _activated_wdata_e_act_raw_normDist_T_219; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_act_raw_subnormFract_T_8 = {31'h0, activated_wdata_e_act_raw_fractIn_4} << activated_wdata_e_act_raw_normDist_4; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_act_raw_subnormFract_T_9 = _activated_wdata_e_act_raw_subnormFract_T_8[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_act_raw_subnormFract_4 = {_activated_wdata_e_act_raw_subnormFract_T_9, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_20 = {4'hF, ~activated_wdata_e_act_raw_normDist_4}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_21 = activated_wdata_e_act_raw_isZeroExpIn_4 ? _activated_wdata_e_act_raw_adjustedExp_T_20 : {1'h0, activated_wdata_e_act_raw_expIn_4}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_act_raw_adjustedExp_T_22 = activated_wdata_e_act_raw_isZeroExpIn_4 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_act_raw_adjustedExp_T_23 = {6'h20, _activated_wdata_e_act_raw_adjustedExp_T_22}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_act_raw_adjustedExp_T_24 = {1'h0, _activated_wdata_e_act_raw_adjustedExp_T_21} + {2'h0, _activated_wdata_e_act_raw_adjustedExp_T_23}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_act_raw_adjustedExp_4 = _activated_wdata_e_act_raw_adjustedExp_T_24[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_act_raw_out_sExp_T_8 = activated_wdata_e_act_raw_adjustedExp_4; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_act_raw_isZero_4 = activated_wdata_e_act_raw_isZeroExpIn_4 & activated_wdata_e_act_raw_isZeroFractIn_4; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_act_raw_4_isZero = activated_wdata_e_act_raw_isZero_4; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_act_raw_isSpecial_T_4 = activated_wdata_e_act_raw_adjustedExp_4[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_act_raw_isSpecial_4 = &_activated_wdata_e_act_raw_isSpecial_T_4; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_act_raw_out_isNaN_T_9; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_act_raw_out_isInf_T_4; // @[rawFloatFromFN.scala:65:28]
wire [9:0] _activated_wdata_e_act_raw_out_sExp_T_9; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_act_raw_out_sig_T_19; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_act_raw_4_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_act_raw_4_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_act_raw_4_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_act_raw_4_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_raw_out_isNaN_T_8 = ~activated_wdata_e_act_raw_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_act_raw_out_isNaN_T_9 = activated_wdata_e_act_raw_isSpecial_4 & _activated_wdata_e_act_raw_out_isNaN_T_8; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_act_raw_4_isNaN = _activated_wdata_e_act_raw_out_isNaN_T_9; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_act_raw_out_isInf_T_4 = activated_wdata_e_act_raw_isSpecial_4 & activated_wdata_e_act_raw_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_act_raw_4_isInf = _activated_wdata_e_act_raw_out_isInf_T_4; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_act_raw_out_sExp_T_9 = {1'h0, _activated_wdata_e_act_raw_out_sExp_T_8}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_act_raw_4_sExp = _activated_wdata_e_act_raw_out_sExp_T_9; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_act_raw_out_sig_T_16 = ~activated_wdata_e_act_raw_isZero_4; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_act_raw_out_sig_T_17 = {1'h0, _activated_wdata_e_act_raw_out_sig_T_16}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_act_raw_out_sig_T_18 = activated_wdata_e_act_raw_isZeroExpIn_4 ? activated_wdata_e_act_raw_subnormFract_4 : activated_wdata_e_act_raw_fractIn_4; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_act_raw_out_sig_T_19 = {_activated_wdata_e_act_raw_out_sig_T_17, _activated_wdata_e_act_raw_out_sig_T_18}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_act_raw_4_sig = _activated_wdata_e_act_raw_out_sig_T_19; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [31:0] _activated_wdata_e_act_result_bits_T_14; // @[Arithmetic.scala:514:27]
wire [31:0] activated_wdata_e_act_result_4_bits; // @[Arithmetic.scala:513:26]
wire _activated_wdata_e_act_result_bits_T_12 = ~activated_wdata_e_act_raw_4_isZero; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_result_bits_T_13 = _activated_wdata_e_act_result_bits_T_12 & activated_wdata_e_act_raw_4_sign; // @[rawFloatFromFN.scala:63:19]
assign _activated_wdata_e_act_result_bits_T_14 = _activated_wdata_e_act_result_bits_T_13 ? 32'h0 : activated_wdata_e_clipped_4_bits; // @[Arithmetic.scala:505:26, :514:{27,40}]
assign activated_wdata_e_act_result_4_bits = _activated_wdata_e_act_result_bits_T_14; // @[Arithmetic.scala:513:26, :514:27]
wire [31:0] activated_wdata_e_act_4_bits = _activated_wdata_e_act_T_4 ? activated_wdata_e_act_result_4_bits : activated_wdata_e_clipped_4_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_wdata_WIRE_4_0_bits = activated_wdata_e_act_4_bits; // @[Mux.scala:126:16]
wire [31:0] activated_wdata_1_0_0_bits = _activated_wdata_WIRE_4_0_bits; // @[ExecuteController.scala:925:{34,74}]
wire activated_wdata_e_clipped_self_rec_rawIn_5_sign = activated_wdata_e_clipped_self_rec_rawIn_sign_5; // @[rawFloatFromFN.scala:44:18, :63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_5 = activated_wdata_e_clipped_self_rec_rawIn_expIn_5 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_5 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_220 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_221 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_222 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_223 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_224 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_225 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_226 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_227 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_228 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_229 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_230 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_231 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_232 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_233 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_234 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_235 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_236 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_237 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_238 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_239 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_240 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_241 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_242 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_5[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_243 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_221 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_244 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_222 ? 5'h14 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_243; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_245 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_223 ? 5'h13 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_244; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_246 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_224 ? 5'h12 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_245; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_247 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_225 ? 5'h11 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_246; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_248 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_226 ? 5'h10 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_247; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_249 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_227 ? 5'hF : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_248; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_250 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_228 ? 5'hE : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_249; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_251 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_229 ? 5'hD : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_250; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_252 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_230 ? 5'hC : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_251; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_253 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_231 ? 5'hB : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_252; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_254 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_232 ? 5'hA : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_253; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_255 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_233 ? 5'h9 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_254; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_256 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_234 ? 5'h8 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_255; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_257 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_235 ? 5'h7 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_256; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_258 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_236 ? 5'h6 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_257; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_259 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_237 ? 5'h5 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_258; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_260 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_238 ? 5'h4 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_259; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_261 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_239 ? 5'h3 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_260; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_262 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_240 ? 5'h2 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_261; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_263 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_241 ? 5'h1 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_262; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_clipped_self_rec_rawIn_normDist_5 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_242 ? 5'h0 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_263; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_10 = {31'h0, activated_wdata_e_clipped_self_rec_rawIn_fractIn_5} << activated_wdata_e_clipped_self_rec_rawIn_normDist_5; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_11 = _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_10[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_subnormFract_5 = {_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_11, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_25 = {4'hF, ~activated_wdata_e_clipped_self_rec_rawIn_normDist_5}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_26 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_5 ? _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_25 : {1'h0, activated_wdata_e_clipped_self_rec_rawIn_expIn_5}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_27 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_5 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_28 = {6'h20, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_27}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_29 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_26} + {2'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_28}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_5 = _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_29[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_10 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_5; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_clipped_self_rec_rawIn_isZero_5 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_5 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_clipped_self_rec_rawIn_5_isZero = activated_wdata_e_clipped_self_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_5 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_5[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_clipped_self_rec_rawIn_isSpecial_5 = &_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_5; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:65:28]
wire _activated_wdata_e_clipped_self_rec_T_42 = activated_wdata_e_clipped_self_rec_rawIn_5_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_clipped_self_rec_rawIn_5_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_clipped_self_rec_rawIn_5_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_clipped_self_rec_rawIn_5_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_10 = ~activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_11 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_5 & _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_10; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_clipped_self_rec_rawIn_5_isNaN = _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_5 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_5 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_clipped_self_rec_rawIn_5_isInf = _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_11 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_10}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_clipped_self_rec_rawIn_5_sExp = _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_20 = ~activated_wdata_e_clipped_self_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_21 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_20}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_22 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_5 ? activated_wdata_e_clipped_self_rec_rawIn_subnormFract_5 : activated_wdata_e_clipped_self_rec_rawIn_fractIn_5; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_23 = {_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_21, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_22}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_clipped_self_rec_rawIn_5_sig = _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_40 = activated_wdata_e_clipped_self_rec_rawIn_5_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_41 = activated_wdata_e_clipped_self_rec_rawIn_5_isZero ? 3'h0 : _activated_wdata_e_clipped_self_rec_T_40; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_43 = {_activated_wdata_e_clipped_self_rec_T_41[2:1], _activated_wdata_e_clipped_self_rec_T_41[0] | _activated_wdata_e_clipped_self_rec_T_42}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_wdata_e_clipped_self_rec_T_44 = {activated_wdata_e_clipped_self_rec_rawIn_5_sign, _activated_wdata_e_clipped_self_rec_T_43}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_wdata_e_clipped_self_rec_T_45 = activated_wdata_e_clipped_self_rec_rawIn_5_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_wdata_e_clipped_self_rec_T_46 = {_activated_wdata_e_clipped_self_rec_T_44, _activated_wdata_e_clipped_self_rec_T_45}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_wdata_e_clipped_self_rec_T_47 = activated_wdata_e_clipped_self_rec_rawIn_5_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_wdata_e_clipped_self_rec_5 = {_activated_wdata_e_clipped_self_rec_T_46, _activated_wdata_e_clipped_self_rec_T_47}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_wdata_e_clipped_result_bits_T_5; // @[fNFromRecFN.scala:66:12]
wire [31:0] activated_wdata_e_clipped_5_bits; // @[Arithmetic.scala:505:26]
wire [8:0] activated_wdata_e_clipped_result_bits_rawIn_exp_5 = _activated_wdata_e_clipped_resizer_5_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_5 = activated_wdata_e_clipped_result_bits_rawIn_exp_5[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isZero_5 = _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_5 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_wdata_e_clipped_result_bits_rawIn_5_isZero = activated_wdata_e_clipped_result_bits_rawIn_isZero_5; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_5 = activated_wdata_e_clipped_result_bits_rawIn_exp_5[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isSpecial_5 = &_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_5; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_11; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_17; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_5; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_5; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_23; // @[rawFloatFromRecFN.scala:61:44]
wire activated_wdata_e_clipped_result_bits_rawIn_5_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_5_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_5_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_wdata_e_clipped_result_bits_rawIn_5_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_wdata_e_clipped_result_bits_rawIn_5_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_10 = activated_wdata_e_clipped_result_bits_rawIn_exp_5[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_15 = activated_wdata_e_clipped_result_bits_rawIn_exp_5[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_11 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_5 & _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_10; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_wdata_e_clipped_result_bits_rawIn_5_isNaN = _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_11; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_16 = ~_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_15; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_17 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_5 & _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_16; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_wdata_e_clipped_result_bits_rawIn_5_isInf = _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_17; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_5 = _activated_wdata_e_clipped_resizer_5_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_wdata_e_clipped_result_bits_rawIn_5_sign = _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_5; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_5 = {1'h0, activated_wdata_e_clipped_result_bits_rawIn_exp_5}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_wdata_e_clipped_result_bits_rawIn_5_sExp = _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_5; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_20 = ~activated_wdata_e_clipped_result_bits_rawIn_isZero_5; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_21 = {1'h0, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_20}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_22 = _activated_wdata_e_clipped_resizer_5_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_23 = {_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_21, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_22}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_wdata_e_clipped_result_bits_rawIn_5_sig = _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_23; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire activated_wdata_e_clipped_result_bits_isSubnormal_5 = $signed(activated_wdata_e_clipped_result_bits_rawIn_5_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_10 = activated_wdata_e_clipped_result_bits_rawIn_5_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_11 = 6'h1 - {1'h0, _activated_wdata_e_clipped_result_bits_denormShiftDist_T_10}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] activated_wdata_e_clipped_result_bits_denormShiftDist_5 = _activated_wdata_e_clipped_result_bits_denormShiftDist_T_11[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_10 = activated_wdata_e_clipped_result_bits_rawIn_5_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_11 = _activated_wdata_e_clipped_result_bits_denormFract_T_10 >> activated_wdata_e_clipped_result_bits_denormShiftDist_5; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] activated_wdata_e_clipped_result_bits_denormFract_5 = _activated_wdata_e_clipped_result_bits_denormFract_T_11[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_30 = activated_wdata_e_clipped_result_bits_rawIn_5_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _activated_wdata_e_clipped_result_bits_expOut_T_31 = {1'h0, _activated_wdata_e_clipped_result_bits_expOut_T_30} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_32 = _activated_wdata_e_clipped_result_bits_expOut_T_31[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_33 = activated_wdata_e_clipped_result_bits_isSubnormal_5 ? 8'h0 : _activated_wdata_e_clipped_result_bits_expOut_T_32; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _activated_wdata_e_clipped_result_bits_expOut_T_34 = activated_wdata_e_clipped_result_bits_rawIn_5_isNaN | activated_wdata_e_clipped_result_bits_rawIn_5_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_35 = {8{_activated_wdata_e_clipped_result_bits_expOut_T_34}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] activated_wdata_e_clipped_result_bits_expOut_5 = _activated_wdata_e_clipped_result_bits_expOut_T_33 | _activated_wdata_e_clipped_result_bits_expOut_T_35; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_10 = activated_wdata_e_clipped_result_bits_rawIn_5_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_11 = activated_wdata_e_clipped_result_bits_rawIn_5_isInf ? 23'h0 : _activated_wdata_e_clipped_result_bits_fractOut_T_10; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] activated_wdata_e_clipped_result_bits_fractOut_5 = activated_wdata_e_clipped_result_bits_isSubnormal_5 ? activated_wdata_e_clipped_result_bits_denormFract_5 : _activated_wdata_e_clipped_result_bits_fractOut_T_11; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] activated_wdata_e_clipped_result_bits_hi_5 = {activated_wdata_e_clipped_result_bits_rawIn_5_sign, activated_wdata_e_clipped_result_bits_expOut_5}; // @[rawFloatFromRecFN.scala:55:23]
assign _activated_wdata_e_clipped_result_bits_T_5 = {activated_wdata_e_clipped_result_bits_hi_5, activated_wdata_e_clipped_result_bits_fractOut_5}; // @[fNFromRecFN.scala:62:16, :66:12]
assign activated_wdata_e_clipped_5_bits = _activated_wdata_e_clipped_result_bits_T_5; // @[fNFromRecFN.scala:66:12]
wire activated_wdata_e_act_raw_sign_5 = activated_wdata_e_clipped_5_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_act_raw_5_sign = activated_wdata_e_act_raw_sign_5; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_wdata_e_act_raw_expIn_5 = activated_wdata_e_clipped_5_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_wdata_e_act_raw_fractIn_5 = activated_wdata_e_clipped_5_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_wdata_e_act_raw_isZeroExpIn_5 = activated_wdata_e_act_raw_expIn_5 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_act_raw_isZeroFractIn_5 = activated_wdata_e_act_raw_fractIn_5 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_act_raw_normDist_T_220 = activated_wdata_e_act_raw_fractIn_5[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_221 = activated_wdata_e_act_raw_fractIn_5[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_222 = activated_wdata_e_act_raw_fractIn_5[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_223 = activated_wdata_e_act_raw_fractIn_5[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_224 = activated_wdata_e_act_raw_fractIn_5[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_225 = activated_wdata_e_act_raw_fractIn_5[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_226 = activated_wdata_e_act_raw_fractIn_5[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_227 = activated_wdata_e_act_raw_fractIn_5[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_228 = activated_wdata_e_act_raw_fractIn_5[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_229 = activated_wdata_e_act_raw_fractIn_5[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_230 = activated_wdata_e_act_raw_fractIn_5[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_231 = activated_wdata_e_act_raw_fractIn_5[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_232 = activated_wdata_e_act_raw_fractIn_5[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_233 = activated_wdata_e_act_raw_fractIn_5[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_234 = activated_wdata_e_act_raw_fractIn_5[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_235 = activated_wdata_e_act_raw_fractIn_5[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_236 = activated_wdata_e_act_raw_fractIn_5[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_237 = activated_wdata_e_act_raw_fractIn_5[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_238 = activated_wdata_e_act_raw_fractIn_5[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_239 = activated_wdata_e_act_raw_fractIn_5[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_240 = activated_wdata_e_act_raw_fractIn_5[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_241 = activated_wdata_e_act_raw_fractIn_5[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_242 = activated_wdata_e_act_raw_fractIn_5[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_243 = _activated_wdata_e_act_raw_normDist_T_221 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_244 = _activated_wdata_e_act_raw_normDist_T_222 ? 5'h14 : _activated_wdata_e_act_raw_normDist_T_243; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_245 = _activated_wdata_e_act_raw_normDist_T_223 ? 5'h13 : _activated_wdata_e_act_raw_normDist_T_244; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_246 = _activated_wdata_e_act_raw_normDist_T_224 ? 5'h12 : _activated_wdata_e_act_raw_normDist_T_245; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_247 = _activated_wdata_e_act_raw_normDist_T_225 ? 5'h11 : _activated_wdata_e_act_raw_normDist_T_246; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_248 = _activated_wdata_e_act_raw_normDist_T_226 ? 5'h10 : _activated_wdata_e_act_raw_normDist_T_247; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_249 = _activated_wdata_e_act_raw_normDist_T_227 ? 5'hF : _activated_wdata_e_act_raw_normDist_T_248; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_250 = _activated_wdata_e_act_raw_normDist_T_228 ? 5'hE : _activated_wdata_e_act_raw_normDist_T_249; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_251 = _activated_wdata_e_act_raw_normDist_T_229 ? 5'hD : _activated_wdata_e_act_raw_normDist_T_250; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_252 = _activated_wdata_e_act_raw_normDist_T_230 ? 5'hC : _activated_wdata_e_act_raw_normDist_T_251; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_253 = _activated_wdata_e_act_raw_normDist_T_231 ? 5'hB : _activated_wdata_e_act_raw_normDist_T_252; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_254 = _activated_wdata_e_act_raw_normDist_T_232 ? 5'hA : _activated_wdata_e_act_raw_normDist_T_253; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_255 = _activated_wdata_e_act_raw_normDist_T_233 ? 5'h9 : _activated_wdata_e_act_raw_normDist_T_254; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_256 = _activated_wdata_e_act_raw_normDist_T_234 ? 5'h8 : _activated_wdata_e_act_raw_normDist_T_255; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_257 = _activated_wdata_e_act_raw_normDist_T_235 ? 5'h7 : _activated_wdata_e_act_raw_normDist_T_256; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_258 = _activated_wdata_e_act_raw_normDist_T_236 ? 5'h6 : _activated_wdata_e_act_raw_normDist_T_257; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_259 = _activated_wdata_e_act_raw_normDist_T_237 ? 5'h5 : _activated_wdata_e_act_raw_normDist_T_258; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_260 = _activated_wdata_e_act_raw_normDist_T_238 ? 5'h4 : _activated_wdata_e_act_raw_normDist_T_259; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_261 = _activated_wdata_e_act_raw_normDist_T_239 ? 5'h3 : _activated_wdata_e_act_raw_normDist_T_260; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_262 = _activated_wdata_e_act_raw_normDist_T_240 ? 5'h2 : _activated_wdata_e_act_raw_normDist_T_261; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_263 = _activated_wdata_e_act_raw_normDist_T_241 ? 5'h1 : _activated_wdata_e_act_raw_normDist_T_262; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_act_raw_normDist_5 = _activated_wdata_e_act_raw_normDist_T_242 ? 5'h0 : _activated_wdata_e_act_raw_normDist_T_263; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_act_raw_subnormFract_T_10 = {31'h0, activated_wdata_e_act_raw_fractIn_5} << activated_wdata_e_act_raw_normDist_5; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_act_raw_subnormFract_T_11 = _activated_wdata_e_act_raw_subnormFract_T_10[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_act_raw_subnormFract_5 = {_activated_wdata_e_act_raw_subnormFract_T_11, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_25 = {4'hF, ~activated_wdata_e_act_raw_normDist_5}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_26 = activated_wdata_e_act_raw_isZeroExpIn_5 ? _activated_wdata_e_act_raw_adjustedExp_T_25 : {1'h0, activated_wdata_e_act_raw_expIn_5}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_act_raw_adjustedExp_T_27 = activated_wdata_e_act_raw_isZeroExpIn_5 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_act_raw_adjustedExp_T_28 = {6'h20, _activated_wdata_e_act_raw_adjustedExp_T_27}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_act_raw_adjustedExp_T_29 = {1'h0, _activated_wdata_e_act_raw_adjustedExp_T_26} + {2'h0, _activated_wdata_e_act_raw_adjustedExp_T_28}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_act_raw_adjustedExp_5 = _activated_wdata_e_act_raw_adjustedExp_T_29[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_act_raw_out_sExp_T_10 = activated_wdata_e_act_raw_adjustedExp_5; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_act_raw_isZero_5 = activated_wdata_e_act_raw_isZeroExpIn_5 & activated_wdata_e_act_raw_isZeroFractIn_5; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_act_raw_5_isZero = activated_wdata_e_act_raw_isZero_5; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_act_raw_isSpecial_T_5 = activated_wdata_e_act_raw_adjustedExp_5[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_act_raw_isSpecial_5 = &_activated_wdata_e_act_raw_isSpecial_T_5; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_act_raw_out_isNaN_T_11; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_act_raw_out_isInf_T_5; // @[rawFloatFromFN.scala:65:28]
wire [9:0] _activated_wdata_e_act_raw_out_sExp_T_11; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_act_raw_out_sig_T_23; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_act_raw_5_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_act_raw_5_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_act_raw_5_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_act_raw_5_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_raw_out_isNaN_T_10 = ~activated_wdata_e_act_raw_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_act_raw_out_isNaN_T_11 = activated_wdata_e_act_raw_isSpecial_5 & _activated_wdata_e_act_raw_out_isNaN_T_10; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_act_raw_5_isNaN = _activated_wdata_e_act_raw_out_isNaN_T_11; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_act_raw_out_isInf_T_5 = activated_wdata_e_act_raw_isSpecial_5 & activated_wdata_e_act_raw_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_act_raw_5_isInf = _activated_wdata_e_act_raw_out_isInf_T_5; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_act_raw_out_sExp_T_11 = {1'h0, _activated_wdata_e_act_raw_out_sExp_T_10}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_act_raw_5_sExp = _activated_wdata_e_act_raw_out_sExp_T_11; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_act_raw_out_sig_T_20 = ~activated_wdata_e_act_raw_isZero_5; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_act_raw_out_sig_T_21 = {1'h0, _activated_wdata_e_act_raw_out_sig_T_20}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_act_raw_out_sig_T_22 = activated_wdata_e_act_raw_isZeroExpIn_5 ? activated_wdata_e_act_raw_subnormFract_5 : activated_wdata_e_act_raw_fractIn_5; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_act_raw_out_sig_T_23 = {_activated_wdata_e_act_raw_out_sig_T_21, _activated_wdata_e_act_raw_out_sig_T_22}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_act_raw_5_sig = _activated_wdata_e_act_raw_out_sig_T_23; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [31:0] _activated_wdata_e_act_result_bits_T_17; // @[Arithmetic.scala:514:27]
wire [31:0] activated_wdata_e_act_result_5_bits; // @[Arithmetic.scala:513:26]
wire _activated_wdata_e_act_result_bits_T_15 = ~activated_wdata_e_act_raw_5_isZero; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_result_bits_T_16 = _activated_wdata_e_act_result_bits_T_15 & activated_wdata_e_act_raw_5_sign; // @[rawFloatFromFN.scala:63:19]
assign _activated_wdata_e_act_result_bits_T_17 = _activated_wdata_e_act_result_bits_T_16 ? 32'h0 : activated_wdata_e_clipped_5_bits; // @[Arithmetic.scala:505:26, :514:{27,40}]
assign activated_wdata_e_act_result_5_bits = _activated_wdata_e_act_result_bits_T_17; // @[Arithmetic.scala:513:26, :514:27]
wire [31:0] activated_wdata_e_act_5_bits = _activated_wdata_e_act_T_5 ? activated_wdata_e_act_result_5_bits : activated_wdata_e_clipped_5_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_wdata_WIRE_5_0_bits = activated_wdata_e_act_5_bits; // @[Mux.scala:126:16]
wire [31:0] activated_wdata_1_1_0_bits = _activated_wdata_WIRE_5_0_bits; // @[ExecuteController.scala:925:{34,74}]
wire activated_wdata_e_clipped_self_rec_rawIn_6_sign = activated_wdata_e_clipped_self_rec_rawIn_sign_6; // @[rawFloatFromFN.scala:44:18, :63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_6 = activated_wdata_e_clipped_self_rec_rawIn_expIn_6 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_6 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_264 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_265 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_266 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_267 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_268 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_269 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_270 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_271 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_272 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_273 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_274 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_275 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_276 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_277 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_278 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_279 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_280 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_281 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_282 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_283 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_284 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_285 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_286 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_6[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_287 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_265 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_288 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_266 ? 5'h14 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_287; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_289 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_267 ? 5'h13 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_288; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_290 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_268 ? 5'h12 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_289; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_291 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_269 ? 5'h11 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_290; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_292 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_270 ? 5'h10 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_291; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_293 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_271 ? 5'hF : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_292; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_294 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_272 ? 5'hE : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_293; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_295 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_273 ? 5'hD : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_294; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_296 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_274 ? 5'hC : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_295; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_297 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_275 ? 5'hB : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_296; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_298 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_276 ? 5'hA : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_297; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_299 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_277 ? 5'h9 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_298; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_300 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_278 ? 5'h8 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_299; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_301 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_279 ? 5'h7 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_300; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_302 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_280 ? 5'h6 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_301; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_303 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_281 ? 5'h5 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_302; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_304 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_282 ? 5'h4 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_303; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_305 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_283 ? 5'h3 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_304; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_306 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_284 ? 5'h2 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_305; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_307 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_285 ? 5'h1 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_306; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_clipped_self_rec_rawIn_normDist_6 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_286 ? 5'h0 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_307; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_12 = {31'h0, activated_wdata_e_clipped_self_rec_rawIn_fractIn_6} << activated_wdata_e_clipped_self_rec_rawIn_normDist_6; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_13 = _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_12[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_subnormFract_6 = {_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_13, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_30 = {4'hF, ~activated_wdata_e_clipped_self_rec_rawIn_normDist_6}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_31 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_6 ? _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_30 : {1'h0, activated_wdata_e_clipped_self_rec_rawIn_expIn_6}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_32 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_6 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_33 = {6'h20, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_32}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_34 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_31} + {2'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_33}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_6 = _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_34[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_12 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_6; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_clipped_self_rec_rawIn_isZero_6 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_6 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_clipped_self_rec_rawIn_6_isZero = activated_wdata_e_clipped_self_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_6 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_6[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_clipped_self_rec_rawIn_isSpecial_6 = &_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_6; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:65:28]
wire _activated_wdata_e_clipped_self_rec_T_50 = activated_wdata_e_clipped_self_rec_rawIn_6_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_clipped_self_rec_rawIn_6_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_clipped_self_rec_rawIn_6_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_clipped_self_rec_rawIn_6_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_12 = ~activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_13 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_6 & _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_12; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_clipped_self_rec_rawIn_6_isNaN = _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_6 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_6 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_clipped_self_rec_rawIn_6_isInf = _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_13 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_12}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_clipped_self_rec_rawIn_6_sExp = _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_24 = ~activated_wdata_e_clipped_self_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_25 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_24}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_26 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_6 ? activated_wdata_e_clipped_self_rec_rawIn_subnormFract_6 : activated_wdata_e_clipped_self_rec_rawIn_fractIn_6; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_27 = {_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_25, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_26}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_clipped_self_rec_rawIn_6_sig = _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_48 = activated_wdata_e_clipped_self_rec_rawIn_6_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_49 = activated_wdata_e_clipped_self_rec_rawIn_6_isZero ? 3'h0 : _activated_wdata_e_clipped_self_rec_T_48; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_51 = {_activated_wdata_e_clipped_self_rec_T_49[2:1], _activated_wdata_e_clipped_self_rec_T_49[0] | _activated_wdata_e_clipped_self_rec_T_50}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_wdata_e_clipped_self_rec_T_52 = {activated_wdata_e_clipped_self_rec_rawIn_6_sign, _activated_wdata_e_clipped_self_rec_T_51}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_wdata_e_clipped_self_rec_T_53 = activated_wdata_e_clipped_self_rec_rawIn_6_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_wdata_e_clipped_self_rec_T_54 = {_activated_wdata_e_clipped_self_rec_T_52, _activated_wdata_e_clipped_self_rec_T_53}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_wdata_e_clipped_self_rec_T_55 = activated_wdata_e_clipped_self_rec_rawIn_6_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_wdata_e_clipped_self_rec_6 = {_activated_wdata_e_clipped_self_rec_T_54, _activated_wdata_e_clipped_self_rec_T_55}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_wdata_e_clipped_result_bits_T_6; // @[fNFromRecFN.scala:66:12]
wire [31:0] activated_wdata_e_clipped_6_bits; // @[Arithmetic.scala:505:26]
wire [8:0] activated_wdata_e_clipped_result_bits_rawIn_exp_6 = _activated_wdata_e_clipped_resizer_6_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_6 = activated_wdata_e_clipped_result_bits_rawIn_exp_6[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isZero_6 = _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_6 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_wdata_e_clipped_result_bits_rawIn_6_isZero = activated_wdata_e_clipped_result_bits_rawIn_isZero_6; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_6 = activated_wdata_e_clipped_result_bits_rawIn_exp_6[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isSpecial_6 = &_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_6; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_13; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_20; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_6; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_6; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_27; // @[rawFloatFromRecFN.scala:61:44]
wire activated_wdata_e_clipped_result_bits_rawIn_6_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_6_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_6_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_wdata_e_clipped_result_bits_rawIn_6_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_wdata_e_clipped_result_bits_rawIn_6_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_12 = activated_wdata_e_clipped_result_bits_rawIn_exp_6[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_18 = activated_wdata_e_clipped_result_bits_rawIn_exp_6[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_13 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_6 & _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_12; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_wdata_e_clipped_result_bits_rawIn_6_isNaN = _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_13; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_19 = ~_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_18; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_20 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_6 & _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_19; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_wdata_e_clipped_result_bits_rawIn_6_isInf = _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_20; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_6 = _activated_wdata_e_clipped_resizer_6_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_wdata_e_clipped_result_bits_rawIn_6_sign = _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_6; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_6 = {1'h0, activated_wdata_e_clipped_result_bits_rawIn_exp_6}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_wdata_e_clipped_result_bits_rawIn_6_sExp = _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_6; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_24 = ~activated_wdata_e_clipped_result_bits_rawIn_isZero_6; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_25 = {1'h0, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_24}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_26 = _activated_wdata_e_clipped_resizer_6_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_27 = {_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_25, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_26}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_wdata_e_clipped_result_bits_rawIn_6_sig = _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_27; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire activated_wdata_e_clipped_result_bits_isSubnormal_6 = $signed(activated_wdata_e_clipped_result_bits_rawIn_6_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_12 = activated_wdata_e_clipped_result_bits_rawIn_6_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_13 = 6'h1 - {1'h0, _activated_wdata_e_clipped_result_bits_denormShiftDist_T_12}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] activated_wdata_e_clipped_result_bits_denormShiftDist_6 = _activated_wdata_e_clipped_result_bits_denormShiftDist_T_13[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_12 = activated_wdata_e_clipped_result_bits_rawIn_6_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_13 = _activated_wdata_e_clipped_result_bits_denormFract_T_12 >> activated_wdata_e_clipped_result_bits_denormShiftDist_6; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] activated_wdata_e_clipped_result_bits_denormFract_6 = _activated_wdata_e_clipped_result_bits_denormFract_T_13[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_36 = activated_wdata_e_clipped_result_bits_rawIn_6_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _activated_wdata_e_clipped_result_bits_expOut_T_37 = {1'h0, _activated_wdata_e_clipped_result_bits_expOut_T_36} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_38 = _activated_wdata_e_clipped_result_bits_expOut_T_37[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_39 = activated_wdata_e_clipped_result_bits_isSubnormal_6 ? 8'h0 : _activated_wdata_e_clipped_result_bits_expOut_T_38; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _activated_wdata_e_clipped_result_bits_expOut_T_40 = activated_wdata_e_clipped_result_bits_rawIn_6_isNaN | activated_wdata_e_clipped_result_bits_rawIn_6_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_41 = {8{_activated_wdata_e_clipped_result_bits_expOut_T_40}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] activated_wdata_e_clipped_result_bits_expOut_6 = _activated_wdata_e_clipped_result_bits_expOut_T_39 | _activated_wdata_e_clipped_result_bits_expOut_T_41; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_12 = activated_wdata_e_clipped_result_bits_rawIn_6_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_13 = activated_wdata_e_clipped_result_bits_rawIn_6_isInf ? 23'h0 : _activated_wdata_e_clipped_result_bits_fractOut_T_12; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] activated_wdata_e_clipped_result_bits_fractOut_6 = activated_wdata_e_clipped_result_bits_isSubnormal_6 ? activated_wdata_e_clipped_result_bits_denormFract_6 : _activated_wdata_e_clipped_result_bits_fractOut_T_13; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] activated_wdata_e_clipped_result_bits_hi_6 = {activated_wdata_e_clipped_result_bits_rawIn_6_sign, activated_wdata_e_clipped_result_bits_expOut_6}; // @[rawFloatFromRecFN.scala:55:23]
assign _activated_wdata_e_clipped_result_bits_T_6 = {activated_wdata_e_clipped_result_bits_hi_6, activated_wdata_e_clipped_result_bits_fractOut_6}; // @[fNFromRecFN.scala:62:16, :66:12]
assign activated_wdata_e_clipped_6_bits = _activated_wdata_e_clipped_result_bits_T_6; // @[fNFromRecFN.scala:66:12]
wire activated_wdata_e_act_raw_sign_6 = activated_wdata_e_clipped_6_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_act_raw_6_sign = activated_wdata_e_act_raw_sign_6; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_wdata_e_act_raw_expIn_6 = activated_wdata_e_clipped_6_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_wdata_e_act_raw_fractIn_6 = activated_wdata_e_clipped_6_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_wdata_e_act_raw_isZeroExpIn_6 = activated_wdata_e_act_raw_expIn_6 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_act_raw_isZeroFractIn_6 = activated_wdata_e_act_raw_fractIn_6 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_act_raw_normDist_T_264 = activated_wdata_e_act_raw_fractIn_6[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_265 = activated_wdata_e_act_raw_fractIn_6[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_266 = activated_wdata_e_act_raw_fractIn_6[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_267 = activated_wdata_e_act_raw_fractIn_6[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_268 = activated_wdata_e_act_raw_fractIn_6[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_269 = activated_wdata_e_act_raw_fractIn_6[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_270 = activated_wdata_e_act_raw_fractIn_6[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_271 = activated_wdata_e_act_raw_fractIn_6[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_272 = activated_wdata_e_act_raw_fractIn_6[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_273 = activated_wdata_e_act_raw_fractIn_6[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_274 = activated_wdata_e_act_raw_fractIn_6[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_275 = activated_wdata_e_act_raw_fractIn_6[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_276 = activated_wdata_e_act_raw_fractIn_6[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_277 = activated_wdata_e_act_raw_fractIn_6[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_278 = activated_wdata_e_act_raw_fractIn_6[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_279 = activated_wdata_e_act_raw_fractIn_6[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_280 = activated_wdata_e_act_raw_fractIn_6[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_281 = activated_wdata_e_act_raw_fractIn_6[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_282 = activated_wdata_e_act_raw_fractIn_6[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_283 = activated_wdata_e_act_raw_fractIn_6[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_284 = activated_wdata_e_act_raw_fractIn_6[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_285 = activated_wdata_e_act_raw_fractIn_6[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_286 = activated_wdata_e_act_raw_fractIn_6[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_287 = _activated_wdata_e_act_raw_normDist_T_265 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_288 = _activated_wdata_e_act_raw_normDist_T_266 ? 5'h14 : _activated_wdata_e_act_raw_normDist_T_287; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_289 = _activated_wdata_e_act_raw_normDist_T_267 ? 5'h13 : _activated_wdata_e_act_raw_normDist_T_288; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_290 = _activated_wdata_e_act_raw_normDist_T_268 ? 5'h12 : _activated_wdata_e_act_raw_normDist_T_289; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_291 = _activated_wdata_e_act_raw_normDist_T_269 ? 5'h11 : _activated_wdata_e_act_raw_normDist_T_290; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_292 = _activated_wdata_e_act_raw_normDist_T_270 ? 5'h10 : _activated_wdata_e_act_raw_normDist_T_291; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_293 = _activated_wdata_e_act_raw_normDist_T_271 ? 5'hF : _activated_wdata_e_act_raw_normDist_T_292; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_294 = _activated_wdata_e_act_raw_normDist_T_272 ? 5'hE : _activated_wdata_e_act_raw_normDist_T_293; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_295 = _activated_wdata_e_act_raw_normDist_T_273 ? 5'hD : _activated_wdata_e_act_raw_normDist_T_294; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_296 = _activated_wdata_e_act_raw_normDist_T_274 ? 5'hC : _activated_wdata_e_act_raw_normDist_T_295; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_297 = _activated_wdata_e_act_raw_normDist_T_275 ? 5'hB : _activated_wdata_e_act_raw_normDist_T_296; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_298 = _activated_wdata_e_act_raw_normDist_T_276 ? 5'hA : _activated_wdata_e_act_raw_normDist_T_297; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_299 = _activated_wdata_e_act_raw_normDist_T_277 ? 5'h9 : _activated_wdata_e_act_raw_normDist_T_298; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_300 = _activated_wdata_e_act_raw_normDist_T_278 ? 5'h8 : _activated_wdata_e_act_raw_normDist_T_299; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_301 = _activated_wdata_e_act_raw_normDist_T_279 ? 5'h7 : _activated_wdata_e_act_raw_normDist_T_300; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_302 = _activated_wdata_e_act_raw_normDist_T_280 ? 5'h6 : _activated_wdata_e_act_raw_normDist_T_301; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_303 = _activated_wdata_e_act_raw_normDist_T_281 ? 5'h5 : _activated_wdata_e_act_raw_normDist_T_302; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_304 = _activated_wdata_e_act_raw_normDist_T_282 ? 5'h4 : _activated_wdata_e_act_raw_normDist_T_303; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_305 = _activated_wdata_e_act_raw_normDist_T_283 ? 5'h3 : _activated_wdata_e_act_raw_normDist_T_304; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_306 = _activated_wdata_e_act_raw_normDist_T_284 ? 5'h2 : _activated_wdata_e_act_raw_normDist_T_305; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_307 = _activated_wdata_e_act_raw_normDist_T_285 ? 5'h1 : _activated_wdata_e_act_raw_normDist_T_306; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_act_raw_normDist_6 = _activated_wdata_e_act_raw_normDist_T_286 ? 5'h0 : _activated_wdata_e_act_raw_normDist_T_307; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_act_raw_subnormFract_T_12 = {31'h0, activated_wdata_e_act_raw_fractIn_6} << activated_wdata_e_act_raw_normDist_6; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_act_raw_subnormFract_T_13 = _activated_wdata_e_act_raw_subnormFract_T_12[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_act_raw_subnormFract_6 = {_activated_wdata_e_act_raw_subnormFract_T_13, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_30 = {4'hF, ~activated_wdata_e_act_raw_normDist_6}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_31 = activated_wdata_e_act_raw_isZeroExpIn_6 ? _activated_wdata_e_act_raw_adjustedExp_T_30 : {1'h0, activated_wdata_e_act_raw_expIn_6}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_act_raw_adjustedExp_T_32 = activated_wdata_e_act_raw_isZeroExpIn_6 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_act_raw_adjustedExp_T_33 = {6'h20, _activated_wdata_e_act_raw_adjustedExp_T_32}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_act_raw_adjustedExp_T_34 = {1'h0, _activated_wdata_e_act_raw_adjustedExp_T_31} + {2'h0, _activated_wdata_e_act_raw_adjustedExp_T_33}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_act_raw_adjustedExp_6 = _activated_wdata_e_act_raw_adjustedExp_T_34[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_act_raw_out_sExp_T_12 = activated_wdata_e_act_raw_adjustedExp_6; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_act_raw_isZero_6 = activated_wdata_e_act_raw_isZeroExpIn_6 & activated_wdata_e_act_raw_isZeroFractIn_6; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_act_raw_6_isZero = activated_wdata_e_act_raw_isZero_6; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_act_raw_isSpecial_T_6 = activated_wdata_e_act_raw_adjustedExp_6[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_act_raw_isSpecial_6 = &_activated_wdata_e_act_raw_isSpecial_T_6; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_act_raw_out_isNaN_T_13; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_act_raw_out_isInf_T_6; // @[rawFloatFromFN.scala:65:28]
wire [9:0] _activated_wdata_e_act_raw_out_sExp_T_13; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_act_raw_out_sig_T_27; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_act_raw_6_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_act_raw_6_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_act_raw_6_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_act_raw_6_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_raw_out_isNaN_T_12 = ~activated_wdata_e_act_raw_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_act_raw_out_isNaN_T_13 = activated_wdata_e_act_raw_isSpecial_6 & _activated_wdata_e_act_raw_out_isNaN_T_12; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_act_raw_6_isNaN = _activated_wdata_e_act_raw_out_isNaN_T_13; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_act_raw_out_isInf_T_6 = activated_wdata_e_act_raw_isSpecial_6 & activated_wdata_e_act_raw_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_act_raw_6_isInf = _activated_wdata_e_act_raw_out_isInf_T_6; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_act_raw_out_sExp_T_13 = {1'h0, _activated_wdata_e_act_raw_out_sExp_T_12}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_act_raw_6_sExp = _activated_wdata_e_act_raw_out_sExp_T_13; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_act_raw_out_sig_T_24 = ~activated_wdata_e_act_raw_isZero_6; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_act_raw_out_sig_T_25 = {1'h0, _activated_wdata_e_act_raw_out_sig_T_24}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_act_raw_out_sig_T_26 = activated_wdata_e_act_raw_isZeroExpIn_6 ? activated_wdata_e_act_raw_subnormFract_6 : activated_wdata_e_act_raw_fractIn_6; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_act_raw_out_sig_T_27 = {_activated_wdata_e_act_raw_out_sig_T_25, _activated_wdata_e_act_raw_out_sig_T_26}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_act_raw_6_sig = _activated_wdata_e_act_raw_out_sig_T_27; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [31:0] _activated_wdata_e_act_result_bits_T_20; // @[Arithmetic.scala:514:27]
wire [31:0] activated_wdata_e_act_result_6_bits; // @[Arithmetic.scala:513:26]
wire _activated_wdata_e_act_result_bits_T_18 = ~activated_wdata_e_act_raw_6_isZero; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_result_bits_T_19 = _activated_wdata_e_act_result_bits_T_18 & activated_wdata_e_act_raw_6_sign; // @[rawFloatFromFN.scala:63:19]
assign _activated_wdata_e_act_result_bits_T_20 = _activated_wdata_e_act_result_bits_T_19 ? 32'h0 : activated_wdata_e_clipped_6_bits; // @[Arithmetic.scala:505:26, :514:{27,40}]
assign activated_wdata_e_act_result_6_bits = _activated_wdata_e_act_result_bits_T_20; // @[Arithmetic.scala:513:26, :514:27]
wire [31:0] activated_wdata_e_act_6_bits = _activated_wdata_e_act_T_6 ? activated_wdata_e_act_result_6_bits : activated_wdata_e_clipped_6_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_wdata_WIRE_6_0_bits = activated_wdata_e_act_6_bits; // @[Mux.scala:126:16]
wire [31:0] activated_wdata_1_2_0_bits = _activated_wdata_WIRE_6_0_bits; // @[ExecuteController.scala:925:{34,74}]
wire activated_wdata_e_clipped_self_rec_rawIn_7_sign = activated_wdata_e_clipped_self_rec_rawIn_sign_7; // @[rawFloatFromFN.scala:44:18, :63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_7 = activated_wdata_e_clipped_self_rec_rawIn_expIn_7 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_7 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_308 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_309 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_310 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_311 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_312 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_313 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_314 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_315 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_316 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_317 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_318 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_319 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_320 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_321 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_322 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_323 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_324 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_325 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_326 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_327 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_328 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_329 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_330 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_7[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_331 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_309 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_332 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_310 ? 5'h14 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_331; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_333 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_311 ? 5'h13 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_332; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_334 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_312 ? 5'h12 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_333; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_335 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_313 ? 5'h11 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_334; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_336 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_314 ? 5'h10 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_335; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_337 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_315 ? 5'hF : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_336; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_338 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_316 ? 5'hE : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_337; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_339 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_317 ? 5'hD : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_338; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_340 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_318 ? 5'hC : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_339; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_341 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_319 ? 5'hB : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_340; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_342 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_320 ? 5'hA : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_341; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_343 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_321 ? 5'h9 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_342; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_344 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_322 ? 5'h8 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_343; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_345 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_323 ? 5'h7 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_344; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_346 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_324 ? 5'h6 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_345; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_347 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_325 ? 5'h5 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_346; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_348 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_326 ? 5'h4 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_347; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_349 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_327 ? 5'h3 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_348; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_350 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_328 ? 5'h2 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_349; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_351 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_329 ? 5'h1 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_350; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_clipped_self_rec_rawIn_normDist_7 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_330 ? 5'h0 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_351; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_14 = {31'h0, activated_wdata_e_clipped_self_rec_rawIn_fractIn_7} << activated_wdata_e_clipped_self_rec_rawIn_normDist_7; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_15 = _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_14[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_subnormFract_7 = {_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_15, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_35 = {4'hF, ~activated_wdata_e_clipped_self_rec_rawIn_normDist_7}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_36 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_7 ? _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_35 : {1'h0, activated_wdata_e_clipped_self_rec_rawIn_expIn_7}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_37 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_7 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_38 = {6'h20, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_37}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_39 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_36} + {2'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_38}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_7 = _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_39[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_14 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_7; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_clipped_self_rec_rawIn_isZero_7 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_7 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_clipped_self_rec_rawIn_7_isZero = activated_wdata_e_clipped_self_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_7 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_7[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_clipped_self_rec_rawIn_isSpecial_7 = &_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_7; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:65:28]
wire _activated_wdata_e_clipped_self_rec_T_58 = activated_wdata_e_clipped_self_rec_rawIn_7_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_clipped_self_rec_rawIn_7_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_clipped_self_rec_rawIn_7_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_clipped_self_rec_rawIn_7_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_14 = ~activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_15 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_7 & _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_14; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_clipped_self_rec_rawIn_7_isNaN = _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_7 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_7 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_clipped_self_rec_rawIn_7_isInf = _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_15 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_14}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_clipped_self_rec_rawIn_7_sExp = _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_28 = ~activated_wdata_e_clipped_self_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_29 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_28}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_30 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_7 ? activated_wdata_e_clipped_self_rec_rawIn_subnormFract_7 : activated_wdata_e_clipped_self_rec_rawIn_fractIn_7; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_31 = {_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_29, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_30}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_clipped_self_rec_rawIn_7_sig = _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_56 = activated_wdata_e_clipped_self_rec_rawIn_7_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_57 = activated_wdata_e_clipped_self_rec_rawIn_7_isZero ? 3'h0 : _activated_wdata_e_clipped_self_rec_T_56; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_59 = {_activated_wdata_e_clipped_self_rec_T_57[2:1], _activated_wdata_e_clipped_self_rec_T_57[0] | _activated_wdata_e_clipped_self_rec_T_58}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_wdata_e_clipped_self_rec_T_60 = {activated_wdata_e_clipped_self_rec_rawIn_7_sign, _activated_wdata_e_clipped_self_rec_T_59}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_wdata_e_clipped_self_rec_T_61 = activated_wdata_e_clipped_self_rec_rawIn_7_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_wdata_e_clipped_self_rec_T_62 = {_activated_wdata_e_clipped_self_rec_T_60, _activated_wdata_e_clipped_self_rec_T_61}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_wdata_e_clipped_self_rec_T_63 = activated_wdata_e_clipped_self_rec_rawIn_7_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_wdata_e_clipped_self_rec_7 = {_activated_wdata_e_clipped_self_rec_T_62, _activated_wdata_e_clipped_self_rec_T_63}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_wdata_e_clipped_result_bits_T_7; // @[fNFromRecFN.scala:66:12]
wire [31:0] activated_wdata_e_clipped_7_bits; // @[Arithmetic.scala:505:26]
wire [8:0] activated_wdata_e_clipped_result_bits_rawIn_exp_7 = _activated_wdata_e_clipped_resizer_7_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_7 = activated_wdata_e_clipped_result_bits_rawIn_exp_7[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isZero_7 = _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_7 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_wdata_e_clipped_result_bits_rawIn_7_isZero = activated_wdata_e_clipped_result_bits_rawIn_isZero_7; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_7 = activated_wdata_e_clipped_result_bits_rawIn_exp_7[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isSpecial_7 = &_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_7; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_15; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_23; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_7; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_7; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_31; // @[rawFloatFromRecFN.scala:61:44]
wire activated_wdata_e_clipped_result_bits_rawIn_7_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_7_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_7_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_wdata_e_clipped_result_bits_rawIn_7_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_wdata_e_clipped_result_bits_rawIn_7_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_14 = activated_wdata_e_clipped_result_bits_rawIn_exp_7[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_21 = activated_wdata_e_clipped_result_bits_rawIn_exp_7[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_15 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_7 & _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_14; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_wdata_e_clipped_result_bits_rawIn_7_isNaN = _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_15; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_22 = ~_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_21; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_23 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_7 & _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_22; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_wdata_e_clipped_result_bits_rawIn_7_isInf = _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_23; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_7 = _activated_wdata_e_clipped_resizer_7_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_wdata_e_clipped_result_bits_rawIn_7_sign = _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_7; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_7 = {1'h0, activated_wdata_e_clipped_result_bits_rawIn_exp_7}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_wdata_e_clipped_result_bits_rawIn_7_sExp = _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_7; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_28 = ~activated_wdata_e_clipped_result_bits_rawIn_isZero_7; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_29 = {1'h0, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_28}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_30 = _activated_wdata_e_clipped_resizer_7_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_31 = {_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_29, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_30}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_wdata_e_clipped_result_bits_rawIn_7_sig = _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_31; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire activated_wdata_e_clipped_result_bits_isSubnormal_7 = $signed(activated_wdata_e_clipped_result_bits_rawIn_7_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_14 = activated_wdata_e_clipped_result_bits_rawIn_7_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_15 = 6'h1 - {1'h0, _activated_wdata_e_clipped_result_bits_denormShiftDist_T_14}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] activated_wdata_e_clipped_result_bits_denormShiftDist_7 = _activated_wdata_e_clipped_result_bits_denormShiftDist_T_15[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_14 = activated_wdata_e_clipped_result_bits_rawIn_7_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_15 = _activated_wdata_e_clipped_result_bits_denormFract_T_14 >> activated_wdata_e_clipped_result_bits_denormShiftDist_7; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] activated_wdata_e_clipped_result_bits_denormFract_7 = _activated_wdata_e_clipped_result_bits_denormFract_T_15[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_42 = activated_wdata_e_clipped_result_bits_rawIn_7_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _activated_wdata_e_clipped_result_bits_expOut_T_43 = {1'h0, _activated_wdata_e_clipped_result_bits_expOut_T_42} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_44 = _activated_wdata_e_clipped_result_bits_expOut_T_43[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_45 = activated_wdata_e_clipped_result_bits_isSubnormal_7 ? 8'h0 : _activated_wdata_e_clipped_result_bits_expOut_T_44; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _activated_wdata_e_clipped_result_bits_expOut_T_46 = activated_wdata_e_clipped_result_bits_rawIn_7_isNaN | activated_wdata_e_clipped_result_bits_rawIn_7_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_47 = {8{_activated_wdata_e_clipped_result_bits_expOut_T_46}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] activated_wdata_e_clipped_result_bits_expOut_7 = _activated_wdata_e_clipped_result_bits_expOut_T_45 | _activated_wdata_e_clipped_result_bits_expOut_T_47; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_14 = activated_wdata_e_clipped_result_bits_rawIn_7_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_15 = activated_wdata_e_clipped_result_bits_rawIn_7_isInf ? 23'h0 : _activated_wdata_e_clipped_result_bits_fractOut_T_14; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] activated_wdata_e_clipped_result_bits_fractOut_7 = activated_wdata_e_clipped_result_bits_isSubnormal_7 ? activated_wdata_e_clipped_result_bits_denormFract_7 : _activated_wdata_e_clipped_result_bits_fractOut_T_15; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] activated_wdata_e_clipped_result_bits_hi_7 = {activated_wdata_e_clipped_result_bits_rawIn_7_sign, activated_wdata_e_clipped_result_bits_expOut_7}; // @[rawFloatFromRecFN.scala:55:23]
assign _activated_wdata_e_clipped_result_bits_T_7 = {activated_wdata_e_clipped_result_bits_hi_7, activated_wdata_e_clipped_result_bits_fractOut_7}; // @[fNFromRecFN.scala:62:16, :66:12]
assign activated_wdata_e_clipped_7_bits = _activated_wdata_e_clipped_result_bits_T_7; // @[fNFromRecFN.scala:66:12]
wire activated_wdata_e_act_raw_sign_7 = activated_wdata_e_clipped_7_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_act_raw_7_sign = activated_wdata_e_act_raw_sign_7; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_wdata_e_act_raw_expIn_7 = activated_wdata_e_clipped_7_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_wdata_e_act_raw_fractIn_7 = activated_wdata_e_clipped_7_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_wdata_e_act_raw_isZeroExpIn_7 = activated_wdata_e_act_raw_expIn_7 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_act_raw_isZeroFractIn_7 = activated_wdata_e_act_raw_fractIn_7 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_act_raw_normDist_T_308 = activated_wdata_e_act_raw_fractIn_7[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_309 = activated_wdata_e_act_raw_fractIn_7[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_310 = activated_wdata_e_act_raw_fractIn_7[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_311 = activated_wdata_e_act_raw_fractIn_7[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_312 = activated_wdata_e_act_raw_fractIn_7[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_313 = activated_wdata_e_act_raw_fractIn_7[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_314 = activated_wdata_e_act_raw_fractIn_7[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_315 = activated_wdata_e_act_raw_fractIn_7[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_316 = activated_wdata_e_act_raw_fractIn_7[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_317 = activated_wdata_e_act_raw_fractIn_7[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_318 = activated_wdata_e_act_raw_fractIn_7[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_319 = activated_wdata_e_act_raw_fractIn_7[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_320 = activated_wdata_e_act_raw_fractIn_7[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_321 = activated_wdata_e_act_raw_fractIn_7[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_322 = activated_wdata_e_act_raw_fractIn_7[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_323 = activated_wdata_e_act_raw_fractIn_7[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_324 = activated_wdata_e_act_raw_fractIn_7[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_325 = activated_wdata_e_act_raw_fractIn_7[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_326 = activated_wdata_e_act_raw_fractIn_7[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_327 = activated_wdata_e_act_raw_fractIn_7[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_328 = activated_wdata_e_act_raw_fractIn_7[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_329 = activated_wdata_e_act_raw_fractIn_7[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_330 = activated_wdata_e_act_raw_fractIn_7[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_331 = _activated_wdata_e_act_raw_normDist_T_309 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_332 = _activated_wdata_e_act_raw_normDist_T_310 ? 5'h14 : _activated_wdata_e_act_raw_normDist_T_331; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_333 = _activated_wdata_e_act_raw_normDist_T_311 ? 5'h13 : _activated_wdata_e_act_raw_normDist_T_332; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_334 = _activated_wdata_e_act_raw_normDist_T_312 ? 5'h12 : _activated_wdata_e_act_raw_normDist_T_333; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_335 = _activated_wdata_e_act_raw_normDist_T_313 ? 5'h11 : _activated_wdata_e_act_raw_normDist_T_334; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_336 = _activated_wdata_e_act_raw_normDist_T_314 ? 5'h10 : _activated_wdata_e_act_raw_normDist_T_335; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_337 = _activated_wdata_e_act_raw_normDist_T_315 ? 5'hF : _activated_wdata_e_act_raw_normDist_T_336; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_338 = _activated_wdata_e_act_raw_normDist_T_316 ? 5'hE : _activated_wdata_e_act_raw_normDist_T_337; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_339 = _activated_wdata_e_act_raw_normDist_T_317 ? 5'hD : _activated_wdata_e_act_raw_normDist_T_338; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_340 = _activated_wdata_e_act_raw_normDist_T_318 ? 5'hC : _activated_wdata_e_act_raw_normDist_T_339; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_341 = _activated_wdata_e_act_raw_normDist_T_319 ? 5'hB : _activated_wdata_e_act_raw_normDist_T_340; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_342 = _activated_wdata_e_act_raw_normDist_T_320 ? 5'hA : _activated_wdata_e_act_raw_normDist_T_341; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_343 = _activated_wdata_e_act_raw_normDist_T_321 ? 5'h9 : _activated_wdata_e_act_raw_normDist_T_342; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_344 = _activated_wdata_e_act_raw_normDist_T_322 ? 5'h8 : _activated_wdata_e_act_raw_normDist_T_343; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_345 = _activated_wdata_e_act_raw_normDist_T_323 ? 5'h7 : _activated_wdata_e_act_raw_normDist_T_344; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_346 = _activated_wdata_e_act_raw_normDist_T_324 ? 5'h6 : _activated_wdata_e_act_raw_normDist_T_345; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_347 = _activated_wdata_e_act_raw_normDist_T_325 ? 5'h5 : _activated_wdata_e_act_raw_normDist_T_346; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_348 = _activated_wdata_e_act_raw_normDist_T_326 ? 5'h4 : _activated_wdata_e_act_raw_normDist_T_347; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_349 = _activated_wdata_e_act_raw_normDist_T_327 ? 5'h3 : _activated_wdata_e_act_raw_normDist_T_348; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_350 = _activated_wdata_e_act_raw_normDist_T_328 ? 5'h2 : _activated_wdata_e_act_raw_normDist_T_349; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_351 = _activated_wdata_e_act_raw_normDist_T_329 ? 5'h1 : _activated_wdata_e_act_raw_normDist_T_350; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_act_raw_normDist_7 = _activated_wdata_e_act_raw_normDist_T_330 ? 5'h0 : _activated_wdata_e_act_raw_normDist_T_351; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_act_raw_subnormFract_T_14 = {31'h0, activated_wdata_e_act_raw_fractIn_7} << activated_wdata_e_act_raw_normDist_7; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_act_raw_subnormFract_T_15 = _activated_wdata_e_act_raw_subnormFract_T_14[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_act_raw_subnormFract_7 = {_activated_wdata_e_act_raw_subnormFract_T_15, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_35 = {4'hF, ~activated_wdata_e_act_raw_normDist_7}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_36 = activated_wdata_e_act_raw_isZeroExpIn_7 ? _activated_wdata_e_act_raw_adjustedExp_T_35 : {1'h0, activated_wdata_e_act_raw_expIn_7}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_act_raw_adjustedExp_T_37 = activated_wdata_e_act_raw_isZeroExpIn_7 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_act_raw_adjustedExp_T_38 = {6'h20, _activated_wdata_e_act_raw_adjustedExp_T_37}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_act_raw_adjustedExp_T_39 = {1'h0, _activated_wdata_e_act_raw_adjustedExp_T_36} + {2'h0, _activated_wdata_e_act_raw_adjustedExp_T_38}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_act_raw_adjustedExp_7 = _activated_wdata_e_act_raw_adjustedExp_T_39[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_act_raw_out_sExp_T_14 = activated_wdata_e_act_raw_adjustedExp_7; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_act_raw_isZero_7 = activated_wdata_e_act_raw_isZeroExpIn_7 & activated_wdata_e_act_raw_isZeroFractIn_7; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_act_raw_7_isZero = activated_wdata_e_act_raw_isZero_7; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_act_raw_isSpecial_T_7 = activated_wdata_e_act_raw_adjustedExp_7[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_act_raw_isSpecial_7 = &_activated_wdata_e_act_raw_isSpecial_T_7; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_act_raw_out_isNaN_T_15; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_act_raw_out_isInf_T_7; // @[rawFloatFromFN.scala:65:28]
wire [9:0] _activated_wdata_e_act_raw_out_sExp_T_15; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_act_raw_out_sig_T_31; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_act_raw_7_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_act_raw_7_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_act_raw_7_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_act_raw_7_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_raw_out_isNaN_T_14 = ~activated_wdata_e_act_raw_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_act_raw_out_isNaN_T_15 = activated_wdata_e_act_raw_isSpecial_7 & _activated_wdata_e_act_raw_out_isNaN_T_14; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_act_raw_7_isNaN = _activated_wdata_e_act_raw_out_isNaN_T_15; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_act_raw_out_isInf_T_7 = activated_wdata_e_act_raw_isSpecial_7 & activated_wdata_e_act_raw_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_act_raw_7_isInf = _activated_wdata_e_act_raw_out_isInf_T_7; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_act_raw_out_sExp_T_15 = {1'h0, _activated_wdata_e_act_raw_out_sExp_T_14}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_act_raw_7_sExp = _activated_wdata_e_act_raw_out_sExp_T_15; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_act_raw_out_sig_T_28 = ~activated_wdata_e_act_raw_isZero_7; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_act_raw_out_sig_T_29 = {1'h0, _activated_wdata_e_act_raw_out_sig_T_28}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_act_raw_out_sig_T_30 = activated_wdata_e_act_raw_isZeroExpIn_7 ? activated_wdata_e_act_raw_subnormFract_7 : activated_wdata_e_act_raw_fractIn_7; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_act_raw_out_sig_T_31 = {_activated_wdata_e_act_raw_out_sig_T_29, _activated_wdata_e_act_raw_out_sig_T_30}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_act_raw_7_sig = _activated_wdata_e_act_raw_out_sig_T_31; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [31:0] _activated_wdata_e_act_result_bits_T_23; // @[Arithmetic.scala:514:27]
wire [31:0] activated_wdata_e_act_result_7_bits; // @[Arithmetic.scala:513:26]
wire _activated_wdata_e_act_result_bits_T_21 = ~activated_wdata_e_act_raw_7_isZero; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_result_bits_T_22 = _activated_wdata_e_act_result_bits_T_21 & activated_wdata_e_act_raw_7_sign; // @[rawFloatFromFN.scala:63:19]
assign _activated_wdata_e_act_result_bits_T_23 = _activated_wdata_e_act_result_bits_T_22 ? 32'h0 : activated_wdata_e_clipped_7_bits; // @[Arithmetic.scala:505:26, :514:{27,40}]
assign activated_wdata_e_act_result_7_bits = _activated_wdata_e_act_result_bits_T_23; // @[Arithmetic.scala:513:26, :514:27]
wire [31:0] activated_wdata_e_act_7_bits = _activated_wdata_e_act_T_7 ? activated_wdata_e_act_result_7_bits : activated_wdata_e_clipped_7_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_wdata_WIRE_7_0_bits = activated_wdata_e_act_7_bits; // @[Mux.scala:126:16]
wire [31:0] activated_wdata_1_3_0_bits = _activated_wdata_WIRE_7_0_bits; // @[ExecuteController.scala:925:{34,74}]
wire _io_srams_write_1_en_T = w_bank == 2'h1; // @[ExecuteController.scala:911:19, :934:64]
wire _io_srams_write_1_en_T_1 = start_array_outputting & _io_srams_write_1_en_T; // @[ExecuteController.scala:270:40, :934:{54,64}]
wire _io_srams_write_1_en_T_2 = ~w_address_is_acc_addr; // @[ExecuteController.scala:907:22, :934:75]
wire _io_srams_write_1_en_T_3 = _io_srams_write_1_en_T_1 & _io_srams_write_1_en_T_2; // @[ExecuteController.scala:934:{54,72,75}]
wire _io_srams_write_1_en_T_4 = ~is_garbage_addr; // @[LocalAddr.scala:43:96]
wire _io_srams_write_1_en_T_5 = _io_srams_write_1_en_T_3 & _io_srams_write_1_en_T_4; // @[ExecuteController.scala:934:{72,89,92}]
assign _io_srams_write_1_en_T_6 = _io_srams_write_1_en_T_5 & write_this_row; // @[ExecuteController.scala:919:27, :934:{89,109}]
assign io_srams_write_1_en_0 = _io_srams_write_1_en_T_6; // @[ExecuteController.scala:12:7, :934:109]
wire [63:0] io_srams_write_1_data_lo = {activated_wdata_1_1_0_bits, activated_wdata_1_0_0_bits}; // @[ExecuteController.scala:925:34, :936:49]
wire [63:0] io_srams_write_1_data_hi = {activated_wdata_1_3_0_bits, activated_wdata_1_2_0_bits}; // @[ExecuteController.scala:925:34, :936:49]
assign _io_srams_write_1_data_T = {io_srams_write_1_data_hi, io_srams_write_1_data_lo}; // @[ExecuteController.scala:936:49]
assign io_srams_write_1_data_0 = _io_srams_write_1_data_T; // @[ExecuteController.scala:12:7, :936:49]
wire activated_wdata_e_clipped_self_rec_rawIn_8_sign = activated_wdata_e_clipped_self_rec_rawIn_sign_8; // @[rawFloatFromFN.scala:44:18, :63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_8 = activated_wdata_e_clipped_self_rec_rawIn_expIn_8 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_8 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_352 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_353 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_354 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_355 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_356 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_357 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_358 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_359 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_360 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_361 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_362 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_363 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_364 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_365 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_366 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_367 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_368 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_369 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_370 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_371 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_372 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_373 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_374 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_8[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_375 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_353 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_376 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_354 ? 5'h14 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_375; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_377 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_355 ? 5'h13 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_376; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_378 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_356 ? 5'h12 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_377; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_379 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_357 ? 5'h11 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_378; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_380 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_358 ? 5'h10 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_379; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_381 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_359 ? 5'hF : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_380; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_382 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_360 ? 5'hE : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_381; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_383 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_361 ? 5'hD : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_382; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_384 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_362 ? 5'hC : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_383; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_385 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_363 ? 5'hB : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_384; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_386 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_364 ? 5'hA : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_385; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_387 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_365 ? 5'h9 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_386; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_388 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_366 ? 5'h8 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_387; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_389 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_367 ? 5'h7 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_388; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_390 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_368 ? 5'h6 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_389; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_391 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_369 ? 5'h5 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_390; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_392 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_370 ? 5'h4 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_391; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_393 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_371 ? 5'h3 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_392; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_394 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_372 ? 5'h2 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_393; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_395 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_373 ? 5'h1 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_394; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_clipped_self_rec_rawIn_normDist_8 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_374 ? 5'h0 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_395; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_16 = {31'h0, activated_wdata_e_clipped_self_rec_rawIn_fractIn_8} << activated_wdata_e_clipped_self_rec_rawIn_normDist_8; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_17 = _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_16[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_subnormFract_8 = {_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_17, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_40 = {4'hF, ~activated_wdata_e_clipped_self_rec_rawIn_normDist_8}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_41 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_8 ? _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_40 : {1'h0, activated_wdata_e_clipped_self_rec_rawIn_expIn_8}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_42 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_8 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_43 = {6'h20, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_42}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_44 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_41} + {2'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_43}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_8 = _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_44[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_16 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_8; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_clipped_self_rec_rawIn_isZero_8 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_8 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_8; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_clipped_self_rec_rawIn_8_isZero = activated_wdata_e_clipped_self_rec_rawIn_isZero_8; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_8 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_8[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_clipped_self_rec_rawIn_isSpecial_8 = &_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_8; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_17; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_8; // @[rawFloatFromFN.scala:65:28]
wire _activated_wdata_e_clipped_self_rec_T_66 = activated_wdata_e_clipped_self_rec_rawIn_8_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_17; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_35; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_clipped_self_rec_rawIn_8_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_clipped_self_rec_rawIn_8_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_clipped_self_rec_rawIn_8_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_16 = ~activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_8; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_17 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_8 & _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_16; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_clipped_self_rec_rawIn_8_isNaN = _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_17; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_8 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_8 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_8; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_clipped_self_rec_rawIn_8_isInf = _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_8; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_17 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_16}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_clipped_self_rec_rawIn_8_sExp = _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_17; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_32 = ~activated_wdata_e_clipped_self_rec_rawIn_isZero_8; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_33 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_32}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_34 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_8 ? activated_wdata_e_clipped_self_rec_rawIn_subnormFract_8 : activated_wdata_e_clipped_self_rec_rawIn_fractIn_8; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_35 = {_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_33, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_34}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_clipped_self_rec_rawIn_8_sig = _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_35; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_64 = activated_wdata_e_clipped_self_rec_rawIn_8_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_65 = activated_wdata_e_clipped_self_rec_rawIn_8_isZero ? 3'h0 : _activated_wdata_e_clipped_self_rec_T_64; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_67 = {_activated_wdata_e_clipped_self_rec_T_65[2:1], _activated_wdata_e_clipped_self_rec_T_65[0] | _activated_wdata_e_clipped_self_rec_T_66}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_wdata_e_clipped_self_rec_T_68 = {activated_wdata_e_clipped_self_rec_rawIn_8_sign, _activated_wdata_e_clipped_self_rec_T_67}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_wdata_e_clipped_self_rec_T_69 = activated_wdata_e_clipped_self_rec_rawIn_8_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_wdata_e_clipped_self_rec_T_70 = {_activated_wdata_e_clipped_self_rec_T_68, _activated_wdata_e_clipped_self_rec_T_69}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_wdata_e_clipped_self_rec_T_71 = activated_wdata_e_clipped_self_rec_rawIn_8_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_wdata_e_clipped_self_rec_8 = {_activated_wdata_e_clipped_self_rec_T_70, _activated_wdata_e_clipped_self_rec_T_71}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_wdata_e_clipped_result_bits_T_8; // @[fNFromRecFN.scala:66:12]
wire [31:0] activated_wdata_e_clipped_8_bits; // @[Arithmetic.scala:505:26]
wire [8:0] activated_wdata_e_clipped_result_bits_rawIn_exp_8 = _activated_wdata_e_clipped_resizer_8_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_8 = activated_wdata_e_clipped_result_bits_rawIn_exp_8[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isZero_8 = _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_8 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_wdata_e_clipped_result_bits_rawIn_8_isZero = activated_wdata_e_clipped_result_bits_rawIn_isZero_8; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_8 = activated_wdata_e_clipped_result_bits_rawIn_exp_8[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isSpecial_8 = &_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_8; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_17; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_26; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_8; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_8; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_35; // @[rawFloatFromRecFN.scala:61:44]
wire activated_wdata_e_clipped_result_bits_rawIn_8_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_8_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_8_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_wdata_e_clipped_result_bits_rawIn_8_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_wdata_e_clipped_result_bits_rawIn_8_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_16 = activated_wdata_e_clipped_result_bits_rawIn_exp_8[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_24 = activated_wdata_e_clipped_result_bits_rawIn_exp_8[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_17 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_8 & _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_16; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_wdata_e_clipped_result_bits_rawIn_8_isNaN = _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_17; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_25 = ~_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_24; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_26 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_8 & _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_25; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_wdata_e_clipped_result_bits_rawIn_8_isInf = _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_26; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_8 = _activated_wdata_e_clipped_resizer_8_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_wdata_e_clipped_result_bits_rawIn_8_sign = _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_8; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_8 = {1'h0, activated_wdata_e_clipped_result_bits_rawIn_exp_8}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_wdata_e_clipped_result_bits_rawIn_8_sExp = _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_8; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_32 = ~activated_wdata_e_clipped_result_bits_rawIn_isZero_8; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_33 = {1'h0, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_32}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_34 = _activated_wdata_e_clipped_resizer_8_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_35 = {_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_33, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_34}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_wdata_e_clipped_result_bits_rawIn_8_sig = _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_35; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire activated_wdata_e_clipped_result_bits_isSubnormal_8 = $signed(activated_wdata_e_clipped_result_bits_rawIn_8_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_16 = activated_wdata_e_clipped_result_bits_rawIn_8_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_17 = 6'h1 - {1'h0, _activated_wdata_e_clipped_result_bits_denormShiftDist_T_16}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] activated_wdata_e_clipped_result_bits_denormShiftDist_8 = _activated_wdata_e_clipped_result_bits_denormShiftDist_T_17[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_16 = activated_wdata_e_clipped_result_bits_rawIn_8_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_17 = _activated_wdata_e_clipped_result_bits_denormFract_T_16 >> activated_wdata_e_clipped_result_bits_denormShiftDist_8; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] activated_wdata_e_clipped_result_bits_denormFract_8 = _activated_wdata_e_clipped_result_bits_denormFract_T_17[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_48 = activated_wdata_e_clipped_result_bits_rawIn_8_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _activated_wdata_e_clipped_result_bits_expOut_T_49 = {1'h0, _activated_wdata_e_clipped_result_bits_expOut_T_48} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_50 = _activated_wdata_e_clipped_result_bits_expOut_T_49[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_51 = activated_wdata_e_clipped_result_bits_isSubnormal_8 ? 8'h0 : _activated_wdata_e_clipped_result_bits_expOut_T_50; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _activated_wdata_e_clipped_result_bits_expOut_T_52 = activated_wdata_e_clipped_result_bits_rawIn_8_isNaN | activated_wdata_e_clipped_result_bits_rawIn_8_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_53 = {8{_activated_wdata_e_clipped_result_bits_expOut_T_52}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] activated_wdata_e_clipped_result_bits_expOut_8 = _activated_wdata_e_clipped_result_bits_expOut_T_51 | _activated_wdata_e_clipped_result_bits_expOut_T_53; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_16 = activated_wdata_e_clipped_result_bits_rawIn_8_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_17 = activated_wdata_e_clipped_result_bits_rawIn_8_isInf ? 23'h0 : _activated_wdata_e_clipped_result_bits_fractOut_T_16; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] activated_wdata_e_clipped_result_bits_fractOut_8 = activated_wdata_e_clipped_result_bits_isSubnormal_8 ? activated_wdata_e_clipped_result_bits_denormFract_8 : _activated_wdata_e_clipped_result_bits_fractOut_T_17; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] activated_wdata_e_clipped_result_bits_hi_8 = {activated_wdata_e_clipped_result_bits_rawIn_8_sign, activated_wdata_e_clipped_result_bits_expOut_8}; // @[rawFloatFromRecFN.scala:55:23]
assign _activated_wdata_e_clipped_result_bits_T_8 = {activated_wdata_e_clipped_result_bits_hi_8, activated_wdata_e_clipped_result_bits_fractOut_8}; // @[fNFromRecFN.scala:62:16, :66:12]
assign activated_wdata_e_clipped_8_bits = _activated_wdata_e_clipped_result_bits_T_8; // @[fNFromRecFN.scala:66:12]
wire activated_wdata_e_act_raw_sign_8 = activated_wdata_e_clipped_8_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_act_raw_8_sign = activated_wdata_e_act_raw_sign_8; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_wdata_e_act_raw_expIn_8 = activated_wdata_e_clipped_8_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_wdata_e_act_raw_fractIn_8 = activated_wdata_e_clipped_8_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_wdata_e_act_raw_isZeroExpIn_8 = activated_wdata_e_act_raw_expIn_8 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_act_raw_isZeroFractIn_8 = activated_wdata_e_act_raw_fractIn_8 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_act_raw_normDist_T_352 = activated_wdata_e_act_raw_fractIn_8[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_353 = activated_wdata_e_act_raw_fractIn_8[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_354 = activated_wdata_e_act_raw_fractIn_8[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_355 = activated_wdata_e_act_raw_fractIn_8[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_356 = activated_wdata_e_act_raw_fractIn_8[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_357 = activated_wdata_e_act_raw_fractIn_8[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_358 = activated_wdata_e_act_raw_fractIn_8[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_359 = activated_wdata_e_act_raw_fractIn_8[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_360 = activated_wdata_e_act_raw_fractIn_8[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_361 = activated_wdata_e_act_raw_fractIn_8[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_362 = activated_wdata_e_act_raw_fractIn_8[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_363 = activated_wdata_e_act_raw_fractIn_8[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_364 = activated_wdata_e_act_raw_fractIn_8[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_365 = activated_wdata_e_act_raw_fractIn_8[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_366 = activated_wdata_e_act_raw_fractIn_8[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_367 = activated_wdata_e_act_raw_fractIn_8[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_368 = activated_wdata_e_act_raw_fractIn_8[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_369 = activated_wdata_e_act_raw_fractIn_8[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_370 = activated_wdata_e_act_raw_fractIn_8[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_371 = activated_wdata_e_act_raw_fractIn_8[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_372 = activated_wdata_e_act_raw_fractIn_8[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_373 = activated_wdata_e_act_raw_fractIn_8[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_374 = activated_wdata_e_act_raw_fractIn_8[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_375 = _activated_wdata_e_act_raw_normDist_T_353 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_376 = _activated_wdata_e_act_raw_normDist_T_354 ? 5'h14 : _activated_wdata_e_act_raw_normDist_T_375; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_377 = _activated_wdata_e_act_raw_normDist_T_355 ? 5'h13 : _activated_wdata_e_act_raw_normDist_T_376; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_378 = _activated_wdata_e_act_raw_normDist_T_356 ? 5'h12 : _activated_wdata_e_act_raw_normDist_T_377; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_379 = _activated_wdata_e_act_raw_normDist_T_357 ? 5'h11 : _activated_wdata_e_act_raw_normDist_T_378; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_380 = _activated_wdata_e_act_raw_normDist_T_358 ? 5'h10 : _activated_wdata_e_act_raw_normDist_T_379; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_381 = _activated_wdata_e_act_raw_normDist_T_359 ? 5'hF : _activated_wdata_e_act_raw_normDist_T_380; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_382 = _activated_wdata_e_act_raw_normDist_T_360 ? 5'hE : _activated_wdata_e_act_raw_normDist_T_381; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_383 = _activated_wdata_e_act_raw_normDist_T_361 ? 5'hD : _activated_wdata_e_act_raw_normDist_T_382; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_384 = _activated_wdata_e_act_raw_normDist_T_362 ? 5'hC : _activated_wdata_e_act_raw_normDist_T_383; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_385 = _activated_wdata_e_act_raw_normDist_T_363 ? 5'hB : _activated_wdata_e_act_raw_normDist_T_384; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_386 = _activated_wdata_e_act_raw_normDist_T_364 ? 5'hA : _activated_wdata_e_act_raw_normDist_T_385; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_387 = _activated_wdata_e_act_raw_normDist_T_365 ? 5'h9 : _activated_wdata_e_act_raw_normDist_T_386; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_388 = _activated_wdata_e_act_raw_normDist_T_366 ? 5'h8 : _activated_wdata_e_act_raw_normDist_T_387; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_389 = _activated_wdata_e_act_raw_normDist_T_367 ? 5'h7 : _activated_wdata_e_act_raw_normDist_T_388; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_390 = _activated_wdata_e_act_raw_normDist_T_368 ? 5'h6 : _activated_wdata_e_act_raw_normDist_T_389; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_391 = _activated_wdata_e_act_raw_normDist_T_369 ? 5'h5 : _activated_wdata_e_act_raw_normDist_T_390; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_392 = _activated_wdata_e_act_raw_normDist_T_370 ? 5'h4 : _activated_wdata_e_act_raw_normDist_T_391; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_393 = _activated_wdata_e_act_raw_normDist_T_371 ? 5'h3 : _activated_wdata_e_act_raw_normDist_T_392; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_394 = _activated_wdata_e_act_raw_normDist_T_372 ? 5'h2 : _activated_wdata_e_act_raw_normDist_T_393; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_395 = _activated_wdata_e_act_raw_normDist_T_373 ? 5'h1 : _activated_wdata_e_act_raw_normDist_T_394; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_act_raw_normDist_8 = _activated_wdata_e_act_raw_normDist_T_374 ? 5'h0 : _activated_wdata_e_act_raw_normDist_T_395; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_act_raw_subnormFract_T_16 = {31'h0, activated_wdata_e_act_raw_fractIn_8} << activated_wdata_e_act_raw_normDist_8; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_act_raw_subnormFract_T_17 = _activated_wdata_e_act_raw_subnormFract_T_16[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_act_raw_subnormFract_8 = {_activated_wdata_e_act_raw_subnormFract_T_17, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_40 = {4'hF, ~activated_wdata_e_act_raw_normDist_8}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_41 = activated_wdata_e_act_raw_isZeroExpIn_8 ? _activated_wdata_e_act_raw_adjustedExp_T_40 : {1'h0, activated_wdata_e_act_raw_expIn_8}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_act_raw_adjustedExp_T_42 = activated_wdata_e_act_raw_isZeroExpIn_8 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_act_raw_adjustedExp_T_43 = {6'h20, _activated_wdata_e_act_raw_adjustedExp_T_42}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_act_raw_adjustedExp_T_44 = {1'h0, _activated_wdata_e_act_raw_adjustedExp_T_41} + {2'h0, _activated_wdata_e_act_raw_adjustedExp_T_43}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_act_raw_adjustedExp_8 = _activated_wdata_e_act_raw_adjustedExp_T_44[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_act_raw_out_sExp_T_16 = activated_wdata_e_act_raw_adjustedExp_8; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_act_raw_isZero_8 = activated_wdata_e_act_raw_isZeroExpIn_8 & activated_wdata_e_act_raw_isZeroFractIn_8; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_act_raw_8_isZero = activated_wdata_e_act_raw_isZero_8; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_act_raw_isSpecial_T_8 = activated_wdata_e_act_raw_adjustedExp_8[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_act_raw_isSpecial_8 = &_activated_wdata_e_act_raw_isSpecial_T_8; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_act_raw_out_isNaN_T_17; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_act_raw_out_isInf_T_8; // @[rawFloatFromFN.scala:65:28]
wire [9:0] _activated_wdata_e_act_raw_out_sExp_T_17; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_act_raw_out_sig_T_35; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_act_raw_8_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_act_raw_8_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_act_raw_8_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_act_raw_8_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_raw_out_isNaN_T_16 = ~activated_wdata_e_act_raw_isZeroFractIn_8; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_act_raw_out_isNaN_T_17 = activated_wdata_e_act_raw_isSpecial_8 & _activated_wdata_e_act_raw_out_isNaN_T_16; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_act_raw_8_isNaN = _activated_wdata_e_act_raw_out_isNaN_T_17; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_act_raw_out_isInf_T_8 = activated_wdata_e_act_raw_isSpecial_8 & activated_wdata_e_act_raw_isZeroFractIn_8; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_act_raw_8_isInf = _activated_wdata_e_act_raw_out_isInf_T_8; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_act_raw_out_sExp_T_17 = {1'h0, _activated_wdata_e_act_raw_out_sExp_T_16}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_act_raw_8_sExp = _activated_wdata_e_act_raw_out_sExp_T_17; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_act_raw_out_sig_T_32 = ~activated_wdata_e_act_raw_isZero_8; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_act_raw_out_sig_T_33 = {1'h0, _activated_wdata_e_act_raw_out_sig_T_32}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_act_raw_out_sig_T_34 = activated_wdata_e_act_raw_isZeroExpIn_8 ? activated_wdata_e_act_raw_subnormFract_8 : activated_wdata_e_act_raw_fractIn_8; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_act_raw_out_sig_T_35 = {_activated_wdata_e_act_raw_out_sig_T_33, _activated_wdata_e_act_raw_out_sig_T_34}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_act_raw_8_sig = _activated_wdata_e_act_raw_out_sig_T_35; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [31:0] _activated_wdata_e_act_result_bits_T_26; // @[Arithmetic.scala:514:27]
wire [31:0] activated_wdata_e_act_result_8_bits; // @[Arithmetic.scala:513:26]
wire _activated_wdata_e_act_result_bits_T_24 = ~activated_wdata_e_act_raw_8_isZero; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_result_bits_T_25 = _activated_wdata_e_act_result_bits_T_24 & activated_wdata_e_act_raw_8_sign; // @[rawFloatFromFN.scala:63:19]
assign _activated_wdata_e_act_result_bits_T_26 = _activated_wdata_e_act_result_bits_T_25 ? 32'h0 : activated_wdata_e_clipped_8_bits; // @[Arithmetic.scala:505:26, :514:{27,40}]
assign activated_wdata_e_act_result_8_bits = _activated_wdata_e_act_result_bits_T_26; // @[Arithmetic.scala:513:26, :514:27]
wire [31:0] activated_wdata_e_act_8_bits = _activated_wdata_e_act_T_8 ? activated_wdata_e_act_result_8_bits : activated_wdata_e_clipped_8_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_wdata_WIRE_8_0_bits = activated_wdata_e_act_8_bits; // @[Mux.scala:126:16]
wire [31:0] activated_wdata_2_0_0_bits = _activated_wdata_WIRE_8_0_bits; // @[ExecuteController.scala:925:{34,74}]
wire activated_wdata_e_clipped_self_rec_rawIn_9_sign = activated_wdata_e_clipped_self_rec_rawIn_sign_9; // @[rawFloatFromFN.scala:44:18, :63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_9 = activated_wdata_e_clipped_self_rec_rawIn_expIn_9 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_9 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_396 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_397 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_398 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_399 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_400 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_401 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_402 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_403 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_404 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_405 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_406 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_407 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_408 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_409 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_410 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_411 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_412 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_413 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_414 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_415 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_416 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_417 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_418 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_9[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_419 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_397 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_420 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_398 ? 5'h14 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_419; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_421 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_399 ? 5'h13 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_420; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_422 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_400 ? 5'h12 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_421; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_423 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_401 ? 5'h11 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_422; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_424 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_402 ? 5'h10 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_423; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_425 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_403 ? 5'hF : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_424; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_426 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_404 ? 5'hE : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_425; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_427 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_405 ? 5'hD : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_426; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_428 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_406 ? 5'hC : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_427; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_429 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_407 ? 5'hB : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_428; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_430 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_408 ? 5'hA : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_429; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_431 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_409 ? 5'h9 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_430; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_432 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_410 ? 5'h8 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_431; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_433 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_411 ? 5'h7 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_432; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_434 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_412 ? 5'h6 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_433; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_435 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_413 ? 5'h5 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_434; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_436 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_414 ? 5'h4 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_435; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_437 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_415 ? 5'h3 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_436; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_438 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_416 ? 5'h2 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_437; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_439 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_417 ? 5'h1 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_438; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_clipped_self_rec_rawIn_normDist_9 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_418 ? 5'h0 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_439; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_18 = {31'h0, activated_wdata_e_clipped_self_rec_rawIn_fractIn_9} << activated_wdata_e_clipped_self_rec_rawIn_normDist_9; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_19 = _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_18[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_subnormFract_9 = {_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_19, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_45 = {4'hF, ~activated_wdata_e_clipped_self_rec_rawIn_normDist_9}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_46 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_9 ? _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_45 : {1'h0, activated_wdata_e_clipped_self_rec_rawIn_expIn_9}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_47 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_9 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_48 = {6'h20, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_47}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_49 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_46} + {2'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_48}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_9 = _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_49[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_18 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_9; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_clipped_self_rec_rawIn_isZero_9 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_9 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_clipped_self_rec_rawIn_9_isZero = activated_wdata_e_clipped_self_rec_rawIn_isZero_9; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_9 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_9[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_clipped_self_rec_rawIn_isSpecial_9 = &_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_9; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_19; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_9; // @[rawFloatFromFN.scala:65:28]
wire _activated_wdata_e_clipped_self_rec_T_74 = activated_wdata_e_clipped_self_rec_rawIn_9_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_19; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_39; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_clipped_self_rec_rawIn_9_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_clipped_self_rec_rawIn_9_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_clipped_self_rec_rawIn_9_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_18 = ~activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_19 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_9 & _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_18; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_clipped_self_rec_rawIn_9_isNaN = _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_19; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_9 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_9 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_clipped_self_rec_rawIn_9_isInf = _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_9; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_19 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_18}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_clipped_self_rec_rawIn_9_sExp = _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_19; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_36 = ~activated_wdata_e_clipped_self_rec_rawIn_isZero_9; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_37 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_36}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_38 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_9 ? activated_wdata_e_clipped_self_rec_rawIn_subnormFract_9 : activated_wdata_e_clipped_self_rec_rawIn_fractIn_9; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_39 = {_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_37, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_38}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_clipped_self_rec_rawIn_9_sig = _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_39; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_72 = activated_wdata_e_clipped_self_rec_rawIn_9_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_73 = activated_wdata_e_clipped_self_rec_rawIn_9_isZero ? 3'h0 : _activated_wdata_e_clipped_self_rec_T_72; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_75 = {_activated_wdata_e_clipped_self_rec_T_73[2:1], _activated_wdata_e_clipped_self_rec_T_73[0] | _activated_wdata_e_clipped_self_rec_T_74}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_wdata_e_clipped_self_rec_T_76 = {activated_wdata_e_clipped_self_rec_rawIn_9_sign, _activated_wdata_e_clipped_self_rec_T_75}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_wdata_e_clipped_self_rec_T_77 = activated_wdata_e_clipped_self_rec_rawIn_9_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_wdata_e_clipped_self_rec_T_78 = {_activated_wdata_e_clipped_self_rec_T_76, _activated_wdata_e_clipped_self_rec_T_77}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_wdata_e_clipped_self_rec_T_79 = activated_wdata_e_clipped_self_rec_rawIn_9_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_wdata_e_clipped_self_rec_9 = {_activated_wdata_e_clipped_self_rec_T_78, _activated_wdata_e_clipped_self_rec_T_79}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_wdata_e_clipped_result_bits_T_9; // @[fNFromRecFN.scala:66:12]
wire [31:0] activated_wdata_e_clipped_9_bits; // @[Arithmetic.scala:505:26]
wire [8:0] activated_wdata_e_clipped_result_bits_rawIn_exp_9 = _activated_wdata_e_clipped_resizer_9_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_9 = activated_wdata_e_clipped_result_bits_rawIn_exp_9[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isZero_9 = _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_9 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_wdata_e_clipped_result_bits_rawIn_9_isZero = activated_wdata_e_clipped_result_bits_rawIn_isZero_9; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_9 = activated_wdata_e_clipped_result_bits_rawIn_exp_9[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isSpecial_9 = &_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_9; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_19; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_29; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_9; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_9; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_39; // @[rawFloatFromRecFN.scala:61:44]
wire activated_wdata_e_clipped_result_bits_rawIn_9_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_9_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_9_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_wdata_e_clipped_result_bits_rawIn_9_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_wdata_e_clipped_result_bits_rawIn_9_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_18 = activated_wdata_e_clipped_result_bits_rawIn_exp_9[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_27 = activated_wdata_e_clipped_result_bits_rawIn_exp_9[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_19 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_9 & _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_18; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_wdata_e_clipped_result_bits_rawIn_9_isNaN = _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_19; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_28 = ~_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_27; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_29 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_9 & _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_28; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_wdata_e_clipped_result_bits_rawIn_9_isInf = _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_29; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_9 = _activated_wdata_e_clipped_resizer_9_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_wdata_e_clipped_result_bits_rawIn_9_sign = _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_9; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_9 = {1'h0, activated_wdata_e_clipped_result_bits_rawIn_exp_9}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_wdata_e_clipped_result_bits_rawIn_9_sExp = _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_9; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_36 = ~activated_wdata_e_clipped_result_bits_rawIn_isZero_9; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_37 = {1'h0, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_36}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_38 = _activated_wdata_e_clipped_resizer_9_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_39 = {_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_37, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_38}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_wdata_e_clipped_result_bits_rawIn_9_sig = _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_39; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire activated_wdata_e_clipped_result_bits_isSubnormal_9 = $signed(activated_wdata_e_clipped_result_bits_rawIn_9_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_18 = activated_wdata_e_clipped_result_bits_rawIn_9_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_19 = 6'h1 - {1'h0, _activated_wdata_e_clipped_result_bits_denormShiftDist_T_18}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] activated_wdata_e_clipped_result_bits_denormShiftDist_9 = _activated_wdata_e_clipped_result_bits_denormShiftDist_T_19[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_18 = activated_wdata_e_clipped_result_bits_rawIn_9_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_19 = _activated_wdata_e_clipped_result_bits_denormFract_T_18 >> activated_wdata_e_clipped_result_bits_denormShiftDist_9; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] activated_wdata_e_clipped_result_bits_denormFract_9 = _activated_wdata_e_clipped_result_bits_denormFract_T_19[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_54 = activated_wdata_e_clipped_result_bits_rawIn_9_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _activated_wdata_e_clipped_result_bits_expOut_T_55 = {1'h0, _activated_wdata_e_clipped_result_bits_expOut_T_54} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_56 = _activated_wdata_e_clipped_result_bits_expOut_T_55[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_57 = activated_wdata_e_clipped_result_bits_isSubnormal_9 ? 8'h0 : _activated_wdata_e_clipped_result_bits_expOut_T_56; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _activated_wdata_e_clipped_result_bits_expOut_T_58 = activated_wdata_e_clipped_result_bits_rawIn_9_isNaN | activated_wdata_e_clipped_result_bits_rawIn_9_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_59 = {8{_activated_wdata_e_clipped_result_bits_expOut_T_58}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] activated_wdata_e_clipped_result_bits_expOut_9 = _activated_wdata_e_clipped_result_bits_expOut_T_57 | _activated_wdata_e_clipped_result_bits_expOut_T_59; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_18 = activated_wdata_e_clipped_result_bits_rawIn_9_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_19 = activated_wdata_e_clipped_result_bits_rawIn_9_isInf ? 23'h0 : _activated_wdata_e_clipped_result_bits_fractOut_T_18; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] activated_wdata_e_clipped_result_bits_fractOut_9 = activated_wdata_e_clipped_result_bits_isSubnormal_9 ? activated_wdata_e_clipped_result_bits_denormFract_9 : _activated_wdata_e_clipped_result_bits_fractOut_T_19; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] activated_wdata_e_clipped_result_bits_hi_9 = {activated_wdata_e_clipped_result_bits_rawIn_9_sign, activated_wdata_e_clipped_result_bits_expOut_9}; // @[rawFloatFromRecFN.scala:55:23]
assign _activated_wdata_e_clipped_result_bits_T_9 = {activated_wdata_e_clipped_result_bits_hi_9, activated_wdata_e_clipped_result_bits_fractOut_9}; // @[fNFromRecFN.scala:62:16, :66:12]
assign activated_wdata_e_clipped_9_bits = _activated_wdata_e_clipped_result_bits_T_9; // @[fNFromRecFN.scala:66:12]
wire activated_wdata_e_act_raw_sign_9 = activated_wdata_e_clipped_9_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_act_raw_9_sign = activated_wdata_e_act_raw_sign_9; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_wdata_e_act_raw_expIn_9 = activated_wdata_e_clipped_9_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_wdata_e_act_raw_fractIn_9 = activated_wdata_e_clipped_9_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_wdata_e_act_raw_isZeroExpIn_9 = activated_wdata_e_act_raw_expIn_9 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_act_raw_isZeroFractIn_9 = activated_wdata_e_act_raw_fractIn_9 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_act_raw_normDist_T_396 = activated_wdata_e_act_raw_fractIn_9[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_397 = activated_wdata_e_act_raw_fractIn_9[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_398 = activated_wdata_e_act_raw_fractIn_9[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_399 = activated_wdata_e_act_raw_fractIn_9[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_400 = activated_wdata_e_act_raw_fractIn_9[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_401 = activated_wdata_e_act_raw_fractIn_9[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_402 = activated_wdata_e_act_raw_fractIn_9[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_403 = activated_wdata_e_act_raw_fractIn_9[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_404 = activated_wdata_e_act_raw_fractIn_9[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_405 = activated_wdata_e_act_raw_fractIn_9[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_406 = activated_wdata_e_act_raw_fractIn_9[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_407 = activated_wdata_e_act_raw_fractIn_9[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_408 = activated_wdata_e_act_raw_fractIn_9[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_409 = activated_wdata_e_act_raw_fractIn_9[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_410 = activated_wdata_e_act_raw_fractIn_9[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_411 = activated_wdata_e_act_raw_fractIn_9[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_412 = activated_wdata_e_act_raw_fractIn_9[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_413 = activated_wdata_e_act_raw_fractIn_9[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_414 = activated_wdata_e_act_raw_fractIn_9[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_415 = activated_wdata_e_act_raw_fractIn_9[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_416 = activated_wdata_e_act_raw_fractIn_9[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_417 = activated_wdata_e_act_raw_fractIn_9[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_418 = activated_wdata_e_act_raw_fractIn_9[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_419 = _activated_wdata_e_act_raw_normDist_T_397 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_420 = _activated_wdata_e_act_raw_normDist_T_398 ? 5'h14 : _activated_wdata_e_act_raw_normDist_T_419; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_421 = _activated_wdata_e_act_raw_normDist_T_399 ? 5'h13 : _activated_wdata_e_act_raw_normDist_T_420; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_422 = _activated_wdata_e_act_raw_normDist_T_400 ? 5'h12 : _activated_wdata_e_act_raw_normDist_T_421; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_423 = _activated_wdata_e_act_raw_normDist_T_401 ? 5'h11 : _activated_wdata_e_act_raw_normDist_T_422; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_424 = _activated_wdata_e_act_raw_normDist_T_402 ? 5'h10 : _activated_wdata_e_act_raw_normDist_T_423; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_425 = _activated_wdata_e_act_raw_normDist_T_403 ? 5'hF : _activated_wdata_e_act_raw_normDist_T_424; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_426 = _activated_wdata_e_act_raw_normDist_T_404 ? 5'hE : _activated_wdata_e_act_raw_normDist_T_425; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_427 = _activated_wdata_e_act_raw_normDist_T_405 ? 5'hD : _activated_wdata_e_act_raw_normDist_T_426; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_428 = _activated_wdata_e_act_raw_normDist_T_406 ? 5'hC : _activated_wdata_e_act_raw_normDist_T_427; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_429 = _activated_wdata_e_act_raw_normDist_T_407 ? 5'hB : _activated_wdata_e_act_raw_normDist_T_428; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_430 = _activated_wdata_e_act_raw_normDist_T_408 ? 5'hA : _activated_wdata_e_act_raw_normDist_T_429; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_431 = _activated_wdata_e_act_raw_normDist_T_409 ? 5'h9 : _activated_wdata_e_act_raw_normDist_T_430; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_432 = _activated_wdata_e_act_raw_normDist_T_410 ? 5'h8 : _activated_wdata_e_act_raw_normDist_T_431; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_433 = _activated_wdata_e_act_raw_normDist_T_411 ? 5'h7 : _activated_wdata_e_act_raw_normDist_T_432; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_434 = _activated_wdata_e_act_raw_normDist_T_412 ? 5'h6 : _activated_wdata_e_act_raw_normDist_T_433; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_435 = _activated_wdata_e_act_raw_normDist_T_413 ? 5'h5 : _activated_wdata_e_act_raw_normDist_T_434; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_436 = _activated_wdata_e_act_raw_normDist_T_414 ? 5'h4 : _activated_wdata_e_act_raw_normDist_T_435; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_437 = _activated_wdata_e_act_raw_normDist_T_415 ? 5'h3 : _activated_wdata_e_act_raw_normDist_T_436; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_438 = _activated_wdata_e_act_raw_normDist_T_416 ? 5'h2 : _activated_wdata_e_act_raw_normDist_T_437; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_439 = _activated_wdata_e_act_raw_normDist_T_417 ? 5'h1 : _activated_wdata_e_act_raw_normDist_T_438; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_act_raw_normDist_9 = _activated_wdata_e_act_raw_normDist_T_418 ? 5'h0 : _activated_wdata_e_act_raw_normDist_T_439; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_act_raw_subnormFract_T_18 = {31'h0, activated_wdata_e_act_raw_fractIn_9} << activated_wdata_e_act_raw_normDist_9; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_act_raw_subnormFract_T_19 = _activated_wdata_e_act_raw_subnormFract_T_18[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_act_raw_subnormFract_9 = {_activated_wdata_e_act_raw_subnormFract_T_19, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_45 = {4'hF, ~activated_wdata_e_act_raw_normDist_9}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_46 = activated_wdata_e_act_raw_isZeroExpIn_9 ? _activated_wdata_e_act_raw_adjustedExp_T_45 : {1'h0, activated_wdata_e_act_raw_expIn_9}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_act_raw_adjustedExp_T_47 = activated_wdata_e_act_raw_isZeroExpIn_9 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_act_raw_adjustedExp_T_48 = {6'h20, _activated_wdata_e_act_raw_adjustedExp_T_47}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_act_raw_adjustedExp_T_49 = {1'h0, _activated_wdata_e_act_raw_adjustedExp_T_46} + {2'h0, _activated_wdata_e_act_raw_adjustedExp_T_48}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_act_raw_adjustedExp_9 = _activated_wdata_e_act_raw_adjustedExp_T_49[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_act_raw_out_sExp_T_18 = activated_wdata_e_act_raw_adjustedExp_9; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_act_raw_isZero_9 = activated_wdata_e_act_raw_isZeroExpIn_9 & activated_wdata_e_act_raw_isZeroFractIn_9; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_act_raw_9_isZero = activated_wdata_e_act_raw_isZero_9; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_act_raw_isSpecial_T_9 = activated_wdata_e_act_raw_adjustedExp_9[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_act_raw_isSpecial_9 = &_activated_wdata_e_act_raw_isSpecial_T_9; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_act_raw_out_isNaN_T_19; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_act_raw_out_isInf_T_9; // @[rawFloatFromFN.scala:65:28]
wire [9:0] _activated_wdata_e_act_raw_out_sExp_T_19; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_act_raw_out_sig_T_39; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_act_raw_9_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_act_raw_9_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_act_raw_9_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_act_raw_9_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_raw_out_isNaN_T_18 = ~activated_wdata_e_act_raw_isZeroFractIn_9; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_act_raw_out_isNaN_T_19 = activated_wdata_e_act_raw_isSpecial_9 & _activated_wdata_e_act_raw_out_isNaN_T_18; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_act_raw_9_isNaN = _activated_wdata_e_act_raw_out_isNaN_T_19; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_act_raw_out_isInf_T_9 = activated_wdata_e_act_raw_isSpecial_9 & activated_wdata_e_act_raw_isZeroFractIn_9; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_act_raw_9_isInf = _activated_wdata_e_act_raw_out_isInf_T_9; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_act_raw_out_sExp_T_19 = {1'h0, _activated_wdata_e_act_raw_out_sExp_T_18}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_act_raw_9_sExp = _activated_wdata_e_act_raw_out_sExp_T_19; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_act_raw_out_sig_T_36 = ~activated_wdata_e_act_raw_isZero_9; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_act_raw_out_sig_T_37 = {1'h0, _activated_wdata_e_act_raw_out_sig_T_36}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_act_raw_out_sig_T_38 = activated_wdata_e_act_raw_isZeroExpIn_9 ? activated_wdata_e_act_raw_subnormFract_9 : activated_wdata_e_act_raw_fractIn_9; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_act_raw_out_sig_T_39 = {_activated_wdata_e_act_raw_out_sig_T_37, _activated_wdata_e_act_raw_out_sig_T_38}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_act_raw_9_sig = _activated_wdata_e_act_raw_out_sig_T_39; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [31:0] _activated_wdata_e_act_result_bits_T_29; // @[Arithmetic.scala:514:27]
wire [31:0] activated_wdata_e_act_result_9_bits; // @[Arithmetic.scala:513:26]
wire _activated_wdata_e_act_result_bits_T_27 = ~activated_wdata_e_act_raw_9_isZero; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_result_bits_T_28 = _activated_wdata_e_act_result_bits_T_27 & activated_wdata_e_act_raw_9_sign; // @[rawFloatFromFN.scala:63:19]
assign _activated_wdata_e_act_result_bits_T_29 = _activated_wdata_e_act_result_bits_T_28 ? 32'h0 : activated_wdata_e_clipped_9_bits; // @[Arithmetic.scala:505:26, :514:{27,40}]
assign activated_wdata_e_act_result_9_bits = _activated_wdata_e_act_result_bits_T_29; // @[Arithmetic.scala:513:26, :514:27]
wire [31:0] activated_wdata_e_act_9_bits = _activated_wdata_e_act_T_9 ? activated_wdata_e_act_result_9_bits : activated_wdata_e_clipped_9_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_wdata_WIRE_9_0_bits = activated_wdata_e_act_9_bits; // @[Mux.scala:126:16]
wire [31:0] activated_wdata_2_1_0_bits = _activated_wdata_WIRE_9_0_bits; // @[ExecuteController.scala:925:{34,74}]
wire activated_wdata_e_clipped_self_rec_rawIn_10_sign = activated_wdata_e_clipped_self_rec_rawIn_sign_10; // @[rawFloatFromFN.scala:44:18, :63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_10 = activated_wdata_e_clipped_self_rec_rawIn_expIn_10 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_10 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_440 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_441 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_442 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_443 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_444 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_445 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_446 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_447 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_448 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_449 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_450 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_451 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_452 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_453 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_454 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_455 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_456 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_457 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_458 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_459 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_460 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_461 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_462 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_10[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_463 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_441 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_464 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_442 ? 5'h14 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_463; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_465 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_443 ? 5'h13 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_464; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_466 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_444 ? 5'h12 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_465; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_467 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_445 ? 5'h11 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_466; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_468 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_446 ? 5'h10 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_467; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_469 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_447 ? 5'hF : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_468; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_470 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_448 ? 5'hE : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_469; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_471 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_449 ? 5'hD : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_470; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_472 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_450 ? 5'hC : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_471; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_473 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_451 ? 5'hB : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_472; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_474 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_452 ? 5'hA : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_473; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_475 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_453 ? 5'h9 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_474; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_476 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_454 ? 5'h8 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_475; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_477 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_455 ? 5'h7 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_476; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_478 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_456 ? 5'h6 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_477; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_479 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_457 ? 5'h5 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_478; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_480 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_458 ? 5'h4 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_479; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_481 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_459 ? 5'h3 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_480; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_482 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_460 ? 5'h2 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_481; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_483 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_461 ? 5'h1 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_482; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_clipped_self_rec_rawIn_normDist_10 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_462 ? 5'h0 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_483; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_20 = {31'h0, activated_wdata_e_clipped_self_rec_rawIn_fractIn_10} << activated_wdata_e_clipped_self_rec_rawIn_normDist_10; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_21 = _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_20[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_subnormFract_10 = {_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_21, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_50 = {4'hF, ~activated_wdata_e_clipped_self_rec_rawIn_normDist_10}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_51 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_10 ? _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_50 : {1'h0, activated_wdata_e_clipped_self_rec_rawIn_expIn_10}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_52 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_10 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_53 = {6'h20, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_52}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_54 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_51} + {2'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_53}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_10 = _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_54[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_20 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_10; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_clipped_self_rec_rawIn_isZero_10 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_10 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_clipped_self_rec_rawIn_10_isZero = activated_wdata_e_clipped_self_rec_rawIn_isZero_10; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_10 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_10[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_clipped_self_rec_rawIn_isSpecial_10 = &_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_10; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_21; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_10; // @[rawFloatFromFN.scala:65:28]
wire _activated_wdata_e_clipped_self_rec_T_82 = activated_wdata_e_clipped_self_rec_rawIn_10_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_21; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_43; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_clipped_self_rec_rawIn_10_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_clipped_self_rec_rawIn_10_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_clipped_self_rec_rawIn_10_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_20 = ~activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_21 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_10 & _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_20; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_clipped_self_rec_rawIn_10_isNaN = _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_21; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_10 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_10 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_clipped_self_rec_rawIn_10_isInf = _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_10; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_21 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_20}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_clipped_self_rec_rawIn_10_sExp = _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_21; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_40 = ~activated_wdata_e_clipped_self_rec_rawIn_isZero_10; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_41 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_40}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_42 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_10 ? activated_wdata_e_clipped_self_rec_rawIn_subnormFract_10 : activated_wdata_e_clipped_self_rec_rawIn_fractIn_10; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_43 = {_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_41, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_42}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_clipped_self_rec_rawIn_10_sig = _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_43; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_80 = activated_wdata_e_clipped_self_rec_rawIn_10_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_81 = activated_wdata_e_clipped_self_rec_rawIn_10_isZero ? 3'h0 : _activated_wdata_e_clipped_self_rec_T_80; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_83 = {_activated_wdata_e_clipped_self_rec_T_81[2:1], _activated_wdata_e_clipped_self_rec_T_81[0] | _activated_wdata_e_clipped_self_rec_T_82}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_wdata_e_clipped_self_rec_T_84 = {activated_wdata_e_clipped_self_rec_rawIn_10_sign, _activated_wdata_e_clipped_self_rec_T_83}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_wdata_e_clipped_self_rec_T_85 = activated_wdata_e_clipped_self_rec_rawIn_10_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_wdata_e_clipped_self_rec_T_86 = {_activated_wdata_e_clipped_self_rec_T_84, _activated_wdata_e_clipped_self_rec_T_85}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_wdata_e_clipped_self_rec_T_87 = activated_wdata_e_clipped_self_rec_rawIn_10_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_wdata_e_clipped_self_rec_10 = {_activated_wdata_e_clipped_self_rec_T_86, _activated_wdata_e_clipped_self_rec_T_87}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_wdata_e_clipped_result_bits_T_10; // @[fNFromRecFN.scala:66:12]
wire [31:0] activated_wdata_e_clipped_10_bits; // @[Arithmetic.scala:505:26]
wire [8:0] activated_wdata_e_clipped_result_bits_rawIn_exp_10 = _activated_wdata_e_clipped_resizer_10_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_10 = activated_wdata_e_clipped_result_bits_rawIn_exp_10[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isZero_10 = _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_10 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_wdata_e_clipped_result_bits_rawIn_10_isZero = activated_wdata_e_clipped_result_bits_rawIn_isZero_10; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_10 = activated_wdata_e_clipped_result_bits_rawIn_exp_10[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isSpecial_10 = &_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_10; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_21; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_32; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_10; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_10; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_43; // @[rawFloatFromRecFN.scala:61:44]
wire activated_wdata_e_clipped_result_bits_rawIn_10_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_10_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_10_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_wdata_e_clipped_result_bits_rawIn_10_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_wdata_e_clipped_result_bits_rawIn_10_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_20 = activated_wdata_e_clipped_result_bits_rawIn_exp_10[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_30 = activated_wdata_e_clipped_result_bits_rawIn_exp_10[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_21 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_10 & _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_20; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_wdata_e_clipped_result_bits_rawIn_10_isNaN = _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_21; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_31 = ~_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_30; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_32 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_10 & _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_31; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_wdata_e_clipped_result_bits_rawIn_10_isInf = _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_32; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_10 = _activated_wdata_e_clipped_resizer_10_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_wdata_e_clipped_result_bits_rawIn_10_sign = _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_10; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_10 = {1'h0, activated_wdata_e_clipped_result_bits_rawIn_exp_10}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_wdata_e_clipped_result_bits_rawIn_10_sExp = _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_10; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_40 = ~activated_wdata_e_clipped_result_bits_rawIn_isZero_10; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_41 = {1'h0, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_40}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_42 = _activated_wdata_e_clipped_resizer_10_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_43 = {_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_41, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_42}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_wdata_e_clipped_result_bits_rawIn_10_sig = _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_43; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire activated_wdata_e_clipped_result_bits_isSubnormal_10 = $signed(activated_wdata_e_clipped_result_bits_rawIn_10_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_20 = activated_wdata_e_clipped_result_bits_rawIn_10_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_21 = 6'h1 - {1'h0, _activated_wdata_e_clipped_result_bits_denormShiftDist_T_20}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] activated_wdata_e_clipped_result_bits_denormShiftDist_10 = _activated_wdata_e_clipped_result_bits_denormShiftDist_T_21[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_20 = activated_wdata_e_clipped_result_bits_rawIn_10_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_21 = _activated_wdata_e_clipped_result_bits_denormFract_T_20 >> activated_wdata_e_clipped_result_bits_denormShiftDist_10; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] activated_wdata_e_clipped_result_bits_denormFract_10 = _activated_wdata_e_clipped_result_bits_denormFract_T_21[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_60 = activated_wdata_e_clipped_result_bits_rawIn_10_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _activated_wdata_e_clipped_result_bits_expOut_T_61 = {1'h0, _activated_wdata_e_clipped_result_bits_expOut_T_60} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_62 = _activated_wdata_e_clipped_result_bits_expOut_T_61[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_63 = activated_wdata_e_clipped_result_bits_isSubnormal_10 ? 8'h0 : _activated_wdata_e_clipped_result_bits_expOut_T_62; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _activated_wdata_e_clipped_result_bits_expOut_T_64 = activated_wdata_e_clipped_result_bits_rawIn_10_isNaN | activated_wdata_e_clipped_result_bits_rawIn_10_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_65 = {8{_activated_wdata_e_clipped_result_bits_expOut_T_64}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] activated_wdata_e_clipped_result_bits_expOut_10 = _activated_wdata_e_clipped_result_bits_expOut_T_63 | _activated_wdata_e_clipped_result_bits_expOut_T_65; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_20 = activated_wdata_e_clipped_result_bits_rawIn_10_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_21 = activated_wdata_e_clipped_result_bits_rawIn_10_isInf ? 23'h0 : _activated_wdata_e_clipped_result_bits_fractOut_T_20; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] activated_wdata_e_clipped_result_bits_fractOut_10 = activated_wdata_e_clipped_result_bits_isSubnormal_10 ? activated_wdata_e_clipped_result_bits_denormFract_10 : _activated_wdata_e_clipped_result_bits_fractOut_T_21; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] activated_wdata_e_clipped_result_bits_hi_10 = {activated_wdata_e_clipped_result_bits_rawIn_10_sign, activated_wdata_e_clipped_result_bits_expOut_10}; // @[rawFloatFromRecFN.scala:55:23]
assign _activated_wdata_e_clipped_result_bits_T_10 = {activated_wdata_e_clipped_result_bits_hi_10, activated_wdata_e_clipped_result_bits_fractOut_10}; // @[fNFromRecFN.scala:62:16, :66:12]
assign activated_wdata_e_clipped_10_bits = _activated_wdata_e_clipped_result_bits_T_10; // @[fNFromRecFN.scala:66:12]
wire activated_wdata_e_act_raw_sign_10 = activated_wdata_e_clipped_10_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_act_raw_10_sign = activated_wdata_e_act_raw_sign_10; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_wdata_e_act_raw_expIn_10 = activated_wdata_e_clipped_10_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_wdata_e_act_raw_fractIn_10 = activated_wdata_e_clipped_10_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_wdata_e_act_raw_isZeroExpIn_10 = activated_wdata_e_act_raw_expIn_10 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_act_raw_isZeroFractIn_10 = activated_wdata_e_act_raw_fractIn_10 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_act_raw_normDist_T_440 = activated_wdata_e_act_raw_fractIn_10[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_441 = activated_wdata_e_act_raw_fractIn_10[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_442 = activated_wdata_e_act_raw_fractIn_10[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_443 = activated_wdata_e_act_raw_fractIn_10[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_444 = activated_wdata_e_act_raw_fractIn_10[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_445 = activated_wdata_e_act_raw_fractIn_10[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_446 = activated_wdata_e_act_raw_fractIn_10[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_447 = activated_wdata_e_act_raw_fractIn_10[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_448 = activated_wdata_e_act_raw_fractIn_10[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_449 = activated_wdata_e_act_raw_fractIn_10[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_450 = activated_wdata_e_act_raw_fractIn_10[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_451 = activated_wdata_e_act_raw_fractIn_10[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_452 = activated_wdata_e_act_raw_fractIn_10[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_453 = activated_wdata_e_act_raw_fractIn_10[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_454 = activated_wdata_e_act_raw_fractIn_10[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_455 = activated_wdata_e_act_raw_fractIn_10[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_456 = activated_wdata_e_act_raw_fractIn_10[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_457 = activated_wdata_e_act_raw_fractIn_10[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_458 = activated_wdata_e_act_raw_fractIn_10[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_459 = activated_wdata_e_act_raw_fractIn_10[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_460 = activated_wdata_e_act_raw_fractIn_10[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_461 = activated_wdata_e_act_raw_fractIn_10[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_462 = activated_wdata_e_act_raw_fractIn_10[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_463 = _activated_wdata_e_act_raw_normDist_T_441 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_464 = _activated_wdata_e_act_raw_normDist_T_442 ? 5'h14 : _activated_wdata_e_act_raw_normDist_T_463; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_465 = _activated_wdata_e_act_raw_normDist_T_443 ? 5'h13 : _activated_wdata_e_act_raw_normDist_T_464; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_466 = _activated_wdata_e_act_raw_normDist_T_444 ? 5'h12 : _activated_wdata_e_act_raw_normDist_T_465; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_467 = _activated_wdata_e_act_raw_normDist_T_445 ? 5'h11 : _activated_wdata_e_act_raw_normDist_T_466; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_468 = _activated_wdata_e_act_raw_normDist_T_446 ? 5'h10 : _activated_wdata_e_act_raw_normDist_T_467; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_469 = _activated_wdata_e_act_raw_normDist_T_447 ? 5'hF : _activated_wdata_e_act_raw_normDist_T_468; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_470 = _activated_wdata_e_act_raw_normDist_T_448 ? 5'hE : _activated_wdata_e_act_raw_normDist_T_469; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_471 = _activated_wdata_e_act_raw_normDist_T_449 ? 5'hD : _activated_wdata_e_act_raw_normDist_T_470; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_472 = _activated_wdata_e_act_raw_normDist_T_450 ? 5'hC : _activated_wdata_e_act_raw_normDist_T_471; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_473 = _activated_wdata_e_act_raw_normDist_T_451 ? 5'hB : _activated_wdata_e_act_raw_normDist_T_472; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_474 = _activated_wdata_e_act_raw_normDist_T_452 ? 5'hA : _activated_wdata_e_act_raw_normDist_T_473; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_475 = _activated_wdata_e_act_raw_normDist_T_453 ? 5'h9 : _activated_wdata_e_act_raw_normDist_T_474; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_476 = _activated_wdata_e_act_raw_normDist_T_454 ? 5'h8 : _activated_wdata_e_act_raw_normDist_T_475; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_477 = _activated_wdata_e_act_raw_normDist_T_455 ? 5'h7 : _activated_wdata_e_act_raw_normDist_T_476; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_478 = _activated_wdata_e_act_raw_normDist_T_456 ? 5'h6 : _activated_wdata_e_act_raw_normDist_T_477; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_479 = _activated_wdata_e_act_raw_normDist_T_457 ? 5'h5 : _activated_wdata_e_act_raw_normDist_T_478; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_480 = _activated_wdata_e_act_raw_normDist_T_458 ? 5'h4 : _activated_wdata_e_act_raw_normDist_T_479; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_481 = _activated_wdata_e_act_raw_normDist_T_459 ? 5'h3 : _activated_wdata_e_act_raw_normDist_T_480; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_482 = _activated_wdata_e_act_raw_normDist_T_460 ? 5'h2 : _activated_wdata_e_act_raw_normDist_T_481; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_483 = _activated_wdata_e_act_raw_normDist_T_461 ? 5'h1 : _activated_wdata_e_act_raw_normDist_T_482; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_act_raw_normDist_10 = _activated_wdata_e_act_raw_normDist_T_462 ? 5'h0 : _activated_wdata_e_act_raw_normDist_T_483; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_act_raw_subnormFract_T_20 = {31'h0, activated_wdata_e_act_raw_fractIn_10} << activated_wdata_e_act_raw_normDist_10; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_act_raw_subnormFract_T_21 = _activated_wdata_e_act_raw_subnormFract_T_20[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_act_raw_subnormFract_10 = {_activated_wdata_e_act_raw_subnormFract_T_21, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_50 = {4'hF, ~activated_wdata_e_act_raw_normDist_10}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_51 = activated_wdata_e_act_raw_isZeroExpIn_10 ? _activated_wdata_e_act_raw_adjustedExp_T_50 : {1'h0, activated_wdata_e_act_raw_expIn_10}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_act_raw_adjustedExp_T_52 = activated_wdata_e_act_raw_isZeroExpIn_10 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_act_raw_adjustedExp_T_53 = {6'h20, _activated_wdata_e_act_raw_adjustedExp_T_52}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_act_raw_adjustedExp_T_54 = {1'h0, _activated_wdata_e_act_raw_adjustedExp_T_51} + {2'h0, _activated_wdata_e_act_raw_adjustedExp_T_53}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_act_raw_adjustedExp_10 = _activated_wdata_e_act_raw_adjustedExp_T_54[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_act_raw_out_sExp_T_20 = activated_wdata_e_act_raw_adjustedExp_10; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_act_raw_isZero_10 = activated_wdata_e_act_raw_isZeroExpIn_10 & activated_wdata_e_act_raw_isZeroFractIn_10; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_act_raw_10_isZero = activated_wdata_e_act_raw_isZero_10; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_act_raw_isSpecial_T_10 = activated_wdata_e_act_raw_adjustedExp_10[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_act_raw_isSpecial_10 = &_activated_wdata_e_act_raw_isSpecial_T_10; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_act_raw_out_isNaN_T_21; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_act_raw_out_isInf_T_10; // @[rawFloatFromFN.scala:65:28]
wire [9:0] _activated_wdata_e_act_raw_out_sExp_T_21; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_act_raw_out_sig_T_43; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_act_raw_10_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_act_raw_10_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_act_raw_10_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_act_raw_10_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_raw_out_isNaN_T_20 = ~activated_wdata_e_act_raw_isZeroFractIn_10; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_act_raw_out_isNaN_T_21 = activated_wdata_e_act_raw_isSpecial_10 & _activated_wdata_e_act_raw_out_isNaN_T_20; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_act_raw_10_isNaN = _activated_wdata_e_act_raw_out_isNaN_T_21; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_act_raw_out_isInf_T_10 = activated_wdata_e_act_raw_isSpecial_10 & activated_wdata_e_act_raw_isZeroFractIn_10; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_act_raw_10_isInf = _activated_wdata_e_act_raw_out_isInf_T_10; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_act_raw_out_sExp_T_21 = {1'h0, _activated_wdata_e_act_raw_out_sExp_T_20}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_act_raw_10_sExp = _activated_wdata_e_act_raw_out_sExp_T_21; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_act_raw_out_sig_T_40 = ~activated_wdata_e_act_raw_isZero_10; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_act_raw_out_sig_T_41 = {1'h0, _activated_wdata_e_act_raw_out_sig_T_40}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_act_raw_out_sig_T_42 = activated_wdata_e_act_raw_isZeroExpIn_10 ? activated_wdata_e_act_raw_subnormFract_10 : activated_wdata_e_act_raw_fractIn_10; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_act_raw_out_sig_T_43 = {_activated_wdata_e_act_raw_out_sig_T_41, _activated_wdata_e_act_raw_out_sig_T_42}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_act_raw_10_sig = _activated_wdata_e_act_raw_out_sig_T_43; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [31:0] _activated_wdata_e_act_result_bits_T_32; // @[Arithmetic.scala:514:27]
wire [31:0] activated_wdata_e_act_result_10_bits; // @[Arithmetic.scala:513:26]
wire _activated_wdata_e_act_result_bits_T_30 = ~activated_wdata_e_act_raw_10_isZero; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_result_bits_T_31 = _activated_wdata_e_act_result_bits_T_30 & activated_wdata_e_act_raw_10_sign; // @[rawFloatFromFN.scala:63:19]
assign _activated_wdata_e_act_result_bits_T_32 = _activated_wdata_e_act_result_bits_T_31 ? 32'h0 : activated_wdata_e_clipped_10_bits; // @[Arithmetic.scala:505:26, :514:{27,40}]
assign activated_wdata_e_act_result_10_bits = _activated_wdata_e_act_result_bits_T_32; // @[Arithmetic.scala:513:26, :514:27]
wire [31:0] activated_wdata_e_act_10_bits = _activated_wdata_e_act_T_10 ? activated_wdata_e_act_result_10_bits : activated_wdata_e_clipped_10_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_wdata_WIRE_10_0_bits = activated_wdata_e_act_10_bits; // @[Mux.scala:126:16]
wire [31:0] activated_wdata_2_2_0_bits = _activated_wdata_WIRE_10_0_bits; // @[ExecuteController.scala:925:{34,74}]
wire activated_wdata_e_clipped_self_rec_rawIn_11_sign = activated_wdata_e_clipped_self_rec_rawIn_sign_11; // @[rawFloatFromFN.scala:44:18, :63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_11 = activated_wdata_e_clipped_self_rec_rawIn_expIn_11 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_11 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_484 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_485 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_486 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_487 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_488 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_489 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_490 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_491 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_492 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_493 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_494 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_495 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_496 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_497 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_498 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_499 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_500 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_501 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_502 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_503 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_504 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_505 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_506 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_11[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_507 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_485 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_508 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_486 ? 5'h14 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_507; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_509 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_487 ? 5'h13 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_508; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_510 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_488 ? 5'h12 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_509; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_511 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_489 ? 5'h11 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_510; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_512 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_490 ? 5'h10 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_511; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_513 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_491 ? 5'hF : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_512; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_514 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_492 ? 5'hE : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_513; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_515 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_493 ? 5'hD : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_514; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_516 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_494 ? 5'hC : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_515; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_517 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_495 ? 5'hB : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_516; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_518 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_496 ? 5'hA : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_517; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_519 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_497 ? 5'h9 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_518; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_520 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_498 ? 5'h8 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_519; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_521 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_499 ? 5'h7 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_520; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_522 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_500 ? 5'h6 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_521; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_523 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_501 ? 5'h5 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_522; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_524 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_502 ? 5'h4 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_523; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_525 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_503 ? 5'h3 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_524; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_526 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_504 ? 5'h2 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_525; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_527 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_505 ? 5'h1 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_526; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_clipped_self_rec_rawIn_normDist_11 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_506 ? 5'h0 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_527; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_22 = {31'h0, activated_wdata_e_clipped_self_rec_rawIn_fractIn_11} << activated_wdata_e_clipped_self_rec_rawIn_normDist_11; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_23 = _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_22[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_subnormFract_11 = {_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_23, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_55 = {4'hF, ~activated_wdata_e_clipped_self_rec_rawIn_normDist_11}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_56 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_11 ? _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_55 : {1'h0, activated_wdata_e_clipped_self_rec_rawIn_expIn_11}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_57 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_11 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_58 = {6'h20, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_57}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_59 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_56} + {2'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_58}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_11 = _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_59[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_22 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_11; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_clipped_self_rec_rawIn_isZero_11 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_11 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_11; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_clipped_self_rec_rawIn_11_isZero = activated_wdata_e_clipped_self_rec_rawIn_isZero_11; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_11 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_11[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_clipped_self_rec_rawIn_isSpecial_11 = &_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_11; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_23; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_11; // @[rawFloatFromFN.scala:65:28]
wire _activated_wdata_e_clipped_self_rec_T_90 = activated_wdata_e_clipped_self_rec_rawIn_11_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_23; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_47; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_clipped_self_rec_rawIn_11_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_clipped_self_rec_rawIn_11_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_clipped_self_rec_rawIn_11_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_22 = ~activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_11; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_23 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_11 & _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_22; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_clipped_self_rec_rawIn_11_isNaN = _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_23; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_11 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_11 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_11; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_clipped_self_rec_rawIn_11_isInf = _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_11; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_23 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_22}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_clipped_self_rec_rawIn_11_sExp = _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_23; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_44 = ~activated_wdata_e_clipped_self_rec_rawIn_isZero_11; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_45 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_44}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_46 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_11 ? activated_wdata_e_clipped_self_rec_rawIn_subnormFract_11 : activated_wdata_e_clipped_self_rec_rawIn_fractIn_11; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_47 = {_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_45, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_46}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_clipped_self_rec_rawIn_11_sig = _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_47; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_88 = activated_wdata_e_clipped_self_rec_rawIn_11_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_89 = activated_wdata_e_clipped_self_rec_rawIn_11_isZero ? 3'h0 : _activated_wdata_e_clipped_self_rec_T_88; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_91 = {_activated_wdata_e_clipped_self_rec_T_89[2:1], _activated_wdata_e_clipped_self_rec_T_89[0] | _activated_wdata_e_clipped_self_rec_T_90}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_wdata_e_clipped_self_rec_T_92 = {activated_wdata_e_clipped_self_rec_rawIn_11_sign, _activated_wdata_e_clipped_self_rec_T_91}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_wdata_e_clipped_self_rec_T_93 = activated_wdata_e_clipped_self_rec_rawIn_11_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_wdata_e_clipped_self_rec_T_94 = {_activated_wdata_e_clipped_self_rec_T_92, _activated_wdata_e_clipped_self_rec_T_93}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_wdata_e_clipped_self_rec_T_95 = activated_wdata_e_clipped_self_rec_rawIn_11_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_wdata_e_clipped_self_rec_11 = {_activated_wdata_e_clipped_self_rec_T_94, _activated_wdata_e_clipped_self_rec_T_95}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_wdata_e_clipped_result_bits_T_11; // @[fNFromRecFN.scala:66:12]
wire [31:0] activated_wdata_e_clipped_11_bits; // @[Arithmetic.scala:505:26]
wire [8:0] activated_wdata_e_clipped_result_bits_rawIn_exp_11 = _activated_wdata_e_clipped_resizer_11_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_11 = activated_wdata_e_clipped_result_bits_rawIn_exp_11[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isZero_11 = _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_11 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_wdata_e_clipped_result_bits_rawIn_11_isZero = activated_wdata_e_clipped_result_bits_rawIn_isZero_11; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_11 = activated_wdata_e_clipped_result_bits_rawIn_exp_11[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isSpecial_11 = &_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_11; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_23; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_35; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_11; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_11; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_47; // @[rawFloatFromRecFN.scala:61:44]
wire activated_wdata_e_clipped_result_bits_rawIn_11_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_11_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_11_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_wdata_e_clipped_result_bits_rawIn_11_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_wdata_e_clipped_result_bits_rawIn_11_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_22 = activated_wdata_e_clipped_result_bits_rawIn_exp_11[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_33 = activated_wdata_e_clipped_result_bits_rawIn_exp_11[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_23 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_11 & _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_22; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_wdata_e_clipped_result_bits_rawIn_11_isNaN = _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_23; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_34 = ~_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_33; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_35 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_11 & _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_34; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_wdata_e_clipped_result_bits_rawIn_11_isInf = _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_35; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_11 = _activated_wdata_e_clipped_resizer_11_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_wdata_e_clipped_result_bits_rawIn_11_sign = _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_11; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_11 = {1'h0, activated_wdata_e_clipped_result_bits_rawIn_exp_11}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_wdata_e_clipped_result_bits_rawIn_11_sExp = _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_11; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_44 = ~activated_wdata_e_clipped_result_bits_rawIn_isZero_11; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_45 = {1'h0, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_44}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_46 = _activated_wdata_e_clipped_resizer_11_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_47 = {_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_45, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_46}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_wdata_e_clipped_result_bits_rawIn_11_sig = _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_47; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire activated_wdata_e_clipped_result_bits_isSubnormal_11 = $signed(activated_wdata_e_clipped_result_bits_rawIn_11_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_22 = activated_wdata_e_clipped_result_bits_rawIn_11_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_23 = 6'h1 - {1'h0, _activated_wdata_e_clipped_result_bits_denormShiftDist_T_22}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] activated_wdata_e_clipped_result_bits_denormShiftDist_11 = _activated_wdata_e_clipped_result_bits_denormShiftDist_T_23[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_22 = activated_wdata_e_clipped_result_bits_rawIn_11_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_23 = _activated_wdata_e_clipped_result_bits_denormFract_T_22 >> activated_wdata_e_clipped_result_bits_denormShiftDist_11; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] activated_wdata_e_clipped_result_bits_denormFract_11 = _activated_wdata_e_clipped_result_bits_denormFract_T_23[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_66 = activated_wdata_e_clipped_result_bits_rawIn_11_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _activated_wdata_e_clipped_result_bits_expOut_T_67 = {1'h0, _activated_wdata_e_clipped_result_bits_expOut_T_66} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_68 = _activated_wdata_e_clipped_result_bits_expOut_T_67[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_69 = activated_wdata_e_clipped_result_bits_isSubnormal_11 ? 8'h0 : _activated_wdata_e_clipped_result_bits_expOut_T_68; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _activated_wdata_e_clipped_result_bits_expOut_T_70 = activated_wdata_e_clipped_result_bits_rawIn_11_isNaN | activated_wdata_e_clipped_result_bits_rawIn_11_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_71 = {8{_activated_wdata_e_clipped_result_bits_expOut_T_70}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] activated_wdata_e_clipped_result_bits_expOut_11 = _activated_wdata_e_clipped_result_bits_expOut_T_69 | _activated_wdata_e_clipped_result_bits_expOut_T_71; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_22 = activated_wdata_e_clipped_result_bits_rawIn_11_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_23 = activated_wdata_e_clipped_result_bits_rawIn_11_isInf ? 23'h0 : _activated_wdata_e_clipped_result_bits_fractOut_T_22; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] activated_wdata_e_clipped_result_bits_fractOut_11 = activated_wdata_e_clipped_result_bits_isSubnormal_11 ? activated_wdata_e_clipped_result_bits_denormFract_11 : _activated_wdata_e_clipped_result_bits_fractOut_T_23; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] activated_wdata_e_clipped_result_bits_hi_11 = {activated_wdata_e_clipped_result_bits_rawIn_11_sign, activated_wdata_e_clipped_result_bits_expOut_11}; // @[rawFloatFromRecFN.scala:55:23]
assign _activated_wdata_e_clipped_result_bits_T_11 = {activated_wdata_e_clipped_result_bits_hi_11, activated_wdata_e_clipped_result_bits_fractOut_11}; // @[fNFromRecFN.scala:62:16, :66:12]
assign activated_wdata_e_clipped_11_bits = _activated_wdata_e_clipped_result_bits_T_11; // @[fNFromRecFN.scala:66:12]
wire activated_wdata_e_act_raw_sign_11 = activated_wdata_e_clipped_11_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_act_raw_11_sign = activated_wdata_e_act_raw_sign_11; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_wdata_e_act_raw_expIn_11 = activated_wdata_e_clipped_11_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_wdata_e_act_raw_fractIn_11 = activated_wdata_e_clipped_11_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_wdata_e_act_raw_isZeroExpIn_11 = activated_wdata_e_act_raw_expIn_11 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_act_raw_isZeroFractIn_11 = activated_wdata_e_act_raw_fractIn_11 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_act_raw_normDist_T_484 = activated_wdata_e_act_raw_fractIn_11[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_485 = activated_wdata_e_act_raw_fractIn_11[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_486 = activated_wdata_e_act_raw_fractIn_11[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_487 = activated_wdata_e_act_raw_fractIn_11[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_488 = activated_wdata_e_act_raw_fractIn_11[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_489 = activated_wdata_e_act_raw_fractIn_11[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_490 = activated_wdata_e_act_raw_fractIn_11[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_491 = activated_wdata_e_act_raw_fractIn_11[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_492 = activated_wdata_e_act_raw_fractIn_11[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_493 = activated_wdata_e_act_raw_fractIn_11[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_494 = activated_wdata_e_act_raw_fractIn_11[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_495 = activated_wdata_e_act_raw_fractIn_11[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_496 = activated_wdata_e_act_raw_fractIn_11[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_497 = activated_wdata_e_act_raw_fractIn_11[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_498 = activated_wdata_e_act_raw_fractIn_11[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_499 = activated_wdata_e_act_raw_fractIn_11[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_500 = activated_wdata_e_act_raw_fractIn_11[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_501 = activated_wdata_e_act_raw_fractIn_11[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_502 = activated_wdata_e_act_raw_fractIn_11[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_503 = activated_wdata_e_act_raw_fractIn_11[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_504 = activated_wdata_e_act_raw_fractIn_11[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_505 = activated_wdata_e_act_raw_fractIn_11[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_506 = activated_wdata_e_act_raw_fractIn_11[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_507 = _activated_wdata_e_act_raw_normDist_T_485 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_508 = _activated_wdata_e_act_raw_normDist_T_486 ? 5'h14 : _activated_wdata_e_act_raw_normDist_T_507; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_509 = _activated_wdata_e_act_raw_normDist_T_487 ? 5'h13 : _activated_wdata_e_act_raw_normDist_T_508; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_510 = _activated_wdata_e_act_raw_normDist_T_488 ? 5'h12 : _activated_wdata_e_act_raw_normDist_T_509; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_511 = _activated_wdata_e_act_raw_normDist_T_489 ? 5'h11 : _activated_wdata_e_act_raw_normDist_T_510; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_512 = _activated_wdata_e_act_raw_normDist_T_490 ? 5'h10 : _activated_wdata_e_act_raw_normDist_T_511; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_513 = _activated_wdata_e_act_raw_normDist_T_491 ? 5'hF : _activated_wdata_e_act_raw_normDist_T_512; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_514 = _activated_wdata_e_act_raw_normDist_T_492 ? 5'hE : _activated_wdata_e_act_raw_normDist_T_513; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_515 = _activated_wdata_e_act_raw_normDist_T_493 ? 5'hD : _activated_wdata_e_act_raw_normDist_T_514; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_516 = _activated_wdata_e_act_raw_normDist_T_494 ? 5'hC : _activated_wdata_e_act_raw_normDist_T_515; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_517 = _activated_wdata_e_act_raw_normDist_T_495 ? 5'hB : _activated_wdata_e_act_raw_normDist_T_516; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_518 = _activated_wdata_e_act_raw_normDist_T_496 ? 5'hA : _activated_wdata_e_act_raw_normDist_T_517; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_519 = _activated_wdata_e_act_raw_normDist_T_497 ? 5'h9 : _activated_wdata_e_act_raw_normDist_T_518; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_520 = _activated_wdata_e_act_raw_normDist_T_498 ? 5'h8 : _activated_wdata_e_act_raw_normDist_T_519; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_521 = _activated_wdata_e_act_raw_normDist_T_499 ? 5'h7 : _activated_wdata_e_act_raw_normDist_T_520; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_522 = _activated_wdata_e_act_raw_normDist_T_500 ? 5'h6 : _activated_wdata_e_act_raw_normDist_T_521; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_523 = _activated_wdata_e_act_raw_normDist_T_501 ? 5'h5 : _activated_wdata_e_act_raw_normDist_T_522; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_524 = _activated_wdata_e_act_raw_normDist_T_502 ? 5'h4 : _activated_wdata_e_act_raw_normDist_T_523; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_525 = _activated_wdata_e_act_raw_normDist_T_503 ? 5'h3 : _activated_wdata_e_act_raw_normDist_T_524; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_526 = _activated_wdata_e_act_raw_normDist_T_504 ? 5'h2 : _activated_wdata_e_act_raw_normDist_T_525; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_527 = _activated_wdata_e_act_raw_normDist_T_505 ? 5'h1 : _activated_wdata_e_act_raw_normDist_T_526; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_act_raw_normDist_11 = _activated_wdata_e_act_raw_normDist_T_506 ? 5'h0 : _activated_wdata_e_act_raw_normDist_T_527; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_act_raw_subnormFract_T_22 = {31'h0, activated_wdata_e_act_raw_fractIn_11} << activated_wdata_e_act_raw_normDist_11; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_act_raw_subnormFract_T_23 = _activated_wdata_e_act_raw_subnormFract_T_22[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_act_raw_subnormFract_11 = {_activated_wdata_e_act_raw_subnormFract_T_23, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_55 = {4'hF, ~activated_wdata_e_act_raw_normDist_11}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_56 = activated_wdata_e_act_raw_isZeroExpIn_11 ? _activated_wdata_e_act_raw_adjustedExp_T_55 : {1'h0, activated_wdata_e_act_raw_expIn_11}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_act_raw_adjustedExp_T_57 = activated_wdata_e_act_raw_isZeroExpIn_11 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_act_raw_adjustedExp_T_58 = {6'h20, _activated_wdata_e_act_raw_adjustedExp_T_57}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_act_raw_adjustedExp_T_59 = {1'h0, _activated_wdata_e_act_raw_adjustedExp_T_56} + {2'h0, _activated_wdata_e_act_raw_adjustedExp_T_58}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_act_raw_adjustedExp_11 = _activated_wdata_e_act_raw_adjustedExp_T_59[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_act_raw_out_sExp_T_22 = activated_wdata_e_act_raw_adjustedExp_11; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_act_raw_isZero_11 = activated_wdata_e_act_raw_isZeroExpIn_11 & activated_wdata_e_act_raw_isZeroFractIn_11; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_act_raw_11_isZero = activated_wdata_e_act_raw_isZero_11; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_act_raw_isSpecial_T_11 = activated_wdata_e_act_raw_adjustedExp_11[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_act_raw_isSpecial_11 = &_activated_wdata_e_act_raw_isSpecial_T_11; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_act_raw_out_isNaN_T_23; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_act_raw_out_isInf_T_11; // @[rawFloatFromFN.scala:65:28]
wire [9:0] _activated_wdata_e_act_raw_out_sExp_T_23; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_act_raw_out_sig_T_47; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_act_raw_11_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_act_raw_11_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_act_raw_11_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_act_raw_11_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_raw_out_isNaN_T_22 = ~activated_wdata_e_act_raw_isZeroFractIn_11; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_act_raw_out_isNaN_T_23 = activated_wdata_e_act_raw_isSpecial_11 & _activated_wdata_e_act_raw_out_isNaN_T_22; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_act_raw_11_isNaN = _activated_wdata_e_act_raw_out_isNaN_T_23; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_act_raw_out_isInf_T_11 = activated_wdata_e_act_raw_isSpecial_11 & activated_wdata_e_act_raw_isZeroFractIn_11; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_act_raw_11_isInf = _activated_wdata_e_act_raw_out_isInf_T_11; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_act_raw_out_sExp_T_23 = {1'h0, _activated_wdata_e_act_raw_out_sExp_T_22}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_act_raw_11_sExp = _activated_wdata_e_act_raw_out_sExp_T_23; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_act_raw_out_sig_T_44 = ~activated_wdata_e_act_raw_isZero_11; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_act_raw_out_sig_T_45 = {1'h0, _activated_wdata_e_act_raw_out_sig_T_44}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_act_raw_out_sig_T_46 = activated_wdata_e_act_raw_isZeroExpIn_11 ? activated_wdata_e_act_raw_subnormFract_11 : activated_wdata_e_act_raw_fractIn_11; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_act_raw_out_sig_T_47 = {_activated_wdata_e_act_raw_out_sig_T_45, _activated_wdata_e_act_raw_out_sig_T_46}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_act_raw_11_sig = _activated_wdata_e_act_raw_out_sig_T_47; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [31:0] _activated_wdata_e_act_result_bits_T_35; // @[Arithmetic.scala:514:27]
wire [31:0] activated_wdata_e_act_result_11_bits; // @[Arithmetic.scala:513:26]
wire _activated_wdata_e_act_result_bits_T_33 = ~activated_wdata_e_act_raw_11_isZero; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_result_bits_T_34 = _activated_wdata_e_act_result_bits_T_33 & activated_wdata_e_act_raw_11_sign; // @[rawFloatFromFN.scala:63:19]
assign _activated_wdata_e_act_result_bits_T_35 = _activated_wdata_e_act_result_bits_T_34 ? 32'h0 : activated_wdata_e_clipped_11_bits; // @[Arithmetic.scala:505:26, :514:{27,40}]
assign activated_wdata_e_act_result_11_bits = _activated_wdata_e_act_result_bits_T_35; // @[Arithmetic.scala:513:26, :514:27]
wire [31:0] activated_wdata_e_act_11_bits = _activated_wdata_e_act_T_11 ? activated_wdata_e_act_result_11_bits : activated_wdata_e_clipped_11_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_wdata_WIRE_11_0_bits = activated_wdata_e_act_11_bits; // @[Mux.scala:126:16]
wire [31:0] activated_wdata_2_3_0_bits = _activated_wdata_WIRE_11_0_bits; // @[ExecuteController.scala:925:{34,74}]
wire _io_srams_write_2_en_T = w_bank == 2'h2; // @[ExecuteController.scala:911:19, :934:64]
wire _io_srams_write_2_en_T_1 = start_array_outputting & _io_srams_write_2_en_T; // @[ExecuteController.scala:270:40, :934:{54,64}]
wire _io_srams_write_2_en_T_2 = ~w_address_is_acc_addr; // @[ExecuteController.scala:907:22, :934:75]
wire _io_srams_write_2_en_T_3 = _io_srams_write_2_en_T_1 & _io_srams_write_2_en_T_2; // @[ExecuteController.scala:934:{54,72,75}]
wire _io_srams_write_2_en_T_4 = ~is_garbage_addr; // @[LocalAddr.scala:43:96]
wire _io_srams_write_2_en_T_5 = _io_srams_write_2_en_T_3 & _io_srams_write_2_en_T_4; // @[ExecuteController.scala:934:{72,89,92}]
assign _io_srams_write_2_en_T_6 = _io_srams_write_2_en_T_5 & write_this_row; // @[ExecuteController.scala:919:27, :934:{89,109}]
assign io_srams_write_2_en_0 = _io_srams_write_2_en_T_6; // @[ExecuteController.scala:12:7, :934:109]
wire [63:0] io_srams_write_2_data_lo = {activated_wdata_2_1_0_bits, activated_wdata_2_0_0_bits}; // @[ExecuteController.scala:925:34, :936:49]
wire [63:0] io_srams_write_2_data_hi = {activated_wdata_2_3_0_bits, activated_wdata_2_2_0_bits}; // @[ExecuteController.scala:925:34, :936:49]
assign _io_srams_write_2_data_T = {io_srams_write_2_data_hi, io_srams_write_2_data_lo}; // @[ExecuteController.scala:936:49]
assign io_srams_write_2_data_0 = _io_srams_write_2_data_T; // @[ExecuteController.scala:12:7, :936:49]
wire activated_wdata_e_clipped_self_rec_rawIn_12_sign = activated_wdata_e_clipped_self_rec_rawIn_sign_12; // @[rawFloatFromFN.scala:44:18, :63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_12 = activated_wdata_e_clipped_self_rec_rawIn_expIn_12 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_12 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_528 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_529 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_530 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_531 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_532 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_533 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_534 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_535 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_536 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_537 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_538 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_539 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_540 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_541 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_542 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_543 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_544 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_545 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_546 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_547 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_548 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_549 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_550 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_12[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_551 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_529 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_552 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_530 ? 5'h14 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_551; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_553 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_531 ? 5'h13 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_552; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_554 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_532 ? 5'h12 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_553; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_555 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_533 ? 5'h11 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_554; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_556 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_534 ? 5'h10 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_555; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_557 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_535 ? 5'hF : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_556; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_558 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_536 ? 5'hE : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_557; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_559 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_537 ? 5'hD : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_558; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_560 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_538 ? 5'hC : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_559; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_561 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_539 ? 5'hB : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_560; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_562 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_540 ? 5'hA : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_561; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_563 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_541 ? 5'h9 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_562; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_564 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_542 ? 5'h8 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_563; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_565 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_543 ? 5'h7 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_564; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_566 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_544 ? 5'h6 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_565; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_567 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_545 ? 5'h5 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_566; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_568 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_546 ? 5'h4 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_567; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_569 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_547 ? 5'h3 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_568; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_570 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_548 ? 5'h2 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_569; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_571 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_549 ? 5'h1 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_570; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_clipped_self_rec_rawIn_normDist_12 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_550 ? 5'h0 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_571; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_24 = {31'h0, activated_wdata_e_clipped_self_rec_rawIn_fractIn_12} << activated_wdata_e_clipped_self_rec_rawIn_normDist_12; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_25 = _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_24[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_subnormFract_12 = {_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_25, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_60 = {4'hF, ~activated_wdata_e_clipped_self_rec_rawIn_normDist_12}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_61 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_12 ? _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_60 : {1'h0, activated_wdata_e_clipped_self_rec_rawIn_expIn_12}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_62 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_12 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_63 = {6'h20, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_62}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_64 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_61} + {2'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_63}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_12 = _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_64[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_24 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_12; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_clipped_self_rec_rawIn_isZero_12 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_12 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_12; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_clipped_self_rec_rawIn_12_isZero = activated_wdata_e_clipped_self_rec_rawIn_isZero_12; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_12 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_12[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_clipped_self_rec_rawIn_isSpecial_12 = &_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_12; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_25; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_12; // @[rawFloatFromFN.scala:65:28]
wire _activated_wdata_e_clipped_self_rec_T_98 = activated_wdata_e_clipped_self_rec_rawIn_12_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_25; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_51; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_clipped_self_rec_rawIn_12_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_clipped_self_rec_rawIn_12_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_clipped_self_rec_rawIn_12_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_24 = ~activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_12; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_25 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_12 & _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_24; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_clipped_self_rec_rawIn_12_isNaN = _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_25; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_12 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_12 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_12; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_clipped_self_rec_rawIn_12_isInf = _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_12; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_25 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_24}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_clipped_self_rec_rawIn_12_sExp = _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_25; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_48 = ~activated_wdata_e_clipped_self_rec_rawIn_isZero_12; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_49 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_48}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_50 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_12 ? activated_wdata_e_clipped_self_rec_rawIn_subnormFract_12 : activated_wdata_e_clipped_self_rec_rawIn_fractIn_12; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_51 = {_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_49, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_50}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_clipped_self_rec_rawIn_12_sig = _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_51; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_96 = activated_wdata_e_clipped_self_rec_rawIn_12_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_97 = activated_wdata_e_clipped_self_rec_rawIn_12_isZero ? 3'h0 : _activated_wdata_e_clipped_self_rec_T_96; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_99 = {_activated_wdata_e_clipped_self_rec_T_97[2:1], _activated_wdata_e_clipped_self_rec_T_97[0] | _activated_wdata_e_clipped_self_rec_T_98}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_wdata_e_clipped_self_rec_T_100 = {activated_wdata_e_clipped_self_rec_rawIn_12_sign, _activated_wdata_e_clipped_self_rec_T_99}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_wdata_e_clipped_self_rec_T_101 = activated_wdata_e_clipped_self_rec_rawIn_12_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_wdata_e_clipped_self_rec_T_102 = {_activated_wdata_e_clipped_self_rec_T_100, _activated_wdata_e_clipped_self_rec_T_101}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_wdata_e_clipped_self_rec_T_103 = activated_wdata_e_clipped_self_rec_rawIn_12_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_wdata_e_clipped_self_rec_12 = {_activated_wdata_e_clipped_self_rec_T_102, _activated_wdata_e_clipped_self_rec_T_103}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_wdata_e_clipped_result_bits_T_12; // @[fNFromRecFN.scala:66:12]
wire [31:0] activated_wdata_e_clipped_12_bits; // @[Arithmetic.scala:505:26]
wire [8:0] activated_wdata_e_clipped_result_bits_rawIn_exp_12 = _activated_wdata_e_clipped_resizer_12_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_12 = activated_wdata_e_clipped_result_bits_rawIn_exp_12[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isZero_12 = _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_12 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_wdata_e_clipped_result_bits_rawIn_12_isZero = activated_wdata_e_clipped_result_bits_rawIn_isZero_12; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_12 = activated_wdata_e_clipped_result_bits_rawIn_exp_12[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isSpecial_12 = &_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_12; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_25; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_38; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_12; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_12; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_51; // @[rawFloatFromRecFN.scala:61:44]
wire activated_wdata_e_clipped_result_bits_rawIn_12_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_12_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_12_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_wdata_e_clipped_result_bits_rawIn_12_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_wdata_e_clipped_result_bits_rawIn_12_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_24 = activated_wdata_e_clipped_result_bits_rawIn_exp_12[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_36 = activated_wdata_e_clipped_result_bits_rawIn_exp_12[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_25 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_12 & _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_24; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_wdata_e_clipped_result_bits_rawIn_12_isNaN = _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_25; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_37 = ~_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_36; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_38 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_12 & _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_37; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_wdata_e_clipped_result_bits_rawIn_12_isInf = _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_38; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_12 = _activated_wdata_e_clipped_resizer_12_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_wdata_e_clipped_result_bits_rawIn_12_sign = _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_12; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_12 = {1'h0, activated_wdata_e_clipped_result_bits_rawIn_exp_12}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_wdata_e_clipped_result_bits_rawIn_12_sExp = _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_12; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_48 = ~activated_wdata_e_clipped_result_bits_rawIn_isZero_12; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_49 = {1'h0, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_48}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_50 = _activated_wdata_e_clipped_resizer_12_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_51 = {_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_49, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_50}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_wdata_e_clipped_result_bits_rawIn_12_sig = _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_51; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire activated_wdata_e_clipped_result_bits_isSubnormal_12 = $signed(activated_wdata_e_clipped_result_bits_rawIn_12_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_24 = activated_wdata_e_clipped_result_bits_rawIn_12_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_25 = 6'h1 - {1'h0, _activated_wdata_e_clipped_result_bits_denormShiftDist_T_24}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] activated_wdata_e_clipped_result_bits_denormShiftDist_12 = _activated_wdata_e_clipped_result_bits_denormShiftDist_T_25[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_24 = activated_wdata_e_clipped_result_bits_rawIn_12_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_25 = _activated_wdata_e_clipped_result_bits_denormFract_T_24 >> activated_wdata_e_clipped_result_bits_denormShiftDist_12; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] activated_wdata_e_clipped_result_bits_denormFract_12 = _activated_wdata_e_clipped_result_bits_denormFract_T_25[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_72 = activated_wdata_e_clipped_result_bits_rawIn_12_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _activated_wdata_e_clipped_result_bits_expOut_T_73 = {1'h0, _activated_wdata_e_clipped_result_bits_expOut_T_72} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_74 = _activated_wdata_e_clipped_result_bits_expOut_T_73[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_75 = activated_wdata_e_clipped_result_bits_isSubnormal_12 ? 8'h0 : _activated_wdata_e_clipped_result_bits_expOut_T_74; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _activated_wdata_e_clipped_result_bits_expOut_T_76 = activated_wdata_e_clipped_result_bits_rawIn_12_isNaN | activated_wdata_e_clipped_result_bits_rawIn_12_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_77 = {8{_activated_wdata_e_clipped_result_bits_expOut_T_76}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] activated_wdata_e_clipped_result_bits_expOut_12 = _activated_wdata_e_clipped_result_bits_expOut_T_75 | _activated_wdata_e_clipped_result_bits_expOut_T_77; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_24 = activated_wdata_e_clipped_result_bits_rawIn_12_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_25 = activated_wdata_e_clipped_result_bits_rawIn_12_isInf ? 23'h0 : _activated_wdata_e_clipped_result_bits_fractOut_T_24; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] activated_wdata_e_clipped_result_bits_fractOut_12 = activated_wdata_e_clipped_result_bits_isSubnormal_12 ? activated_wdata_e_clipped_result_bits_denormFract_12 : _activated_wdata_e_clipped_result_bits_fractOut_T_25; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] activated_wdata_e_clipped_result_bits_hi_12 = {activated_wdata_e_clipped_result_bits_rawIn_12_sign, activated_wdata_e_clipped_result_bits_expOut_12}; // @[rawFloatFromRecFN.scala:55:23]
assign _activated_wdata_e_clipped_result_bits_T_12 = {activated_wdata_e_clipped_result_bits_hi_12, activated_wdata_e_clipped_result_bits_fractOut_12}; // @[fNFromRecFN.scala:62:16, :66:12]
assign activated_wdata_e_clipped_12_bits = _activated_wdata_e_clipped_result_bits_T_12; // @[fNFromRecFN.scala:66:12]
wire activated_wdata_e_act_raw_sign_12 = activated_wdata_e_clipped_12_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_act_raw_12_sign = activated_wdata_e_act_raw_sign_12; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_wdata_e_act_raw_expIn_12 = activated_wdata_e_clipped_12_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_wdata_e_act_raw_fractIn_12 = activated_wdata_e_clipped_12_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_wdata_e_act_raw_isZeroExpIn_12 = activated_wdata_e_act_raw_expIn_12 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_act_raw_isZeroFractIn_12 = activated_wdata_e_act_raw_fractIn_12 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_act_raw_normDist_T_528 = activated_wdata_e_act_raw_fractIn_12[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_529 = activated_wdata_e_act_raw_fractIn_12[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_530 = activated_wdata_e_act_raw_fractIn_12[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_531 = activated_wdata_e_act_raw_fractIn_12[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_532 = activated_wdata_e_act_raw_fractIn_12[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_533 = activated_wdata_e_act_raw_fractIn_12[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_534 = activated_wdata_e_act_raw_fractIn_12[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_535 = activated_wdata_e_act_raw_fractIn_12[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_536 = activated_wdata_e_act_raw_fractIn_12[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_537 = activated_wdata_e_act_raw_fractIn_12[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_538 = activated_wdata_e_act_raw_fractIn_12[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_539 = activated_wdata_e_act_raw_fractIn_12[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_540 = activated_wdata_e_act_raw_fractIn_12[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_541 = activated_wdata_e_act_raw_fractIn_12[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_542 = activated_wdata_e_act_raw_fractIn_12[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_543 = activated_wdata_e_act_raw_fractIn_12[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_544 = activated_wdata_e_act_raw_fractIn_12[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_545 = activated_wdata_e_act_raw_fractIn_12[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_546 = activated_wdata_e_act_raw_fractIn_12[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_547 = activated_wdata_e_act_raw_fractIn_12[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_548 = activated_wdata_e_act_raw_fractIn_12[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_549 = activated_wdata_e_act_raw_fractIn_12[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_550 = activated_wdata_e_act_raw_fractIn_12[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_551 = _activated_wdata_e_act_raw_normDist_T_529 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_552 = _activated_wdata_e_act_raw_normDist_T_530 ? 5'h14 : _activated_wdata_e_act_raw_normDist_T_551; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_553 = _activated_wdata_e_act_raw_normDist_T_531 ? 5'h13 : _activated_wdata_e_act_raw_normDist_T_552; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_554 = _activated_wdata_e_act_raw_normDist_T_532 ? 5'h12 : _activated_wdata_e_act_raw_normDist_T_553; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_555 = _activated_wdata_e_act_raw_normDist_T_533 ? 5'h11 : _activated_wdata_e_act_raw_normDist_T_554; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_556 = _activated_wdata_e_act_raw_normDist_T_534 ? 5'h10 : _activated_wdata_e_act_raw_normDist_T_555; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_557 = _activated_wdata_e_act_raw_normDist_T_535 ? 5'hF : _activated_wdata_e_act_raw_normDist_T_556; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_558 = _activated_wdata_e_act_raw_normDist_T_536 ? 5'hE : _activated_wdata_e_act_raw_normDist_T_557; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_559 = _activated_wdata_e_act_raw_normDist_T_537 ? 5'hD : _activated_wdata_e_act_raw_normDist_T_558; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_560 = _activated_wdata_e_act_raw_normDist_T_538 ? 5'hC : _activated_wdata_e_act_raw_normDist_T_559; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_561 = _activated_wdata_e_act_raw_normDist_T_539 ? 5'hB : _activated_wdata_e_act_raw_normDist_T_560; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_562 = _activated_wdata_e_act_raw_normDist_T_540 ? 5'hA : _activated_wdata_e_act_raw_normDist_T_561; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_563 = _activated_wdata_e_act_raw_normDist_T_541 ? 5'h9 : _activated_wdata_e_act_raw_normDist_T_562; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_564 = _activated_wdata_e_act_raw_normDist_T_542 ? 5'h8 : _activated_wdata_e_act_raw_normDist_T_563; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_565 = _activated_wdata_e_act_raw_normDist_T_543 ? 5'h7 : _activated_wdata_e_act_raw_normDist_T_564; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_566 = _activated_wdata_e_act_raw_normDist_T_544 ? 5'h6 : _activated_wdata_e_act_raw_normDist_T_565; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_567 = _activated_wdata_e_act_raw_normDist_T_545 ? 5'h5 : _activated_wdata_e_act_raw_normDist_T_566; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_568 = _activated_wdata_e_act_raw_normDist_T_546 ? 5'h4 : _activated_wdata_e_act_raw_normDist_T_567; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_569 = _activated_wdata_e_act_raw_normDist_T_547 ? 5'h3 : _activated_wdata_e_act_raw_normDist_T_568; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_570 = _activated_wdata_e_act_raw_normDist_T_548 ? 5'h2 : _activated_wdata_e_act_raw_normDist_T_569; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_571 = _activated_wdata_e_act_raw_normDist_T_549 ? 5'h1 : _activated_wdata_e_act_raw_normDist_T_570; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_act_raw_normDist_12 = _activated_wdata_e_act_raw_normDist_T_550 ? 5'h0 : _activated_wdata_e_act_raw_normDist_T_571; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_act_raw_subnormFract_T_24 = {31'h0, activated_wdata_e_act_raw_fractIn_12} << activated_wdata_e_act_raw_normDist_12; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_act_raw_subnormFract_T_25 = _activated_wdata_e_act_raw_subnormFract_T_24[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_act_raw_subnormFract_12 = {_activated_wdata_e_act_raw_subnormFract_T_25, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_60 = {4'hF, ~activated_wdata_e_act_raw_normDist_12}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_61 = activated_wdata_e_act_raw_isZeroExpIn_12 ? _activated_wdata_e_act_raw_adjustedExp_T_60 : {1'h0, activated_wdata_e_act_raw_expIn_12}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_act_raw_adjustedExp_T_62 = activated_wdata_e_act_raw_isZeroExpIn_12 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_act_raw_adjustedExp_T_63 = {6'h20, _activated_wdata_e_act_raw_adjustedExp_T_62}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_act_raw_adjustedExp_T_64 = {1'h0, _activated_wdata_e_act_raw_adjustedExp_T_61} + {2'h0, _activated_wdata_e_act_raw_adjustedExp_T_63}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_act_raw_adjustedExp_12 = _activated_wdata_e_act_raw_adjustedExp_T_64[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_act_raw_out_sExp_T_24 = activated_wdata_e_act_raw_adjustedExp_12; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_act_raw_isZero_12 = activated_wdata_e_act_raw_isZeroExpIn_12 & activated_wdata_e_act_raw_isZeroFractIn_12; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_act_raw_12_isZero = activated_wdata_e_act_raw_isZero_12; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_act_raw_isSpecial_T_12 = activated_wdata_e_act_raw_adjustedExp_12[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_act_raw_isSpecial_12 = &_activated_wdata_e_act_raw_isSpecial_T_12; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_act_raw_out_isNaN_T_25; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_act_raw_out_isInf_T_12; // @[rawFloatFromFN.scala:65:28]
wire [9:0] _activated_wdata_e_act_raw_out_sExp_T_25; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_act_raw_out_sig_T_51; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_act_raw_12_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_act_raw_12_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_act_raw_12_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_act_raw_12_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_raw_out_isNaN_T_24 = ~activated_wdata_e_act_raw_isZeroFractIn_12; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_act_raw_out_isNaN_T_25 = activated_wdata_e_act_raw_isSpecial_12 & _activated_wdata_e_act_raw_out_isNaN_T_24; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_act_raw_12_isNaN = _activated_wdata_e_act_raw_out_isNaN_T_25; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_act_raw_out_isInf_T_12 = activated_wdata_e_act_raw_isSpecial_12 & activated_wdata_e_act_raw_isZeroFractIn_12; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_act_raw_12_isInf = _activated_wdata_e_act_raw_out_isInf_T_12; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_act_raw_out_sExp_T_25 = {1'h0, _activated_wdata_e_act_raw_out_sExp_T_24}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_act_raw_12_sExp = _activated_wdata_e_act_raw_out_sExp_T_25; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_act_raw_out_sig_T_48 = ~activated_wdata_e_act_raw_isZero_12; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_act_raw_out_sig_T_49 = {1'h0, _activated_wdata_e_act_raw_out_sig_T_48}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_act_raw_out_sig_T_50 = activated_wdata_e_act_raw_isZeroExpIn_12 ? activated_wdata_e_act_raw_subnormFract_12 : activated_wdata_e_act_raw_fractIn_12; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_act_raw_out_sig_T_51 = {_activated_wdata_e_act_raw_out_sig_T_49, _activated_wdata_e_act_raw_out_sig_T_50}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_act_raw_12_sig = _activated_wdata_e_act_raw_out_sig_T_51; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [31:0] _activated_wdata_e_act_result_bits_T_38; // @[Arithmetic.scala:514:27]
wire [31:0] activated_wdata_e_act_result_12_bits; // @[Arithmetic.scala:513:26]
wire _activated_wdata_e_act_result_bits_T_36 = ~activated_wdata_e_act_raw_12_isZero; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_result_bits_T_37 = _activated_wdata_e_act_result_bits_T_36 & activated_wdata_e_act_raw_12_sign; // @[rawFloatFromFN.scala:63:19]
assign _activated_wdata_e_act_result_bits_T_38 = _activated_wdata_e_act_result_bits_T_37 ? 32'h0 : activated_wdata_e_clipped_12_bits; // @[Arithmetic.scala:505:26, :514:{27,40}]
assign activated_wdata_e_act_result_12_bits = _activated_wdata_e_act_result_bits_T_38; // @[Arithmetic.scala:513:26, :514:27]
wire [31:0] activated_wdata_e_act_12_bits = _activated_wdata_e_act_T_12 ? activated_wdata_e_act_result_12_bits : activated_wdata_e_clipped_12_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_wdata_WIRE_12_0_bits = activated_wdata_e_act_12_bits; // @[Mux.scala:126:16]
wire [31:0] activated_wdata_3_0_0_bits = _activated_wdata_WIRE_12_0_bits; // @[ExecuteController.scala:925:{34,74}]
wire activated_wdata_e_clipped_self_rec_rawIn_13_sign = activated_wdata_e_clipped_self_rec_rawIn_sign_13; // @[rawFloatFromFN.scala:44:18, :63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_13 = activated_wdata_e_clipped_self_rec_rawIn_expIn_13 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_13 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_572 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_573 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_574 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_575 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_576 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_577 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_578 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_579 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_580 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_581 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_582 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_583 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_584 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_585 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_586 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_587 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_588 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_589 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_590 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_591 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_592 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_593 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_594 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_13[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_595 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_573 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_596 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_574 ? 5'h14 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_595; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_597 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_575 ? 5'h13 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_596; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_598 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_576 ? 5'h12 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_597; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_599 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_577 ? 5'h11 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_598; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_600 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_578 ? 5'h10 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_599; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_601 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_579 ? 5'hF : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_600; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_602 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_580 ? 5'hE : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_601; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_603 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_581 ? 5'hD : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_602; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_604 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_582 ? 5'hC : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_603; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_605 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_583 ? 5'hB : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_604; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_606 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_584 ? 5'hA : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_605; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_607 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_585 ? 5'h9 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_606; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_608 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_586 ? 5'h8 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_607; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_609 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_587 ? 5'h7 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_608; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_610 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_588 ? 5'h6 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_609; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_611 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_589 ? 5'h5 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_610; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_612 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_590 ? 5'h4 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_611; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_613 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_591 ? 5'h3 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_612; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_614 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_592 ? 5'h2 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_613; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_615 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_593 ? 5'h1 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_614; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_clipped_self_rec_rawIn_normDist_13 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_594 ? 5'h0 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_615; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_26 = {31'h0, activated_wdata_e_clipped_self_rec_rawIn_fractIn_13} << activated_wdata_e_clipped_self_rec_rawIn_normDist_13; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_27 = _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_26[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_subnormFract_13 = {_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_27, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_65 = {4'hF, ~activated_wdata_e_clipped_self_rec_rawIn_normDist_13}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_66 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_13 ? _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_65 : {1'h0, activated_wdata_e_clipped_self_rec_rawIn_expIn_13}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_67 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_13 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_68 = {6'h20, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_67}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_69 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_66} + {2'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_68}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_13 = _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_69[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_26 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_13; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_clipped_self_rec_rawIn_isZero_13 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_13 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_13; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_clipped_self_rec_rawIn_13_isZero = activated_wdata_e_clipped_self_rec_rawIn_isZero_13; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_13 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_13[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_clipped_self_rec_rawIn_isSpecial_13 = &_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_13; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_27; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_13; // @[rawFloatFromFN.scala:65:28]
wire _activated_wdata_e_clipped_self_rec_T_106 = activated_wdata_e_clipped_self_rec_rawIn_13_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_27; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_55; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_clipped_self_rec_rawIn_13_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_clipped_self_rec_rawIn_13_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_clipped_self_rec_rawIn_13_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_26 = ~activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_13; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_27 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_13 & _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_26; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_clipped_self_rec_rawIn_13_isNaN = _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_27; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_13 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_13 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_13; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_clipped_self_rec_rawIn_13_isInf = _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_13; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_27 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_26}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_clipped_self_rec_rawIn_13_sExp = _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_27; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_52 = ~activated_wdata_e_clipped_self_rec_rawIn_isZero_13; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_53 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_52}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_54 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_13 ? activated_wdata_e_clipped_self_rec_rawIn_subnormFract_13 : activated_wdata_e_clipped_self_rec_rawIn_fractIn_13; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_55 = {_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_53, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_54}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_clipped_self_rec_rawIn_13_sig = _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_55; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_104 = activated_wdata_e_clipped_self_rec_rawIn_13_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_105 = activated_wdata_e_clipped_self_rec_rawIn_13_isZero ? 3'h0 : _activated_wdata_e_clipped_self_rec_T_104; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_107 = {_activated_wdata_e_clipped_self_rec_T_105[2:1], _activated_wdata_e_clipped_self_rec_T_105[0] | _activated_wdata_e_clipped_self_rec_T_106}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_wdata_e_clipped_self_rec_T_108 = {activated_wdata_e_clipped_self_rec_rawIn_13_sign, _activated_wdata_e_clipped_self_rec_T_107}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_wdata_e_clipped_self_rec_T_109 = activated_wdata_e_clipped_self_rec_rawIn_13_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_wdata_e_clipped_self_rec_T_110 = {_activated_wdata_e_clipped_self_rec_T_108, _activated_wdata_e_clipped_self_rec_T_109}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_wdata_e_clipped_self_rec_T_111 = activated_wdata_e_clipped_self_rec_rawIn_13_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_wdata_e_clipped_self_rec_13 = {_activated_wdata_e_clipped_self_rec_T_110, _activated_wdata_e_clipped_self_rec_T_111}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_wdata_e_clipped_result_bits_T_13; // @[fNFromRecFN.scala:66:12]
wire [31:0] activated_wdata_e_clipped_13_bits; // @[Arithmetic.scala:505:26]
wire [8:0] activated_wdata_e_clipped_result_bits_rawIn_exp_13 = _activated_wdata_e_clipped_resizer_13_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_13 = activated_wdata_e_clipped_result_bits_rawIn_exp_13[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isZero_13 = _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_13 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_wdata_e_clipped_result_bits_rawIn_13_isZero = activated_wdata_e_clipped_result_bits_rawIn_isZero_13; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_13 = activated_wdata_e_clipped_result_bits_rawIn_exp_13[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isSpecial_13 = &_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_13; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_27; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_41; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_13; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_13; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_55; // @[rawFloatFromRecFN.scala:61:44]
wire activated_wdata_e_clipped_result_bits_rawIn_13_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_13_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_13_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_wdata_e_clipped_result_bits_rawIn_13_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_wdata_e_clipped_result_bits_rawIn_13_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_26 = activated_wdata_e_clipped_result_bits_rawIn_exp_13[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_39 = activated_wdata_e_clipped_result_bits_rawIn_exp_13[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_27 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_13 & _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_26; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_wdata_e_clipped_result_bits_rawIn_13_isNaN = _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_27; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_40 = ~_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_39; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_41 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_13 & _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_40; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_wdata_e_clipped_result_bits_rawIn_13_isInf = _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_41; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_13 = _activated_wdata_e_clipped_resizer_13_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_wdata_e_clipped_result_bits_rawIn_13_sign = _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_13; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_13 = {1'h0, activated_wdata_e_clipped_result_bits_rawIn_exp_13}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_wdata_e_clipped_result_bits_rawIn_13_sExp = _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_13; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_52 = ~activated_wdata_e_clipped_result_bits_rawIn_isZero_13; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_53 = {1'h0, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_52}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_54 = _activated_wdata_e_clipped_resizer_13_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_55 = {_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_53, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_54}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_wdata_e_clipped_result_bits_rawIn_13_sig = _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_55; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire activated_wdata_e_clipped_result_bits_isSubnormal_13 = $signed(activated_wdata_e_clipped_result_bits_rawIn_13_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_26 = activated_wdata_e_clipped_result_bits_rawIn_13_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_27 = 6'h1 - {1'h0, _activated_wdata_e_clipped_result_bits_denormShiftDist_T_26}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] activated_wdata_e_clipped_result_bits_denormShiftDist_13 = _activated_wdata_e_clipped_result_bits_denormShiftDist_T_27[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_26 = activated_wdata_e_clipped_result_bits_rawIn_13_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_27 = _activated_wdata_e_clipped_result_bits_denormFract_T_26 >> activated_wdata_e_clipped_result_bits_denormShiftDist_13; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] activated_wdata_e_clipped_result_bits_denormFract_13 = _activated_wdata_e_clipped_result_bits_denormFract_T_27[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_78 = activated_wdata_e_clipped_result_bits_rawIn_13_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _activated_wdata_e_clipped_result_bits_expOut_T_79 = {1'h0, _activated_wdata_e_clipped_result_bits_expOut_T_78} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_80 = _activated_wdata_e_clipped_result_bits_expOut_T_79[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_81 = activated_wdata_e_clipped_result_bits_isSubnormal_13 ? 8'h0 : _activated_wdata_e_clipped_result_bits_expOut_T_80; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _activated_wdata_e_clipped_result_bits_expOut_T_82 = activated_wdata_e_clipped_result_bits_rawIn_13_isNaN | activated_wdata_e_clipped_result_bits_rawIn_13_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_83 = {8{_activated_wdata_e_clipped_result_bits_expOut_T_82}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] activated_wdata_e_clipped_result_bits_expOut_13 = _activated_wdata_e_clipped_result_bits_expOut_T_81 | _activated_wdata_e_clipped_result_bits_expOut_T_83; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_26 = activated_wdata_e_clipped_result_bits_rawIn_13_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_27 = activated_wdata_e_clipped_result_bits_rawIn_13_isInf ? 23'h0 : _activated_wdata_e_clipped_result_bits_fractOut_T_26; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] activated_wdata_e_clipped_result_bits_fractOut_13 = activated_wdata_e_clipped_result_bits_isSubnormal_13 ? activated_wdata_e_clipped_result_bits_denormFract_13 : _activated_wdata_e_clipped_result_bits_fractOut_T_27; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] activated_wdata_e_clipped_result_bits_hi_13 = {activated_wdata_e_clipped_result_bits_rawIn_13_sign, activated_wdata_e_clipped_result_bits_expOut_13}; // @[rawFloatFromRecFN.scala:55:23]
assign _activated_wdata_e_clipped_result_bits_T_13 = {activated_wdata_e_clipped_result_bits_hi_13, activated_wdata_e_clipped_result_bits_fractOut_13}; // @[fNFromRecFN.scala:62:16, :66:12]
assign activated_wdata_e_clipped_13_bits = _activated_wdata_e_clipped_result_bits_T_13; // @[fNFromRecFN.scala:66:12]
wire activated_wdata_e_act_raw_sign_13 = activated_wdata_e_clipped_13_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_act_raw_13_sign = activated_wdata_e_act_raw_sign_13; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_wdata_e_act_raw_expIn_13 = activated_wdata_e_clipped_13_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_wdata_e_act_raw_fractIn_13 = activated_wdata_e_clipped_13_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_wdata_e_act_raw_isZeroExpIn_13 = activated_wdata_e_act_raw_expIn_13 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_act_raw_isZeroFractIn_13 = activated_wdata_e_act_raw_fractIn_13 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_act_raw_normDist_T_572 = activated_wdata_e_act_raw_fractIn_13[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_573 = activated_wdata_e_act_raw_fractIn_13[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_574 = activated_wdata_e_act_raw_fractIn_13[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_575 = activated_wdata_e_act_raw_fractIn_13[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_576 = activated_wdata_e_act_raw_fractIn_13[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_577 = activated_wdata_e_act_raw_fractIn_13[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_578 = activated_wdata_e_act_raw_fractIn_13[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_579 = activated_wdata_e_act_raw_fractIn_13[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_580 = activated_wdata_e_act_raw_fractIn_13[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_581 = activated_wdata_e_act_raw_fractIn_13[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_582 = activated_wdata_e_act_raw_fractIn_13[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_583 = activated_wdata_e_act_raw_fractIn_13[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_584 = activated_wdata_e_act_raw_fractIn_13[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_585 = activated_wdata_e_act_raw_fractIn_13[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_586 = activated_wdata_e_act_raw_fractIn_13[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_587 = activated_wdata_e_act_raw_fractIn_13[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_588 = activated_wdata_e_act_raw_fractIn_13[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_589 = activated_wdata_e_act_raw_fractIn_13[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_590 = activated_wdata_e_act_raw_fractIn_13[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_591 = activated_wdata_e_act_raw_fractIn_13[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_592 = activated_wdata_e_act_raw_fractIn_13[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_593 = activated_wdata_e_act_raw_fractIn_13[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_594 = activated_wdata_e_act_raw_fractIn_13[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_595 = _activated_wdata_e_act_raw_normDist_T_573 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_596 = _activated_wdata_e_act_raw_normDist_T_574 ? 5'h14 : _activated_wdata_e_act_raw_normDist_T_595; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_597 = _activated_wdata_e_act_raw_normDist_T_575 ? 5'h13 : _activated_wdata_e_act_raw_normDist_T_596; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_598 = _activated_wdata_e_act_raw_normDist_T_576 ? 5'h12 : _activated_wdata_e_act_raw_normDist_T_597; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_599 = _activated_wdata_e_act_raw_normDist_T_577 ? 5'h11 : _activated_wdata_e_act_raw_normDist_T_598; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_600 = _activated_wdata_e_act_raw_normDist_T_578 ? 5'h10 : _activated_wdata_e_act_raw_normDist_T_599; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_601 = _activated_wdata_e_act_raw_normDist_T_579 ? 5'hF : _activated_wdata_e_act_raw_normDist_T_600; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_602 = _activated_wdata_e_act_raw_normDist_T_580 ? 5'hE : _activated_wdata_e_act_raw_normDist_T_601; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_603 = _activated_wdata_e_act_raw_normDist_T_581 ? 5'hD : _activated_wdata_e_act_raw_normDist_T_602; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_604 = _activated_wdata_e_act_raw_normDist_T_582 ? 5'hC : _activated_wdata_e_act_raw_normDist_T_603; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_605 = _activated_wdata_e_act_raw_normDist_T_583 ? 5'hB : _activated_wdata_e_act_raw_normDist_T_604; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_606 = _activated_wdata_e_act_raw_normDist_T_584 ? 5'hA : _activated_wdata_e_act_raw_normDist_T_605; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_607 = _activated_wdata_e_act_raw_normDist_T_585 ? 5'h9 : _activated_wdata_e_act_raw_normDist_T_606; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_608 = _activated_wdata_e_act_raw_normDist_T_586 ? 5'h8 : _activated_wdata_e_act_raw_normDist_T_607; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_609 = _activated_wdata_e_act_raw_normDist_T_587 ? 5'h7 : _activated_wdata_e_act_raw_normDist_T_608; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_610 = _activated_wdata_e_act_raw_normDist_T_588 ? 5'h6 : _activated_wdata_e_act_raw_normDist_T_609; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_611 = _activated_wdata_e_act_raw_normDist_T_589 ? 5'h5 : _activated_wdata_e_act_raw_normDist_T_610; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_612 = _activated_wdata_e_act_raw_normDist_T_590 ? 5'h4 : _activated_wdata_e_act_raw_normDist_T_611; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_613 = _activated_wdata_e_act_raw_normDist_T_591 ? 5'h3 : _activated_wdata_e_act_raw_normDist_T_612; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_614 = _activated_wdata_e_act_raw_normDist_T_592 ? 5'h2 : _activated_wdata_e_act_raw_normDist_T_613; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_615 = _activated_wdata_e_act_raw_normDist_T_593 ? 5'h1 : _activated_wdata_e_act_raw_normDist_T_614; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_act_raw_normDist_13 = _activated_wdata_e_act_raw_normDist_T_594 ? 5'h0 : _activated_wdata_e_act_raw_normDist_T_615; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_act_raw_subnormFract_T_26 = {31'h0, activated_wdata_e_act_raw_fractIn_13} << activated_wdata_e_act_raw_normDist_13; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_act_raw_subnormFract_T_27 = _activated_wdata_e_act_raw_subnormFract_T_26[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_act_raw_subnormFract_13 = {_activated_wdata_e_act_raw_subnormFract_T_27, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_65 = {4'hF, ~activated_wdata_e_act_raw_normDist_13}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_66 = activated_wdata_e_act_raw_isZeroExpIn_13 ? _activated_wdata_e_act_raw_adjustedExp_T_65 : {1'h0, activated_wdata_e_act_raw_expIn_13}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_act_raw_adjustedExp_T_67 = activated_wdata_e_act_raw_isZeroExpIn_13 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_act_raw_adjustedExp_T_68 = {6'h20, _activated_wdata_e_act_raw_adjustedExp_T_67}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_act_raw_adjustedExp_T_69 = {1'h0, _activated_wdata_e_act_raw_adjustedExp_T_66} + {2'h0, _activated_wdata_e_act_raw_adjustedExp_T_68}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_act_raw_adjustedExp_13 = _activated_wdata_e_act_raw_adjustedExp_T_69[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_act_raw_out_sExp_T_26 = activated_wdata_e_act_raw_adjustedExp_13; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_act_raw_isZero_13 = activated_wdata_e_act_raw_isZeroExpIn_13 & activated_wdata_e_act_raw_isZeroFractIn_13; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_act_raw_13_isZero = activated_wdata_e_act_raw_isZero_13; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_act_raw_isSpecial_T_13 = activated_wdata_e_act_raw_adjustedExp_13[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_act_raw_isSpecial_13 = &_activated_wdata_e_act_raw_isSpecial_T_13; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_act_raw_out_isNaN_T_27; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_act_raw_out_isInf_T_13; // @[rawFloatFromFN.scala:65:28]
wire [9:0] _activated_wdata_e_act_raw_out_sExp_T_27; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_act_raw_out_sig_T_55; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_act_raw_13_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_act_raw_13_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_act_raw_13_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_act_raw_13_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_raw_out_isNaN_T_26 = ~activated_wdata_e_act_raw_isZeroFractIn_13; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_act_raw_out_isNaN_T_27 = activated_wdata_e_act_raw_isSpecial_13 & _activated_wdata_e_act_raw_out_isNaN_T_26; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_act_raw_13_isNaN = _activated_wdata_e_act_raw_out_isNaN_T_27; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_act_raw_out_isInf_T_13 = activated_wdata_e_act_raw_isSpecial_13 & activated_wdata_e_act_raw_isZeroFractIn_13; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_act_raw_13_isInf = _activated_wdata_e_act_raw_out_isInf_T_13; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_act_raw_out_sExp_T_27 = {1'h0, _activated_wdata_e_act_raw_out_sExp_T_26}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_act_raw_13_sExp = _activated_wdata_e_act_raw_out_sExp_T_27; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_act_raw_out_sig_T_52 = ~activated_wdata_e_act_raw_isZero_13; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_act_raw_out_sig_T_53 = {1'h0, _activated_wdata_e_act_raw_out_sig_T_52}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_act_raw_out_sig_T_54 = activated_wdata_e_act_raw_isZeroExpIn_13 ? activated_wdata_e_act_raw_subnormFract_13 : activated_wdata_e_act_raw_fractIn_13; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_act_raw_out_sig_T_55 = {_activated_wdata_e_act_raw_out_sig_T_53, _activated_wdata_e_act_raw_out_sig_T_54}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_act_raw_13_sig = _activated_wdata_e_act_raw_out_sig_T_55; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [31:0] _activated_wdata_e_act_result_bits_T_41; // @[Arithmetic.scala:514:27]
wire [31:0] activated_wdata_e_act_result_13_bits; // @[Arithmetic.scala:513:26]
wire _activated_wdata_e_act_result_bits_T_39 = ~activated_wdata_e_act_raw_13_isZero; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_result_bits_T_40 = _activated_wdata_e_act_result_bits_T_39 & activated_wdata_e_act_raw_13_sign; // @[rawFloatFromFN.scala:63:19]
assign _activated_wdata_e_act_result_bits_T_41 = _activated_wdata_e_act_result_bits_T_40 ? 32'h0 : activated_wdata_e_clipped_13_bits; // @[Arithmetic.scala:505:26, :514:{27,40}]
assign activated_wdata_e_act_result_13_bits = _activated_wdata_e_act_result_bits_T_41; // @[Arithmetic.scala:513:26, :514:27]
wire [31:0] activated_wdata_e_act_13_bits = _activated_wdata_e_act_T_13 ? activated_wdata_e_act_result_13_bits : activated_wdata_e_clipped_13_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_wdata_WIRE_13_0_bits = activated_wdata_e_act_13_bits; // @[Mux.scala:126:16]
wire [31:0] activated_wdata_3_1_0_bits = _activated_wdata_WIRE_13_0_bits; // @[ExecuteController.scala:925:{34,74}]
wire activated_wdata_e_clipped_self_rec_rawIn_14_sign = activated_wdata_e_clipped_self_rec_rawIn_sign_14; // @[rawFloatFromFN.scala:44:18, :63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_14 = activated_wdata_e_clipped_self_rec_rawIn_expIn_14 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_14 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_616 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_617 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_618 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_619 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_620 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_621 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_622 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_623 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_624 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_625 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_626 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_627 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_628 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_629 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_630 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_631 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_632 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_633 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_634 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_635 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_636 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_637 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_638 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_14[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_639 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_617 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_640 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_618 ? 5'h14 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_639; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_641 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_619 ? 5'h13 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_640; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_642 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_620 ? 5'h12 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_641; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_643 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_621 ? 5'h11 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_642; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_644 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_622 ? 5'h10 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_643; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_645 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_623 ? 5'hF : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_644; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_646 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_624 ? 5'hE : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_645; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_647 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_625 ? 5'hD : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_646; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_648 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_626 ? 5'hC : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_647; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_649 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_627 ? 5'hB : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_648; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_650 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_628 ? 5'hA : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_649; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_651 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_629 ? 5'h9 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_650; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_652 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_630 ? 5'h8 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_651; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_653 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_631 ? 5'h7 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_652; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_654 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_632 ? 5'h6 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_653; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_655 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_633 ? 5'h5 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_654; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_656 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_634 ? 5'h4 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_655; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_657 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_635 ? 5'h3 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_656; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_658 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_636 ? 5'h2 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_657; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_659 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_637 ? 5'h1 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_658; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_clipped_self_rec_rawIn_normDist_14 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_638 ? 5'h0 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_659; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_28 = {31'h0, activated_wdata_e_clipped_self_rec_rawIn_fractIn_14} << activated_wdata_e_clipped_self_rec_rawIn_normDist_14; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_29 = _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_28[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_subnormFract_14 = {_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_29, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_70 = {4'hF, ~activated_wdata_e_clipped_self_rec_rawIn_normDist_14}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_71 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_14 ? _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_70 : {1'h0, activated_wdata_e_clipped_self_rec_rawIn_expIn_14}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_72 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_14 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_73 = {6'h20, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_72}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_74 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_71} + {2'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_73}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_14 = _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_74[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_28 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_14; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_clipped_self_rec_rawIn_isZero_14 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_14 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_14; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_clipped_self_rec_rawIn_14_isZero = activated_wdata_e_clipped_self_rec_rawIn_isZero_14; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_14 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_14[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_clipped_self_rec_rawIn_isSpecial_14 = &_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_14; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_29; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_14; // @[rawFloatFromFN.scala:65:28]
wire _activated_wdata_e_clipped_self_rec_T_114 = activated_wdata_e_clipped_self_rec_rawIn_14_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_29; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_59; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_clipped_self_rec_rawIn_14_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_clipped_self_rec_rawIn_14_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_clipped_self_rec_rawIn_14_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_28 = ~activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_14; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_29 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_14 & _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_28; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_clipped_self_rec_rawIn_14_isNaN = _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_29; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_14 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_14 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_14; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_clipped_self_rec_rawIn_14_isInf = _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_14; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_29 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_28}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_clipped_self_rec_rawIn_14_sExp = _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_29; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_56 = ~activated_wdata_e_clipped_self_rec_rawIn_isZero_14; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_57 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_56}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_58 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_14 ? activated_wdata_e_clipped_self_rec_rawIn_subnormFract_14 : activated_wdata_e_clipped_self_rec_rawIn_fractIn_14; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_59 = {_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_57, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_58}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_clipped_self_rec_rawIn_14_sig = _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_59; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_112 = activated_wdata_e_clipped_self_rec_rawIn_14_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_113 = activated_wdata_e_clipped_self_rec_rawIn_14_isZero ? 3'h0 : _activated_wdata_e_clipped_self_rec_T_112; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_115 = {_activated_wdata_e_clipped_self_rec_T_113[2:1], _activated_wdata_e_clipped_self_rec_T_113[0] | _activated_wdata_e_clipped_self_rec_T_114}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_wdata_e_clipped_self_rec_T_116 = {activated_wdata_e_clipped_self_rec_rawIn_14_sign, _activated_wdata_e_clipped_self_rec_T_115}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_wdata_e_clipped_self_rec_T_117 = activated_wdata_e_clipped_self_rec_rawIn_14_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_wdata_e_clipped_self_rec_T_118 = {_activated_wdata_e_clipped_self_rec_T_116, _activated_wdata_e_clipped_self_rec_T_117}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_wdata_e_clipped_self_rec_T_119 = activated_wdata_e_clipped_self_rec_rawIn_14_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_wdata_e_clipped_self_rec_14 = {_activated_wdata_e_clipped_self_rec_T_118, _activated_wdata_e_clipped_self_rec_T_119}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_wdata_e_clipped_result_bits_T_14; // @[fNFromRecFN.scala:66:12]
wire [31:0] activated_wdata_e_clipped_14_bits; // @[Arithmetic.scala:505:26]
wire [8:0] activated_wdata_e_clipped_result_bits_rawIn_exp_14 = _activated_wdata_e_clipped_resizer_14_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_14 = activated_wdata_e_clipped_result_bits_rawIn_exp_14[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isZero_14 = _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_14 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_wdata_e_clipped_result_bits_rawIn_14_isZero = activated_wdata_e_clipped_result_bits_rawIn_isZero_14; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_14 = activated_wdata_e_clipped_result_bits_rawIn_exp_14[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isSpecial_14 = &_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_14; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_29; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_44; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_14; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_14; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_59; // @[rawFloatFromRecFN.scala:61:44]
wire activated_wdata_e_clipped_result_bits_rawIn_14_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_14_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_14_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_wdata_e_clipped_result_bits_rawIn_14_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_wdata_e_clipped_result_bits_rawIn_14_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_28 = activated_wdata_e_clipped_result_bits_rawIn_exp_14[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_42 = activated_wdata_e_clipped_result_bits_rawIn_exp_14[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_29 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_14 & _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_28; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_wdata_e_clipped_result_bits_rawIn_14_isNaN = _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_29; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_43 = ~_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_42; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_44 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_14 & _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_43; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_wdata_e_clipped_result_bits_rawIn_14_isInf = _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_44; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_14 = _activated_wdata_e_clipped_resizer_14_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_wdata_e_clipped_result_bits_rawIn_14_sign = _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_14; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_14 = {1'h0, activated_wdata_e_clipped_result_bits_rawIn_exp_14}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_wdata_e_clipped_result_bits_rawIn_14_sExp = _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_14; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_56 = ~activated_wdata_e_clipped_result_bits_rawIn_isZero_14; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_57 = {1'h0, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_56}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_58 = _activated_wdata_e_clipped_resizer_14_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_59 = {_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_57, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_58}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_wdata_e_clipped_result_bits_rawIn_14_sig = _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_59; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire activated_wdata_e_clipped_result_bits_isSubnormal_14 = $signed(activated_wdata_e_clipped_result_bits_rawIn_14_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_28 = activated_wdata_e_clipped_result_bits_rawIn_14_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_29 = 6'h1 - {1'h0, _activated_wdata_e_clipped_result_bits_denormShiftDist_T_28}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] activated_wdata_e_clipped_result_bits_denormShiftDist_14 = _activated_wdata_e_clipped_result_bits_denormShiftDist_T_29[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_28 = activated_wdata_e_clipped_result_bits_rawIn_14_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_29 = _activated_wdata_e_clipped_result_bits_denormFract_T_28 >> activated_wdata_e_clipped_result_bits_denormShiftDist_14; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] activated_wdata_e_clipped_result_bits_denormFract_14 = _activated_wdata_e_clipped_result_bits_denormFract_T_29[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_84 = activated_wdata_e_clipped_result_bits_rawIn_14_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _activated_wdata_e_clipped_result_bits_expOut_T_85 = {1'h0, _activated_wdata_e_clipped_result_bits_expOut_T_84} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_86 = _activated_wdata_e_clipped_result_bits_expOut_T_85[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_87 = activated_wdata_e_clipped_result_bits_isSubnormal_14 ? 8'h0 : _activated_wdata_e_clipped_result_bits_expOut_T_86; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _activated_wdata_e_clipped_result_bits_expOut_T_88 = activated_wdata_e_clipped_result_bits_rawIn_14_isNaN | activated_wdata_e_clipped_result_bits_rawIn_14_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_89 = {8{_activated_wdata_e_clipped_result_bits_expOut_T_88}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] activated_wdata_e_clipped_result_bits_expOut_14 = _activated_wdata_e_clipped_result_bits_expOut_T_87 | _activated_wdata_e_clipped_result_bits_expOut_T_89; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_28 = activated_wdata_e_clipped_result_bits_rawIn_14_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_29 = activated_wdata_e_clipped_result_bits_rawIn_14_isInf ? 23'h0 : _activated_wdata_e_clipped_result_bits_fractOut_T_28; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] activated_wdata_e_clipped_result_bits_fractOut_14 = activated_wdata_e_clipped_result_bits_isSubnormal_14 ? activated_wdata_e_clipped_result_bits_denormFract_14 : _activated_wdata_e_clipped_result_bits_fractOut_T_29; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] activated_wdata_e_clipped_result_bits_hi_14 = {activated_wdata_e_clipped_result_bits_rawIn_14_sign, activated_wdata_e_clipped_result_bits_expOut_14}; // @[rawFloatFromRecFN.scala:55:23]
assign _activated_wdata_e_clipped_result_bits_T_14 = {activated_wdata_e_clipped_result_bits_hi_14, activated_wdata_e_clipped_result_bits_fractOut_14}; // @[fNFromRecFN.scala:62:16, :66:12]
assign activated_wdata_e_clipped_14_bits = _activated_wdata_e_clipped_result_bits_T_14; // @[fNFromRecFN.scala:66:12]
wire activated_wdata_e_act_raw_sign_14 = activated_wdata_e_clipped_14_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_act_raw_14_sign = activated_wdata_e_act_raw_sign_14; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_wdata_e_act_raw_expIn_14 = activated_wdata_e_clipped_14_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_wdata_e_act_raw_fractIn_14 = activated_wdata_e_clipped_14_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_wdata_e_act_raw_isZeroExpIn_14 = activated_wdata_e_act_raw_expIn_14 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_act_raw_isZeroFractIn_14 = activated_wdata_e_act_raw_fractIn_14 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_act_raw_normDist_T_616 = activated_wdata_e_act_raw_fractIn_14[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_617 = activated_wdata_e_act_raw_fractIn_14[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_618 = activated_wdata_e_act_raw_fractIn_14[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_619 = activated_wdata_e_act_raw_fractIn_14[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_620 = activated_wdata_e_act_raw_fractIn_14[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_621 = activated_wdata_e_act_raw_fractIn_14[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_622 = activated_wdata_e_act_raw_fractIn_14[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_623 = activated_wdata_e_act_raw_fractIn_14[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_624 = activated_wdata_e_act_raw_fractIn_14[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_625 = activated_wdata_e_act_raw_fractIn_14[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_626 = activated_wdata_e_act_raw_fractIn_14[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_627 = activated_wdata_e_act_raw_fractIn_14[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_628 = activated_wdata_e_act_raw_fractIn_14[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_629 = activated_wdata_e_act_raw_fractIn_14[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_630 = activated_wdata_e_act_raw_fractIn_14[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_631 = activated_wdata_e_act_raw_fractIn_14[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_632 = activated_wdata_e_act_raw_fractIn_14[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_633 = activated_wdata_e_act_raw_fractIn_14[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_634 = activated_wdata_e_act_raw_fractIn_14[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_635 = activated_wdata_e_act_raw_fractIn_14[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_636 = activated_wdata_e_act_raw_fractIn_14[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_637 = activated_wdata_e_act_raw_fractIn_14[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_638 = activated_wdata_e_act_raw_fractIn_14[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_639 = _activated_wdata_e_act_raw_normDist_T_617 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_640 = _activated_wdata_e_act_raw_normDist_T_618 ? 5'h14 : _activated_wdata_e_act_raw_normDist_T_639; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_641 = _activated_wdata_e_act_raw_normDist_T_619 ? 5'h13 : _activated_wdata_e_act_raw_normDist_T_640; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_642 = _activated_wdata_e_act_raw_normDist_T_620 ? 5'h12 : _activated_wdata_e_act_raw_normDist_T_641; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_643 = _activated_wdata_e_act_raw_normDist_T_621 ? 5'h11 : _activated_wdata_e_act_raw_normDist_T_642; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_644 = _activated_wdata_e_act_raw_normDist_T_622 ? 5'h10 : _activated_wdata_e_act_raw_normDist_T_643; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_645 = _activated_wdata_e_act_raw_normDist_T_623 ? 5'hF : _activated_wdata_e_act_raw_normDist_T_644; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_646 = _activated_wdata_e_act_raw_normDist_T_624 ? 5'hE : _activated_wdata_e_act_raw_normDist_T_645; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_647 = _activated_wdata_e_act_raw_normDist_T_625 ? 5'hD : _activated_wdata_e_act_raw_normDist_T_646; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_648 = _activated_wdata_e_act_raw_normDist_T_626 ? 5'hC : _activated_wdata_e_act_raw_normDist_T_647; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_649 = _activated_wdata_e_act_raw_normDist_T_627 ? 5'hB : _activated_wdata_e_act_raw_normDist_T_648; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_650 = _activated_wdata_e_act_raw_normDist_T_628 ? 5'hA : _activated_wdata_e_act_raw_normDist_T_649; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_651 = _activated_wdata_e_act_raw_normDist_T_629 ? 5'h9 : _activated_wdata_e_act_raw_normDist_T_650; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_652 = _activated_wdata_e_act_raw_normDist_T_630 ? 5'h8 : _activated_wdata_e_act_raw_normDist_T_651; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_653 = _activated_wdata_e_act_raw_normDist_T_631 ? 5'h7 : _activated_wdata_e_act_raw_normDist_T_652; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_654 = _activated_wdata_e_act_raw_normDist_T_632 ? 5'h6 : _activated_wdata_e_act_raw_normDist_T_653; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_655 = _activated_wdata_e_act_raw_normDist_T_633 ? 5'h5 : _activated_wdata_e_act_raw_normDist_T_654; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_656 = _activated_wdata_e_act_raw_normDist_T_634 ? 5'h4 : _activated_wdata_e_act_raw_normDist_T_655; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_657 = _activated_wdata_e_act_raw_normDist_T_635 ? 5'h3 : _activated_wdata_e_act_raw_normDist_T_656; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_658 = _activated_wdata_e_act_raw_normDist_T_636 ? 5'h2 : _activated_wdata_e_act_raw_normDist_T_657; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_659 = _activated_wdata_e_act_raw_normDist_T_637 ? 5'h1 : _activated_wdata_e_act_raw_normDist_T_658; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_act_raw_normDist_14 = _activated_wdata_e_act_raw_normDist_T_638 ? 5'h0 : _activated_wdata_e_act_raw_normDist_T_659; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_act_raw_subnormFract_T_28 = {31'h0, activated_wdata_e_act_raw_fractIn_14} << activated_wdata_e_act_raw_normDist_14; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_act_raw_subnormFract_T_29 = _activated_wdata_e_act_raw_subnormFract_T_28[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_act_raw_subnormFract_14 = {_activated_wdata_e_act_raw_subnormFract_T_29, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_70 = {4'hF, ~activated_wdata_e_act_raw_normDist_14}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_71 = activated_wdata_e_act_raw_isZeroExpIn_14 ? _activated_wdata_e_act_raw_adjustedExp_T_70 : {1'h0, activated_wdata_e_act_raw_expIn_14}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_act_raw_adjustedExp_T_72 = activated_wdata_e_act_raw_isZeroExpIn_14 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_act_raw_adjustedExp_T_73 = {6'h20, _activated_wdata_e_act_raw_adjustedExp_T_72}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_act_raw_adjustedExp_T_74 = {1'h0, _activated_wdata_e_act_raw_adjustedExp_T_71} + {2'h0, _activated_wdata_e_act_raw_adjustedExp_T_73}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_act_raw_adjustedExp_14 = _activated_wdata_e_act_raw_adjustedExp_T_74[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_act_raw_out_sExp_T_28 = activated_wdata_e_act_raw_adjustedExp_14; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_act_raw_isZero_14 = activated_wdata_e_act_raw_isZeroExpIn_14 & activated_wdata_e_act_raw_isZeroFractIn_14; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_act_raw_14_isZero = activated_wdata_e_act_raw_isZero_14; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_act_raw_isSpecial_T_14 = activated_wdata_e_act_raw_adjustedExp_14[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_act_raw_isSpecial_14 = &_activated_wdata_e_act_raw_isSpecial_T_14; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_act_raw_out_isNaN_T_29; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_act_raw_out_isInf_T_14; // @[rawFloatFromFN.scala:65:28]
wire [9:0] _activated_wdata_e_act_raw_out_sExp_T_29; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_act_raw_out_sig_T_59; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_act_raw_14_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_act_raw_14_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_act_raw_14_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_act_raw_14_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_raw_out_isNaN_T_28 = ~activated_wdata_e_act_raw_isZeroFractIn_14; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_act_raw_out_isNaN_T_29 = activated_wdata_e_act_raw_isSpecial_14 & _activated_wdata_e_act_raw_out_isNaN_T_28; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_act_raw_14_isNaN = _activated_wdata_e_act_raw_out_isNaN_T_29; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_act_raw_out_isInf_T_14 = activated_wdata_e_act_raw_isSpecial_14 & activated_wdata_e_act_raw_isZeroFractIn_14; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_act_raw_14_isInf = _activated_wdata_e_act_raw_out_isInf_T_14; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_act_raw_out_sExp_T_29 = {1'h0, _activated_wdata_e_act_raw_out_sExp_T_28}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_act_raw_14_sExp = _activated_wdata_e_act_raw_out_sExp_T_29; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_act_raw_out_sig_T_56 = ~activated_wdata_e_act_raw_isZero_14; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_act_raw_out_sig_T_57 = {1'h0, _activated_wdata_e_act_raw_out_sig_T_56}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_act_raw_out_sig_T_58 = activated_wdata_e_act_raw_isZeroExpIn_14 ? activated_wdata_e_act_raw_subnormFract_14 : activated_wdata_e_act_raw_fractIn_14; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_act_raw_out_sig_T_59 = {_activated_wdata_e_act_raw_out_sig_T_57, _activated_wdata_e_act_raw_out_sig_T_58}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_act_raw_14_sig = _activated_wdata_e_act_raw_out_sig_T_59; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [31:0] _activated_wdata_e_act_result_bits_T_44; // @[Arithmetic.scala:514:27]
wire [31:0] activated_wdata_e_act_result_14_bits; // @[Arithmetic.scala:513:26]
wire _activated_wdata_e_act_result_bits_T_42 = ~activated_wdata_e_act_raw_14_isZero; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_result_bits_T_43 = _activated_wdata_e_act_result_bits_T_42 & activated_wdata_e_act_raw_14_sign; // @[rawFloatFromFN.scala:63:19]
assign _activated_wdata_e_act_result_bits_T_44 = _activated_wdata_e_act_result_bits_T_43 ? 32'h0 : activated_wdata_e_clipped_14_bits; // @[Arithmetic.scala:505:26, :514:{27,40}]
assign activated_wdata_e_act_result_14_bits = _activated_wdata_e_act_result_bits_T_44; // @[Arithmetic.scala:513:26, :514:27]
wire [31:0] activated_wdata_e_act_14_bits = _activated_wdata_e_act_T_14 ? activated_wdata_e_act_result_14_bits : activated_wdata_e_clipped_14_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_wdata_WIRE_14_0_bits = activated_wdata_e_act_14_bits; // @[Mux.scala:126:16]
wire [31:0] activated_wdata_3_2_0_bits = _activated_wdata_WIRE_14_0_bits; // @[ExecuteController.scala:925:{34,74}]
wire activated_wdata_e_clipped_self_rec_rawIn_15_sign = activated_wdata_e_clipped_self_rec_rawIn_sign_15; // @[rawFloatFromFN.scala:44:18, :63:19]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_15 = activated_wdata_e_clipped_self_rec_rawIn_expIn_15 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_15 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_660 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_661 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_662 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_663 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_664 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_665 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_666 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_667 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_668 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_669 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_670 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_671 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_672 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_673 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_674 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_675 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_676 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_677 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_678 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_679 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_680 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_681 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_682 = activated_wdata_e_clipped_self_rec_rawIn_fractIn_15[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_683 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_661 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_684 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_662 ? 5'h14 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_683; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_685 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_663 ? 5'h13 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_684; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_686 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_664 ? 5'h12 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_685; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_687 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_665 ? 5'h11 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_686; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_688 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_666 ? 5'h10 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_687; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_689 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_667 ? 5'hF : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_688; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_690 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_668 ? 5'hE : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_689; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_691 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_669 ? 5'hD : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_690; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_692 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_670 ? 5'hC : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_691; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_693 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_671 ? 5'hB : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_692; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_694 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_672 ? 5'hA : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_693; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_695 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_673 ? 5'h9 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_694; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_696 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_674 ? 5'h8 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_695; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_697 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_675 ? 5'h7 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_696; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_698 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_676 ? 5'h6 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_697; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_699 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_677 ? 5'h5 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_698; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_700 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_678 ? 5'h4 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_699; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_701 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_679 ? 5'h3 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_700; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_702 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_680 ? 5'h2 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_701; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_703 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_681 ? 5'h1 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_702; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_clipped_self_rec_rawIn_normDist_15 = _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_682 ? 5'h0 : _activated_wdata_e_clipped_self_rec_rawIn_normDist_T_703; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_30 = {31'h0, activated_wdata_e_clipped_self_rec_rawIn_fractIn_15} << activated_wdata_e_clipped_self_rec_rawIn_normDist_15; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_31 = _activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_30[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_clipped_self_rec_rawIn_subnormFract_15 = {_activated_wdata_e_clipped_self_rec_rawIn_subnormFract_T_31, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_75 = {4'hF, ~activated_wdata_e_clipped_self_rec_rawIn_normDist_15}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_76 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_15 ? _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_75 : {1'h0, activated_wdata_e_clipped_self_rec_rawIn_expIn_15}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_77 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_15 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_78 = {6'h20, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_77}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_79 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_76} + {2'h0, _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_78}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_15 = _activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_T_79[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_30 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_15; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_clipped_self_rec_rawIn_isZero_15 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_15 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_15; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_clipped_self_rec_rawIn_15_isZero = activated_wdata_e_clipped_self_rec_rawIn_isZero_15; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_15 = activated_wdata_e_clipped_self_rec_rawIn_adjustedExp_15[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_clipped_self_rec_rawIn_isSpecial_15 = &_activated_wdata_e_clipped_self_rec_rawIn_isSpecial_T_15; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_31; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_15; // @[rawFloatFromFN.scala:65:28]
wire _activated_wdata_e_clipped_self_rec_T_122 = activated_wdata_e_clipped_self_rec_rawIn_15_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_31; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_63; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_clipped_self_rec_rawIn_15_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_clipped_self_rec_rawIn_15_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_clipped_self_rec_rawIn_15_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_30 = ~activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_15; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_31 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_15 & _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_30; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_clipped_self_rec_rawIn_15_isNaN = _activated_wdata_e_clipped_self_rec_rawIn_out_isNaN_T_31; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_15 = activated_wdata_e_clipped_self_rec_rawIn_isSpecial_15 & activated_wdata_e_clipped_self_rec_rawIn_isZeroFractIn_15; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_clipped_self_rec_rawIn_15_isInf = _activated_wdata_e_clipped_self_rec_rawIn_out_isInf_T_15; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_31 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_30}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_clipped_self_rec_rawIn_15_sExp = _activated_wdata_e_clipped_self_rec_rawIn_out_sExp_T_31; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_60 = ~activated_wdata_e_clipped_self_rec_rawIn_isZero_15; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_61 = {1'h0, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_60}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_62 = activated_wdata_e_clipped_self_rec_rawIn_isZeroExpIn_15 ? activated_wdata_e_clipped_self_rec_rawIn_subnormFract_15 : activated_wdata_e_clipped_self_rec_rawIn_fractIn_15; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_63 = {_activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_61, _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_62}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_clipped_self_rec_rawIn_15_sig = _activated_wdata_e_clipped_self_rec_rawIn_out_sig_T_63; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_120 = activated_wdata_e_clipped_self_rec_rawIn_15_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_121 = activated_wdata_e_clipped_self_rec_rawIn_15_isZero ? 3'h0 : _activated_wdata_e_clipped_self_rec_T_120; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_wdata_e_clipped_self_rec_T_123 = {_activated_wdata_e_clipped_self_rec_T_121[2:1], _activated_wdata_e_clipped_self_rec_T_121[0] | _activated_wdata_e_clipped_self_rec_T_122}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_wdata_e_clipped_self_rec_T_124 = {activated_wdata_e_clipped_self_rec_rawIn_15_sign, _activated_wdata_e_clipped_self_rec_T_123}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_wdata_e_clipped_self_rec_T_125 = activated_wdata_e_clipped_self_rec_rawIn_15_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_wdata_e_clipped_self_rec_T_126 = {_activated_wdata_e_clipped_self_rec_T_124, _activated_wdata_e_clipped_self_rec_T_125}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_wdata_e_clipped_self_rec_T_127 = activated_wdata_e_clipped_self_rec_rawIn_15_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_wdata_e_clipped_self_rec_15 = {_activated_wdata_e_clipped_self_rec_T_126, _activated_wdata_e_clipped_self_rec_T_127}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_wdata_e_clipped_result_bits_T_15; // @[fNFromRecFN.scala:66:12]
wire [31:0] activated_wdata_e_clipped_15_bits; // @[Arithmetic.scala:505:26]
wire [8:0] activated_wdata_e_clipped_result_bits_rawIn_exp_15 = _activated_wdata_e_clipped_resizer_15_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_15 = activated_wdata_e_clipped_result_bits_rawIn_exp_15[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isZero_15 = _activated_wdata_e_clipped_result_bits_rawIn_isZero_T_15 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_wdata_e_clipped_result_bits_rawIn_15_isZero = activated_wdata_e_clipped_result_bits_rawIn_isZero_15; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_15 = activated_wdata_e_clipped_result_bits_rawIn_exp_15[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_wdata_e_clipped_result_bits_rawIn_isSpecial_15 = &_activated_wdata_e_clipped_result_bits_rawIn_isSpecial_T_15; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_31; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_47; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_15; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_15; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_63; // @[rawFloatFromRecFN.scala:61:44]
wire activated_wdata_e_clipped_result_bits_rawIn_15_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_15_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_wdata_e_clipped_result_bits_rawIn_15_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_wdata_e_clipped_result_bits_rawIn_15_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_wdata_e_clipped_result_bits_rawIn_15_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_30 = activated_wdata_e_clipped_result_bits_rawIn_exp_15[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_45 = activated_wdata_e_clipped_result_bits_rawIn_exp_15[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_31 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_15 & _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_30; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_wdata_e_clipped_result_bits_rawIn_15_isNaN = _activated_wdata_e_clipped_result_bits_rawIn_out_isNaN_T_31; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_46 = ~_activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_45; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_47 = activated_wdata_e_clipped_result_bits_rawIn_isSpecial_15 & _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_46; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_wdata_e_clipped_result_bits_rawIn_15_isInf = _activated_wdata_e_clipped_result_bits_rawIn_out_isInf_T_47; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_15 = _activated_wdata_e_clipped_resizer_15_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_wdata_e_clipped_result_bits_rawIn_15_sign = _activated_wdata_e_clipped_result_bits_rawIn_out_sign_T_15; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_15 = {1'h0, activated_wdata_e_clipped_result_bits_rawIn_exp_15}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_wdata_e_clipped_result_bits_rawIn_15_sExp = _activated_wdata_e_clipped_result_bits_rawIn_out_sExp_T_15; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_60 = ~activated_wdata_e_clipped_result_bits_rawIn_isZero_15; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_61 = {1'h0, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_60}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_62 = _activated_wdata_e_clipped_resizer_15_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_63 = {_activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_61, _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_62}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_wdata_e_clipped_result_bits_rawIn_15_sig = _activated_wdata_e_clipped_result_bits_rawIn_out_sig_T_63; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire activated_wdata_e_clipped_result_bits_isSubnormal_15 = $signed(activated_wdata_e_clipped_result_bits_rawIn_15_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_30 = activated_wdata_e_clipped_result_bits_rawIn_15_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _activated_wdata_e_clipped_result_bits_denormShiftDist_T_31 = 6'h1 - {1'h0, _activated_wdata_e_clipped_result_bits_denormShiftDist_T_30}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] activated_wdata_e_clipped_result_bits_denormShiftDist_15 = _activated_wdata_e_clipped_result_bits_denormShiftDist_T_31[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_30 = activated_wdata_e_clipped_result_bits_rawIn_15_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _activated_wdata_e_clipped_result_bits_denormFract_T_31 = _activated_wdata_e_clipped_result_bits_denormFract_T_30 >> activated_wdata_e_clipped_result_bits_denormShiftDist_15; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] activated_wdata_e_clipped_result_bits_denormFract_15 = _activated_wdata_e_clipped_result_bits_denormFract_T_31[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_90 = activated_wdata_e_clipped_result_bits_rawIn_15_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _activated_wdata_e_clipped_result_bits_expOut_T_91 = {1'h0, _activated_wdata_e_clipped_result_bits_expOut_T_90} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_92 = _activated_wdata_e_clipped_result_bits_expOut_T_91[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_93 = activated_wdata_e_clipped_result_bits_isSubnormal_15 ? 8'h0 : _activated_wdata_e_clipped_result_bits_expOut_T_92; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _activated_wdata_e_clipped_result_bits_expOut_T_94 = activated_wdata_e_clipped_result_bits_rawIn_15_isNaN | activated_wdata_e_clipped_result_bits_rawIn_15_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _activated_wdata_e_clipped_result_bits_expOut_T_95 = {8{_activated_wdata_e_clipped_result_bits_expOut_T_94}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] activated_wdata_e_clipped_result_bits_expOut_15 = _activated_wdata_e_clipped_result_bits_expOut_T_93 | _activated_wdata_e_clipped_result_bits_expOut_T_95; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_30 = activated_wdata_e_clipped_result_bits_rawIn_15_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _activated_wdata_e_clipped_result_bits_fractOut_T_31 = activated_wdata_e_clipped_result_bits_rawIn_15_isInf ? 23'h0 : _activated_wdata_e_clipped_result_bits_fractOut_T_30; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] activated_wdata_e_clipped_result_bits_fractOut_15 = activated_wdata_e_clipped_result_bits_isSubnormal_15 ? activated_wdata_e_clipped_result_bits_denormFract_15 : _activated_wdata_e_clipped_result_bits_fractOut_T_31; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] activated_wdata_e_clipped_result_bits_hi_15 = {activated_wdata_e_clipped_result_bits_rawIn_15_sign, activated_wdata_e_clipped_result_bits_expOut_15}; // @[rawFloatFromRecFN.scala:55:23]
assign _activated_wdata_e_clipped_result_bits_T_15 = {activated_wdata_e_clipped_result_bits_hi_15, activated_wdata_e_clipped_result_bits_fractOut_15}; // @[fNFromRecFN.scala:62:16, :66:12]
assign activated_wdata_e_clipped_15_bits = _activated_wdata_e_clipped_result_bits_T_15; // @[fNFromRecFN.scala:66:12]
wire activated_wdata_e_act_raw_sign_15 = activated_wdata_e_clipped_15_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_wdata_e_act_raw_15_sign = activated_wdata_e_act_raw_sign_15; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_wdata_e_act_raw_expIn_15 = activated_wdata_e_clipped_15_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_wdata_e_act_raw_fractIn_15 = activated_wdata_e_clipped_15_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_wdata_e_act_raw_isZeroExpIn_15 = activated_wdata_e_act_raw_expIn_15 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_wdata_e_act_raw_isZeroFractIn_15 = activated_wdata_e_act_raw_fractIn_15 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_wdata_e_act_raw_normDist_T_660 = activated_wdata_e_act_raw_fractIn_15[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_661 = activated_wdata_e_act_raw_fractIn_15[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_662 = activated_wdata_e_act_raw_fractIn_15[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_663 = activated_wdata_e_act_raw_fractIn_15[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_664 = activated_wdata_e_act_raw_fractIn_15[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_665 = activated_wdata_e_act_raw_fractIn_15[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_666 = activated_wdata_e_act_raw_fractIn_15[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_667 = activated_wdata_e_act_raw_fractIn_15[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_668 = activated_wdata_e_act_raw_fractIn_15[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_669 = activated_wdata_e_act_raw_fractIn_15[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_670 = activated_wdata_e_act_raw_fractIn_15[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_671 = activated_wdata_e_act_raw_fractIn_15[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_672 = activated_wdata_e_act_raw_fractIn_15[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_673 = activated_wdata_e_act_raw_fractIn_15[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_674 = activated_wdata_e_act_raw_fractIn_15[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_675 = activated_wdata_e_act_raw_fractIn_15[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_676 = activated_wdata_e_act_raw_fractIn_15[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_677 = activated_wdata_e_act_raw_fractIn_15[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_678 = activated_wdata_e_act_raw_fractIn_15[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_679 = activated_wdata_e_act_raw_fractIn_15[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_680 = activated_wdata_e_act_raw_fractIn_15[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_681 = activated_wdata_e_act_raw_fractIn_15[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_wdata_e_act_raw_normDist_T_682 = activated_wdata_e_act_raw_fractIn_15[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_683 = _activated_wdata_e_act_raw_normDist_T_661 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_684 = _activated_wdata_e_act_raw_normDist_T_662 ? 5'h14 : _activated_wdata_e_act_raw_normDist_T_683; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_685 = _activated_wdata_e_act_raw_normDist_T_663 ? 5'h13 : _activated_wdata_e_act_raw_normDist_T_684; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_686 = _activated_wdata_e_act_raw_normDist_T_664 ? 5'h12 : _activated_wdata_e_act_raw_normDist_T_685; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_687 = _activated_wdata_e_act_raw_normDist_T_665 ? 5'h11 : _activated_wdata_e_act_raw_normDist_T_686; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_688 = _activated_wdata_e_act_raw_normDist_T_666 ? 5'h10 : _activated_wdata_e_act_raw_normDist_T_687; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_689 = _activated_wdata_e_act_raw_normDist_T_667 ? 5'hF : _activated_wdata_e_act_raw_normDist_T_688; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_690 = _activated_wdata_e_act_raw_normDist_T_668 ? 5'hE : _activated_wdata_e_act_raw_normDist_T_689; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_691 = _activated_wdata_e_act_raw_normDist_T_669 ? 5'hD : _activated_wdata_e_act_raw_normDist_T_690; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_692 = _activated_wdata_e_act_raw_normDist_T_670 ? 5'hC : _activated_wdata_e_act_raw_normDist_T_691; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_693 = _activated_wdata_e_act_raw_normDist_T_671 ? 5'hB : _activated_wdata_e_act_raw_normDist_T_692; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_694 = _activated_wdata_e_act_raw_normDist_T_672 ? 5'hA : _activated_wdata_e_act_raw_normDist_T_693; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_695 = _activated_wdata_e_act_raw_normDist_T_673 ? 5'h9 : _activated_wdata_e_act_raw_normDist_T_694; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_696 = _activated_wdata_e_act_raw_normDist_T_674 ? 5'h8 : _activated_wdata_e_act_raw_normDist_T_695; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_697 = _activated_wdata_e_act_raw_normDist_T_675 ? 5'h7 : _activated_wdata_e_act_raw_normDist_T_696; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_698 = _activated_wdata_e_act_raw_normDist_T_676 ? 5'h6 : _activated_wdata_e_act_raw_normDist_T_697; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_699 = _activated_wdata_e_act_raw_normDist_T_677 ? 5'h5 : _activated_wdata_e_act_raw_normDist_T_698; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_700 = _activated_wdata_e_act_raw_normDist_T_678 ? 5'h4 : _activated_wdata_e_act_raw_normDist_T_699; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_701 = _activated_wdata_e_act_raw_normDist_T_679 ? 5'h3 : _activated_wdata_e_act_raw_normDist_T_700; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_702 = _activated_wdata_e_act_raw_normDist_T_680 ? 5'h2 : _activated_wdata_e_act_raw_normDist_T_701; // @[Mux.scala:50:70]
wire [4:0] _activated_wdata_e_act_raw_normDist_T_703 = _activated_wdata_e_act_raw_normDist_T_681 ? 5'h1 : _activated_wdata_e_act_raw_normDist_T_702; // @[Mux.scala:50:70]
wire [4:0] activated_wdata_e_act_raw_normDist_15 = _activated_wdata_e_act_raw_normDist_T_682 ? 5'h0 : _activated_wdata_e_act_raw_normDist_T_703; // @[Mux.scala:50:70]
wire [53:0] _activated_wdata_e_act_raw_subnormFract_T_30 = {31'h0, activated_wdata_e_act_raw_fractIn_15} << activated_wdata_e_act_raw_normDist_15; // @[Mux.scala:50:70]
wire [21:0] _activated_wdata_e_act_raw_subnormFract_T_31 = _activated_wdata_e_act_raw_subnormFract_T_30[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_wdata_e_act_raw_subnormFract_15 = {_activated_wdata_e_act_raw_subnormFract_T_31, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_75 = {4'hF, ~activated_wdata_e_act_raw_normDist_15}; // @[Mux.scala:50:70]
wire [8:0] _activated_wdata_e_act_raw_adjustedExp_T_76 = activated_wdata_e_act_raw_isZeroExpIn_15 ? _activated_wdata_e_act_raw_adjustedExp_T_75 : {1'h0, activated_wdata_e_act_raw_expIn_15}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_wdata_e_act_raw_adjustedExp_T_77 = activated_wdata_e_act_raw_isZeroExpIn_15 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_wdata_e_act_raw_adjustedExp_T_78 = {6'h20, _activated_wdata_e_act_raw_adjustedExp_T_77}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_wdata_e_act_raw_adjustedExp_T_79 = {1'h0, _activated_wdata_e_act_raw_adjustedExp_T_76} + {2'h0, _activated_wdata_e_act_raw_adjustedExp_T_78}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_wdata_e_act_raw_adjustedExp_15 = _activated_wdata_e_act_raw_adjustedExp_T_79[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_wdata_e_act_raw_out_sExp_T_30 = activated_wdata_e_act_raw_adjustedExp_15; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_wdata_e_act_raw_isZero_15 = activated_wdata_e_act_raw_isZeroExpIn_15 & activated_wdata_e_act_raw_isZeroFractIn_15; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_wdata_e_act_raw_15_isZero = activated_wdata_e_act_raw_isZero_15; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_wdata_e_act_raw_isSpecial_T_15 = activated_wdata_e_act_raw_adjustedExp_15[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_wdata_e_act_raw_isSpecial_15 = &_activated_wdata_e_act_raw_isSpecial_T_15; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_wdata_e_act_raw_out_isNaN_T_31; // @[rawFloatFromFN.scala:64:28]
wire _activated_wdata_e_act_raw_out_isInf_T_15; // @[rawFloatFromFN.scala:65:28]
wire [9:0] _activated_wdata_e_act_raw_out_sExp_T_31; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_wdata_e_act_raw_out_sig_T_63; // @[rawFloatFromFN.scala:70:27]
wire activated_wdata_e_act_raw_15_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_wdata_e_act_raw_15_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_wdata_e_act_raw_15_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_wdata_e_act_raw_15_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_raw_out_isNaN_T_30 = ~activated_wdata_e_act_raw_isZeroFractIn_15; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_wdata_e_act_raw_out_isNaN_T_31 = activated_wdata_e_act_raw_isSpecial_15 & _activated_wdata_e_act_raw_out_isNaN_T_30; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_wdata_e_act_raw_15_isNaN = _activated_wdata_e_act_raw_out_isNaN_T_31; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_wdata_e_act_raw_out_isInf_T_15 = activated_wdata_e_act_raw_isSpecial_15 & activated_wdata_e_act_raw_isZeroFractIn_15; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_wdata_e_act_raw_15_isInf = _activated_wdata_e_act_raw_out_isInf_T_15; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_wdata_e_act_raw_out_sExp_T_31 = {1'h0, _activated_wdata_e_act_raw_out_sExp_T_30}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_wdata_e_act_raw_15_sExp = _activated_wdata_e_act_raw_out_sExp_T_31; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_wdata_e_act_raw_out_sig_T_60 = ~activated_wdata_e_act_raw_isZero_15; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_wdata_e_act_raw_out_sig_T_61 = {1'h0, _activated_wdata_e_act_raw_out_sig_T_60}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_wdata_e_act_raw_out_sig_T_62 = activated_wdata_e_act_raw_isZeroExpIn_15 ? activated_wdata_e_act_raw_subnormFract_15 : activated_wdata_e_act_raw_fractIn_15; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_wdata_e_act_raw_out_sig_T_63 = {_activated_wdata_e_act_raw_out_sig_T_61, _activated_wdata_e_act_raw_out_sig_T_62}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_wdata_e_act_raw_15_sig = _activated_wdata_e_act_raw_out_sig_T_63; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [31:0] _activated_wdata_e_act_result_bits_T_47; // @[Arithmetic.scala:514:27]
wire [31:0] activated_wdata_e_act_result_15_bits; // @[Arithmetic.scala:513:26]
wire _activated_wdata_e_act_result_bits_T_45 = ~activated_wdata_e_act_raw_15_isZero; // @[rawFloatFromFN.scala:63:19]
wire _activated_wdata_e_act_result_bits_T_46 = _activated_wdata_e_act_result_bits_T_45 & activated_wdata_e_act_raw_15_sign; // @[rawFloatFromFN.scala:63:19]
assign _activated_wdata_e_act_result_bits_T_47 = _activated_wdata_e_act_result_bits_T_46 ? 32'h0 : activated_wdata_e_clipped_15_bits; // @[Arithmetic.scala:505:26, :514:{27,40}]
assign activated_wdata_e_act_result_15_bits = _activated_wdata_e_act_result_bits_T_47; // @[Arithmetic.scala:513:26, :514:27]
wire [31:0] activated_wdata_e_act_15_bits = _activated_wdata_e_act_T_15 ? activated_wdata_e_act_result_15_bits : activated_wdata_e_clipped_15_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_wdata_WIRE_15_0_bits = activated_wdata_e_act_15_bits; // @[Mux.scala:126:16]
wire [31:0] activated_wdata_3_3_0_bits = _activated_wdata_WIRE_15_0_bits; // @[ExecuteController.scala:925:{34,74}]
wire _io_srams_write_3_en_T = &w_bank; // @[ExecuteController.scala:911:19, :934:64]
wire _io_srams_write_3_en_T_1 = start_array_outputting & _io_srams_write_3_en_T; // @[ExecuteController.scala:270:40, :934:{54,64}]
wire _io_srams_write_3_en_T_2 = ~w_address_is_acc_addr; // @[ExecuteController.scala:907:22, :934:75]
wire _io_srams_write_3_en_T_3 = _io_srams_write_3_en_T_1 & _io_srams_write_3_en_T_2; // @[ExecuteController.scala:934:{54,72,75}]
wire _io_srams_write_3_en_T_4 = ~is_garbage_addr; // @[LocalAddr.scala:43:96]
wire _io_srams_write_3_en_T_5 = _io_srams_write_3_en_T_3 & _io_srams_write_3_en_T_4; // @[ExecuteController.scala:934:{72,89,92}]
assign _io_srams_write_3_en_T_6 = _io_srams_write_3_en_T_5 & write_this_row; // @[ExecuteController.scala:919:27, :934:{89,109}]
assign io_srams_write_3_en_0 = _io_srams_write_3_en_T_6; // @[ExecuteController.scala:12:7, :934:109]
wire [63:0] io_srams_write_3_data_lo = {activated_wdata_3_1_0_bits, activated_wdata_3_0_0_bits}; // @[ExecuteController.scala:925:34, :936:49]
wire [63:0] io_srams_write_3_data_hi = {activated_wdata_3_3_0_bits, activated_wdata_3_2_0_bits}; // @[ExecuteController.scala:925:34, :936:49]
assign _io_srams_write_3_data_T = {io_srams_write_3_data_hi, io_srams_write_3_data_lo}; // @[ExecuteController.scala:936:49]
assign io_srams_write_3_data_0 = _io_srams_write_3_data_T; // @[ExecuteController.scala:12:7, :936:49]
wire _io_acc_write_0_valid_T_1 = start_array_outputting & _io_acc_write_0_valid_T; // @[ExecuteController.scala:270:40, :949:{55,65}]
wire _io_acc_write_0_valid_T_2 = _io_acc_write_0_valid_T_1 & w_address_is_acc_addr; // @[ExecuteController.scala:907:22, :949:{55,73}]
wire _io_acc_write_0_valid_T_3 = ~is_garbage_addr; // @[LocalAddr.scala:43:96]
wire _io_acc_write_0_valid_T_4 = _io_acc_write_0_valid_T_2 & _io_acc_write_0_valid_T_3; // @[ExecuteController.scala:949:{73,89,92}]
assign _io_acc_write_0_valid_T_5 = _io_acc_write_0_valid_T_4 & write_this_row; // @[ExecuteController.scala:919:27, :949:{89,109}]
assign io_acc_write_0_valid_0 = _io_acc_write_0_valid_T_5; // @[ExecuteController.scala:12:7, :949:109]
wire self_rec_rawIn_sign_0 = self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire self_rec_rawIn_isZeroExpIn = self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire self_rec_rawIn_isZeroFractIn = self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _self_rec_rawIn_normDist_T = self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_1 = self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_2 = self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_3 = self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_4 = self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_5 = self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_6 = self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_7 = self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_8 = self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_9 = self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_10 = self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_11 = self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_12 = self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_13 = self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_14 = self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_15 = self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_16 = self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_17 = self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_18 = self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_19 = self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_20 = self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_21 = self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_22 = self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _self_rec_rawIn_normDist_T_23 = _self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_24 = _self_rec_rawIn_normDist_T_2 ? 5'h14 : _self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_25 = _self_rec_rawIn_normDist_T_3 ? 5'h13 : _self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_26 = _self_rec_rawIn_normDist_T_4 ? 5'h12 : _self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_27 = _self_rec_rawIn_normDist_T_5 ? 5'h11 : _self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_28 = _self_rec_rawIn_normDist_T_6 ? 5'h10 : _self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_29 = _self_rec_rawIn_normDist_T_7 ? 5'hF : _self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_30 = _self_rec_rawIn_normDist_T_8 ? 5'hE : _self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_31 = _self_rec_rawIn_normDist_T_9 ? 5'hD : _self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_32 = _self_rec_rawIn_normDist_T_10 ? 5'hC : _self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_33 = _self_rec_rawIn_normDist_T_11 ? 5'hB : _self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_34 = _self_rec_rawIn_normDist_T_12 ? 5'hA : _self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_35 = _self_rec_rawIn_normDist_T_13 ? 5'h9 : _self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_36 = _self_rec_rawIn_normDist_T_14 ? 5'h8 : _self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_37 = _self_rec_rawIn_normDist_T_15 ? 5'h7 : _self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_38 = _self_rec_rawIn_normDist_T_16 ? 5'h6 : _self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_39 = _self_rec_rawIn_normDist_T_17 ? 5'h5 : _self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_40 = _self_rec_rawIn_normDist_T_18 ? 5'h4 : _self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_41 = _self_rec_rawIn_normDist_T_19 ? 5'h3 : _self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_42 = _self_rec_rawIn_normDist_T_20 ? 5'h2 : _self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_43 = _self_rec_rawIn_normDist_T_21 ? 5'h1 : _self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] self_rec_rawIn_normDist = _self_rec_rawIn_normDist_T_22 ? 5'h0 : _self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _self_rec_rawIn_subnormFract_T = {31'h0, self_rec_rawIn_fractIn} << self_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _self_rec_rawIn_subnormFract_T_1 = _self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] self_rec_rawIn_subnormFract = {_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _self_rec_rawIn_adjustedExp_T = {4'hF, ~self_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _self_rec_rawIn_adjustedExp_T_1 = self_rec_rawIn_isZeroExpIn ? _self_rec_rawIn_adjustedExp_T : {1'h0, self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _self_rec_rawIn_adjustedExp_T_2 = self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _self_rec_rawIn_adjustedExp_T_3 = {6'h20, _self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _self_rec_rawIn_adjustedExp_T_4 = {1'h0, _self_rec_rawIn_adjustedExp_T_1} + {2'h0, _self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] self_rec_rawIn_adjustedExp = _self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _self_rec_rawIn_out_sExp_T = self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire self_rec_rawIn_isZero = self_rec_rawIn_isZeroExpIn & self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire self_rec_rawIn_isZero_0 = self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _self_rec_rawIn_isSpecial_T = self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire self_rec_rawIn_isSpecial = &_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _self_rec_T_2 = self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _self_rec_rawIn_out_isNaN_T = ~self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _self_rec_rawIn_out_isNaN_T_1 = self_rec_rawIn_isSpecial & _self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign self_rec_rawIn_isNaN = _self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _self_rec_rawIn_out_isInf_T = self_rec_rawIn_isSpecial & self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign self_rec_rawIn_isInf = _self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _self_rec_rawIn_out_sExp_T_1 = {1'h0, _self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign self_rec_rawIn_sExp = _self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _self_rec_rawIn_out_sig_T = ~self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _self_rec_rawIn_out_sig_T_1 = {1'h0, _self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _self_rec_rawIn_out_sig_T_2 = self_rec_rawIn_isZeroExpIn ? self_rec_rawIn_subnormFract : self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _self_rec_rawIn_out_sig_T_3 = {_self_rec_rawIn_out_sig_T_1, _self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign self_rec_rawIn_sig = _self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _self_rec_T = self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _self_rec_T_1 = self_rec_rawIn_isZero_0 ? 3'h0 : _self_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _self_rec_T_3 = {_self_rec_T_1[2:1], _self_rec_T_1[0] | _self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _self_rec_T_4 = {self_rec_rawIn_sign_0, _self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _self_rec_T_5 = self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _self_rec_T_6 = {_self_rec_T_4, _self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _self_rec_T_7 = self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] self_rec = {_self_rec_T_6, _self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _result_bits_T; // @[fNFromRecFN.scala:66:12]
assign io_acc_write_0_bits_data_0_0_bits_0 = result_bits; // @[ExecuteController.scala:12:7]
wire [8:0] result_bits_rawIn_exp = _resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _result_bits_rawIn_isZero_T = result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire result_bits_rawIn_isZero = _result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire result_bits_rawIn_isZero_0 = result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _result_bits_rawIn_isSpecial_T = result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire result_bits_rawIn_isSpecial = &_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _result_bits_rawIn_out_isNaN_T = result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _result_bits_rawIn_out_isInf_T = result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _result_bits_rawIn_out_isNaN_T_1 = result_bits_rawIn_isSpecial & _result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign result_bits_rawIn_isNaN = _result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _result_bits_rawIn_out_isInf_T_1 = ~_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _result_bits_rawIn_out_isInf_T_2 = result_bits_rawIn_isSpecial & _result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign result_bits_rawIn_isInf = _result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _result_bits_rawIn_out_sign_T = _resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign result_bits_rawIn_sign = _result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _result_bits_rawIn_out_sExp_T = {1'h0, result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign result_bits_rawIn_sExp = _result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _result_bits_rawIn_out_sig_T = ~result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _result_bits_rawIn_out_sig_T_1 = {1'h0, _result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _result_bits_rawIn_out_sig_T_2 = _resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _result_bits_rawIn_out_sig_T_3 = {_result_bits_rawIn_out_sig_T_1, _result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign result_bits_rawIn_sig = _result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire result_bits_isSubnormal = $signed(result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _result_bits_denormShiftDist_T = result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] result_bits_denormShiftDist = _result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _result_bits_denormFract_T = result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _result_bits_denormFract_T_1 = _result_bits_denormFract_T >> result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] result_bits_denormFract = _result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _result_bits_expOut_T = result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _result_bits_expOut_T_1 = {1'h0, _result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _result_bits_expOut_T_2 = _result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _result_bits_expOut_T_3 = result_bits_isSubnormal ? 8'h0 : _result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _result_bits_expOut_T_4 = result_bits_rawIn_isNaN | result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _result_bits_expOut_T_5 = {8{_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] result_bits_expOut = _result_bits_expOut_T_3 | _result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _result_bits_fractOut_T = result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _result_bits_fractOut_T_1 = result_bits_rawIn_isInf ? 23'h0 : _result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] result_bits_fractOut = result_bits_isSubnormal ? result_bits_denormFract : _result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] result_bits_hi = {result_bits_rawIn_sign, result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23]
assign _result_bits_T = {result_bits_hi, result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
assign result_bits = _result_bits_T; // @[fNFromRecFN.scala:66:12]
wire self_rec_rawIn_1_sign = self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19]
wire self_rec_rawIn_isZeroExpIn_1 = self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire self_rec_rawIn_isZeroFractIn_1 = self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _self_rec_rawIn_normDist_T_44 = self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_45 = self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_46 = self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_47 = self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_48 = self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_49 = self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_50 = self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_51 = self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_52 = self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_53 = self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_54 = self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_55 = self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_56 = self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_57 = self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_58 = self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_59 = self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_60 = self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_61 = self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_62 = self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_63 = self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_64 = self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_65 = self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_66 = self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _self_rec_rawIn_normDist_T_67 = _self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_68 = _self_rec_rawIn_normDist_T_46 ? 5'h14 : _self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_69 = _self_rec_rawIn_normDist_T_47 ? 5'h13 : _self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_70 = _self_rec_rawIn_normDist_T_48 ? 5'h12 : _self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_71 = _self_rec_rawIn_normDist_T_49 ? 5'h11 : _self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_72 = _self_rec_rawIn_normDist_T_50 ? 5'h10 : _self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_73 = _self_rec_rawIn_normDist_T_51 ? 5'hF : _self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_74 = _self_rec_rawIn_normDist_T_52 ? 5'hE : _self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_75 = _self_rec_rawIn_normDist_T_53 ? 5'hD : _self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_76 = _self_rec_rawIn_normDist_T_54 ? 5'hC : _self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_77 = _self_rec_rawIn_normDist_T_55 ? 5'hB : _self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_78 = _self_rec_rawIn_normDist_T_56 ? 5'hA : _self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_79 = _self_rec_rawIn_normDist_T_57 ? 5'h9 : _self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_80 = _self_rec_rawIn_normDist_T_58 ? 5'h8 : _self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_81 = _self_rec_rawIn_normDist_T_59 ? 5'h7 : _self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_82 = _self_rec_rawIn_normDist_T_60 ? 5'h6 : _self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_83 = _self_rec_rawIn_normDist_T_61 ? 5'h5 : _self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_84 = _self_rec_rawIn_normDist_T_62 ? 5'h4 : _self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_85 = _self_rec_rawIn_normDist_T_63 ? 5'h3 : _self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_86 = _self_rec_rawIn_normDist_T_64 ? 5'h2 : _self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_87 = _self_rec_rawIn_normDist_T_65 ? 5'h1 : _self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70]
wire [4:0] self_rec_rawIn_normDist_1 = _self_rec_rawIn_normDist_T_66 ? 5'h0 : _self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70]
wire [53:0] _self_rec_rawIn_subnormFract_T_2 = {31'h0, self_rec_rawIn_fractIn_1} << self_rec_rawIn_normDist_1; // @[Mux.scala:50:70]
wire [21:0] _self_rec_rawIn_subnormFract_T_3 = _self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] self_rec_rawIn_subnormFract_1 = {_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70]
wire [8:0] _self_rec_rawIn_adjustedExp_T_6 = self_rec_rawIn_isZeroExpIn_1 ? _self_rec_rawIn_adjustedExp_T_5 : {1'h0, self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _self_rec_rawIn_adjustedExp_T_7 = self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _self_rec_rawIn_adjustedExp_T_8 = {6'h20, _self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _self_rec_rawIn_adjustedExp_T_9 = {1'h0, _self_rec_rawIn_adjustedExp_T_6} + {2'h0, _self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] self_rec_rawIn_adjustedExp_1 = _self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _self_rec_rawIn_out_sExp_T_2 = self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28]
wire self_rec_rawIn_isZero_1 = self_rec_rawIn_isZeroExpIn_1 & self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire self_rec_rawIn_1_isZero = self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _self_rec_rawIn_isSpecial_T_1 = self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire self_rec_rawIn_isSpecial_1 = &_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}]
wire _self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28]
wire _self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28]
wire _self_rec_T_10 = self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27]
wire self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19]
wire _self_rec_rawIn_out_isNaN_T_2 = ~self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _self_rec_rawIn_out_isNaN_T_3 = self_rec_rawIn_isSpecial_1 & _self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign self_rec_rawIn_1_isNaN = _self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _self_rec_rawIn_out_isInf_T_1 = self_rec_rawIn_isSpecial_1 & self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign self_rec_rawIn_1_isInf = _self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _self_rec_rawIn_out_sExp_T_3 = {1'h0, _self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}]
assign self_rec_rawIn_1_sExp = _self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _self_rec_rawIn_out_sig_T_4 = ~self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _self_rec_rawIn_out_sig_T_5 = {1'h0, _self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _self_rec_rawIn_out_sig_T_6 = self_rec_rawIn_isZeroExpIn_1 ? self_rec_rawIn_subnormFract_1 : self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _self_rec_rawIn_out_sig_T_7 = {_self_rec_rawIn_out_sig_T_5, _self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign self_rec_rawIn_1_sig = _self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _self_rec_T_8 = self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _self_rec_T_9 = self_rec_rawIn_1_isZero ? 3'h0 : _self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _self_rec_T_11 = {_self_rec_T_9[2:1], _self_rec_T_9[0] | _self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _self_rec_T_12 = {self_rec_rawIn_1_sign, _self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _self_rec_T_13 = self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _self_rec_T_14 = {_self_rec_T_12, _self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _self_rec_T_15 = self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] self_rec_1 = {_self_rec_T_14, _self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _result_bits_T_1; // @[fNFromRecFN.scala:66:12]
assign io_acc_write_0_bits_data_1_0_bits_0 = result_1_bits; // @[ExecuteController.scala:12:7]
wire [8:0] result_bits_rawIn_exp_1 = _resizer_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _result_bits_rawIn_isZero_T_1 = result_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire result_bits_rawIn_isZero_1 = _result_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire result_bits_rawIn_1_isZero = result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _result_bits_rawIn_isSpecial_T_1 = result_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire result_bits_rawIn_isSpecial_1 = &_result_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33]
wire _result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33]
wire _result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44]
wire result_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire result_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] result_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] result_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _result_bits_rawIn_out_isNaN_T_2 = result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _result_bits_rawIn_out_isInf_T_3 = result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _result_bits_rawIn_out_isNaN_T_3 = result_bits_rawIn_isSpecial_1 & _result_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign result_bits_rawIn_1_isNaN = _result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _result_bits_rawIn_out_isInf_T_4 = ~_result_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _result_bits_rawIn_out_isInf_T_5 = result_bits_rawIn_isSpecial_1 & _result_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign result_bits_rawIn_1_isInf = _result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _result_bits_rawIn_out_sign_T_1 = _resizer_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign result_bits_rawIn_1_sign = _result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _result_bits_rawIn_out_sExp_T_1 = {1'h0, result_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign result_bits_rawIn_1_sExp = _result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _result_bits_rawIn_out_sig_T_4 = ~result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _result_bits_rawIn_out_sig_T_5 = {1'h0, _result_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _result_bits_rawIn_out_sig_T_6 = _resizer_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _result_bits_rawIn_out_sig_T_7 = {_result_bits_rawIn_out_sig_T_5, _result_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign result_bits_rawIn_1_sig = _result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire result_bits_isSubnormal_1 = $signed(result_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _result_bits_denormShiftDist_T_2 = result_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _result_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _result_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] result_bits_denormShiftDist_1 = _result_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _result_bits_denormFract_T_2 = result_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _result_bits_denormFract_T_3 = _result_bits_denormFract_T_2 >> result_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] result_bits_denormFract_1 = _result_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _result_bits_expOut_T_6 = result_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _result_bits_expOut_T_7 = {1'h0, _result_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _result_bits_expOut_T_8 = _result_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _result_bits_expOut_T_9 = result_bits_isSubnormal_1 ? 8'h0 : _result_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _result_bits_expOut_T_10 = result_bits_rawIn_1_isNaN | result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _result_bits_expOut_T_11 = {8{_result_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] result_bits_expOut_1 = _result_bits_expOut_T_9 | _result_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _result_bits_fractOut_T_2 = result_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _result_bits_fractOut_T_3 = result_bits_rawIn_1_isInf ? 23'h0 : _result_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] result_bits_fractOut_1 = result_bits_isSubnormal_1 ? result_bits_denormFract_1 : _result_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] result_bits_hi_1 = {result_bits_rawIn_1_sign, result_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23]
assign _result_bits_T_1 = {result_bits_hi_1, result_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12]
assign result_1_bits = _result_bits_T_1; // @[fNFromRecFN.scala:66:12]
wire self_rec_rawIn_2_sign = self_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19]
wire self_rec_rawIn_isZeroExpIn_2 = self_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire self_rec_rawIn_isZeroFractIn_2 = self_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _self_rec_rawIn_normDist_T_88 = self_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_89 = self_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_90 = self_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_91 = self_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_92 = self_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_93 = self_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_94 = self_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_95 = self_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_96 = self_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_97 = self_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_98 = self_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_99 = self_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_100 = self_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_101 = self_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_102 = self_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_103 = self_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_104 = self_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_105 = self_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_106 = self_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_107 = self_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_108 = self_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_109 = self_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_110 = self_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _self_rec_rawIn_normDist_T_111 = _self_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_112 = _self_rec_rawIn_normDist_T_90 ? 5'h14 : _self_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_113 = _self_rec_rawIn_normDist_T_91 ? 5'h13 : _self_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_114 = _self_rec_rawIn_normDist_T_92 ? 5'h12 : _self_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_115 = _self_rec_rawIn_normDist_T_93 ? 5'h11 : _self_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_116 = _self_rec_rawIn_normDist_T_94 ? 5'h10 : _self_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_117 = _self_rec_rawIn_normDist_T_95 ? 5'hF : _self_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_118 = _self_rec_rawIn_normDist_T_96 ? 5'hE : _self_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_119 = _self_rec_rawIn_normDist_T_97 ? 5'hD : _self_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_120 = _self_rec_rawIn_normDist_T_98 ? 5'hC : _self_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_121 = _self_rec_rawIn_normDist_T_99 ? 5'hB : _self_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_122 = _self_rec_rawIn_normDist_T_100 ? 5'hA : _self_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_123 = _self_rec_rawIn_normDist_T_101 ? 5'h9 : _self_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_124 = _self_rec_rawIn_normDist_T_102 ? 5'h8 : _self_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_125 = _self_rec_rawIn_normDist_T_103 ? 5'h7 : _self_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_126 = _self_rec_rawIn_normDist_T_104 ? 5'h6 : _self_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_127 = _self_rec_rawIn_normDist_T_105 ? 5'h5 : _self_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_128 = _self_rec_rawIn_normDist_T_106 ? 5'h4 : _self_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_129 = _self_rec_rawIn_normDist_T_107 ? 5'h3 : _self_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_130 = _self_rec_rawIn_normDist_T_108 ? 5'h2 : _self_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_131 = _self_rec_rawIn_normDist_T_109 ? 5'h1 : _self_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70]
wire [4:0] self_rec_rawIn_normDist_2 = _self_rec_rawIn_normDist_T_110 ? 5'h0 : _self_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70]
wire [53:0] _self_rec_rawIn_subnormFract_T_4 = {31'h0, self_rec_rawIn_fractIn_2} << self_rec_rawIn_normDist_2; // @[Mux.scala:50:70]
wire [21:0] _self_rec_rawIn_subnormFract_T_5 = _self_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] self_rec_rawIn_subnormFract_2 = {_self_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _self_rec_rawIn_adjustedExp_T_10 = {4'hF, ~self_rec_rawIn_normDist_2}; // @[Mux.scala:50:70]
wire [8:0] _self_rec_rawIn_adjustedExp_T_11 = self_rec_rawIn_isZeroExpIn_2 ? _self_rec_rawIn_adjustedExp_T_10 : {1'h0, self_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _self_rec_rawIn_adjustedExp_T_12 = self_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _self_rec_rawIn_adjustedExp_T_13 = {6'h20, _self_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _self_rec_rawIn_adjustedExp_T_14 = {1'h0, _self_rec_rawIn_adjustedExp_T_11} + {2'h0, _self_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] self_rec_rawIn_adjustedExp_2 = _self_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _self_rec_rawIn_out_sExp_T_4 = self_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28]
wire self_rec_rawIn_isZero_2 = self_rec_rawIn_isZeroExpIn_2 & self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire self_rec_rawIn_2_isZero = self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _self_rec_rawIn_isSpecial_T_2 = self_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire self_rec_rawIn_isSpecial_2 = &_self_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}]
wire _self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28]
wire _self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28]
wire _self_rec_T_18 = self_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27]
wire self_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] self_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] self_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19]
wire _self_rec_rawIn_out_isNaN_T_4 = ~self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _self_rec_rawIn_out_isNaN_T_5 = self_rec_rawIn_isSpecial_2 & _self_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign self_rec_rawIn_2_isNaN = _self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _self_rec_rawIn_out_isInf_T_2 = self_rec_rawIn_isSpecial_2 & self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign self_rec_rawIn_2_isInf = _self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _self_rec_rawIn_out_sExp_T_5 = {1'h0, _self_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}]
assign self_rec_rawIn_2_sExp = _self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _self_rec_rawIn_out_sig_T_8 = ~self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _self_rec_rawIn_out_sig_T_9 = {1'h0, _self_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _self_rec_rawIn_out_sig_T_10 = self_rec_rawIn_isZeroExpIn_2 ? self_rec_rawIn_subnormFract_2 : self_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _self_rec_rawIn_out_sig_T_11 = {_self_rec_rawIn_out_sig_T_9, _self_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign self_rec_rawIn_2_sig = _self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _self_rec_T_16 = self_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _self_rec_T_17 = self_rec_rawIn_2_isZero ? 3'h0 : _self_rec_T_16; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _self_rec_T_19 = {_self_rec_T_17[2:1], _self_rec_T_17[0] | _self_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _self_rec_T_20 = {self_rec_rawIn_2_sign, _self_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _self_rec_T_21 = self_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _self_rec_T_22 = {_self_rec_T_20, _self_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _self_rec_T_23 = self_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] self_rec_2 = {_self_rec_T_22, _self_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _result_bits_T_2; // @[fNFromRecFN.scala:66:12]
assign io_acc_write_0_bits_data_2_0_bits_0 = result_2_bits; // @[ExecuteController.scala:12:7]
wire [8:0] result_bits_rawIn_exp_2 = _resizer_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _result_bits_rawIn_isZero_T_2 = result_bits_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire result_bits_rawIn_isZero_2 = _result_bits_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire result_bits_rawIn_2_isZero = result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _result_bits_rawIn_isSpecial_T_2 = result_bits_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire result_bits_rawIn_isSpecial_2 = &_result_bits_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33]
wire _result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33]
wire _result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44]
wire result_bits_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire result_bits_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] result_bits_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] result_bits_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _result_bits_rawIn_out_isNaN_T_4 = result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _result_bits_rawIn_out_isInf_T_6 = result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _result_bits_rawIn_out_isNaN_T_5 = result_bits_rawIn_isSpecial_2 & _result_bits_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign result_bits_rawIn_2_isNaN = _result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _result_bits_rawIn_out_isInf_T_7 = ~_result_bits_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _result_bits_rawIn_out_isInf_T_8 = result_bits_rawIn_isSpecial_2 & _result_bits_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign result_bits_rawIn_2_isInf = _result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _result_bits_rawIn_out_sign_T_2 = _resizer_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign result_bits_rawIn_2_sign = _result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _result_bits_rawIn_out_sExp_T_2 = {1'h0, result_bits_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign result_bits_rawIn_2_sExp = _result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _result_bits_rawIn_out_sig_T_8 = ~result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _result_bits_rawIn_out_sig_T_9 = {1'h0, _result_bits_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _result_bits_rawIn_out_sig_T_10 = _resizer_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _result_bits_rawIn_out_sig_T_11 = {_result_bits_rawIn_out_sig_T_9, _result_bits_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign result_bits_rawIn_2_sig = _result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire result_bits_isSubnormal_2 = $signed(result_bits_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _result_bits_denormShiftDist_T_4 = result_bits_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _result_bits_denormShiftDist_T_5 = 6'h1 - {1'h0, _result_bits_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] result_bits_denormShiftDist_2 = _result_bits_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _result_bits_denormFract_T_4 = result_bits_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _result_bits_denormFract_T_5 = _result_bits_denormFract_T_4 >> result_bits_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] result_bits_denormFract_2 = _result_bits_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _result_bits_expOut_T_12 = result_bits_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _result_bits_expOut_T_13 = {1'h0, _result_bits_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _result_bits_expOut_T_14 = _result_bits_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _result_bits_expOut_T_15 = result_bits_isSubnormal_2 ? 8'h0 : _result_bits_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _result_bits_expOut_T_16 = result_bits_rawIn_2_isNaN | result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _result_bits_expOut_T_17 = {8{_result_bits_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] result_bits_expOut_2 = _result_bits_expOut_T_15 | _result_bits_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _result_bits_fractOut_T_4 = result_bits_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _result_bits_fractOut_T_5 = result_bits_rawIn_2_isInf ? 23'h0 : _result_bits_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] result_bits_fractOut_2 = result_bits_isSubnormal_2 ? result_bits_denormFract_2 : _result_bits_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] result_bits_hi_2 = {result_bits_rawIn_2_sign, result_bits_expOut_2}; // @[rawFloatFromRecFN.scala:55:23]
assign _result_bits_T_2 = {result_bits_hi_2, result_bits_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12]
assign result_2_bits = _result_bits_T_2; // @[fNFromRecFN.scala:66:12]
wire self_rec_rawIn_3_sign = self_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19]
wire self_rec_rawIn_isZeroExpIn_3 = self_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire self_rec_rawIn_isZeroFractIn_3 = self_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _self_rec_rawIn_normDist_T_132 = self_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_133 = self_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_134 = self_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_135 = self_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_136 = self_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_137 = self_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_138 = self_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_139 = self_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_140 = self_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_141 = self_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_142 = self_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_143 = self_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_144 = self_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_145 = self_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_146 = self_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_147 = self_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_148 = self_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_149 = self_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_150 = self_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_151 = self_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_152 = self_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_153 = self_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_154 = self_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _self_rec_rawIn_normDist_T_155 = _self_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_156 = _self_rec_rawIn_normDist_T_134 ? 5'h14 : _self_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_157 = _self_rec_rawIn_normDist_T_135 ? 5'h13 : _self_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_158 = _self_rec_rawIn_normDist_T_136 ? 5'h12 : _self_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_159 = _self_rec_rawIn_normDist_T_137 ? 5'h11 : _self_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_160 = _self_rec_rawIn_normDist_T_138 ? 5'h10 : _self_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_161 = _self_rec_rawIn_normDist_T_139 ? 5'hF : _self_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_162 = _self_rec_rawIn_normDist_T_140 ? 5'hE : _self_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_163 = _self_rec_rawIn_normDist_T_141 ? 5'hD : _self_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_164 = _self_rec_rawIn_normDist_T_142 ? 5'hC : _self_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_165 = _self_rec_rawIn_normDist_T_143 ? 5'hB : _self_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_166 = _self_rec_rawIn_normDist_T_144 ? 5'hA : _self_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_167 = _self_rec_rawIn_normDist_T_145 ? 5'h9 : _self_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_168 = _self_rec_rawIn_normDist_T_146 ? 5'h8 : _self_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_169 = _self_rec_rawIn_normDist_T_147 ? 5'h7 : _self_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_170 = _self_rec_rawIn_normDist_T_148 ? 5'h6 : _self_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_171 = _self_rec_rawIn_normDist_T_149 ? 5'h5 : _self_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_172 = _self_rec_rawIn_normDist_T_150 ? 5'h4 : _self_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_173 = _self_rec_rawIn_normDist_T_151 ? 5'h3 : _self_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_174 = _self_rec_rawIn_normDist_T_152 ? 5'h2 : _self_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_175 = _self_rec_rawIn_normDist_T_153 ? 5'h1 : _self_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70]
wire [4:0] self_rec_rawIn_normDist_3 = _self_rec_rawIn_normDist_T_154 ? 5'h0 : _self_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70]
wire [53:0] _self_rec_rawIn_subnormFract_T_6 = {31'h0, self_rec_rawIn_fractIn_3} << self_rec_rawIn_normDist_3; // @[Mux.scala:50:70]
wire [21:0] _self_rec_rawIn_subnormFract_T_7 = _self_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] self_rec_rawIn_subnormFract_3 = {_self_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _self_rec_rawIn_adjustedExp_T_15 = {4'hF, ~self_rec_rawIn_normDist_3}; // @[Mux.scala:50:70]
wire [8:0] _self_rec_rawIn_adjustedExp_T_16 = self_rec_rawIn_isZeroExpIn_3 ? _self_rec_rawIn_adjustedExp_T_15 : {1'h0, self_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _self_rec_rawIn_adjustedExp_T_17 = self_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _self_rec_rawIn_adjustedExp_T_18 = {6'h20, _self_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _self_rec_rawIn_adjustedExp_T_19 = {1'h0, _self_rec_rawIn_adjustedExp_T_16} + {2'h0, _self_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] self_rec_rawIn_adjustedExp_3 = _self_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _self_rec_rawIn_out_sExp_T_6 = self_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28]
wire self_rec_rawIn_isZero_3 = self_rec_rawIn_isZeroExpIn_3 & self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire self_rec_rawIn_3_isZero = self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _self_rec_rawIn_isSpecial_T_3 = self_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire self_rec_rawIn_isSpecial_3 = &_self_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}]
wire _self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28]
wire _self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28]
wire _self_rec_T_26 = self_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27]
wire self_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] self_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] self_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19]
wire _self_rec_rawIn_out_isNaN_T_6 = ~self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _self_rec_rawIn_out_isNaN_T_7 = self_rec_rawIn_isSpecial_3 & _self_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign self_rec_rawIn_3_isNaN = _self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _self_rec_rawIn_out_isInf_T_3 = self_rec_rawIn_isSpecial_3 & self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign self_rec_rawIn_3_isInf = _self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _self_rec_rawIn_out_sExp_T_7 = {1'h0, _self_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}]
assign self_rec_rawIn_3_sExp = _self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _self_rec_rawIn_out_sig_T_12 = ~self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _self_rec_rawIn_out_sig_T_13 = {1'h0, _self_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _self_rec_rawIn_out_sig_T_14 = self_rec_rawIn_isZeroExpIn_3 ? self_rec_rawIn_subnormFract_3 : self_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _self_rec_rawIn_out_sig_T_15 = {_self_rec_rawIn_out_sig_T_13, _self_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign self_rec_rawIn_3_sig = _self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _self_rec_T_24 = self_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _self_rec_T_25 = self_rec_rawIn_3_isZero ? 3'h0 : _self_rec_T_24; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _self_rec_T_27 = {_self_rec_T_25[2:1], _self_rec_T_25[0] | _self_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _self_rec_T_28 = {self_rec_rawIn_3_sign, _self_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _self_rec_T_29 = self_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _self_rec_T_30 = {_self_rec_T_28, _self_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _self_rec_T_31 = self_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] self_rec_3 = {_self_rec_T_30, _self_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _result_bits_T_3; // @[fNFromRecFN.scala:66:12]
assign io_acc_write_0_bits_data_3_0_bits_0 = result_3_bits; // @[ExecuteController.scala:12:7]
wire [8:0] result_bits_rawIn_exp_3 = _resizer_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _result_bits_rawIn_isZero_T_3 = result_bits_rawIn_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire result_bits_rawIn_isZero_3 = _result_bits_rawIn_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire result_bits_rawIn_3_isZero = result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _result_bits_rawIn_isSpecial_T_3 = result_bits_rawIn_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire result_bits_rawIn_isSpecial_3 = &_result_bits_rawIn_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33]
wire _result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33]
wire _result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44]
wire result_bits_rawIn_3_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire result_bits_rawIn_3_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] result_bits_rawIn_3_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] result_bits_rawIn_3_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _result_bits_rawIn_out_isNaN_T_6 = result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _result_bits_rawIn_out_isInf_T_9 = result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _result_bits_rawIn_out_isNaN_T_7 = result_bits_rawIn_isSpecial_3 & _result_bits_rawIn_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign result_bits_rawIn_3_isNaN = _result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _result_bits_rawIn_out_isInf_T_10 = ~_result_bits_rawIn_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _result_bits_rawIn_out_isInf_T_11 = result_bits_rawIn_isSpecial_3 & _result_bits_rawIn_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign result_bits_rawIn_3_isInf = _result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _result_bits_rawIn_out_sign_T_3 = _resizer_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign result_bits_rawIn_3_sign = _result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _result_bits_rawIn_out_sExp_T_3 = {1'h0, result_bits_rawIn_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign result_bits_rawIn_3_sExp = _result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _result_bits_rawIn_out_sig_T_12 = ~result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _result_bits_rawIn_out_sig_T_13 = {1'h0, _result_bits_rawIn_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _result_bits_rawIn_out_sig_T_14 = _resizer_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _result_bits_rawIn_out_sig_T_15 = {_result_bits_rawIn_out_sig_T_13, _result_bits_rawIn_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign result_bits_rawIn_3_sig = _result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire result_bits_isSubnormal_3 = $signed(result_bits_rawIn_3_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _result_bits_denormShiftDist_T_6 = result_bits_rawIn_3_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _result_bits_denormShiftDist_T_7 = 6'h1 - {1'h0, _result_bits_denormShiftDist_T_6}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] result_bits_denormShiftDist_3 = _result_bits_denormShiftDist_T_7[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _result_bits_denormFract_T_6 = result_bits_rawIn_3_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _result_bits_denormFract_T_7 = _result_bits_denormFract_T_6 >> result_bits_denormShiftDist_3; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] result_bits_denormFract_3 = _result_bits_denormFract_T_7[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _result_bits_expOut_T_18 = result_bits_rawIn_3_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _result_bits_expOut_T_19 = {1'h0, _result_bits_expOut_T_18} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _result_bits_expOut_T_20 = _result_bits_expOut_T_19[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _result_bits_expOut_T_21 = result_bits_isSubnormal_3 ? 8'h0 : _result_bits_expOut_T_20; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _result_bits_expOut_T_22 = result_bits_rawIn_3_isNaN | result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _result_bits_expOut_T_23 = {8{_result_bits_expOut_T_22}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] result_bits_expOut_3 = _result_bits_expOut_T_21 | _result_bits_expOut_T_23; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _result_bits_fractOut_T_6 = result_bits_rawIn_3_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _result_bits_fractOut_T_7 = result_bits_rawIn_3_isInf ? 23'h0 : _result_bits_fractOut_T_6; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] result_bits_fractOut_3 = result_bits_isSubnormal_3 ? result_bits_denormFract_3 : _result_bits_fractOut_T_7; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] result_bits_hi_3 = {result_bits_rawIn_3_sign, result_bits_expOut_3}; // @[rawFloatFromRecFN.scala:55:23]
assign _result_bits_T_3 = {result_bits_hi_3, result_bits_fractOut_3}; // @[fNFromRecFN.scala:62:16, :66:12]
assign result_3_bits = _result_bits_T_3; // @[fNFromRecFN.scala:66:12]
wire mesh_completed_rob_id_fire; // @[ExecuteController.scala:966:44]
wire _T_197 = _mesh_io_resp_valid & _mesh_io_resp_bits_tag_rob_id_valid; // @[ExecuteController.scala:186:20, :970:26]
wire [2:0] output_counter_max = _output_counter_max_T[2:0]; // @[Util.scala:18:28]
wire _output_counter_T = |output_counter_max; // @[Util.scala:18:28, :19:14]
wire _GEN_92 = output_counter_max == 3'h0; // @[Util.scala:18:28, :19:28]
wire _output_counter_T_1; // @[Util.scala:19:28]
assign _output_counter_T_1 = _GEN_92; // @[Util.scala:19:28]
wire _output_counter_T_9; // @[Util.scala:29:12]
assign _output_counter_T_9 = _GEN_92; // @[Util.scala:19:28, :29:12]
wire _output_counter_T_2 = _output_counter_T | _output_counter_T_1; // @[Util.scala:19:{14,21,28}]
wire _output_counter_T_4 = ~_output_counter_T_3; // @[Util.scala:19:11]
wire _output_counter_T_5 = ~_output_counter_T_2; // @[Util.scala:19:{11,21}] |
Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_1 :
input clock : Clock
input reset : Reset
output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>}
cmem ram : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>} [16]
wire _valids_WIRE : UInt<1>[16]
connect _valids_WIRE[0], UInt<1>(0h0)
connect _valids_WIRE[1], UInt<1>(0h0)
connect _valids_WIRE[2], UInt<1>(0h0)
connect _valids_WIRE[3], UInt<1>(0h0)
connect _valids_WIRE[4], UInt<1>(0h0)
connect _valids_WIRE[5], UInt<1>(0h0)
connect _valids_WIRE[6], UInt<1>(0h0)
connect _valids_WIRE[7], UInt<1>(0h0)
connect _valids_WIRE[8], UInt<1>(0h0)
connect _valids_WIRE[9], UInt<1>(0h0)
connect _valids_WIRE[10], UInt<1>(0h0)
connect _valids_WIRE[11], UInt<1>(0h0)
connect _valids_WIRE[12], UInt<1>(0h0)
connect _valids_WIRE[13], UInt<1>(0h0)
connect _valids_WIRE[14], UInt<1>(0h0)
connect _valids_WIRE[15], UInt<1>(0h0)
regreset valids : UInt<1>[16], clock, reset, _valids_WIRE
reg uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[16], clock
regreset enq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0)
regreset deq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0)
regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0)
node ptr_match = eq(enq_ptr_value, deq_ptr_value)
node _io_empty_T = eq(maybe_full, UInt<1>(0h0))
node _io_empty_T_1 = and(ptr_match, _io_empty_T)
connect io.empty, _io_empty_T_1
node full = and(ptr_match, maybe_full)
node _do_enq_T = and(io.enq.ready, io.enq.valid)
wire do_enq : UInt<1>
connect do_enq, _do_enq_T
node _do_deq_T = eq(valids[deq_ptr_value], UInt<1>(0h0))
node _do_deq_T_1 = or(io.deq.ready, _do_deq_T)
node _do_deq_T_2 = eq(io.empty, UInt<1>(0h0))
node _do_deq_T_3 = and(_do_deq_T_1, _do_deq_T_2)
wire do_deq : UInt<1>
connect do_deq, _do_deq_T_3
node _valids_0_T = and(io.brupdate.b1.mispredict_mask, uops[0].br_mask)
node _valids_0_T_1 = neq(_valids_0_T, UInt<1>(0h0))
node _valids_0_T_2 = eq(_valids_0_T_1, UInt<1>(0h0))
node _valids_0_T_3 = and(valids[0], _valids_0_T_2)
node _valids_0_T_4 = and(io.flush, uops[0].uses_ldq)
node _valids_0_T_5 = eq(_valids_0_T_4, UInt<1>(0h0))
node _valids_0_T_6 = and(_valids_0_T_3, _valids_0_T_5)
connect valids[0], _valids_0_T_6
when valids[0] :
node _uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_0_br_mask_T_1 = and(uops[0].br_mask, _uops_0_br_mask_T)
connect uops[0].br_mask, _uops_0_br_mask_T_1
node _valids_1_T = and(io.brupdate.b1.mispredict_mask, uops[1].br_mask)
node _valids_1_T_1 = neq(_valids_1_T, UInt<1>(0h0))
node _valids_1_T_2 = eq(_valids_1_T_1, UInt<1>(0h0))
node _valids_1_T_3 = and(valids[1], _valids_1_T_2)
node _valids_1_T_4 = and(io.flush, uops[1].uses_ldq)
node _valids_1_T_5 = eq(_valids_1_T_4, UInt<1>(0h0))
node _valids_1_T_6 = and(_valids_1_T_3, _valids_1_T_5)
connect valids[1], _valids_1_T_6
when valids[1] :
node _uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_1_br_mask_T_1 = and(uops[1].br_mask, _uops_1_br_mask_T)
connect uops[1].br_mask, _uops_1_br_mask_T_1
node _valids_2_T = and(io.brupdate.b1.mispredict_mask, uops[2].br_mask)
node _valids_2_T_1 = neq(_valids_2_T, UInt<1>(0h0))
node _valids_2_T_2 = eq(_valids_2_T_1, UInt<1>(0h0))
node _valids_2_T_3 = and(valids[2], _valids_2_T_2)
node _valids_2_T_4 = and(io.flush, uops[2].uses_ldq)
node _valids_2_T_5 = eq(_valids_2_T_4, UInt<1>(0h0))
node _valids_2_T_6 = and(_valids_2_T_3, _valids_2_T_5)
connect valids[2], _valids_2_T_6
when valids[2] :
node _uops_2_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_2_br_mask_T_1 = and(uops[2].br_mask, _uops_2_br_mask_T)
connect uops[2].br_mask, _uops_2_br_mask_T_1
node _valids_3_T = and(io.brupdate.b1.mispredict_mask, uops[3].br_mask)
node _valids_3_T_1 = neq(_valids_3_T, UInt<1>(0h0))
node _valids_3_T_2 = eq(_valids_3_T_1, UInt<1>(0h0))
node _valids_3_T_3 = and(valids[3], _valids_3_T_2)
node _valids_3_T_4 = and(io.flush, uops[3].uses_ldq)
node _valids_3_T_5 = eq(_valids_3_T_4, UInt<1>(0h0))
node _valids_3_T_6 = and(_valids_3_T_3, _valids_3_T_5)
connect valids[3], _valids_3_T_6
when valids[3] :
node _uops_3_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_3_br_mask_T_1 = and(uops[3].br_mask, _uops_3_br_mask_T)
connect uops[3].br_mask, _uops_3_br_mask_T_1
node _valids_4_T = and(io.brupdate.b1.mispredict_mask, uops[4].br_mask)
node _valids_4_T_1 = neq(_valids_4_T, UInt<1>(0h0))
node _valids_4_T_2 = eq(_valids_4_T_1, UInt<1>(0h0))
node _valids_4_T_3 = and(valids[4], _valids_4_T_2)
node _valids_4_T_4 = and(io.flush, uops[4].uses_ldq)
node _valids_4_T_5 = eq(_valids_4_T_4, UInt<1>(0h0))
node _valids_4_T_6 = and(_valids_4_T_3, _valids_4_T_5)
connect valids[4], _valids_4_T_6
when valids[4] :
node _uops_4_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_4_br_mask_T_1 = and(uops[4].br_mask, _uops_4_br_mask_T)
connect uops[4].br_mask, _uops_4_br_mask_T_1
node _valids_5_T = and(io.brupdate.b1.mispredict_mask, uops[5].br_mask)
node _valids_5_T_1 = neq(_valids_5_T, UInt<1>(0h0))
node _valids_5_T_2 = eq(_valids_5_T_1, UInt<1>(0h0))
node _valids_5_T_3 = and(valids[5], _valids_5_T_2)
node _valids_5_T_4 = and(io.flush, uops[5].uses_ldq)
node _valids_5_T_5 = eq(_valids_5_T_4, UInt<1>(0h0))
node _valids_5_T_6 = and(_valids_5_T_3, _valids_5_T_5)
connect valids[5], _valids_5_T_6
when valids[5] :
node _uops_5_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_5_br_mask_T_1 = and(uops[5].br_mask, _uops_5_br_mask_T)
connect uops[5].br_mask, _uops_5_br_mask_T_1
node _valids_6_T = and(io.brupdate.b1.mispredict_mask, uops[6].br_mask)
node _valids_6_T_1 = neq(_valids_6_T, UInt<1>(0h0))
node _valids_6_T_2 = eq(_valids_6_T_1, UInt<1>(0h0))
node _valids_6_T_3 = and(valids[6], _valids_6_T_2)
node _valids_6_T_4 = and(io.flush, uops[6].uses_ldq)
node _valids_6_T_5 = eq(_valids_6_T_4, UInt<1>(0h0))
node _valids_6_T_6 = and(_valids_6_T_3, _valids_6_T_5)
connect valids[6], _valids_6_T_6
when valids[6] :
node _uops_6_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_6_br_mask_T_1 = and(uops[6].br_mask, _uops_6_br_mask_T)
connect uops[6].br_mask, _uops_6_br_mask_T_1
node _valids_7_T = and(io.brupdate.b1.mispredict_mask, uops[7].br_mask)
node _valids_7_T_1 = neq(_valids_7_T, UInt<1>(0h0))
node _valids_7_T_2 = eq(_valids_7_T_1, UInt<1>(0h0))
node _valids_7_T_3 = and(valids[7], _valids_7_T_2)
node _valids_7_T_4 = and(io.flush, uops[7].uses_ldq)
node _valids_7_T_5 = eq(_valids_7_T_4, UInt<1>(0h0))
node _valids_7_T_6 = and(_valids_7_T_3, _valids_7_T_5)
connect valids[7], _valids_7_T_6
when valids[7] :
node _uops_7_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_7_br_mask_T_1 = and(uops[7].br_mask, _uops_7_br_mask_T)
connect uops[7].br_mask, _uops_7_br_mask_T_1
node _valids_8_T = and(io.brupdate.b1.mispredict_mask, uops[8].br_mask)
node _valids_8_T_1 = neq(_valids_8_T, UInt<1>(0h0))
node _valids_8_T_2 = eq(_valids_8_T_1, UInt<1>(0h0))
node _valids_8_T_3 = and(valids[8], _valids_8_T_2)
node _valids_8_T_4 = and(io.flush, uops[8].uses_ldq)
node _valids_8_T_5 = eq(_valids_8_T_4, UInt<1>(0h0))
node _valids_8_T_6 = and(_valids_8_T_3, _valids_8_T_5)
connect valids[8], _valids_8_T_6
when valids[8] :
node _uops_8_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_8_br_mask_T_1 = and(uops[8].br_mask, _uops_8_br_mask_T)
connect uops[8].br_mask, _uops_8_br_mask_T_1
node _valids_9_T = and(io.brupdate.b1.mispredict_mask, uops[9].br_mask)
node _valids_9_T_1 = neq(_valids_9_T, UInt<1>(0h0))
node _valids_9_T_2 = eq(_valids_9_T_1, UInt<1>(0h0))
node _valids_9_T_3 = and(valids[9], _valids_9_T_2)
node _valids_9_T_4 = and(io.flush, uops[9].uses_ldq)
node _valids_9_T_5 = eq(_valids_9_T_4, UInt<1>(0h0))
node _valids_9_T_6 = and(_valids_9_T_3, _valids_9_T_5)
connect valids[9], _valids_9_T_6
when valids[9] :
node _uops_9_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_9_br_mask_T_1 = and(uops[9].br_mask, _uops_9_br_mask_T)
connect uops[9].br_mask, _uops_9_br_mask_T_1
node _valids_10_T = and(io.brupdate.b1.mispredict_mask, uops[10].br_mask)
node _valids_10_T_1 = neq(_valids_10_T, UInt<1>(0h0))
node _valids_10_T_2 = eq(_valids_10_T_1, UInt<1>(0h0))
node _valids_10_T_3 = and(valids[10], _valids_10_T_2)
node _valids_10_T_4 = and(io.flush, uops[10].uses_ldq)
node _valids_10_T_5 = eq(_valids_10_T_4, UInt<1>(0h0))
node _valids_10_T_6 = and(_valids_10_T_3, _valids_10_T_5)
connect valids[10], _valids_10_T_6
when valids[10] :
node _uops_10_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_10_br_mask_T_1 = and(uops[10].br_mask, _uops_10_br_mask_T)
connect uops[10].br_mask, _uops_10_br_mask_T_1
node _valids_11_T = and(io.brupdate.b1.mispredict_mask, uops[11].br_mask)
node _valids_11_T_1 = neq(_valids_11_T, UInt<1>(0h0))
node _valids_11_T_2 = eq(_valids_11_T_1, UInt<1>(0h0))
node _valids_11_T_3 = and(valids[11], _valids_11_T_2)
node _valids_11_T_4 = and(io.flush, uops[11].uses_ldq)
node _valids_11_T_5 = eq(_valids_11_T_4, UInt<1>(0h0))
node _valids_11_T_6 = and(_valids_11_T_3, _valids_11_T_5)
connect valids[11], _valids_11_T_6
when valids[11] :
node _uops_11_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_11_br_mask_T_1 = and(uops[11].br_mask, _uops_11_br_mask_T)
connect uops[11].br_mask, _uops_11_br_mask_T_1
node _valids_12_T = and(io.brupdate.b1.mispredict_mask, uops[12].br_mask)
node _valids_12_T_1 = neq(_valids_12_T, UInt<1>(0h0))
node _valids_12_T_2 = eq(_valids_12_T_1, UInt<1>(0h0))
node _valids_12_T_3 = and(valids[12], _valids_12_T_2)
node _valids_12_T_4 = and(io.flush, uops[12].uses_ldq)
node _valids_12_T_5 = eq(_valids_12_T_4, UInt<1>(0h0))
node _valids_12_T_6 = and(_valids_12_T_3, _valids_12_T_5)
connect valids[12], _valids_12_T_6
when valids[12] :
node _uops_12_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_12_br_mask_T_1 = and(uops[12].br_mask, _uops_12_br_mask_T)
connect uops[12].br_mask, _uops_12_br_mask_T_1
node _valids_13_T = and(io.brupdate.b1.mispredict_mask, uops[13].br_mask)
node _valids_13_T_1 = neq(_valids_13_T, UInt<1>(0h0))
node _valids_13_T_2 = eq(_valids_13_T_1, UInt<1>(0h0))
node _valids_13_T_3 = and(valids[13], _valids_13_T_2)
node _valids_13_T_4 = and(io.flush, uops[13].uses_ldq)
node _valids_13_T_5 = eq(_valids_13_T_4, UInt<1>(0h0))
node _valids_13_T_6 = and(_valids_13_T_3, _valids_13_T_5)
connect valids[13], _valids_13_T_6
when valids[13] :
node _uops_13_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_13_br_mask_T_1 = and(uops[13].br_mask, _uops_13_br_mask_T)
connect uops[13].br_mask, _uops_13_br_mask_T_1
node _valids_14_T = and(io.brupdate.b1.mispredict_mask, uops[14].br_mask)
node _valids_14_T_1 = neq(_valids_14_T, UInt<1>(0h0))
node _valids_14_T_2 = eq(_valids_14_T_1, UInt<1>(0h0))
node _valids_14_T_3 = and(valids[14], _valids_14_T_2)
node _valids_14_T_4 = and(io.flush, uops[14].uses_ldq)
node _valids_14_T_5 = eq(_valids_14_T_4, UInt<1>(0h0))
node _valids_14_T_6 = and(_valids_14_T_3, _valids_14_T_5)
connect valids[14], _valids_14_T_6
when valids[14] :
node _uops_14_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_14_br_mask_T_1 = and(uops[14].br_mask, _uops_14_br_mask_T)
connect uops[14].br_mask, _uops_14_br_mask_T_1
node _valids_15_T = and(io.brupdate.b1.mispredict_mask, uops[15].br_mask)
node _valids_15_T_1 = neq(_valids_15_T, UInt<1>(0h0))
node _valids_15_T_2 = eq(_valids_15_T_1, UInt<1>(0h0))
node _valids_15_T_3 = and(valids[15], _valids_15_T_2)
node _valids_15_T_4 = and(io.flush, uops[15].uses_ldq)
node _valids_15_T_5 = eq(_valids_15_T_4, UInt<1>(0h0))
node _valids_15_T_6 = and(_valids_15_T_3, _valids_15_T_5)
connect valids[15], _valids_15_T_6
when valids[15] :
node _uops_15_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_15_br_mask_T_1 = and(uops[15].br_mask, _uops_15_br_mask_T)
connect uops[15].br_mask, _uops_15_br_mask_T_1
when do_enq :
infer mport MPORT = ram[enq_ptr_value], clock
connect MPORT, io.enq.bits
connect valids[enq_ptr_value], UInt<1>(0h1)
connect uops[enq_ptr_value], io.enq.bits.uop
node _uops_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_br_mask_T_1 = and(io.enq.bits.uop.br_mask, _uops_br_mask_T)
connect uops[enq_ptr_value].br_mask, _uops_br_mask_T_1
node wrap = eq(enq_ptr_value, UInt<4>(0hf))
node _value_T = add(enq_ptr_value, UInt<1>(0h1))
node _value_T_1 = tail(_value_T, 1)
connect enq_ptr_value, _value_T_1
when do_deq :
connect valids[deq_ptr_value], UInt<1>(0h0)
node wrap_1 = eq(deq_ptr_value, UInt<4>(0hf))
node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1))
node _value_T_3 = tail(_value_T_2, 1)
connect deq_ptr_value, _value_T_3
node _T = neq(do_enq, do_deq)
when _T :
connect maybe_full, do_enq
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
connect io.enq.ready, _io_enq_ready_T
wire out : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}
infer mport out_MPORT = ram[deq_ptr_value], clock
connect out, out_MPORT
connect out.uop, uops[deq_ptr_value]
node _io_deq_valid_T = eq(io.empty, UInt<1>(0h0))
node _io_deq_valid_T_1 = and(_io_deq_valid_T, valids[deq_ptr_value])
node _io_deq_valid_T_2 = and(io.brupdate.b1.mispredict_mask, out.uop.br_mask)
node _io_deq_valid_T_3 = neq(_io_deq_valid_T_2, UInt<1>(0h0))
node _io_deq_valid_T_4 = eq(_io_deq_valid_T_3, UInt<1>(0h0))
node _io_deq_valid_T_5 = and(_io_deq_valid_T_1, _io_deq_valid_T_4)
node _io_deq_valid_T_6 = and(io.flush, out.uop.uses_ldq)
node _io_deq_valid_T_7 = eq(_io_deq_valid_T_6, UInt<1>(0h0))
node _io_deq_valid_T_8 = and(_io_deq_valid_T_5, _io_deq_valid_T_7)
connect io.deq.valid, _io_deq_valid_T_8
connect io.deq.bits, out
node _io_deq_bits_uop_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _io_deq_bits_uop_br_mask_T_1 = and(out.uop.br_mask, _io_deq_bits_uop_br_mask_T)
connect io.deq.bits.uop.br_mask, _io_deq_bits_uop_br_mask_T_1
node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value)
node ptr_diff = tail(_ptr_diff_T, 1)
node _io_count_T = and(maybe_full, ptr_match)
node _io_count_T_1 = cat(_io_count_T, ptr_diff)
connect io.count, _io_count_T_1 | module BranchKillableQueue_1( // @[util.scala:448:7]
input clock, // @[util.scala:448:7]
input reset, // @[util.scala:448:7]
output io_enq_ready, // @[util.scala:453:14]
input io_enq_valid, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_uopc, // @[util.scala:453:14]
input [31:0] io_enq_bits_uop_inst, // @[util.scala:453:14]
input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:453:14]
input io_enq_bits_uop_is_rvc, // @[util.scala:453:14]
input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_iq_type, // @[util.scala:453:14]
input [9:0] io_enq_bits_uop_fu_code, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_ctrl_br_type, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14]
input [4:0] io_enq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_is_load, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_is_sta, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_is_std, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_iw_state, // @[util.scala:453:14]
input io_enq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14]
input io_enq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14]
input io_enq_bits_uop_is_br, // @[util.scala:453:14]
input io_enq_bits_uop_is_jalr, // @[util.scala:453:14]
input io_enq_bits_uop_is_jal, // @[util.scala:453:14]
input io_enq_bits_uop_is_sfb, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:453:14]
input io_enq_bits_uop_edge_inst, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:453:14]
input io_enq_bits_uop_taken, // @[util.scala:453:14]
input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:453:14]
input [11:0] io_enq_bits_uop_csr_addr, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_rob_idx, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_pdst, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_prs1, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_prs2, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_prs3, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_ppred, // @[util.scala:453:14]
input io_enq_bits_uop_prs1_busy, // @[util.scala:453:14]
input io_enq_bits_uop_prs2_busy, // @[util.scala:453:14]
input io_enq_bits_uop_prs3_busy, // @[util.scala:453:14]
input io_enq_bits_uop_ppred_busy, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:453:14]
input io_enq_bits_uop_exception, // @[util.scala:453:14]
input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:453:14]
input io_enq_bits_uop_bypassable, // @[util.scala:453:14]
input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:453:14]
input io_enq_bits_uop_mem_signed, // @[util.scala:453:14]
input io_enq_bits_uop_is_fence, // @[util.scala:453:14]
input io_enq_bits_uop_is_fencei, // @[util.scala:453:14]
input io_enq_bits_uop_is_amo, // @[util.scala:453:14]
input io_enq_bits_uop_uses_ldq, // @[util.scala:453:14]
input io_enq_bits_uop_uses_stq, // @[util.scala:453:14]
input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14]
input io_enq_bits_uop_is_unique, // @[util.scala:453:14]
input io_enq_bits_uop_flush_on_commit, // @[util.scala:453:14]
input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_ldst, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:453:14]
input io_enq_bits_uop_ldst_val, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:453:14]
input io_enq_bits_uop_frs3_en, // @[util.scala:453:14]
input io_enq_bits_uop_fp_val, // @[util.scala:453:14]
input io_enq_bits_uop_fp_single, // @[util.scala:453:14]
input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:453:14]
input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:453:14]
input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:453:14]
input io_enq_bits_uop_bp_debug_if, // @[util.scala:453:14]
input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:453:14]
input [33:0] io_enq_bits_addr, // @[util.scala:453:14]
input [63:0] io_enq_bits_data, // @[util.scala:453:14]
input io_enq_bits_is_hella, // @[util.scala:453:14]
input io_enq_bits_tag_match, // @[util.scala:453:14]
input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:453:14]
input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:453:14]
input [1:0] io_enq_bits_way_en, // @[util.scala:453:14]
input [4:0] io_enq_bits_sdq_id, // @[util.scala:453:14]
input io_deq_ready, // @[util.scala:453:14]
output io_deq_valid, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_uopc, // @[util.scala:453:14]
output [31:0] io_deq_bits_uop_inst, // @[util.scala:453:14]
output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:453:14]
output io_deq_bits_uop_is_rvc, // @[util.scala:453:14]
output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_iq_type, // @[util.scala:453:14]
output [9:0] io_deq_bits_uop_fu_code, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_ctrl_br_type, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14]
output [4:0] io_deq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_is_load, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_is_sta, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_is_std, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_iw_state, // @[util.scala:453:14]
output io_deq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14]
output io_deq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14]
output io_deq_bits_uop_is_br, // @[util.scala:453:14]
output io_deq_bits_uop_is_jalr, // @[util.scala:453:14]
output io_deq_bits_uop_is_jal, // @[util.scala:453:14]
output io_deq_bits_uop_is_sfb, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:453:14]
output io_deq_bits_uop_edge_inst, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:453:14]
output io_deq_bits_uop_taken, // @[util.scala:453:14]
output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:453:14]
output [11:0] io_deq_bits_uop_csr_addr, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_rob_idx, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_pdst, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_prs1, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_prs2, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_prs3, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_ppred, // @[util.scala:453:14]
output io_deq_bits_uop_prs1_busy, // @[util.scala:453:14]
output io_deq_bits_uop_prs2_busy, // @[util.scala:453:14]
output io_deq_bits_uop_prs3_busy, // @[util.scala:453:14]
output io_deq_bits_uop_ppred_busy, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:453:14]
output io_deq_bits_uop_exception, // @[util.scala:453:14]
output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:453:14]
output io_deq_bits_uop_bypassable, // @[util.scala:453:14]
output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:453:14]
output io_deq_bits_uop_mem_signed, // @[util.scala:453:14]
output io_deq_bits_uop_is_fence, // @[util.scala:453:14]
output io_deq_bits_uop_is_fencei, // @[util.scala:453:14]
output io_deq_bits_uop_is_amo, // @[util.scala:453:14]
output io_deq_bits_uop_uses_ldq, // @[util.scala:453:14]
output io_deq_bits_uop_uses_stq, // @[util.scala:453:14]
output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14]
output io_deq_bits_uop_is_unique, // @[util.scala:453:14]
output io_deq_bits_uop_flush_on_commit, // @[util.scala:453:14]
output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_ldst, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:453:14]
output io_deq_bits_uop_ldst_val, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:453:14]
output io_deq_bits_uop_frs3_en, // @[util.scala:453:14]
output io_deq_bits_uop_fp_val, // @[util.scala:453:14]
output io_deq_bits_uop_fp_single, // @[util.scala:453:14]
output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:453:14]
output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:453:14]
output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:453:14]
output io_deq_bits_uop_bp_debug_if, // @[util.scala:453:14]
output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:453:14]
output [33:0] io_deq_bits_addr, // @[util.scala:453:14]
output [63:0] io_deq_bits_data, // @[util.scala:453:14]
output io_deq_bits_is_hella, // @[util.scala:453:14]
output io_deq_bits_tag_match, // @[util.scala:453:14]
output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:453:14]
output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:453:14]
output [4:0] io_deq_bits_sdq_id, // @[util.scala:453:14]
output io_empty // @[util.scala:453:14]
);
wire [3:0] out_uop_br_mask; // @[util.scala:506:17]
wire [130:0] _ram_ext_R0_data; // @[util.scala:464:20]
wire io_enq_valid_0 = io_enq_valid; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_uopc_0 = io_enq_bits_uop_uopc; // @[util.scala:448:7]
wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:448:7]
wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:448:7]
wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:448:7]
wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_iq_type_0 = io_enq_bits_uop_iq_type; // @[util.scala:448:7]
wire [9:0] io_enq_bits_uop_fu_code_0 = io_enq_bits_uop_fu_code; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_ctrl_br_type_0 = io_enq_bits_uop_ctrl_br_type; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_ctrl_op1_sel_0 = io_enq_bits_uop_ctrl_op1_sel; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_ctrl_op2_sel_0 = io_enq_bits_uop_ctrl_op2_sel; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_ctrl_imm_sel_0 = io_enq_bits_uop_ctrl_imm_sel; // @[util.scala:448:7]
wire [4:0] io_enq_bits_uop_ctrl_op_fcn_0 = io_enq_bits_uop_ctrl_op_fcn; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_fcn_dw_0 = io_enq_bits_uop_ctrl_fcn_dw; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_ctrl_csr_cmd_0 = io_enq_bits_uop_ctrl_csr_cmd; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_is_load_0 = io_enq_bits_uop_ctrl_is_load; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_is_sta_0 = io_enq_bits_uop_ctrl_is_sta; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_is_std_0 = io_enq_bits_uop_ctrl_is_std; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_iw_state_0 = io_enq_bits_uop_iw_state; // @[util.scala:448:7]
wire io_enq_bits_uop_iw_p1_poisoned_0 = io_enq_bits_uop_iw_p1_poisoned; // @[util.scala:448:7]
wire io_enq_bits_uop_iw_p2_poisoned_0 = io_enq_bits_uop_iw_p2_poisoned; // @[util.scala:448:7]
wire io_enq_bits_uop_is_br_0 = io_enq_bits_uop_is_br; // @[util.scala:448:7]
wire io_enq_bits_uop_is_jalr_0 = io_enq_bits_uop_is_jalr; // @[util.scala:448:7]
wire io_enq_bits_uop_is_jal_0 = io_enq_bits_uop_is_jal; // @[util.scala:448:7]
wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:448:7]
wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:448:7]
wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:448:7]
wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:448:7]
wire [11:0] io_enq_bits_uop_csr_addr_0 = io_enq_bits_uop_csr_addr; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:448:7]
wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:448:7]
wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:448:7]
wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:448:7]
wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:448:7]
wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:448:7]
wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:448:7]
wire io_enq_bits_uop_bypassable_0 = io_enq_bits_uop_bypassable; // @[util.scala:448:7]
wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:448:7]
wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:448:7]
wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:448:7]
wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:448:7]
wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:448:7]
wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:448:7]
wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:448:7]
wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:448:7]
wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:448:7]
wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:448:7]
wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:448:7]
wire io_enq_bits_uop_ldst_val_0 = io_enq_bits_uop_ldst_val; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:448:7]
wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:448:7]
wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:448:7]
wire io_enq_bits_uop_fp_single_0 = io_enq_bits_uop_fp_single; // @[util.scala:448:7]
wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:448:7]
wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:448:7]
wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:448:7]
wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:448:7]
wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:448:7]
wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:448:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:448:7]
wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:448:7]
wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:448:7]
wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:448:7]
wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:448:7]
wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:448:7]
wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:448:7]
wire io_deq_ready_0 = io_deq_ready; // @[util.scala:448:7]
wire _valids_0_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_0_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_1_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_1_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_2_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_2_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_3_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_3_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_4_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_4_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_5_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_5_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_6_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_6_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_7_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_7_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_8_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_8_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_9_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_9_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_10_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_10_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_11_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_11_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_12_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_12_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_13_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_13_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_14_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_14_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_15_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_15_T_5 = 1'h1; // @[util.scala:481:72]
wire _io_deq_valid_T_4 = 1'h1; // @[util.scala:509:68]
wire _io_deq_valid_T_7 = 1'h1; // @[util.scala:509:111]
wire [3:0] _uops_0_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_1_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_2_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_3_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_4_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_5_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_6_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_7_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_8_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_9_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_10_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_11_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_12_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_13_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_14_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_15_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _io_deq_bits_uop_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:448:7, :453:14]
wire [11:0] io_brupdate_b2_uop_csr_addr = 12'h0; // @[util.scala:448:7, :453:14]
wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_brupdate_b2_uop_rob_idx = 6'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:448:7, :453:14]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[util.scala:448:7, :453:14]
wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_iw_state = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_debug_fsrc = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_debug_tsrc = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_target_offset = 2'h0; // @[util.scala:448:7, :453:14]
wire [9:0] io_brupdate_b2_uop_fu_code = 10'h0; // @[util.scala:448:7, :453:14]
wire [2:0] io_brupdate_b2_uop_iq_type = 3'h0; // @[util.scala:448:7, :453:14]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[util.scala:448:7, :453:14]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[util.scala:448:7, :453:14]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[util.scala:448:7, :453:14]
wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:448:7, :453:14]
wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:448:7, :453:14]
wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:448:7, :453:14]
wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_br = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_jalr = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_jal = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_bypassable = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ldst_val = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_fp_single = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_valid = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_taken = 1'h0; // @[util.scala:448:7]
wire io_flush = 1'h0; // @[util.scala:448:7]
wire _valids_WIRE_0 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_1 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_2 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_3 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_4 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_5 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_6 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_7 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_8 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_9 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_10 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_11 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_12 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_13 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_14 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_15 = 1'h0; // @[util.scala:465:32]
wire _valids_0_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_0_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_1_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_1_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_2_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_2_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_3_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_3_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_4_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_4_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_5_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_5_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_6_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_6_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_7_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_7_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_8_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_8_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_9_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_9_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_10_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_10_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_11_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_11_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_12_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_12_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_13_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_13_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_14_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_14_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_15_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_15_T_4 = 1'h0; // @[util.scala:481:83]
wire _io_deq_valid_T_3 = 1'h0; // @[util.scala:118:59]
wire _io_deq_valid_T_6 = 1'h0; // @[util.scala:509:122]
wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:448:7, :453:14]
wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_brupdate_b2_uop_uopc = 7'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_brupdate_b2_uop_pdst = 7'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_brupdate_b2_uop_prs1 = 7'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_brupdate_b2_uop_prs2 = 7'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_brupdate_b2_uop_prs3 = 7'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_brupdate_b2_uop_stale_pdst = 7'h0; // @[util.scala:448:7, :453:14]
wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:448:7]
wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:448:7]
wire [3:0] _valids_0_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_1_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_2_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_3_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_4_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_5_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_6_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_7_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_8_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_9_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_10_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_11_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_12_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_13_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_14_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_15_T = 4'h0; // @[util.scala:118:51]
wire _io_enq_ready_T; // @[util.scala:504:19]
wire [3:0] _io_deq_valid_T_2 = 4'h0; // @[util.scala:118:51]
wire [3:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0; // @[util.scala:85:25, :448:7]
wire _io_deq_valid_T_8; // @[util.scala:509:108]
wire [6:0] out_uop_uopc; // @[util.scala:506:17]
wire [31:0] out_uop_inst; // @[util.scala:506:17]
wire [31:0] out_uop_debug_inst; // @[util.scala:506:17]
wire out_uop_is_rvc; // @[util.scala:506:17]
wire [33:0] out_uop_debug_pc; // @[util.scala:506:17]
wire [2:0] out_uop_iq_type; // @[util.scala:506:17]
wire [9:0] out_uop_fu_code; // @[util.scala:506:17]
wire [3:0] out_uop_ctrl_br_type; // @[util.scala:506:17]
wire [1:0] out_uop_ctrl_op1_sel; // @[util.scala:506:17]
wire [2:0] out_uop_ctrl_op2_sel; // @[util.scala:506:17]
wire [2:0] out_uop_ctrl_imm_sel; // @[util.scala:506:17]
wire [4:0] out_uop_ctrl_op_fcn; // @[util.scala:506:17]
wire out_uop_ctrl_fcn_dw; // @[util.scala:506:17]
wire [2:0] out_uop_ctrl_csr_cmd; // @[util.scala:506:17]
wire out_uop_ctrl_is_load; // @[util.scala:506:17]
wire out_uop_ctrl_is_sta; // @[util.scala:506:17]
wire out_uop_ctrl_is_std; // @[util.scala:506:17]
wire [1:0] out_uop_iw_state; // @[util.scala:506:17]
wire out_uop_iw_p1_poisoned; // @[util.scala:506:17]
wire out_uop_iw_p2_poisoned; // @[util.scala:506:17]
wire out_uop_is_br; // @[util.scala:506:17]
wire out_uop_is_jalr; // @[util.scala:506:17]
wire out_uop_is_jal; // @[util.scala:506:17]
wire out_uop_is_sfb; // @[util.scala:506:17]
wire [3:0] _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25]
wire [1:0] out_uop_br_tag; // @[util.scala:506:17]
wire [3:0] out_uop_ftq_idx; // @[util.scala:506:17]
wire out_uop_edge_inst; // @[util.scala:506:17]
wire [5:0] out_uop_pc_lob; // @[util.scala:506:17]
wire out_uop_taken; // @[util.scala:506:17]
wire [19:0] out_uop_imm_packed; // @[util.scala:506:17]
wire [11:0] out_uop_csr_addr; // @[util.scala:506:17]
wire [5:0] out_uop_rob_idx; // @[util.scala:506:17]
wire [3:0] out_uop_ldq_idx; // @[util.scala:506:17]
wire [3:0] out_uop_stq_idx; // @[util.scala:506:17]
wire [1:0] out_uop_rxq_idx; // @[util.scala:506:17]
wire [6:0] out_uop_pdst; // @[util.scala:506:17]
wire [6:0] out_uop_prs1; // @[util.scala:506:17]
wire [6:0] out_uop_prs2; // @[util.scala:506:17]
wire [6:0] out_uop_prs3; // @[util.scala:506:17]
wire [3:0] out_uop_ppred; // @[util.scala:506:17]
wire out_uop_prs1_busy; // @[util.scala:506:17]
wire out_uop_prs2_busy; // @[util.scala:506:17]
wire out_uop_prs3_busy; // @[util.scala:506:17]
wire out_uop_ppred_busy; // @[util.scala:506:17]
wire [6:0] out_uop_stale_pdst; // @[util.scala:506:17]
wire out_uop_exception; // @[util.scala:506:17]
wire [63:0] out_uop_exc_cause; // @[util.scala:506:17]
wire out_uop_bypassable; // @[util.scala:506:17]
wire [4:0] out_uop_mem_cmd; // @[util.scala:506:17]
wire [1:0] out_uop_mem_size; // @[util.scala:506:17]
wire out_uop_mem_signed; // @[util.scala:506:17]
wire out_uop_is_fence; // @[util.scala:506:17]
wire out_uop_is_fencei; // @[util.scala:506:17]
wire out_uop_is_amo; // @[util.scala:506:17]
wire out_uop_uses_ldq; // @[util.scala:506:17]
wire out_uop_uses_stq; // @[util.scala:506:17]
wire out_uop_is_sys_pc2epc; // @[util.scala:506:17]
wire out_uop_is_unique; // @[util.scala:506:17]
wire out_uop_flush_on_commit; // @[util.scala:506:17]
wire out_uop_ldst_is_rs1; // @[util.scala:506:17]
wire [5:0] out_uop_ldst; // @[util.scala:506:17]
wire [5:0] out_uop_lrs1; // @[util.scala:506:17]
wire [5:0] out_uop_lrs2; // @[util.scala:506:17]
wire [5:0] out_uop_lrs3; // @[util.scala:506:17]
wire out_uop_ldst_val; // @[util.scala:506:17]
wire [1:0] out_uop_dst_rtype; // @[util.scala:506:17]
wire [1:0] out_uop_lrs1_rtype; // @[util.scala:506:17]
wire [1:0] out_uop_lrs2_rtype; // @[util.scala:506:17]
wire out_uop_frs3_en; // @[util.scala:506:17]
wire out_uop_fp_val; // @[util.scala:506:17]
wire out_uop_fp_single; // @[util.scala:506:17]
wire out_uop_xcpt_pf_if; // @[util.scala:506:17]
wire out_uop_xcpt_ae_if; // @[util.scala:506:17]
wire out_uop_xcpt_ma_if; // @[util.scala:506:17]
wire out_uop_bp_debug_if; // @[util.scala:506:17]
wire out_uop_bp_xcpt_if; // @[util.scala:506:17]
wire [1:0] out_uop_debug_fsrc; // @[util.scala:506:17]
wire [1:0] out_uop_debug_tsrc; // @[util.scala:506:17]
wire [33:0] out_addr; // @[util.scala:506:17]
wire [63:0] out_data; // @[util.scala:506:17]
wire out_is_hella; // @[util.scala:506:17]
wire out_tag_match; // @[util.scala:506:17]
wire [1:0] out_old_meta_coh_state; // @[util.scala:506:17]
wire [21:0] out_old_meta_tag; // @[util.scala:506:17]
wire [1:0] out_way_en; // @[util.scala:506:17]
wire [4:0] out_sdq_id; // @[util.scala:506:17]
wire _io_empty_T_1; // @[util.scala:473:25]
wire io_enq_ready_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_uopc_0; // @[util.scala:448:7]
wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:448:7]
wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7]
wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_iq_type_0; // @[util.scala:448:7]
wire [9:0] io_deq_bits_uop_fu_code_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_iw_state_0; // @[util.scala:448:7]
wire io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7]
wire io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_br_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_jal_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7]
wire io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7]
wire io_deq_bits_uop_taken_0; // @[util.scala:448:7]
wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7]
wire [11:0] io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:448:7]
wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7]
wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7]
wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7]
wire io_deq_bits_uop_exception_0; // @[util.scala:448:7]
wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7]
wire io_deq_bits_uop_bypassable_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:448:7]
wire io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_fence_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_amo_0; // @[util.scala:448:7]
wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7]
wire io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_unique_0; // @[util.scala:448:7]
wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7]
wire io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7]
wire io_deq_bits_uop_fp_val_0; // @[util.scala:448:7]
wire io_deq_bits_uop_fp_single_0; // @[util.scala:448:7]
wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7]
wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:448:7]
wire [33:0] io_deq_bits_addr_0; // @[util.scala:448:7]
wire [63:0] io_deq_bits_data_0; // @[util.scala:448:7]
wire io_deq_bits_is_hella_0; // @[util.scala:448:7]
wire io_deq_bits_tag_match_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_way_en; // @[util.scala:448:7]
wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:448:7]
wire io_deq_valid_0; // @[util.scala:448:7]
wire io_empty_0; // @[util.scala:448:7]
wire [3:0] io_count; // @[util.scala:448:7]
assign out_addr = _ram_ext_R0_data[33:0]; // @[util.scala:464:20, :506:17]
assign out_data = _ram_ext_R0_data[97:34]; // @[util.scala:464:20, :506:17]
assign out_is_hella = _ram_ext_R0_data[98]; // @[util.scala:464:20, :506:17]
assign out_tag_match = _ram_ext_R0_data[99]; // @[util.scala:464:20, :506:17]
assign out_old_meta_coh_state = _ram_ext_R0_data[101:100]; // @[util.scala:464:20, :506:17]
assign out_old_meta_tag = _ram_ext_R0_data[123:102]; // @[util.scala:464:20, :506:17]
assign out_way_en = _ram_ext_R0_data[125:124]; // @[util.scala:464:20, :506:17]
assign out_sdq_id = _ram_ext_R0_data[130:126]; // @[util.scala:464:20, :506:17]
reg valids_0; // @[util.scala:465:24]
wire _valids_0_T_3 = valids_0; // @[util.scala:465:24, :481:29]
reg valids_1; // @[util.scala:465:24]
wire _valids_1_T_3 = valids_1; // @[util.scala:465:24, :481:29]
reg valids_2; // @[util.scala:465:24]
wire _valids_2_T_3 = valids_2; // @[util.scala:465:24, :481:29]
reg valids_3; // @[util.scala:465:24]
wire _valids_3_T_3 = valids_3; // @[util.scala:465:24, :481:29]
reg valids_4; // @[util.scala:465:24]
wire _valids_4_T_3 = valids_4; // @[util.scala:465:24, :481:29]
reg valids_5; // @[util.scala:465:24]
wire _valids_5_T_3 = valids_5; // @[util.scala:465:24, :481:29]
reg valids_6; // @[util.scala:465:24]
wire _valids_6_T_3 = valids_6; // @[util.scala:465:24, :481:29]
reg valids_7; // @[util.scala:465:24]
wire _valids_7_T_3 = valids_7; // @[util.scala:465:24, :481:29]
reg valids_8; // @[util.scala:465:24]
wire _valids_8_T_3 = valids_8; // @[util.scala:465:24, :481:29]
reg valids_9; // @[util.scala:465:24]
wire _valids_9_T_3 = valids_9; // @[util.scala:465:24, :481:29]
reg valids_10; // @[util.scala:465:24]
wire _valids_10_T_3 = valids_10; // @[util.scala:465:24, :481:29]
reg valids_11; // @[util.scala:465:24]
wire _valids_11_T_3 = valids_11; // @[util.scala:465:24, :481:29]
reg valids_12; // @[util.scala:465:24]
wire _valids_12_T_3 = valids_12; // @[util.scala:465:24, :481:29]
reg valids_13; // @[util.scala:465:24]
wire _valids_13_T_3 = valids_13; // @[util.scala:465:24, :481:29]
reg valids_14; // @[util.scala:465:24]
wire _valids_14_T_3 = valids_14; // @[util.scala:465:24, :481:29]
reg valids_15; // @[util.scala:465:24]
wire _valids_15_T_3 = valids_15; // @[util.scala:465:24, :481:29]
reg [6:0] uops_0_uopc; // @[util.scala:466:20]
reg [31:0] uops_0_inst; // @[util.scala:466:20]
reg [31:0] uops_0_debug_inst; // @[util.scala:466:20]
reg uops_0_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_0_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_0_iq_type; // @[util.scala:466:20]
reg [9:0] uops_0_fu_code; // @[util.scala:466:20]
reg [3:0] uops_0_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_0_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_0_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_0_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_0_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_0_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_0_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_0_ctrl_is_load; // @[util.scala:466:20]
reg uops_0_ctrl_is_sta; // @[util.scala:466:20]
reg uops_0_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_0_iw_state; // @[util.scala:466:20]
reg uops_0_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_0_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_0_is_br; // @[util.scala:466:20]
reg uops_0_is_jalr; // @[util.scala:466:20]
reg uops_0_is_jal; // @[util.scala:466:20]
reg uops_0_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_0_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_0_br_mask_T_1 = uops_0_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_0_br_tag; // @[util.scala:466:20]
reg [3:0] uops_0_ftq_idx; // @[util.scala:466:20]
reg uops_0_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_0_pc_lob; // @[util.scala:466:20]
reg uops_0_taken; // @[util.scala:466:20]
reg [19:0] uops_0_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_0_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_0_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_0_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_0_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_0_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_0_pdst; // @[util.scala:466:20]
reg [6:0] uops_0_prs1; // @[util.scala:466:20]
reg [6:0] uops_0_prs2; // @[util.scala:466:20]
reg [6:0] uops_0_prs3; // @[util.scala:466:20]
reg [3:0] uops_0_ppred; // @[util.scala:466:20]
reg uops_0_prs1_busy; // @[util.scala:466:20]
reg uops_0_prs2_busy; // @[util.scala:466:20]
reg uops_0_prs3_busy; // @[util.scala:466:20]
reg uops_0_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_0_stale_pdst; // @[util.scala:466:20]
reg uops_0_exception; // @[util.scala:466:20]
reg [63:0] uops_0_exc_cause; // @[util.scala:466:20]
reg uops_0_bypassable; // @[util.scala:466:20]
reg [4:0] uops_0_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_0_mem_size; // @[util.scala:466:20]
reg uops_0_mem_signed; // @[util.scala:466:20]
reg uops_0_is_fence; // @[util.scala:466:20]
reg uops_0_is_fencei; // @[util.scala:466:20]
reg uops_0_is_amo; // @[util.scala:466:20]
reg uops_0_uses_ldq; // @[util.scala:466:20]
reg uops_0_uses_stq; // @[util.scala:466:20]
reg uops_0_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_0_is_unique; // @[util.scala:466:20]
reg uops_0_flush_on_commit; // @[util.scala:466:20]
reg uops_0_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_0_ldst; // @[util.scala:466:20]
reg [5:0] uops_0_lrs1; // @[util.scala:466:20]
reg [5:0] uops_0_lrs2; // @[util.scala:466:20]
reg [5:0] uops_0_lrs3; // @[util.scala:466:20]
reg uops_0_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_0_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_0_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_0_lrs2_rtype; // @[util.scala:466:20]
reg uops_0_frs3_en; // @[util.scala:466:20]
reg uops_0_fp_val; // @[util.scala:466:20]
reg uops_0_fp_single; // @[util.scala:466:20]
reg uops_0_xcpt_pf_if; // @[util.scala:466:20]
reg uops_0_xcpt_ae_if; // @[util.scala:466:20]
reg uops_0_xcpt_ma_if; // @[util.scala:466:20]
reg uops_0_bp_debug_if; // @[util.scala:466:20]
reg uops_0_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_0_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_0_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_1_uopc; // @[util.scala:466:20]
reg [31:0] uops_1_inst; // @[util.scala:466:20]
reg [31:0] uops_1_debug_inst; // @[util.scala:466:20]
reg uops_1_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_1_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_1_iq_type; // @[util.scala:466:20]
reg [9:0] uops_1_fu_code; // @[util.scala:466:20]
reg [3:0] uops_1_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_1_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_1_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_1_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_1_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_1_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_1_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_1_ctrl_is_load; // @[util.scala:466:20]
reg uops_1_ctrl_is_sta; // @[util.scala:466:20]
reg uops_1_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_1_iw_state; // @[util.scala:466:20]
reg uops_1_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_1_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_1_is_br; // @[util.scala:466:20]
reg uops_1_is_jalr; // @[util.scala:466:20]
reg uops_1_is_jal; // @[util.scala:466:20]
reg uops_1_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_1_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_1_br_mask_T_1 = uops_1_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_1_br_tag; // @[util.scala:466:20]
reg [3:0] uops_1_ftq_idx; // @[util.scala:466:20]
reg uops_1_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_1_pc_lob; // @[util.scala:466:20]
reg uops_1_taken; // @[util.scala:466:20]
reg [19:0] uops_1_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_1_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_1_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_1_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_1_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_1_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_1_pdst; // @[util.scala:466:20]
reg [6:0] uops_1_prs1; // @[util.scala:466:20]
reg [6:0] uops_1_prs2; // @[util.scala:466:20]
reg [6:0] uops_1_prs3; // @[util.scala:466:20]
reg [3:0] uops_1_ppred; // @[util.scala:466:20]
reg uops_1_prs1_busy; // @[util.scala:466:20]
reg uops_1_prs2_busy; // @[util.scala:466:20]
reg uops_1_prs3_busy; // @[util.scala:466:20]
reg uops_1_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_1_stale_pdst; // @[util.scala:466:20]
reg uops_1_exception; // @[util.scala:466:20]
reg [63:0] uops_1_exc_cause; // @[util.scala:466:20]
reg uops_1_bypassable; // @[util.scala:466:20]
reg [4:0] uops_1_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_1_mem_size; // @[util.scala:466:20]
reg uops_1_mem_signed; // @[util.scala:466:20]
reg uops_1_is_fence; // @[util.scala:466:20]
reg uops_1_is_fencei; // @[util.scala:466:20]
reg uops_1_is_amo; // @[util.scala:466:20]
reg uops_1_uses_ldq; // @[util.scala:466:20]
reg uops_1_uses_stq; // @[util.scala:466:20]
reg uops_1_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_1_is_unique; // @[util.scala:466:20]
reg uops_1_flush_on_commit; // @[util.scala:466:20]
reg uops_1_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_1_ldst; // @[util.scala:466:20]
reg [5:0] uops_1_lrs1; // @[util.scala:466:20]
reg [5:0] uops_1_lrs2; // @[util.scala:466:20]
reg [5:0] uops_1_lrs3; // @[util.scala:466:20]
reg uops_1_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_1_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_1_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_1_lrs2_rtype; // @[util.scala:466:20]
reg uops_1_frs3_en; // @[util.scala:466:20]
reg uops_1_fp_val; // @[util.scala:466:20]
reg uops_1_fp_single; // @[util.scala:466:20]
reg uops_1_xcpt_pf_if; // @[util.scala:466:20]
reg uops_1_xcpt_ae_if; // @[util.scala:466:20]
reg uops_1_xcpt_ma_if; // @[util.scala:466:20]
reg uops_1_bp_debug_if; // @[util.scala:466:20]
reg uops_1_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_1_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_1_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_2_uopc; // @[util.scala:466:20]
reg [31:0] uops_2_inst; // @[util.scala:466:20]
reg [31:0] uops_2_debug_inst; // @[util.scala:466:20]
reg uops_2_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_2_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_2_iq_type; // @[util.scala:466:20]
reg [9:0] uops_2_fu_code; // @[util.scala:466:20]
reg [3:0] uops_2_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_2_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_2_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_2_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_2_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_2_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_2_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_2_ctrl_is_load; // @[util.scala:466:20]
reg uops_2_ctrl_is_sta; // @[util.scala:466:20]
reg uops_2_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_2_iw_state; // @[util.scala:466:20]
reg uops_2_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_2_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_2_is_br; // @[util.scala:466:20]
reg uops_2_is_jalr; // @[util.scala:466:20]
reg uops_2_is_jal; // @[util.scala:466:20]
reg uops_2_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_2_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_2_br_mask_T_1 = uops_2_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_2_br_tag; // @[util.scala:466:20]
reg [3:0] uops_2_ftq_idx; // @[util.scala:466:20]
reg uops_2_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_2_pc_lob; // @[util.scala:466:20]
reg uops_2_taken; // @[util.scala:466:20]
reg [19:0] uops_2_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_2_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_2_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_2_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_2_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_2_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_2_pdst; // @[util.scala:466:20]
reg [6:0] uops_2_prs1; // @[util.scala:466:20]
reg [6:0] uops_2_prs2; // @[util.scala:466:20]
reg [6:0] uops_2_prs3; // @[util.scala:466:20]
reg [3:0] uops_2_ppred; // @[util.scala:466:20]
reg uops_2_prs1_busy; // @[util.scala:466:20]
reg uops_2_prs2_busy; // @[util.scala:466:20]
reg uops_2_prs3_busy; // @[util.scala:466:20]
reg uops_2_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_2_stale_pdst; // @[util.scala:466:20]
reg uops_2_exception; // @[util.scala:466:20]
reg [63:0] uops_2_exc_cause; // @[util.scala:466:20]
reg uops_2_bypassable; // @[util.scala:466:20]
reg [4:0] uops_2_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_2_mem_size; // @[util.scala:466:20]
reg uops_2_mem_signed; // @[util.scala:466:20]
reg uops_2_is_fence; // @[util.scala:466:20]
reg uops_2_is_fencei; // @[util.scala:466:20]
reg uops_2_is_amo; // @[util.scala:466:20]
reg uops_2_uses_ldq; // @[util.scala:466:20]
reg uops_2_uses_stq; // @[util.scala:466:20]
reg uops_2_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_2_is_unique; // @[util.scala:466:20]
reg uops_2_flush_on_commit; // @[util.scala:466:20]
reg uops_2_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_2_ldst; // @[util.scala:466:20]
reg [5:0] uops_2_lrs1; // @[util.scala:466:20]
reg [5:0] uops_2_lrs2; // @[util.scala:466:20]
reg [5:0] uops_2_lrs3; // @[util.scala:466:20]
reg uops_2_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_2_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_2_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_2_lrs2_rtype; // @[util.scala:466:20]
reg uops_2_frs3_en; // @[util.scala:466:20]
reg uops_2_fp_val; // @[util.scala:466:20]
reg uops_2_fp_single; // @[util.scala:466:20]
reg uops_2_xcpt_pf_if; // @[util.scala:466:20]
reg uops_2_xcpt_ae_if; // @[util.scala:466:20]
reg uops_2_xcpt_ma_if; // @[util.scala:466:20]
reg uops_2_bp_debug_if; // @[util.scala:466:20]
reg uops_2_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_2_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_2_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_3_uopc; // @[util.scala:466:20]
reg [31:0] uops_3_inst; // @[util.scala:466:20]
reg [31:0] uops_3_debug_inst; // @[util.scala:466:20]
reg uops_3_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_3_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_3_iq_type; // @[util.scala:466:20]
reg [9:0] uops_3_fu_code; // @[util.scala:466:20]
reg [3:0] uops_3_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_3_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_3_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_3_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_3_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_3_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_3_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_3_ctrl_is_load; // @[util.scala:466:20]
reg uops_3_ctrl_is_sta; // @[util.scala:466:20]
reg uops_3_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_3_iw_state; // @[util.scala:466:20]
reg uops_3_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_3_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_3_is_br; // @[util.scala:466:20]
reg uops_3_is_jalr; // @[util.scala:466:20]
reg uops_3_is_jal; // @[util.scala:466:20]
reg uops_3_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_3_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_3_br_mask_T_1 = uops_3_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_3_br_tag; // @[util.scala:466:20]
reg [3:0] uops_3_ftq_idx; // @[util.scala:466:20]
reg uops_3_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_3_pc_lob; // @[util.scala:466:20]
reg uops_3_taken; // @[util.scala:466:20]
reg [19:0] uops_3_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_3_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_3_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_3_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_3_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_3_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_3_pdst; // @[util.scala:466:20]
reg [6:0] uops_3_prs1; // @[util.scala:466:20]
reg [6:0] uops_3_prs2; // @[util.scala:466:20]
reg [6:0] uops_3_prs3; // @[util.scala:466:20]
reg [3:0] uops_3_ppred; // @[util.scala:466:20]
reg uops_3_prs1_busy; // @[util.scala:466:20]
reg uops_3_prs2_busy; // @[util.scala:466:20]
reg uops_3_prs3_busy; // @[util.scala:466:20]
reg uops_3_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_3_stale_pdst; // @[util.scala:466:20]
reg uops_3_exception; // @[util.scala:466:20]
reg [63:0] uops_3_exc_cause; // @[util.scala:466:20]
reg uops_3_bypassable; // @[util.scala:466:20]
reg [4:0] uops_3_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_3_mem_size; // @[util.scala:466:20]
reg uops_3_mem_signed; // @[util.scala:466:20]
reg uops_3_is_fence; // @[util.scala:466:20]
reg uops_3_is_fencei; // @[util.scala:466:20]
reg uops_3_is_amo; // @[util.scala:466:20]
reg uops_3_uses_ldq; // @[util.scala:466:20]
reg uops_3_uses_stq; // @[util.scala:466:20]
reg uops_3_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_3_is_unique; // @[util.scala:466:20]
reg uops_3_flush_on_commit; // @[util.scala:466:20]
reg uops_3_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_3_ldst; // @[util.scala:466:20]
reg [5:0] uops_3_lrs1; // @[util.scala:466:20]
reg [5:0] uops_3_lrs2; // @[util.scala:466:20]
reg [5:0] uops_3_lrs3; // @[util.scala:466:20]
reg uops_3_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_3_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_3_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_3_lrs2_rtype; // @[util.scala:466:20]
reg uops_3_frs3_en; // @[util.scala:466:20]
reg uops_3_fp_val; // @[util.scala:466:20]
reg uops_3_fp_single; // @[util.scala:466:20]
reg uops_3_xcpt_pf_if; // @[util.scala:466:20]
reg uops_3_xcpt_ae_if; // @[util.scala:466:20]
reg uops_3_xcpt_ma_if; // @[util.scala:466:20]
reg uops_3_bp_debug_if; // @[util.scala:466:20]
reg uops_3_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_3_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_3_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_4_uopc; // @[util.scala:466:20]
reg [31:0] uops_4_inst; // @[util.scala:466:20]
reg [31:0] uops_4_debug_inst; // @[util.scala:466:20]
reg uops_4_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_4_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_4_iq_type; // @[util.scala:466:20]
reg [9:0] uops_4_fu_code; // @[util.scala:466:20]
reg [3:0] uops_4_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_4_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_4_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_4_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_4_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_4_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_4_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_4_ctrl_is_load; // @[util.scala:466:20]
reg uops_4_ctrl_is_sta; // @[util.scala:466:20]
reg uops_4_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_4_iw_state; // @[util.scala:466:20]
reg uops_4_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_4_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_4_is_br; // @[util.scala:466:20]
reg uops_4_is_jalr; // @[util.scala:466:20]
reg uops_4_is_jal; // @[util.scala:466:20]
reg uops_4_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_4_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_4_br_mask_T_1 = uops_4_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_4_br_tag; // @[util.scala:466:20]
reg [3:0] uops_4_ftq_idx; // @[util.scala:466:20]
reg uops_4_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_4_pc_lob; // @[util.scala:466:20]
reg uops_4_taken; // @[util.scala:466:20]
reg [19:0] uops_4_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_4_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_4_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_4_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_4_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_4_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_4_pdst; // @[util.scala:466:20]
reg [6:0] uops_4_prs1; // @[util.scala:466:20]
reg [6:0] uops_4_prs2; // @[util.scala:466:20]
reg [6:0] uops_4_prs3; // @[util.scala:466:20]
reg [3:0] uops_4_ppred; // @[util.scala:466:20]
reg uops_4_prs1_busy; // @[util.scala:466:20]
reg uops_4_prs2_busy; // @[util.scala:466:20]
reg uops_4_prs3_busy; // @[util.scala:466:20]
reg uops_4_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_4_stale_pdst; // @[util.scala:466:20]
reg uops_4_exception; // @[util.scala:466:20]
reg [63:0] uops_4_exc_cause; // @[util.scala:466:20]
reg uops_4_bypassable; // @[util.scala:466:20]
reg [4:0] uops_4_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_4_mem_size; // @[util.scala:466:20]
reg uops_4_mem_signed; // @[util.scala:466:20]
reg uops_4_is_fence; // @[util.scala:466:20]
reg uops_4_is_fencei; // @[util.scala:466:20]
reg uops_4_is_amo; // @[util.scala:466:20]
reg uops_4_uses_ldq; // @[util.scala:466:20]
reg uops_4_uses_stq; // @[util.scala:466:20]
reg uops_4_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_4_is_unique; // @[util.scala:466:20]
reg uops_4_flush_on_commit; // @[util.scala:466:20]
reg uops_4_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_4_ldst; // @[util.scala:466:20]
reg [5:0] uops_4_lrs1; // @[util.scala:466:20]
reg [5:0] uops_4_lrs2; // @[util.scala:466:20]
reg [5:0] uops_4_lrs3; // @[util.scala:466:20]
reg uops_4_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_4_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_4_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_4_lrs2_rtype; // @[util.scala:466:20]
reg uops_4_frs3_en; // @[util.scala:466:20]
reg uops_4_fp_val; // @[util.scala:466:20]
reg uops_4_fp_single; // @[util.scala:466:20]
reg uops_4_xcpt_pf_if; // @[util.scala:466:20]
reg uops_4_xcpt_ae_if; // @[util.scala:466:20]
reg uops_4_xcpt_ma_if; // @[util.scala:466:20]
reg uops_4_bp_debug_if; // @[util.scala:466:20]
reg uops_4_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_4_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_4_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_5_uopc; // @[util.scala:466:20]
reg [31:0] uops_5_inst; // @[util.scala:466:20]
reg [31:0] uops_5_debug_inst; // @[util.scala:466:20]
reg uops_5_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_5_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_5_iq_type; // @[util.scala:466:20]
reg [9:0] uops_5_fu_code; // @[util.scala:466:20]
reg [3:0] uops_5_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_5_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_5_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_5_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_5_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_5_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_5_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_5_ctrl_is_load; // @[util.scala:466:20]
reg uops_5_ctrl_is_sta; // @[util.scala:466:20]
reg uops_5_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_5_iw_state; // @[util.scala:466:20]
reg uops_5_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_5_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_5_is_br; // @[util.scala:466:20]
reg uops_5_is_jalr; // @[util.scala:466:20]
reg uops_5_is_jal; // @[util.scala:466:20]
reg uops_5_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_5_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_5_br_mask_T_1 = uops_5_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_5_br_tag; // @[util.scala:466:20]
reg [3:0] uops_5_ftq_idx; // @[util.scala:466:20]
reg uops_5_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_5_pc_lob; // @[util.scala:466:20]
reg uops_5_taken; // @[util.scala:466:20]
reg [19:0] uops_5_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_5_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_5_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_5_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_5_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_5_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_5_pdst; // @[util.scala:466:20]
reg [6:0] uops_5_prs1; // @[util.scala:466:20]
reg [6:0] uops_5_prs2; // @[util.scala:466:20]
reg [6:0] uops_5_prs3; // @[util.scala:466:20]
reg [3:0] uops_5_ppred; // @[util.scala:466:20]
reg uops_5_prs1_busy; // @[util.scala:466:20]
reg uops_5_prs2_busy; // @[util.scala:466:20]
reg uops_5_prs3_busy; // @[util.scala:466:20]
reg uops_5_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_5_stale_pdst; // @[util.scala:466:20]
reg uops_5_exception; // @[util.scala:466:20]
reg [63:0] uops_5_exc_cause; // @[util.scala:466:20]
reg uops_5_bypassable; // @[util.scala:466:20]
reg [4:0] uops_5_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_5_mem_size; // @[util.scala:466:20]
reg uops_5_mem_signed; // @[util.scala:466:20]
reg uops_5_is_fence; // @[util.scala:466:20]
reg uops_5_is_fencei; // @[util.scala:466:20]
reg uops_5_is_amo; // @[util.scala:466:20]
reg uops_5_uses_ldq; // @[util.scala:466:20]
reg uops_5_uses_stq; // @[util.scala:466:20]
reg uops_5_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_5_is_unique; // @[util.scala:466:20]
reg uops_5_flush_on_commit; // @[util.scala:466:20]
reg uops_5_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_5_ldst; // @[util.scala:466:20]
reg [5:0] uops_5_lrs1; // @[util.scala:466:20]
reg [5:0] uops_5_lrs2; // @[util.scala:466:20]
reg [5:0] uops_5_lrs3; // @[util.scala:466:20]
reg uops_5_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_5_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_5_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_5_lrs2_rtype; // @[util.scala:466:20]
reg uops_5_frs3_en; // @[util.scala:466:20]
reg uops_5_fp_val; // @[util.scala:466:20]
reg uops_5_fp_single; // @[util.scala:466:20]
reg uops_5_xcpt_pf_if; // @[util.scala:466:20]
reg uops_5_xcpt_ae_if; // @[util.scala:466:20]
reg uops_5_xcpt_ma_if; // @[util.scala:466:20]
reg uops_5_bp_debug_if; // @[util.scala:466:20]
reg uops_5_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_5_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_5_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_6_uopc; // @[util.scala:466:20]
reg [31:0] uops_6_inst; // @[util.scala:466:20]
reg [31:0] uops_6_debug_inst; // @[util.scala:466:20]
reg uops_6_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_6_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_6_iq_type; // @[util.scala:466:20]
reg [9:0] uops_6_fu_code; // @[util.scala:466:20]
reg [3:0] uops_6_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_6_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_6_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_6_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_6_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_6_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_6_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_6_ctrl_is_load; // @[util.scala:466:20]
reg uops_6_ctrl_is_sta; // @[util.scala:466:20]
reg uops_6_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_6_iw_state; // @[util.scala:466:20]
reg uops_6_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_6_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_6_is_br; // @[util.scala:466:20]
reg uops_6_is_jalr; // @[util.scala:466:20]
reg uops_6_is_jal; // @[util.scala:466:20]
reg uops_6_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_6_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_6_br_mask_T_1 = uops_6_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_6_br_tag; // @[util.scala:466:20]
reg [3:0] uops_6_ftq_idx; // @[util.scala:466:20]
reg uops_6_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_6_pc_lob; // @[util.scala:466:20]
reg uops_6_taken; // @[util.scala:466:20]
reg [19:0] uops_6_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_6_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_6_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_6_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_6_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_6_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_6_pdst; // @[util.scala:466:20]
reg [6:0] uops_6_prs1; // @[util.scala:466:20]
reg [6:0] uops_6_prs2; // @[util.scala:466:20]
reg [6:0] uops_6_prs3; // @[util.scala:466:20]
reg [3:0] uops_6_ppred; // @[util.scala:466:20]
reg uops_6_prs1_busy; // @[util.scala:466:20]
reg uops_6_prs2_busy; // @[util.scala:466:20]
reg uops_6_prs3_busy; // @[util.scala:466:20]
reg uops_6_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_6_stale_pdst; // @[util.scala:466:20]
reg uops_6_exception; // @[util.scala:466:20]
reg [63:0] uops_6_exc_cause; // @[util.scala:466:20]
reg uops_6_bypassable; // @[util.scala:466:20]
reg [4:0] uops_6_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_6_mem_size; // @[util.scala:466:20]
reg uops_6_mem_signed; // @[util.scala:466:20]
reg uops_6_is_fence; // @[util.scala:466:20]
reg uops_6_is_fencei; // @[util.scala:466:20]
reg uops_6_is_amo; // @[util.scala:466:20]
reg uops_6_uses_ldq; // @[util.scala:466:20]
reg uops_6_uses_stq; // @[util.scala:466:20]
reg uops_6_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_6_is_unique; // @[util.scala:466:20]
reg uops_6_flush_on_commit; // @[util.scala:466:20]
reg uops_6_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_6_ldst; // @[util.scala:466:20]
reg [5:0] uops_6_lrs1; // @[util.scala:466:20]
reg [5:0] uops_6_lrs2; // @[util.scala:466:20]
reg [5:0] uops_6_lrs3; // @[util.scala:466:20]
reg uops_6_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_6_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_6_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_6_lrs2_rtype; // @[util.scala:466:20]
reg uops_6_frs3_en; // @[util.scala:466:20]
reg uops_6_fp_val; // @[util.scala:466:20]
reg uops_6_fp_single; // @[util.scala:466:20]
reg uops_6_xcpt_pf_if; // @[util.scala:466:20]
reg uops_6_xcpt_ae_if; // @[util.scala:466:20]
reg uops_6_xcpt_ma_if; // @[util.scala:466:20]
reg uops_6_bp_debug_if; // @[util.scala:466:20]
reg uops_6_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_6_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_6_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_7_uopc; // @[util.scala:466:20]
reg [31:0] uops_7_inst; // @[util.scala:466:20]
reg [31:0] uops_7_debug_inst; // @[util.scala:466:20]
reg uops_7_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_7_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_7_iq_type; // @[util.scala:466:20]
reg [9:0] uops_7_fu_code; // @[util.scala:466:20]
reg [3:0] uops_7_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_7_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_7_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_7_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_7_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_7_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_7_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_7_ctrl_is_load; // @[util.scala:466:20]
reg uops_7_ctrl_is_sta; // @[util.scala:466:20]
reg uops_7_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_7_iw_state; // @[util.scala:466:20]
reg uops_7_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_7_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_7_is_br; // @[util.scala:466:20]
reg uops_7_is_jalr; // @[util.scala:466:20]
reg uops_7_is_jal; // @[util.scala:466:20]
reg uops_7_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_7_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_7_br_mask_T_1 = uops_7_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_7_br_tag; // @[util.scala:466:20]
reg [3:0] uops_7_ftq_idx; // @[util.scala:466:20]
reg uops_7_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_7_pc_lob; // @[util.scala:466:20]
reg uops_7_taken; // @[util.scala:466:20]
reg [19:0] uops_7_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_7_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_7_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_7_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_7_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_7_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_7_pdst; // @[util.scala:466:20]
reg [6:0] uops_7_prs1; // @[util.scala:466:20]
reg [6:0] uops_7_prs2; // @[util.scala:466:20]
reg [6:0] uops_7_prs3; // @[util.scala:466:20]
reg [3:0] uops_7_ppred; // @[util.scala:466:20]
reg uops_7_prs1_busy; // @[util.scala:466:20]
reg uops_7_prs2_busy; // @[util.scala:466:20]
reg uops_7_prs3_busy; // @[util.scala:466:20]
reg uops_7_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_7_stale_pdst; // @[util.scala:466:20]
reg uops_7_exception; // @[util.scala:466:20]
reg [63:0] uops_7_exc_cause; // @[util.scala:466:20]
reg uops_7_bypassable; // @[util.scala:466:20]
reg [4:0] uops_7_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_7_mem_size; // @[util.scala:466:20]
reg uops_7_mem_signed; // @[util.scala:466:20]
reg uops_7_is_fence; // @[util.scala:466:20]
reg uops_7_is_fencei; // @[util.scala:466:20]
reg uops_7_is_amo; // @[util.scala:466:20]
reg uops_7_uses_ldq; // @[util.scala:466:20]
reg uops_7_uses_stq; // @[util.scala:466:20]
reg uops_7_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_7_is_unique; // @[util.scala:466:20]
reg uops_7_flush_on_commit; // @[util.scala:466:20]
reg uops_7_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_7_ldst; // @[util.scala:466:20]
reg [5:0] uops_7_lrs1; // @[util.scala:466:20]
reg [5:0] uops_7_lrs2; // @[util.scala:466:20]
reg [5:0] uops_7_lrs3; // @[util.scala:466:20]
reg uops_7_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_7_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_7_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_7_lrs2_rtype; // @[util.scala:466:20]
reg uops_7_frs3_en; // @[util.scala:466:20]
reg uops_7_fp_val; // @[util.scala:466:20]
reg uops_7_fp_single; // @[util.scala:466:20]
reg uops_7_xcpt_pf_if; // @[util.scala:466:20]
reg uops_7_xcpt_ae_if; // @[util.scala:466:20]
reg uops_7_xcpt_ma_if; // @[util.scala:466:20]
reg uops_7_bp_debug_if; // @[util.scala:466:20]
reg uops_7_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_7_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_7_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_8_uopc; // @[util.scala:466:20]
reg [31:0] uops_8_inst; // @[util.scala:466:20]
reg [31:0] uops_8_debug_inst; // @[util.scala:466:20]
reg uops_8_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_8_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_8_iq_type; // @[util.scala:466:20]
reg [9:0] uops_8_fu_code; // @[util.scala:466:20]
reg [3:0] uops_8_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_8_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_8_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_8_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_8_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_8_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_8_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_8_ctrl_is_load; // @[util.scala:466:20]
reg uops_8_ctrl_is_sta; // @[util.scala:466:20]
reg uops_8_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_8_iw_state; // @[util.scala:466:20]
reg uops_8_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_8_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_8_is_br; // @[util.scala:466:20]
reg uops_8_is_jalr; // @[util.scala:466:20]
reg uops_8_is_jal; // @[util.scala:466:20]
reg uops_8_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_8_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_8_br_mask_T_1 = uops_8_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_8_br_tag; // @[util.scala:466:20]
reg [3:0] uops_8_ftq_idx; // @[util.scala:466:20]
reg uops_8_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_8_pc_lob; // @[util.scala:466:20]
reg uops_8_taken; // @[util.scala:466:20]
reg [19:0] uops_8_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_8_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_8_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_8_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_8_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_8_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_8_pdst; // @[util.scala:466:20]
reg [6:0] uops_8_prs1; // @[util.scala:466:20]
reg [6:0] uops_8_prs2; // @[util.scala:466:20]
reg [6:0] uops_8_prs3; // @[util.scala:466:20]
reg [3:0] uops_8_ppred; // @[util.scala:466:20]
reg uops_8_prs1_busy; // @[util.scala:466:20]
reg uops_8_prs2_busy; // @[util.scala:466:20]
reg uops_8_prs3_busy; // @[util.scala:466:20]
reg uops_8_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_8_stale_pdst; // @[util.scala:466:20]
reg uops_8_exception; // @[util.scala:466:20]
reg [63:0] uops_8_exc_cause; // @[util.scala:466:20]
reg uops_8_bypassable; // @[util.scala:466:20]
reg [4:0] uops_8_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_8_mem_size; // @[util.scala:466:20]
reg uops_8_mem_signed; // @[util.scala:466:20]
reg uops_8_is_fence; // @[util.scala:466:20]
reg uops_8_is_fencei; // @[util.scala:466:20]
reg uops_8_is_amo; // @[util.scala:466:20]
reg uops_8_uses_ldq; // @[util.scala:466:20]
reg uops_8_uses_stq; // @[util.scala:466:20]
reg uops_8_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_8_is_unique; // @[util.scala:466:20]
reg uops_8_flush_on_commit; // @[util.scala:466:20]
reg uops_8_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_8_ldst; // @[util.scala:466:20]
reg [5:0] uops_8_lrs1; // @[util.scala:466:20]
reg [5:0] uops_8_lrs2; // @[util.scala:466:20]
reg [5:0] uops_8_lrs3; // @[util.scala:466:20]
reg uops_8_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_8_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_8_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_8_lrs2_rtype; // @[util.scala:466:20]
reg uops_8_frs3_en; // @[util.scala:466:20]
reg uops_8_fp_val; // @[util.scala:466:20]
reg uops_8_fp_single; // @[util.scala:466:20]
reg uops_8_xcpt_pf_if; // @[util.scala:466:20]
reg uops_8_xcpt_ae_if; // @[util.scala:466:20]
reg uops_8_xcpt_ma_if; // @[util.scala:466:20]
reg uops_8_bp_debug_if; // @[util.scala:466:20]
reg uops_8_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_8_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_8_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_9_uopc; // @[util.scala:466:20]
reg [31:0] uops_9_inst; // @[util.scala:466:20]
reg [31:0] uops_9_debug_inst; // @[util.scala:466:20]
reg uops_9_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_9_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_9_iq_type; // @[util.scala:466:20]
reg [9:0] uops_9_fu_code; // @[util.scala:466:20]
reg [3:0] uops_9_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_9_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_9_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_9_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_9_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_9_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_9_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_9_ctrl_is_load; // @[util.scala:466:20]
reg uops_9_ctrl_is_sta; // @[util.scala:466:20]
reg uops_9_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_9_iw_state; // @[util.scala:466:20]
reg uops_9_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_9_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_9_is_br; // @[util.scala:466:20]
reg uops_9_is_jalr; // @[util.scala:466:20]
reg uops_9_is_jal; // @[util.scala:466:20]
reg uops_9_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_9_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_9_br_mask_T_1 = uops_9_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_9_br_tag; // @[util.scala:466:20]
reg [3:0] uops_9_ftq_idx; // @[util.scala:466:20]
reg uops_9_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_9_pc_lob; // @[util.scala:466:20]
reg uops_9_taken; // @[util.scala:466:20]
reg [19:0] uops_9_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_9_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_9_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_9_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_9_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_9_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_9_pdst; // @[util.scala:466:20]
reg [6:0] uops_9_prs1; // @[util.scala:466:20]
reg [6:0] uops_9_prs2; // @[util.scala:466:20]
reg [6:0] uops_9_prs3; // @[util.scala:466:20]
reg [3:0] uops_9_ppred; // @[util.scala:466:20]
reg uops_9_prs1_busy; // @[util.scala:466:20]
reg uops_9_prs2_busy; // @[util.scala:466:20]
reg uops_9_prs3_busy; // @[util.scala:466:20]
reg uops_9_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_9_stale_pdst; // @[util.scala:466:20]
reg uops_9_exception; // @[util.scala:466:20]
reg [63:0] uops_9_exc_cause; // @[util.scala:466:20]
reg uops_9_bypassable; // @[util.scala:466:20]
reg [4:0] uops_9_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_9_mem_size; // @[util.scala:466:20]
reg uops_9_mem_signed; // @[util.scala:466:20]
reg uops_9_is_fence; // @[util.scala:466:20]
reg uops_9_is_fencei; // @[util.scala:466:20]
reg uops_9_is_amo; // @[util.scala:466:20]
reg uops_9_uses_ldq; // @[util.scala:466:20]
reg uops_9_uses_stq; // @[util.scala:466:20]
reg uops_9_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_9_is_unique; // @[util.scala:466:20]
reg uops_9_flush_on_commit; // @[util.scala:466:20]
reg uops_9_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_9_ldst; // @[util.scala:466:20]
reg [5:0] uops_9_lrs1; // @[util.scala:466:20]
reg [5:0] uops_9_lrs2; // @[util.scala:466:20]
reg [5:0] uops_9_lrs3; // @[util.scala:466:20]
reg uops_9_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_9_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_9_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_9_lrs2_rtype; // @[util.scala:466:20]
reg uops_9_frs3_en; // @[util.scala:466:20]
reg uops_9_fp_val; // @[util.scala:466:20]
reg uops_9_fp_single; // @[util.scala:466:20]
reg uops_9_xcpt_pf_if; // @[util.scala:466:20]
reg uops_9_xcpt_ae_if; // @[util.scala:466:20]
reg uops_9_xcpt_ma_if; // @[util.scala:466:20]
reg uops_9_bp_debug_if; // @[util.scala:466:20]
reg uops_9_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_9_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_9_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_10_uopc; // @[util.scala:466:20]
reg [31:0] uops_10_inst; // @[util.scala:466:20]
reg [31:0] uops_10_debug_inst; // @[util.scala:466:20]
reg uops_10_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_10_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_10_iq_type; // @[util.scala:466:20]
reg [9:0] uops_10_fu_code; // @[util.scala:466:20]
reg [3:0] uops_10_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_10_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_10_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_10_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_10_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_10_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_10_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_10_ctrl_is_load; // @[util.scala:466:20]
reg uops_10_ctrl_is_sta; // @[util.scala:466:20]
reg uops_10_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_10_iw_state; // @[util.scala:466:20]
reg uops_10_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_10_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_10_is_br; // @[util.scala:466:20]
reg uops_10_is_jalr; // @[util.scala:466:20]
reg uops_10_is_jal; // @[util.scala:466:20]
reg uops_10_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_10_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_10_br_mask_T_1 = uops_10_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_10_br_tag; // @[util.scala:466:20]
reg [3:0] uops_10_ftq_idx; // @[util.scala:466:20]
reg uops_10_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_10_pc_lob; // @[util.scala:466:20]
reg uops_10_taken; // @[util.scala:466:20]
reg [19:0] uops_10_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_10_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_10_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_10_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_10_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_10_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_10_pdst; // @[util.scala:466:20]
reg [6:0] uops_10_prs1; // @[util.scala:466:20]
reg [6:0] uops_10_prs2; // @[util.scala:466:20]
reg [6:0] uops_10_prs3; // @[util.scala:466:20]
reg [3:0] uops_10_ppred; // @[util.scala:466:20]
reg uops_10_prs1_busy; // @[util.scala:466:20]
reg uops_10_prs2_busy; // @[util.scala:466:20]
reg uops_10_prs3_busy; // @[util.scala:466:20]
reg uops_10_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_10_stale_pdst; // @[util.scala:466:20]
reg uops_10_exception; // @[util.scala:466:20]
reg [63:0] uops_10_exc_cause; // @[util.scala:466:20]
reg uops_10_bypassable; // @[util.scala:466:20]
reg [4:0] uops_10_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_10_mem_size; // @[util.scala:466:20]
reg uops_10_mem_signed; // @[util.scala:466:20]
reg uops_10_is_fence; // @[util.scala:466:20]
reg uops_10_is_fencei; // @[util.scala:466:20]
reg uops_10_is_amo; // @[util.scala:466:20]
reg uops_10_uses_ldq; // @[util.scala:466:20]
reg uops_10_uses_stq; // @[util.scala:466:20]
reg uops_10_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_10_is_unique; // @[util.scala:466:20]
reg uops_10_flush_on_commit; // @[util.scala:466:20]
reg uops_10_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_10_ldst; // @[util.scala:466:20]
reg [5:0] uops_10_lrs1; // @[util.scala:466:20]
reg [5:0] uops_10_lrs2; // @[util.scala:466:20]
reg [5:0] uops_10_lrs3; // @[util.scala:466:20]
reg uops_10_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_10_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_10_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_10_lrs2_rtype; // @[util.scala:466:20]
reg uops_10_frs3_en; // @[util.scala:466:20]
reg uops_10_fp_val; // @[util.scala:466:20]
reg uops_10_fp_single; // @[util.scala:466:20]
reg uops_10_xcpt_pf_if; // @[util.scala:466:20]
reg uops_10_xcpt_ae_if; // @[util.scala:466:20]
reg uops_10_xcpt_ma_if; // @[util.scala:466:20]
reg uops_10_bp_debug_if; // @[util.scala:466:20]
reg uops_10_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_10_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_10_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_11_uopc; // @[util.scala:466:20]
reg [31:0] uops_11_inst; // @[util.scala:466:20]
reg [31:0] uops_11_debug_inst; // @[util.scala:466:20]
reg uops_11_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_11_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_11_iq_type; // @[util.scala:466:20]
reg [9:0] uops_11_fu_code; // @[util.scala:466:20]
reg [3:0] uops_11_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_11_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_11_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_11_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_11_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_11_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_11_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_11_ctrl_is_load; // @[util.scala:466:20]
reg uops_11_ctrl_is_sta; // @[util.scala:466:20]
reg uops_11_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_11_iw_state; // @[util.scala:466:20]
reg uops_11_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_11_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_11_is_br; // @[util.scala:466:20]
reg uops_11_is_jalr; // @[util.scala:466:20]
reg uops_11_is_jal; // @[util.scala:466:20]
reg uops_11_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_11_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_11_br_mask_T_1 = uops_11_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_11_br_tag; // @[util.scala:466:20]
reg [3:0] uops_11_ftq_idx; // @[util.scala:466:20]
reg uops_11_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_11_pc_lob; // @[util.scala:466:20]
reg uops_11_taken; // @[util.scala:466:20]
reg [19:0] uops_11_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_11_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_11_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_11_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_11_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_11_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_11_pdst; // @[util.scala:466:20]
reg [6:0] uops_11_prs1; // @[util.scala:466:20]
reg [6:0] uops_11_prs2; // @[util.scala:466:20]
reg [6:0] uops_11_prs3; // @[util.scala:466:20]
reg [3:0] uops_11_ppred; // @[util.scala:466:20]
reg uops_11_prs1_busy; // @[util.scala:466:20]
reg uops_11_prs2_busy; // @[util.scala:466:20]
reg uops_11_prs3_busy; // @[util.scala:466:20]
reg uops_11_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_11_stale_pdst; // @[util.scala:466:20]
reg uops_11_exception; // @[util.scala:466:20]
reg [63:0] uops_11_exc_cause; // @[util.scala:466:20]
reg uops_11_bypassable; // @[util.scala:466:20]
reg [4:0] uops_11_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_11_mem_size; // @[util.scala:466:20]
reg uops_11_mem_signed; // @[util.scala:466:20]
reg uops_11_is_fence; // @[util.scala:466:20]
reg uops_11_is_fencei; // @[util.scala:466:20]
reg uops_11_is_amo; // @[util.scala:466:20]
reg uops_11_uses_ldq; // @[util.scala:466:20]
reg uops_11_uses_stq; // @[util.scala:466:20]
reg uops_11_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_11_is_unique; // @[util.scala:466:20]
reg uops_11_flush_on_commit; // @[util.scala:466:20]
reg uops_11_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_11_ldst; // @[util.scala:466:20]
reg [5:0] uops_11_lrs1; // @[util.scala:466:20]
reg [5:0] uops_11_lrs2; // @[util.scala:466:20]
reg [5:0] uops_11_lrs3; // @[util.scala:466:20]
reg uops_11_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_11_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_11_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_11_lrs2_rtype; // @[util.scala:466:20]
reg uops_11_frs3_en; // @[util.scala:466:20]
reg uops_11_fp_val; // @[util.scala:466:20]
reg uops_11_fp_single; // @[util.scala:466:20]
reg uops_11_xcpt_pf_if; // @[util.scala:466:20]
reg uops_11_xcpt_ae_if; // @[util.scala:466:20]
reg uops_11_xcpt_ma_if; // @[util.scala:466:20]
reg uops_11_bp_debug_if; // @[util.scala:466:20]
reg uops_11_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_11_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_11_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_12_uopc; // @[util.scala:466:20]
reg [31:0] uops_12_inst; // @[util.scala:466:20]
reg [31:0] uops_12_debug_inst; // @[util.scala:466:20]
reg uops_12_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_12_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_12_iq_type; // @[util.scala:466:20]
reg [9:0] uops_12_fu_code; // @[util.scala:466:20]
reg [3:0] uops_12_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_12_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_12_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_12_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_12_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_12_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_12_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_12_ctrl_is_load; // @[util.scala:466:20]
reg uops_12_ctrl_is_sta; // @[util.scala:466:20]
reg uops_12_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_12_iw_state; // @[util.scala:466:20]
reg uops_12_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_12_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_12_is_br; // @[util.scala:466:20]
reg uops_12_is_jalr; // @[util.scala:466:20]
reg uops_12_is_jal; // @[util.scala:466:20]
reg uops_12_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_12_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_12_br_mask_T_1 = uops_12_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_12_br_tag; // @[util.scala:466:20]
reg [3:0] uops_12_ftq_idx; // @[util.scala:466:20]
reg uops_12_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_12_pc_lob; // @[util.scala:466:20]
reg uops_12_taken; // @[util.scala:466:20]
reg [19:0] uops_12_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_12_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_12_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_12_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_12_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_12_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_12_pdst; // @[util.scala:466:20]
reg [6:0] uops_12_prs1; // @[util.scala:466:20]
reg [6:0] uops_12_prs2; // @[util.scala:466:20]
reg [6:0] uops_12_prs3; // @[util.scala:466:20]
reg [3:0] uops_12_ppred; // @[util.scala:466:20]
reg uops_12_prs1_busy; // @[util.scala:466:20]
reg uops_12_prs2_busy; // @[util.scala:466:20]
reg uops_12_prs3_busy; // @[util.scala:466:20]
reg uops_12_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_12_stale_pdst; // @[util.scala:466:20]
reg uops_12_exception; // @[util.scala:466:20]
reg [63:0] uops_12_exc_cause; // @[util.scala:466:20]
reg uops_12_bypassable; // @[util.scala:466:20]
reg [4:0] uops_12_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_12_mem_size; // @[util.scala:466:20]
reg uops_12_mem_signed; // @[util.scala:466:20]
reg uops_12_is_fence; // @[util.scala:466:20]
reg uops_12_is_fencei; // @[util.scala:466:20]
reg uops_12_is_amo; // @[util.scala:466:20]
reg uops_12_uses_ldq; // @[util.scala:466:20]
reg uops_12_uses_stq; // @[util.scala:466:20]
reg uops_12_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_12_is_unique; // @[util.scala:466:20]
reg uops_12_flush_on_commit; // @[util.scala:466:20]
reg uops_12_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_12_ldst; // @[util.scala:466:20]
reg [5:0] uops_12_lrs1; // @[util.scala:466:20]
reg [5:0] uops_12_lrs2; // @[util.scala:466:20]
reg [5:0] uops_12_lrs3; // @[util.scala:466:20]
reg uops_12_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_12_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_12_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_12_lrs2_rtype; // @[util.scala:466:20]
reg uops_12_frs3_en; // @[util.scala:466:20]
reg uops_12_fp_val; // @[util.scala:466:20]
reg uops_12_fp_single; // @[util.scala:466:20]
reg uops_12_xcpt_pf_if; // @[util.scala:466:20]
reg uops_12_xcpt_ae_if; // @[util.scala:466:20]
reg uops_12_xcpt_ma_if; // @[util.scala:466:20]
reg uops_12_bp_debug_if; // @[util.scala:466:20]
reg uops_12_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_12_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_12_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_13_uopc; // @[util.scala:466:20]
reg [31:0] uops_13_inst; // @[util.scala:466:20]
reg [31:0] uops_13_debug_inst; // @[util.scala:466:20]
reg uops_13_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_13_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_13_iq_type; // @[util.scala:466:20]
reg [9:0] uops_13_fu_code; // @[util.scala:466:20]
reg [3:0] uops_13_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_13_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_13_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_13_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_13_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_13_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_13_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_13_ctrl_is_load; // @[util.scala:466:20]
reg uops_13_ctrl_is_sta; // @[util.scala:466:20]
reg uops_13_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_13_iw_state; // @[util.scala:466:20]
reg uops_13_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_13_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_13_is_br; // @[util.scala:466:20]
reg uops_13_is_jalr; // @[util.scala:466:20]
reg uops_13_is_jal; // @[util.scala:466:20]
reg uops_13_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_13_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_13_br_mask_T_1 = uops_13_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_13_br_tag; // @[util.scala:466:20]
reg [3:0] uops_13_ftq_idx; // @[util.scala:466:20]
reg uops_13_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_13_pc_lob; // @[util.scala:466:20]
reg uops_13_taken; // @[util.scala:466:20]
reg [19:0] uops_13_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_13_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_13_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_13_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_13_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_13_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_13_pdst; // @[util.scala:466:20]
reg [6:0] uops_13_prs1; // @[util.scala:466:20]
reg [6:0] uops_13_prs2; // @[util.scala:466:20]
reg [6:0] uops_13_prs3; // @[util.scala:466:20]
reg [3:0] uops_13_ppred; // @[util.scala:466:20]
reg uops_13_prs1_busy; // @[util.scala:466:20]
reg uops_13_prs2_busy; // @[util.scala:466:20]
reg uops_13_prs3_busy; // @[util.scala:466:20]
reg uops_13_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_13_stale_pdst; // @[util.scala:466:20]
reg uops_13_exception; // @[util.scala:466:20]
reg [63:0] uops_13_exc_cause; // @[util.scala:466:20]
reg uops_13_bypassable; // @[util.scala:466:20]
reg [4:0] uops_13_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_13_mem_size; // @[util.scala:466:20]
reg uops_13_mem_signed; // @[util.scala:466:20]
reg uops_13_is_fence; // @[util.scala:466:20]
reg uops_13_is_fencei; // @[util.scala:466:20]
reg uops_13_is_amo; // @[util.scala:466:20]
reg uops_13_uses_ldq; // @[util.scala:466:20]
reg uops_13_uses_stq; // @[util.scala:466:20]
reg uops_13_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_13_is_unique; // @[util.scala:466:20]
reg uops_13_flush_on_commit; // @[util.scala:466:20]
reg uops_13_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_13_ldst; // @[util.scala:466:20]
reg [5:0] uops_13_lrs1; // @[util.scala:466:20]
reg [5:0] uops_13_lrs2; // @[util.scala:466:20]
reg [5:0] uops_13_lrs3; // @[util.scala:466:20]
reg uops_13_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_13_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_13_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_13_lrs2_rtype; // @[util.scala:466:20]
reg uops_13_frs3_en; // @[util.scala:466:20]
reg uops_13_fp_val; // @[util.scala:466:20]
reg uops_13_fp_single; // @[util.scala:466:20]
reg uops_13_xcpt_pf_if; // @[util.scala:466:20]
reg uops_13_xcpt_ae_if; // @[util.scala:466:20]
reg uops_13_xcpt_ma_if; // @[util.scala:466:20]
reg uops_13_bp_debug_if; // @[util.scala:466:20]
reg uops_13_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_13_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_13_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_14_uopc; // @[util.scala:466:20]
reg [31:0] uops_14_inst; // @[util.scala:466:20]
reg [31:0] uops_14_debug_inst; // @[util.scala:466:20]
reg uops_14_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_14_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_14_iq_type; // @[util.scala:466:20]
reg [9:0] uops_14_fu_code; // @[util.scala:466:20]
reg [3:0] uops_14_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_14_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_14_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_14_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_14_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_14_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_14_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_14_ctrl_is_load; // @[util.scala:466:20]
reg uops_14_ctrl_is_sta; // @[util.scala:466:20]
reg uops_14_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_14_iw_state; // @[util.scala:466:20]
reg uops_14_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_14_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_14_is_br; // @[util.scala:466:20]
reg uops_14_is_jalr; // @[util.scala:466:20]
reg uops_14_is_jal; // @[util.scala:466:20]
reg uops_14_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_14_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_14_br_mask_T_1 = uops_14_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_14_br_tag; // @[util.scala:466:20]
reg [3:0] uops_14_ftq_idx; // @[util.scala:466:20]
reg uops_14_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_14_pc_lob; // @[util.scala:466:20]
reg uops_14_taken; // @[util.scala:466:20]
reg [19:0] uops_14_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_14_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_14_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_14_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_14_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_14_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_14_pdst; // @[util.scala:466:20]
reg [6:0] uops_14_prs1; // @[util.scala:466:20]
reg [6:0] uops_14_prs2; // @[util.scala:466:20]
reg [6:0] uops_14_prs3; // @[util.scala:466:20]
reg [3:0] uops_14_ppred; // @[util.scala:466:20]
reg uops_14_prs1_busy; // @[util.scala:466:20]
reg uops_14_prs2_busy; // @[util.scala:466:20]
reg uops_14_prs3_busy; // @[util.scala:466:20]
reg uops_14_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_14_stale_pdst; // @[util.scala:466:20]
reg uops_14_exception; // @[util.scala:466:20]
reg [63:0] uops_14_exc_cause; // @[util.scala:466:20]
reg uops_14_bypassable; // @[util.scala:466:20]
reg [4:0] uops_14_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_14_mem_size; // @[util.scala:466:20]
reg uops_14_mem_signed; // @[util.scala:466:20]
reg uops_14_is_fence; // @[util.scala:466:20]
reg uops_14_is_fencei; // @[util.scala:466:20]
reg uops_14_is_amo; // @[util.scala:466:20]
reg uops_14_uses_ldq; // @[util.scala:466:20]
reg uops_14_uses_stq; // @[util.scala:466:20]
reg uops_14_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_14_is_unique; // @[util.scala:466:20]
reg uops_14_flush_on_commit; // @[util.scala:466:20]
reg uops_14_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_14_ldst; // @[util.scala:466:20]
reg [5:0] uops_14_lrs1; // @[util.scala:466:20]
reg [5:0] uops_14_lrs2; // @[util.scala:466:20]
reg [5:0] uops_14_lrs3; // @[util.scala:466:20]
reg uops_14_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_14_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_14_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_14_lrs2_rtype; // @[util.scala:466:20]
reg uops_14_frs3_en; // @[util.scala:466:20]
reg uops_14_fp_val; // @[util.scala:466:20]
reg uops_14_fp_single; // @[util.scala:466:20]
reg uops_14_xcpt_pf_if; // @[util.scala:466:20]
reg uops_14_xcpt_ae_if; // @[util.scala:466:20]
reg uops_14_xcpt_ma_if; // @[util.scala:466:20]
reg uops_14_bp_debug_if; // @[util.scala:466:20]
reg uops_14_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_14_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_14_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_15_uopc; // @[util.scala:466:20]
reg [31:0] uops_15_inst; // @[util.scala:466:20]
reg [31:0] uops_15_debug_inst; // @[util.scala:466:20]
reg uops_15_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_15_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_15_iq_type; // @[util.scala:466:20]
reg [9:0] uops_15_fu_code; // @[util.scala:466:20]
reg [3:0] uops_15_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_15_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_15_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_15_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_15_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_15_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_15_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_15_ctrl_is_load; // @[util.scala:466:20]
reg uops_15_ctrl_is_sta; // @[util.scala:466:20]
reg uops_15_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_15_iw_state; // @[util.scala:466:20]
reg uops_15_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_15_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_15_is_br; // @[util.scala:466:20]
reg uops_15_is_jalr; // @[util.scala:466:20]
reg uops_15_is_jal; // @[util.scala:466:20]
reg uops_15_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_15_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_15_br_mask_T_1 = uops_15_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_15_br_tag; // @[util.scala:466:20]
reg [3:0] uops_15_ftq_idx; // @[util.scala:466:20]
reg uops_15_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_15_pc_lob; // @[util.scala:466:20]
reg uops_15_taken; // @[util.scala:466:20]
reg [19:0] uops_15_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_15_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_15_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_15_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_15_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_15_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_15_pdst; // @[util.scala:466:20]
reg [6:0] uops_15_prs1; // @[util.scala:466:20]
reg [6:0] uops_15_prs2; // @[util.scala:466:20]
reg [6:0] uops_15_prs3; // @[util.scala:466:20]
reg [3:0] uops_15_ppred; // @[util.scala:466:20]
reg uops_15_prs1_busy; // @[util.scala:466:20]
reg uops_15_prs2_busy; // @[util.scala:466:20]
reg uops_15_prs3_busy; // @[util.scala:466:20]
reg uops_15_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_15_stale_pdst; // @[util.scala:466:20]
reg uops_15_exception; // @[util.scala:466:20]
reg [63:0] uops_15_exc_cause; // @[util.scala:466:20]
reg uops_15_bypassable; // @[util.scala:466:20]
reg [4:0] uops_15_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_15_mem_size; // @[util.scala:466:20]
reg uops_15_mem_signed; // @[util.scala:466:20]
reg uops_15_is_fence; // @[util.scala:466:20]
reg uops_15_is_fencei; // @[util.scala:466:20]
reg uops_15_is_amo; // @[util.scala:466:20]
reg uops_15_uses_ldq; // @[util.scala:466:20]
reg uops_15_uses_stq; // @[util.scala:466:20]
reg uops_15_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_15_is_unique; // @[util.scala:466:20]
reg uops_15_flush_on_commit; // @[util.scala:466:20]
reg uops_15_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_15_ldst; // @[util.scala:466:20]
reg [5:0] uops_15_lrs1; // @[util.scala:466:20]
reg [5:0] uops_15_lrs2; // @[util.scala:466:20]
reg [5:0] uops_15_lrs3; // @[util.scala:466:20]
reg uops_15_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_15_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_15_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_15_lrs2_rtype; // @[util.scala:466:20]
reg uops_15_frs3_en; // @[util.scala:466:20]
reg uops_15_fp_val; // @[util.scala:466:20]
reg uops_15_fp_single; // @[util.scala:466:20]
reg uops_15_xcpt_pf_if; // @[util.scala:466:20]
reg uops_15_xcpt_ae_if; // @[util.scala:466:20]
reg uops_15_xcpt_ma_if; // @[util.scala:466:20]
reg uops_15_bp_debug_if; // @[util.scala:466:20]
reg uops_15_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_15_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_15_debug_tsrc; // @[util.scala:466:20]
reg [3:0] enq_ptr_value; // @[Counter.scala:61:40]
reg [3:0] deq_ptr_value; // @[Counter.scala:61:40]
reg maybe_full; // @[util.scala:470:27]
wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40]
wire _io_empty_T = ~maybe_full; // @[util.scala:470:27, :473:28]
assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:472:33, :473:{25,28}]
assign io_empty_0 = _io_empty_T_1; // @[util.scala:448:7, :473:25]
wire _GEN = ptr_match & maybe_full; // @[util.scala:470:27, :472:33, :474:24]
wire full; // @[util.scala:474:24]
assign full = _GEN; // @[util.scala:474:24]
wire _io_count_T; // @[util.scala:526:32]
assign _io_count_T = _GEN; // @[util.scala:474:24, :526:32]
wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire do_enq = _do_enq_T; // @[Decoupled.scala:51:35]
wire [15:0] _GEN_0 = {{valids_15}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:465:24, :476:42]
wire _GEN_1 = _GEN_0[deq_ptr_value]; // @[Counter.scala:61:40]
wire _do_deq_T = ~_GEN_1; // @[util.scala:476:42]
wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:448:7, :476:{39,42}]
wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:448:7, :476:69]
wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:476:{39,66,69}]
wire do_deq = _do_deq_T_3; // @[util.scala:476:{24,66}]
wire _valids_0_T_6 = _valids_0_T_3; // @[util.scala:481:{29,69}]
wire _valids_1_T_6 = _valids_1_T_3; // @[util.scala:481:{29,69}]
wire _valids_2_T_6 = _valids_2_T_3; // @[util.scala:481:{29,69}]
wire _valids_3_T_6 = _valids_3_T_3; // @[util.scala:481:{29,69}]
wire _valids_4_T_6 = _valids_4_T_3; // @[util.scala:481:{29,69}]
wire _valids_5_T_6 = _valids_5_T_3; // @[util.scala:481:{29,69}]
wire _valids_6_T_6 = _valids_6_T_3; // @[util.scala:481:{29,69}]
wire _valids_7_T_6 = _valids_7_T_3; // @[util.scala:481:{29,69}]
wire _valids_8_T_6 = _valids_8_T_3; // @[util.scala:481:{29,69}]
wire _valids_9_T_6 = _valids_9_T_3; // @[util.scala:481:{29,69}]
wire _valids_10_T_6 = _valids_10_T_3; // @[util.scala:481:{29,69}]
wire _valids_11_T_6 = _valids_11_T_3; // @[util.scala:481:{29,69}]
wire _valids_12_T_6 = _valids_12_T_3; // @[util.scala:481:{29,69}]
wire _valids_13_T_6 = _valids_13_T_3; // @[util.scala:481:{29,69}]
wire _valids_14_T_6 = _valids_14_T_3; // @[util.scala:481:{29,69}]
wire _valids_15_T_6 = _valids_15_T_3; // @[util.scala:481:{29,69}]
wire wrap = &enq_ptr_value; // @[Counter.scala:61:40, :73:24]
wire [4:0] _GEN_2 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [4:0] _value_T = _GEN_2 + 5'h1; // @[Counter.scala:77:24]
wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24]
wire wrap_1 = &deq_ptr_value; // @[Counter.scala:61:40, :73:24]
wire [4:0] _GEN_3 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [4:0] _value_T_2 = _GEN_3 + 5'h1; // @[Counter.scala:77:24]
wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24]
assign _io_enq_ready_T = ~full; // @[util.scala:474:24, :504:19]
assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:448:7, :504:19]
assign io_deq_bits_uop_uopc_0 = out_uop_uopc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_iq_type_0 = out_uop_iq_type; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_fu_code_0 = out_uop_fu_code; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_br_type_0 = out_uop_ctrl_br_type; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_op1_sel_0 = out_uop_ctrl_op1_sel; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_op2_sel_0 = out_uop_ctrl_op2_sel; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_imm_sel_0 = out_uop_ctrl_imm_sel; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_op_fcn_0 = out_uop_ctrl_op_fcn; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_fcn_dw_0 = out_uop_ctrl_fcn_dw; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_csr_cmd_0 = out_uop_ctrl_csr_cmd; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_is_load_0 = out_uop_ctrl_is_load; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_is_sta_0 = out_uop_ctrl_is_sta; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_is_std_0 = out_uop_ctrl_is_std; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_iw_state_0 = out_uop_iw_state; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_iw_p1_poisoned_0 = out_uop_iw_p1_poisoned; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_iw_p2_poisoned_0 = out_uop_iw_p2_poisoned; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_br_0 = out_uop_is_br; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_jalr_0 = out_uop_is_jalr; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_jal_0 = out_uop_is_jal; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:448:7, :506:17]
assign _io_deq_bits_uop_br_mask_T_1 = out_uop_br_mask; // @[util.scala:85:25, :506:17]
assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_csr_addr_0 = out_uop_csr_addr; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_bypassable_0 = out_uop_bypassable; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ldst_val_0 = out_uop_ldst_val; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_fp_single_0 = out_uop_fp_single; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_addr_0 = out_addr; // @[util.scala:448:7, :506:17]
assign io_deq_bits_data_0 = out_data; // @[util.scala:448:7, :506:17]
assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:448:7, :506:17]
assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:448:7, :506:17]
assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:448:7, :506:17]
assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:448:7, :506:17]
assign io_deq_bits_way_en = out_way_en; // @[util.scala:448:7, :506:17]
assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:448:7, :506:17]
wire [15:0][6:0] _GEN_4 = {{uops_15_uopc}, {uops_14_uopc}, {uops_13_uopc}, {uops_12_uopc}, {uops_11_uopc}, {uops_10_uopc}, {uops_9_uopc}, {uops_8_uopc}, {uops_7_uopc}, {uops_6_uopc}, {uops_5_uopc}, {uops_4_uopc}, {uops_3_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}}; // @[util.scala:466:20, :508:19]
assign out_uop_uopc = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][31:0] _GEN_5 = {{uops_15_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:466:20, :508:19]
assign out_uop_inst = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][31:0] _GEN_6 = {{uops_15_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_inst = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_7 = {{uops_15_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_rvc = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][33:0] _GEN_8 = {{uops_15_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_pc = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_9 = {{uops_15_iq_type}, {uops_14_iq_type}, {uops_13_iq_type}, {uops_12_iq_type}, {uops_11_iq_type}, {uops_10_iq_type}, {uops_9_iq_type}, {uops_8_iq_type}, {uops_7_iq_type}, {uops_6_iq_type}, {uops_5_iq_type}, {uops_4_iq_type}, {uops_3_iq_type}, {uops_2_iq_type}, {uops_1_iq_type}, {uops_0_iq_type}}; // @[util.scala:466:20, :508:19]
assign out_uop_iq_type = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][9:0] _GEN_10 = {{uops_15_fu_code}, {uops_14_fu_code}, {uops_13_fu_code}, {uops_12_fu_code}, {uops_11_fu_code}, {uops_10_fu_code}, {uops_9_fu_code}, {uops_8_fu_code}, {uops_7_fu_code}, {uops_6_fu_code}, {uops_5_fu_code}, {uops_4_fu_code}, {uops_3_fu_code}, {uops_2_fu_code}, {uops_1_fu_code}, {uops_0_fu_code}}; // @[util.scala:466:20, :508:19]
assign out_uop_fu_code = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_11 = {{uops_15_ctrl_br_type}, {uops_14_ctrl_br_type}, {uops_13_ctrl_br_type}, {uops_12_ctrl_br_type}, {uops_11_ctrl_br_type}, {uops_10_ctrl_br_type}, {uops_9_ctrl_br_type}, {uops_8_ctrl_br_type}, {uops_7_ctrl_br_type}, {uops_6_ctrl_br_type}, {uops_5_ctrl_br_type}, {uops_4_ctrl_br_type}, {uops_3_ctrl_br_type}, {uops_2_ctrl_br_type}, {uops_1_ctrl_br_type}, {uops_0_ctrl_br_type}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_br_type = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_12 = {{uops_15_ctrl_op1_sel}, {uops_14_ctrl_op1_sel}, {uops_13_ctrl_op1_sel}, {uops_12_ctrl_op1_sel}, {uops_11_ctrl_op1_sel}, {uops_10_ctrl_op1_sel}, {uops_9_ctrl_op1_sel}, {uops_8_ctrl_op1_sel}, {uops_7_ctrl_op1_sel}, {uops_6_ctrl_op1_sel}, {uops_5_ctrl_op1_sel}, {uops_4_ctrl_op1_sel}, {uops_3_ctrl_op1_sel}, {uops_2_ctrl_op1_sel}, {uops_1_ctrl_op1_sel}, {uops_0_ctrl_op1_sel}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_op1_sel = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_13 = {{uops_15_ctrl_op2_sel}, {uops_14_ctrl_op2_sel}, {uops_13_ctrl_op2_sel}, {uops_12_ctrl_op2_sel}, {uops_11_ctrl_op2_sel}, {uops_10_ctrl_op2_sel}, {uops_9_ctrl_op2_sel}, {uops_8_ctrl_op2_sel}, {uops_7_ctrl_op2_sel}, {uops_6_ctrl_op2_sel}, {uops_5_ctrl_op2_sel}, {uops_4_ctrl_op2_sel}, {uops_3_ctrl_op2_sel}, {uops_2_ctrl_op2_sel}, {uops_1_ctrl_op2_sel}, {uops_0_ctrl_op2_sel}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_op2_sel = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_14 = {{uops_15_ctrl_imm_sel}, {uops_14_ctrl_imm_sel}, {uops_13_ctrl_imm_sel}, {uops_12_ctrl_imm_sel}, {uops_11_ctrl_imm_sel}, {uops_10_ctrl_imm_sel}, {uops_9_ctrl_imm_sel}, {uops_8_ctrl_imm_sel}, {uops_7_ctrl_imm_sel}, {uops_6_ctrl_imm_sel}, {uops_5_ctrl_imm_sel}, {uops_4_ctrl_imm_sel}, {uops_3_ctrl_imm_sel}, {uops_2_ctrl_imm_sel}, {uops_1_ctrl_imm_sel}, {uops_0_ctrl_imm_sel}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_imm_sel = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_15 = {{uops_15_ctrl_op_fcn}, {uops_14_ctrl_op_fcn}, {uops_13_ctrl_op_fcn}, {uops_12_ctrl_op_fcn}, {uops_11_ctrl_op_fcn}, {uops_10_ctrl_op_fcn}, {uops_9_ctrl_op_fcn}, {uops_8_ctrl_op_fcn}, {uops_7_ctrl_op_fcn}, {uops_6_ctrl_op_fcn}, {uops_5_ctrl_op_fcn}, {uops_4_ctrl_op_fcn}, {uops_3_ctrl_op_fcn}, {uops_2_ctrl_op_fcn}, {uops_1_ctrl_op_fcn}, {uops_0_ctrl_op_fcn}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_op_fcn = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_16 = {{uops_15_ctrl_fcn_dw}, {uops_14_ctrl_fcn_dw}, {uops_13_ctrl_fcn_dw}, {uops_12_ctrl_fcn_dw}, {uops_11_ctrl_fcn_dw}, {uops_10_ctrl_fcn_dw}, {uops_9_ctrl_fcn_dw}, {uops_8_ctrl_fcn_dw}, {uops_7_ctrl_fcn_dw}, {uops_6_ctrl_fcn_dw}, {uops_5_ctrl_fcn_dw}, {uops_4_ctrl_fcn_dw}, {uops_3_ctrl_fcn_dw}, {uops_2_ctrl_fcn_dw}, {uops_1_ctrl_fcn_dw}, {uops_0_ctrl_fcn_dw}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_fcn_dw = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_17 = {{uops_15_ctrl_csr_cmd}, {uops_14_ctrl_csr_cmd}, {uops_13_ctrl_csr_cmd}, {uops_12_ctrl_csr_cmd}, {uops_11_ctrl_csr_cmd}, {uops_10_ctrl_csr_cmd}, {uops_9_ctrl_csr_cmd}, {uops_8_ctrl_csr_cmd}, {uops_7_ctrl_csr_cmd}, {uops_6_ctrl_csr_cmd}, {uops_5_ctrl_csr_cmd}, {uops_4_ctrl_csr_cmd}, {uops_3_ctrl_csr_cmd}, {uops_2_ctrl_csr_cmd}, {uops_1_ctrl_csr_cmd}, {uops_0_ctrl_csr_cmd}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_csr_cmd = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_18 = {{uops_15_ctrl_is_load}, {uops_14_ctrl_is_load}, {uops_13_ctrl_is_load}, {uops_12_ctrl_is_load}, {uops_11_ctrl_is_load}, {uops_10_ctrl_is_load}, {uops_9_ctrl_is_load}, {uops_8_ctrl_is_load}, {uops_7_ctrl_is_load}, {uops_6_ctrl_is_load}, {uops_5_ctrl_is_load}, {uops_4_ctrl_is_load}, {uops_3_ctrl_is_load}, {uops_2_ctrl_is_load}, {uops_1_ctrl_is_load}, {uops_0_ctrl_is_load}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_is_load = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_19 = {{uops_15_ctrl_is_sta}, {uops_14_ctrl_is_sta}, {uops_13_ctrl_is_sta}, {uops_12_ctrl_is_sta}, {uops_11_ctrl_is_sta}, {uops_10_ctrl_is_sta}, {uops_9_ctrl_is_sta}, {uops_8_ctrl_is_sta}, {uops_7_ctrl_is_sta}, {uops_6_ctrl_is_sta}, {uops_5_ctrl_is_sta}, {uops_4_ctrl_is_sta}, {uops_3_ctrl_is_sta}, {uops_2_ctrl_is_sta}, {uops_1_ctrl_is_sta}, {uops_0_ctrl_is_sta}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_is_sta = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_20 = {{uops_15_ctrl_is_std}, {uops_14_ctrl_is_std}, {uops_13_ctrl_is_std}, {uops_12_ctrl_is_std}, {uops_11_ctrl_is_std}, {uops_10_ctrl_is_std}, {uops_9_ctrl_is_std}, {uops_8_ctrl_is_std}, {uops_7_ctrl_is_std}, {uops_6_ctrl_is_std}, {uops_5_ctrl_is_std}, {uops_4_ctrl_is_std}, {uops_3_ctrl_is_std}, {uops_2_ctrl_is_std}, {uops_1_ctrl_is_std}, {uops_0_ctrl_is_std}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_is_std = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_21 = {{uops_15_iw_state}, {uops_14_iw_state}, {uops_13_iw_state}, {uops_12_iw_state}, {uops_11_iw_state}, {uops_10_iw_state}, {uops_9_iw_state}, {uops_8_iw_state}, {uops_7_iw_state}, {uops_6_iw_state}, {uops_5_iw_state}, {uops_4_iw_state}, {uops_3_iw_state}, {uops_2_iw_state}, {uops_1_iw_state}, {uops_0_iw_state}}; // @[util.scala:466:20, :508:19]
assign out_uop_iw_state = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_22 = {{uops_15_iw_p1_poisoned}, {uops_14_iw_p1_poisoned}, {uops_13_iw_p1_poisoned}, {uops_12_iw_p1_poisoned}, {uops_11_iw_p1_poisoned}, {uops_10_iw_p1_poisoned}, {uops_9_iw_p1_poisoned}, {uops_8_iw_p1_poisoned}, {uops_7_iw_p1_poisoned}, {uops_6_iw_p1_poisoned}, {uops_5_iw_p1_poisoned}, {uops_4_iw_p1_poisoned}, {uops_3_iw_p1_poisoned}, {uops_2_iw_p1_poisoned}, {uops_1_iw_p1_poisoned}, {uops_0_iw_p1_poisoned}}; // @[util.scala:466:20, :508:19]
assign out_uop_iw_p1_poisoned = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_23 = {{uops_15_iw_p2_poisoned}, {uops_14_iw_p2_poisoned}, {uops_13_iw_p2_poisoned}, {uops_12_iw_p2_poisoned}, {uops_11_iw_p2_poisoned}, {uops_10_iw_p2_poisoned}, {uops_9_iw_p2_poisoned}, {uops_8_iw_p2_poisoned}, {uops_7_iw_p2_poisoned}, {uops_6_iw_p2_poisoned}, {uops_5_iw_p2_poisoned}, {uops_4_iw_p2_poisoned}, {uops_3_iw_p2_poisoned}, {uops_2_iw_p2_poisoned}, {uops_1_iw_p2_poisoned}, {uops_0_iw_p2_poisoned}}; // @[util.scala:466:20, :508:19]
assign out_uop_iw_p2_poisoned = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_24 = {{uops_15_is_br}, {uops_14_is_br}, {uops_13_is_br}, {uops_12_is_br}, {uops_11_is_br}, {uops_10_is_br}, {uops_9_is_br}, {uops_8_is_br}, {uops_7_is_br}, {uops_6_is_br}, {uops_5_is_br}, {uops_4_is_br}, {uops_3_is_br}, {uops_2_is_br}, {uops_1_is_br}, {uops_0_is_br}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_br = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_25 = {{uops_15_is_jalr}, {uops_14_is_jalr}, {uops_13_is_jalr}, {uops_12_is_jalr}, {uops_11_is_jalr}, {uops_10_is_jalr}, {uops_9_is_jalr}, {uops_8_is_jalr}, {uops_7_is_jalr}, {uops_6_is_jalr}, {uops_5_is_jalr}, {uops_4_is_jalr}, {uops_3_is_jalr}, {uops_2_is_jalr}, {uops_1_is_jalr}, {uops_0_is_jalr}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_jalr = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_26 = {{uops_15_is_jal}, {uops_14_is_jal}, {uops_13_is_jal}, {uops_12_is_jal}, {uops_11_is_jal}, {uops_10_is_jal}, {uops_9_is_jal}, {uops_8_is_jal}, {uops_7_is_jal}, {uops_6_is_jal}, {uops_5_is_jal}, {uops_4_is_jal}, {uops_3_is_jal}, {uops_2_is_jal}, {uops_1_is_jal}, {uops_0_is_jal}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_jal = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_27 = {{uops_15_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_sfb = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_28 = {{uops_15_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:466:20, :508:19]
assign out_uop_br_mask = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_29 = {{uops_15_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:466:20, :508:19]
assign out_uop_br_tag = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_30 = {{uops_15_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_ftq_idx = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_31 = {{uops_15_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:466:20, :508:19]
assign out_uop_edge_inst = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_32 = {{uops_15_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:466:20, :508:19]
assign out_uop_pc_lob = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_33 = {{uops_15_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:466:20, :508:19]
assign out_uop_taken = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][19:0] _GEN_34 = {{uops_15_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:466:20, :508:19]
assign out_uop_imm_packed = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][11:0] _GEN_35 = {{uops_15_csr_addr}, {uops_14_csr_addr}, {uops_13_csr_addr}, {uops_12_csr_addr}, {uops_11_csr_addr}, {uops_10_csr_addr}, {uops_9_csr_addr}, {uops_8_csr_addr}, {uops_7_csr_addr}, {uops_6_csr_addr}, {uops_5_csr_addr}, {uops_4_csr_addr}, {uops_3_csr_addr}, {uops_2_csr_addr}, {uops_1_csr_addr}, {uops_0_csr_addr}}; // @[util.scala:466:20, :508:19]
assign out_uop_csr_addr = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_36 = {{uops_15_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_rob_idx = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_37 = {{uops_15_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldq_idx = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_38 = {{uops_15_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_stq_idx = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_39 = {{uops_15_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_rxq_idx = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_40 = {{uops_15_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:466:20, :508:19]
assign out_uop_pdst = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_41 = {{uops_15_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs1 = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_42 = {{uops_15_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs2 = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_43 = {{uops_15_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs3 = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_44 = {{uops_15_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:466:20, :508:19]
assign out_uop_ppred = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_45 = {{uops_15_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs1_busy = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_46 = {{uops_15_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs2_busy = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_47 = {{uops_15_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs3_busy = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_48 = {{uops_15_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_ppred_busy = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_49 = {{uops_15_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:466:20, :508:19]
assign out_uop_stale_pdst = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_50 = {{uops_15_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:466:20, :508:19]
assign out_uop_exception = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][63:0] _GEN_51 = {{uops_15_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:466:20, :508:19]
assign out_uop_exc_cause = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_52 = {{uops_15_bypassable}, {uops_14_bypassable}, {uops_13_bypassable}, {uops_12_bypassable}, {uops_11_bypassable}, {uops_10_bypassable}, {uops_9_bypassable}, {uops_8_bypassable}, {uops_7_bypassable}, {uops_6_bypassable}, {uops_5_bypassable}, {uops_4_bypassable}, {uops_3_bypassable}, {uops_2_bypassable}, {uops_1_bypassable}, {uops_0_bypassable}}; // @[util.scala:466:20, :508:19]
assign out_uop_bypassable = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_53 = {{uops_15_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:466:20, :508:19]
assign out_uop_mem_cmd = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_54 = {{uops_15_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:466:20, :508:19]
assign out_uop_mem_size = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_55 = {{uops_15_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:466:20, :508:19]
assign out_uop_mem_signed = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_56 = {{uops_15_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_fence = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_57 = {{uops_15_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_fencei = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_58 = {{uops_15_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_amo = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_59 = {{uops_15_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:466:20, :508:19]
assign out_uop_uses_ldq = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_60 = {{uops_15_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:466:20, :508:19]
assign out_uop_uses_stq = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_61 = {{uops_15_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_sys_pc2epc = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_62 = {{uops_15_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_unique = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_63 = {{uops_15_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:466:20, :508:19]
assign out_uop_flush_on_commit = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_64 = {{uops_15_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldst_is_rs1 = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_65 = {{uops_15_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldst = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_66 = {{uops_15_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs1 = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_67 = {{uops_15_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs2 = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_68 = {{uops_15_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs3 = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_69 = {{uops_15_ldst_val}, {uops_14_ldst_val}, {uops_13_ldst_val}, {uops_12_ldst_val}, {uops_11_ldst_val}, {uops_10_ldst_val}, {uops_9_ldst_val}, {uops_8_ldst_val}, {uops_7_ldst_val}, {uops_6_ldst_val}, {uops_5_ldst_val}, {uops_4_ldst_val}, {uops_3_ldst_val}, {uops_2_ldst_val}, {uops_1_ldst_val}, {uops_0_ldst_val}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldst_val = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_70 = {{uops_15_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:466:20, :508:19]
assign out_uop_dst_rtype = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_71 = {{uops_15_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs1_rtype = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_72 = {{uops_15_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs2_rtype = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_73 = {{uops_15_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:466:20, :508:19]
assign out_uop_frs3_en = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_74 = {{uops_15_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:466:20, :508:19]
assign out_uop_fp_val = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_75 = {{uops_15_fp_single}, {uops_14_fp_single}, {uops_13_fp_single}, {uops_12_fp_single}, {uops_11_fp_single}, {uops_10_fp_single}, {uops_9_fp_single}, {uops_8_fp_single}, {uops_7_fp_single}, {uops_6_fp_single}, {uops_5_fp_single}, {uops_4_fp_single}, {uops_3_fp_single}, {uops_2_fp_single}, {uops_1_fp_single}, {uops_0_fp_single}}; // @[util.scala:466:20, :508:19]
assign out_uop_fp_single = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_76 = {{uops_15_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_xcpt_pf_if = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_77 = {{uops_15_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_xcpt_ae_if = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_78 = {{uops_15_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_xcpt_ma_if = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_79 = {{uops_15_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_bp_debug_if = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_80 = {{uops_15_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_bp_xcpt_if = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_81 = {{uops_15_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_fsrc = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_82 = {{uops_15_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_tsrc = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40]
wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:448:7, :476:69, :509:30]
wire _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_1; // @[util.scala:476:42, :509:{30,40}]
wire _io_deq_valid_T_5 = _io_deq_valid_T_1; // @[util.scala:509:{40,65}]
assign _io_deq_valid_T_8 = _io_deq_valid_T_5; // @[util.scala:509:{65,108}]
assign io_deq_valid_0 = _io_deq_valid_T_8; // @[util.scala:448:7, :509:108]
assign io_deq_bits_uop_br_mask_0 = _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25, :448:7]
wire [4:0] _ptr_diff_T = _GEN_2 - _GEN_3; // @[Counter.scala:77:24]
wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:524:40]
wire [4:0] _io_count_T_1 = {_io_count_T, ptr_diff}; // @[util.scala:524:40, :526:{20,32}]
assign io_count = _io_count_T_1[3:0]; // @[util.scala:448:7, :526:{14,20}]
wire _GEN_83 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40]
wire _GEN_84 = do_enq & _GEN_83; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_85 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40]
wire _GEN_86 = do_enq & _GEN_85; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_87 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40]
wire _GEN_88 = do_enq & _GEN_87; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_89 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40]
wire _GEN_90 = do_enq & _GEN_89; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_91 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40]
wire _GEN_92 = do_enq & _GEN_91; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_93 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40]
wire _GEN_94 = do_enq & _GEN_93; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_95 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40]
wire _GEN_96 = do_enq & _GEN_95; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_97 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40]
wire _GEN_98 = do_enq & _GEN_97; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_99 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40]
wire _GEN_100 = do_enq & _GEN_99; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_101 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40]
wire _GEN_102 = do_enq & _GEN_101; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_103 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40]
wire _GEN_104 = do_enq & _GEN_103; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_105 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40]
wire _GEN_106 = do_enq & _GEN_105; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_107 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40]
wire _GEN_108 = do_enq & _GEN_107; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_109 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40]
wire _GEN_110 = do_enq & _GEN_109; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_111 = enq_ptr_value == 4'hE; // @[Counter.scala:61:40]
wire _GEN_112 = do_enq & _GEN_111; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_113 = do_enq & (&enq_ptr_value); // @[Counter.scala:61:40]
always @(posedge clock) begin // @[util.scala:448:7]
if (reset) begin // @[util.scala:448:7]
valids_0 <= 1'h0; // @[util.scala:465:24]
valids_1 <= 1'h0; // @[util.scala:465:24]
valids_2 <= 1'h0; // @[util.scala:465:24]
valids_3 <= 1'h0; // @[util.scala:465:24]
valids_4 <= 1'h0; // @[util.scala:465:24]
valids_5 <= 1'h0; // @[util.scala:465:24]
valids_6 <= 1'h0; // @[util.scala:465:24]
valids_7 <= 1'h0; // @[util.scala:465:24]
valids_8 <= 1'h0; // @[util.scala:465:24]
valids_9 <= 1'h0; // @[util.scala:465:24]
valids_10 <= 1'h0; // @[util.scala:465:24]
valids_11 <= 1'h0; // @[util.scala:465:24]
valids_12 <= 1'h0; // @[util.scala:465:24]
valids_13 <= 1'h0; // @[util.scala:465:24]
valids_14 <= 1'h0; // @[util.scala:465:24]
valids_15 <= 1'h0; // @[util.scala:465:24]
enq_ptr_value <= 4'h0; // @[Counter.scala:61:40]
deq_ptr_value <= 4'h0; // @[Counter.scala:61:40]
maybe_full <= 1'h0; // @[util.scala:470:27]
end
else begin // @[util.scala:448:7]
valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_84 | _valids_0_T_6); // @[Counter.scala:61:40]
valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_86 | _valids_1_T_6); // @[Counter.scala:61:40]
valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_88 | _valids_2_T_6); // @[Counter.scala:61:40]
valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_90 | _valids_3_T_6); // @[Counter.scala:61:40]
valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_92 | _valids_4_T_6); // @[Counter.scala:61:40]
valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_94 | _valids_5_T_6); // @[Counter.scala:61:40]
valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_96 | _valids_6_T_6); // @[Counter.scala:61:40]
valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_98 | _valids_7_T_6); // @[Counter.scala:61:40]
valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_100 | _valids_8_T_6); // @[Counter.scala:61:40]
valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_102 | _valids_9_T_6); // @[Counter.scala:61:40]
valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_104 | _valids_10_T_6); // @[Counter.scala:61:40]
valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_106 | _valids_11_T_6); // @[Counter.scala:61:40]
valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_108 | _valids_12_T_6); // @[Counter.scala:61:40]
valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_110 | _valids_13_T_6); // @[Counter.scala:61:40]
valids_14 <= ~(do_deq & deq_ptr_value == 4'hE) & (_GEN_112 | _valids_14_T_6); // @[Counter.scala:61:40]
valids_15 <= ~(do_deq & (&deq_ptr_value)) & (_GEN_113 | _valids_15_T_6); // @[Counter.scala:61:40]
if (do_enq) // @[util.scala:475:24]
enq_ptr_value <= _value_T_1; // @[Counter.scala:61:40, :77:24]
if (do_deq) // @[util.scala:476:24]
deq_ptr_value <= _value_T_3; // @[Counter.scala:61:40, :77:24]
if (~(do_enq == do_deq)) // @[util.scala:470:27, :475:24, :476:24, :500:{16,28}, :501:16]
maybe_full <= do_enq; // @[util.scala:470:27, :475:24]
end
if (_GEN_84) begin // @[util.scala:481:16, :487:17, :489:33]
uops_0_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_0_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_0_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_0_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_0_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_0_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_0_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_0_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_0_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_0_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_0_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_0_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_0_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_83) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_0) // @[util.scala:465:24]
uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_86) begin // @[util.scala:481:16, :487:17, :489:33]
uops_1_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_1_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_1_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_1_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_1_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_1_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_1_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_1_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_1_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_1_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_1_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_1_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_1_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_85) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_1) // @[util.scala:465:24]
uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_88) begin // @[util.scala:481:16, :487:17, :489:33]
uops_2_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_2_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_2_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_2_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_2_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_2_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_2_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_2_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_2_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_2_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_2_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_2_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_2_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_87) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_2) // @[util.scala:465:24]
uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_90) begin // @[util.scala:481:16, :487:17, :489:33]
uops_3_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_3_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_3_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_3_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_3_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_3_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_3_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_3_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_3_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_3_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_3_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_3_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_3_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_89) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_3) // @[util.scala:465:24]
uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_92) begin // @[util.scala:481:16, :487:17, :489:33]
uops_4_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_4_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_4_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_4_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_4_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_4_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_4_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_4_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_4_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_4_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_4_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_4_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_4_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_91) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_4) // @[util.scala:465:24]
uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_94) begin // @[util.scala:481:16, :487:17, :489:33]
uops_5_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_5_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_5_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_5_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_5_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_5_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_5_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_5_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_5_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_5_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_5_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_5_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_5_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_93) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_5) // @[util.scala:465:24]
uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_96) begin // @[util.scala:481:16, :487:17, :489:33]
uops_6_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_6_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_6_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_6_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_6_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_6_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_6_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_6_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_6_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_6_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_6_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_6_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_6_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_95) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_6) // @[util.scala:465:24]
uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_98) begin // @[util.scala:481:16, :487:17, :489:33]
uops_7_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_7_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_7_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_7_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_7_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_7_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_7_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_7_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_7_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_7_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_7_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_7_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_7_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_97) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_7) // @[util.scala:465:24]
uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_100) begin // @[util.scala:481:16, :487:17, :489:33]
uops_8_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_8_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_8_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_8_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_8_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_8_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_8_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_8_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_8_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_8_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_8_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_8_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_8_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_99) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_8) // @[util.scala:465:24]
uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_102) begin // @[util.scala:481:16, :487:17, :489:33]
uops_9_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_9_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_9_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_9_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_9_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_9_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_9_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_9_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_9_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_9_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_9_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_9_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_9_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_101) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_9) // @[util.scala:465:24]
uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_104) begin // @[util.scala:481:16, :487:17, :489:33]
uops_10_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_10_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_10_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_10_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_10_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_10_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_10_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_10_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_10_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_10_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_10_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_10_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_10_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_103) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_10) // @[util.scala:465:24]
uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_106) begin // @[util.scala:481:16, :487:17, :489:33]
uops_11_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_11_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_11_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_11_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_11_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_11_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_11_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_11_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_11_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_11_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_11_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_11_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_11_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_105) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_11) // @[util.scala:465:24]
uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_108) begin // @[util.scala:481:16, :487:17, :489:33]
uops_12_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_12_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_12_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_12_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_12_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_12_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_12_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_12_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_12_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_12_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_12_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_12_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_12_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_107) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_12) // @[util.scala:465:24]
uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_110) begin // @[util.scala:481:16, :487:17, :489:33]
uops_13_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_13_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_13_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_13_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_13_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_13_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_13_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_13_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_13_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_13_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_13_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_13_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_13_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_109) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_13) // @[util.scala:465:24]
uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_112) begin // @[util.scala:481:16, :487:17, :489:33]
uops_14_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_14_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_14_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_14_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_14_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_14_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_14_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_14_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_14_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_14_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_14_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_14_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_14_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_111) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_14) // @[util.scala:465:24]
uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_113) begin // @[util.scala:481:16, :487:17, :489:33]
uops_15_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_15_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_15_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_15_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_15_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_15_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_15_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_15_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_15_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_15_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_15_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_15_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_15_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_15_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_15_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_15_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_15_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_15_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_15_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_15_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_15_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_15_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_15_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_15_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_15_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_15_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_15_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_15_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_15_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_15_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_15_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_15_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_15_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_15_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_15_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_15_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_15_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_15_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_15_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_15_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_15_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_15_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_15_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_15_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_15_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_15_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_15_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_15_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_15_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_15_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_15_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_15_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_15_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_15_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_15_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_15_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_15_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_15_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_15_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_15_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_15_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_15_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_15_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_15_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_15_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_15_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_15_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_15_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & (&enq_ptr_value)) // @[Counter.scala:61:40]
uops_15_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_15) // @[util.scala:465:24]
uops_15_br_mask <= _uops_15_br_mask_T_1; // @[util.scala:89:21, :466:20]
always @(posedge)
ram_16x131 ram_ext ( // @[util.scala:464:20]
.R0_addr (deq_ptr_value), // @[Counter.scala:61:40]
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_ram_ext_R0_data),
.W0_addr (enq_ptr_value), // @[Counter.scala:61:40]
.W0_en (do_enq), // @[util.scala:475:24]
.W0_clk (clock),
.W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:448:7, :464:20]
); // @[util.scala:464:20]
assign io_enq_ready = io_enq_ready_0; // @[util.scala:448:7]
assign io_deq_valid = io_deq_valid_0; // @[util.scala:448:7]
assign io_deq_bits_uop_uopc = io_deq_bits_uop_uopc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iq_type = io_deq_bits_uop_iq_type_0; // @[util.scala:448:7]
assign io_deq_bits_uop_fu_code = io_deq_bits_uop_fu_code_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_br_type = io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_op1_sel = io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_op2_sel = io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_imm_sel = io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_op_fcn = io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_fcn_dw = io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_csr_cmd = io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_is_load = io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_is_sta = io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_is_std = io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iw_state = io_deq_bits_uop_iw_state_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iw_p1_poisoned = io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iw_p2_poisoned = io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_br = io_deq_bits_uop_is_br_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_jalr = io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_jal = io_deq_bits_uop_is_jal_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7]
assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:448:7]
assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7]
assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:448:7]
assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7]
assign io_deq_bits_uop_csr_addr = io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7]
assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:448:7]
assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7]
assign io_deq_bits_uop_bypassable = io_deq_bits_uop_bypassable_0; // @[util.scala:448:7]
assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7]
assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:448:7]
assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:448:7]
assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7]
assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:448:7]
assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldst_val = io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7]
assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7]
assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7]
assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:448:7]
assign io_deq_bits_uop_fp_single = io_deq_bits_uop_fp_single_0; // @[util.scala:448:7]
assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7]
assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:448:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:448:7]
assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:448:7]
assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:448:7]
assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7]
assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:448:7]
assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:448:7]
assign io_empty = io_empty_0; // @[util.scala:448:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_22 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_22( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IntToFP_6 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<64>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}}
regreset in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect in_pipe_v, io.in.valid
reg in_pipe_b : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<64>}, clock
when io.in.valid :
connect in_pipe_b, io.in.bits
wire in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<64>}}
connect in.valid, in_pipe_v
connect in.bits, in_pipe_b
wire mux : { data : UInt<65>, exc : UInt<5>}
connect mux.exc, UInt<1>(0h0)
node _mux_data_T = eq(in.bits.typeTagIn, UInt<1>(0h1))
node _mux_data_T_1 = mux(_mux_data_T, UInt<64>(0hffffffff00000000), UInt<64>(0hffffffffffff0000))
node _mux_data_T_2 = eq(in.bits.typeTagIn, UInt<2>(0h2))
node _mux_data_T_3 = mux(_mux_data_T_2, UInt<1>(0h0), _mux_data_T_1)
node _mux_data_T_4 = eq(in.bits.typeTagIn, UInt<2>(0h3))
node _mux_data_T_5 = mux(_mux_data_T_4, UInt<1>(0h0), _mux_data_T_3)
node _mux_data_T_6 = or(_mux_data_T_5, in.bits.in1)
node mux_data_rawIn_sign = bits(_mux_data_T_6, 63, 63)
node mux_data_rawIn_expIn = bits(_mux_data_T_6, 62, 52)
node mux_data_rawIn_fractIn = bits(_mux_data_T_6, 51, 0)
node mux_data_rawIn_isZeroExpIn = eq(mux_data_rawIn_expIn, UInt<1>(0h0))
node mux_data_rawIn_isZeroFractIn = eq(mux_data_rawIn_fractIn, UInt<1>(0h0))
node _mux_data_rawIn_normDist_T = bits(mux_data_rawIn_fractIn, 0, 0)
node _mux_data_rawIn_normDist_T_1 = bits(mux_data_rawIn_fractIn, 1, 1)
node _mux_data_rawIn_normDist_T_2 = bits(mux_data_rawIn_fractIn, 2, 2)
node _mux_data_rawIn_normDist_T_3 = bits(mux_data_rawIn_fractIn, 3, 3)
node _mux_data_rawIn_normDist_T_4 = bits(mux_data_rawIn_fractIn, 4, 4)
node _mux_data_rawIn_normDist_T_5 = bits(mux_data_rawIn_fractIn, 5, 5)
node _mux_data_rawIn_normDist_T_6 = bits(mux_data_rawIn_fractIn, 6, 6)
node _mux_data_rawIn_normDist_T_7 = bits(mux_data_rawIn_fractIn, 7, 7)
node _mux_data_rawIn_normDist_T_8 = bits(mux_data_rawIn_fractIn, 8, 8)
node _mux_data_rawIn_normDist_T_9 = bits(mux_data_rawIn_fractIn, 9, 9)
node _mux_data_rawIn_normDist_T_10 = bits(mux_data_rawIn_fractIn, 10, 10)
node _mux_data_rawIn_normDist_T_11 = bits(mux_data_rawIn_fractIn, 11, 11)
node _mux_data_rawIn_normDist_T_12 = bits(mux_data_rawIn_fractIn, 12, 12)
node _mux_data_rawIn_normDist_T_13 = bits(mux_data_rawIn_fractIn, 13, 13)
node _mux_data_rawIn_normDist_T_14 = bits(mux_data_rawIn_fractIn, 14, 14)
node _mux_data_rawIn_normDist_T_15 = bits(mux_data_rawIn_fractIn, 15, 15)
node _mux_data_rawIn_normDist_T_16 = bits(mux_data_rawIn_fractIn, 16, 16)
node _mux_data_rawIn_normDist_T_17 = bits(mux_data_rawIn_fractIn, 17, 17)
node _mux_data_rawIn_normDist_T_18 = bits(mux_data_rawIn_fractIn, 18, 18)
node _mux_data_rawIn_normDist_T_19 = bits(mux_data_rawIn_fractIn, 19, 19)
node _mux_data_rawIn_normDist_T_20 = bits(mux_data_rawIn_fractIn, 20, 20)
node _mux_data_rawIn_normDist_T_21 = bits(mux_data_rawIn_fractIn, 21, 21)
node _mux_data_rawIn_normDist_T_22 = bits(mux_data_rawIn_fractIn, 22, 22)
node _mux_data_rawIn_normDist_T_23 = bits(mux_data_rawIn_fractIn, 23, 23)
node _mux_data_rawIn_normDist_T_24 = bits(mux_data_rawIn_fractIn, 24, 24)
node _mux_data_rawIn_normDist_T_25 = bits(mux_data_rawIn_fractIn, 25, 25)
node _mux_data_rawIn_normDist_T_26 = bits(mux_data_rawIn_fractIn, 26, 26)
node _mux_data_rawIn_normDist_T_27 = bits(mux_data_rawIn_fractIn, 27, 27)
node _mux_data_rawIn_normDist_T_28 = bits(mux_data_rawIn_fractIn, 28, 28)
node _mux_data_rawIn_normDist_T_29 = bits(mux_data_rawIn_fractIn, 29, 29)
node _mux_data_rawIn_normDist_T_30 = bits(mux_data_rawIn_fractIn, 30, 30)
node _mux_data_rawIn_normDist_T_31 = bits(mux_data_rawIn_fractIn, 31, 31)
node _mux_data_rawIn_normDist_T_32 = bits(mux_data_rawIn_fractIn, 32, 32)
node _mux_data_rawIn_normDist_T_33 = bits(mux_data_rawIn_fractIn, 33, 33)
node _mux_data_rawIn_normDist_T_34 = bits(mux_data_rawIn_fractIn, 34, 34)
node _mux_data_rawIn_normDist_T_35 = bits(mux_data_rawIn_fractIn, 35, 35)
node _mux_data_rawIn_normDist_T_36 = bits(mux_data_rawIn_fractIn, 36, 36)
node _mux_data_rawIn_normDist_T_37 = bits(mux_data_rawIn_fractIn, 37, 37)
node _mux_data_rawIn_normDist_T_38 = bits(mux_data_rawIn_fractIn, 38, 38)
node _mux_data_rawIn_normDist_T_39 = bits(mux_data_rawIn_fractIn, 39, 39)
node _mux_data_rawIn_normDist_T_40 = bits(mux_data_rawIn_fractIn, 40, 40)
node _mux_data_rawIn_normDist_T_41 = bits(mux_data_rawIn_fractIn, 41, 41)
node _mux_data_rawIn_normDist_T_42 = bits(mux_data_rawIn_fractIn, 42, 42)
node _mux_data_rawIn_normDist_T_43 = bits(mux_data_rawIn_fractIn, 43, 43)
node _mux_data_rawIn_normDist_T_44 = bits(mux_data_rawIn_fractIn, 44, 44)
node _mux_data_rawIn_normDist_T_45 = bits(mux_data_rawIn_fractIn, 45, 45)
node _mux_data_rawIn_normDist_T_46 = bits(mux_data_rawIn_fractIn, 46, 46)
node _mux_data_rawIn_normDist_T_47 = bits(mux_data_rawIn_fractIn, 47, 47)
node _mux_data_rawIn_normDist_T_48 = bits(mux_data_rawIn_fractIn, 48, 48)
node _mux_data_rawIn_normDist_T_49 = bits(mux_data_rawIn_fractIn, 49, 49)
node _mux_data_rawIn_normDist_T_50 = bits(mux_data_rawIn_fractIn, 50, 50)
node _mux_data_rawIn_normDist_T_51 = bits(mux_data_rawIn_fractIn, 51, 51)
node _mux_data_rawIn_normDist_T_52 = mux(_mux_data_rawIn_normDist_T_1, UInt<6>(0h32), UInt<6>(0h33))
node _mux_data_rawIn_normDist_T_53 = mux(_mux_data_rawIn_normDist_T_2, UInt<6>(0h31), _mux_data_rawIn_normDist_T_52)
node _mux_data_rawIn_normDist_T_54 = mux(_mux_data_rawIn_normDist_T_3, UInt<6>(0h30), _mux_data_rawIn_normDist_T_53)
node _mux_data_rawIn_normDist_T_55 = mux(_mux_data_rawIn_normDist_T_4, UInt<6>(0h2f), _mux_data_rawIn_normDist_T_54)
node _mux_data_rawIn_normDist_T_56 = mux(_mux_data_rawIn_normDist_T_5, UInt<6>(0h2e), _mux_data_rawIn_normDist_T_55)
node _mux_data_rawIn_normDist_T_57 = mux(_mux_data_rawIn_normDist_T_6, UInt<6>(0h2d), _mux_data_rawIn_normDist_T_56)
node _mux_data_rawIn_normDist_T_58 = mux(_mux_data_rawIn_normDist_T_7, UInt<6>(0h2c), _mux_data_rawIn_normDist_T_57)
node _mux_data_rawIn_normDist_T_59 = mux(_mux_data_rawIn_normDist_T_8, UInt<6>(0h2b), _mux_data_rawIn_normDist_T_58)
node _mux_data_rawIn_normDist_T_60 = mux(_mux_data_rawIn_normDist_T_9, UInt<6>(0h2a), _mux_data_rawIn_normDist_T_59)
node _mux_data_rawIn_normDist_T_61 = mux(_mux_data_rawIn_normDist_T_10, UInt<6>(0h29), _mux_data_rawIn_normDist_T_60)
node _mux_data_rawIn_normDist_T_62 = mux(_mux_data_rawIn_normDist_T_11, UInt<6>(0h28), _mux_data_rawIn_normDist_T_61)
node _mux_data_rawIn_normDist_T_63 = mux(_mux_data_rawIn_normDist_T_12, UInt<6>(0h27), _mux_data_rawIn_normDist_T_62)
node _mux_data_rawIn_normDist_T_64 = mux(_mux_data_rawIn_normDist_T_13, UInt<6>(0h26), _mux_data_rawIn_normDist_T_63)
node _mux_data_rawIn_normDist_T_65 = mux(_mux_data_rawIn_normDist_T_14, UInt<6>(0h25), _mux_data_rawIn_normDist_T_64)
node _mux_data_rawIn_normDist_T_66 = mux(_mux_data_rawIn_normDist_T_15, UInt<6>(0h24), _mux_data_rawIn_normDist_T_65)
node _mux_data_rawIn_normDist_T_67 = mux(_mux_data_rawIn_normDist_T_16, UInt<6>(0h23), _mux_data_rawIn_normDist_T_66)
node _mux_data_rawIn_normDist_T_68 = mux(_mux_data_rawIn_normDist_T_17, UInt<6>(0h22), _mux_data_rawIn_normDist_T_67)
node _mux_data_rawIn_normDist_T_69 = mux(_mux_data_rawIn_normDist_T_18, UInt<6>(0h21), _mux_data_rawIn_normDist_T_68)
node _mux_data_rawIn_normDist_T_70 = mux(_mux_data_rawIn_normDist_T_19, UInt<6>(0h20), _mux_data_rawIn_normDist_T_69)
node _mux_data_rawIn_normDist_T_71 = mux(_mux_data_rawIn_normDist_T_20, UInt<5>(0h1f), _mux_data_rawIn_normDist_T_70)
node _mux_data_rawIn_normDist_T_72 = mux(_mux_data_rawIn_normDist_T_21, UInt<5>(0h1e), _mux_data_rawIn_normDist_T_71)
node _mux_data_rawIn_normDist_T_73 = mux(_mux_data_rawIn_normDist_T_22, UInt<5>(0h1d), _mux_data_rawIn_normDist_T_72)
node _mux_data_rawIn_normDist_T_74 = mux(_mux_data_rawIn_normDist_T_23, UInt<5>(0h1c), _mux_data_rawIn_normDist_T_73)
node _mux_data_rawIn_normDist_T_75 = mux(_mux_data_rawIn_normDist_T_24, UInt<5>(0h1b), _mux_data_rawIn_normDist_T_74)
node _mux_data_rawIn_normDist_T_76 = mux(_mux_data_rawIn_normDist_T_25, UInt<5>(0h1a), _mux_data_rawIn_normDist_T_75)
node _mux_data_rawIn_normDist_T_77 = mux(_mux_data_rawIn_normDist_T_26, UInt<5>(0h19), _mux_data_rawIn_normDist_T_76)
node _mux_data_rawIn_normDist_T_78 = mux(_mux_data_rawIn_normDist_T_27, UInt<5>(0h18), _mux_data_rawIn_normDist_T_77)
node _mux_data_rawIn_normDist_T_79 = mux(_mux_data_rawIn_normDist_T_28, UInt<5>(0h17), _mux_data_rawIn_normDist_T_78)
node _mux_data_rawIn_normDist_T_80 = mux(_mux_data_rawIn_normDist_T_29, UInt<5>(0h16), _mux_data_rawIn_normDist_T_79)
node _mux_data_rawIn_normDist_T_81 = mux(_mux_data_rawIn_normDist_T_30, UInt<5>(0h15), _mux_data_rawIn_normDist_T_80)
node _mux_data_rawIn_normDist_T_82 = mux(_mux_data_rawIn_normDist_T_31, UInt<5>(0h14), _mux_data_rawIn_normDist_T_81)
node _mux_data_rawIn_normDist_T_83 = mux(_mux_data_rawIn_normDist_T_32, UInt<5>(0h13), _mux_data_rawIn_normDist_T_82)
node _mux_data_rawIn_normDist_T_84 = mux(_mux_data_rawIn_normDist_T_33, UInt<5>(0h12), _mux_data_rawIn_normDist_T_83)
node _mux_data_rawIn_normDist_T_85 = mux(_mux_data_rawIn_normDist_T_34, UInt<5>(0h11), _mux_data_rawIn_normDist_T_84)
node _mux_data_rawIn_normDist_T_86 = mux(_mux_data_rawIn_normDist_T_35, UInt<5>(0h10), _mux_data_rawIn_normDist_T_85)
node _mux_data_rawIn_normDist_T_87 = mux(_mux_data_rawIn_normDist_T_36, UInt<4>(0hf), _mux_data_rawIn_normDist_T_86)
node _mux_data_rawIn_normDist_T_88 = mux(_mux_data_rawIn_normDist_T_37, UInt<4>(0he), _mux_data_rawIn_normDist_T_87)
node _mux_data_rawIn_normDist_T_89 = mux(_mux_data_rawIn_normDist_T_38, UInt<4>(0hd), _mux_data_rawIn_normDist_T_88)
node _mux_data_rawIn_normDist_T_90 = mux(_mux_data_rawIn_normDist_T_39, UInt<4>(0hc), _mux_data_rawIn_normDist_T_89)
node _mux_data_rawIn_normDist_T_91 = mux(_mux_data_rawIn_normDist_T_40, UInt<4>(0hb), _mux_data_rawIn_normDist_T_90)
node _mux_data_rawIn_normDist_T_92 = mux(_mux_data_rawIn_normDist_T_41, UInt<4>(0ha), _mux_data_rawIn_normDist_T_91)
node _mux_data_rawIn_normDist_T_93 = mux(_mux_data_rawIn_normDist_T_42, UInt<4>(0h9), _mux_data_rawIn_normDist_T_92)
node _mux_data_rawIn_normDist_T_94 = mux(_mux_data_rawIn_normDist_T_43, UInt<4>(0h8), _mux_data_rawIn_normDist_T_93)
node _mux_data_rawIn_normDist_T_95 = mux(_mux_data_rawIn_normDist_T_44, UInt<3>(0h7), _mux_data_rawIn_normDist_T_94)
node _mux_data_rawIn_normDist_T_96 = mux(_mux_data_rawIn_normDist_T_45, UInt<3>(0h6), _mux_data_rawIn_normDist_T_95)
node _mux_data_rawIn_normDist_T_97 = mux(_mux_data_rawIn_normDist_T_46, UInt<3>(0h5), _mux_data_rawIn_normDist_T_96)
node _mux_data_rawIn_normDist_T_98 = mux(_mux_data_rawIn_normDist_T_47, UInt<3>(0h4), _mux_data_rawIn_normDist_T_97)
node _mux_data_rawIn_normDist_T_99 = mux(_mux_data_rawIn_normDist_T_48, UInt<2>(0h3), _mux_data_rawIn_normDist_T_98)
node _mux_data_rawIn_normDist_T_100 = mux(_mux_data_rawIn_normDist_T_49, UInt<2>(0h2), _mux_data_rawIn_normDist_T_99)
node _mux_data_rawIn_normDist_T_101 = mux(_mux_data_rawIn_normDist_T_50, UInt<1>(0h1), _mux_data_rawIn_normDist_T_100)
node mux_data_rawIn_normDist = mux(_mux_data_rawIn_normDist_T_51, UInt<1>(0h0), _mux_data_rawIn_normDist_T_101)
node _mux_data_rawIn_subnormFract_T = dshl(mux_data_rawIn_fractIn, mux_data_rawIn_normDist)
node _mux_data_rawIn_subnormFract_T_1 = bits(_mux_data_rawIn_subnormFract_T, 50, 0)
node mux_data_rawIn_subnormFract = shl(_mux_data_rawIn_subnormFract_T_1, 1)
node _mux_data_rawIn_adjustedExp_T = xor(mux_data_rawIn_normDist, UInt<12>(0hfff))
node _mux_data_rawIn_adjustedExp_T_1 = mux(mux_data_rawIn_isZeroExpIn, _mux_data_rawIn_adjustedExp_T, mux_data_rawIn_expIn)
node _mux_data_rawIn_adjustedExp_T_2 = mux(mux_data_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1))
node _mux_data_rawIn_adjustedExp_T_3 = or(UInt<11>(0h400), _mux_data_rawIn_adjustedExp_T_2)
node _mux_data_rawIn_adjustedExp_T_4 = add(_mux_data_rawIn_adjustedExp_T_1, _mux_data_rawIn_adjustedExp_T_3)
node mux_data_rawIn_adjustedExp = tail(_mux_data_rawIn_adjustedExp_T_4, 1)
node mux_data_rawIn_isZero = and(mux_data_rawIn_isZeroExpIn, mux_data_rawIn_isZeroFractIn)
node _mux_data_rawIn_isSpecial_T = bits(mux_data_rawIn_adjustedExp, 11, 10)
node mux_data_rawIn_isSpecial = eq(_mux_data_rawIn_isSpecial_T, UInt<2>(0h3))
wire mux_data_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _mux_data_rawIn_out_isNaN_T = eq(mux_data_rawIn_isZeroFractIn, UInt<1>(0h0))
node _mux_data_rawIn_out_isNaN_T_1 = and(mux_data_rawIn_isSpecial, _mux_data_rawIn_out_isNaN_T)
connect mux_data_rawIn.isNaN, _mux_data_rawIn_out_isNaN_T_1
node _mux_data_rawIn_out_isInf_T = and(mux_data_rawIn_isSpecial, mux_data_rawIn_isZeroFractIn)
connect mux_data_rawIn.isInf, _mux_data_rawIn_out_isInf_T
connect mux_data_rawIn.isZero, mux_data_rawIn_isZero
connect mux_data_rawIn.sign, mux_data_rawIn_sign
node _mux_data_rawIn_out_sExp_T = bits(mux_data_rawIn_adjustedExp, 11, 0)
node _mux_data_rawIn_out_sExp_T_1 = cvt(_mux_data_rawIn_out_sExp_T)
connect mux_data_rawIn.sExp, _mux_data_rawIn_out_sExp_T_1
node _mux_data_rawIn_out_sig_T = eq(mux_data_rawIn_isZero, UInt<1>(0h0))
node _mux_data_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _mux_data_rawIn_out_sig_T)
node _mux_data_rawIn_out_sig_T_2 = mux(mux_data_rawIn_isZeroExpIn, mux_data_rawIn_subnormFract, mux_data_rawIn_fractIn)
node _mux_data_rawIn_out_sig_T_3 = cat(_mux_data_rawIn_out_sig_T_1, _mux_data_rawIn_out_sig_T_2)
connect mux_data_rawIn.sig, _mux_data_rawIn_out_sig_T_3
node _mux_data_T_7 = bits(mux_data_rawIn.sExp, 11, 9)
node _mux_data_T_8 = mux(mux_data_rawIn.isZero, UInt<3>(0h0), _mux_data_T_7)
node _mux_data_T_9 = mux(mux_data_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _mux_data_T_10 = or(_mux_data_T_8, _mux_data_T_9)
node _mux_data_T_11 = cat(mux_data_rawIn.sign, _mux_data_T_10)
node _mux_data_T_12 = bits(mux_data_rawIn.sExp, 8, 0)
node _mux_data_T_13 = cat(_mux_data_T_11, _mux_data_T_12)
node _mux_data_T_14 = bits(mux_data_rawIn.sig, 51, 0)
node _mux_data_T_15 = cat(_mux_data_T_13, _mux_data_T_14)
node mux_data_rawIn_sign_1 = bits(_mux_data_T_6, 31, 31)
node mux_data_rawIn_expIn_1 = bits(_mux_data_T_6, 30, 23)
node mux_data_rawIn_fractIn_1 = bits(_mux_data_T_6, 22, 0)
node mux_data_rawIn_isZeroExpIn_1 = eq(mux_data_rawIn_expIn_1, UInt<1>(0h0))
node mux_data_rawIn_isZeroFractIn_1 = eq(mux_data_rawIn_fractIn_1, UInt<1>(0h0))
node _mux_data_rawIn_normDist_T_102 = bits(mux_data_rawIn_fractIn_1, 0, 0)
node _mux_data_rawIn_normDist_T_103 = bits(mux_data_rawIn_fractIn_1, 1, 1)
node _mux_data_rawIn_normDist_T_104 = bits(mux_data_rawIn_fractIn_1, 2, 2)
node _mux_data_rawIn_normDist_T_105 = bits(mux_data_rawIn_fractIn_1, 3, 3)
node _mux_data_rawIn_normDist_T_106 = bits(mux_data_rawIn_fractIn_1, 4, 4)
node _mux_data_rawIn_normDist_T_107 = bits(mux_data_rawIn_fractIn_1, 5, 5)
node _mux_data_rawIn_normDist_T_108 = bits(mux_data_rawIn_fractIn_1, 6, 6)
node _mux_data_rawIn_normDist_T_109 = bits(mux_data_rawIn_fractIn_1, 7, 7)
node _mux_data_rawIn_normDist_T_110 = bits(mux_data_rawIn_fractIn_1, 8, 8)
node _mux_data_rawIn_normDist_T_111 = bits(mux_data_rawIn_fractIn_1, 9, 9)
node _mux_data_rawIn_normDist_T_112 = bits(mux_data_rawIn_fractIn_1, 10, 10)
node _mux_data_rawIn_normDist_T_113 = bits(mux_data_rawIn_fractIn_1, 11, 11)
node _mux_data_rawIn_normDist_T_114 = bits(mux_data_rawIn_fractIn_1, 12, 12)
node _mux_data_rawIn_normDist_T_115 = bits(mux_data_rawIn_fractIn_1, 13, 13)
node _mux_data_rawIn_normDist_T_116 = bits(mux_data_rawIn_fractIn_1, 14, 14)
node _mux_data_rawIn_normDist_T_117 = bits(mux_data_rawIn_fractIn_1, 15, 15)
node _mux_data_rawIn_normDist_T_118 = bits(mux_data_rawIn_fractIn_1, 16, 16)
node _mux_data_rawIn_normDist_T_119 = bits(mux_data_rawIn_fractIn_1, 17, 17)
node _mux_data_rawIn_normDist_T_120 = bits(mux_data_rawIn_fractIn_1, 18, 18)
node _mux_data_rawIn_normDist_T_121 = bits(mux_data_rawIn_fractIn_1, 19, 19)
node _mux_data_rawIn_normDist_T_122 = bits(mux_data_rawIn_fractIn_1, 20, 20)
node _mux_data_rawIn_normDist_T_123 = bits(mux_data_rawIn_fractIn_1, 21, 21)
node _mux_data_rawIn_normDist_T_124 = bits(mux_data_rawIn_fractIn_1, 22, 22)
node _mux_data_rawIn_normDist_T_125 = mux(_mux_data_rawIn_normDist_T_103, UInt<5>(0h15), UInt<5>(0h16))
node _mux_data_rawIn_normDist_T_126 = mux(_mux_data_rawIn_normDist_T_104, UInt<5>(0h14), _mux_data_rawIn_normDist_T_125)
node _mux_data_rawIn_normDist_T_127 = mux(_mux_data_rawIn_normDist_T_105, UInt<5>(0h13), _mux_data_rawIn_normDist_T_126)
node _mux_data_rawIn_normDist_T_128 = mux(_mux_data_rawIn_normDist_T_106, UInt<5>(0h12), _mux_data_rawIn_normDist_T_127)
node _mux_data_rawIn_normDist_T_129 = mux(_mux_data_rawIn_normDist_T_107, UInt<5>(0h11), _mux_data_rawIn_normDist_T_128)
node _mux_data_rawIn_normDist_T_130 = mux(_mux_data_rawIn_normDist_T_108, UInt<5>(0h10), _mux_data_rawIn_normDist_T_129)
node _mux_data_rawIn_normDist_T_131 = mux(_mux_data_rawIn_normDist_T_109, UInt<4>(0hf), _mux_data_rawIn_normDist_T_130)
node _mux_data_rawIn_normDist_T_132 = mux(_mux_data_rawIn_normDist_T_110, UInt<4>(0he), _mux_data_rawIn_normDist_T_131)
node _mux_data_rawIn_normDist_T_133 = mux(_mux_data_rawIn_normDist_T_111, UInt<4>(0hd), _mux_data_rawIn_normDist_T_132)
node _mux_data_rawIn_normDist_T_134 = mux(_mux_data_rawIn_normDist_T_112, UInt<4>(0hc), _mux_data_rawIn_normDist_T_133)
node _mux_data_rawIn_normDist_T_135 = mux(_mux_data_rawIn_normDist_T_113, UInt<4>(0hb), _mux_data_rawIn_normDist_T_134)
node _mux_data_rawIn_normDist_T_136 = mux(_mux_data_rawIn_normDist_T_114, UInt<4>(0ha), _mux_data_rawIn_normDist_T_135)
node _mux_data_rawIn_normDist_T_137 = mux(_mux_data_rawIn_normDist_T_115, UInt<4>(0h9), _mux_data_rawIn_normDist_T_136)
node _mux_data_rawIn_normDist_T_138 = mux(_mux_data_rawIn_normDist_T_116, UInt<4>(0h8), _mux_data_rawIn_normDist_T_137)
node _mux_data_rawIn_normDist_T_139 = mux(_mux_data_rawIn_normDist_T_117, UInt<3>(0h7), _mux_data_rawIn_normDist_T_138)
node _mux_data_rawIn_normDist_T_140 = mux(_mux_data_rawIn_normDist_T_118, UInt<3>(0h6), _mux_data_rawIn_normDist_T_139)
node _mux_data_rawIn_normDist_T_141 = mux(_mux_data_rawIn_normDist_T_119, UInt<3>(0h5), _mux_data_rawIn_normDist_T_140)
node _mux_data_rawIn_normDist_T_142 = mux(_mux_data_rawIn_normDist_T_120, UInt<3>(0h4), _mux_data_rawIn_normDist_T_141)
node _mux_data_rawIn_normDist_T_143 = mux(_mux_data_rawIn_normDist_T_121, UInt<2>(0h3), _mux_data_rawIn_normDist_T_142)
node _mux_data_rawIn_normDist_T_144 = mux(_mux_data_rawIn_normDist_T_122, UInt<2>(0h2), _mux_data_rawIn_normDist_T_143)
node _mux_data_rawIn_normDist_T_145 = mux(_mux_data_rawIn_normDist_T_123, UInt<1>(0h1), _mux_data_rawIn_normDist_T_144)
node mux_data_rawIn_normDist_1 = mux(_mux_data_rawIn_normDist_T_124, UInt<1>(0h0), _mux_data_rawIn_normDist_T_145)
node _mux_data_rawIn_subnormFract_T_2 = dshl(mux_data_rawIn_fractIn_1, mux_data_rawIn_normDist_1)
node _mux_data_rawIn_subnormFract_T_3 = bits(_mux_data_rawIn_subnormFract_T_2, 21, 0)
node mux_data_rawIn_subnormFract_1 = shl(_mux_data_rawIn_subnormFract_T_3, 1)
node _mux_data_rawIn_adjustedExp_T_5 = xor(mux_data_rawIn_normDist_1, UInt<9>(0h1ff))
node _mux_data_rawIn_adjustedExp_T_6 = mux(mux_data_rawIn_isZeroExpIn_1, _mux_data_rawIn_adjustedExp_T_5, mux_data_rawIn_expIn_1)
node _mux_data_rawIn_adjustedExp_T_7 = mux(mux_data_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1))
node _mux_data_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _mux_data_rawIn_adjustedExp_T_7)
node _mux_data_rawIn_adjustedExp_T_9 = add(_mux_data_rawIn_adjustedExp_T_6, _mux_data_rawIn_adjustedExp_T_8)
node mux_data_rawIn_adjustedExp_1 = tail(_mux_data_rawIn_adjustedExp_T_9, 1)
node mux_data_rawIn_isZero_1 = and(mux_data_rawIn_isZeroExpIn_1, mux_data_rawIn_isZeroFractIn_1)
node _mux_data_rawIn_isSpecial_T_1 = bits(mux_data_rawIn_adjustedExp_1, 8, 7)
node mux_data_rawIn_isSpecial_1 = eq(_mux_data_rawIn_isSpecial_T_1, UInt<2>(0h3))
wire mux_data_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _mux_data_rawIn_out_isNaN_T_2 = eq(mux_data_rawIn_isZeroFractIn_1, UInt<1>(0h0))
node _mux_data_rawIn_out_isNaN_T_3 = and(mux_data_rawIn_isSpecial_1, _mux_data_rawIn_out_isNaN_T_2)
connect mux_data_rawIn_1.isNaN, _mux_data_rawIn_out_isNaN_T_3
node _mux_data_rawIn_out_isInf_T_1 = and(mux_data_rawIn_isSpecial_1, mux_data_rawIn_isZeroFractIn_1)
connect mux_data_rawIn_1.isInf, _mux_data_rawIn_out_isInf_T_1
connect mux_data_rawIn_1.isZero, mux_data_rawIn_isZero_1
connect mux_data_rawIn_1.sign, mux_data_rawIn_sign_1
node _mux_data_rawIn_out_sExp_T_2 = bits(mux_data_rawIn_adjustedExp_1, 8, 0)
node _mux_data_rawIn_out_sExp_T_3 = cvt(_mux_data_rawIn_out_sExp_T_2)
connect mux_data_rawIn_1.sExp, _mux_data_rawIn_out_sExp_T_3
node _mux_data_rawIn_out_sig_T_4 = eq(mux_data_rawIn_isZero_1, UInt<1>(0h0))
node _mux_data_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _mux_data_rawIn_out_sig_T_4)
node _mux_data_rawIn_out_sig_T_6 = mux(mux_data_rawIn_isZeroExpIn_1, mux_data_rawIn_subnormFract_1, mux_data_rawIn_fractIn_1)
node _mux_data_rawIn_out_sig_T_7 = cat(_mux_data_rawIn_out_sig_T_5, _mux_data_rawIn_out_sig_T_6)
connect mux_data_rawIn_1.sig, _mux_data_rawIn_out_sig_T_7
node _mux_data_T_16 = bits(mux_data_rawIn_1.sExp, 8, 6)
node _mux_data_T_17 = mux(mux_data_rawIn_1.isZero, UInt<3>(0h0), _mux_data_T_16)
node _mux_data_T_18 = mux(mux_data_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _mux_data_T_19 = or(_mux_data_T_17, _mux_data_T_18)
node _mux_data_T_20 = cat(mux_data_rawIn_1.sign, _mux_data_T_19)
node _mux_data_T_21 = bits(mux_data_rawIn_1.sExp, 5, 0)
node _mux_data_T_22 = cat(_mux_data_T_20, _mux_data_T_21)
node _mux_data_T_23 = bits(mux_data_rawIn_1.sig, 22, 0)
node _mux_data_T_24 = cat(_mux_data_T_22, _mux_data_T_23)
node mux_data_rawIn_sign_2 = bits(_mux_data_T_6, 15, 15)
node mux_data_rawIn_expIn_2 = bits(_mux_data_T_6, 14, 10)
node mux_data_rawIn_fractIn_2 = bits(_mux_data_T_6, 9, 0)
node mux_data_rawIn_isZeroExpIn_2 = eq(mux_data_rawIn_expIn_2, UInt<1>(0h0))
node mux_data_rawIn_isZeroFractIn_2 = eq(mux_data_rawIn_fractIn_2, UInt<1>(0h0))
node _mux_data_rawIn_normDist_T_146 = bits(mux_data_rawIn_fractIn_2, 0, 0)
node _mux_data_rawIn_normDist_T_147 = bits(mux_data_rawIn_fractIn_2, 1, 1)
node _mux_data_rawIn_normDist_T_148 = bits(mux_data_rawIn_fractIn_2, 2, 2)
node _mux_data_rawIn_normDist_T_149 = bits(mux_data_rawIn_fractIn_2, 3, 3)
node _mux_data_rawIn_normDist_T_150 = bits(mux_data_rawIn_fractIn_2, 4, 4)
node _mux_data_rawIn_normDist_T_151 = bits(mux_data_rawIn_fractIn_2, 5, 5)
node _mux_data_rawIn_normDist_T_152 = bits(mux_data_rawIn_fractIn_2, 6, 6)
node _mux_data_rawIn_normDist_T_153 = bits(mux_data_rawIn_fractIn_2, 7, 7)
node _mux_data_rawIn_normDist_T_154 = bits(mux_data_rawIn_fractIn_2, 8, 8)
node _mux_data_rawIn_normDist_T_155 = bits(mux_data_rawIn_fractIn_2, 9, 9)
node _mux_data_rawIn_normDist_T_156 = mux(_mux_data_rawIn_normDist_T_147, UInt<4>(0h8), UInt<4>(0h9))
node _mux_data_rawIn_normDist_T_157 = mux(_mux_data_rawIn_normDist_T_148, UInt<3>(0h7), _mux_data_rawIn_normDist_T_156)
node _mux_data_rawIn_normDist_T_158 = mux(_mux_data_rawIn_normDist_T_149, UInt<3>(0h6), _mux_data_rawIn_normDist_T_157)
node _mux_data_rawIn_normDist_T_159 = mux(_mux_data_rawIn_normDist_T_150, UInt<3>(0h5), _mux_data_rawIn_normDist_T_158)
node _mux_data_rawIn_normDist_T_160 = mux(_mux_data_rawIn_normDist_T_151, UInt<3>(0h4), _mux_data_rawIn_normDist_T_159)
node _mux_data_rawIn_normDist_T_161 = mux(_mux_data_rawIn_normDist_T_152, UInt<2>(0h3), _mux_data_rawIn_normDist_T_160)
node _mux_data_rawIn_normDist_T_162 = mux(_mux_data_rawIn_normDist_T_153, UInt<2>(0h2), _mux_data_rawIn_normDist_T_161)
node _mux_data_rawIn_normDist_T_163 = mux(_mux_data_rawIn_normDist_T_154, UInt<1>(0h1), _mux_data_rawIn_normDist_T_162)
node mux_data_rawIn_normDist_2 = mux(_mux_data_rawIn_normDist_T_155, UInt<1>(0h0), _mux_data_rawIn_normDist_T_163)
node _mux_data_rawIn_subnormFract_T_4 = dshl(mux_data_rawIn_fractIn_2, mux_data_rawIn_normDist_2)
node _mux_data_rawIn_subnormFract_T_5 = bits(_mux_data_rawIn_subnormFract_T_4, 8, 0)
node mux_data_rawIn_subnormFract_2 = shl(_mux_data_rawIn_subnormFract_T_5, 1)
node _mux_data_rawIn_adjustedExp_T_10 = xor(mux_data_rawIn_normDist_2, UInt<6>(0h3f))
node _mux_data_rawIn_adjustedExp_T_11 = mux(mux_data_rawIn_isZeroExpIn_2, _mux_data_rawIn_adjustedExp_T_10, mux_data_rawIn_expIn_2)
node _mux_data_rawIn_adjustedExp_T_12 = mux(mux_data_rawIn_isZeroExpIn_2, UInt<2>(0h2), UInt<1>(0h1))
node _mux_data_rawIn_adjustedExp_T_13 = or(UInt<5>(0h10), _mux_data_rawIn_adjustedExp_T_12)
node _mux_data_rawIn_adjustedExp_T_14 = add(_mux_data_rawIn_adjustedExp_T_11, _mux_data_rawIn_adjustedExp_T_13)
node mux_data_rawIn_adjustedExp_2 = tail(_mux_data_rawIn_adjustedExp_T_14, 1)
node mux_data_rawIn_isZero_2 = and(mux_data_rawIn_isZeroExpIn_2, mux_data_rawIn_isZeroFractIn_2)
node _mux_data_rawIn_isSpecial_T_2 = bits(mux_data_rawIn_adjustedExp_2, 5, 4)
node mux_data_rawIn_isSpecial_2 = eq(_mux_data_rawIn_isSpecial_T_2, UInt<2>(0h3))
wire mux_data_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}
node _mux_data_rawIn_out_isNaN_T_4 = eq(mux_data_rawIn_isZeroFractIn_2, UInt<1>(0h0))
node _mux_data_rawIn_out_isNaN_T_5 = and(mux_data_rawIn_isSpecial_2, _mux_data_rawIn_out_isNaN_T_4)
connect mux_data_rawIn_2.isNaN, _mux_data_rawIn_out_isNaN_T_5
node _mux_data_rawIn_out_isInf_T_2 = and(mux_data_rawIn_isSpecial_2, mux_data_rawIn_isZeroFractIn_2)
connect mux_data_rawIn_2.isInf, _mux_data_rawIn_out_isInf_T_2
connect mux_data_rawIn_2.isZero, mux_data_rawIn_isZero_2
connect mux_data_rawIn_2.sign, mux_data_rawIn_sign_2
node _mux_data_rawIn_out_sExp_T_4 = bits(mux_data_rawIn_adjustedExp_2, 5, 0)
node _mux_data_rawIn_out_sExp_T_5 = cvt(_mux_data_rawIn_out_sExp_T_4)
connect mux_data_rawIn_2.sExp, _mux_data_rawIn_out_sExp_T_5
node _mux_data_rawIn_out_sig_T_8 = eq(mux_data_rawIn_isZero_2, UInt<1>(0h0))
node _mux_data_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _mux_data_rawIn_out_sig_T_8)
node _mux_data_rawIn_out_sig_T_10 = mux(mux_data_rawIn_isZeroExpIn_2, mux_data_rawIn_subnormFract_2, mux_data_rawIn_fractIn_2)
node _mux_data_rawIn_out_sig_T_11 = cat(_mux_data_rawIn_out_sig_T_9, _mux_data_rawIn_out_sig_T_10)
connect mux_data_rawIn_2.sig, _mux_data_rawIn_out_sig_T_11
node _mux_data_T_25 = bits(mux_data_rawIn_2.sExp, 5, 3)
node _mux_data_T_26 = mux(mux_data_rawIn_2.isZero, UInt<3>(0h0), _mux_data_T_25)
node _mux_data_T_27 = mux(mux_data_rawIn_2.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _mux_data_T_28 = or(_mux_data_T_26, _mux_data_T_27)
node _mux_data_T_29 = cat(mux_data_rawIn_2.sign, _mux_data_T_28)
node _mux_data_T_30 = bits(mux_data_rawIn_2.sExp, 2, 0)
node _mux_data_T_31 = cat(_mux_data_T_29, _mux_data_T_30)
node _mux_data_T_32 = bits(mux_data_rawIn_2.sig, 9, 0)
node _mux_data_T_33 = cat(_mux_data_T_31, _mux_data_T_32)
node _mux_data_swizzledNaN_T = bits(_mux_data_T_24, 32, 29)
node _mux_data_swizzledNaN_T_1 = bits(_mux_data_T_24, 22, 16)
node _mux_data_swizzledNaN_T_2 = andr(_mux_data_swizzledNaN_T_1)
node _mux_data_swizzledNaN_T_3 = bits(_mux_data_T_24, 27, 24)
node _mux_data_swizzledNaN_T_4 = bits(_mux_data_T_33, 15, 15)
node _mux_data_swizzledNaN_T_5 = bits(_mux_data_T_24, 22, 16)
node _mux_data_swizzledNaN_T_6 = bits(_mux_data_T_33, 16, 16)
node _mux_data_swizzledNaN_T_7 = bits(_mux_data_T_33, 14, 0)
node mux_data_swizzledNaN_lo_hi = cat(_mux_data_swizzledNaN_T_5, _mux_data_swizzledNaN_T_6)
node mux_data_swizzledNaN_lo = cat(mux_data_swizzledNaN_lo_hi, _mux_data_swizzledNaN_T_7)
node mux_data_swizzledNaN_hi_lo = cat(_mux_data_swizzledNaN_T_3, _mux_data_swizzledNaN_T_4)
node mux_data_swizzledNaN_hi_hi = cat(_mux_data_swizzledNaN_T, _mux_data_swizzledNaN_T_2)
node mux_data_swizzledNaN_hi = cat(mux_data_swizzledNaN_hi_hi, mux_data_swizzledNaN_hi_lo)
node mux_data_swizzledNaN = cat(mux_data_swizzledNaN_hi, mux_data_swizzledNaN_lo)
node _mux_data_T_34 = bits(_mux_data_T_24, 31, 29)
node _mux_data_T_35 = andr(_mux_data_T_34)
node _mux_data_T_36 = mux(_mux_data_T_35, mux_data_swizzledNaN, _mux_data_T_24)
node _mux_data_swizzledNaN_T_8 = bits(_mux_data_T_15, 64, 61)
node _mux_data_swizzledNaN_T_9 = bits(_mux_data_T_15, 51, 32)
node _mux_data_swizzledNaN_T_10 = andr(_mux_data_swizzledNaN_T_9)
node _mux_data_swizzledNaN_T_11 = bits(_mux_data_T_15, 59, 53)
node _mux_data_swizzledNaN_T_12 = bits(_mux_data_T_36, 31, 31)
node _mux_data_swizzledNaN_T_13 = bits(_mux_data_T_15, 51, 32)
node _mux_data_swizzledNaN_T_14 = bits(_mux_data_T_36, 32, 32)
node _mux_data_swizzledNaN_T_15 = bits(_mux_data_T_36, 30, 0)
node mux_data_swizzledNaN_lo_hi_1 = cat(_mux_data_swizzledNaN_T_13, _mux_data_swizzledNaN_T_14)
node mux_data_swizzledNaN_lo_1 = cat(mux_data_swizzledNaN_lo_hi_1, _mux_data_swizzledNaN_T_15)
node mux_data_swizzledNaN_hi_lo_1 = cat(_mux_data_swizzledNaN_T_11, _mux_data_swizzledNaN_T_12)
node mux_data_swizzledNaN_hi_hi_1 = cat(_mux_data_swizzledNaN_T_8, _mux_data_swizzledNaN_T_10)
node mux_data_swizzledNaN_hi_1 = cat(mux_data_swizzledNaN_hi_hi_1, mux_data_swizzledNaN_hi_lo_1)
node mux_data_swizzledNaN_1 = cat(mux_data_swizzledNaN_hi_1, mux_data_swizzledNaN_lo_1)
node _mux_data_T_37 = bits(_mux_data_T_15, 63, 61)
node _mux_data_T_38 = andr(_mux_data_T_37)
node _mux_data_T_39 = mux(_mux_data_T_38, mux_data_swizzledNaN_1, _mux_data_T_15)
connect mux.data, _mux_data_T_39
node _intValue_res_T = asSInt(in.bits.in1)
wire intValue_res : SInt
connect intValue_res, _intValue_res_T
node intValue_smallInt = bits(in.bits.in1, 31, 0)
node _intValue_T = bits(in.bits.typ, 1, 1)
node _intValue_T_1 = eq(_intValue_T, UInt<1>(0h0))
when _intValue_T_1 :
node _intValue_res_T_1 = bits(in.bits.typ, 0, 0)
node _intValue_res_T_2 = cvt(intValue_smallInt)
node _intValue_res_T_3 = asSInt(intValue_smallInt)
node _intValue_res_T_4 = mux(_intValue_res_T_1, _intValue_res_T_2, _intValue_res_T_3)
connect intValue_res, _intValue_res_T_4
node intValue = asUInt(intValue_res)
when in.bits.wflags :
inst i2fResults_i2f of INToRecFN_i64_e5_s11_6
node _i2fResults_i2f_io_signedIn_T = bits(in.bits.typ, 0, 0)
node _i2fResults_i2f_io_signedIn_T_1 = not(_i2fResults_i2f_io_signedIn_T)
connect i2fResults_i2f.io.signedIn, _i2fResults_i2f_io_signedIn_T_1
connect i2fResults_i2f.io.in, intValue
connect i2fResults_i2f.io.roundingMode, in.bits.rm
connect i2fResults_i2f.io.detectTininess, UInt<1>(0h1)
inst i2fResults_i2f_1 of INToRecFN_i64_e8_s24_6
node _i2fResults_i2f_io_signedIn_T_2 = bits(in.bits.typ, 0, 0)
node _i2fResults_i2f_io_signedIn_T_3 = not(_i2fResults_i2f_io_signedIn_T_2)
connect i2fResults_i2f_1.io.signedIn, _i2fResults_i2f_io_signedIn_T_3
connect i2fResults_i2f_1.io.in, intValue
connect i2fResults_i2f_1.io.roundingMode, in.bits.rm
connect i2fResults_i2f_1.io.detectTininess, UInt<1>(0h1)
node _i2fResults_maskedNaN_T = not(UInt<33>(0h10800000))
node i2fResults_maskedNaN = and(i2fResults_i2f_1.io.out, _i2fResults_maskedNaN_T)
node _i2fResults_T = bits(i2fResults_i2f_1.io.out, 31, 29)
node _i2fResults_T_1 = andr(_i2fResults_T)
node i2fResults_1_1 = mux(_i2fResults_T_1, i2fResults_maskedNaN, i2fResults_i2f_1.io.out)
inst i2fResults_i2f_2 of INToRecFN_i64_e11_s53_6
node _i2fResults_i2f_io_signedIn_T_4 = bits(in.bits.typ, 0, 0)
node _i2fResults_i2f_io_signedIn_T_5 = not(_i2fResults_i2f_io_signedIn_T_4)
connect i2fResults_i2f_2.io.signedIn, _i2fResults_i2f_io_signedIn_T_5
connect i2fResults_i2f_2.io.in, intValue
connect i2fResults_i2f_2.io.roundingMode, in.bits.rm
connect i2fResults_i2f_2.io.detectTininess, UInt<1>(0h1)
node _i2fResults_maskedNaN_T_1 = not(UInt<65>(0h1010000000000000))
node i2fResults_maskedNaN_1 = and(i2fResults_i2f_2.io.out, _i2fResults_maskedNaN_T_1)
node _i2fResults_T_2 = bits(i2fResults_i2f_2.io.out, 63, 61)
node _i2fResults_T_3 = andr(_i2fResults_T_2)
node i2fResults_2_1 = mux(_i2fResults_T_3, i2fResults_maskedNaN_1, i2fResults_i2f_2.io.out)
node _dataPadded_T = shr(i2fResults_2_1, 17)
node dataPadded_0 = cat(_dataPadded_T, i2fResults_i2f.io.out)
node _dataPadded_T_1 = shr(i2fResults_2_1, 33)
node dataPadded_1 = cat(_dataPadded_T_1, i2fResults_1_1)
node _mux_data_T_40 = eq(in.bits.typeTagIn, UInt<1>(0h1))
node _mux_data_T_41 = mux(_mux_data_T_40, dataPadded_1, dataPadded_0)
node _mux_data_T_42 = eq(in.bits.typeTagIn, UInt<2>(0h2))
node _mux_data_T_43 = mux(_mux_data_T_42, i2fResults_2_1, _mux_data_T_41)
node _mux_data_T_44 = eq(in.bits.typeTagIn, UInt<2>(0h3))
node _mux_data_T_45 = mux(_mux_data_T_44, i2fResults_2_1, _mux_data_T_43)
connect mux.data, _mux_data_T_45
node _mux_exc_T = eq(in.bits.typeTagIn, UInt<1>(0h1))
node _mux_exc_T_1 = mux(_mux_exc_T, i2fResults_i2f_1.io.exceptionFlags, i2fResults_i2f.io.exceptionFlags)
node _mux_exc_T_2 = eq(in.bits.typeTagIn, UInt<2>(0h2))
node _mux_exc_T_3 = mux(_mux_exc_T_2, i2fResults_i2f_2.io.exceptionFlags, _mux_exc_T_1)
node _mux_exc_T_4 = eq(in.bits.typeTagIn, UInt<2>(0h3))
node _mux_exc_T_5 = mux(_mux_exc_T_4, i2fResults_i2f_2.io.exceptionFlags, _mux_exc_T_3)
connect mux.exc, _mux_exc_T_5
regreset io_out_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect io_out_pipe_v, in.valid
reg io_out_pipe_b : { data : UInt<65>, exc : UInt<5>}, clock
when in.valid :
connect io_out_pipe_b, mux
wire io_out_pipe_out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}
connect io_out_pipe_out.valid, io_out_pipe_v
connect io_out_pipe_out.bits, io_out_pipe_b
connect io.out, io_out_pipe_out | module IntToFP_6( // @[FPU.scala:528:7]
input clock, // @[FPU.scala:528:7]
input reset, // @[FPU.scala:528:7]
input io_in_valid, // @[FPU.scala:529:14]
input io_in_bits_ldst, // @[FPU.scala:529:14]
input io_in_bits_wen, // @[FPU.scala:529:14]
input io_in_bits_ren1, // @[FPU.scala:529:14]
input io_in_bits_ren2, // @[FPU.scala:529:14]
input io_in_bits_ren3, // @[FPU.scala:529:14]
input io_in_bits_swap12, // @[FPU.scala:529:14]
input io_in_bits_swap23, // @[FPU.scala:529:14]
input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:529:14]
input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:529:14]
input io_in_bits_fromint, // @[FPU.scala:529:14]
input io_in_bits_toint, // @[FPU.scala:529:14]
input io_in_bits_fastpipe, // @[FPU.scala:529:14]
input io_in_bits_fma, // @[FPU.scala:529:14]
input io_in_bits_div, // @[FPU.scala:529:14]
input io_in_bits_sqrt, // @[FPU.scala:529:14]
input io_in_bits_wflags, // @[FPU.scala:529:14]
input io_in_bits_vec, // @[FPU.scala:529:14]
input [2:0] io_in_bits_rm, // @[FPU.scala:529:14]
input [1:0] io_in_bits_typ, // @[FPU.scala:529:14]
input [63:0] io_in_bits_in1, // @[FPU.scala:529:14]
output [64:0] io_out_bits_data, // @[FPU.scala:529:14]
output [4:0] io_out_bits_exc // @[FPU.scala:529:14]
);
wire mux_data_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19]
wire mux_data_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19]
wire mux_data_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire [64:0] _i2fResults_i2f_2_io_out; // @[FPU.scala:556:23]
wire [4:0] _i2fResults_i2f_2_io_exceptionFlags; // @[FPU.scala:556:23]
wire [32:0] _i2fResults_i2f_1_io_out; // @[FPU.scala:556:23]
wire [4:0] _i2fResults_i2f_1_io_exceptionFlags; // @[FPU.scala:556:23]
wire [16:0] _i2fResults_i2f_io_out; // @[FPU.scala:556:23]
wire [4:0] _i2fResults_i2f_io_exceptionFlags; // @[FPU.scala:556:23]
wire io_in_valid_0 = io_in_valid; // @[FPU.scala:528:7]
wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:528:7]
wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:528:7]
wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:528:7]
wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:528:7]
wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:528:7]
wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:528:7]
wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:528:7]
wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:528:7]
wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:528:7]
wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:528:7]
wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:528:7]
wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:528:7]
wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:528:7]
wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:528:7]
wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:528:7]
wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:528:7]
wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:528:7]
wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:528:7]
wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:528:7]
wire [63:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:528:7]
wire [32:0] _i2fResults_maskedNaN_T = 33'h1EF7FFFFF; // @[FPU.scala:413:27]
wire [64:0] _i2fResults_maskedNaN_T_1 = 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:27]
wire io_out_pipe_out_valid; // @[Valid.scala:135:21]
wire [64:0] io_out_pipe_out_bits_data; // @[Valid.scala:135:21]
wire [4:0] io_out_pipe_out_bits_exc; // @[Valid.scala:135:21]
wire [64:0] io_out_bits_data_0; // @[FPU.scala:528:7]
wire [4:0] io_out_bits_exc_0; // @[FPU.scala:528:7]
wire io_out_valid; // @[FPU.scala:528:7]
reg in_pipe_v; // @[Valid.scala:141:24]
wire in_valid = in_pipe_v; // @[Valid.scala:135:21, :141:24]
reg in_pipe_b_ldst; // @[Valid.scala:142:26]
wire in_bits_ldst = in_pipe_b_ldst; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_wen; // @[Valid.scala:142:26]
wire in_bits_wen = in_pipe_b_wen; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_ren1; // @[Valid.scala:142:26]
wire in_bits_ren1 = in_pipe_b_ren1; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_ren2; // @[Valid.scala:142:26]
wire in_bits_ren2 = in_pipe_b_ren2; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_ren3; // @[Valid.scala:142:26]
wire in_bits_ren3 = in_pipe_b_ren3; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_swap12; // @[Valid.scala:142:26]
wire in_bits_swap12 = in_pipe_b_swap12; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_swap23; // @[Valid.scala:142:26]
wire in_bits_swap23 = in_pipe_b_swap23; // @[Valid.scala:135:21, :142:26]
reg [1:0] in_pipe_b_typeTagIn; // @[Valid.scala:142:26]
wire [1:0] in_bits_typeTagIn = in_pipe_b_typeTagIn; // @[Valid.scala:135:21, :142:26]
reg [1:0] in_pipe_b_typeTagOut; // @[Valid.scala:142:26]
wire [1:0] in_bits_typeTagOut = in_pipe_b_typeTagOut; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_fromint; // @[Valid.scala:142:26]
wire in_bits_fromint = in_pipe_b_fromint; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_toint; // @[Valid.scala:142:26]
wire in_bits_toint = in_pipe_b_toint; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_fastpipe; // @[Valid.scala:142:26]
wire in_bits_fastpipe = in_pipe_b_fastpipe; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_fma; // @[Valid.scala:142:26]
wire in_bits_fma = in_pipe_b_fma; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_div; // @[Valid.scala:142:26]
wire in_bits_div = in_pipe_b_div; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_sqrt; // @[Valid.scala:142:26]
wire in_bits_sqrt = in_pipe_b_sqrt; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_wflags; // @[Valid.scala:142:26]
wire in_bits_wflags = in_pipe_b_wflags; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_vec; // @[Valid.scala:142:26]
wire in_bits_vec = in_pipe_b_vec; // @[Valid.scala:135:21, :142:26]
reg [2:0] in_pipe_b_rm; // @[Valid.scala:142:26]
wire [2:0] in_bits_rm = in_pipe_b_rm; // @[Valid.scala:135:21, :142:26]
reg [1:0] in_pipe_b_typ; // @[Valid.scala:142:26]
wire [1:0] in_bits_typ = in_pipe_b_typ; // @[Valid.scala:135:21, :142:26]
reg [63:0] in_pipe_b_in1; // @[Valid.scala:142:26]
wire [63:0] in_bits_in1 = in_pipe_b_in1; // @[Valid.scala:135:21, :142:26]
wire [63:0] _intValue_res_T = in_bits_in1; // @[Valid.scala:135:21]
wire [64:0] mux_data; // @[FPU.scala:537:17]
wire [4:0] mux_exc; // @[FPU.scala:537:17]
wire _GEN = in_bits_typeTagIn == 2'h1; // @[Valid.scala:135:21]
wire _mux_data_T; // @[package.scala:39:86]
assign _mux_data_T = _GEN; // @[package.scala:39:86]
wire _mux_data_T_40; // @[package.scala:39:86]
assign _mux_data_T_40 = _GEN; // @[package.scala:39:86]
wire _mux_exc_T; // @[package.scala:39:86]
assign _mux_exc_T = _GEN; // @[package.scala:39:86]
wire [63:0] _mux_data_T_1 = _mux_data_T ? 64'hFFFFFFFF00000000 : 64'hFFFFFFFFFFFF0000; // @[package.scala:39:{76,86}]
wire _GEN_0 = in_bits_typeTagIn == 2'h2; // @[Valid.scala:135:21]
wire _mux_data_T_2; // @[package.scala:39:86]
assign _mux_data_T_2 = _GEN_0; // @[package.scala:39:86]
wire _mux_data_T_42; // @[package.scala:39:86]
assign _mux_data_T_42 = _GEN_0; // @[package.scala:39:86]
wire _mux_exc_T_2; // @[package.scala:39:86]
assign _mux_exc_T_2 = _GEN_0; // @[package.scala:39:86]
wire [63:0] _mux_data_T_3 = _mux_data_T_2 ? 64'h0 : _mux_data_T_1; // @[package.scala:39:{76,86}]
wire _mux_data_T_4 = &in_bits_typeTagIn; // @[Valid.scala:135:21]
wire [63:0] _mux_data_T_5 = _mux_data_T_4 ? 64'h0 : _mux_data_T_3; // @[package.scala:39:{76,86}]
wire [63:0] _mux_data_T_6 = _mux_data_T_5 | in_bits_in1; // @[Valid.scala:135:21]
wire mux_data_rawIn_sign = _mux_data_T_6[63]; // @[FPU.scala:431:23]
wire mux_data_rawIn_sign_0 = mux_data_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [10:0] mux_data_rawIn_expIn = _mux_data_T_6[62:52]; // @[FPU.scala:431:23]
wire [51:0] mux_data_rawIn_fractIn = _mux_data_T_6[51:0]; // @[FPU.scala:431:23]
wire mux_data_rawIn_isZeroExpIn = mux_data_rawIn_expIn == 11'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire mux_data_rawIn_isZeroFractIn = mux_data_rawIn_fractIn == 52'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _mux_data_rawIn_normDist_T = mux_data_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_1 = mux_data_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_2 = mux_data_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_3 = mux_data_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_4 = mux_data_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_5 = mux_data_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_6 = mux_data_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_7 = mux_data_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_8 = mux_data_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_9 = mux_data_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_10 = mux_data_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_11 = mux_data_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_12 = mux_data_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_13 = mux_data_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_14 = mux_data_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_15 = mux_data_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_16 = mux_data_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_17 = mux_data_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_18 = mux_data_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_19 = mux_data_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_20 = mux_data_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_21 = mux_data_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_22 = mux_data_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_23 = mux_data_rawIn_fractIn[23]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_24 = mux_data_rawIn_fractIn[24]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_25 = mux_data_rawIn_fractIn[25]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_26 = mux_data_rawIn_fractIn[26]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_27 = mux_data_rawIn_fractIn[27]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_28 = mux_data_rawIn_fractIn[28]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_29 = mux_data_rawIn_fractIn[29]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_30 = mux_data_rawIn_fractIn[30]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_31 = mux_data_rawIn_fractIn[31]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_32 = mux_data_rawIn_fractIn[32]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_33 = mux_data_rawIn_fractIn[33]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_34 = mux_data_rawIn_fractIn[34]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_35 = mux_data_rawIn_fractIn[35]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_36 = mux_data_rawIn_fractIn[36]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_37 = mux_data_rawIn_fractIn[37]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_38 = mux_data_rawIn_fractIn[38]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_39 = mux_data_rawIn_fractIn[39]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_40 = mux_data_rawIn_fractIn[40]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_41 = mux_data_rawIn_fractIn[41]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_42 = mux_data_rawIn_fractIn[42]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_43 = mux_data_rawIn_fractIn[43]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_44 = mux_data_rawIn_fractIn[44]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_45 = mux_data_rawIn_fractIn[45]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_46 = mux_data_rawIn_fractIn[46]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_47 = mux_data_rawIn_fractIn[47]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_48 = mux_data_rawIn_fractIn[48]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_49 = mux_data_rawIn_fractIn[49]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_50 = mux_data_rawIn_fractIn[50]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_51 = mux_data_rawIn_fractIn[51]; // @[rawFloatFromFN.scala:46:21]
wire [5:0] _mux_data_rawIn_normDist_T_52 = {5'h19, ~_mux_data_rawIn_normDist_T_1}; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_53 = _mux_data_rawIn_normDist_T_2 ? 6'h31 : _mux_data_rawIn_normDist_T_52; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_54 = _mux_data_rawIn_normDist_T_3 ? 6'h30 : _mux_data_rawIn_normDist_T_53; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_55 = _mux_data_rawIn_normDist_T_4 ? 6'h2F : _mux_data_rawIn_normDist_T_54; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_56 = _mux_data_rawIn_normDist_T_5 ? 6'h2E : _mux_data_rawIn_normDist_T_55; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_57 = _mux_data_rawIn_normDist_T_6 ? 6'h2D : _mux_data_rawIn_normDist_T_56; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_58 = _mux_data_rawIn_normDist_T_7 ? 6'h2C : _mux_data_rawIn_normDist_T_57; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_59 = _mux_data_rawIn_normDist_T_8 ? 6'h2B : _mux_data_rawIn_normDist_T_58; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_60 = _mux_data_rawIn_normDist_T_9 ? 6'h2A : _mux_data_rawIn_normDist_T_59; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_61 = _mux_data_rawIn_normDist_T_10 ? 6'h29 : _mux_data_rawIn_normDist_T_60; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_62 = _mux_data_rawIn_normDist_T_11 ? 6'h28 : _mux_data_rawIn_normDist_T_61; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_63 = _mux_data_rawIn_normDist_T_12 ? 6'h27 : _mux_data_rawIn_normDist_T_62; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_64 = _mux_data_rawIn_normDist_T_13 ? 6'h26 : _mux_data_rawIn_normDist_T_63; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_65 = _mux_data_rawIn_normDist_T_14 ? 6'h25 : _mux_data_rawIn_normDist_T_64; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_66 = _mux_data_rawIn_normDist_T_15 ? 6'h24 : _mux_data_rawIn_normDist_T_65; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_67 = _mux_data_rawIn_normDist_T_16 ? 6'h23 : _mux_data_rawIn_normDist_T_66; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_68 = _mux_data_rawIn_normDist_T_17 ? 6'h22 : _mux_data_rawIn_normDist_T_67; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_69 = _mux_data_rawIn_normDist_T_18 ? 6'h21 : _mux_data_rawIn_normDist_T_68; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_70 = _mux_data_rawIn_normDist_T_19 ? 6'h20 : _mux_data_rawIn_normDist_T_69; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_71 = _mux_data_rawIn_normDist_T_20 ? 6'h1F : _mux_data_rawIn_normDist_T_70; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_72 = _mux_data_rawIn_normDist_T_21 ? 6'h1E : _mux_data_rawIn_normDist_T_71; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_73 = _mux_data_rawIn_normDist_T_22 ? 6'h1D : _mux_data_rawIn_normDist_T_72; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_74 = _mux_data_rawIn_normDist_T_23 ? 6'h1C : _mux_data_rawIn_normDist_T_73; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_75 = _mux_data_rawIn_normDist_T_24 ? 6'h1B : _mux_data_rawIn_normDist_T_74; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_76 = _mux_data_rawIn_normDist_T_25 ? 6'h1A : _mux_data_rawIn_normDist_T_75; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_77 = _mux_data_rawIn_normDist_T_26 ? 6'h19 : _mux_data_rawIn_normDist_T_76; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_78 = _mux_data_rawIn_normDist_T_27 ? 6'h18 : _mux_data_rawIn_normDist_T_77; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_79 = _mux_data_rawIn_normDist_T_28 ? 6'h17 : _mux_data_rawIn_normDist_T_78; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_80 = _mux_data_rawIn_normDist_T_29 ? 6'h16 : _mux_data_rawIn_normDist_T_79; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_81 = _mux_data_rawIn_normDist_T_30 ? 6'h15 : _mux_data_rawIn_normDist_T_80; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_82 = _mux_data_rawIn_normDist_T_31 ? 6'h14 : _mux_data_rawIn_normDist_T_81; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_83 = _mux_data_rawIn_normDist_T_32 ? 6'h13 : _mux_data_rawIn_normDist_T_82; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_84 = _mux_data_rawIn_normDist_T_33 ? 6'h12 : _mux_data_rawIn_normDist_T_83; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_85 = _mux_data_rawIn_normDist_T_34 ? 6'h11 : _mux_data_rawIn_normDist_T_84; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_86 = _mux_data_rawIn_normDist_T_35 ? 6'h10 : _mux_data_rawIn_normDist_T_85; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_87 = _mux_data_rawIn_normDist_T_36 ? 6'hF : _mux_data_rawIn_normDist_T_86; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_88 = _mux_data_rawIn_normDist_T_37 ? 6'hE : _mux_data_rawIn_normDist_T_87; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_89 = _mux_data_rawIn_normDist_T_38 ? 6'hD : _mux_data_rawIn_normDist_T_88; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_90 = _mux_data_rawIn_normDist_T_39 ? 6'hC : _mux_data_rawIn_normDist_T_89; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_91 = _mux_data_rawIn_normDist_T_40 ? 6'hB : _mux_data_rawIn_normDist_T_90; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_92 = _mux_data_rawIn_normDist_T_41 ? 6'hA : _mux_data_rawIn_normDist_T_91; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_93 = _mux_data_rawIn_normDist_T_42 ? 6'h9 : _mux_data_rawIn_normDist_T_92; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_94 = _mux_data_rawIn_normDist_T_43 ? 6'h8 : _mux_data_rawIn_normDist_T_93; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_95 = _mux_data_rawIn_normDist_T_44 ? 6'h7 : _mux_data_rawIn_normDist_T_94; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_96 = _mux_data_rawIn_normDist_T_45 ? 6'h6 : _mux_data_rawIn_normDist_T_95; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_97 = _mux_data_rawIn_normDist_T_46 ? 6'h5 : _mux_data_rawIn_normDist_T_96; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_98 = _mux_data_rawIn_normDist_T_47 ? 6'h4 : _mux_data_rawIn_normDist_T_97; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_99 = _mux_data_rawIn_normDist_T_48 ? 6'h3 : _mux_data_rawIn_normDist_T_98; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_100 = _mux_data_rawIn_normDist_T_49 ? 6'h2 : _mux_data_rawIn_normDist_T_99; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_normDist_T_101 = _mux_data_rawIn_normDist_T_50 ? 6'h1 : _mux_data_rawIn_normDist_T_100; // @[Mux.scala:50:70]
wire [5:0] mux_data_rawIn_normDist = _mux_data_rawIn_normDist_T_51 ? 6'h0 : _mux_data_rawIn_normDist_T_101; // @[Mux.scala:50:70]
wire [114:0] _mux_data_rawIn_subnormFract_T = {63'h0, mux_data_rawIn_fractIn} << mux_data_rawIn_normDist; // @[Mux.scala:50:70]
wire [50:0] _mux_data_rawIn_subnormFract_T_1 = _mux_data_rawIn_subnormFract_T[50:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [51:0] mux_data_rawIn_subnormFract = {_mux_data_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [11:0] _mux_data_rawIn_adjustedExp_T = {6'h3F, ~mux_data_rawIn_normDist}; // @[Mux.scala:50:70]
wire [11:0] _mux_data_rawIn_adjustedExp_T_1 = mux_data_rawIn_isZeroExpIn ? _mux_data_rawIn_adjustedExp_T : {1'h0, mux_data_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _mux_data_rawIn_adjustedExp_T_2 = mux_data_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[package.scala:39:86]
wire [10:0] _mux_data_rawIn_adjustedExp_T_3 = {9'h100, _mux_data_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [12:0] _mux_data_rawIn_adjustedExp_T_4 = {1'h0, _mux_data_rawIn_adjustedExp_T_1} + {2'h0, _mux_data_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [11:0] mux_data_rawIn_adjustedExp = _mux_data_rawIn_adjustedExp_T_4[11:0]; // @[rawFloatFromFN.scala:57:9]
wire [11:0] _mux_data_rawIn_out_sExp_T = mux_data_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire mux_data_rawIn_isZero = mux_data_rawIn_isZeroExpIn & mux_data_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire mux_data_rawIn_isZero_0 = mux_data_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _mux_data_rawIn_isSpecial_T = mux_data_rawIn_adjustedExp[11:10]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire mux_data_rawIn_isSpecial = &_mux_data_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _mux_data_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _mux_data_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _mux_data_T_9 = mux_data_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [12:0] _mux_data_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [53:0] _mux_data_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire mux_data_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [12:0] mux_data_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [53:0] mux_data_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _mux_data_rawIn_out_isNaN_T = ~mux_data_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _mux_data_rawIn_out_isNaN_T_1 = mux_data_rawIn_isSpecial & _mux_data_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign mux_data_rawIn_isNaN = _mux_data_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _mux_data_rawIn_out_isInf_T = mux_data_rawIn_isSpecial & mux_data_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign mux_data_rawIn_isInf = _mux_data_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _mux_data_rawIn_out_sExp_T_1 = {1'h0, _mux_data_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign mux_data_rawIn_sExp = _mux_data_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _mux_data_rawIn_out_sig_T = ~mux_data_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _mux_data_rawIn_out_sig_T_1 = {1'h0, _mux_data_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [51:0] _mux_data_rawIn_out_sig_T_2 = mux_data_rawIn_isZeroExpIn ? mux_data_rawIn_subnormFract : mux_data_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _mux_data_rawIn_out_sig_T_3 = {_mux_data_rawIn_out_sig_T_1, _mux_data_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign mux_data_rawIn_sig = _mux_data_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _mux_data_T_7 = mux_data_rawIn_sExp[11:9]; // @[recFNFromFN.scala:48:50]
wire [2:0] _mux_data_T_8 = mux_data_rawIn_isZero_0 ? 3'h0 : _mux_data_T_7; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _mux_data_T_10 = {_mux_data_T_8[2:1], _mux_data_T_8[0] | _mux_data_T_9}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _mux_data_T_11 = {mux_data_rawIn_sign_0, _mux_data_T_10}; // @[recFNFromFN.scala:47:20, :48:76]
wire [8:0] _mux_data_T_12 = mux_data_rawIn_sExp[8:0]; // @[recFNFromFN.scala:50:23]
wire [12:0] _mux_data_T_13 = {_mux_data_T_11, _mux_data_T_12}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [51:0] _mux_data_T_14 = mux_data_rawIn_sig[51:0]; // @[recFNFromFN.scala:51:22]
wire [64:0] _mux_data_T_15 = {_mux_data_T_13, _mux_data_T_14}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire mux_data_rawIn_sign_1 = _mux_data_T_6[31]; // @[FPU.scala:431:23]
wire mux_data_rawIn_1_sign = mux_data_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] mux_data_rawIn_expIn_1 = _mux_data_T_6[30:23]; // @[FPU.scala:431:23]
wire [22:0] mux_data_rawIn_fractIn_1 = _mux_data_T_6[22:0]; // @[FPU.scala:431:23]
wire mux_data_rawIn_isZeroExpIn_1 = mux_data_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire mux_data_rawIn_isZeroFractIn_1 = mux_data_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _mux_data_rawIn_normDist_T_102 = mux_data_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_103 = mux_data_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_104 = mux_data_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_105 = mux_data_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_106 = mux_data_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_107 = mux_data_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_108 = mux_data_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_109 = mux_data_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_110 = mux_data_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_111 = mux_data_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_112 = mux_data_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_113 = mux_data_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_114 = mux_data_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_115 = mux_data_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_116 = mux_data_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_117 = mux_data_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_118 = mux_data_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_119 = mux_data_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_120 = mux_data_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_121 = mux_data_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_122 = mux_data_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_123 = mux_data_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_124 = mux_data_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _mux_data_rawIn_normDist_T_125 = _mux_data_rawIn_normDist_T_103 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _mux_data_rawIn_normDist_T_126 = _mux_data_rawIn_normDist_T_104 ? 5'h14 : _mux_data_rawIn_normDist_T_125; // @[Mux.scala:50:70]
wire [4:0] _mux_data_rawIn_normDist_T_127 = _mux_data_rawIn_normDist_T_105 ? 5'h13 : _mux_data_rawIn_normDist_T_126; // @[Mux.scala:50:70]
wire [4:0] _mux_data_rawIn_normDist_T_128 = _mux_data_rawIn_normDist_T_106 ? 5'h12 : _mux_data_rawIn_normDist_T_127; // @[Mux.scala:50:70]
wire [4:0] _mux_data_rawIn_normDist_T_129 = _mux_data_rawIn_normDist_T_107 ? 5'h11 : _mux_data_rawIn_normDist_T_128; // @[Mux.scala:50:70]
wire [4:0] _mux_data_rawIn_normDist_T_130 = _mux_data_rawIn_normDist_T_108 ? 5'h10 : _mux_data_rawIn_normDist_T_129; // @[Mux.scala:50:70]
wire [4:0] _mux_data_rawIn_normDist_T_131 = _mux_data_rawIn_normDist_T_109 ? 5'hF : _mux_data_rawIn_normDist_T_130; // @[Mux.scala:50:70]
wire [4:0] _mux_data_rawIn_normDist_T_132 = _mux_data_rawIn_normDist_T_110 ? 5'hE : _mux_data_rawIn_normDist_T_131; // @[Mux.scala:50:70]
wire [4:0] _mux_data_rawIn_normDist_T_133 = _mux_data_rawIn_normDist_T_111 ? 5'hD : _mux_data_rawIn_normDist_T_132; // @[Mux.scala:50:70]
wire [4:0] _mux_data_rawIn_normDist_T_134 = _mux_data_rawIn_normDist_T_112 ? 5'hC : _mux_data_rawIn_normDist_T_133; // @[Mux.scala:50:70]
wire [4:0] _mux_data_rawIn_normDist_T_135 = _mux_data_rawIn_normDist_T_113 ? 5'hB : _mux_data_rawIn_normDist_T_134; // @[Mux.scala:50:70]
wire [4:0] _mux_data_rawIn_normDist_T_136 = _mux_data_rawIn_normDist_T_114 ? 5'hA : _mux_data_rawIn_normDist_T_135; // @[Mux.scala:50:70]
wire [4:0] _mux_data_rawIn_normDist_T_137 = _mux_data_rawIn_normDist_T_115 ? 5'h9 : _mux_data_rawIn_normDist_T_136; // @[Mux.scala:50:70]
wire [4:0] _mux_data_rawIn_normDist_T_138 = _mux_data_rawIn_normDist_T_116 ? 5'h8 : _mux_data_rawIn_normDist_T_137; // @[Mux.scala:50:70]
wire [4:0] _mux_data_rawIn_normDist_T_139 = _mux_data_rawIn_normDist_T_117 ? 5'h7 : _mux_data_rawIn_normDist_T_138; // @[Mux.scala:50:70]
wire [4:0] _mux_data_rawIn_normDist_T_140 = _mux_data_rawIn_normDist_T_118 ? 5'h6 : _mux_data_rawIn_normDist_T_139; // @[Mux.scala:50:70]
wire [4:0] _mux_data_rawIn_normDist_T_141 = _mux_data_rawIn_normDist_T_119 ? 5'h5 : _mux_data_rawIn_normDist_T_140; // @[Mux.scala:50:70]
wire [4:0] _mux_data_rawIn_normDist_T_142 = _mux_data_rawIn_normDist_T_120 ? 5'h4 : _mux_data_rawIn_normDist_T_141; // @[Mux.scala:50:70]
wire [4:0] _mux_data_rawIn_normDist_T_143 = _mux_data_rawIn_normDist_T_121 ? 5'h3 : _mux_data_rawIn_normDist_T_142; // @[Mux.scala:50:70]
wire [4:0] _mux_data_rawIn_normDist_T_144 = _mux_data_rawIn_normDist_T_122 ? 5'h2 : _mux_data_rawIn_normDist_T_143; // @[Mux.scala:50:70]
wire [4:0] _mux_data_rawIn_normDist_T_145 = _mux_data_rawIn_normDist_T_123 ? 5'h1 : _mux_data_rawIn_normDist_T_144; // @[Mux.scala:50:70]
wire [4:0] mux_data_rawIn_normDist_1 = _mux_data_rawIn_normDist_T_124 ? 5'h0 : _mux_data_rawIn_normDist_T_145; // @[Mux.scala:50:70]
wire [53:0] _mux_data_rawIn_subnormFract_T_2 = {31'h0, mux_data_rawIn_fractIn_1} << mux_data_rawIn_normDist_1; // @[Mux.scala:50:70]
wire [21:0] _mux_data_rawIn_subnormFract_T_3 = _mux_data_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] mux_data_rawIn_subnormFract_1 = {_mux_data_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _mux_data_rawIn_adjustedExp_T_5 = {4'hF, ~mux_data_rawIn_normDist_1}; // @[Mux.scala:50:70]
wire [8:0] _mux_data_rawIn_adjustedExp_T_6 = mux_data_rawIn_isZeroExpIn_1 ? _mux_data_rawIn_adjustedExp_T_5 : {1'h0, mux_data_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _mux_data_rawIn_adjustedExp_T_7 = mux_data_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[package.scala:39:86]
wire [7:0] _mux_data_rawIn_adjustedExp_T_8 = {6'h20, _mux_data_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _mux_data_rawIn_adjustedExp_T_9 = {1'h0, _mux_data_rawIn_adjustedExp_T_6} + {2'h0, _mux_data_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] mux_data_rawIn_adjustedExp_1 = _mux_data_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _mux_data_rawIn_out_sExp_T_2 = mux_data_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28]
wire mux_data_rawIn_isZero_1 = mux_data_rawIn_isZeroExpIn_1 & mux_data_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire mux_data_rawIn_1_isZero = mux_data_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _mux_data_rawIn_isSpecial_T_1 = mux_data_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire mux_data_rawIn_isSpecial_1 = &_mux_data_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}]
wire _mux_data_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28]
wire _mux_data_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28]
wire _mux_data_T_18 = mux_data_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _mux_data_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _mux_data_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27]
wire mux_data_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] mux_data_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] mux_data_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19]
wire _mux_data_rawIn_out_isNaN_T_2 = ~mux_data_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _mux_data_rawIn_out_isNaN_T_3 = mux_data_rawIn_isSpecial_1 & _mux_data_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign mux_data_rawIn_1_isNaN = _mux_data_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _mux_data_rawIn_out_isInf_T_1 = mux_data_rawIn_isSpecial_1 & mux_data_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign mux_data_rawIn_1_isInf = _mux_data_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _mux_data_rawIn_out_sExp_T_3 = {1'h0, _mux_data_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}]
assign mux_data_rawIn_1_sExp = _mux_data_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _mux_data_rawIn_out_sig_T_4 = ~mux_data_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _mux_data_rawIn_out_sig_T_5 = {1'h0, _mux_data_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _mux_data_rawIn_out_sig_T_6 = mux_data_rawIn_isZeroExpIn_1 ? mux_data_rawIn_subnormFract_1 : mux_data_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _mux_data_rawIn_out_sig_T_7 = {_mux_data_rawIn_out_sig_T_5, _mux_data_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign mux_data_rawIn_1_sig = _mux_data_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _mux_data_T_16 = mux_data_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _mux_data_T_17 = mux_data_rawIn_1_isZero ? 3'h0 : _mux_data_T_16; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _mux_data_T_19 = {_mux_data_T_17[2:1], _mux_data_T_17[0] | _mux_data_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _mux_data_T_20 = {mux_data_rawIn_1_sign, _mux_data_T_19}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _mux_data_T_21 = mux_data_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _mux_data_T_22 = {_mux_data_T_20, _mux_data_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _mux_data_T_23 = mux_data_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] _mux_data_T_24 = {_mux_data_T_22, _mux_data_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire mux_data_rawIn_sign_2 = _mux_data_T_6[15]; // @[FPU.scala:431:23]
wire mux_data_rawIn_2_sign = mux_data_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [4:0] mux_data_rawIn_expIn_2 = _mux_data_T_6[14:10]; // @[FPU.scala:431:23]
wire [9:0] mux_data_rawIn_fractIn_2 = _mux_data_T_6[9:0]; // @[FPU.scala:431:23]
wire mux_data_rawIn_isZeroExpIn_2 = mux_data_rawIn_expIn_2 == 5'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire mux_data_rawIn_isZeroFractIn_2 = mux_data_rawIn_fractIn_2 == 10'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _mux_data_rawIn_normDist_T_146 = mux_data_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_147 = mux_data_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_148 = mux_data_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_149 = mux_data_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_150 = mux_data_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_151 = mux_data_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_152 = mux_data_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_153 = mux_data_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_154 = mux_data_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21]
wire _mux_data_rawIn_normDist_T_155 = mux_data_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21]
wire [3:0] _mux_data_rawIn_normDist_T_156 = {3'h4, ~_mux_data_rawIn_normDist_T_147}; // @[Mux.scala:50:70]
wire [3:0] _mux_data_rawIn_normDist_T_157 = _mux_data_rawIn_normDist_T_148 ? 4'h7 : _mux_data_rawIn_normDist_T_156; // @[Mux.scala:50:70]
wire [3:0] _mux_data_rawIn_normDist_T_158 = _mux_data_rawIn_normDist_T_149 ? 4'h6 : _mux_data_rawIn_normDist_T_157; // @[Mux.scala:50:70]
wire [3:0] _mux_data_rawIn_normDist_T_159 = _mux_data_rawIn_normDist_T_150 ? 4'h5 : _mux_data_rawIn_normDist_T_158; // @[Mux.scala:50:70]
wire [3:0] _mux_data_rawIn_normDist_T_160 = _mux_data_rawIn_normDist_T_151 ? 4'h4 : _mux_data_rawIn_normDist_T_159; // @[Mux.scala:50:70]
wire [3:0] _mux_data_rawIn_normDist_T_161 = _mux_data_rawIn_normDist_T_152 ? 4'h3 : _mux_data_rawIn_normDist_T_160; // @[Mux.scala:50:70]
wire [3:0] _mux_data_rawIn_normDist_T_162 = _mux_data_rawIn_normDist_T_153 ? 4'h2 : _mux_data_rawIn_normDist_T_161; // @[Mux.scala:50:70]
wire [3:0] _mux_data_rawIn_normDist_T_163 = _mux_data_rawIn_normDist_T_154 ? 4'h1 : _mux_data_rawIn_normDist_T_162; // @[Mux.scala:50:70]
wire [3:0] mux_data_rawIn_normDist_2 = _mux_data_rawIn_normDist_T_155 ? 4'h0 : _mux_data_rawIn_normDist_T_163; // @[Mux.scala:50:70]
wire [24:0] _mux_data_rawIn_subnormFract_T_4 = {15'h0, mux_data_rawIn_fractIn_2} << mux_data_rawIn_normDist_2; // @[Mux.scala:50:70]
wire [8:0] _mux_data_rawIn_subnormFract_T_5 = _mux_data_rawIn_subnormFract_T_4[8:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [9:0] mux_data_rawIn_subnormFract_2 = {_mux_data_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [5:0] _mux_data_rawIn_adjustedExp_T_10 = {2'h3, ~mux_data_rawIn_normDist_2}; // @[Mux.scala:50:70]
wire [5:0] _mux_data_rawIn_adjustedExp_T_11 = mux_data_rawIn_isZeroExpIn_2 ? _mux_data_rawIn_adjustedExp_T_10 : {1'h0, mux_data_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _mux_data_rawIn_adjustedExp_T_12 = mux_data_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[package.scala:39:86]
wire [4:0] _mux_data_rawIn_adjustedExp_T_13 = {3'h4, _mux_data_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [6:0] _mux_data_rawIn_adjustedExp_T_14 = {1'h0, _mux_data_rawIn_adjustedExp_T_11} + {2'h0, _mux_data_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [5:0] mux_data_rawIn_adjustedExp_2 = _mux_data_rawIn_adjustedExp_T_14[5:0]; // @[rawFloatFromFN.scala:57:9]
wire [5:0] _mux_data_rawIn_out_sExp_T_4 = mux_data_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28]
wire mux_data_rawIn_isZero_2 = mux_data_rawIn_isZeroExpIn_2 & mux_data_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire mux_data_rawIn_2_isZero = mux_data_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _mux_data_rawIn_isSpecial_T_2 = mux_data_rawIn_adjustedExp_2[5:4]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire mux_data_rawIn_isSpecial_2 = &_mux_data_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}]
wire _mux_data_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28]
wire _mux_data_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28]
wire _mux_data_T_27 = mux_data_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20]
wire [6:0] _mux_data_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42]
wire [11:0] _mux_data_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27]
wire mux_data_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19]
wire [6:0] mux_data_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19]
wire [11:0] mux_data_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19]
wire _mux_data_rawIn_out_isNaN_T_4 = ~mux_data_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _mux_data_rawIn_out_isNaN_T_5 = mux_data_rawIn_isSpecial_2 & _mux_data_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign mux_data_rawIn_2_isNaN = _mux_data_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _mux_data_rawIn_out_isInf_T_2 = mux_data_rawIn_isSpecial_2 & mux_data_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign mux_data_rawIn_2_isInf = _mux_data_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _mux_data_rawIn_out_sExp_T_5 = {1'h0, _mux_data_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}]
assign mux_data_rawIn_2_sExp = _mux_data_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _mux_data_rawIn_out_sig_T_8 = ~mux_data_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _mux_data_rawIn_out_sig_T_9 = {1'h0, _mux_data_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [9:0] _mux_data_rawIn_out_sig_T_10 = mux_data_rawIn_isZeroExpIn_2 ? mux_data_rawIn_subnormFract_2 : mux_data_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _mux_data_rawIn_out_sig_T_11 = {_mux_data_rawIn_out_sig_T_9, _mux_data_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign mux_data_rawIn_2_sig = _mux_data_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _mux_data_T_25 = mux_data_rawIn_2_sExp[5:3]; // @[recFNFromFN.scala:48:50]
wire [2:0] _mux_data_T_26 = mux_data_rawIn_2_isZero ? 3'h0 : _mux_data_T_25; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _mux_data_T_28 = {_mux_data_T_26[2:1], _mux_data_T_26[0] | _mux_data_T_27}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _mux_data_T_29 = {mux_data_rawIn_2_sign, _mux_data_T_28}; // @[recFNFromFN.scala:47:20, :48:76]
wire [2:0] _mux_data_T_30 = mux_data_rawIn_2_sExp[2:0]; // @[recFNFromFN.scala:50:23]
wire [6:0] _mux_data_T_31 = {_mux_data_T_29, _mux_data_T_30}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [9:0] _mux_data_T_32 = mux_data_rawIn_2_sig[9:0]; // @[recFNFromFN.scala:51:22]
wire [16:0] _mux_data_T_33 = {_mux_data_T_31, _mux_data_T_32}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [3:0] _mux_data_swizzledNaN_T = _mux_data_T_24[32:29]; // @[FPU.scala:337:8]
wire [6:0] _mux_data_swizzledNaN_T_1 = _mux_data_T_24[22:16]; // @[FPU.scala:338:8]
wire [6:0] _mux_data_swizzledNaN_T_5 = _mux_data_T_24[22:16]; // @[FPU.scala:338:8, :341:8]
wire _mux_data_swizzledNaN_T_2 = &_mux_data_swizzledNaN_T_1; // @[FPU.scala:338:{8,42}]
wire [3:0] _mux_data_swizzledNaN_T_3 = _mux_data_T_24[27:24]; // @[FPU.scala:339:8]
wire _mux_data_swizzledNaN_T_4 = _mux_data_T_33[15]; // @[FPU.scala:340:8]
wire _mux_data_swizzledNaN_T_6 = _mux_data_T_33[16]; // @[FPU.scala:342:8]
wire [14:0] _mux_data_swizzledNaN_T_7 = _mux_data_T_33[14:0]; // @[FPU.scala:343:8]
wire [7:0] mux_data_swizzledNaN_lo_hi = {_mux_data_swizzledNaN_T_5, _mux_data_swizzledNaN_T_6}; // @[FPU.scala:336:26, :341:8, :342:8]
wire [22:0] mux_data_swizzledNaN_lo = {mux_data_swizzledNaN_lo_hi, _mux_data_swizzledNaN_T_7}; // @[FPU.scala:336:26, :343:8]
wire [4:0] mux_data_swizzledNaN_hi_lo = {_mux_data_swizzledNaN_T_3, _mux_data_swizzledNaN_T_4}; // @[FPU.scala:336:26, :339:8, :340:8]
wire [4:0] mux_data_swizzledNaN_hi_hi = {_mux_data_swizzledNaN_T, _mux_data_swizzledNaN_T_2}; // @[FPU.scala:336:26, :337:8, :338:42]
wire [9:0] mux_data_swizzledNaN_hi = {mux_data_swizzledNaN_hi_hi, mux_data_swizzledNaN_hi_lo}; // @[FPU.scala:336:26]
wire [32:0] mux_data_swizzledNaN = {mux_data_swizzledNaN_hi, mux_data_swizzledNaN_lo}; // @[FPU.scala:336:26]
wire [2:0] _mux_data_T_34 = _mux_data_T_24[31:29]; // @[FPU.scala:249:25]
wire _mux_data_T_35 = &_mux_data_T_34; // @[FPU.scala:249:{25,56}]
wire [32:0] _mux_data_T_36 = _mux_data_T_35 ? mux_data_swizzledNaN : _mux_data_T_24; // @[FPU.scala:249:56, :336:26, :344:8]
wire [3:0] _mux_data_swizzledNaN_T_8 = _mux_data_T_15[64:61]; // @[FPU.scala:337:8]
wire [19:0] _mux_data_swizzledNaN_T_9 = _mux_data_T_15[51:32]; // @[FPU.scala:338:8]
wire [19:0] _mux_data_swizzledNaN_T_13 = _mux_data_T_15[51:32]; // @[FPU.scala:338:8, :341:8]
wire _mux_data_swizzledNaN_T_10 = &_mux_data_swizzledNaN_T_9; // @[FPU.scala:338:{8,42}]
wire [6:0] _mux_data_swizzledNaN_T_11 = _mux_data_T_15[59:53]; // @[FPU.scala:339:8]
wire _mux_data_swizzledNaN_T_12 = _mux_data_T_36[31]; // @[FPU.scala:340:8, :344:8]
wire _mux_data_swizzledNaN_T_14 = _mux_data_T_36[32]; // @[FPU.scala:342:8, :344:8]
wire [30:0] _mux_data_swizzledNaN_T_15 = _mux_data_T_36[30:0]; // @[FPU.scala:343:8, :344:8]
wire [20:0] mux_data_swizzledNaN_lo_hi_1 = {_mux_data_swizzledNaN_T_13, _mux_data_swizzledNaN_T_14}; // @[FPU.scala:336:26, :341:8, :342:8]
wire [51:0] mux_data_swizzledNaN_lo_1 = {mux_data_swizzledNaN_lo_hi_1, _mux_data_swizzledNaN_T_15}; // @[FPU.scala:336:26, :343:8]
wire [7:0] mux_data_swizzledNaN_hi_lo_1 = {_mux_data_swizzledNaN_T_11, _mux_data_swizzledNaN_T_12}; // @[FPU.scala:336:26, :339:8, :340:8]
wire [4:0] mux_data_swizzledNaN_hi_hi_1 = {_mux_data_swizzledNaN_T_8, _mux_data_swizzledNaN_T_10}; // @[FPU.scala:336:26, :337:8, :338:42]
wire [12:0] mux_data_swizzledNaN_hi_1 = {mux_data_swizzledNaN_hi_hi_1, mux_data_swizzledNaN_hi_lo_1}; // @[FPU.scala:336:26]
wire [64:0] mux_data_swizzledNaN_1 = {mux_data_swizzledNaN_hi_1, mux_data_swizzledNaN_lo_1}; // @[FPU.scala:336:26]
wire [2:0] _mux_data_T_37 = _mux_data_T_15[63:61]; // @[FPU.scala:249:25]
wire _mux_data_T_38 = &_mux_data_T_37; // @[FPU.scala:249:{25,56}]
wire [64:0] _mux_data_T_39 = _mux_data_T_38 ? mux_data_swizzledNaN_1 : _mux_data_T_15; // @[FPU.scala:249:56, :336:26, :344:8]
wire [63:0] intValue_res; // @[FPU.scala:542:26]
wire [63:0] intValue = intValue_res; // @[FPU.scala:542:26, :549:9]
wire [31:0] intValue_smallInt = in_bits_in1[31:0]; // @[Valid.scala:135:21]
wire [31:0] _intValue_res_T_3 = intValue_smallInt; // @[FPU.scala:544:33, :546:60]
wire _intValue_T = in_bits_typ[1]; // @[Valid.scala:135:21]
wire _intValue_T_1 = ~_intValue_T; // @[package.scala:163:13]
wire _intValue_res_T_1 = in_bits_typ[0]; // @[Valid.scala:135:21]
wire _i2fResults_i2f_io_signedIn_T = in_bits_typ[0]; // @[Valid.scala:135:21]
wire _i2fResults_i2f_io_signedIn_T_2 = in_bits_typ[0]; // @[Valid.scala:135:21]
wire _i2fResults_i2f_io_signedIn_T_4 = in_bits_typ[0]; // @[Valid.scala:135:21]
wire [32:0] _intValue_res_T_2 = {1'h0, intValue_smallInt}; // @[FPU.scala:544:33, :546:45]
wire [32:0] _intValue_res_T_4 = _intValue_res_T_1 ? _intValue_res_T_2 : {_intValue_res_T_3[31], _intValue_res_T_3}; // @[FPU.scala:546:{19,31,45,60}]
assign intValue_res = _intValue_T_1 ? {{31{_intValue_res_T_4[32]}}, _intValue_res_T_4} : _intValue_res_T; // @[FPU.scala:542:{26,39}, :545:{57,66}, :546:{13,19}]
wire _i2fResults_i2f_io_signedIn_T_1 = ~_i2fResults_i2f_io_signedIn_T; // @[FPU.scala:557:{26,38}]
wire _i2fResults_i2f_io_signedIn_T_3 = ~_i2fResults_i2f_io_signedIn_T_2; // @[FPU.scala:557:{26,38}]
wire [32:0] i2fResults_maskedNaN = _i2fResults_i2f_1_io_out & 33'h1EF7FFFFF; // @[FPU.scala:413:25, :556:23]
wire [2:0] _i2fResults_T = _i2fResults_i2f_1_io_out[31:29]; // @[FPU.scala:249:25, :556:23]
wire _i2fResults_T_1 = &_i2fResults_T; // @[FPU.scala:249:{25,56}]
wire [32:0] i2fResults_1_1 = _i2fResults_T_1 ? i2fResults_maskedNaN : _i2fResults_i2f_1_io_out; // @[FPU.scala:249:56, :413:25, :414:10, :556:23]
wire _i2fResults_i2f_io_signedIn_T_5 = ~_i2fResults_i2f_io_signedIn_T_4; // @[FPU.scala:557:{26,38}]
wire [64:0] i2fResults_maskedNaN_1 = _i2fResults_i2f_2_io_out & 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:25, :556:23]
wire [2:0] _i2fResults_T_2 = _i2fResults_i2f_2_io_out[63:61]; // @[FPU.scala:249:25, :556:23]
wire _i2fResults_T_3 = &_i2fResults_T_2; // @[FPU.scala:249:{25,56}]
wire [64:0] i2fResults_2_1 = _i2fResults_T_3 ? i2fResults_maskedNaN_1 : _i2fResults_i2f_2_io_out; // @[FPU.scala:249:56, :413:25, :414:10, :556:23]
wire [47:0] _dataPadded_T = i2fResults_2_1[64:17]; // @[FPU.scala:414:10, :565:55]
wire [64:0] dataPadded_0 = {_dataPadded_T, _i2fResults_i2f_io_out}; // @[FPU.scala:556:23, :565:{44,55}]
wire [31:0] _dataPadded_T_1 = i2fResults_2_1[64:33]; // @[FPU.scala:414:10, :565:55]
wire [64:0] dataPadded_1 = {_dataPadded_T_1, i2fResults_1_1}; // @[FPU.scala:414:10, :565:{44,55}]
wire [64:0] _mux_data_T_41 = _mux_data_T_40 ? dataPadded_1 : dataPadded_0; // @[package.scala:39:{76,86}]
wire [64:0] _mux_data_T_43 = _mux_data_T_42 ? i2fResults_2_1 : _mux_data_T_41; // @[package.scala:39:{76,86}]
wire _mux_data_T_44 = &in_bits_typeTagIn; // @[Valid.scala:135:21]
wire [64:0] _mux_data_T_45 = _mux_data_T_44 ? i2fResults_2_1 : _mux_data_T_43; // @[package.scala:39:{76,86}]
assign mux_data = in_bits_wflags ? _mux_data_T_45 : _mux_data_T_39; // @[Valid.scala:135:21]
wire [4:0] _mux_exc_T_1 = _mux_exc_T ? _i2fResults_i2f_1_io_exceptionFlags : _i2fResults_i2f_io_exceptionFlags; // @[package.scala:39:{76,86}]
wire [4:0] _mux_exc_T_3 = _mux_exc_T_2 ? _i2fResults_i2f_2_io_exceptionFlags : _mux_exc_T_1; // @[package.scala:39:{76,86}]
wire _mux_exc_T_4 = &in_bits_typeTagIn; // @[Valid.scala:135:21]
wire [4:0] _mux_exc_T_5 = _mux_exc_T_4 ? _i2fResults_i2f_2_io_exceptionFlags : _mux_exc_T_3; // @[package.scala:39:{76,86}]
assign mux_exc = in_bits_wflags ? _mux_exc_T_5 : 5'h0; // @[Valid.scala:135:21]
reg io_out_pipe_v; // @[Valid.scala:141:24]
assign io_out_pipe_out_valid = io_out_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [64:0] io_out_pipe_b_data; // @[Valid.scala:142:26]
assign io_out_pipe_out_bits_data = io_out_pipe_b_data; // @[Valid.scala:135:21, :142:26]
reg [4:0] io_out_pipe_b_exc; // @[Valid.scala:142:26]
assign io_out_pipe_out_bits_exc = io_out_pipe_b_exc; // @[Valid.scala:135:21, :142:26]
assign io_out_valid = io_out_pipe_out_valid; // @[Valid.scala:135:21]
assign io_out_bits_data_0 = io_out_pipe_out_bits_data; // @[Valid.scala:135:21]
assign io_out_bits_exc_0 = io_out_pipe_out_bits_exc; // @[Valid.scala:135:21]
always @(posedge clock) begin // @[FPU.scala:528:7]
if (reset) begin // @[FPU.scala:528:7]
in_pipe_v <= 1'h0; // @[Valid.scala:141:24]
io_out_pipe_v <= 1'h0; // @[Valid.scala:141:24]
end
else begin // @[FPU.scala:528:7]
in_pipe_v <= io_in_valid_0; // @[Valid.scala:141:24]
io_out_pipe_v <= in_valid; // @[Valid.scala:135:21, :141:24]
end
if (io_in_valid_0) begin // @[FPU.scala:528:7]
in_pipe_b_ldst <= io_in_bits_ldst_0; // @[Valid.scala:142:26]
in_pipe_b_wen <= io_in_bits_wen_0; // @[Valid.scala:142:26]
in_pipe_b_ren1 <= io_in_bits_ren1_0; // @[Valid.scala:142:26]
in_pipe_b_ren2 <= io_in_bits_ren2_0; // @[Valid.scala:142:26]
in_pipe_b_ren3 <= io_in_bits_ren3_0; // @[Valid.scala:142:26]
in_pipe_b_swap12 <= io_in_bits_swap12_0; // @[Valid.scala:142:26]
in_pipe_b_swap23 <= io_in_bits_swap23_0; // @[Valid.scala:142:26]
in_pipe_b_typeTagIn <= io_in_bits_typeTagIn_0; // @[Valid.scala:142:26]
in_pipe_b_typeTagOut <= io_in_bits_typeTagOut_0; // @[Valid.scala:142:26]
in_pipe_b_fromint <= io_in_bits_fromint_0; // @[Valid.scala:142:26]
in_pipe_b_toint <= io_in_bits_toint_0; // @[Valid.scala:142:26]
in_pipe_b_fastpipe <= io_in_bits_fastpipe_0; // @[Valid.scala:142:26]
in_pipe_b_fma <= io_in_bits_fma_0; // @[Valid.scala:142:26]
in_pipe_b_div <= io_in_bits_div_0; // @[Valid.scala:142:26]
in_pipe_b_sqrt <= io_in_bits_sqrt_0; // @[Valid.scala:142:26]
in_pipe_b_wflags <= io_in_bits_wflags_0; // @[Valid.scala:142:26]
in_pipe_b_vec <= io_in_bits_vec_0; // @[Valid.scala:142:26]
in_pipe_b_rm <= io_in_bits_rm_0; // @[Valid.scala:142:26]
in_pipe_b_typ <= io_in_bits_typ_0; // @[Valid.scala:142:26]
in_pipe_b_in1 <= io_in_bits_in1_0; // @[Valid.scala:142:26]
end
if (in_valid) begin // @[Valid.scala:135:21]
io_out_pipe_b_data <= mux_data; // @[Valid.scala:142:26]
io_out_pipe_b_exc <= mux_exc; // @[Valid.scala:142:26]
end
always @(posedge)
INToRecFN_i64_e5_s11_6 i2fResults_i2f ( // @[FPU.scala:556:23]
.io_signedIn (_i2fResults_i2f_io_signedIn_T_1), // @[FPU.scala:557:26]
.io_in (intValue), // @[FPU.scala:549:9]
.io_roundingMode (in_bits_rm), // @[Valid.scala:135:21]
.io_out (_i2fResults_i2f_io_out),
.io_exceptionFlags (_i2fResults_i2f_io_exceptionFlags)
); // @[FPU.scala:556:23]
INToRecFN_i64_e8_s24_6 i2fResults_i2f_1 ( // @[FPU.scala:556:23]
.io_signedIn (_i2fResults_i2f_io_signedIn_T_3), // @[FPU.scala:557:26]
.io_in (intValue), // @[FPU.scala:549:9]
.io_roundingMode (in_bits_rm), // @[Valid.scala:135:21]
.io_out (_i2fResults_i2f_1_io_out),
.io_exceptionFlags (_i2fResults_i2f_1_io_exceptionFlags)
); // @[FPU.scala:556:23]
INToRecFN_i64_e11_s53_6 i2fResults_i2f_2 ( // @[FPU.scala:556:23]
.io_signedIn (_i2fResults_i2f_io_signedIn_T_5), // @[FPU.scala:557:26]
.io_in (intValue), // @[FPU.scala:549:9]
.io_roundingMode (in_bits_rm), // @[Valid.scala:135:21]
.io_out (_i2fResults_i2f_2_io_out),
.io_exceptionFlags (_i2fResults_i2f_2_io_exceptionFlags)
); // @[FPU.scala:556:23]
assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:528:7]
assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:528:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_533 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_533( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module FPToFP_5 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}, flip lt : UInt<1>}
regreset in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect in_pipe_v, io.in.valid
reg in_pipe_b : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock
when io.in.valid :
connect in_pipe_b, io.in.bits
wire in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}
connect in.valid, in_pipe_v
connect in.bits, in_pipe_b
node _signNum_T = bits(in.bits.rm, 1, 1)
node _signNum_T_1 = xor(in.bits.in1, in.bits.in2)
node _signNum_T_2 = bits(in.bits.rm, 0, 0)
node _signNum_T_3 = not(in.bits.in2)
node _signNum_T_4 = mux(_signNum_T_2, _signNum_T_3, in.bits.in2)
node signNum = mux(_signNum_T, _signNum_T_1, _signNum_T_4)
node _fsgnj_T = bits(signNum, 64, 64)
node _fsgnj_T_1 = bits(in.bits.in1, 63, 0)
node fsgnj = cat(_fsgnj_T, _fsgnj_T_1)
wire fsgnjMux : { data : UInt<65>, exc : UInt<5>}
connect fsgnjMux.exc, UInt<1>(0h0)
connect fsgnjMux.data, fsgnj
when in.bits.wflags :
node _isnan1_T = bits(in.bits.in1, 63, 61)
node isnan1 = andr(_isnan1_T)
node _isnan2_T = bits(in.bits.in2, 63, 61)
node isnan2 = andr(_isnan2_T)
node _isInvalid_T = bits(in.bits.in1, 63, 61)
node _isInvalid_T_1 = andr(_isInvalid_T)
node _isInvalid_T_2 = bits(in.bits.in1, 51, 51)
node _isInvalid_T_3 = eq(_isInvalid_T_2, UInt<1>(0h0))
node _isInvalid_T_4 = and(_isInvalid_T_1, _isInvalid_T_3)
node _isInvalid_T_5 = bits(in.bits.in2, 63, 61)
node _isInvalid_T_6 = andr(_isInvalid_T_5)
node _isInvalid_T_7 = bits(in.bits.in2, 51, 51)
node _isInvalid_T_8 = eq(_isInvalid_T_7, UInt<1>(0h0))
node _isInvalid_T_9 = and(_isInvalid_T_6, _isInvalid_T_8)
node isInvalid = or(_isInvalid_T_4, _isInvalid_T_9)
node isNaNOut = and(isnan1, isnan2)
node _isLHS_T = bits(in.bits.rm, 0, 0)
node _isLHS_T_1 = neq(_isLHS_T, io.lt)
node _isLHS_T_2 = eq(isnan1, UInt<1>(0h0))
node _isLHS_T_3 = and(_isLHS_T_1, _isLHS_T_2)
node isLHS = or(isnan2, _isLHS_T_3)
node _fsgnjMux_exc_T = shl(isInvalid, 4)
connect fsgnjMux.exc, _fsgnjMux_exc_T
node _fsgnjMux_data_T = mux(isLHS, in.bits.in1, in.bits.in2)
node _fsgnjMux_data_T_1 = mux(isNaNOut, UInt<65>(0he008000000000000), _fsgnjMux_data_T)
connect fsgnjMux.data, _fsgnjMux_data_T_1
wire mux : { data : UInt<65>, exc : UInt<5>}
connect mux, fsgnjMux
node _T = eq(in.bits.typeTagOut, UInt<1>(0h0))
when _T :
node _mux_data_T = shr(fsgnjMux.data, 17)
node mux_data_sign = bits(fsgnjMux.data, 64, 64)
node mux_data_fractIn = bits(fsgnjMux.data, 51, 0)
node mux_data_expIn = bits(fsgnjMux.data, 63, 52)
node _mux_data_fractOut_T = shl(mux_data_fractIn, 11)
node mux_data_fractOut = shr(_mux_data_fractOut_T, 53)
node mux_data_expOut_expCode = bits(mux_data_expIn, 11, 9)
node _mux_data_expOut_commonCase_T = add(mux_data_expIn, UInt<6>(0h20))
node _mux_data_expOut_commonCase_T_1 = tail(_mux_data_expOut_commonCase_T, 1)
node _mux_data_expOut_commonCase_T_2 = sub(_mux_data_expOut_commonCase_T_1, UInt<12>(0h800))
node mux_data_expOut_commonCase = tail(_mux_data_expOut_commonCase_T_2, 1)
node _mux_data_expOut_T = eq(mux_data_expOut_expCode, UInt<1>(0h0))
node _mux_data_expOut_T_1 = geq(mux_data_expOut_expCode, UInt<3>(0h6))
node _mux_data_expOut_T_2 = or(_mux_data_expOut_T, _mux_data_expOut_T_1)
node _mux_data_expOut_T_3 = bits(mux_data_expOut_commonCase, 2, 0)
node _mux_data_expOut_T_4 = cat(mux_data_expOut_expCode, _mux_data_expOut_T_3)
node _mux_data_expOut_T_5 = bits(mux_data_expOut_commonCase, 5, 0)
node mux_data_expOut = mux(_mux_data_expOut_T_2, _mux_data_expOut_T_4, _mux_data_expOut_T_5)
node mux_data_hi = cat(mux_data_sign, mux_data_expOut)
node _mux_data_T_1 = cat(mux_data_hi, mux_data_fractOut)
node _mux_data_T_2 = cat(_mux_data_T, _mux_data_T_1)
connect mux.data, _mux_data_T_2
node _T_1 = eq(in.bits.typeTagOut, UInt<1>(0h1))
when _T_1 :
node _mux_data_T_3 = shr(fsgnjMux.data, 33)
node mux_data_sign_1 = bits(fsgnjMux.data, 64, 64)
node mux_data_fractIn_1 = bits(fsgnjMux.data, 51, 0)
node mux_data_expIn_1 = bits(fsgnjMux.data, 63, 52)
node _mux_data_fractOut_T_1 = shl(mux_data_fractIn_1, 24)
node mux_data_fractOut_1 = shr(_mux_data_fractOut_T_1, 53)
node mux_data_expOut_expCode_1 = bits(mux_data_expIn_1, 11, 9)
node _mux_data_expOut_commonCase_T_3 = add(mux_data_expIn_1, UInt<9>(0h100))
node _mux_data_expOut_commonCase_T_4 = tail(_mux_data_expOut_commonCase_T_3, 1)
node _mux_data_expOut_commonCase_T_5 = sub(_mux_data_expOut_commonCase_T_4, UInt<12>(0h800))
node mux_data_expOut_commonCase_1 = tail(_mux_data_expOut_commonCase_T_5, 1)
node _mux_data_expOut_T_6 = eq(mux_data_expOut_expCode_1, UInt<1>(0h0))
node _mux_data_expOut_T_7 = geq(mux_data_expOut_expCode_1, UInt<3>(0h6))
node _mux_data_expOut_T_8 = or(_mux_data_expOut_T_6, _mux_data_expOut_T_7)
node _mux_data_expOut_T_9 = bits(mux_data_expOut_commonCase_1, 5, 0)
node _mux_data_expOut_T_10 = cat(mux_data_expOut_expCode_1, _mux_data_expOut_T_9)
node _mux_data_expOut_T_11 = bits(mux_data_expOut_commonCase_1, 8, 0)
node mux_data_expOut_1 = mux(_mux_data_expOut_T_8, _mux_data_expOut_T_10, _mux_data_expOut_T_11)
node mux_data_hi_1 = cat(mux_data_sign_1, mux_data_expOut_1)
node _mux_data_T_4 = cat(mux_data_hi_1, mux_data_fractOut_1)
node _mux_data_T_5 = cat(_mux_data_T_3, _mux_data_T_4)
connect mux.data, _mux_data_T_5
node _T_2 = eq(in.bits.ren2, UInt<1>(0h0))
node _T_3 = and(in.bits.wflags, _T_2)
when _T_3 :
node _widened_T = bits(in.bits.in1, 63, 61)
node _widened_T_1 = andr(_widened_T)
node widened = mux(_widened_T_1, UInt<65>(0he008000000000000), in.bits.in1)
connect fsgnjMux.data, widened
node _fsgnjMux_exc_T_1 = bits(in.bits.in1, 63, 61)
node _fsgnjMux_exc_T_2 = andr(_fsgnjMux_exc_T_1)
node _fsgnjMux_exc_T_3 = bits(in.bits.in1, 51, 51)
node _fsgnjMux_exc_T_4 = eq(_fsgnjMux_exc_T_3, UInt<1>(0h0))
node _fsgnjMux_exc_T_5 = and(_fsgnjMux_exc_T_2, _fsgnjMux_exc_T_4)
node _fsgnjMux_exc_T_6 = shl(_fsgnjMux_exc_T_5, 4)
connect fsgnjMux.exc, _fsgnjMux_exc_T_6
node _T_4 = eq(in.bits.typeTagOut, UInt<1>(0h0))
node _T_5 = lt(in.bits.typeTagOut, in.bits.typeTagIn)
node _T_6 = or(UInt<1>(0h1), _T_5)
node _T_7 = and(_T_4, _T_6)
when _T_7 :
inst narrower of RecFNToRecFN_10
connect narrower.io.in, in.bits.in1
connect narrower.io.roundingMode, in.bits.rm
connect narrower.io.detectTininess, UInt<1>(0h1)
node _mux_data_T_6 = shr(fsgnjMux.data, 17)
node _mux_data_T_7 = cat(_mux_data_T_6, narrower.io.out)
connect mux.data, _mux_data_T_7
connect mux.exc, narrower.io.exceptionFlags
node _T_8 = eq(in.bits.typeTagOut, UInt<1>(0h1))
node _T_9 = lt(in.bits.typeTagOut, in.bits.typeTagIn)
node _T_10 = or(UInt<1>(0h0), _T_9)
node _T_11 = and(_T_8, _T_10)
when _T_11 :
inst narrower_1 of RecFNToRecFN_11
connect narrower_1.io.in, in.bits.in1
connect narrower_1.io.roundingMode, in.bits.rm
connect narrower_1.io.detectTininess, UInt<1>(0h1)
node _narrowed_maskedNaN_T = not(UInt<33>(0h10800000))
node narrowed_maskedNaN = and(narrower_1.io.out, _narrowed_maskedNaN_T)
node _narrowed_T = bits(narrower_1.io.out, 31, 29)
node _narrowed_T_1 = andr(_narrowed_T)
node narrowed = mux(_narrowed_T_1, narrowed_maskedNaN, narrower_1.io.out)
node _mux_data_T_8 = shr(fsgnjMux.data, 33)
node _mux_data_T_9 = cat(_mux_data_T_8, narrowed)
connect mux.data, _mux_data_T_9
connect mux.exc, narrower_1.io.exceptionFlags
regreset io_out_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect io_out_pipe_v, in.valid
reg io_out_pipe_b : { data : UInt<65>, exc : UInt<5>}, clock
when in.valid :
connect io_out_pipe_b, mux
wire io_out_pipe_out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}
connect io_out_pipe_out.valid, io_out_pipe_v
connect io_out_pipe_out.bits, io_out_pipe_b
connect io.out, io_out_pipe_out | module FPToFP_5( // @[FPU.scala:573:7]
input clock, // @[FPU.scala:573:7]
input reset, // @[FPU.scala:573:7]
input io_in_valid, // @[FPU.scala:574:14]
input io_in_bits_ldst, // @[FPU.scala:574:14]
input io_in_bits_wen, // @[FPU.scala:574:14]
input io_in_bits_ren1, // @[FPU.scala:574:14]
input io_in_bits_ren2, // @[FPU.scala:574:14]
input io_in_bits_ren3, // @[FPU.scala:574:14]
input io_in_bits_swap12, // @[FPU.scala:574:14]
input io_in_bits_swap23, // @[FPU.scala:574:14]
input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:574:14]
input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:574:14]
input io_in_bits_fromint, // @[FPU.scala:574:14]
input io_in_bits_toint, // @[FPU.scala:574:14]
input io_in_bits_fastpipe, // @[FPU.scala:574:14]
input io_in_bits_fma, // @[FPU.scala:574:14]
input io_in_bits_div, // @[FPU.scala:574:14]
input io_in_bits_sqrt, // @[FPU.scala:574:14]
input io_in_bits_wflags, // @[FPU.scala:574:14]
input io_in_bits_vec, // @[FPU.scala:574:14]
input [2:0] io_in_bits_rm, // @[FPU.scala:574:14]
input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:574:14]
input [1:0] io_in_bits_typ, // @[FPU.scala:574:14]
input [1:0] io_in_bits_fmt, // @[FPU.scala:574:14]
input [64:0] io_in_bits_in1, // @[FPU.scala:574:14]
input [64:0] io_in_bits_in2, // @[FPU.scala:574:14]
input [64:0] io_in_bits_in3, // @[FPU.scala:574:14]
output [64:0] io_out_bits_data, // @[FPU.scala:574:14]
output [4:0] io_out_bits_exc, // @[FPU.scala:574:14]
input io_lt // @[FPU.scala:574:14]
);
wire [32:0] _narrower_1_io_out; // @[FPU.scala:619:30]
wire [4:0] _narrower_1_io_exceptionFlags; // @[FPU.scala:619:30]
wire [16:0] _narrower_io_out; // @[FPU.scala:619:30]
wire [4:0] _narrower_io_exceptionFlags; // @[FPU.scala:619:30]
wire io_in_valid_0 = io_in_valid; // @[FPU.scala:573:7]
wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:573:7]
wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:573:7]
wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:573:7]
wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:573:7]
wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:573:7]
wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:573:7]
wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:573:7]
wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:573:7]
wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:573:7]
wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:573:7]
wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:573:7]
wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:573:7]
wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:573:7]
wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:573:7]
wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:573:7]
wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:573:7]
wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:573:7]
wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:573:7]
wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:573:7]
wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:573:7]
wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:573:7]
wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:573:7]
wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:573:7]
wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:573:7]
wire io_lt_0 = io_lt; // @[FPU.scala:573:7]
wire [32:0] _narrowed_maskedNaN_T = 33'h1EF7FFFFF; // @[FPU.scala:413:27]
wire io_out_pipe_out_valid; // @[Valid.scala:135:21]
wire [64:0] io_out_pipe_out_bits_data; // @[Valid.scala:135:21]
wire [4:0] io_out_pipe_out_bits_exc; // @[Valid.scala:135:21]
wire [64:0] io_out_bits_data_0; // @[FPU.scala:573:7]
wire [4:0] io_out_bits_exc_0; // @[FPU.scala:573:7]
wire io_out_valid; // @[FPU.scala:573:7]
reg in_pipe_v; // @[Valid.scala:141:24]
wire in_valid = in_pipe_v; // @[Valid.scala:135:21, :141:24]
reg in_pipe_b_ldst; // @[Valid.scala:142:26]
wire in_bits_ldst = in_pipe_b_ldst; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_wen; // @[Valid.scala:142:26]
wire in_bits_wen = in_pipe_b_wen; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_ren1; // @[Valid.scala:142:26]
wire in_bits_ren1 = in_pipe_b_ren1; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_ren2; // @[Valid.scala:142:26]
wire in_bits_ren2 = in_pipe_b_ren2; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_ren3; // @[Valid.scala:142:26]
wire in_bits_ren3 = in_pipe_b_ren3; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_swap12; // @[Valid.scala:142:26]
wire in_bits_swap12 = in_pipe_b_swap12; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_swap23; // @[Valid.scala:142:26]
wire in_bits_swap23 = in_pipe_b_swap23; // @[Valid.scala:135:21, :142:26]
reg [1:0] in_pipe_b_typeTagIn; // @[Valid.scala:142:26]
wire [1:0] in_bits_typeTagIn = in_pipe_b_typeTagIn; // @[Valid.scala:135:21, :142:26]
reg [1:0] in_pipe_b_typeTagOut; // @[Valid.scala:142:26]
wire [1:0] in_bits_typeTagOut = in_pipe_b_typeTagOut; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_fromint; // @[Valid.scala:142:26]
wire in_bits_fromint = in_pipe_b_fromint; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_toint; // @[Valid.scala:142:26]
wire in_bits_toint = in_pipe_b_toint; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_fastpipe; // @[Valid.scala:142:26]
wire in_bits_fastpipe = in_pipe_b_fastpipe; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_fma; // @[Valid.scala:142:26]
wire in_bits_fma = in_pipe_b_fma; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_div; // @[Valid.scala:142:26]
wire in_bits_div = in_pipe_b_div; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_sqrt; // @[Valid.scala:142:26]
wire in_bits_sqrt = in_pipe_b_sqrt; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_wflags; // @[Valid.scala:142:26]
wire in_bits_wflags = in_pipe_b_wflags; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_vec; // @[Valid.scala:142:26]
wire in_bits_vec = in_pipe_b_vec; // @[Valid.scala:135:21, :142:26]
reg [2:0] in_pipe_b_rm; // @[Valid.scala:142:26]
wire [2:0] in_bits_rm = in_pipe_b_rm; // @[Valid.scala:135:21, :142:26]
reg [1:0] in_pipe_b_fmaCmd; // @[Valid.scala:142:26]
wire [1:0] in_bits_fmaCmd = in_pipe_b_fmaCmd; // @[Valid.scala:135:21, :142:26]
reg [1:0] in_pipe_b_typ; // @[Valid.scala:142:26]
wire [1:0] in_bits_typ = in_pipe_b_typ; // @[Valid.scala:135:21, :142:26]
reg [1:0] in_pipe_b_fmt; // @[Valid.scala:142:26]
wire [1:0] in_bits_fmt = in_pipe_b_fmt; // @[Valid.scala:135:21, :142:26]
reg [64:0] in_pipe_b_in1; // @[Valid.scala:142:26]
wire [64:0] in_bits_in1 = in_pipe_b_in1; // @[Valid.scala:135:21, :142:26]
reg [64:0] in_pipe_b_in2; // @[Valid.scala:142:26]
wire [64:0] in_bits_in2 = in_pipe_b_in2; // @[Valid.scala:135:21, :142:26]
reg [64:0] in_pipe_b_in3; // @[Valid.scala:142:26]
wire [64:0] in_bits_in3 = in_pipe_b_in3; // @[Valid.scala:135:21, :142:26]
wire _signNum_T = in_bits_rm[1]; // @[Valid.scala:135:21]
wire [64:0] _signNum_T_1 = in_bits_in1 ^ in_bits_in2; // @[Valid.scala:135:21]
wire _signNum_T_2 = in_bits_rm[0]; // @[Valid.scala:135:21]
wire _isLHS_T = in_bits_rm[0]; // @[Valid.scala:135:21]
wire [64:0] _signNum_T_3 = ~in_bits_in2; // @[Valid.scala:135:21]
wire [64:0] _signNum_T_4 = _signNum_T_2 ? _signNum_T_3 : in_bits_in2; // @[Valid.scala:135:21]
wire [64:0] signNum = _signNum_T ? _signNum_T_1 : _signNum_T_4; // @[FPU.scala:582:{20,31,48,66}]
wire _fsgnj_T = signNum[64]; // @[FPU.scala:582:20, :583:26]
wire [63:0] _fsgnj_T_1 = in_bits_in1[63:0]; // @[Valid.scala:135:21]
wire [64:0] fsgnj = {_fsgnj_T, _fsgnj_T_1}; // @[FPU.scala:583:{18,26,45}]
wire [64:0] fsgnjMux_data; // @[FPU.scala:585:22]
wire [4:0] fsgnjMux_exc; // @[FPU.scala:585:22]
wire [2:0] _isnan1_T = in_bits_in1[63:61]; // @[Valid.scala:135:21]
wire [2:0] _isInvalid_T = in_bits_in1[63:61]; // @[Valid.scala:135:21]
wire [2:0] _widened_T = in_bits_in1[63:61]; // @[Valid.scala:135:21]
wire [2:0] _fsgnjMux_exc_T_1 = in_bits_in1[63:61]; // @[Valid.scala:135:21]
wire isnan1 = &_isnan1_T; // @[FPU.scala:249:{25,56}]
wire [2:0] _isnan2_T = in_bits_in2[63:61]; // @[Valid.scala:135:21]
wire [2:0] _isInvalid_T_5 = in_bits_in2[63:61]; // @[Valid.scala:135:21]
wire isnan2 = &_isnan2_T; // @[FPU.scala:249:{25,56}]
wire _isInvalid_T_1 = &_isInvalid_T; // @[FPU.scala:249:{25,56}]
wire _isInvalid_T_2 = in_bits_in1[51]; // @[Valid.scala:135:21]
wire _fsgnjMux_exc_T_3 = in_bits_in1[51]; // @[Valid.scala:135:21]
wire _isInvalid_T_3 = ~_isInvalid_T_2; // @[FPU.scala:250:{37,39}]
wire _isInvalid_T_4 = _isInvalid_T_1 & _isInvalid_T_3; // @[FPU.scala:249:56, :250:{34,37}]
wire _isInvalid_T_6 = &_isInvalid_T_5; // @[FPU.scala:249:{25,56}]
wire _isInvalid_T_7 = in_bits_in2[51]; // @[Valid.scala:135:21]
wire _isInvalid_T_8 = ~_isInvalid_T_7; // @[FPU.scala:250:{37,39}]
wire _isInvalid_T_9 = _isInvalid_T_6 & _isInvalid_T_8; // @[FPU.scala:249:56, :250:{34,37}]
wire isInvalid = _isInvalid_T_4 | _isInvalid_T_9; // @[FPU.scala:250:34, :592:49]
wire isNaNOut = isnan1 & isnan2; // @[FPU.scala:249:56, :593:27]
wire _isLHS_T_1 = _isLHS_T != io_lt_0; // @[FPU.scala:573:7, :594:{37,41}]
wire _isLHS_T_2 = ~isnan1; // @[FPU.scala:249:56, :594:54]
wire _isLHS_T_3 = _isLHS_T_1 & _isLHS_T_2; // @[FPU.scala:594:{41,51,54}]
wire isLHS = isnan2 | _isLHS_T_3; // @[FPU.scala:249:56, :594:{24,51}]
wire [4:0] _fsgnjMux_exc_T = {isInvalid, 4'h0}; // @[FPU.scala:592:49, :595:31]
wire [64:0] _fsgnjMux_data_T = isLHS ? in_bits_in1 : in_bits_in2; // @[Valid.scala:135:21]
wire [64:0] _fsgnjMux_data_T_1 = isNaNOut ? 65'hE008000000000000 : _fsgnjMux_data_T; // @[FPU.scala:593:27, :596:{25,53}]
wire [64:0] mux_data; // @[FPU.scala:601:24]
wire [4:0] mux_exc; // @[FPU.scala:601:24]
wire _T_7 = in_bits_typeTagOut == 2'h0; // @[Valid.scala:135:21]
wire [47:0] _mux_data_T = fsgnjMux_data[64:17]; // @[FPU.scala:585:22, :604:37]
wire [47:0] _mux_data_T_6 = fsgnjMux_data[64:17]; // @[FPU.scala:585:22, :604:37, :624:39]
wire mux_data_sign = fsgnjMux_data[64]; // @[FPU.scala:274:17, :585:22]
wire mux_data_sign_1 = fsgnjMux_data[64]; // @[FPU.scala:274:17, :585:22]
wire [51:0] mux_data_fractIn = fsgnjMux_data[51:0]; // @[FPU.scala:275:20, :585:22]
wire [51:0] mux_data_fractIn_1 = fsgnjMux_data[51:0]; // @[FPU.scala:275:20, :585:22]
wire [11:0] mux_data_expIn = fsgnjMux_data[63:52]; // @[FPU.scala:276:18, :585:22]
wire [11:0] mux_data_expIn_1 = fsgnjMux_data[63:52]; // @[FPU.scala:276:18, :585:22]
wire [62:0] _mux_data_fractOut_T = {mux_data_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28]
wire [9:0] mux_data_fractOut = _mux_data_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] mux_data_expOut_expCode = mux_data_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _mux_data_expOut_commonCase_T = {1'h0, mux_data_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31]
wire [11:0] _mux_data_expOut_commonCase_T_1 = _mux_data_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _mux_data_expOut_commonCase_T_2 = {1'h0, _mux_data_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] mux_data_expOut_commonCase = _mux_data_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _mux_data_expOut_T = mux_data_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _mux_data_expOut_T_1 = mux_data_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _mux_data_expOut_T_2 = _mux_data_expOut_T | _mux_data_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [2:0] _mux_data_expOut_T_3 = mux_data_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69]
wire [5:0] _mux_data_expOut_T_4 = {mux_data_expOut_expCode, _mux_data_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [5:0] _mux_data_expOut_T_5 = mux_data_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97]
wire [5:0] mux_data_expOut = _mux_data_expOut_T_2 ? _mux_data_expOut_T_4 : _mux_data_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [6:0] mux_data_hi = {mux_data_sign, mux_data_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [16:0] _mux_data_T_1 = {mux_data_hi, mux_data_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [64:0] _mux_data_T_2 = {_mux_data_T, _mux_data_T_1}; // @[FPU.scala:283:8, :604:{22,37}]
wire _T_8 = in_bits_typeTagOut == 2'h1; // @[Valid.scala:135:21]
wire [31:0] _mux_data_T_3 = fsgnjMux_data[64:33]; // @[FPU.scala:585:22, :604:37]
wire [31:0] _mux_data_T_8 = fsgnjMux_data[64:33]; // @[FPU.scala:585:22, :604:37, :624:39]
wire [75:0] _mux_data_fractOut_T_1 = {mux_data_fractIn_1, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] mux_data_fractOut_1 = _mux_data_fractOut_T_1[75:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] mux_data_expOut_expCode_1 = mux_data_expIn_1[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _mux_data_expOut_commonCase_T_3 = {1'h0, mux_data_expIn_1} + 13'h100; // @[FPU.scala:276:18, :280:31]
wire [11:0] _mux_data_expOut_commonCase_T_4 = _mux_data_expOut_commonCase_T_3[11:0]; // @[FPU.scala:280:31]
wire [12:0] _mux_data_expOut_commonCase_T_5 = {1'h0, _mux_data_expOut_commonCase_T_4} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] mux_data_expOut_commonCase_1 = _mux_data_expOut_commonCase_T_5[11:0]; // @[FPU.scala:280:50]
wire _mux_data_expOut_T_6 = mux_data_expOut_expCode_1 == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _mux_data_expOut_T_7 = mux_data_expOut_expCode_1 > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _mux_data_expOut_T_8 = _mux_data_expOut_T_6 | _mux_data_expOut_T_7; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _mux_data_expOut_T_9 = mux_data_expOut_commonCase_1[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _mux_data_expOut_T_10 = {mux_data_expOut_expCode_1, _mux_data_expOut_T_9}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] _mux_data_expOut_T_11 = mux_data_expOut_commonCase_1[8:0]; // @[FPU.scala:280:50, :281:97]
wire [8:0] mux_data_expOut_1 = _mux_data_expOut_T_8 ? _mux_data_expOut_T_10 : _mux_data_expOut_T_11; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] mux_data_hi_1 = {mux_data_sign_1, mux_data_expOut_1}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] _mux_data_T_4 = {mux_data_hi_1, mux_data_fractOut_1}; // @[FPU.scala:277:38, :283:8]
wire [64:0] _mux_data_T_5 = {_mux_data_T_3, _mux_data_T_4}; // @[FPU.scala:283:8, :604:{22,37}]
wire _T_3 = in_bits_wflags & ~in_bits_ren2; // @[Valid.scala:135:21]
wire _widened_T_1 = &_widened_T; // @[FPU.scala:249:{25,56}]
wire [64:0] widened = _widened_T_1 ? 65'hE008000000000000 : in_bits_in1; // @[Valid.scala:135:21]
assign fsgnjMux_data = _T_3 ? widened : in_bits_wflags ? _fsgnjMux_data_T_1 : fsgnj; // @[Valid.scala:135:21]
wire _fsgnjMux_exc_T_2 = &_fsgnjMux_exc_T_1; // @[FPU.scala:249:{25,56}]
wire _fsgnjMux_exc_T_4 = ~_fsgnjMux_exc_T_3; // @[FPU.scala:250:{37,39}]
wire _fsgnjMux_exc_T_5 = _fsgnjMux_exc_T_2 & _fsgnjMux_exc_T_4; // @[FPU.scala:249:56, :250:{34,37}]
wire [4:0] _fsgnjMux_exc_T_6 = {_fsgnjMux_exc_T_5, 4'h0}; // @[FPU.scala:250:34, :595:31, :613:51]
assign fsgnjMux_exc = _T_3 ? _fsgnjMux_exc_T_6 : in_bits_wflags ? _fsgnjMux_exc_T : 5'h0; // @[Valid.scala:135:21]
wire [64:0] _mux_data_T_7 = {_mux_data_T_6, _narrower_io_out}; // @[FPU.scala:619:30, :624:{24,39}]
wire _T_11 = _T_8 & in_bits_typeTagOut < in_bits_typeTagIn; // @[Valid.scala:135:21]
wire [32:0] narrowed_maskedNaN = _narrower_1_io_out & 33'h1EF7FFFFF; // @[FPU.scala:413:25, :619:30]
wire [2:0] _narrowed_T = _narrower_1_io_out[31:29]; // @[FPU.scala:249:25, :619:30]
wire _narrowed_T_1 = &_narrowed_T; // @[FPU.scala:249:{25,56}]
wire [32:0] narrowed = _narrowed_T_1 ? narrowed_maskedNaN : _narrower_1_io_out; // @[FPU.scala:249:56, :413:25, :414:10, :619:30]
wire [64:0] _mux_data_T_9 = {_mux_data_T_8, narrowed}; // @[FPU.scala:414:10, :624:{24,39}]
assign mux_data = _T_3 ? (_T_11 ? _mux_data_T_9 : _T_7 ? _mux_data_T_7 : _T_8 ? _mux_data_T_5 : fsgnjMux_data) : _T_8 ? _mux_data_T_5 : _T_7 ? _mux_data_T_2 : fsgnjMux_data; // @[FPU.scala:585:22, :601:24, :603:{18,36}, :604:{16,22}, :608:{24,42}, :618:{76,126}, :624:{18,24}]
assign mux_exc = _T_3 ? (_T_11 ? _narrower_1_io_exceptionFlags : _T_7 ? _narrower_io_exceptionFlags : fsgnjMux_exc) : fsgnjMux_exc; // @[FPU.scala:585:22, :601:24, :603:18, :608:{24,42}, :618:{76,126}, :619:30, :625:17]
reg io_out_pipe_v; // @[Valid.scala:141:24]
assign io_out_pipe_out_valid = io_out_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [64:0] io_out_pipe_b_data; // @[Valid.scala:142:26]
assign io_out_pipe_out_bits_data = io_out_pipe_b_data; // @[Valid.scala:135:21, :142:26]
reg [4:0] io_out_pipe_b_exc; // @[Valid.scala:142:26]
assign io_out_pipe_out_bits_exc = io_out_pipe_b_exc; // @[Valid.scala:135:21, :142:26]
assign io_out_valid = io_out_pipe_out_valid; // @[Valid.scala:135:21]
assign io_out_bits_data_0 = io_out_pipe_out_bits_data; // @[Valid.scala:135:21]
assign io_out_bits_exc_0 = io_out_pipe_out_bits_exc; // @[Valid.scala:135:21]
always @(posedge clock) begin // @[FPU.scala:573:7]
if (reset) begin // @[FPU.scala:573:7]
in_pipe_v <= 1'h0; // @[Valid.scala:141:24]
io_out_pipe_v <= 1'h0; // @[Valid.scala:141:24]
end
else begin // @[FPU.scala:573:7]
in_pipe_v <= io_in_valid_0; // @[Valid.scala:141:24]
io_out_pipe_v <= in_valid; // @[Valid.scala:135:21, :141:24]
end
if (io_in_valid_0) begin // @[FPU.scala:573:7]
in_pipe_b_ldst <= io_in_bits_ldst_0; // @[Valid.scala:142:26]
in_pipe_b_wen <= io_in_bits_wen_0; // @[Valid.scala:142:26]
in_pipe_b_ren1 <= io_in_bits_ren1_0; // @[Valid.scala:142:26]
in_pipe_b_ren2 <= io_in_bits_ren2_0; // @[Valid.scala:142:26]
in_pipe_b_ren3 <= io_in_bits_ren3_0; // @[Valid.scala:142:26]
in_pipe_b_swap12 <= io_in_bits_swap12_0; // @[Valid.scala:142:26]
in_pipe_b_swap23 <= io_in_bits_swap23_0; // @[Valid.scala:142:26]
in_pipe_b_typeTagIn <= io_in_bits_typeTagIn_0; // @[Valid.scala:142:26]
in_pipe_b_typeTagOut <= io_in_bits_typeTagOut_0; // @[Valid.scala:142:26]
in_pipe_b_fromint <= io_in_bits_fromint_0; // @[Valid.scala:142:26]
in_pipe_b_toint <= io_in_bits_toint_0; // @[Valid.scala:142:26]
in_pipe_b_fastpipe <= io_in_bits_fastpipe_0; // @[Valid.scala:142:26]
in_pipe_b_fma <= io_in_bits_fma_0; // @[Valid.scala:142:26]
in_pipe_b_div <= io_in_bits_div_0; // @[Valid.scala:142:26]
in_pipe_b_sqrt <= io_in_bits_sqrt_0; // @[Valid.scala:142:26]
in_pipe_b_wflags <= io_in_bits_wflags_0; // @[Valid.scala:142:26]
in_pipe_b_vec <= io_in_bits_vec_0; // @[Valid.scala:142:26]
in_pipe_b_rm <= io_in_bits_rm_0; // @[Valid.scala:142:26]
in_pipe_b_fmaCmd <= io_in_bits_fmaCmd_0; // @[Valid.scala:142:26]
in_pipe_b_typ <= io_in_bits_typ_0; // @[Valid.scala:142:26]
in_pipe_b_fmt <= io_in_bits_fmt_0; // @[Valid.scala:142:26]
in_pipe_b_in1 <= io_in_bits_in1_0; // @[Valid.scala:142:26]
in_pipe_b_in2 <= io_in_bits_in2_0; // @[Valid.scala:142:26]
in_pipe_b_in3 <= io_in_bits_in3_0; // @[Valid.scala:142:26]
end
if (in_valid) begin // @[Valid.scala:135:21]
io_out_pipe_b_data <= mux_data; // @[Valid.scala:142:26]
io_out_pipe_b_exc <= mux_exc; // @[Valid.scala:142:26]
end
always @(posedge)
RecFNToRecFN_10 narrower ( // @[FPU.scala:619:30]
.io_in (in_bits_in1), // @[Valid.scala:135:21]
.io_roundingMode (in_bits_rm), // @[Valid.scala:135:21]
.io_out (_narrower_io_out),
.io_exceptionFlags (_narrower_io_exceptionFlags)
); // @[FPU.scala:619:30]
RecFNToRecFN_11 narrower_1 ( // @[FPU.scala:619:30]
.io_in (in_bits_in1), // @[Valid.scala:135:21]
.io_roundingMode (in_bits_rm), // @[Valid.scala:135:21]
.io_out (_narrower_1_io_out),
.io_exceptionFlags (_narrower_1_io_exceptionFlags)
); // @[FPU.scala:619:30]
assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:573:7]
assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:573:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLCToNoC_2 :
input clock : Clock
input reset : Reset
output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<65>, egress_id : UInt}}}
inst q of Queue1_TLBundleC_a32d64s6k5z4c_2
connect q.clock, clock
connect q.reset, reset
wire has_body : UInt<1>
node _head_T = and(q.io.deq.ready, q.io.deq.valid)
node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0)
node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1)
node head_beats1_decode = shr(_head_beats1_decode_T_2, 3)
node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0)
node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0))
regreset head_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _head_counter1_T = sub(head_counter, UInt<1>(0h1))
node head_counter1 = tail(_head_counter1_T, 1)
node head = eq(head_counter, UInt<1>(0h0))
node _head_last_T = eq(head_counter, UInt<1>(0h1))
node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0))
node head_last = or(_head_last_T, _head_last_T_1)
node head_done = and(head_last, _head_T)
node _head_count_T = not(head_counter1)
node head_count = and(head_beats1, _head_count_T)
when _head_T :
node _head_counter_T = mux(head, head_beats1, head_counter1)
connect head_counter, _head_counter_T
node _tail_T = and(q.io.deq.ready, q.io.deq.valid)
node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0)
node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1)
node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 3)
node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0)
node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0))
regreset tail_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1))
node tail_counter1 = tail(_tail_counter1_T, 1)
node tail_first = eq(tail_counter, UInt<1>(0h0))
node _tail_last_T = eq(tail_counter, UInt<1>(0h1))
node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0))
node tail = or(_tail_last_T, _tail_last_T_1)
node tail_done = and(tail, _tail_T)
node _tail_count_T = not(tail_counter1)
node tail_count = and(tail_beats1, _tail_count_T)
when _tail_T :
node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1)
connect tail_counter, _tail_counter_T
node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt)
node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address)
node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param)
node const_hi = cat(const_hi_hi, q.io.deq.bits.size)
node const = cat(const_hi, const_lo)
regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0)
connect io.flit.valid, q.io.deq.valid
node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0))
node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T)
node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1)
connect q.io.deq.ready, _q_io_deq_ready_T_2
node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0))
node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T)
connect io.flit.bits.head, _io_flit_bits_head_T_1
node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0))
node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T)
node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1)
connect io.flit.bits.tail, _io_flit_bits_tail_T_2
node _io_flit_bits_egress_id_requestOH_T = xor(q.io.deq.bits.address, UInt<1>(0h0))
node _io_flit_bits_egress_id_requestOH_T_1 = cvt(_io_flit_bits_egress_id_requestOH_T)
node _io_flit_bits_egress_id_requestOH_T_2 = and(_io_flit_bits_egress_id_requestOH_T_1, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_3 = asSInt(_io_flit_bits_egress_id_requestOH_T_2)
node _io_flit_bits_egress_id_requestOH_T_4 = eq(_io_flit_bits_egress_id_requestOH_T_3, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_5 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_4)
node io_flit_bits_egress_id_requestOH_0 = and(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_5)
node _io_flit_bits_egress_id_requestOH_T_6 = xor(q.io.deq.bits.address, UInt<1>(0h0))
node _io_flit_bits_egress_id_requestOH_T_7 = cvt(_io_flit_bits_egress_id_requestOH_T_6)
node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_7, asSInt(UInt<9>(0hc0)))
node _io_flit_bits_egress_id_requestOH_T_9 = asSInt(_io_flit_bits_egress_id_requestOH_T_8)
node _io_flit_bits_egress_id_requestOH_T_10 = eq(_io_flit_bits_egress_id_requestOH_T_9, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_11 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_10)
node io_flit_bits_egress_id_requestOH_1 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_11)
node _io_flit_bits_egress_id_requestOH_T_12 = xor(q.io.deq.bits.address, UInt<7>(0h40))
node _io_flit_bits_egress_id_requestOH_T_13 = cvt(_io_flit_bits_egress_id_requestOH_T_12)
node _io_flit_bits_egress_id_requestOH_T_14 = and(_io_flit_bits_egress_id_requestOH_T_13, asSInt(UInt<9>(0hc0)))
node _io_flit_bits_egress_id_requestOH_T_15 = asSInt(_io_flit_bits_egress_id_requestOH_T_14)
node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_17 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_16)
node io_flit_bits_egress_id_requestOH_2 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_17)
node _io_flit_bits_egress_id_requestOH_T_18 = xor(q.io.deq.bits.address, UInt<8>(0h80))
node _io_flit_bits_egress_id_requestOH_T_19 = cvt(_io_flit_bits_egress_id_requestOH_T_18)
node _io_flit_bits_egress_id_requestOH_T_20 = and(_io_flit_bits_egress_id_requestOH_T_19, asSInt(UInt<9>(0hc0)))
node _io_flit_bits_egress_id_requestOH_T_21 = asSInt(_io_flit_bits_egress_id_requestOH_T_20)
node _io_flit_bits_egress_id_requestOH_T_22 = eq(_io_flit_bits_egress_id_requestOH_T_21, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_23 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_22)
node io_flit_bits_egress_id_requestOH_3 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_23)
node _io_flit_bits_egress_id_requestOH_T_24 = xor(q.io.deq.bits.address, UInt<8>(0hc0))
node _io_flit_bits_egress_id_requestOH_T_25 = cvt(_io_flit_bits_egress_id_requestOH_T_24)
node _io_flit_bits_egress_id_requestOH_T_26 = and(_io_flit_bits_egress_id_requestOH_T_25, asSInt(UInt<9>(0hc0)))
node _io_flit_bits_egress_id_requestOH_T_27 = asSInt(_io_flit_bits_egress_id_requestOH_T_26)
node _io_flit_bits_egress_id_requestOH_T_28 = eq(_io_flit_bits_egress_id_requestOH_T_27, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_29 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_28)
node io_flit_bits_egress_id_requestOH_4 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_29)
node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<4>(0hb), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<4>(0he), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<5>(0h11), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<5>(0h14), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<5>(0h17), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1)
node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2)
node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3)
node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4)
wire _io_flit_bits_egress_id_WIRE : UInt<5>
connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8
connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE
node _io_flit_bits_payload_T = mux(is_body, body, const)
connect io.flit.bits.payload, _io_flit_bits_payload_T
node _T = and(io.flit.ready, io.flit.valid)
node _T_1 = and(_T, io.flit.bits.head)
when _T_1 :
connect is_body, UInt<1>(0h1)
node _T_2 = and(io.flit.ready, io.flit.valid)
node _T_3 = and(_T_2, io.flit.bits.tail)
when _T_3 :
connect is_body, UInt<1>(0h0)
node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0)
connect has_body, has_body_opdata
connect q.io.enq, io.protocol
node _q_io_enq_bits_source_T = or(io.protocol.bits.source, UInt<6>(0h28))
connect q.io.enq.bits.source, _q_io_enq_bits_source_T | module TLCToNoC_2( // @[TilelinkAdapters.scala:151:7]
input clock, // @[TilelinkAdapters.scala:151:7]
input reset, // @[TilelinkAdapters.scala:151:7]
output io_protocol_ready, // @[TilelinkAdapters.scala:19:14]
input io_protocol_valid, // @[TilelinkAdapters.scala:19:14]
input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14]
input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14]
input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14]
input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14]
input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14]
input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14]
input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14]
input io_flit_ready, // @[TilelinkAdapters.scala:19:14]
output io_flit_valid, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14]
output [64:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14]
output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14]
);
wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17]
wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17]
wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17]
wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17]
wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17]
wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17]
wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71]
reg [8:0] head_counter; // @[Edges.scala:229:27]
wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0; // @[package.scala:243:{46,71,76}]
reg [8:0] tail_counter; // @[Edges.scala:229:27]
reg is_body; // @[TilelinkAdapters.scala:39:24]
wire q_io_deq_ready = io_flit_ready & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36]
wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25]
wire io_flit_bits_tail_0 = (tail_counter == 9'h1 | tail_beats1 == 9'h0) & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36, :221:14, :229:27, :232:{25,33,43}]
wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TilelinkAdapters.scala:151:7]
if (reset) begin // @[TilelinkAdapters.scala:151:7]
head_counter <= 9'h0; // @[Edges.scala:229:27]
tail_counter <= 9'h0; // @[Edges.scala:229:27]
is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :151:7]
end
else begin // @[TilelinkAdapters.scala:151:7]
if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35]
head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0) : head_counter - 9'h1; // @[package.scala:243:{46,71,76}]
tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21]
end
is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_93 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_95
connect io_out_sink_valid_1.clock, clock
connect io_out_sink_valid_1.reset, reset
connect io_out_sink_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_93( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_95 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SwitchAllocator_14 :
input clock : Clock
input reset : Reset
output io : { req : { flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1]}, credit_alloc : { `2` : { alloc : UInt<1>, tail : UInt<1>}[8], `1` : { alloc : UInt<1>, tail : UInt<1>}[8], `0` : { alloc : UInt<1>, tail : UInt<1>}[8]}, switch_sel : { `2` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}}
inst arbs_0 of SwitchArbiter_64
connect arbs_0.clock, clock
connect arbs_0.reset, reset
inst arbs_1 of SwitchArbiter_65
connect arbs_1.clock, clock
connect arbs_1.reset, reset
inst arbs_2 of SwitchArbiter_66
connect arbs_2.clock, clock
connect arbs_2.reset, reset
connect arbs_0.io.out[0].ready, UInt<1>(0h1)
connect arbs_1.io.out[0].ready, UInt<1>(0h1)
connect arbs_2.io.out[0].ready, UInt<1>(0h1)
wire fires : UInt<1>[3]
node _arbs_0_io_in_0_valid_T = or(io.req.`0`[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[1])
node _arbs_0_io_in_0_valid_T_1 = or(_arbs_0_io_in_0_valid_T, io.req.`0`[0].bits.vc_sel.`0`[2])
node _arbs_0_io_in_0_valid_T_2 = or(_arbs_0_io_in_0_valid_T_1, io.req.`0`[0].bits.vc_sel.`0`[3])
node _arbs_0_io_in_0_valid_T_3 = or(_arbs_0_io_in_0_valid_T_2, io.req.`0`[0].bits.vc_sel.`0`[4])
node _arbs_0_io_in_0_valid_T_4 = or(_arbs_0_io_in_0_valid_T_3, io.req.`0`[0].bits.vc_sel.`0`[5])
node _arbs_0_io_in_0_valid_T_5 = or(_arbs_0_io_in_0_valid_T_4, io.req.`0`[0].bits.vc_sel.`0`[6])
node _arbs_0_io_in_0_valid_T_6 = or(_arbs_0_io_in_0_valid_T_5, io.req.`0`[0].bits.vc_sel.`0`[7])
node _arbs_0_io_in_0_valid_T_7 = and(io.req.`0`[0].valid, _arbs_0_io_in_0_valid_T_6)
connect arbs_0.io.in[0].valid, _arbs_0_io_in_0_valid_T_7
connect arbs_0.io.in[0].bits.tail, io.req.`0`[0].bits.tail
connect arbs_0.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0]
connect arbs_0.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1]
connect arbs_0.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2]
connect arbs_0.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3]
connect arbs_0.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4]
connect arbs_0.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5]
connect arbs_0.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6]
connect arbs_0.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7]
connect arbs_0.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0]
connect arbs_0.io.in[0].bits.vc_sel.`1`[1], io.req.`0`[0].bits.vc_sel.`1`[1]
connect arbs_0.io.in[0].bits.vc_sel.`1`[2], io.req.`0`[0].bits.vc_sel.`1`[2]
connect arbs_0.io.in[0].bits.vc_sel.`1`[3], io.req.`0`[0].bits.vc_sel.`1`[3]
connect arbs_0.io.in[0].bits.vc_sel.`1`[4], io.req.`0`[0].bits.vc_sel.`1`[4]
connect arbs_0.io.in[0].bits.vc_sel.`1`[5], io.req.`0`[0].bits.vc_sel.`1`[5]
connect arbs_0.io.in[0].bits.vc_sel.`1`[6], io.req.`0`[0].bits.vc_sel.`1`[6]
connect arbs_0.io.in[0].bits.vc_sel.`1`[7], io.req.`0`[0].bits.vc_sel.`1`[7]
connect arbs_0.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0]
connect arbs_0.io.in[0].bits.vc_sel.`2`[1], io.req.`0`[0].bits.vc_sel.`2`[1]
connect arbs_0.io.in[0].bits.vc_sel.`2`[2], io.req.`0`[0].bits.vc_sel.`2`[2]
connect arbs_0.io.in[0].bits.vc_sel.`2`[3], io.req.`0`[0].bits.vc_sel.`2`[3]
connect arbs_0.io.in[0].bits.vc_sel.`2`[4], io.req.`0`[0].bits.vc_sel.`2`[4]
connect arbs_0.io.in[0].bits.vc_sel.`2`[5], io.req.`0`[0].bits.vc_sel.`2`[5]
connect arbs_0.io.in[0].bits.vc_sel.`2`[6], io.req.`0`[0].bits.vc_sel.`2`[6]
connect arbs_0.io.in[0].bits.vc_sel.`2`[7], io.req.`0`[0].bits.vc_sel.`2`[7]
node _fires_0_T = and(arbs_0.io.in[0].ready, arbs_0.io.in[0].valid)
connect fires[0], _fires_0_T
node _arbs_1_io_in_0_valid_T = or(io.req.`0`[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[1])
node _arbs_1_io_in_0_valid_T_1 = or(_arbs_1_io_in_0_valid_T, io.req.`0`[0].bits.vc_sel.`1`[2])
node _arbs_1_io_in_0_valid_T_2 = or(_arbs_1_io_in_0_valid_T_1, io.req.`0`[0].bits.vc_sel.`1`[3])
node _arbs_1_io_in_0_valid_T_3 = or(_arbs_1_io_in_0_valid_T_2, io.req.`0`[0].bits.vc_sel.`1`[4])
node _arbs_1_io_in_0_valid_T_4 = or(_arbs_1_io_in_0_valid_T_3, io.req.`0`[0].bits.vc_sel.`1`[5])
node _arbs_1_io_in_0_valid_T_5 = or(_arbs_1_io_in_0_valid_T_4, io.req.`0`[0].bits.vc_sel.`1`[6])
node _arbs_1_io_in_0_valid_T_6 = or(_arbs_1_io_in_0_valid_T_5, io.req.`0`[0].bits.vc_sel.`1`[7])
node _arbs_1_io_in_0_valid_T_7 = and(io.req.`0`[0].valid, _arbs_1_io_in_0_valid_T_6)
connect arbs_1.io.in[0].valid, _arbs_1_io_in_0_valid_T_7
connect arbs_1.io.in[0].bits.tail, io.req.`0`[0].bits.tail
connect arbs_1.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0]
connect arbs_1.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1]
connect arbs_1.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2]
connect arbs_1.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3]
connect arbs_1.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4]
connect arbs_1.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5]
connect arbs_1.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6]
connect arbs_1.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7]
connect arbs_1.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0]
connect arbs_1.io.in[0].bits.vc_sel.`1`[1], io.req.`0`[0].bits.vc_sel.`1`[1]
connect arbs_1.io.in[0].bits.vc_sel.`1`[2], io.req.`0`[0].bits.vc_sel.`1`[2]
connect arbs_1.io.in[0].bits.vc_sel.`1`[3], io.req.`0`[0].bits.vc_sel.`1`[3]
connect arbs_1.io.in[0].bits.vc_sel.`1`[4], io.req.`0`[0].bits.vc_sel.`1`[4]
connect arbs_1.io.in[0].bits.vc_sel.`1`[5], io.req.`0`[0].bits.vc_sel.`1`[5]
connect arbs_1.io.in[0].bits.vc_sel.`1`[6], io.req.`0`[0].bits.vc_sel.`1`[6]
connect arbs_1.io.in[0].bits.vc_sel.`1`[7], io.req.`0`[0].bits.vc_sel.`1`[7]
connect arbs_1.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0]
connect arbs_1.io.in[0].bits.vc_sel.`2`[1], io.req.`0`[0].bits.vc_sel.`2`[1]
connect arbs_1.io.in[0].bits.vc_sel.`2`[2], io.req.`0`[0].bits.vc_sel.`2`[2]
connect arbs_1.io.in[0].bits.vc_sel.`2`[3], io.req.`0`[0].bits.vc_sel.`2`[3]
connect arbs_1.io.in[0].bits.vc_sel.`2`[4], io.req.`0`[0].bits.vc_sel.`2`[4]
connect arbs_1.io.in[0].bits.vc_sel.`2`[5], io.req.`0`[0].bits.vc_sel.`2`[5]
connect arbs_1.io.in[0].bits.vc_sel.`2`[6], io.req.`0`[0].bits.vc_sel.`2`[6]
connect arbs_1.io.in[0].bits.vc_sel.`2`[7], io.req.`0`[0].bits.vc_sel.`2`[7]
node _fires_1_T = and(arbs_1.io.in[0].ready, arbs_1.io.in[0].valid)
connect fires[1], _fires_1_T
node _arbs_2_io_in_0_valid_T = or(io.req.`0`[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[1])
node _arbs_2_io_in_0_valid_T_1 = or(_arbs_2_io_in_0_valid_T, io.req.`0`[0].bits.vc_sel.`2`[2])
node _arbs_2_io_in_0_valid_T_2 = or(_arbs_2_io_in_0_valid_T_1, io.req.`0`[0].bits.vc_sel.`2`[3])
node _arbs_2_io_in_0_valid_T_3 = or(_arbs_2_io_in_0_valid_T_2, io.req.`0`[0].bits.vc_sel.`2`[4])
node _arbs_2_io_in_0_valid_T_4 = or(_arbs_2_io_in_0_valid_T_3, io.req.`0`[0].bits.vc_sel.`2`[5])
node _arbs_2_io_in_0_valid_T_5 = or(_arbs_2_io_in_0_valid_T_4, io.req.`0`[0].bits.vc_sel.`2`[6])
node _arbs_2_io_in_0_valid_T_6 = or(_arbs_2_io_in_0_valid_T_5, io.req.`0`[0].bits.vc_sel.`2`[7])
node _arbs_2_io_in_0_valid_T_7 = and(io.req.`0`[0].valid, _arbs_2_io_in_0_valid_T_6)
connect arbs_2.io.in[0].valid, _arbs_2_io_in_0_valid_T_7
connect arbs_2.io.in[0].bits.tail, io.req.`0`[0].bits.tail
connect arbs_2.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0]
connect arbs_2.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1]
connect arbs_2.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2]
connect arbs_2.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3]
connect arbs_2.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4]
connect arbs_2.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5]
connect arbs_2.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6]
connect arbs_2.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7]
connect arbs_2.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0]
connect arbs_2.io.in[0].bits.vc_sel.`1`[1], io.req.`0`[0].bits.vc_sel.`1`[1]
connect arbs_2.io.in[0].bits.vc_sel.`1`[2], io.req.`0`[0].bits.vc_sel.`1`[2]
connect arbs_2.io.in[0].bits.vc_sel.`1`[3], io.req.`0`[0].bits.vc_sel.`1`[3]
connect arbs_2.io.in[0].bits.vc_sel.`1`[4], io.req.`0`[0].bits.vc_sel.`1`[4]
connect arbs_2.io.in[0].bits.vc_sel.`1`[5], io.req.`0`[0].bits.vc_sel.`1`[5]
connect arbs_2.io.in[0].bits.vc_sel.`1`[6], io.req.`0`[0].bits.vc_sel.`1`[6]
connect arbs_2.io.in[0].bits.vc_sel.`1`[7], io.req.`0`[0].bits.vc_sel.`1`[7]
connect arbs_2.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0]
connect arbs_2.io.in[0].bits.vc_sel.`2`[1], io.req.`0`[0].bits.vc_sel.`2`[1]
connect arbs_2.io.in[0].bits.vc_sel.`2`[2], io.req.`0`[0].bits.vc_sel.`2`[2]
connect arbs_2.io.in[0].bits.vc_sel.`2`[3], io.req.`0`[0].bits.vc_sel.`2`[3]
connect arbs_2.io.in[0].bits.vc_sel.`2`[4], io.req.`0`[0].bits.vc_sel.`2`[4]
connect arbs_2.io.in[0].bits.vc_sel.`2`[5], io.req.`0`[0].bits.vc_sel.`2`[5]
connect arbs_2.io.in[0].bits.vc_sel.`2`[6], io.req.`0`[0].bits.vc_sel.`2`[6]
connect arbs_2.io.in[0].bits.vc_sel.`2`[7], io.req.`0`[0].bits.vc_sel.`2`[7]
node _fires_2_T = and(arbs_2.io.in[0].ready, arbs_2.io.in[0].valid)
connect fires[2], _fires_2_T
node _io_req_0_0_ready_T = or(fires[0], fires[1])
node _io_req_0_0_ready_T_1 = or(_io_req_0_0_ready_T, fires[2])
connect io.req.`0`[0].ready, _io_req_0_0_ready_T_1
wire fires_1 : UInt<1>[3]
node _arbs_0_io_in_1_valid_T = or(io.req.`1`[0].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[1])
node _arbs_0_io_in_1_valid_T_1 = or(_arbs_0_io_in_1_valid_T, io.req.`1`[0].bits.vc_sel.`0`[2])
node _arbs_0_io_in_1_valid_T_2 = or(_arbs_0_io_in_1_valid_T_1, io.req.`1`[0].bits.vc_sel.`0`[3])
node _arbs_0_io_in_1_valid_T_3 = or(_arbs_0_io_in_1_valid_T_2, io.req.`1`[0].bits.vc_sel.`0`[4])
node _arbs_0_io_in_1_valid_T_4 = or(_arbs_0_io_in_1_valid_T_3, io.req.`1`[0].bits.vc_sel.`0`[5])
node _arbs_0_io_in_1_valid_T_5 = or(_arbs_0_io_in_1_valid_T_4, io.req.`1`[0].bits.vc_sel.`0`[6])
node _arbs_0_io_in_1_valid_T_6 = or(_arbs_0_io_in_1_valid_T_5, io.req.`1`[0].bits.vc_sel.`0`[7])
node _arbs_0_io_in_1_valid_T_7 = and(io.req.`1`[0].valid, _arbs_0_io_in_1_valid_T_6)
connect arbs_0.io.in[1].valid, _arbs_0_io_in_1_valid_T_7
connect arbs_0.io.in[1].bits.tail, io.req.`1`[0].bits.tail
connect arbs_0.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0]
connect arbs_0.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1]
connect arbs_0.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2]
connect arbs_0.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3]
connect arbs_0.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4]
connect arbs_0.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5]
connect arbs_0.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6]
connect arbs_0.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7]
connect arbs_0.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0]
connect arbs_0.io.in[1].bits.vc_sel.`1`[1], io.req.`1`[0].bits.vc_sel.`1`[1]
connect arbs_0.io.in[1].bits.vc_sel.`1`[2], io.req.`1`[0].bits.vc_sel.`1`[2]
connect arbs_0.io.in[1].bits.vc_sel.`1`[3], io.req.`1`[0].bits.vc_sel.`1`[3]
connect arbs_0.io.in[1].bits.vc_sel.`1`[4], io.req.`1`[0].bits.vc_sel.`1`[4]
connect arbs_0.io.in[1].bits.vc_sel.`1`[5], io.req.`1`[0].bits.vc_sel.`1`[5]
connect arbs_0.io.in[1].bits.vc_sel.`1`[6], io.req.`1`[0].bits.vc_sel.`1`[6]
connect arbs_0.io.in[1].bits.vc_sel.`1`[7], io.req.`1`[0].bits.vc_sel.`1`[7]
connect arbs_0.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0]
connect arbs_0.io.in[1].bits.vc_sel.`2`[1], io.req.`1`[0].bits.vc_sel.`2`[1]
connect arbs_0.io.in[1].bits.vc_sel.`2`[2], io.req.`1`[0].bits.vc_sel.`2`[2]
connect arbs_0.io.in[1].bits.vc_sel.`2`[3], io.req.`1`[0].bits.vc_sel.`2`[3]
connect arbs_0.io.in[1].bits.vc_sel.`2`[4], io.req.`1`[0].bits.vc_sel.`2`[4]
connect arbs_0.io.in[1].bits.vc_sel.`2`[5], io.req.`1`[0].bits.vc_sel.`2`[5]
connect arbs_0.io.in[1].bits.vc_sel.`2`[6], io.req.`1`[0].bits.vc_sel.`2`[6]
connect arbs_0.io.in[1].bits.vc_sel.`2`[7], io.req.`1`[0].bits.vc_sel.`2`[7]
node _fires_0_T_1 = and(arbs_0.io.in[1].ready, arbs_0.io.in[1].valid)
connect fires_1[0], _fires_0_T_1
node _arbs_1_io_in_1_valid_T = or(io.req.`1`[0].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[1])
node _arbs_1_io_in_1_valid_T_1 = or(_arbs_1_io_in_1_valid_T, io.req.`1`[0].bits.vc_sel.`1`[2])
node _arbs_1_io_in_1_valid_T_2 = or(_arbs_1_io_in_1_valid_T_1, io.req.`1`[0].bits.vc_sel.`1`[3])
node _arbs_1_io_in_1_valid_T_3 = or(_arbs_1_io_in_1_valid_T_2, io.req.`1`[0].bits.vc_sel.`1`[4])
node _arbs_1_io_in_1_valid_T_4 = or(_arbs_1_io_in_1_valid_T_3, io.req.`1`[0].bits.vc_sel.`1`[5])
node _arbs_1_io_in_1_valid_T_5 = or(_arbs_1_io_in_1_valid_T_4, io.req.`1`[0].bits.vc_sel.`1`[6])
node _arbs_1_io_in_1_valid_T_6 = or(_arbs_1_io_in_1_valid_T_5, io.req.`1`[0].bits.vc_sel.`1`[7])
node _arbs_1_io_in_1_valid_T_7 = and(io.req.`1`[0].valid, _arbs_1_io_in_1_valid_T_6)
connect arbs_1.io.in[1].valid, _arbs_1_io_in_1_valid_T_7
connect arbs_1.io.in[1].bits.tail, io.req.`1`[0].bits.tail
connect arbs_1.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0]
connect arbs_1.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1]
connect arbs_1.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2]
connect arbs_1.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3]
connect arbs_1.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4]
connect arbs_1.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5]
connect arbs_1.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6]
connect arbs_1.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7]
connect arbs_1.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0]
connect arbs_1.io.in[1].bits.vc_sel.`1`[1], io.req.`1`[0].bits.vc_sel.`1`[1]
connect arbs_1.io.in[1].bits.vc_sel.`1`[2], io.req.`1`[0].bits.vc_sel.`1`[2]
connect arbs_1.io.in[1].bits.vc_sel.`1`[3], io.req.`1`[0].bits.vc_sel.`1`[3]
connect arbs_1.io.in[1].bits.vc_sel.`1`[4], io.req.`1`[0].bits.vc_sel.`1`[4]
connect arbs_1.io.in[1].bits.vc_sel.`1`[5], io.req.`1`[0].bits.vc_sel.`1`[5]
connect arbs_1.io.in[1].bits.vc_sel.`1`[6], io.req.`1`[0].bits.vc_sel.`1`[6]
connect arbs_1.io.in[1].bits.vc_sel.`1`[7], io.req.`1`[0].bits.vc_sel.`1`[7]
connect arbs_1.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0]
connect arbs_1.io.in[1].bits.vc_sel.`2`[1], io.req.`1`[0].bits.vc_sel.`2`[1]
connect arbs_1.io.in[1].bits.vc_sel.`2`[2], io.req.`1`[0].bits.vc_sel.`2`[2]
connect arbs_1.io.in[1].bits.vc_sel.`2`[3], io.req.`1`[0].bits.vc_sel.`2`[3]
connect arbs_1.io.in[1].bits.vc_sel.`2`[4], io.req.`1`[0].bits.vc_sel.`2`[4]
connect arbs_1.io.in[1].bits.vc_sel.`2`[5], io.req.`1`[0].bits.vc_sel.`2`[5]
connect arbs_1.io.in[1].bits.vc_sel.`2`[6], io.req.`1`[0].bits.vc_sel.`2`[6]
connect arbs_1.io.in[1].bits.vc_sel.`2`[7], io.req.`1`[0].bits.vc_sel.`2`[7]
node _fires_1_T_1 = and(arbs_1.io.in[1].ready, arbs_1.io.in[1].valid)
connect fires_1[1], _fires_1_T_1
node _arbs_2_io_in_1_valid_T = or(io.req.`1`[0].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[1])
node _arbs_2_io_in_1_valid_T_1 = or(_arbs_2_io_in_1_valid_T, io.req.`1`[0].bits.vc_sel.`2`[2])
node _arbs_2_io_in_1_valid_T_2 = or(_arbs_2_io_in_1_valid_T_1, io.req.`1`[0].bits.vc_sel.`2`[3])
node _arbs_2_io_in_1_valid_T_3 = or(_arbs_2_io_in_1_valid_T_2, io.req.`1`[0].bits.vc_sel.`2`[4])
node _arbs_2_io_in_1_valid_T_4 = or(_arbs_2_io_in_1_valid_T_3, io.req.`1`[0].bits.vc_sel.`2`[5])
node _arbs_2_io_in_1_valid_T_5 = or(_arbs_2_io_in_1_valid_T_4, io.req.`1`[0].bits.vc_sel.`2`[6])
node _arbs_2_io_in_1_valid_T_6 = or(_arbs_2_io_in_1_valid_T_5, io.req.`1`[0].bits.vc_sel.`2`[7])
node _arbs_2_io_in_1_valid_T_7 = and(io.req.`1`[0].valid, _arbs_2_io_in_1_valid_T_6)
connect arbs_2.io.in[1].valid, _arbs_2_io_in_1_valid_T_7
connect arbs_2.io.in[1].bits.tail, io.req.`1`[0].bits.tail
connect arbs_2.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0]
connect arbs_2.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1]
connect arbs_2.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2]
connect arbs_2.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3]
connect arbs_2.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4]
connect arbs_2.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5]
connect arbs_2.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6]
connect arbs_2.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7]
connect arbs_2.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0]
connect arbs_2.io.in[1].bits.vc_sel.`1`[1], io.req.`1`[0].bits.vc_sel.`1`[1]
connect arbs_2.io.in[1].bits.vc_sel.`1`[2], io.req.`1`[0].bits.vc_sel.`1`[2]
connect arbs_2.io.in[1].bits.vc_sel.`1`[3], io.req.`1`[0].bits.vc_sel.`1`[3]
connect arbs_2.io.in[1].bits.vc_sel.`1`[4], io.req.`1`[0].bits.vc_sel.`1`[4]
connect arbs_2.io.in[1].bits.vc_sel.`1`[5], io.req.`1`[0].bits.vc_sel.`1`[5]
connect arbs_2.io.in[1].bits.vc_sel.`1`[6], io.req.`1`[0].bits.vc_sel.`1`[6]
connect arbs_2.io.in[1].bits.vc_sel.`1`[7], io.req.`1`[0].bits.vc_sel.`1`[7]
connect arbs_2.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0]
connect arbs_2.io.in[1].bits.vc_sel.`2`[1], io.req.`1`[0].bits.vc_sel.`2`[1]
connect arbs_2.io.in[1].bits.vc_sel.`2`[2], io.req.`1`[0].bits.vc_sel.`2`[2]
connect arbs_2.io.in[1].bits.vc_sel.`2`[3], io.req.`1`[0].bits.vc_sel.`2`[3]
connect arbs_2.io.in[1].bits.vc_sel.`2`[4], io.req.`1`[0].bits.vc_sel.`2`[4]
connect arbs_2.io.in[1].bits.vc_sel.`2`[5], io.req.`1`[0].bits.vc_sel.`2`[5]
connect arbs_2.io.in[1].bits.vc_sel.`2`[6], io.req.`1`[0].bits.vc_sel.`2`[6]
connect arbs_2.io.in[1].bits.vc_sel.`2`[7], io.req.`1`[0].bits.vc_sel.`2`[7]
node _fires_2_T_1 = and(arbs_2.io.in[1].ready, arbs_2.io.in[1].valid)
connect fires_1[2], _fires_2_T_1
node _io_req_1_0_ready_T = or(fires_1[0], fires_1[1])
node _io_req_1_0_ready_T_1 = or(_io_req_1_0_ready_T, fires_1[2])
connect io.req.`1`[0].ready, _io_req_1_0_ready_T_1
wire fires_2 : UInt<1>[3]
node _arbs_0_io_in_2_valid_T = or(io.req.`2`[0].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[1])
node _arbs_0_io_in_2_valid_T_1 = or(_arbs_0_io_in_2_valid_T, io.req.`2`[0].bits.vc_sel.`0`[2])
node _arbs_0_io_in_2_valid_T_2 = or(_arbs_0_io_in_2_valid_T_1, io.req.`2`[0].bits.vc_sel.`0`[3])
node _arbs_0_io_in_2_valid_T_3 = or(_arbs_0_io_in_2_valid_T_2, io.req.`2`[0].bits.vc_sel.`0`[4])
node _arbs_0_io_in_2_valid_T_4 = or(_arbs_0_io_in_2_valid_T_3, io.req.`2`[0].bits.vc_sel.`0`[5])
node _arbs_0_io_in_2_valid_T_5 = or(_arbs_0_io_in_2_valid_T_4, io.req.`2`[0].bits.vc_sel.`0`[6])
node _arbs_0_io_in_2_valid_T_6 = or(_arbs_0_io_in_2_valid_T_5, io.req.`2`[0].bits.vc_sel.`0`[7])
node _arbs_0_io_in_2_valid_T_7 = and(io.req.`2`[0].valid, _arbs_0_io_in_2_valid_T_6)
connect arbs_0.io.in[2].valid, _arbs_0_io_in_2_valid_T_7
connect arbs_0.io.in[2].bits.tail, io.req.`2`[0].bits.tail
connect arbs_0.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0]
connect arbs_0.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1]
connect arbs_0.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2]
connect arbs_0.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3]
connect arbs_0.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4]
connect arbs_0.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5]
connect arbs_0.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6]
connect arbs_0.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7]
connect arbs_0.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0]
connect arbs_0.io.in[2].bits.vc_sel.`1`[1], io.req.`2`[0].bits.vc_sel.`1`[1]
connect arbs_0.io.in[2].bits.vc_sel.`1`[2], io.req.`2`[0].bits.vc_sel.`1`[2]
connect arbs_0.io.in[2].bits.vc_sel.`1`[3], io.req.`2`[0].bits.vc_sel.`1`[3]
connect arbs_0.io.in[2].bits.vc_sel.`1`[4], io.req.`2`[0].bits.vc_sel.`1`[4]
connect arbs_0.io.in[2].bits.vc_sel.`1`[5], io.req.`2`[0].bits.vc_sel.`1`[5]
connect arbs_0.io.in[2].bits.vc_sel.`1`[6], io.req.`2`[0].bits.vc_sel.`1`[6]
connect arbs_0.io.in[2].bits.vc_sel.`1`[7], io.req.`2`[0].bits.vc_sel.`1`[7]
connect arbs_0.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0]
connect arbs_0.io.in[2].bits.vc_sel.`2`[1], io.req.`2`[0].bits.vc_sel.`2`[1]
connect arbs_0.io.in[2].bits.vc_sel.`2`[2], io.req.`2`[0].bits.vc_sel.`2`[2]
connect arbs_0.io.in[2].bits.vc_sel.`2`[3], io.req.`2`[0].bits.vc_sel.`2`[3]
connect arbs_0.io.in[2].bits.vc_sel.`2`[4], io.req.`2`[0].bits.vc_sel.`2`[4]
connect arbs_0.io.in[2].bits.vc_sel.`2`[5], io.req.`2`[0].bits.vc_sel.`2`[5]
connect arbs_0.io.in[2].bits.vc_sel.`2`[6], io.req.`2`[0].bits.vc_sel.`2`[6]
connect arbs_0.io.in[2].bits.vc_sel.`2`[7], io.req.`2`[0].bits.vc_sel.`2`[7]
node _fires_0_T_2 = and(arbs_0.io.in[2].ready, arbs_0.io.in[2].valid)
connect fires_2[0], _fires_0_T_2
node _arbs_1_io_in_2_valid_T = or(io.req.`2`[0].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[1])
node _arbs_1_io_in_2_valid_T_1 = or(_arbs_1_io_in_2_valid_T, io.req.`2`[0].bits.vc_sel.`1`[2])
node _arbs_1_io_in_2_valid_T_2 = or(_arbs_1_io_in_2_valid_T_1, io.req.`2`[0].bits.vc_sel.`1`[3])
node _arbs_1_io_in_2_valid_T_3 = or(_arbs_1_io_in_2_valid_T_2, io.req.`2`[0].bits.vc_sel.`1`[4])
node _arbs_1_io_in_2_valid_T_4 = or(_arbs_1_io_in_2_valid_T_3, io.req.`2`[0].bits.vc_sel.`1`[5])
node _arbs_1_io_in_2_valid_T_5 = or(_arbs_1_io_in_2_valid_T_4, io.req.`2`[0].bits.vc_sel.`1`[6])
node _arbs_1_io_in_2_valid_T_6 = or(_arbs_1_io_in_2_valid_T_5, io.req.`2`[0].bits.vc_sel.`1`[7])
node _arbs_1_io_in_2_valid_T_7 = and(io.req.`2`[0].valid, _arbs_1_io_in_2_valid_T_6)
connect arbs_1.io.in[2].valid, _arbs_1_io_in_2_valid_T_7
connect arbs_1.io.in[2].bits.tail, io.req.`2`[0].bits.tail
connect arbs_1.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0]
connect arbs_1.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1]
connect arbs_1.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2]
connect arbs_1.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3]
connect arbs_1.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4]
connect arbs_1.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5]
connect arbs_1.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6]
connect arbs_1.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7]
connect arbs_1.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0]
connect arbs_1.io.in[2].bits.vc_sel.`1`[1], io.req.`2`[0].bits.vc_sel.`1`[1]
connect arbs_1.io.in[2].bits.vc_sel.`1`[2], io.req.`2`[0].bits.vc_sel.`1`[2]
connect arbs_1.io.in[2].bits.vc_sel.`1`[3], io.req.`2`[0].bits.vc_sel.`1`[3]
connect arbs_1.io.in[2].bits.vc_sel.`1`[4], io.req.`2`[0].bits.vc_sel.`1`[4]
connect arbs_1.io.in[2].bits.vc_sel.`1`[5], io.req.`2`[0].bits.vc_sel.`1`[5]
connect arbs_1.io.in[2].bits.vc_sel.`1`[6], io.req.`2`[0].bits.vc_sel.`1`[6]
connect arbs_1.io.in[2].bits.vc_sel.`1`[7], io.req.`2`[0].bits.vc_sel.`1`[7]
connect arbs_1.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0]
connect arbs_1.io.in[2].bits.vc_sel.`2`[1], io.req.`2`[0].bits.vc_sel.`2`[1]
connect arbs_1.io.in[2].bits.vc_sel.`2`[2], io.req.`2`[0].bits.vc_sel.`2`[2]
connect arbs_1.io.in[2].bits.vc_sel.`2`[3], io.req.`2`[0].bits.vc_sel.`2`[3]
connect arbs_1.io.in[2].bits.vc_sel.`2`[4], io.req.`2`[0].bits.vc_sel.`2`[4]
connect arbs_1.io.in[2].bits.vc_sel.`2`[5], io.req.`2`[0].bits.vc_sel.`2`[5]
connect arbs_1.io.in[2].bits.vc_sel.`2`[6], io.req.`2`[0].bits.vc_sel.`2`[6]
connect arbs_1.io.in[2].bits.vc_sel.`2`[7], io.req.`2`[0].bits.vc_sel.`2`[7]
node _fires_1_T_2 = and(arbs_1.io.in[2].ready, arbs_1.io.in[2].valid)
connect fires_2[1], _fires_1_T_2
node _arbs_2_io_in_2_valid_T = or(io.req.`2`[0].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[1])
node _arbs_2_io_in_2_valid_T_1 = or(_arbs_2_io_in_2_valid_T, io.req.`2`[0].bits.vc_sel.`2`[2])
node _arbs_2_io_in_2_valid_T_2 = or(_arbs_2_io_in_2_valid_T_1, io.req.`2`[0].bits.vc_sel.`2`[3])
node _arbs_2_io_in_2_valid_T_3 = or(_arbs_2_io_in_2_valid_T_2, io.req.`2`[0].bits.vc_sel.`2`[4])
node _arbs_2_io_in_2_valid_T_4 = or(_arbs_2_io_in_2_valid_T_3, io.req.`2`[0].bits.vc_sel.`2`[5])
node _arbs_2_io_in_2_valid_T_5 = or(_arbs_2_io_in_2_valid_T_4, io.req.`2`[0].bits.vc_sel.`2`[6])
node _arbs_2_io_in_2_valid_T_6 = or(_arbs_2_io_in_2_valid_T_5, io.req.`2`[0].bits.vc_sel.`2`[7])
node _arbs_2_io_in_2_valid_T_7 = and(io.req.`2`[0].valid, _arbs_2_io_in_2_valid_T_6)
connect arbs_2.io.in[2].valid, _arbs_2_io_in_2_valid_T_7
connect arbs_2.io.in[2].bits.tail, io.req.`2`[0].bits.tail
connect arbs_2.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0]
connect arbs_2.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1]
connect arbs_2.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2]
connect arbs_2.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3]
connect arbs_2.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4]
connect arbs_2.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5]
connect arbs_2.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6]
connect arbs_2.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7]
connect arbs_2.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0]
connect arbs_2.io.in[2].bits.vc_sel.`1`[1], io.req.`2`[0].bits.vc_sel.`1`[1]
connect arbs_2.io.in[2].bits.vc_sel.`1`[2], io.req.`2`[0].bits.vc_sel.`1`[2]
connect arbs_2.io.in[2].bits.vc_sel.`1`[3], io.req.`2`[0].bits.vc_sel.`1`[3]
connect arbs_2.io.in[2].bits.vc_sel.`1`[4], io.req.`2`[0].bits.vc_sel.`1`[4]
connect arbs_2.io.in[2].bits.vc_sel.`1`[5], io.req.`2`[0].bits.vc_sel.`1`[5]
connect arbs_2.io.in[2].bits.vc_sel.`1`[6], io.req.`2`[0].bits.vc_sel.`1`[6]
connect arbs_2.io.in[2].bits.vc_sel.`1`[7], io.req.`2`[0].bits.vc_sel.`1`[7]
connect arbs_2.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0]
connect arbs_2.io.in[2].bits.vc_sel.`2`[1], io.req.`2`[0].bits.vc_sel.`2`[1]
connect arbs_2.io.in[2].bits.vc_sel.`2`[2], io.req.`2`[0].bits.vc_sel.`2`[2]
connect arbs_2.io.in[2].bits.vc_sel.`2`[3], io.req.`2`[0].bits.vc_sel.`2`[3]
connect arbs_2.io.in[2].bits.vc_sel.`2`[4], io.req.`2`[0].bits.vc_sel.`2`[4]
connect arbs_2.io.in[2].bits.vc_sel.`2`[5], io.req.`2`[0].bits.vc_sel.`2`[5]
connect arbs_2.io.in[2].bits.vc_sel.`2`[6], io.req.`2`[0].bits.vc_sel.`2`[6]
connect arbs_2.io.in[2].bits.vc_sel.`2`[7], io.req.`2`[0].bits.vc_sel.`2`[7]
node _fires_2_T_2 = and(arbs_2.io.in[2].ready, arbs_2.io.in[2].valid)
connect fires_2[2], _fires_2_T_2
node _io_req_2_0_ready_T = or(fires_2[0], fires_2[1])
node _io_req_2_0_ready_T_1 = or(_io_req_2_0_ready_T, fires_2[2])
connect io.req.`2`[0].ready, _io_req_2_0_ready_T_1
node _io_switch_sel_0_0_0_0_T = bits(arbs_0.io.chosen_oh[0], 0, 0)
node _io_switch_sel_0_0_0_0_T_1 = and(arbs_0.io.in[0].valid, _io_switch_sel_0_0_0_0_T)
node _io_switch_sel_0_0_0_0_T_2 = and(_io_switch_sel_0_0_0_0_T_1, arbs_0.io.out[0].valid)
connect io.switch_sel.`0`[0].`0`[0], _io_switch_sel_0_0_0_0_T_2
node _io_switch_sel_0_0_1_0_T = bits(arbs_0.io.chosen_oh[0], 1, 1)
node _io_switch_sel_0_0_1_0_T_1 = and(arbs_0.io.in[1].valid, _io_switch_sel_0_0_1_0_T)
node _io_switch_sel_0_0_1_0_T_2 = and(_io_switch_sel_0_0_1_0_T_1, arbs_0.io.out[0].valid)
connect io.switch_sel.`0`[0].`1`[0], _io_switch_sel_0_0_1_0_T_2
node _io_switch_sel_0_0_2_0_T = bits(arbs_0.io.chosen_oh[0], 2, 2)
node _io_switch_sel_0_0_2_0_T_1 = and(arbs_0.io.in[2].valid, _io_switch_sel_0_0_2_0_T)
node _io_switch_sel_0_0_2_0_T_2 = and(_io_switch_sel_0_0_2_0_T_1, arbs_0.io.out[0].valid)
connect io.switch_sel.`0`[0].`2`[0], _io_switch_sel_0_0_2_0_T_2
node _io_switch_sel_1_0_0_0_T = bits(arbs_1.io.chosen_oh[0], 0, 0)
node _io_switch_sel_1_0_0_0_T_1 = and(arbs_1.io.in[0].valid, _io_switch_sel_1_0_0_0_T)
node _io_switch_sel_1_0_0_0_T_2 = and(_io_switch_sel_1_0_0_0_T_1, arbs_1.io.out[0].valid)
connect io.switch_sel.`1`[0].`0`[0], _io_switch_sel_1_0_0_0_T_2
node _io_switch_sel_1_0_1_0_T = bits(arbs_1.io.chosen_oh[0], 1, 1)
node _io_switch_sel_1_0_1_0_T_1 = and(arbs_1.io.in[1].valid, _io_switch_sel_1_0_1_0_T)
node _io_switch_sel_1_0_1_0_T_2 = and(_io_switch_sel_1_0_1_0_T_1, arbs_1.io.out[0].valid)
connect io.switch_sel.`1`[0].`1`[0], _io_switch_sel_1_0_1_0_T_2
node _io_switch_sel_1_0_2_0_T = bits(arbs_1.io.chosen_oh[0], 2, 2)
node _io_switch_sel_1_0_2_0_T_1 = and(arbs_1.io.in[2].valid, _io_switch_sel_1_0_2_0_T)
node _io_switch_sel_1_0_2_0_T_2 = and(_io_switch_sel_1_0_2_0_T_1, arbs_1.io.out[0].valid)
connect io.switch_sel.`1`[0].`2`[0], _io_switch_sel_1_0_2_0_T_2
node _io_switch_sel_2_0_0_0_T = bits(arbs_2.io.chosen_oh[0], 0, 0)
node _io_switch_sel_2_0_0_0_T_1 = and(arbs_2.io.in[0].valid, _io_switch_sel_2_0_0_0_T)
node _io_switch_sel_2_0_0_0_T_2 = and(_io_switch_sel_2_0_0_0_T_1, arbs_2.io.out[0].valid)
connect io.switch_sel.`2`[0].`0`[0], _io_switch_sel_2_0_0_0_T_2
node _io_switch_sel_2_0_1_0_T = bits(arbs_2.io.chosen_oh[0], 1, 1)
node _io_switch_sel_2_0_1_0_T_1 = and(arbs_2.io.in[1].valid, _io_switch_sel_2_0_1_0_T)
node _io_switch_sel_2_0_1_0_T_2 = and(_io_switch_sel_2_0_1_0_T_1, arbs_2.io.out[0].valid)
connect io.switch_sel.`2`[0].`1`[0], _io_switch_sel_2_0_1_0_T_2
node _io_switch_sel_2_0_2_0_T = bits(arbs_2.io.chosen_oh[0], 2, 2)
node _io_switch_sel_2_0_2_0_T_1 = and(arbs_2.io.in[2].valid, _io_switch_sel_2_0_2_0_T)
node _io_switch_sel_2_0_2_0_T_2 = and(_io_switch_sel_2_0_2_0_T_1, arbs_2.io.out[0].valid)
connect io.switch_sel.`2`[0].`2`[0], _io_switch_sel_2_0_2_0_T_2
connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[3].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[4].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[5].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[6].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[7].alloc, UInt<1>(0h0)
connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h0)
connect io.credit_alloc.`1`[1].alloc, UInt<1>(0h0)
connect io.credit_alloc.`1`[2].alloc, UInt<1>(0h0)
connect io.credit_alloc.`1`[3].alloc, UInt<1>(0h0)
connect io.credit_alloc.`1`[4].alloc, UInt<1>(0h0)
connect io.credit_alloc.`1`[5].alloc, UInt<1>(0h0)
connect io.credit_alloc.`1`[6].alloc, UInt<1>(0h0)
connect io.credit_alloc.`1`[7].alloc, UInt<1>(0h0)
connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h0)
connect io.credit_alloc.`2`[1].alloc, UInt<1>(0h0)
connect io.credit_alloc.`2`[2].alloc, UInt<1>(0h0)
connect io.credit_alloc.`2`[3].alloc, UInt<1>(0h0)
connect io.credit_alloc.`2`[4].alloc, UInt<1>(0h0)
connect io.credit_alloc.`2`[5].alloc, UInt<1>(0h0)
connect io.credit_alloc.`2`[6].alloc, UInt<1>(0h0)
connect io.credit_alloc.`2`[7].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[0].tail, UInt<1>(0h0)
connect io.credit_alloc.`0`[1].tail, UInt<1>(0h0)
connect io.credit_alloc.`0`[2].tail, UInt<1>(0h0)
connect io.credit_alloc.`0`[3].tail, UInt<1>(0h0)
connect io.credit_alloc.`0`[4].tail, UInt<1>(0h0)
connect io.credit_alloc.`0`[5].tail, UInt<1>(0h0)
connect io.credit_alloc.`0`[6].tail, UInt<1>(0h0)
connect io.credit_alloc.`0`[7].tail, UInt<1>(0h0)
connect io.credit_alloc.`1`[0].tail, UInt<1>(0h0)
connect io.credit_alloc.`1`[1].tail, UInt<1>(0h0)
connect io.credit_alloc.`1`[2].tail, UInt<1>(0h0)
connect io.credit_alloc.`1`[3].tail, UInt<1>(0h0)
connect io.credit_alloc.`1`[4].tail, UInt<1>(0h0)
connect io.credit_alloc.`1`[5].tail, UInt<1>(0h0)
connect io.credit_alloc.`1`[6].tail, UInt<1>(0h0)
connect io.credit_alloc.`1`[7].tail, UInt<1>(0h0)
connect io.credit_alloc.`2`[0].tail, UInt<1>(0h0)
connect io.credit_alloc.`2`[1].tail, UInt<1>(0h0)
connect io.credit_alloc.`2`[2].tail, UInt<1>(0h0)
connect io.credit_alloc.`2`[3].tail, UInt<1>(0h0)
connect io.credit_alloc.`2`[4].tail, UInt<1>(0h0)
connect io.credit_alloc.`2`[5].tail, UInt<1>(0h0)
connect io.credit_alloc.`2`[6].tail, UInt<1>(0h0)
connect io.credit_alloc.`2`[7].tail, UInt<1>(0h0)
node _T = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[0])
when _T :
connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[0].tail, arbs_0.io.out[0].bits.tail
node _T_1 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[1])
when _T_1 :
connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[1].tail, arbs_0.io.out[0].bits.tail
node _T_2 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[2])
when _T_2 :
connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[2].tail, arbs_0.io.out[0].bits.tail
node _T_3 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[3])
when _T_3 :
connect io.credit_alloc.`0`[3].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[3].tail, arbs_0.io.out[0].bits.tail
node _T_4 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[4])
when _T_4 :
connect io.credit_alloc.`0`[4].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[4].tail, arbs_0.io.out[0].bits.tail
node _T_5 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[5])
when _T_5 :
connect io.credit_alloc.`0`[5].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[5].tail, arbs_0.io.out[0].bits.tail
node _T_6 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[6])
when _T_6 :
connect io.credit_alloc.`0`[6].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[6].tail, arbs_0.io.out[0].bits.tail
node _T_7 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[7])
when _T_7 :
connect io.credit_alloc.`0`[7].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[7].tail, arbs_0.io.out[0].bits.tail
node _T_8 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[0])
when _T_8 :
connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h1)
connect io.credit_alloc.`1`[0].tail, arbs_1.io.out[0].bits.tail
node _T_9 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[1])
when _T_9 :
connect io.credit_alloc.`1`[1].alloc, UInt<1>(0h1)
connect io.credit_alloc.`1`[1].tail, arbs_1.io.out[0].bits.tail
node _T_10 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[2])
when _T_10 :
connect io.credit_alloc.`1`[2].alloc, UInt<1>(0h1)
connect io.credit_alloc.`1`[2].tail, arbs_1.io.out[0].bits.tail
node _T_11 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[3])
when _T_11 :
connect io.credit_alloc.`1`[3].alloc, UInt<1>(0h1)
connect io.credit_alloc.`1`[3].tail, arbs_1.io.out[0].bits.tail
node _T_12 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[4])
when _T_12 :
connect io.credit_alloc.`1`[4].alloc, UInt<1>(0h1)
connect io.credit_alloc.`1`[4].tail, arbs_1.io.out[0].bits.tail
node _T_13 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[5])
when _T_13 :
connect io.credit_alloc.`1`[5].alloc, UInt<1>(0h1)
connect io.credit_alloc.`1`[5].tail, arbs_1.io.out[0].bits.tail
node _T_14 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[6])
when _T_14 :
connect io.credit_alloc.`1`[6].alloc, UInt<1>(0h1)
connect io.credit_alloc.`1`[6].tail, arbs_1.io.out[0].bits.tail
node _T_15 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[7])
when _T_15 :
connect io.credit_alloc.`1`[7].alloc, UInt<1>(0h1)
connect io.credit_alloc.`1`[7].tail, arbs_1.io.out[0].bits.tail
node _T_16 = and(arbs_2.io.out[0].valid, arbs_2.io.out[0].bits.vc_sel.`2`[0])
when _T_16 :
connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h1)
connect io.credit_alloc.`2`[0].tail, arbs_2.io.out[0].bits.tail
node _T_17 = and(arbs_2.io.out[0].valid, arbs_2.io.out[0].bits.vc_sel.`2`[1])
when _T_17 :
connect io.credit_alloc.`2`[1].alloc, UInt<1>(0h1)
connect io.credit_alloc.`2`[1].tail, arbs_2.io.out[0].bits.tail
node _T_18 = and(arbs_2.io.out[0].valid, arbs_2.io.out[0].bits.vc_sel.`2`[2])
when _T_18 :
connect io.credit_alloc.`2`[2].alloc, UInt<1>(0h1)
connect io.credit_alloc.`2`[2].tail, arbs_2.io.out[0].bits.tail
node _T_19 = and(arbs_2.io.out[0].valid, arbs_2.io.out[0].bits.vc_sel.`2`[3])
when _T_19 :
connect io.credit_alloc.`2`[3].alloc, UInt<1>(0h1)
connect io.credit_alloc.`2`[3].tail, arbs_2.io.out[0].bits.tail
node _T_20 = and(arbs_2.io.out[0].valid, arbs_2.io.out[0].bits.vc_sel.`2`[4])
when _T_20 :
connect io.credit_alloc.`2`[4].alloc, UInt<1>(0h1)
connect io.credit_alloc.`2`[4].tail, arbs_2.io.out[0].bits.tail
node _T_21 = and(arbs_2.io.out[0].valid, arbs_2.io.out[0].bits.vc_sel.`2`[5])
when _T_21 :
connect io.credit_alloc.`2`[5].alloc, UInt<1>(0h1)
connect io.credit_alloc.`2`[5].tail, arbs_2.io.out[0].bits.tail
node _T_22 = and(arbs_2.io.out[0].valid, arbs_2.io.out[0].bits.vc_sel.`2`[6])
when _T_22 :
connect io.credit_alloc.`2`[6].alloc, UInt<1>(0h1)
connect io.credit_alloc.`2`[6].tail, arbs_2.io.out[0].bits.tail
node _T_23 = and(arbs_2.io.out[0].valid, arbs_2.io.out[0].bits.vc_sel.`2`[7])
when _T_23 :
connect io.credit_alloc.`2`[7].alloc, UInt<1>(0h1)
connect io.credit_alloc.`2`[7].tail, arbs_2.io.out[0].bits.tail | module SwitchAllocator_14( // @[SwitchAllocator.scala:64:7]
input clock, // @[SwitchAllocator.scala:64:7]
input reset, // @[SwitchAllocator.scala:64:7]
output io_req_2_0_ready, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_valid, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_2_1, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_2_2, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_2_3, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_2_4, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_2_5, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_2_6, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_2_7, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_1_3, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_1_5, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_1_6, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_1_7, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_tail, // @[SwitchAllocator.scala:74:14]
output io_req_1_0_ready, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_valid, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_2_1, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_2_2, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_2_3, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_2_4, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_2_5, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_2_6, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_2_7, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_1_3, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_1_5, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_1_6, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_1_7, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_tail, // @[SwitchAllocator.scala:74:14]
output io_req_0_0_ready, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_valid, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_2_1, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_2_2, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_2_3, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_2_4, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_2_5, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_2_6, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_2_7, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_1_3, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_1_5, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_1_6, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_1_7, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_tail, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_2_0_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_2_1_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_2_2_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_2_3_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_2_4_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_2_5_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_2_6_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_2_7_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_1_0_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_1_1_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_1_2_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_1_3_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_1_4_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_1_5_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_1_6_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_1_7_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_1_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_2_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_3_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_4_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_5_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_6_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_7_alloc, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_2_0_2_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_2_0_1_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_2_0_0_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_1_0_2_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_1_0_1_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_1_0_0_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_0_0_2_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_0_0_1_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_0_0_0_0 // @[SwitchAllocator.scala:74:14]
);
wire _arbs_2_io_in_0_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_in_1_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_in_2_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_out_0_bits_vc_sel_2_1; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_out_0_bits_vc_sel_2_2; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_out_0_bits_vc_sel_2_3; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_out_0_bits_vc_sel_2_4; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_out_0_bits_vc_sel_2_5; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_out_0_bits_vc_sel_2_6; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_out_0_bits_vc_sel_2_7; // @[SwitchAllocator.scala:83:45]
wire [2:0] _arbs_2_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_in_0_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_in_1_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_in_2_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_out_0_bits_vc_sel_1_1; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_out_0_bits_vc_sel_1_2; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_out_0_bits_vc_sel_1_3; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_out_0_bits_vc_sel_1_4; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_out_0_bits_vc_sel_1_5; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_out_0_bits_vc_sel_1_6; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_out_0_bits_vc_sel_1_7; // @[SwitchAllocator.scala:83:45]
wire [2:0] _arbs_1_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_in_0_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_in_1_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_in_2_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_1; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_2; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_3; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_4; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_5; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_6; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_7; // @[SwitchAllocator.scala:83:45]
wire [2:0] _arbs_0_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45]
wire arbs_0_io_in_0_valid = io_req_0_0_valid & (io_req_0_0_bits_vc_sel_0_1 | io_req_0_0_bits_vc_sel_0_2 | io_req_0_0_bits_vc_sel_0_3 | io_req_0_0_bits_vc_sel_0_4 | io_req_0_0_bits_vc_sel_0_5 | io_req_0_0_bits_vc_sel_0_6 | io_req_0_0_bits_vc_sel_0_7); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_1_io_in_0_valid = io_req_0_0_valid & (io_req_0_0_bits_vc_sel_1_0 | io_req_0_0_bits_vc_sel_1_1 | io_req_0_0_bits_vc_sel_1_2 | io_req_0_0_bits_vc_sel_1_3 | io_req_0_0_bits_vc_sel_1_4 | io_req_0_0_bits_vc_sel_1_5 | io_req_0_0_bits_vc_sel_1_6 | io_req_0_0_bits_vc_sel_1_7); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_2_io_in_0_valid = io_req_0_0_valid & (io_req_0_0_bits_vc_sel_2_0 | io_req_0_0_bits_vc_sel_2_1 | io_req_0_0_bits_vc_sel_2_2 | io_req_0_0_bits_vc_sel_2_3 | io_req_0_0_bits_vc_sel_2_4 | io_req_0_0_bits_vc_sel_2_5 | io_req_0_0_bits_vc_sel_2_6 | io_req_0_0_bits_vc_sel_2_7); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_0_io_in_1_valid = io_req_1_0_valid & (io_req_1_0_bits_vc_sel_0_1 | io_req_1_0_bits_vc_sel_0_2 | io_req_1_0_bits_vc_sel_0_3 | io_req_1_0_bits_vc_sel_0_4 | io_req_1_0_bits_vc_sel_0_5 | io_req_1_0_bits_vc_sel_0_6 | io_req_1_0_bits_vc_sel_0_7); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_1_io_in_1_valid = io_req_1_0_valid & (io_req_1_0_bits_vc_sel_1_0 | io_req_1_0_bits_vc_sel_1_1 | io_req_1_0_bits_vc_sel_1_2 | io_req_1_0_bits_vc_sel_1_3 | io_req_1_0_bits_vc_sel_1_4 | io_req_1_0_bits_vc_sel_1_5 | io_req_1_0_bits_vc_sel_1_6 | io_req_1_0_bits_vc_sel_1_7); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_2_io_in_1_valid = io_req_1_0_valid & (io_req_1_0_bits_vc_sel_2_0 | io_req_1_0_bits_vc_sel_2_1 | io_req_1_0_bits_vc_sel_2_2 | io_req_1_0_bits_vc_sel_2_3 | io_req_1_0_bits_vc_sel_2_4 | io_req_1_0_bits_vc_sel_2_5 | io_req_1_0_bits_vc_sel_2_6 | io_req_1_0_bits_vc_sel_2_7); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_0_io_in_2_valid = io_req_2_0_valid & (io_req_2_0_bits_vc_sel_0_1 | io_req_2_0_bits_vc_sel_0_2 | io_req_2_0_bits_vc_sel_0_3 | io_req_2_0_bits_vc_sel_0_4 | io_req_2_0_bits_vc_sel_0_5 | io_req_2_0_bits_vc_sel_0_6 | io_req_2_0_bits_vc_sel_0_7); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_1_io_in_2_valid = io_req_2_0_valid & (io_req_2_0_bits_vc_sel_1_0 | io_req_2_0_bits_vc_sel_1_1 | io_req_2_0_bits_vc_sel_1_2 | io_req_2_0_bits_vc_sel_1_3 | io_req_2_0_bits_vc_sel_1_4 | io_req_2_0_bits_vc_sel_1_5 | io_req_2_0_bits_vc_sel_1_6 | io_req_2_0_bits_vc_sel_1_7); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_2_io_in_2_valid = io_req_2_0_valid & (io_req_2_0_bits_vc_sel_2_0 | io_req_2_0_bits_vc_sel_2_1 | io_req_2_0_bits_vc_sel_2_2 | io_req_2_0_bits_vc_sel_2_3 | io_req_2_0_bits_vc_sel_2_4 | io_req_2_0_bits_vc_sel_2_5 | io_req_2_0_bits_vc_sel_2_6 | io_req_2_0_bits_vc_sel_2_7); // @[SwitchAllocator.scala:95:{37,65}]
SwitchArbiter_64 arbs_0 ( // @[SwitchAllocator.scala:83:45]
.clock (clock),
.reset (reset),
.io_in_0_ready (_arbs_0_io_in_0_ready),
.io_in_0_valid (arbs_0_io_in_0_valid), // @[SwitchAllocator.scala:95:37]
.io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0),
.io_in_0_bits_vc_sel_2_1 (io_req_0_0_bits_vc_sel_2_1),
.io_in_0_bits_vc_sel_2_2 (io_req_0_0_bits_vc_sel_2_2),
.io_in_0_bits_vc_sel_2_3 (io_req_0_0_bits_vc_sel_2_3),
.io_in_0_bits_vc_sel_2_4 (io_req_0_0_bits_vc_sel_2_4),
.io_in_0_bits_vc_sel_2_5 (io_req_0_0_bits_vc_sel_2_5),
.io_in_0_bits_vc_sel_2_6 (io_req_0_0_bits_vc_sel_2_6),
.io_in_0_bits_vc_sel_2_7 (io_req_0_0_bits_vc_sel_2_7),
.io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0),
.io_in_0_bits_vc_sel_1_1 (io_req_0_0_bits_vc_sel_1_1),
.io_in_0_bits_vc_sel_1_2 (io_req_0_0_bits_vc_sel_1_2),
.io_in_0_bits_vc_sel_1_3 (io_req_0_0_bits_vc_sel_1_3),
.io_in_0_bits_vc_sel_1_4 (io_req_0_0_bits_vc_sel_1_4),
.io_in_0_bits_vc_sel_1_5 (io_req_0_0_bits_vc_sel_1_5),
.io_in_0_bits_vc_sel_1_6 (io_req_0_0_bits_vc_sel_1_6),
.io_in_0_bits_vc_sel_1_7 (io_req_0_0_bits_vc_sel_1_7),
.io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1),
.io_in_0_bits_vc_sel_0_2 (io_req_0_0_bits_vc_sel_0_2),
.io_in_0_bits_vc_sel_0_3 (io_req_0_0_bits_vc_sel_0_3),
.io_in_0_bits_vc_sel_0_4 (io_req_0_0_bits_vc_sel_0_4),
.io_in_0_bits_vc_sel_0_5 (io_req_0_0_bits_vc_sel_0_5),
.io_in_0_bits_vc_sel_0_6 (io_req_0_0_bits_vc_sel_0_6),
.io_in_0_bits_vc_sel_0_7 (io_req_0_0_bits_vc_sel_0_7),
.io_in_0_bits_tail (io_req_0_0_bits_tail),
.io_in_1_ready (_arbs_0_io_in_1_ready),
.io_in_1_valid (arbs_0_io_in_1_valid), // @[SwitchAllocator.scala:95:37]
.io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0),
.io_in_1_bits_vc_sel_2_1 (io_req_1_0_bits_vc_sel_2_1),
.io_in_1_bits_vc_sel_2_2 (io_req_1_0_bits_vc_sel_2_2),
.io_in_1_bits_vc_sel_2_3 (io_req_1_0_bits_vc_sel_2_3),
.io_in_1_bits_vc_sel_2_4 (io_req_1_0_bits_vc_sel_2_4),
.io_in_1_bits_vc_sel_2_5 (io_req_1_0_bits_vc_sel_2_5),
.io_in_1_bits_vc_sel_2_6 (io_req_1_0_bits_vc_sel_2_6),
.io_in_1_bits_vc_sel_2_7 (io_req_1_0_bits_vc_sel_2_7),
.io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0),
.io_in_1_bits_vc_sel_1_1 (io_req_1_0_bits_vc_sel_1_1),
.io_in_1_bits_vc_sel_1_2 (io_req_1_0_bits_vc_sel_1_2),
.io_in_1_bits_vc_sel_1_3 (io_req_1_0_bits_vc_sel_1_3),
.io_in_1_bits_vc_sel_1_4 (io_req_1_0_bits_vc_sel_1_4),
.io_in_1_bits_vc_sel_1_5 (io_req_1_0_bits_vc_sel_1_5),
.io_in_1_bits_vc_sel_1_6 (io_req_1_0_bits_vc_sel_1_6),
.io_in_1_bits_vc_sel_1_7 (io_req_1_0_bits_vc_sel_1_7),
.io_in_1_bits_vc_sel_0_1 (io_req_1_0_bits_vc_sel_0_1),
.io_in_1_bits_vc_sel_0_2 (io_req_1_0_bits_vc_sel_0_2),
.io_in_1_bits_vc_sel_0_3 (io_req_1_0_bits_vc_sel_0_3),
.io_in_1_bits_vc_sel_0_4 (io_req_1_0_bits_vc_sel_0_4),
.io_in_1_bits_vc_sel_0_5 (io_req_1_0_bits_vc_sel_0_5),
.io_in_1_bits_vc_sel_0_6 (io_req_1_0_bits_vc_sel_0_6),
.io_in_1_bits_vc_sel_0_7 (io_req_1_0_bits_vc_sel_0_7),
.io_in_1_bits_tail (io_req_1_0_bits_tail),
.io_in_2_ready (_arbs_0_io_in_2_ready),
.io_in_2_valid (arbs_0_io_in_2_valid), // @[SwitchAllocator.scala:95:37]
.io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0),
.io_in_2_bits_vc_sel_2_1 (io_req_2_0_bits_vc_sel_2_1),
.io_in_2_bits_vc_sel_2_2 (io_req_2_0_bits_vc_sel_2_2),
.io_in_2_bits_vc_sel_2_3 (io_req_2_0_bits_vc_sel_2_3),
.io_in_2_bits_vc_sel_2_4 (io_req_2_0_bits_vc_sel_2_4),
.io_in_2_bits_vc_sel_2_5 (io_req_2_0_bits_vc_sel_2_5),
.io_in_2_bits_vc_sel_2_6 (io_req_2_0_bits_vc_sel_2_6),
.io_in_2_bits_vc_sel_2_7 (io_req_2_0_bits_vc_sel_2_7),
.io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0),
.io_in_2_bits_vc_sel_1_1 (io_req_2_0_bits_vc_sel_1_1),
.io_in_2_bits_vc_sel_1_2 (io_req_2_0_bits_vc_sel_1_2),
.io_in_2_bits_vc_sel_1_3 (io_req_2_0_bits_vc_sel_1_3),
.io_in_2_bits_vc_sel_1_4 (io_req_2_0_bits_vc_sel_1_4),
.io_in_2_bits_vc_sel_1_5 (io_req_2_0_bits_vc_sel_1_5),
.io_in_2_bits_vc_sel_1_6 (io_req_2_0_bits_vc_sel_1_6),
.io_in_2_bits_vc_sel_1_7 (io_req_2_0_bits_vc_sel_1_7),
.io_in_2_bits_vc_sel_0_1 (io_req_2_0_bits_vc_sel_0_1),
.io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2),
.io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3),
.io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4),
.io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5),
.io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6),
.io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7),
.io_in_2_bits_tail (io_req_2_0_bits_tail),
.io_out_0_valid (_arbs_0_io_out_0_valid),
.io_out_0_bits_vc_sel_2_0 (/* unused */),
.io_out_0_bits_vc_sel_2_1 (/* unused */),
.io_out_0_bits_vc_sel_2_2 (/* unused */),
.io_out_0_bits_vc_sel_2_3 (/* unused */),
.io_out_0_bits_vc_sel_2_4 (/* unused */),
.io_out_0_bits_vc_sel_2_5 (/* unused */),
.io_out_0_bits_vc_sel_2_6 (/* unused */),
.io_out_0_bits_vc_sel_2_7 (/* unused */),
.io_out_0_bits_vc_sel_1_0 (/* unused */),
.io_out_0_bits_vc_sel_1_1 (/* unused */),
.io_out_0_bits_vc_sel_1_2 (/* unused */),
.io_out_0_bits_vc_sel_1_3 (/* unused */),
.io_out_0_bits_vc_sel_1_4 (/* unused */),
.io_out_0_bits_vc_sel_1_5 (/* unused */),
.io_out_0_bits_vc_sel_1_6 (/* unused */),
.io_out_0_bits_vc_sel_1_7 (/* unused */),
.io_out_0_bits_vc_sel_0_1 (_arbs_0_io_out_0_bits_vc_sel_0_1),
.io_out_0_bits_vc_sel_0_2 (_arbs_0_io_out_0_bits_vc_sel_0_2),
.io_out_0_bits_vc_sel_0_3 (_arbs_0_io_out_0_bits_vc_sel_0_3),
.io_out_0_bits_vc_sel_0_4 (_arbs_0_io_out_0_bits_vc_sel_0_4),
.io_out_0_bits_vc_sel_0_5 (_arbs_0_io_out_0_bits_vc_sel_0_5),
.io_out_0_bits_vc_sel_0_6 (_arbs_0_io_out_0_bits_vc_sel_0_6),
.io_out_0_bits_vc_sel_0_7 (_arbs_0_io_out_0_bits_vc_sel_0_7),
.io_chosen_oh_0 (_arbs_0_io_chosen_oh_0)
); // @[SwitchAllocator.scala:83:45]
SwitchArbiter_64 arbs_1 ( // @[SwitchAllocator.scala:83:45]
.clock (clock),
.reset (reset),
.io_in_0_ready (_arbs_1_io_in_0_ready),
.io_in_0_valid (arbs_1_io_in_0_valid), // @[SwitchAllocator.scala:95:37]
.io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0),
.io_in_0_bits_vc_sel_2_1 (io_req_0_0_bits_vc_sel_2_1),
.io_in_0_bits_vc_sel_2_2 (io_req_0_0_bits_vc_sel_2_2),
.io_in_0_bits_vc_sel_2_3 (io_req_0_0_bits_vc_sel_2_3),
.io_in_0_bits_vc_sel_2_4 (io_req_0_0_bits_vc_sel_2_4),
.io_in_0_bits_vc_sel_2_5 (io_req_0_0_bits_vc_sel_2_5),
.io_in_0_bits_vc_sel_2_6 (io_req_0_0_bits_vc_sel_2_6),
.io_in_0_bits_vc_sel_2_7 (io_req_0_0_bits_vc_sel_2_7),
.io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0),
.io_in_0_bits_vc_sel_1_1 (io_req_0_0_bits_vc_sel_1_1),
.io_in_0_bits_vc_sel_1_2 (io_req_0_0_bits_vc_sel_1_2),
.io_in_0_bits_vc_sel_1_3 (io_req_0_0_bits_vc_sel_1_3),
.io_in_0_bits_vc_sel_1_4 (io_req_0_0_bits_vc_sel_1_4),
.io_in_0_bits_vc_sel_1_5 (io_req_0_0_bits_vc_sel_1_5),
.io_in_0_bits_vc_sel_1_6 (io_req_0_0_bits_vc_sel_1_6),
.io_in_0_bits_vc_sel_1_7 (io_req_0_0_bits_vc_sel_1_7),
.io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1),
.io_in_0_bits_vc_sel_0_2 (io_req_0_0_bits_vc_sel_0_2),
.io_in_0_bits_vc_sel_0_3 (io_req_0_0_bits_vc_sel_0_3),
.io_in_0_bits_vc_sel_0_4 (io_req_0_0_bits_vc_sel_0_4),
.io_in_0_bits_vc_sel_0_5 (io_req_0_0_bits_vc_sel_0_5),
.io_in_0_bits_vc_sel_0_6 (io_req_0_0_bits_vc_sel_0_6),
.io_in_0_bits_vc_sel_0_7 (io_req_0_0_bits_vc_sel_0_7),
.io_in_0_bits_tail (io_req_0_0_bits_tail),
.io_in_1_ready (_arbs_1_io_in_1_ready),
.io_in_1_valid (arbs_1_io_in_1_valid), // @[SwitchAllocator.scala:95:37]
.io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0),
.io_in_1_bits_vc_sel_2_1 (io_req_1_0_bits_vc_sel_2_1),
.io_in_1_bits_vc_sel_2_2 (io_req_1_0_bits_vc_sel_2_2),
.io_in_1_bits_vc_sel_2_3 (io_req_1_0_bits_vc_sel_2_3),
.io_in_1_bits_vc_sel_2_4 (io_req_1_0_bits_vc_sel_2_4),
.io_in_1_bits_vc_sel_2_5 (io_req_1_0_bits_vc_sel_2_5),
.io_in_1_bits_vc_sel_2_6 (io_req_1_0_bits_vc_sel_2_6),
.io_in_1_bits_vc_sel_2_7 (io_req_1_0_bits_vc_sel_2_7),
.io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0),
.io_in_1_bits_vc_sel_1_1 (io_req_1_0_bits_vc_sel_1_1),
.io_in_1_bits_vc_sel_1_2 (io_req_1_0_bits_vc_sel_1_2),
.io_in_1_bits_vc_sel_1_3 (io_req_1_0_bits_vc_sel_1_3),
.io_in_1_bits_vc_sel_1_4 (io_req_1_0_bits_vc_sel_1_4),
.io_in_1_bits_vc_sel_1_5 (io_req_1_0_bits_vc_sel_1_5),
.io_in_1_bits_vc_sel_1_6 (io_req_1_0_bits_vc_sel_1_6),
.io_in_1_bits_vc_sel_1_7 (io_req_1_0_bits_vc_sel_1_7),
.io_in_1_bits_vc_sel_0_1 (io_req_1_0_bits_vc_sel_0_1),
.io_in_1_bits_vc_sel_0_2 (io_req_1_0_bits_vc_sel_0_2),
.io_in_1_bits_vc_sel_0_3 (io_req_1_0_bits_vc_sel_0_3),
.io_in_1_bits_vc_sel_0_4 (io_req_1_0_bits_vc_sel_0_4),
.io_in_1_bits_vc_sel_0_5 (io_req_1_0_bits_vc_sel_0_5),
.io_in_1_bits_vc_sel_0_6 (io_req_1_0_bits_vc_sel_0_6),
.io_in_1_bits_vc_sel_0_7 (io_req_1_0_bits_vc_sel_0_7),
.io_in_1_bits_tail (io_req_1_0_bits_tail),
.io_in_2_ready (_arbs_1_io_in_2_ready),
.io_in_2_valid (arbs_1_io_in_2_valid), // @[SwitchAllocator.scala:95:37]
.io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0),
.io_in_2_bits_vc_sel_2_1 (io_req_2_0_bits_vc_sel_2_1),
.io_in_2_bits_vc_sel_2_2 (io_req_2_0_bits_vc_sel_2_2),
.io_in_2_bits_vc_sel_2_3 (io_req_2_0_bits_vc_sel_2_3),
.io_in_2_bits_vc_sel_2_4 (io_req_2_0_bits_vc_sel_2_4),
.io_in_2_bits_vc_sel_2_5 (io_req_2_0_bits_vc_sel_2_5),
.io_in_2_bits_vc_sel_2_6 (io_req_2_0_bits_vc_sel_2_6),
.io_in_2_bits_vc_sel_2_7 (io_req_2_0_bits_vc_sel_2_7),
.io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0),
.io_in_2_bits_vc_sel_1_1 (io_req_2_0_bits_vc_sel_1_1),
.io_in_2_bits_vc_sel_1_2 (io_req_2_0_bits_vc_sel_1_2),
.io_in_2_bits_vc_sel_1_3 (io_req_2_0_bits_vc_sel_1_3),
.io_in_2_bits_vc_sel_1_4 (io_req_2_0_bits_vc_sel_1_4),
.io_in_2_bits_vc_sel_1_5 (io_req_2_0_bits_vc_sel_1_5),
.io_in_2_bits_vc_sel_1_6 (io_req_2_0_bits_vc_sel_1_6),
.io_in_2_bits_vc_sel_1_7 (io_req_2_0_bits_vc_sel_1_7),
.io_in_2_bits_vc_sel_0_1 (io_req_2_0_bits_vc_sel_0_1),
.io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2),
.io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3),
.io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4),
.io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5),
.io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6),
.io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7),
.io_in_2_bits_tail (io_req_2_0_bits_tail),
.io_out_0_valid (_arbs_1_io_out_0_valid),
.io_out_0_bits_vc_sel_2_0 (/* unused */),
.io_out_0_bits_vc_sel_2_1 (/* unused */),
.io_out_0_bits_vc_sel_2_2 (/* unused */),
.io_out_0_bits_vc_sel_2_3 (/* unused */),
.io_out_0_bits_vc_sel_2_4 (/* unused */),
.io_out_0_bits_vc_sel_2_5 (/* unused */),
.io_out_0_bits_vc_sel_2_6 (/* unused */),
.io_out_0_bits_vc_sel_2_7 (/* unused */),
.io_out_0_bits_vc_sel_1_0 (_arbs_1_io_out_0_bits_vc_sel_1_0),
.io_out_0_bits_vc_sel_1_1 (_arbs_1_io_out_0_bits_vc_sel_1_1),
.io_out_0_bits_vc_sel_1_2 (_arbs_1_io_out_0_bits_vc_sel_1_2),
.io_out_0_bits_vc_sel_1_3 (_arbs_1_io_out_0_bits_vc_sel_1_3),
.io_out_0_bits_vc_sel_1_4 (_arbs_1_io_out_0_bits_vc_sel_1_4),
.io_out_0_bits_vc_sel_1_5 (_arbs_1_io_out_0_bits_vc_sel_1_5),
.io_out_0_bits_vc_sel_1_6 (_arbs_1_io_out_0_bits_vc_sel_1_6),
.io_out_0_bits_vc_sel_1_7 (_arbs_1_io_out_0_bits_vc_sel_1_7),
.io_out_0_bits_vc_sel_0_1 (/* unused */),
.io_out_0_bits_vc_sel_0_2 (/* unused */),
.io_out_0_bits_vc_sel_0_3 (/* unused */),
.io_out_0_bits_vc_sel_0_4 (/* unused */),
.io_out_0_bits_vc_sel_0_5 (/* unused */),
.io_out_0_bits_vc_sel_0_6 (/* unused */),
.io_out_0_bits_vc_sel_0_7 (/* unused */),
.io_chosen_oh_0 (_arbs_1_io_chosen_oh_0)
); // @[SwitchAllocator.scala:83:45]
SwitchArbiter_64 arbs_2 ( // @[SwitchAllocator.scala:83:45]
.clock (clock),
.reset (reset),
.io_in_0_ready (_arbs_2_io_in_0_ready),
.io_in_0_valid (arbs_2_io_in_0_valid), // @[SwitchAllocator.scala:95:37]
.io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0),
.io_in_0_bits_vc_sel_2_1 (io_req_0_0_bits_vc_sel_2_1),
.io_in_0_bits_vc_sel_2_2 (io_req_0_0_bits_vc_sel_2_2),
.io_in_0_bits_vc_sel_2_3 (io_req_0_0_bits_vc_sel_2_3),
.io_in_0_bits_vc_sel_2_4 (io_req_0_0_bits_vc_sel_2_4),
.io_in_0_bits_vc_sel_2_5 (io_req_0_0_bits_vc_sel_2_5),
.io_in_0_bits_vc_sel_2_6 (io_req_0_0_bits_vc_sel_2_6),
.io_in_0_bits_vc_sel_2_7 (io_req_0_0_bits_vc_sel_2_7),
.io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0),
.io_in_0_bits_vc_sel_1_1 (io_req_0_0_bits_vc_sel_1_1),
.io_in_0_bits_vc_sel_1_2 (io_req_0_0_bits_vc_sel_1_2),
.io_in_0_bits_vc_sel_1_3 (io_req_0_0_bits_vc_sel_1_3),
.io_in_0_bits_vc_sel_1_4 (io_req_0_0_bits_vc_sel_1_4),
.io_in_0_bits_vc_sel_1_5 (io_req_0_0_bits_vc_sel_1_5),
.io_in_0_bits_vc_sel_1_6 (io_req_0_0_bits_vc_sel_1_6),
.io_in_0_bits_vc_sel_1_7 (io_req_0_0_bits_vc_sel_1_7),
.io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1),
.io_in_0_bits_vc_sel_0_2 (io_req_0_0_bits_vc_sel_0_2),
.io_in_0_bits_vc_sel_0_3 (io_req_0_0_bits_vc_sel_0_3),
.io_in_0_bits_vc_sel_0_4 (io_req_0_0_bits_vc_sel_0_4),
.io_in_0_bits_vc_sel_0_5 (io_req_0_0_bits_vc_sel_0_5),
.io_in_0_bits_vc_sel_0_6 (io_req_0_0_bits_vc_sel_0_6),
.io_in_0_bits_vc_sel_0_7 (io_req_0_0_bits_vc_sel_0_7),
.io_in_0_bits_tail (io_req_0_0_bits_tail),
.io_in_1_ready (_arbs_2_io_in_1_ready),
.io_in_1_valid (arbs_2_io_in_1_valid), // @[SwitchAllocator.scala:95:37]
.io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0),
.io_in_1_bits_vc_sel_2_1 (io_req_1_0_bits_vc_sel_2_1),
.io_in_1_bits_vc_sel_2_2 (io_req_1_0_bits_vc_sel_2_2),
.io_in_1_bits_vc_sel_2_3 (io_req_1_0_bits_vc_sel_2_3),
.io_in_1_bits_vc_sel_2_4 (io_req_1_0_bits_vc_sel_2_4),
.io_in_1_bits_vc_sel_2_5 (io_req_1_0_bits_vc_sel_2_5),
.io_in_1_bits_vc_sel_2_6 (io_req_1_0_bits_vc_sel_2_6),
.io_in_1_bits_vc_sel_2_7 (io_req_1_0_bits_vc_sel_2_7),
.io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0),
.io_in_1_bits_vc_sel_1_1 (io_req_1_0_bits_vc_sel_1_1),
.io_in_1_bits_vc_sel_1_2 (io_req_1_0_bits_vc_sel_1_2),
.io_in_1_bits_vc_sel_1_3 (io_req_1_0_bits_vc_sel_1_3),
.io_in_1_bits_vc_sel_1_4 (io_req_1_0_bits_vc_sel_1_4),
.io_in_1_bits_vc_sel_1_5 (io_req_1_0_bits_vc_sel_1_5),
.io_in_1_bits_vc_sel_1_6 (io_req_1_0_bits_vc_sel_1_6),
.io_in_1_bits_vc_sel_1_7 (io_req_1_0_bits_vc_sel_1_7),
.io_in_1_bits_vc_sel_0_1 (io_req_1_0_bits_vc_sel_0_1),
.io_in_1_bits_vc_sel_0_2 (io_req_1_0_bits_vc_sel_0_2),
.io_in_1_bits_vc_sel_0_3 (io_req_1_0_bits_vc_sel_0_3),
.io_in_1_bits_vc_sel_0_4 (io_req_1_0_bits_vc_sel_0_4),
.io_in_1_bits_vc_sel_0_5 (io_req_1_0_bits_vc_sel_0_5),
.io_in_1_bits_vc_sel_0_6 (io_req_1_0_bits_vc_sel_0_6),
.io_in_1_bits_vc_sel_0_7 (io_req_1_0_bits_vc_sel_0_7),
.io_in_1_bits_tail (io_req_1_0_bits_tail),
.io_in_2_ready (_arbs_2_io_in_2_ready),
.io_in_2_valid (arbs_2_io_in_2_valid), // @[SwitchAllocator.scala:95:37]
.io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0),
.io_in_2_bits_vc_sel_2_1 (io_req_2_0_bits_vc_sel_2_1),
.io_in_2_bits_vc_sel_2_2 (io_req_2_0_bits_vc_sel_2_2),
.io_in_2_bits_vc_sel_2_3 (io_req_2_0_bits_vc_sel_2_3),
.io_in_2_bits_vc_sel_2_4 (io_req_2_0_bits_vc_sel_2_4),
.io_in_2_bits_vc_sel_2_5 (io_req_2_0_bits_vc_sel_2_5),
.io_in_2_bits_vc_sel_2_6 (io_req_2_0_bits_vc_sel_2_6),
.io_in_2_bits_vc_sel_2_7 (io_req_2_0_bits_vc_sel_2_7),
.io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0),
.io_in_2_bits_vc_sel_1_1 (io_req_2_0_bits_vc_sel_1_1),
.io_in_2_bits_vc_sel_1_2 (io_req_2_0_bits_vc_sel_1_2),
.io_in_2_bits_vc_sel_1_3 (io_req_2_0_bits_vc_sel_1_3),
.io_in_2_bits_vc_sel_1_4 (io_req_2_0_bits_vc_sel_1_4),
.io_in_2_bits_vc_sel_1_5 (io_req_2_0_bits_vc_sel_1_5),
.io_in_2_bits_vc_sel_1_6 (io_req_2_0_bits_vc_sel_1_6),
.io_in_2_bits_vc_sel_1_7 (io_req_2_0_bits_vc_sel_1_7),
.io_in_2_bits_vc_sel_0_1 (io_req_2_0_bits_vc_sel_0_1),
.io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2),
.io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3),
.io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4),
.io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5),
.io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6),
.io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7),
.io_in_2_bits_tail (io_req_2_0_bits_tail),
.io_out_0_valid (_arbs_2_io_out_0_valid),
.io_out_0_bits_vc_sel_2_0 (_arbs_2_io_out_0_bits_vc_sel_2_0),
.io_out_0_bits_vc_sel_2_1 (_arbs_2_io_out_0_bits_vc_sel_2_1),
.io_out_0_bits_vc_sel_2_2 (_arbs_2_io_out_0_bits_vc_sel_2_2),
.io_out_0_bits_vc_sel_2_3 (_arbs_2_io_out_0_bits_vc_sel_2_3),
.io_out_0_bits_vc_sel_2_4 (_arbs_2_io_out_0_bits_vc_sel_2_4),
.io_out_0_bits_vc_sel_2_5 (_arbs_2_io_out_0_bits_vc_sel_2_5),
.io_out_0_bits_vc_sel_2_6 (_arbs_2_io_out_0_bits_vc_sel_2_6),
.io_out_0_bits_vc_sel_2_7 (_arbs_2_io_out_0_bits_vc_sel_2_7),
.io_out_0_bits_vc_sel_1_0 (/* unused */),
.io_out_0_bits_vc_sel_1_1 (/* unused */),
.io_out_0_bits_vc_sel_1_2 (/* unused */),
.io_out_0_bits_vc_sel_1_3 (/* unused */),
.io_out_0_bits_vc_sel_1_4 (/* unused */),
.io_out_0_bits_vc_sel_1_5 (/* unused */),
.io_out_0_bits_vc_sel_1_6 (/* unused */),
.io_out_0_bits_vc_sel_1_7 (/* unused */),
.io_out_0_bits_vc_sel_0_1 (/* unused */),
.io_out_0_bits_vc_sel_0_2 (/* unused */),
.io_out_0_bits_vc_sel_0_3 (/* unused */),
.io_out_0_bits_vc_sel_0_4 (/* unused */),
.io_out_0_bits_vc_sel_0_5 (/* unused */),
.io_out_0_bits_vc_sel_0_6 (/* unused */),
.io_out_0_bits_vc_sel_0_7 (/* unused */),
.io_chosen_oh_0 (_arbs_2_io_chosen_oh_0)
); // @[SwitchAllocator.scala:83:45]
assign io_req_2_0_ready = _arbs_0_io_in_2_ready & arbs_0_io_in_2_valid | _arbs_1_io_in_2_ready & arbs_1_io_in_2_valid | _arbs_2_io_in_2_ready & arbs_2_io_in_2_valid; // @[Decoupled.scala:51:35]
assign io_req_1_0_ready = _arbs_0_io_in_1_ready & arbs_0_io_in_1_valid | _arbs_1_io_in_1_ready & arbs_1_io_in_1_valid | _arbs_2_io_in_1_ready & arbs_2_io_in_1_valid; // @[Decoupled.scala:51:35]
assign io_req_0_0_ready = _arbs_0_io_in_0_ready & arbs_0_io_in_0_valid | _arbs_1_io_in_0_ready & arbs_1_io_in_0_valid | _arbs_2_io_in_0_ready & arbs_2_io_in_0_valid; // @[Decoupled.scala:51:35]
assign io_credit_alloc_2_0_alloc = _arbs_2_io_out_0_valid & _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_2_1_alloc = _arbs_2_io_out_0_valid & _arbs_2_io_out_0_bits_vc_sel_2_1; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_2_2_alloc = _arbs_2_io_out_0_valid & _arbs_2_io_out_0_bits_vc_sel_2_2; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_2_3_alloc = _arbs_2_io_out_0_valid & _arbs_2_io_out_0_bits_vc_sel_2_3; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_2_4_alloc = _arbs_2_io_out_0_valid & _arbs_2_io_out_0_bits_vc_sel_2_4; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_2_5_alloc = _arbs_2_io_out_0_valid & _arbs_2_io_out_0_bits_vc_sel_2_5; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_2_6_alloc = _arbs_2_io_out_0_valid & _arbs_2_io_out_0_bits_vc_sel_2_6; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_2_7_alloc = _arbs_2_io_out_0_valid & _arbs_2_io_out_0_bits_vc_sel_2_7; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_1_0_alloc = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_1_1_alloc = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_1; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_1_2_alloc = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_2; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_1_3_alloc = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_3; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_1_4_alloc = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_4; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_1_5_alloc = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_5; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_1_6_alloc = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_6; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_1_7_alloc = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_7; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_1_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_1; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_2_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_2; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_3_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_3; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_4_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_4; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_5_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_5; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_6_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_6; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_7_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_7; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_switch_sel_2_0_2_0 = arbs_2_io_in_2_valid & _arbs_2_io_chosen_oh_0[2] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_2_0_1_0 = arbs_2_io_in_1_valid & _arbs_2_io_chosen_oh_0[1] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_2_0_0_0 = arbs_2_io_in_0_valid & _arbs_2_io_chosen_oh_0[0] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_1_0_2_0 = arbs_1_io_in_2_valid & _arbs_1_io_chosen_oh_0[2] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_1_0_1_0 = arbs_1_io_in_1_valid & _arbs_1_io_chosen_oh_0[1] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_1_0_0_0 = arbs_1_io_in_0_valid & _arbs_1_io_chosen_oh_0[0] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_0_0_2_0 = arbs_0_io_in_2_valid & _arbs_0_io_chosen_oh_0[2] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_0_0_1_0 = arbs_0_io_in_1_valid & _arbs_0_io_chosen_oh_0[1] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_0_0_0_0 = arbs_0_io_in_0_valid & _arbs_0_io_chosen_oh_0[0] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_47 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0)
node _source_ok_T = shr(io.in.a.bits.source, 4)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits = bits(_uncommonBits_T, 3, 0)
node _T_4 = shr(io.in.a.bits.source, 4)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<4>(0h9))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0)
node _T_24 = shr(io.in.a.bits.source, 4)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<4>(0h9))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<29>(0h10000000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<29>(0h10000000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0)
node _T_86 = shr(io.in.a.bits.source, 4)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<4>(0h9))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<29>(0h10000000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<29>(0h10000000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0)
node _T_152 = shr(io.in.a.bits.source, 4)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<4>(0h9))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<29>(0h10000000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_199 = shr(io.in.a.bits.source, 4)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<4>(0h9))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<29>(0h10000000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_240 = shr(io.in.a.bits.source, 4)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<4>(0h9))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<29>(0h10000000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0)
node _T_283 = shr(io.in.a.bits.source, 4)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<4>(0h9))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<29>(0h10000000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0)
node _T_321 = shr(io.in.a.bits.source, 4)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<4>(0h9))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<29>(0h10000000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0)
node _T_359 = shr(io.in.a.bits.source, 4)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<4>(0h9))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<29>(0h10000000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 4)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h1), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h1), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h1), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h1), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h1), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<10>
connect a_set, UInt<10>(0h0)
wire a_set_wo_ready : UInt<10>
connect a_set_wo_ready, UInt<10>(0h0)
wire a_opcodes_set : UInt<40>
connect a_opcodes_set, UInt<40>(0h0)
wire a_sizes_set : UInt<40>
connect a_sizes_set, UInt<40>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<10>
connect d_clr, UInt<10>(0h0)
wire d_clr_wo_ready : UInt<10>
connect d_clr_wo_ready, UInt<10>(0h0)
wire d_opcodes_clr : UInt<40>
connect d_opcodes_clr, UInt<40>(0h0)
wire d_sizes_clr : UInt<40>
connect d_sizes_clr, UInt<40>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_94
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<10>
connect c_set, UInt<10>(0h0)
wire c_set_wo_ready : UInt<10>
connect c_set_wo_ready, UInt<10>(0h0)
wire c_opcodes_set : UInt<40>
connect c_opcodes_set, UInt<40>(0h0)
wire c_sizes_set : UInt<40>
connect c_sizes_set, UInt<40>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<10>
connect d_clr_1, UInt<10>(0h0)
wire d_clr_wo_ready_1 : UInt<10>
connect d_clr_wo_ready_1, UInt<10>(0h0)
wire d_opcodes_clr_1 : UInt<40>
connect d_opcodes_clr_1, UInt<40>(0h0)
wire d_sizes_clr_1 : UInt<40>
connect d_sizes_clr_1, UInt<40>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_95
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_96 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_97 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_47( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54]
wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52]
wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79]
wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35]
wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34]
wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34]
wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34]
wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_672; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg denied; // @[Monitor.scala:543:22]
reg [9:0] inflight; // @[Monitor.scala:614:27]
reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [9:0] a_set; // @[Monitor.scala:626:34]
wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [39:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [9:0] d_clr; // @[Monitor.scala:664:34]
wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [9:0] inflight_1; // @[Monitor.scala:726:35]
wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [9:0] d_clr_1; // @[Monitor.scala:774:34]
wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113]
wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_87 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_87( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_73 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_73( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_cbus_to_bootrom :
input clock : Clock
input reset : Reset
output auto : { fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
inst fragmenter of TLFragmenter_BootROM
connect fragmenter.clock, clock
connect fragmenter.reset, reset
wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlOut.d.bits.corrupt
invalidate tlOut.d.bits.data
invalidate tlOut.d.bits.denied
invalidate tlOut.d.bits.sink
invalidate tlOut.d.bits.source
invalidate tlOut.d.bits.size
invalidate tlOut.d.bits.param
invalidate tlOut.d.bits.opcode
invalidate tlOut.d.valid
invalidate tlOut.d.ready
invalidate tlOut.a.bits.corrupt
invalidate tlOut.a.bits.data
invalidate tlOut.a.bits.mask
invalidate tlOut.a.bits.address
invalidate tlOut.a.bits.source
invalidate tlOut.a.bits.size
invalidate tlOut.a.bits.param
invalidate tlOut.a.bits.opcode
invalidate tlOut.a.valid
invalidate tlOut.a.ready
wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlIn.d.bits.corrupt
invalidate tlIn.d.bits.data
invalidate tlIn.d.bits.denied
invalidate tlIn.d.bits.sink
invalidate tlIn.d.bits.source
invalidate tlIn.d.bits.size
invalidate tlIn.d.bits.param
invalidate tlIn.d.bits.opcode
invalidate tlIn.d.valid
invalidate tlIn.d.ready
invalidate tlIn.a.bits.corrupt
invalidate tlIn.a.bits.data
invalidate tlIn.a.bits.mask
invalidate tlIn.a.bits.address
invalidate tlIn.a.bits.source
invalidate tlIn.a.bits.size
invalidate tlIn.a.bits.param
invalidate tlIn.a.bits.opcode
invalidate tlIn.a.valid
invalidate tlIn.a.ready
connect tlOut, tlIn
connect fragmenter.auto.anon_in, tlOut
connect tlIn, auto.tl_in
connect fragmenter.auto.anon_out.d, auto.fragmenter_anon_out.d
connect auto.fragmenter_anon_out.a.bits, fragmenter.auto.anon_out.a.bits
connect auto.fragmenter_anon_out.a.valid, fragmenter.auto.anon_out.a.valid
connect fragmenter.auto.anon_out.a.ready, auto.fragmenter_anon_out.a.ready | module TLInterconnectCoupler_cbus_to_bootrom( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [16:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [16:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire tlOut_d_valid; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_d_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_d_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_size; // @[MixedNode.scala:542:17]
wire tlOut_a_ready; // @[MixedNode.scala:542:17]
wire auto_fragmenter_anon_out_a_ready_0 = auto_fragmenter_anon_out_a_ready; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_d_valid_0 = auto_fragmenter_anon_out_d_valid; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_fragmenter_anon_out_d_bits_size_0 = auto_fragmenter_anon_out_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [11:0] auto_fragmenter_anon_out_d_bits_source_0 = auto_fragmenter_anon_out_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_fragmenter_anon_out_d_bits_data_0 = auto_fragmenter_anon_out_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [16:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_fragmenter_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_tl_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_tl_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_tl_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire tlOut_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire tlOut_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire tlOut_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire tlIn_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire tlIn_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire tlIn_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire [1:0] auto_fragmenter_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire [1:0] tlOut_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire [1:0] tlIn_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire [2:0] auto_fragmenter_anon_out_d_bits_opcode = 3'h1; // @[Fragmenter.scala:345:34]
wire [2:0] auto_tl_in_d_bits_opcode = 3'h1; // @[Fragmenter.scala:345:34]
wire [2:0] tlOut_d_bits_opcode = 3'h1; // @[Fragmenter.scala:345:34]
wire [2:0] tlIn_d_bits_opcode = 3'h1; // @[Fragmenter.scala:345:34]
wire tlIn_a_ready; // @[MixedNode.scala:551:17]
wire tlIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17]
wire [16:0] tlIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17]
wire [63:0] tlIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17]
wire tlIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17]
wire tlIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17]
wire tlIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] tlIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [2:0] auto_fragmenter_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_fragmenter_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_fragmenter_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [11:0] auto_fragmenter_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [16:0] auto_fragmenter_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_fragmenter_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_fragmenter_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [16:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlOut_a_valid; // @[MixedNode.scala:542:17]
wire tlOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_tl_in_a_ready_0 = tlIn_a_ready; // @[MixedNode.scala:551:17]
assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_tl_in_d_valid_0 = tlIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_size_0 = tlIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_source_0 = tlIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_data_0 = tlIn_d_bits_data; // @[MixedNode.scala:551:17]
TLFragmenter_BootROM fragmenter ( // @[Fragmenter.scala:345:34]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (tlOut_a_ready),
.auto_anon_in_a_valid (tlOut_a_valid), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_opcode (tlOut_a_bits_opcode), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_param (tlOut_a_bits_param), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_size (tlOut_a_bits_size), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_source (tlOut_a_bits_source), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_address (tlOut_a_bits_address), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_mask (tlOut_a_bits_mask), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_data (tlOut_a_bits_data), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_corrupt (tlOut_a_bits_corrupt), // @[MixedNode.scala:542:17]
.auto_anon_in_d_ready (tlOut_d_ready), // @[MixedNode.scala:542:17]
.auto_anon_in_d_valid (tlOut_d_valid),
.auto_anon_in_d_bits_size (tlOut_d_bits_size),
.auto_anon_in_d_bits_source (tlOut_d_bits_source),
.auto_anon_in_d_bits_data (tlOut_d_bits_data),
.auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid_0),
.auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode_0),
.auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param_0),
.auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size_0),
.auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source_0),
.auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address_0),
.auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask_0),
.auto_anon_out_a_bits_data (auto_fragmenter_anon_out_a_bits_data_0),
.auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt_0),
.auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready_0),
.auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data_0) // @[LazyModuleImp.scala:138:7]
); // @[Fragmenter.scala:345:34]
assign auto_fragmenter_anon_out_a_valid = auto_fragmenter_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_opcode = auto_fragmenter_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_param = auto_fragmenter_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_size = auto_fragmenter_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_source = auto_fragmenter_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_address = auto_fragmenter_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_mask = auto_fragmenter_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_data = auto_fragmenter_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_corrupt = auto_fragmenter_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_d_ready = auto_fragmenter_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_data = auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ReverseMemLoader_1 :
input clock : Clock
input reset : Reset
output io : { l2helperUser : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, flip src_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { ip : UInt<64>, isize : UInt<64>}}, consumer : { flip user_consumed_bytes : UInt<6>, available_output_bytes : UInt<6>, output_valid : UInt<1>, flip output_ready : UInt<1>, output_data : UInt<256>, output_last_chunk : UInt<1>}}
inst buf_info_queue of Queue32_BufInfoBundle_1
connect buf_info_queue.clock, clock
connect buf_info_queue.reset, reset
inst load_info_queue of Queue256_LoadInfoBundle_6
connect load_info_queue.clock, clock
connect load_info_queue.reset, reset
node base_addr_start_index = and(io.src_info.bits.ip, UInt<5>(0h1f))
node _aligned_loadlen_T = add(io.src_info.bits.isize, base_addr_start_index)
node aligned_loadlen = tail(_aligned_loadlen_T, 1)
node _base_addr_end_index_T = add(io.src_info.bits.isize, base_addr_start_index)
node _base_addr_end_index_T_1 = tail(_base_addr_end_index_T, 1)
node base_addr_end_index = and(_base_addr_end_index_T_1, UInt<5>(0h1f))
node _base_addr_end_index_inclusive_T = add(io.src_info.bits.isize, base_addr_start_index)
node _base_addr_end_index_inclusive_T_1 = tail(_base_addr_end_index_inclusive_T, 1)
node _base_addr_end_index_inclusive_T_2 = sub(_base_addr_end_index_inclusive_T_1, UInt<1>(0h1))
node _base_addr_end_index_inclusive_T_3 = tail(_base_addr_end_index_inclusive_T_2, 1)
node base_addr_end_index_inclusive = and(_base_addr_end_index_inclusive_T_3, UInt<5>(0h1f))
node _extra_word_T = and(aligned_loadlen, UInt<5>(0h1f))
node extra_word = neq(_extra_word_T, UInt<1>(0h0))
node _base_addr_bytes_aligned_T = dshr(io.src_info.bits.ip, UInt<3>(0h5))
node base_addr_bytes_aligned = dshl(_base_addr_bytes_aligned_T, UInt<3>(0h5))
node _words_to_load_T = dshr(aligned_loadlen, UInt<3>(0h5))
node _words_to_load_T_1 = add(_words_to_load_T, extra_word)
node words_to_load = tail(_words_to_load_T_1, 1)
node _words_to_load_minus_one_T = sub(words_to_load, UInt<1>(0h1))
node words_to_load_minus_one = tail(_words_to_load_minus_one_T, 1)
node _end_addr_bytes_aligned_T = add(io.src_info.bits.ip, io.src_info.bits.isize)
node _end_addr_bytes_aligned_T_1 = tail(_end_addr_bytes_aligned_T, 1)
node _end_addr_bytes_aligned_T_2 = sub(_end_addr_bytes_aligned_T_1, UInt<1>(0h1))
node _end_addr_bytes_aligned_T_3 = tail(_end_addr_bytes_aligned_T_2, 1)
node _end_addr_bytes_aligned_T_4 = dshr(_end_addr_bytes_aligned_T_3, UInt<3>(0h5))
node end_addr_bytes_aligned = dshl(_end_addr_bytes_aligned_T_4, UInt<3>(0h5))
regreset print_not_done : UInt<1>, clock, reset, UInt<1>(0h1)
node _T = and(io.src_info.valid, print_not_done)
when _T :
regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1))
node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1)
connect loginfo_cycles, _loginfo_cycles_T_1
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "seq-revmemloader base_addr_bytes: %x\n", io.src_info.bits.ip) : printf_1
regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1))
node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1)
connect loginfo_cycles_1, _loginfo_cycles_T_3
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "seq-revmemloader base_len: %x\n", io.src_info.bits.isize) : printf_3
regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1))
node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1)
connect loginfo_cycles_2, _loginfo_cycles_T_5
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4
node _T_11 = asUInt(reset)
node _T_12 = eq(_T_11, UInt<1>(0h0))
when _T_12 :
printf(clock, UInt<1>(0h1), "seq-revmemloader base_addr_start_index: %x\n", base_addr_start_index) : printf_5
regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1))
node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1)
connect loginfo_cycles_3, _loginfo_cycles_T_7
node _T_13 = asUInt(reset)
node _T_14 = eq(_T_13, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_6
node _T_15 = asUInt(reset)
node _T_16 = eq(_T_15, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "seq-revmemloader aligned_loadlen: %x\n", aligned_loadlen) : printf_7
regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1))
node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1)
connect loginfo_cycles_4, _loginfo_cycles_T_9
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_8
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "seq-revmemloader base_addr_end_index: %x\n", base_addr_end_index) : printf_9
regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1))
node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1)
connect loginfo_cycles_5, _loginfo_cycles_T_11
node _T_21 = asUInt(reset)
node _T_22 = eq(_T_21, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_10
node _T_23 = asUInt(reset)
node _T_24 = eq(_T_23, UInt<1>(0h0))
when _T_24 :
printf(clock, UInt<1>(0h1), "seq-revmemloader base_addr_end_index_inclusive: %x\n", base_addr_end_index_inclusive) : printf_11
regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1))
node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1)
connect loginfo_cycles_6, _loginfo_cycles_T_13
node _T_25 = asUInt(reset)
node _T_26 = eq(_T_25, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_12
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
printf(clock, UInt<1>(0h1), "seq-revmemloader base_addr_bytes: %x\n", io.src_info.bits.ip) : printf_13
regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1))
node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1)
connect loginfo_cycles_7, _loginfo_cycles_T_15
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_14
node _T_31 = asUInt(reset)
node _T_32 = eq(_T_31, UInt<1>(0h0))
when _T_32 :
printf(clock, UInt<1>(0h1), "seq-revmemloader extra_word: %x\n", extra_word) : printf_15
regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1))
node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1)
connect loginfo_cycles_8, _loginfo_cycles_T_17
node _T_33 = asUInt(reset)
node _T_34 = eq(_T_33, UInt<1>(0h0))
when _T_34 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_16
node _T_35 = asUInt(reset)
node _T_36 = eq(_T_35, UInt<1>(0h0))
when _T_36 :
printf(clock, UInt<1>(0h1), "seq-revmemloader base_addr_bytes_aligned: %x\n", base_addr_bytes_aligned) : printf_17
regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1))
node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1)
connect loginfo_cycles_9, _loginfo_cycles_T_19
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_18
node _T_39 = asUInt(reset)
node _T_40 = eq(_T_39, UInt<1>(0h0))
when _T_40 :
printf(clock, UInt<1>(0h1), "seq-revmemloader words_to_load: %x\n", words_to_load) : printf_19
regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1))
node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1)
connect loginfo_cycles_10, _loginfo_cycles_T_21
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_20
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
printf(clock, UInt<1>(0h1), "seq-revmemloader words_to_load_minus_one: %x\n", words_to_load_minus_one) : printf_21
regreset loginfo_cycles_11 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_22 = add(loginfo_cycles_11, UInt<1>(0h1))
node _loginfo_cycles_T_23 = tail(_loginfo_cycles_T_22, 1)
connect loginfo_cycles_11, _loginfo_cycles_T_23
node _T_45 = asUInt(reset)
node _T_46 = eq(_T_45, UInt<1>(0h0))
when _T_46 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_11) : printf_22
node _T_47 = asUInt(reset)
node _T_48 = eq(_T_47, UInt<1>(0h0))
when _T_48 :
printf(clock, UInt<1>(0h1), "seq-revmemloader end_addr_bytes_aligned: %x\n", end_addr_bytes_aligned) : printf_23
when io.src_info.ready :
connect print_not_done, UInt<1>(0h1)
else :
connect print_not_done, UInt<1>(0h0)
connect io.l2helperUser.req.bits.cmd, UInt<1>(0h0)
connect io.l2helperUser.req.bits.size, UInt<3>(0h5)
connect io.l2helperUser.req.bits.data, UInt<1>(0h0)
regreset addrinc : UInt<64>, clock, reset, UInt<64>(0h0)
node _load_info_queue_io_enq_bits_start_byte_T = eq(addrinc, words_to_load_minus_one)
node _load_info_queue_io_enq_bits_start_byte_T_1 = mux(_load_info_queue_io_enq_bits_start_byte_T, base_addr_start_index, UInt<1>(0h0))
connect load_info_queue.io.enq.bits.start_byte, _load_info_queue_io_enq_bits_start_byte_T_1
node _load_info_queue_io_enq_bits_end_byte_T = eq(addrinc, UInt<1>(0h0))
node _load_info_queue_io_enq_bits_end_byte_T_1 = mux(_load_info_queue_io_enq_bits_end_byte_T, base_addr_end_index_inclusive, UInt<5>(0h1f))
connect load_info_queue.io.enq.bits.end_byte, _load_info_queue_io_enq_bits_end_byte_T_1
node _T_49 = and(io.l2helperUser.req.ready, io.src_info.valid)
node _T_50 = and(_T_49, buf_info_queue.io.enq.ready)
node _T_51 = and(_T_50, load_info_queue.io.enq.ready)
node _T_52 = eq(addrinc, words_to_load_minus_one)
node _T_53 = and(_T_51, _T_52)
when _T_53 :
connect addrinc, UInt<1>(0h0)
else :
node _T_54 = and(io.l2helperUser.req.ready, io.src_info.valid)
node _T_55 = and(_T_54, buf_info_queue.io.enq.ready)
node _T_56 = and(_T_55, load_info_queue.io.enq.ready)
when _T_56 :
node _addrinc_T = add(addrinc, UInt<1>(0h1))
node _addrinc_T_1 = tail(_addrinc_T, 1)
connect addrinc, _addrinc_T_1
node _T_57 = and(io.src_info.ready, io.src_info.valid)
when _T_57 :
regreset loginfo_cycles_12 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_24 = add(loginfo_cycles_12, UInt<1>(0h1))
node _loginfo_cycles_T_25 = tail(_loginfo_cycles_T_24, 1)
connect loginfo_cycles_12, _loginfo_cycles_T_25
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_12) : printf_24
node _T_60 = asUInt(reset)
node _T_61 = eq(_T_60, UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "seq-revmemloader COMPLETED_LITERAL_LOAD_FOR_DECOMPRESSION\n") : printf_25
node _io_src_info_ready_T = eq(addrinc, words_to_load_minus_one)
node _io_src_info_ready_T_1 = and(io.l2helperUser.req.ready, buf_info_queue.io.enq.ready)
node _io_src_info_ready_T_2 = and(_io_src_info_ready_T_1, load_info_queue.io.enq.ready)
node _io_src_info_ready_T_3 = and(_io_src_info_ready_T_2, _io_src_info_ready_T)
connect io.src_info.ready, _io_src_info_ready_T_3
node _buf_info_queue_io_enq_valid_T = eq(addrinc, UInt<1>(0h0))
node _buf_info_queue_io_enq_valid_T_1 = and(io.l2helperUser.req.ready, io.src_info.valid)
node _buf_info_queue_io_enq_valid_T_2 = and(_buf_info_queue_io_enq_valid_T_1, load_info_queue.io.enq.ready)
node _buf_info_queue_io_enq_valid_T_3 = and(_buf_info_queue_io_enq_valid_T_2, _buf_info_queue_io_enq_valid_T)
connect buf_info_queue.io.enq.valid, _buf_info_queue_io_enq_valid_T_3
node _load_info_queue_io_enq_valid_T = and(io.l2helperUser.req.ready, io.src_info.valid)
node _load_info_queue_io_enq_valid_T_1 = and(_load_info_queue_io_enq_valid_T, buf_info_queue.io.enq.ready)
connect load_info_queue.io.enq.valid, _load_info_queue_io_enq_valid_T_1
connect buf_info_queue.io.enq.bits.len_bytes, io.src_info.bits.isize
node _io_l2helperUser_req_bits_addr_T = shl(addrinc, 5)
node _io_l2helperUser_req_bits_addr_T_1 = sub(end_addr_bytes_aligned, _io_l2helperUser_req_bits_addr_T)
node _io_l2helperUser_req_bits_addr_T_2 = tail(_io_l2helperUser_req_bits_addr_T_1, 1)
connect io.l2helperUser.req.bits.addr, _io_l2helperUser_req_bits_addr_T_2
node _io_l2helperUser_req_valid_T = and(io.src_info.valid, buf_info_queue.io.enq.ready)
node _io_l2helperUser_req_valid_T_1 = and(_io_l2helperUser_req_valid_T, load_info_queue.io.enq.ready)
connect io.l2helperUser.req.valid, _io_l2helperUser_req_valid_T_1
regreset write_start_index : UInt<6>, clock, reset, UInt<6>(0h0)
inst Queue64_UInt8 of Queue64_UInt8_224
connect Queue64_UInt8.clock, clock
connect Queue64_UInt8.reset, reset
inst Queue64_UInt8_1 of Queue64_UInt8_225
connect Queue64_UInt8_1.clock, clock
connect Queue64_UInt8_1.reset, reset
inst Queue64_UInt8_2 of Queue64_UInt8_226
connect Queue64_UInt8_2.clock, clock
connect Queue64_UInt8_2.reset, reset
inst Queue64_UInt8_3 of Queue64_UInt8_227
connect Queue64_UInt8_3.clock, clock
connect Queue64_UInt8_3.reset, reset
inst Queue64_UInt8_4 of Queue64_UInt8_228
connect Queue64_UInt8_4.clock, clock
connect Queue64_UInt8_4.reset, reset
inst Queue64_UInt8_5 of Queue64_UInt8_229
connect Queue64_UInt8_5.clock, clock
connect Queue64_UInt8_5.reset, reset
inst Queue64_UInt8_6 of Queue64_UInt8_230
connect Queue64_UInt8_6.clock, clock
connect Queue64_UInt8_6.reset, reset
inst Queue64_UInt8_7 of Queue64_UInt8_231
connect Queue64_UInt8_7.clock, clock
connect Queue64_UInt8_7.reset, reset
inst Queue64_UInt8_8 of Queue64_UInt8_232
connect Queue64_UInt8_8.clock, clock
connect Queue64_UInt8_8.reset, reset
inst Queue64_UInt8_9 of Queue64_UInt8_233
connect Queue64_UInt8_9.clock, clock
connect Queue64_UInt8_9.reset, reset
inst Queue64_UInt8_10 of Queue64_UInt8_234
connect Queue64_UInt8_10.clock, clock
connect Queue64_UInt8_10.reset, reset
inst Queue64_UInt8_11 of Queue64_UInt8_235
connect Queue64_UInt8_11.clock, clock
connect Queue64_UInt8_11.reset, reset
inst Queue64_UInt8_12 of Queue64_UInt8_236
connect Queue64_UInt8_12.clock, clock
connect Queue64_UInt8_12.reset, reset
inst Queue64_UInt8_13 of Queue64_UInt8_237
connect Queue64_UInt8_13.clock, clock
connect Queue64_UInt8_13.reset, reset
inst Queue64_UInt8_14 of Queue64_UInt8_238
connect Queue64_UInt8_14.clock, clock
connect Queue64_UInt8_14.reset, reset
inst Queue64_UInt8_15 of Queue64_UInt8_239
connect Queue64_UInt8_15.clock, clock
connect Queue64_UInt8_15.reset, reset
inst Queue64_UInt8_16 of Queue64_UInt8_240
connect Queue64_UInt8_16.clock, clock
connect Queue64_UInt8_16.reset, reset
inst Queue64_UInt8_17 of Queue64_UInt8_241
connect Queue64_UInt8_17.clock, clock
connect Queue64_UInt8_17.reset, reset
inst Queue64_UInt8_18 of Queue64_UInt8_242
connect Queue64_UInt8_18.clock, clock
connect Queue64_UInt8_18.reset, reset
inst Queue64_UInt8_19 of Queue64_UInt8_243
connect Queue64_UInt8_19.clock, clock
connect Queue64_UInt8_19.reset, reset
inst Queue64_UInt8_20 of Queue64_UInt8_244
connect Queue64_UInt8_20.clock, clock
connect Queue64_UInt8_20.reset, reset
inst Queue64_UInt8_21 of Queue64_UInt8_245
connect Queue64_UInt8_21.clock, clock
connect Queue64_UInt8_21.reset, reset
inst Queue64_UInt8_22 of Queue64_UInt8_246
connect Queue64_UInt8_22.clock, clock
connect Queue64_UInt8_22.reset, reset
inst Queue64_UInt8_23 of Queue64_UInt8_247
connect Queue64_UInt8_23.clock, clock
connect Queue64_UInt8_23.reset, reset
inst Queue64_UInt8_24 of Queue64_UInt8_248
connect Queue64_UInt8_24.clock, clock
connect Queue64_UInt8_24.reset, reset
inst Queue64_UInt8_25 of Queue64_UInt8_249
connect Queue64_UInt8_25.clock, clock
connect Queue64_UInt8_25.reset, reset
inst Queue64_UInt8_26 of Queue64_UInt8_250
connect Queue64_UInt8_26.clock, clock
connect Queue64_UInt8_26.reset, reset
inst Queue64_UInt8_27 of Queue64_UInt8_251
connect Queue64_UInt8_27.clock, clock
connect Queue64_UInt8_27.reset, reset
inst Queue64_UInt8_28 of Queue64_UInt8_252
connect Queue64_UInt8_28.clock, clock
connect Queue64_UInt8_28.reset, reset
inst Queue64_UInt8_29 of Queue64_UInt8_253
connect Queue64_UInt8_29.clock, clock
connect Queue64_UInt8_29.reset, reset
inst Queue64_UInt8_30 of Queue64_UInt8_254
connect Queue64_UInt8_30.clock, clock
connect Queue64_UInt8_30.reset, reset
inst Queue64_UInt8_31 of Queue64_UInt8_255
connect Queue64_UInt8_31.clock, clock
connect Queue64_UInt8_31.reset, reset
node _align_shamt_T = sub(UInt<5>(0h1f), load_info_queue.io.deq.bits.end_byte)
node _align_shamt_T_1 = tail(_align_shamt_T, 1)
node align_shamt = shl(_align_shamt_T_1, 3)
node memresp_bits_shifted = dshl(io.l2helperUser.resp.bits.data, align_shamt)
node _MAX_QUEUE_IDX_T = sub(UInt<6>(0h20), UInt<1>(0h1))
node MAX_QUEUE_IDX = tail(_MAX_QUEUE_IDX_T, 1)
connect Queue64_UInt8.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_1.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_2.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_3.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_4.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_5.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_6.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_7.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_8.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_9.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_10.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_11.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_12.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_13.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_14.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_15.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_16.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_17.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_18.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_19.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_20.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_21.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_22.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_23.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_24.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_25.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_26.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_27.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_28.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_29.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_30.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_31.io.enq.bits, UInt<1>(0h0)
node _idx_T = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_1 = sub(_idx_T, write_start_index)
node _idx_T_2 = asUInt(_idx_T_1)
node _idx_T_3 = sub(_idx_T_2, UInt<1>(0h0))
node _idx_T_4 = asUInt(_idx_T_3)
node idx = rem(_idx_T_4, UInt<6>(0h20))
node _T_62 = eq(UInt<1>(0h0), idx)
when _T_62 :
node _T_63 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8.io.enq.bits, _T_63
node _T_64 = eq(UInt<1>(0h1), idx)
when _T_64 :
node _T_65 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_1.io.enq.bits, _T_65
node _T_66 = eq(UInt<2>(0h2), idx)
when _T_66 :
node _T_67 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_2.io.enq.bits, _T_67
node _T_68 = eq(UInt<2>(0h3), idx)
when _T_68 :
node _T_69 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_3.io.enq.bits, _T_69
node _T_70 = eq(UInt<3>(0h4), idx)
when _T_70 :
node _T_71 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_4.io.enq.bits, _T_71
node _T_72 = eq(UInt<3>(0h5), idx)
when _T_72 :
node _T_73 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_5.io.enq.bits, _T_73
node _T_74 = eq(UInt<3>(0h6), idx)
when _T_74 :
node _T_75 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_6.io.enq.bits, _T_75
node _T_76 = eq(UInt<3>(0h7), idx)
when _T_76 :
node _T_77 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_7.io.enq.bits, _T_77
node _T_78 = eq(UInt<4>(0h8), idx)
when _T_78 :
node _T_79 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_8.io.enq.bits, _T_79
node _T_80 = eq(UInt<4>(0h9), idx)
when _T_80 :
node _T_81 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_9.io.enq.bits, _T_81
node _T_82 = eq(UInt<4>(0ha), idx)
when _T_82 :
node _T_83 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_10.io.enq.bits, _T_83
node _T_84 = eq(UInt<4>(0hb), idx)
when _T_84 :
node _T_85 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_11.io.enq.bits, _T_85
node _T_86 = eq(UInt<4>(0hc), idx)
when _T_86 :
node _T_87 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_12.io.enq.bits, _T_87
node _T_88 = eq(UInt<4>(0hd), idx)
when _T_88 :
node _T_89 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_13.io.enq.bits, _T_89
node _T_90 = eq(UInt<4>(0he), idx)
when _T_90 :
node _T_91 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_14.io.enq.bits, _T_91
node _T_92 = eq(UInt<4>(0hf), idx)
when _T_92 :
node _T_93 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_15.io.enq.bits, _T_93
node _T_94 = eq(UInt<5>(0h10), idx)
when _T_94 :
node _T_95 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_16.io.enq.bits, _T_95
node _T_96 = eq(UInt<5>(0h11), idx)
when _T_96 :
node _T_97 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_17.io.enq.bits, _T_97
node _T_98 = eq(UInt<5>(0h12), idx)
when _T_98 :
node _T_99 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_18.io.enq.bits, _T_99
node _T_100 = eq(UInt<5>(0h13), idx)
when _T_100 :
node _T_101 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_19.io.enq.bits, _T_101
node _T_102 = eq(UInt<5>(0h14), idx)
when _T_102 :
node _T_103 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_20.io.enq.bits, _T_103
node _T_104 = eq(UInt<5>(0h15), idx)
when _T_104 :
node _T_105 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_21.io.enq.bits, _T_105
node _T_106 = eq(UInt<5>(0h16), idx)
when _T_106 :
node _T_107 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_22.io.enq.bits, _T_107
node _T_108 = eq(UInt<5>(0h17), idx)
when _T_108 :
node _T_109 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_23.io.enq.bits, _T_109
node _T_110 = eq(UInt<5>(0h18), idx)
when _T_110 :
node _T_111 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_24.io.enq.bits, _T_111
node _T_112 = eq(UInt<5>(0h19), idx)
when _T_112 :
node _T_113 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_25.io.enq.bits, _T_113
node _T_114 = eq(UInt<5>(0h1a), idx)
when _T_114 :
node _T_115 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_26.io.enq.bits, _T_115
node _T_116 = eq(UInt<5>(0h1b), idx)
when _T_116 :
node _T_117 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_27.io.enq.bits, _T_117
node _T_118 = eq(UInt<5>(0h1c), idx)
when _T_118 :
node _T_119 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_28.io.enq.bits, _T_119
node _T_120 = eq(UInt<5>(0h1d), idx)
when _T_120 :
node _T_121 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_29.io.enq.bits, _T_121
node _T_122 = eq(UInt<5>(0h1e), idx)
when _T_122 :
node _T_123 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_30.io.enq.bits, _T_123
node _T_124 = eq(UInt<5>(0h1f), idx)
when _T_124 :
node _T_125 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_31.io.enq.bits, _T_125
node _idx_T_5 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_6 = sub(_idx_T_5, write_start_index)
node _idx_T_7 = asUInt(_idx_T_6)
node _idx_T_8 = sub(_idx_T_7, UInt<1>(0h1))
node _idx_T_9 = asUInt(_idx_T_8)
node idx_1 = rem(_idx_T_9, UInt<6>(0h20))
node _T_126 = eq(UInt<1>(0h0), idx_1)
when _T_126 :
node _T_127 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8.io.enq.bits, _T_127
node _T_128 = eq(UInt<1>(0h1), idx_1)
when _T_128 :
node _T_129 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_1.io.enq.bits, _T_129
node _T_130 = eq(UInt<2>(0h2), idx_1)
when _T_130 :
node _T_131 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_2.io.enq.bits, _T_131
node _T_132 = eq(UInt<2>(0h3), idx_1)
when _T_132 :
node _T_133 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_3.io.enq.bits, _T_133
node _T_134 = eq(UInt<3>(0h4), idx_1)
when _T_134 :
node _T_135 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_4.io.enq.bits, _T_135
node _T_136 = eq(UInt<3>(0h5), idx_1)
when _T_136 :
node _T_137 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_5.io.enq.bits, _T_137
node _T_138 = eq(UInt<3>(0h6), idx_1)
when _T_138 :
node _T_139 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_6.io.enq.bits, _T_139
node _T_140 = eq(UInt<3>(0h7), idx_1)
when _T_140 :
node _T_141 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_7.io.enq.bits, _T_141
node _T_142 = eq(UInt<4>(0h8), idx_1)
when _T_142 :
node _T_143 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_8.io.enq.bits, _T_143
node _T_144 = eq(UInt<4>(0h9), idx_1)
when _T_144 :
node _T_145 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_9.io.enq.bits, _T_145
node _T_146 = eq(UInt<4>(0ha), idx_1)
when _T_146 :
node _T_147 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_10.io.enq.bits, _T_147
node _T_148 = eq(UInt<4>(0hb), idx_1)
when _T_148 :
node _T_149 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_11.io.enq.bits, _T_149
node _T_150 = eq(UInt<4>(0hc), idx_1)
when _T_150 :
node _T_151 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_12.io.enq.bits, _T_151
node _T_152 = eq(UInt<4>(0hd), idx_1)
when _T_152 :
node _T_153 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_13.io.enq.bits, _T_153
node _T_154 = eq(UInt<4>(0he), idx_1)
when _T_154 :
node _T_155 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_14.io.enq.bits, _T_155
node _T_156 = eq(UInt<4>(0hf), idx_1)
when _T_156 :
node _T_157 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_15.io.enq.bits, _T_157
node _T_158 = eq(UInt<5>(0h10), idx_1)
when _T_158 :
node _T_159 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_16.io.enq.bits, _T_159
node _T_160 = eq(UInt<5>(0h11), idx_1)
when _T_160 :
node _T_161 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_17.io.enq.bits, _T_161
node _T_162 = eq(UInt<5>(0h12), idx_1)
when _T_162 :
node _T_163 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_18.io.enq.bits, _T_163
node _T_164 = eq(UInt<5>(0h13), idx_1)
when _T_164 :
node _T_165 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_19.io.enq.bits, _T_165
node _T_166 = eq(UInt<5>(0h14), idx_1)
when _T_166 :
node _T_167 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_20.io.enq.bits, _T_167
node _T_168 = eq(UInt<5>(0h15), idx_1)
when _T_168 :
node _T_169 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_21.io.enq.bits, _T_169
node _T_170 = eq(UInt<5>(0h16), idx_1)
when _T_170 :
node _T_171 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_22.io.enq.bits, _T_171
node _T_172 = eq(UInt<5>(0h17), idx_1)
when _T_172 :
node _T_173 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_23.io.enq.bits, _T_173
node _T_174 = eq(UInt<5>(0h18), idx_1)
when _T_174 :
node _T_175 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_24.io.enq.bits, _T_175
node _T_176 = eq(UInt<5>(0h19), idx_1)
when _T_176 :
node _T_177 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_25.io.enq.bits, _T_177
node _T_178 = eq(UInt<5>(0h1a), idx_1)
when _T_178 :
node _T_179 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_26.io.enq.bits, _T_179
node _T_180 = eq(UInt<5>(0h1b), idx_1)
when _T_180 :
node _T_181 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_27.io.enq.bits, _T_181
node _T_182 = eq(UInt<5>(0h1c), idx_1)
when _T_182 :
node _T_183 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_28.io.enq.bits, _T_183
node _T_184 = eq(UInt<5>(0h1d), idx_1)
when _T_184 :
node _T_185 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_29.io.enq.bits, _T_185
node _T_186 = eq(UInt<5>(0h1e), idx_1)
when _T_186 :
node _T_187 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_30.io.enq.bits, _T_187
node _T_188 = eq(UInt<5>(0h1f), idx_1)
when _T_188 :
node _T_189 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_31.io.enq.bits, _T_189
node _idx_T_10 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_11 = sub(_idx_T_10, write_start_index)
node _idx_T_12 = asUInt(_idx_T_11)
node _idx_T_13 = sub(_idx_T_12, UInt<2>(0h2))
node _idx_T_14 = asUInt(_idx_T_13)
node idx_2 = rem(_idx_T_14, UInt<6>(0h20))
node _T_190 = eq(UInt<1>(0h0), idx_2)
when _T_190 :
node _T_191 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8.io.enq.bits, _T_191
node _T_192 = eq(UInt<1>(0h1), idx_2)
when _T_192 :
node _T_193 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_1.io.enq.bits, _T_193
node _T_194 = eq(UInt<2>(0h2), idx_2)
when _T_194 :
node _T_195 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_2.io.enq.bits, _T_195
node _T_196 = eq(UInt<2>(0h3), idx_2)
when _T_196 :
node _T_197 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_3.io.enq.bits, _T_197
node _T_198 = eq(UInt<3>(0h4), idx_2)
when _T_198 :
node _T_199 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_4.io.enq.bits, _T_199
node _T_200 = eq(UInt<3>(0h5), idx_2)
when _T_200 :
node _T_201 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_5.io.enq.bits, _T_201
node _T_202 = eq(UInt<3>(0h6), idx_2)
when _T_202 :
node _T_203 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_6.io.enq.bits, _T_203
node _T_204 = eq(UInt<3>(0h7), idx_2)
when _T_204 :
node _T_205 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_7.io.enq.bits, _T_205
node _T_206 = eq(UInt<4>(0h8), idx_2)
when _T_206 :
node _T_207 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_8.io.enq.bits, _T_207
node _T_208 = eq(UInt<4>(0h9), idx_2)
when _T_208 :
node _T_209 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_9.io.enq.bits, _T_209
node _T_210 = eq(UInt<4>(0ha), idx_2)
when _T_210 :
node _T_211 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_10.io.enq.bits, _T_211
node _T_212 = eq(UInt<4>(0hb), idx_2)
when _T_212 :
node _T_213 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_11.io.enq.bits, _T_213
node _T_214 = eq(UInt<4>(0hc), idx_2)
when _T_214 :
node _T_215 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_12.io.enq.bits, _T_215
node _T_216 = eq(UInt<4>(0hd), idx_2)
when _T_216 :
node _T_217 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_13.io.enq.bits, _T_217
node _T_218 = eq(UInt<4>(0he), idx_2)
when _T_218 :
node _T_219 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_14.io.enq.bits, _T_219
node _T_220 = eq(UInt<4>(0hf), idx_2)
when _T_220 :
node _T_221 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_15.io.enq.bits, _T_221
node _T_222 = eq(UInt<5>(0h10), idx_2)
when _T_222 :
node _T_223 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_16.io.enq.bits, _T_223
node _T_224 = eq(UInt<5>(0h11), idx_2)
when _T_224 :
node _T_225 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_17.io.enq.bits, _T_225
node _T_226 = eq(UInt<5>(0h12), idx_2)
when _T_226 :
node _T_227 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_18.io.enq.bits, _T_227
node _T_228 = eq(UInt<5>(0h13), idx_2)
when _T_228 :
node _T_229 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_19.io.enq.bits, _T_229
node _T_230 = eq(UInt<5>(0h14), idx_2)
when _T_230 :
node _T_231 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_20.io.enq.bits, _T_231
node _T_232 = eq(UInt<5>(0h15), idx_2)
when _T_232 :
node _T_233 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_21.io.enq.bits, _T_233
node _T_234 = eq(UInt<5>(0h16), idx_2)
when _T_234 :
node _T_235 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_22.io.enq.bits, _T_235
node _T_236 = eq(UInt<5>(0h17), idx_2)
when _T_236 :
node _T_237 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_23.io.enq.bits, _T_237
node _T_238 = eq(UInt<5>(0h18), idx_2)
when _T_238 :
node _T_239 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_24.io.enq.bits, _T_239
node _T_240 = eq(UInt<5>(0h19), idx_2)
when _T_240 :
node _T_241 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_25.io.enq.bits, _T_241
node _T_242 = eq(UInt<5>(0h1a), idx_2)
when _T_242 :
node _T_243 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_26.io.enq.bits, _T_243
node _T_244 = eq(UInt<5>(0h1b), idx_2)
when _T_244 :
node _T_245 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_27.io.enq.bits, _T_245
node _T_246 = eq(UInt<5>(0h1c), idx_2)
when _T_246 :
node _T_247 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_28.io.enq.bits, _T_247
node _T_248 = eq(UInt<5>(0h1d), idx_2)
when _T_248 :
node _T_249 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_29.io.enq.bits, _T_249
node _T_250 = eq(UInt<5>(0h1e), idx_2)
when _T_250 :
node _T_251 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_30.io.enq.bits, _T_251
node _T_252 = eq(UInt<5>(0h1f), idx_2)
when _T_252 :
node _T_253 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_31.io.enq.bits, _T_253
node _idx_T_15 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_16 = sub(_idx_T_15, write_start_index)
node _idx_T_17 = asUInt(_idx_T_16)
node _idx_T_18 = sub(_idx_T_17, UInt<2>(0h3))
node _idx_T_19 = asUInt(_idx_T_18)
node idx_3 = rem(_idx_T_19, UInt<6>(0h20))
node _T_254 = eq(UInt<1>(0h0), idx_3)
when _T_254 :
node _T_255 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8.io.enq.bits, _T_255
node _T_256 = eq(UInt<1>(0h1), idx_3)
when _T_256 :
node _T_257 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_1.io.enq.bits, _T_257
node _T_258 = eq(UInt<2>(0h2), idx_3)
when _T_258 :
node _T_259 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_2.io.enq.bits, _T_259
node _T_260 = eq(UInt<2>(0h3), idx_3)
when _T_260 :
node _T_261 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_3.io.enq.bits, _T_261
node _T_262 = eq(UInt<3>(0h4), idx_3)
when _T_262 :
node _T_263 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_4.io.enq.bits, _T_263
node _T_264 = eq(UInt<3>(0h5), idx_3)
when _T_264 :
node _T_265 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_5.io.enq.bits, _T_265
node _T_266 = eq(UInt<3>(0h6), idx_3)
when _T_266 :
node _T_267 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_6.io.enq.bits, _T_267
node _T_268 = eq(UInt<3>(0h7), idx_3)
when _T_268 :
node _T_269 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_7.io.enq.bits, _T_269
node _T_270 = eq(UInt<4>(0h8), idx_3)
when _T_270 :
node _T_271 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_8.io.enq.bits, _T_271
node _T_272 = eq(UInt<4>(0h9), idx_3)
when _T_272 :
node _T_273 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_9.io.enq.bits, _T_273
node _T_274 = eq(UInt<4>(0ha), idx_3)
when _T_274 :
node _T_275 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_10.io.enq.bits, _T_275
node _T_276 = eq(UInt<4>(0hb), idx_3)
when _T_276 :
node _T_277 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_11.io.enq.bits, _T_277
node _T_278 = eq(UInt<4>(0hc), idx_3)
when _T_278 :
node _T_279 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_12.io.enq.bits, _T_279
node _T_280 = eq(UInt<4>(0hd), idx_3)
when _T_280 :
node _T_281 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_13.io.enq.bits, _T_281
node _T_282 = eq(UInt<4>(0he), idx_3)
when _T_282 :
node _T_283 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_14.io.enq.bits, _T_283
node _T_284 = eq(UInt<4>(0hf), idx_3)
when _T_284 :
node _T_285 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_15.io.enq.bits, _T_285
node _T_286 = eq(UInt<5>(0h10), idx_3)
when _T_286 :
node _T_287 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_16.io.enq.bits, _T_287
node _T_288 = eq(UInt<5>(0h11), idx_3)
when _T_288 :
node _T_289 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_17.io.enq.bits, _T_289
node _T_290 = eq(UInt<5>(0h12), idx_3)
when _T_290 :
node _T_291 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_18.io.enq.bits, _T_291
node _T_292 = eq(UInt<5>(0h13), idx_3)
when _T_292 :
node _T_293 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_19.io.enq.bits, _T_293
node _T_294 = eq(UInt<5>(0h14), idx_3)
when _T_294 :
node _T_295 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_20.io.enq.bits, _T_295
node _T_296 = eq(UInt<5>(0h15), idx_3)
when _T_296 :
node _T_297 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_21.io.enq.bits, _T_297
node _T_298 = eq(UInt<5>(0h16), idx_3)
when _T_298 :
node _T_299 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_22.io.enq.bits, _T_299
node _T_300 = eq(UInt<5>(0h17), idx_3)
when _T_300 :
node _T_301 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_23.io.enq.bits, _T_301
node _T_302 = eq(UInt<5>(0h18), idx_3)
when _T_302 :
node _T_303 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_24.io.enq.bits, _T_303
node _T_304 = eq(UInt<5>(0h19), idx_3)
when _T_304 :
node _T_305 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_25.io.enq.bits, _T_305
node _T_306 = eq(UInt<5>(0h1a), idx_3)
when _T_306 :
node _T_307 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_26.io.enq.bits, _T_307
node _T_308 = eq(UInt<5>(0h1b), idx_3)
when _T_308 :
node _T_309 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_27.io.enq.bits, _T_309
node _T_310 = eq(UInt<5>(0h1c), idx_3)
when _T_310 :
node _T_311 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_28.io.enq.bits, _T_311
node _T_312 = eq(UInt<5>(0h1d), idx_3)
when _T_312 :
node _T_313 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_29.io.enq.bits, _T_313
node _T_314 = eq(UInt<5>(0h1e), idx_3)
when _T_314 :
node _T_315 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_30.io.enq.bits, _T_315
node _T_316 = eq(UInt<5>(0h1f), idx_3)
when _T_316 :
node _T_317 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_31.io.enq.bits, _T_317
node _idx_T_20 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_21 = sub(_idx_T_20, write_start_index)
node _idx_T_22 = asUInt(_idx_T_21)
node _idx_T_23 = sub(_idx_T_22, UInt<3>(0h4))
node _idx_T_24 = asUInt(_idx_T_23)
node idx_4 = rem(_idx_T_24, UInt<6>(0h20))
node _T_318 = eq(UInt<1>(0h0), idx_4)
when _T_318 :
node _T_319 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8.io.enq.bits, _T_319
node _T_320 = eq(UInt<1>(0h1), idx_4)
when _T_320 :
node _T_321 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_1.io.enq.bits, _T_321
node _T_322 = eq(UInt<2>(0h2), idx_4)
when _T_322 :
node _T_323 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_2.io.enq.bits, _T_323
node _T_324 = eq(UInt<2>(0h3), idx_4)
when _T_324 :
node _T_325 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_3.io.enq.bits, _T_325
node _T_326 = eq(UInt<3>(0h4), idx_4)
when _T_326 :
node _T_327 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_4.io.enq.bits, _T_327
node _T_328 = eq(UInt<3>(0h5), idx_4)
when _T_328 :
node _T_329 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_5.io.enq.bits, _T_329
node _T_330 = eq(UInt<3>(0h6), idx_4)
when _T_330 :
node _T_331 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_6.io.enq.bits, _T_331
node _T_332 = eq(UInt<3>(0h7), idx_4)
when _T_332 :
node _T_333 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_7.io.enq.bits, _T_333
node _T_334 = eq(UInt<4>(0h8), idx_4)
when _T_334 :
node _T_335 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_8.io.enq.bits, _T_335
node _T_336 = eq(UInt<4>(0h9), idx_4)
when _T_336 :
node _T_337 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_9.io.enq.bits, _T_337
node _T_338 = eq(UInt<4>(0ha), idx_4)
when _T_338 :
node _T_339 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_10.io.enq.bits, _T_339
node _T_340 = eq(UInt<4>(0hb), idx_4)
when _T_340 :
node _T_341 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_11.io.enq.bits, _T_341
node _T_342 = eq(UInt<4>(0hc), idx_4)
when _T_342 :
node _T_343 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_12.io.enq.bits, _T_343
node _T_344 = eq(UInt<4>(0hd), idx_4)
when _T_344 :
node _T_345 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_13.io.enq.bits, _T_345
node _T_346 = eq(UInt<4>(0he), idx_4)
when _T_346 :
node _T_347 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_14.io.enq.bits, _T_347
node _T_348 = eq(UInt<4>(0hf), idx_4)
when _T_348 :
node _T_349 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_15.io.enq.bits, _T_349
node _T_350 = eq(UInt<5>(0h10), idx_4)
when _T_350 :
node _T_351 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_16.io.enq.bits, _T_351
node _T_352 = eq(UInt<5>(0h11), idx_4)
when _T_352 :
node _T_353 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_17.io.enq.bits, _T_353
node _T_354 = eq(UInt<5>(0h12), idx_4)
when _T_354 :
node _T_355 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_18.io.enq.bits, _T_355
node _T_356 = eq(UInt<5>(0h13), idx_4)
when _T_356 :
node _T_357 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_19.io.enq.bits, _T_357
node _T_358 = eq(UInt<5>(0h14), idx_4)
when _T_358 :
node _T_359 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_20.io.enq.bits, _T_359
node _T_360 = eq(UInt<5>(0h15), idx_4)
when _T_360 :
node _T_361 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_21.io.enq.bits, _T_361
node _T_362 = eq(UInt<5>(0h16), idx_4)
when _T_362 :
node _T_363 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_22.io.enq.bits, _T_363
node _T_364 = eq(UInt<5>(0h17), idx_4)
when _T_364 :
node _T_365 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_23.io.enq.bits, _T_365
node _T_366 = eq(UInt<5>(0h18), idx_4)
when _T_366 :
node _T_367 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_24.io.enq.bits, _T_367
node _T_368 = eq(UInt<5>(0h19), idx_4)
when _T_368 :
node _T_369 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_25.io.enq.bits, _T_369
node _T_370 = eq(UInt<5>(0h1a), idx_4)
when _T_370 :
node _T_371 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_26.io.enq.bits, _T_371
node _T_372 = eq(UInt<5>(0h1b), idx_4)
when _T_372 :
node _T_373 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_27.io.enq.bits, _T_373
node _T_374 = eq(UInt<5>(0h1c), idx_4)
when _T_374 :
node _T_375 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_28.io.enq.bits, _T_375
node _T_376 = eq(UInt<5>(0h1d), idx_4)
when _T_376 :
node _T_377 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_29.io.enq.bits, _T_377
node _T_378 = eq(UInt<5>(0h1e), idx_4)
when _T_378 :
node _T_379 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_30.io.enq.bits, _T_379
node _T_380 = eq(UInt<5>(0h1f), idx_4)
when _T_380 :
node _T_381 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_31.io.enq.bits, _T_381
node _idx_T_25 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_26 = sub(_idx_T_25, write_start_index)
node _idx_T_27 = asUInt(_idx_T_26)
node _idx_T_28 = sub(_idx_T_27, UInt<3>(0h5))
node _idx_T_29 = asUInt(_idx_T_28)
node idx_5 = rem(_idx_T_29, UInt<6>(0h20))
node _T_382 = eq(UInt<1>(0h0), idx_5)
when _T_382 :
node _T_383 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8.io.enq.bits, _T_383
node _T_384 = eq(UInt<1>(0h1), idx_5)
when _T_384 :
node _T_385 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_1.io.enq.bits, _T_385
node _T_386 = eq(UInt<2>(0h2), idx_5)
when _T_386 :
node _T_387 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_2.io.enq.bits, _T_387
node _T_388 = eq(UInt<2>(0h3), idx_5)
when _T_388 :
node _T_389 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_3.io.enq.bits, _T_389
node _T_390 = eq(UInt<3>(0h4), idx_5)
when _T_390 :
node _T_391 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_4.io.enq.bits, _T_391
node _T_392 = eq(UInt<3>(0h5), idx_5)
when _T_392 :
node _T_393 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_5.io.enq.bits, _T_393
node _T_394 = eq(UInt<3>(0h6), idx_5)
when _T_394 :
node _T_395 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_6.io.enq.bits, _T_395
node _T_396 = eq(UInt<3>(0h7), idx_5)
when _T_396 :
node _T_397 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_7.io.enq.bits, _T_397
node _T_398 = eq(UInt<4>(0h8), idx_5)
when _T_398 :
node _T_399 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_8.io.enq.bits, _T_399
node _T_400 = eq(UInt<4>(0h9), idx_5)
when _T_400 :
node _T_401 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_9.io.enq.bits, _T_401
node _T_402 = eq(UInt<4>(0ha), idx_5)
when _T_402 :
node _T_403 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_10.io.enq.bits, _T_403
node _T_404 = eq(UInt<4>(0hb), idx_5)
when _T_404 :
node _T_405 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_11.io.enq.bits, _T_405
node _T_406 = eq(UInt<4>(0hc), idx_5)
when _T_406 :
node _T_407 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_12.io.enq.bits, _T_407
node _T_408 = eq(UInt<4>(0hd), idx_5)
when _T_408 :
node _T_409 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_13.io.enq.bits, _T_409
node _T_410 = eq(UInt<4>(0he), idx_5)
when _T_410 :
node _T_411 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_14.io.enq.bits, _T_411
node _T_412 = eq(UInt<4>(0hf), idx_5)
when _T_412 :
node _T_413 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_15.io.enq.bits, _T_413
node _T_414 = eq(UInt<5>(0h10), idx_5)
when _T_414 :
node _T_415 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_16.io.enq.bits, _T_415
node _T_416 = eq(UInt<5>(0h11), idx_5)
when _T_416 :
node _T_417 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_17.io.enq.bits, _T_417
node _T_418 = eq(UInt<5>(0h12), idx_5)
when _T_418 :
node _T_419 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_18.io.enq.bits, _T_419
node _T_420 = eq(UInt<5>(0h13), idx_5)
when _T_420 :
node _T_421 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_19.io.enq.bits, _T_421
node _T_422 = eq(UInt<5>(0h14), idx_5)
when _T_422 :
node _T_423 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_20.io.enq.bits, _T_423
node _T_424 = eq(UInt<5>(0h15), idx_5)
when _T_424 :
node _T_425 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_21.io.enq.bits, _T_425
node _T_426 = eq(UInt<5>(0h16), idx_5)
when _T_426 :
node _T_427 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_22.io.enq.bits, _T_427
node _T_428 = eq(UInt<5>(0h17), idx_5)
when _T_428 :
node _T_429 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_23.io.enq.bits, _T_429
node _T_430 = eq(UInt<5>(0h18), idx_5)
when _T_430 :
node _T_431 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_24.io.enq.bits, _T_431
node _T_432 = eq(UInt<5>(0h19), idx_5)
when _T_432 :
node _T_433 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_25.io.enq.bits, _T_433
node _T_434 = eq(UInt<5>(0h1a), idx_5)
when _T_434 :
node _T_435 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_26.io.enq.bits, _T_435
node _T_436 = eq(UInt<5>(0h1b), idx_5)
when _T_436 :
node _T_437 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_27.io.enq.bits, _T_437
node _T_438 = eq(UInt<5>(0h1c), idx_5)
when _T_438 :
node _T_439 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_28.io.enq.bits, _T_439
node _T_440 = eq(UInt<5>(0h1d), idx_5)
when _T_440 :
node _T_441 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_29.io.enq.bits, _T_441
node _T_442 = eq(UInt<5>(0h1e), idx_5)
when _T_442 :
node _T_443 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_30.io.enq.bits, _T_443
node _T_444 = eq(UInt<5>(0h1f), idx_5)
when _T_444 :
node _T_445 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_31.io.enq.bits, _T_445
node _idx_T_30 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_31 = sub(_idx_T_30, write_start_index)
node _idx_T_32 = asUInt(_idx_T_31)
node _idx_T_33 = sub(_idx_T_32, UInt<3>(0h6))
node _idx_T_34 = asUInt(_idx_T_33)
node idx_6 = rem(_idx_T_34, UInt<6>(0h20))
node _T_446 = eq(UInt<1>(0h0), idx_6)
when _T_446 :
node _T_447 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8.io.enq.bits, _T_447
node _T_448 = eq(UInt<1>(0h1), idx_6)
when _T_448 :
node _T_449 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_1.io.enq.bits, _T_449
node _T_450 = eq(UInt<2>(0h2), idx_6)
when _T_450 :
node _T_451 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_2.io.enq.bits, _T_451
node _T_452 = eq(UInt<2>(0h3), idx_6)
when _T_452 :
node _T_453 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_3.io.enq.bits, _T_453
node _T_454 = eq(UInt<3>(0h4), idx_6)
when _T_454 :
node _T_455 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_4.io.enq.bits, _T_455
node _T_456 = eq(UInt<3>(0h5), idx_6)
when _T_456 :
node _T_457 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_5.io.enq.bits, _T_457
node _T_458 = eq(UInt<3>(0h6), idx_6)
when _T_458 :
node _T_459 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_6.io.enq.bits, _T_459
node _T_460 = eq(UInt<3>(0h7), idx_6)
when _T_460 :
node _T_461 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_7.io.enq.bits, _T_461
node _T_462 = eq(UInt<4>(0h8), idx_6)
when _T_462 :
node _T_463 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_8.io.enq.bits, _T_463
node _T_464 = eq(UInt<4>(0h9), idx_6)
when _T_464 :
node _T_465 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_9.io.enq.bits, _T_465
node _T_466 = eq(UInt<4>(0ha), idx_6)
when _T_466 :
node _T_467 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_10.io.enq.bits, _T_467
node _T_468 = eq(UInt<4>(0hb), idx_6)
when _T_468 :
node _T_469 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_11.io.enq.bits, _T_469
node _T_470 = eq(UInt<4>(0hc), idx_6)
when _T_470 :
node _T_471 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_12.io.enq.bits, _T_471
node _T_472 = eq(UInt<4>(0hd), idx_6)
when _T_472 :
node _T_473 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_13.io.enq.bits, _T_473
node _T_474 = eq(UInt<4>(0he), idx_6)
when _T_474 :
node _T_475 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_14.io.enq.bits, _T_475
node _T_476 = eq(UInt<4>(0hf), idx_6)
when _T_476 :
node _T_477 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_15.io.enq.bits, _T_477
node _T_478 = eq(UInt<5>(0h10), idx_6)
when _T_478 :
node _T_479 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_16.io.enq.bits, _T_479
node _T_480 = eq(UInt<5>(0h11), idx_6)
when _T_480 :
node _T_481 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_17.io.enq.bits, _T_481
node _T_482 = eq(UInt<5>(0h12), idx_6)
when _T_482 :
node _T_483 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_18.io.enq.bits, _T_483
node _T_484 = eq(UInt<5>(0h13), idx_6)
when _T_484 :
node _T_485 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_19.io.enq.bits, _T_485
node _T_486 = eq(UInt<5>(0h14), idx_6)
when _T_486 :
node _T_487 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_20.io.enq.bits, _T_487
node _T_488 = eq(UInt<5>(0h15), idx_6)
when _T_488 :
node _T_489 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_21.io.enq.bits, _T_489
node _T_490 = eq(UInt<5>(0h16), idx_6)
when _T_490 :
node _T_491 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_22.io.enq.bits, _T_491
node _T_492 = eq(UInt<5>(0h17), idx_6)
when _T_492 :
node _T_493 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_23.io.enq.bits, _T_493
node _T_494 = eq(UInt<5>(0h18), idx_6)
when _T_494 :
node _T_495 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_24.io.enq.bits, _T_495
node _T_496 = eq(UInt<5>(0h19), idx_6)
when _T_496 :
node _T_497 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_25.io.enq.bits, _T_497
node _T_498 = eq(UInt<5>(0h1a), idx_6)
when _T_498 :
node _T_499 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_26.io.enq.bits, _T_499
node _T_500 = eq(UInt<5>(0h1b), idx_6)
when _T_500 :
node _T_501 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_27.io.enq.bits, _T_501
node _T_502 = eq(UInt<5>(0h1c), idx_6)
when _T_502 :
node _T_503 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_28.io.enq.bits, _T_503
node _T_504 = eq(UInt<5>(0h1d), idx_6)
when _T_504 :
node _T_505 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_29.io.enq.bits, _T_505
node _T_506 = eq(UInt<5>(0h1e), idx_6)
when _T_506 :
node _T_507 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_30.io.enq.bits, _T_507
node _T_508 = eq(UInt<5>(0h1f), idx_6)
when _T_508 :
node _T_509 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_31.io.enq.bits, _T_509
node _idx_T_35 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_36 = sub(_idx_T_35, write_start_index)
node _idx_T_37 = asUInt(_idx_T_36)
node _idx_T_38 = sub(_idx_T_37, UInt<3>(0h7))
node _idx_T_39 = asUInt(_idx_T_38)
node idx_7 = rem(_idx_T_39, UInt<6>(0h20))
node _T_510 = eq(UInt<1>(0h0), idx_7)
when _T_510 :
node _T_511 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8.io.enq.bits, _T_511
node _T_512 = eq(UInt<1>(0h1), idx_7)
when _T_512 :
node _T_513 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_1.io.enq.bits, _T_513
node _T_514 = eq(UInt<2>(0h2), idx_7)
when _T_514 :
node _T_515 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_2.io.enq.bits, _T_515
node _T_516 = eq(UInt<2>(0h3), idx_7)
when _T_516 :
node _T_517 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_3.io.enq.bits, _T_517
node _T_518 = eq(UInt<3>(0h4), idx_7)
when _T_518 :
node _T_519 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_4.io.enq.bits, _T_519
node _T_520 = eq(UInt<3>(0h5), idx_7)
when _T_520 :
node _T_521 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_5.io.enq.bits, _T_521
node _T_522 = eq(UInt<3>(0h6), idx_7)
when _T_522 :
node _T_523 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_6.io.enq.bits, _T_523
node _T_524 = eq(UInt<3>(0h7), idx_7)
when _T_524 :
node _T_525 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_7.io.enq.bits, _T_525
node _T_526 = eq(UInt<4>(0h8), idx_7)
when _T_526 :
node _T_527 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_8.io.enq.bits, _T_527
node _T_528 = eq(UInt<4>(0h9), idx_7)
when _T_528 :
node _T_529 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_9.io.enq.bits, _T_529
node _T_530 = eq(UInt<4>(0ha), idx_7)
when _T_530 :
node _T_531 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_10.io.enq.bits, _T_531
node _T_532 = eq(UInt<4>(0hb), idx_7)
when _T_532 :
node _T_533 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_11.io.enq.bits, _T_533
node _T_534 = eq(UInt<4>(0hc), idx_7)
when _T_534 :
node _T_535 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_12.io.enq.bits, _T_535
node _T_536 = eq(UInt<4>(0hd), idx_7)
when _T_536 :
node _T_537 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_13.io.enq.bits, _T_537
node _T_538 = eq(UInt<4>(0he), idx_7)
when _T_538 :
node _T_539 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_14.io.enq.bits, _T_539
node _T_540 = eq(UInt<4>(0hf), idx_7)
when _T_540 :
node _T_541 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_15.io.enq.bits, _T_541
node _T_542 = eq(UInt<5>(0h10), idx_7)
when _T_542 :
node _T_543 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_16.io.enq.bits, _T_543
node _T_544 = eq(UInt<5>(0h11), idx_7)
when _T_544 :
node _T_545 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_17.io.enq.bits, _T_545
node _T_546 = eq(UInt<5>(0h12), idx_7)
when _T_546 :
node _T_547 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_18.io.enq.bits, _T_547
node _T_548 = eq(UInt<5>(0h13), idx_7)
when _T_548 :
node _T_549 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_19.io.enq.bits, _T_549
node _T_550 = eq(UInt<5>(0h14), idx_7)
when _T_550 :
node _T_551 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_20.io.enq.bits, _T_551
node _T_552 = eq(UInt<5>(0h15), idx_7)
when _T_552 :
node _T_553 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_21.io.enq.bits, _T_553
node _T_554 = eq(UInt<5>(0h16), idx_7)
when _T_554 :
node _T_555 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_22.io.enq.bits, _T_555
node _T_556 = eq(UInt<5>(0h17), idx_7)
when _T_556 :
node _T_557 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_23.io.enq.bits, _T_557
node _T_558 = eq(UInt<5>(0h18), idx_7)
when _T_558 :
node _T_559 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_24.io.enq.bits, _T_559
node _T_560 = eq(UInt<5>(0h19), idx_7)
when _T_560 :
node _T_561 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_25.io.enq.bits, _T_561
node _T_562 = eq(UInt<5>(0h1a), idx_7)
when _T_562 :
node _T_563 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_26.io.enq.bits, _T_563
node _T_564 = eq(UInt<5>(0h1b), idx_7)
when _T_564 :
node _T_565 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_27.io.enq.bits, _T_565
node _T_566 = eq(UInt<5>(0h1c), idx_7)
when _T_566 :
node _T_567 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_28.io.enq.bits, _T_567
node _T_568 = eq(UInt<5>(0h1d), idx_7)
when _T_568 :
node _T_569 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_29.io.enq.bits, _T_569
node _T_570 = eq(UInt<5>(0h1e), idx_7)
when _T_570 :
node _T_571 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_30.io.enq.bits, _T_571
node _T_572 = eq(UInt<5>(0h1f), idx_7)
when _T_572 :
node _T_573 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_31.io.enq.bits, _T_573
node _idx_T_40 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_41 = sub(_idx_T_40, write_start_index)
node _idx_T_42 = asUInt(_idx_T_41)
node _idx_T_43 = sub(_idx_T_42, UInt<4>(0h8))
node _idx_T_44 = asUInt(_idx_T_43)
node idx_8 = rem(_idx_T_44, UInt<6>(0h20))
node _T_574 = eq(UInt<1>(0h0), idx_8)
when _T_574 :
node _T_575 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8.io.enq.bits, _T_575
node _T_576 = eq(UInt<1>(0h1), idx_8)
when _T_576 :
node _T_577 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_1.io.enq.bits, _T_577
node _T_578 = eq(UInt<2>(0h2), idx_8)
when _T_578 :
node _T_579 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_2.io.enq.bits, _T_579
node _T_580 = eq(UInt<2>(0h3), idx_8)
when _T_580 :
node _T_581 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_3.io.enq.bits, _T_581
node _T_582 = eq(UInt<3>(0h4), idx_8)
when _T_582 :
node _T_583 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_4.io.enq.bits, _T_583
node _T_584 = eq(UInt<3>(0h5), idx_8)
when _T_584 :
node _T_585 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_5.io.enq.bits, _T_585
node _T_586 = eq(UInt<3>(0h6), idx_8)
when _T_586 :
node _T_587 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_6.io.enq.bits, _T_587
node _T_588 = eq(UInt<3>(0h7), idx_8)
when _T_588 :
node _T_589 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_7.io.enq.bits, _T_589
node _T_590 = eq(UInt<4>(0h8), idx_8)
when _T_590 :
node _T_591 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_8.io.enq.bits, _T_591
node _T_592 = eq(UInt<4>(0h9), idx_8)
when _T_592 :
node _T_593 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_9.io.enq.bits, _T_593
node _T_594 = eq(UInt<4>(0ha), idx_8)
when _T_594 :
node _T_595 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_10.io.enq.bits, _T_595
node _T_596 = eq(UInt<4>(0hb), idx_8)
when _T_596 :
node _T_597 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_11.io.enq.bits, _T_597
node _T_598 = eq(UInt<4>(0hc), idx_8)
when _T_598 :
node _T_599 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_12.io.enq.bits, _T_599
node _T_600 = eq(UInt<4>(0hd), idx_8)
when _T_600 :
node _T_601 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_13.io.enq.bits, _T_601
node _T_602 = eq(UInt<4>(0he), idx_8)
when _T_602 :
node _T_603 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_14.io.enq.bits, _T_603
node _T_604 = eq(UInt<4>(0hf), idx_8)
when _T_604 :
node _T_605 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_15.io.enq.bits, _T_605
node _T_606 = eq(UInt<5>(0h10), idx_8)
when _T_606 :
node _T_607 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_16.io.enq.bits, _T_607
node _T_608 = eq(UInt<5>(0h11), idx_8)
when _T_608 :
node _T_609 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_17.io.enq.bits, _T_609
node _T_610 = eq(UInt<5>(0h12), idx_8)
when _T_610 :
node _T_611 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_18.io.enq.bits, _T_611
node _T_612 = eq(UInt<5>(0h13), idx_8)
when _T_612 :
node _T_613 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_19.io.enq.bits, _T_613
node _T_614 = eq(UInt<5>(0h14), idx_8)
when _T_614 :
node _T_615 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_20.io.enq.bits, _T_615
node _T_616 = eq(UInt<5>(0h15), idx_8)
when _T_616 :
node _T_617 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_21.io.enq.bits, _T_617
node _T_618 = eq(UInt<5>(0h16), idx_8)
when _T_618 :
node _T_619 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_22.io.enq.bits, _T_619
node _T_620 = eq(UInt<5>(0h17), idx_8)
when _T_620 :
node _T_621 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_23.io.enq.bits, _T_621
node _T_622 = eq(UInt<5>(0h18), idx_8)
when _T_622 :
node _T_623 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_24.io.enq.bits, _T_623
node _T_624 = eq(UInt<5>(0h19), idx_8)
when _T_624 :
node _T_625 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_25.io.enq.bits, _T_625
node _T_626 = eq(UInt<5>(0h1a), idx_8)
when _T_626 :
node _T_627 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_26.io.enq.bits, _T_627
node _T_628 = eq(UInt<5>(0h1b), idx_8)
when _T_628 :
node _T_629 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_27.io.enq.bits, _T_629
node _T_630 = eq(UInt<5>(0h1c), idx_8)
when _T_630 :
node _T_631 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_28.io.enq.bits, _T_631
node _T_632 = eq(UInt<5>(0h1d), idx_8)
when _T_632 :
node _T_633 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_29.io.enq.bits, _T_633
node _T_634 = eq(UInt<5>(0h1e), idx_8)
when _T_634 :
node _T_635 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_30.io.enq.bits, _T_635
node _T_636 = eq(UInt<5>(0h1f), idx_8)
when _T_636 :
node _T_637 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_31.io.enq.bits, _T_637
node _idx_T_45 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_46 = sub(_idx_T_45, write_start_index)
node _idx_T_47 = asUInt(_idx_T_46)
node _idx_T_48 = sub(_idx_T_47, UInt<4>(0h9))
node _idx_T_49 = asUInt(_idx_T_48)
node idx_9 = rem(_idx_T_49, UInt<6>(0h20))
node _T_638 = eq(UInt<1>(0h0), idx_9)
when _T_638 :
node _T_639 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8.io.enq.bits, _T_639
node _T_640 = eq(UInt<1>(0h1), idx_9)
when _T_640 :
node _T_641 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_1.io.enq.bits, _T_641
node _T_642 = eq(UInt<2>(0h2), idx_9)
when _T_642 :
node _T_643 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_2.io.enq.bits, _T_643
node _T_644 = eq(UInt<2>(0h3), idx_9)
when _T_644 :
node _T_645 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_3.io.enq.bits, _T_645
node _T_646 = eq(UInt<3>(0h4), idx_9)
when _T_646 :
node _T_647 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_4.io.enq.bits, _T_647
node _T_648 = eq(UInt<3>(0h5), idx_9)
when _T_648 :
node _T_649 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_5.io.enq.bits, _T_649
node _T_650 = eq(UInt<3>(0h6), idx_9)
when _T_650 :
node _T_651 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_6.io.enq.bits, _T_651
node _T_652 = eq(UInt<3>(0h7), idx_9)
when _T_652 :
node _T_653 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_7.io.enq.bits, _T_653
node _T_654 = eq(UInt<4>(0h8), idx_9)
when _T_654 :
node _T_655 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_8.io.enq.bits, _T_655
node _T_656 = eq(UInt<4>(0h9), idx_9)
when _T_656 :
node _T_657 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_9.io.enq.bits, _T_657
node _T_658 = eq(UInt<4>(0ha), idx_9)
when _T_658 :
node _T_659 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_10.io.enq.bits, _T_659
node _T_660 = eq(UInt<4>(0hb), idx_9)
when _T_660 :
node _T_661 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_11.io.enq.bits, _T_661
node _T_662 = eq(UInt<4>(0hc), idx_9)
when _T_662 :
node _T_663 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_12.io.enq.bits, _T_663
node _T_664 = eq(UInt<4>(0hd), idx_9)
when _T_664 :
node _T_665 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_13.io.enq.bits, _T_665
node _T_666 = eq(UInt<4>(0he), idx_9)
when _T_666 :
node _T_667 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_14.io.enq.bits, _T_667
node _T_668 = eq(UInt<4>(0hf), idx_9)
when _T_668 :
node _T_669 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_15.io.enq.bits, _T_669
node _T_670 = eq(UInt<5>(0h10), idx_9)
when _T_670 :
node _T_671 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_16.io.enq.bits, _T_671
node _T_672 = eq(UInt<5>(0h11), idx_9)
when _T_672 :
node _T_673 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_17.io.enq.bits, _T_673
node _T_674 = eq(UInt<5>(0h12), idx_9)
when _T_674 :
node _T_675 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_18.io.enq.bits, _T_675
node _T_676 = eq(UInt<5>(0h13), idx_9)
when _T_676 :
node _T_677 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_19.io.enq.bits, _T_677
node _T_678 = eq(UInt<5>(0h14), idx_9)
when _T_678 :
node _T_679 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_20.io.enq.bits, _T_679
node _T_680 = eq(UInt<5>(0h15), idx_9)
when _T_680 :
node _T_681 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_21.io.enq.bits, _T_681
node _T_682 = eq(UInt<5>(0h16), idx_9)
when _T_682 :
node _T_683 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_22.io.enq.bits, _T_683
node _T_684 = eq(UInt<5>(0h17), idx_9)
when _T_684 :
node _T_685 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_23.io.enq.bits, _T_685
node _T_686 = eq(UInt<5>(0h18), idx_9)
when _T_686 :
node _T_687 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_24.io.enq.bits, _T_687
node _T_688 = eq(UInt<5>(0h19), idx_9)
when _T_688 :
node _T_689 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_25.io.enq.bits, _T_689
node _T_690 = eq(UInt<5>(0h1a), idx_9)
when _T_690 :
node _T_691 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_26.io.enq.bits, _T_691
node _T_692 = eq(UInt<5>(0h1b), idx_9)
when _T_692 :
node _T_693 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_27.io.enq.bits, _T_693
node _T_694 = eq(UInt<5>(0h1c), idx_9)
when _T_694 :
node _T_695 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_28.io.enq.bits, _T_695
node _T_696 = eq(UInt<5>(0h1d), idx_9)
when _T_696 :
node _T_697 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_29.io.enq.bits, _T_697
node _T_698 = eq(UInt<5>(0h1e), idx_9)
when _T_698 :
node _T_699 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_30.io.enq.bits, _T_699
node _T_700 = eq(UInt<5>(0h1f), idx_9)
when _T_700 :
node _T_701 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_31.io.enq.bits, _T_701
node _idx_T_50 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_51 = sub(_idx_T_50, write_start_index)
node _idx_T_52 = asUInt(_idx_T_51)
node _idx_T_53 = sub(_idx_T_52, UInt<4>(0ha))
node _idx_T_54 = asUInt(_idx_T_53)
node idx_10 = rem(_idx_T_54, UInt<6>(0h20))
node _T_702 = eq(UInt<1>(0h0), idx_10)
when _T_702 :
node _T_703 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8.io.enq.bits, _T_703
node _T_704 = eq(UInt<1>(0h1), idx_10)
when _T_704 :
node _T_705 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_1.io.enq.bits, _T_705
node _T_706 = eq(UInt<2>(0h2), idx_10)
when _T_706 :
node _T_707 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_2.io.enq.bits, _T_707
node _T_708 = eq(UInt<2>(0h3), idx_10)
when _T_708 :
node _T_709 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_3.io.enq.bits, _T_709
node _T_710 = eq(UInt<3>(0h4), idx_10)
when _T_710 :
node _T_711 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_4.io.enq.bits, _T_711
node _T_712 = eq(UInt<3>(0h5), idx_10)
when _T_712 :
node _T_713 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_5.io.enq.bits, _T_713
node _T_714 = eq(UInt<3>(0h6), idx_10)
when _T_714 :
node _T_715 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_6.io.enq.bits, _T_715
node _T_716 = eq(UInt<3>(0h7), idx_10)
when _T_716 :
node _T_717 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_7.io.enq.bits, _T_717
node _T_718 = eq(UInt<4>(0h8), idx_10)
when _T_718 :
node _T_719 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_8.io.enq.bits, _T_719
node _T_720 = eq(UInt<4>(0h9), idx_10)
when _T_720 :
node _T_721 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_9.io.enq.bits, _T_721
node _T_722 = eq(UInt<4>(0ha), idx_10)
when _T_722 :
node _T_723 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_10.io.enq.bits, _T_723
node _T_724 = eq(UInt<4>(0hb), idx_10)
when _T_724 :
node _T_725 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_11.io.enq.bits, _T_725
node _T_726 = eq(UInt<4>(0hc), idx_10)
when _T_726 :
node _T_727 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_12.io.enq.bits, _T_727
node _T_728 = eq(UInt<4>(0hd), idx_10)
when _T_728 :
node _T_729 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_13.io.enq.bits, _T_729
node _T_730 = eq(UInt<4>(0he), idx_10)
when _T_730 :
node _T_731 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_14.io.enq.bits, _T_731
node _T_732 = eq(UInt<4>(0hf), idx_10)
when _T_732 :
node _T_733 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_15.io.enq.bits, _T_733
node _T_734 = eq(UInt<5>(0h10), idx_10)
when _T_734 :
node _T_735 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_16.io.enq.bits, _T_735
node _T_736 = eq(UInt<5>(0h11), idx_10)
when _T_736 :
node _T_737 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_17.io.enq.bits, _T_737
node _T_738 = eq(UInt<5>(0h12), idx_10)
when _T_738 :
node _T_739 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_18.io.enq.bits, _T_739
node _T_740 = eq(UInt<5>(0h13), idx_10)
when _T_740 :
node _T_741 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_19.io.enq.bits, _T_741
node _T_742 = eq(UInt<5>(0h14), idx_10)
when _T_742 :
node _T_743 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_20.io.enq.bits, _T_743
node _T_744 = eq(UInt<5>(0h15), idx_10)
when _T_744 :
node _T_745 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_21.io.enq.bits, _T_745
node _T_746 = eq(UInt<5>(0h16), idx_10)
when _T_746 :
node _T_747 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_22.io.enq.bits, _T_747
node _T_748 = eq(UInt<5>(0h17), idx_10)
when _T_748 :
node _T_749 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_23.io.enq.bits, _T_749
node _T_750 = eq(UInt<5>(0h18), idx_10)
when _T_750 :
node _T_751 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_24.io.enq.bits, _T_751
node _T_752 = eq(UInt<5>(0h19), idx_10)
when _T_752 :
node _T_753 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_25.io.enq.bits, _T_753
node _T_754 = eq(UInt<5>(0h1a), idx_10)
when _T_754 :
node _T_755 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_26.io.enq.bits, _T_755
node _T_756 = eq(UInt<5>(0h1b), idx_10)
when _T_756 :
node _T_757 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_27.io.enq.bits, _T_757
node _T_758 = eq(UInt<5>(0h1c), idx_10)
when _T_758 :
node _T_759 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_28.io.enq.bits, _T_759
node _T_760 = eq(UInt<5>(0h1d), idx_10)
when _T_760 :
node _T_761 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_29.io.enq.bits, _T_761
node _T_762 = eq(UInt<5>(0h1e), idx_10)
when _T_762 :
node _T_763 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_30.io.enq.bits, _T_763
node _T_764 = eq(UInt<5>(0h1f), idx_10)
when _T_764 :
node _T_765 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_31.io.enq.bits, _T_765
node _idx_T_55 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_56 = sub(_idx_T_55, write_start_index)
node _idx_T_57 = asUInt(_idx_T_56)
node _idx_T_58 = sub(_idx_T_57, UInt<4>(0hb))
node _idx_T_59 = asUInt(_idx_T_58)
node idx_11 = rem(_idx_T_59, UInt<6>(0h20))
node _T_766 = eq(UInt<1>(0h0), idx_11)
when _T_766 :
node _T_767 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8.io.enq.bits, _T_767
node _T_768 = eq(UInt<1>(0h1), idx_11)
when _T_768 :
node _T_769 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_1.io.enq.bits, _T_769
node _T_770 = eq(UInt<2>(0h2), idx_11)
when _T_770 :
node _T_771 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_2.io.enq.bits, _T_771
node _T_772 = eq(UInt<2>(0h3), idx_11)
when _T_772 :
node _T_773 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_3.io.enq.bits, _T_773
node _T_774 = eq(UInt<3>(0h4), idx_11)
when _T_774 :
node _T_775 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_4.io.enq.bits, _T_775
node _T_776 = eq(UInt<3>(0h5), idx_11)
when _T_776 :
node _T_777 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_5.io.enq.bits, _T_777
node _T_778 = eq(UInt<3>(0h6), idx_11)
when _T_778 :
node _T_779 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_6.io.enq.bits, _T_779
node _T_780 = eq(UInt<3>(0h7), idx_11)
when _T_780 :
node _T_781 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_7.io.enq.bits, _T_781
node _T_782 = eq(UInt<4>(0h8), idx_11)
when _T_782 :
node _T_783 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_8.io.enq.bits, _T_783
node _T_784 = eq(UInt<4>(0h9), idx_11)
when _T_784 :
node _T_785 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_9.io.enq.bits, _T_785
node _T_786 = eq(UInt<4>(0ha), idx_11)
when _T_786 :
node _T_787 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_10.io.enq.bits, _T_787
node _T_788 = eq(UInt<4>(0hb), idx_11)
when _T_788 :
node _T_789 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_11.io.enq.bits, _T_789
node _T_790 = eq(UInt<4>(0hc), idx_11)
when _T_790 :
node _T_791 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_12.io.enq.bits, _T_791
node _T_792 = eq(UInt<4>(0hd), idx_11)
when _T_792 :
node _T_793 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_13.io.enq.bits, _T_793
node _T_794 = eq(UInt<4>(0he), idx_11)
when _T_794 :
node _T_795 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_14.io.enq.bits, _T_795
node _T_796 = eq(UInt<4>(0hf), idx_11)
when _T_796 :
node _T_797 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_15.io.enq.bits, _T_797
node _T_798 = eq(UInt<5>(0h10), idx_11)
when _T_798 :
node _T_799 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_16.io.enq.bits, _T_799
node _T_800 = eq(UInt<5>(0h11), idx_11)
when _T_800 :
node _T_801 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_17.io.enq.bits, _T_801
node _T_802 = eq(UInt<5>(0h12), idx_11)
when _T_802 :
node _T_803 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_18.io.enq.bits, _T_803
node _T_804 = eq(UInt<5>(0h13), idx_11)
when _T_804 :
node _T_805 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_19.io.enq.bits, _T_805
node _T_806 = eq(UInt<5>(0h14), idx_11)
when _T_806 :
node _T_807 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_20.io.enq.bits, _T_807
node _T_808 = eq(UInt<5>(0h15), idx_11)
when _T_808 :
node _T_809 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_21.io.enq.bits, _T_809
node _T_810 = eq(UInt<5>(0h16), idx_11)
when _T_810 :
node _T_811 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_22.io.enq.bits, _T_811
node _T_812 = eq(UInt<5>(0h17), idx_11)
when _T_812 :
node _T_813 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_23.io.enq.bits, _T_813
node _T_814 = eq(UInt<5>(0h18), idx_11)
when _T_814 :
node _T_815 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_24.io.enq.bits, _T_815
node _T_816 = eq(UInt<5>(0h19), idx_11)
when _T_816 :
node _T_817 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_25.io.enq.bits, _T_817
node _T_818 = eq(UInt<5>(0h1a), idx_11)
when _T_818 :
node _T_819 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_26.io.enq.bits, _T_819
node _T_820 = eq(UInt<5>(0h1b), idx_11)
when _T_820 :
node _T_821 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_27.io.enq.bits, _T_821
node _T_822 = eq(UInt<5>(0h1c), idx_11)
when _T_822 :
node _T_823 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_28.io.enq.bits, _T_823
node _T_824 = eq(UInt<5>(0h1d), idx_11)
when _T_824 :
node _T_825 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_29.io.enq.bits, _T_825
node _T_826 = eq(UInt<5>(0h1e), idx_11)
when _T_826 :
node _T_827 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_30.io.enq.bits, _T_827
node _T_828 = eq(UInt<5>(0h1f), idx_11)
when _T_828 :
node _T_829 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_31.io.enq.bits, _T_829
node _idx_T_60 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_61 = sub(_idx_T_60, write_start_index)
node _idx_T_62 = asUInt(_idx_T_61)
node _idx_T_63 = sub(_idx_T_62, UInt<4>(0hc))
node _idx_T_64 = asUInt(_idx_T_63)
node idx_12 = rem(_idx_T_64, UInt<6>(0h20))
node _T_830 = eq(UInt<1>(0h0), idx_12)
when _T_830 :
node _T_831 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8.io.enq.bits, _T_831
node _T_832 = eq(UInt<1>(0h1), idx_12)
when _T_832 :
node _T_833 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_1.io.enq.bits, _T_833
node _T_834 = eq(UInt<2>(0h2), idx_12)
when _T_834 :
node _T_835 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_2.io.enq.bits, _T_835
node _T_836 = eq(UInt<2>(0h3), idx_12)
when _T_836 :
node _T_837 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_3.io.enq.bits, _T_837
node _T_838 = eq(UInt<3>(0h4), idx_12)
when _T_838 :
node _T_839 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_4.io.enq.bits, _T_839
node _T_840 = eq(UInt<3>(0h5), idx_12)
when _T_840 :
node _T_841 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_5.io.enq.bits, _T_841
node _T_842 = eq(UInt<3>(0h6), idx_12)
when _T_842 :
node _T_843 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_6.io.enq.bits, _T_843
node _T_844 = eq(UInt<3>(0h7), idx_12)
when _T_844 :
node _T_845 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_7.io.enq.bits, _T_845
node _T_846 = eq(UInt<4>(0h8), idx_12)
when _T_846 :
node _T_847 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_8.io.enq.bits, _T_847
node _T_848 = eq(UInt<4>(0h9), idx_12)
when _T_848 :
node _T_849 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_9.io.enq.bits, _T_849
node _T_850 = eq(UInt<4>(0ha), idx_12)
when _T_850 :
node _T_851 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_10.io.enq.bits, _T_851
node _T_852 = eq(UInt<4>(0hb), idx_12)
when _T_852 :
node _T_853 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_11.io.enq.bits, _T_853
node _T_854 = eq(UInt<4>(0hc), idx_12)
when _T_854 :
node _T_855 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_12.io.enq.bits, _T_855
node _T_856 = eq(UInt<4>(0hd), idx_12)
when _T_856 :
node _T_857 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_13.io.enq.bits, _T_857
node _T_858 = eq(UInt<4>(0he), idx_12)
when _T_858 :
node _T_859 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_14.io.enq.bits, _T_859
node _T_860 = eq(UInt<4>(0hf), idx_12)
when _T_860 :
node _T_861 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_15.io.enq.bits, _T_861
node _T_862 = eq(UInt<5>(0h10), idx_12)
when _T_862 :
node _T_863 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_16.io.enq.bits, _T_863
node _T_864 = eq(UInt<5>(0h11), idx_12)
when _T_864 :
node _T_865 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_17.io.enq.bits, _T_865
node _T_866 = eq(UInt<5>(0h12), idx_12)
when _T_866 :
node _T_867 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_18.io.enq.bits, _T_867
node _T_868 = eq(UInt<5>(0h13), idx_12)
when _T_868 :
node _T_869 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_19.io.enq.bits, _T_869
node _T_870 = eq(UInt<5>(0h14), idx_12)
when _T_870 :
node _T_871 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_20.io.enq.bits, _T_871
node _T_872 = eq(UInt<5>(0h15), idx_12)
when _T_872 :
node _T_873 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_21.io.enq.bits, _T_873
node _T_874 = eq(UInt<5>(0h16), idx_12)
when _T_874 :
node _T_875 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_22.io.enq.bits, _T_875
node _T_876 = eq(UInt<5>(0h17), idx_12)
when _T_876 :
node _T_877 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_23.io.enq.bits, _T_877
node _T_878 = eq(UInt<5>(0h18), idx_12)
when _T_878 :
node _T_879 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_24.io.enq.bits, _T_879
node _T_880 = eq(UInt<5>(0h19), idx_12)
when _T_880 :
node _T_881 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_25.io.enq.bits, _T_881
node _T_882 = eq(UInt<5>(0h1a), idx_12)
when _T_882 :
node _T_883 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_26.io.enq.bits, _T_883
node _T_884 = eq(UInt<5>(0h1b), idx_12)
when _T_884 :
node _T_885 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_27.io.enq.bits, _T_885
node _T_886 = eq(UInt<5>(0h1c), idx_12)
when _T_886 :
node _T_887 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_28.io.enq.bits, _T_887
node _T_888 = eq(UInt<5>(0h1d), idx_12)
when _T_888 :
node _T_889 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_29.io.enq.bits, _T_889
node _T_890 = eq(UInt<5>(0h1e), idx_12)
when _T_890 :
node _T_891 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_30.io.enq.bits, _T_891
node _T_892 = eq(UInt<5>(0h1f), idx_12)
when _T_892 :
node _T_893 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_31.io.enq.bits, _T_893
node _idx_T_65 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_66 = sub(_idx_T_65, write_start_index)
node _idx_T_67 = asUInt(_idx_T_66)
node _idx_T_68 = sub(_idx_T_67, UInt<4>(0hd))
node _idx_T_69 = asUInt(_idx_T_68)
node idx_13 = rem(_idx_T_69, UInt<6>(0h20))
node _T_894 = eq(UInt<1>(0h0), idx_13)
when _T_894 :
node _T_895 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8.io.enq.bits, _T_895
node _T_896 = eq(UInt<1>(0h1), idx_13)
when _T_896 :
node _T_897 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_1.io.enq.bits, _T_897
node _T_898 = eq(UInt<2>(0h2), idx_13)
when _T_898 :
node _T_899 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_2.io.enq.bits, _T_899
node _T_900 = eq(UInt<2>(0h3), idx_13)
when _T_900 :
node _T_901 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_3.io.enq.bits, _T_901
node _T_902 = eq(UInt<3>(0h4), idx_13)
when _T_902 :
node _T_903 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_4.io.enq.bits, _T_903
node _T_904 = eq(UInt<3>(0h5), idx_13)
when _T_904 :
node _T_905 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_5.io.enq.bits, _T_905
node _T_906 = eq(UInt<3>(0h6), idx_13)
when _T_906 :
node _T_907 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_6.io.enq.bits, _T_907
node _T_908 = eq(UInt<3>(0h7), idx_13)
when _T_908 :
node _T_909 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_7.io.enq.bits, _T_909
node _T_910 = eq(UInt<4>(0h8), idx_13)
when _T_910 :
node _T_911 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_8.io.enq.bits, _T_911
node _T_912 = eq(UInt<4>(0h9), idx_13)
when _T_912 :
node _T_913 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_9.io.enq.bits, _T_913
node _T_914 = eq(UInt<4>(0ha), idx_13)
when _T_914 :
node _T_915 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_10.io.enq.bits, _T_915
node _T_916 = eq(UInt<4>(0hb), idx_13)
when _T_916 :
node _T_917 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_11.io.enq.bits, _T_917
node _T_918 = eq(UInt<4>(0hc), idx_13)
when _T_918 :
node _T_919 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_12.io.enq.bits, _T_919
node _T_920 = eq(UInt<4>(0hd), idx_13)
when _T_920 :
node _T_921 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_13.io.enq.bits, _T_921
node _T_922 = eq(UInt<4>(0he), idx_13)
when _T_922 :
node _T_923 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_14.io.enq.bits, _T_923
node _T_924 = eq(UInt<4>(0hf), idx_13)
when _T_924 :
node _T_925 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_15.io.enq.bits, _T_925
node _T_926 = eq(UInt<5>(0h10), idx_13)
when _T_926 :
node _T_927 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_16.io.enq.bits, _T_927
node _T_928 = eq(UInt<5>(0h11), idx_13)
when _T_928 :
node _T_929 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_17.io.enq.bits, _T_929
node _T_930 = eq(UInt<5>(0h12), idx_13)
when _T_930 :
node _T_931 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_18.io.enq.bits, _T_931
node _T_932 = eq(UInt<5>(0h13), idx_13)
when _T_932 :
node _T_933 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_19.io.enq.bits, _T_933
node _T_934 = eq(UInt<5>(0h14), idx_13)
when _T_934 :
node _T_935 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_20.io.enq.bits, _T_935
node _T_936 = eq(UInt<5>(0h15), idx_13)
when _T_936 :
node _T_937 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_21.io.enq.bits, _T_937
node _T_938 = eq(UInt<5>(0h16), idx_13)
when _T_938 :
node _T_939 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_22.io.enq.bits, _T_939
node _T_940 = eq(UInt<5>(0h17), idx_13)
when _T_940 :
node _T_941 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_23.io.enq.bits, _T_941
node _T_942 = eq(UInt<5>(0h18), idx_13)
when _T_942 :
node _T_943 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_24.io.enq.bits, _T_943
node _T_944 = eq(UInt<5>(0h19), idx_13)
when _T_944 :
node _T_945 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_25.io.enq.bits, _T_945
node _T_946 = eq(UInt<5>(0h1a), idx_13)
when _T_946 :
node _T_947 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_26.io.enq.bits, _T_947
node _T_948 = eq(UInt<5>(0h1b), idx_13)
when _T_948 :
node _T_949 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_27.io.enq.bits, _T_949
node _T_950 = eq(UInt<5>(0h1c), idx_13)
when _T_950 :
node _T_951 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_28.io.enq.bits, _T_951
node _T_952 = eq(UInt<5>(0h1d), idx_13)
when _T_952 :
node _T_953 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_29.io.enq.bits, _T_953
node _T_954 = eq(UInt<5>(0h1e), idx_13)
when _T_954 :
node _T_955 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_30.io.enq.bits, _T_955
node _T_956 = eq(UInt<5>(0h1f), idx_13)
when _T_956 :
node _T_957 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_31.io.enq.bits, _T_957
node _idx_T_70 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_71 = sub(_idx_T_70, write_start_index)
node _idx_T_72 = asUInt(_idx_T_71)
node _idx_T_73 = sub(_idx_T_72, UInt<4>(0he))
node _idx_T_74 = asUInt(_idx_T_73)
node idx_14 = rem(_idx_T_74, UInt<6>(0h20))
node _T_958 = eq(UInt<1>(0h0), idx_14)
when _T_958 :
node _T_959 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8.io.enq.bits, _T_959
node _T_960 = eq(UInt<1>(0h1), idx_14)
when _T_960 :
node _T_961 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_1.io.enq.bits, _T_961
node _T_962 = eq(UInt<2>(0h2), idx_14)
when _T_962 :
node _T_963 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_2.io.enq.bits, _T_963
node _T_964 = eq(UInt<2>(0h3), idx_14)
when _T_964 :
node _T_965 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_3.io.enq.bits, _T_965
node _T_966 = eq(UInt<3>(0h4), idx_14)
when _T_966 :
node _T_967 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_4.io.enq.bits, _T_967
node _T_968 = eq(UInt<3>(0h5), idx_14)
when _T_968 :
node _T_969 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_5.io.enq.bits, _T_969
node _T_970 = eq(UInt<3>(0h6), idx_14)
when _T_970 :
node _T_971 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_6.io.enq.bits, _T_971
node _T_972 = eq(UInt<3>(0h7), idx_14)
when _T_972 :
node _T_973 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_7.io.enq.bits, _T_973
node _T_974 = eq(UInt<4>(0h8), idx_14)
when _T_974 :
node _T_975 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_8.io.enq.bits, _T_975
node _T_976 = eq(UInt<4>(0h9), idx_14)
when _T_976 :
node _T_977 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_9.io.enq.bits, _T_977
node _T_978 = eq(UInt<4>(0ha), idx_14)
when _T_978 :
node _T_979 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_10.io.enq.bits, _T_979
node _T_980 = eq(UInt<4>(0hb), idx_14)
when _T_980 :
node _T_981 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_11.io.enq.bits, _T_981
node _T_982 = eq(UInt<4>(0hc), idx_14)
when _T_982 :
node _T_983 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_12.io.enq.bits, _T_983
node _T_984 = eq(UInt<4>(0hd), idx_14)
when _T_984 :
node _T_985 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_13.io.enq.bits, _T_985
node _T_986 = eq(UInt<4>(0he), idx_14)
when _T_986 :
node _T_987 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_14.io.enq.bits, _T_987
node _T_988 = eq(UInt<4>(0hf), idx_14)
when _T_988 :
node _T_989 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_15.io.enq.bits, _T_989
node _T_990 = eq(UInt<5>(0h10), idx_14)
when _T_990 :
node _T_991 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_16.io.enq.bits, _T_991
node _T_992 = eq(UInt<5>(0h11), idx_14)
when _T_992 :
node _T_993 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_17.io.enq.bits, _T_993
node _T_994 = eq(UInt<5>(0h12), idx_14)
when _T_994 :
node _T_995 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_18.io.enq.bits, _T_995
node _T_996 = eq(UInt<5>(0h13), idx_14)
when _T_996 :
node _T_997 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_19.io.enq.bits, _T_997
node _T_998 = eq(UInt<5>(0h14), idx_14)
when _T_998 :
node _T_999 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_20.io.enq.bits, _T_999
node _T_1000 = eq(UInt<5>(0h15), idx_14)
when _T_1000 :
node _T_1001 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_21.io.enq.bits, _T_1001
node _T_1002 = eq(UInt<5>(0h16), idx_14)
when _T_1002 :
node _T_1003 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_22.io.enq.bits, _T_1003
node _T_1004 = eq(UInt<5>(0h17), idx_14)
when _T_1004 :
node _T_1005 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_23.io.enq.bits, _T_1005
node _T_1006 = eq(UInt<5>(0h18), idx_14)
when _T_1006 :
node _T_1007 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_24.io.enq.bits, _T_1007
node _T_1008 = eq(UInt<5>(0h19), idx_14)
when _T_1008 :
node _T_1009 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_25.io.enq.bits, _T_1009
node _T_1010 = eq(UInt<5>(0h1a), idx_14)
when _T_1010 :
node _T_1011 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_26.io.enq.bits, _T_1011
node _T_1012 = eq(UInt<5>(0h1b), idx_14)
when _T_1012 :
node _T_1013 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_27.io.enq.bits, _T_1013
node _T_1014 = eq(UInt<5>(0h1c), idx_14)
when _T_1014 :
node _T_1015 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_28.io.enq.bits, _T_1015
node _T_1016 = eq(UInt<5>(0h1d), idx_14)
when _T_1016 :
node _T_1017 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_29.io.enq.bits, _T_1017
node _T_1018 = eq(UInt<5>(0h1e), idx_14)
when _T_1018 :
node _T_1019 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_30.io.enq.bits, _T_1019
node _T_1020 = eq(UInt<5>(0h1f), idx_14)
when _T_1020 :
node _T_1021 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_31.io.enq.bits, _T_1021
node _idx_T_75 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_76 = sub(_idx_T_75, write_start_index)
node _idx_T_77 = asUInt(_idx_T_76)
node _idx_T_78 = sub(_idx_T_77, UInt<4>(0hf))
node _idx_T_79 = asUInt(_idx_T_78)
node idx_15 = rem(_idx_T_79, UInt<6>(0h20))
node _T_1022 = eq(UInt<1>(0h0), idx_15)
when _T_1022 :
node _T_1023 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8.io.enq.bits, _T_1023
node _T_1024 = eq(UInt<1>(0h1), idx_15)
when _T_1024 :
node _T_1025 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_1.io.enq.bits, _T_1025
node _T_1026 = eq(UInt<2>(0h2), idx_15)
when _T_1026 :
node _T_1027 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_2.io.enq.bits, _T_1027
node _T_1028 = eq(UInt<2>(0h3), idx_15)
when _T_1028 :
node _T_1029 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_3.io.enq.bits, _T_1029
node _T_1030 = eq(UInt<3>(0h4), idx_15)
when _T_1030 :
node _T_1031 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_4.io.enq.bits, _T_1031
node _T_1032 = eq(UInt<3>(0h5), idx_15)
when _T_1032 :
node _T_1033 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_5.io.enq.bits, _T_1033
node _T_1034 = eq(UInt<3>(0h6), idx_15)
when _T_1034 :
node _T_1035 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_6.io.enq.bits, _T_1035
node _T_1036 = eq(UInt<3>(0h7), idx_15)
when _T_1036 :
node _T_1037 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_7.io.enq.bits, _T_1037
node _T_1038 = eq(UInt<4>(0h8), idx_15)
when _T_1038 :
node _T_1039 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_8.io.enq.bits, _T_1039
node _T_1040 = eq(UInt<4>(0h9), idx_15)
when _T_1040 :
node _T_1041 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_9.io.enq.bits, _T_1041
node _T_1042 = eq(UInt<4>(0ha), idx_15)
when _T_1042 :
node _T_1043 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_10.io.enq.bits, _T_1043
node _T_1044 = eq(UInt<4>(0hb), idx_15)
when _T_1044 :
node _T_1045 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_11.io.enq.bits, _T_1045
node _T_1046 = eq(UInt<4>(0hc), idx_15)
when _T_1046 :
node _T_1047 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_12.io.enq.bits, _T_1047
node _T_1048 = eq(UInt<4>(0hd), idx_15)
when _T_1048 :
node _T_1049 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_13.io.enq.bits, _T_1049
node _T_1050 = eq(UInt<4>(0he), idx_15)
when _T_1050 :
node _T_1051 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_14.io.enq.bits, _T_1051
node _T_1052 = eq(UInt<4>(0hf), idx_15)
when _T_1052 :
node _T_1053 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_15.io.enq.bits, _T_1053
node _T_1054 = eq(UInt<5>(0h10), idx_15)
when _T_1054 :
node _T_1055 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_16.io.enq.bits, _T_1055
node _T_1056 = eq(UInt<5>(0h11), idx_15)
when _T_1056 :
node _T_1057 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_17.io.enq.bits, _T_1057
node _T_1058 = eq(UInt<5>(0h12), idx_15)
when _T_1058 :
node _T_1059 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_18.io.enq.bits, _T_1059
node _T_1060 = eq(UInt<5>(0h13), idx_15)
when _T_1060 :
node _T_1061 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_19.io.enq.bits, _T_1061
node _T_1062 = eq(UInt<5>(0h14), idx_15)
when _T_1062 :
node _T_1063 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_20.io.enq.bits, _T_1063
node _T_1064 = eq(UInt<5>(0h15), idx_15)
when _T_1064 :
node _T_1065 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_21.io.enq.bits, _T_1065
node _T_1066 = eq(UInt<5>(0h16), idx_15)
when _T_1066 :
node _T_1067 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_22.io.enq.bits, _T_1067
node _T_1068 = eq(UInt<5>(0h17), idx_15)
when _T_1068 :
node _T_1069 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_23.io.enq.bits, _T_1069
node _T_1070 = eq(UInt<5>(0h18), idx_15)
when _T_1070 :
node _T_1071 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_24.io.enq.bits, _T_1071
node _T_1072 = eq(UInt<5>(0h19), idx_15)
when _T_1072 :
node _T_1073 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_25.io.enq.bits, _T_1073
node _T_1074 = eq(UInt<5>(0h1a), idx_15)
when _T_1074 :
node _T_1075 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_26.io.enq.bits, _T_1075
node _T_1076 = eq(UInt<5>(0h1b), idx_15)
when _T_1076 :
node _T_1077 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_27.io.enq.bits, _T_1077
node _T_1078 = eq(UInt<5>(0h1c), idx_15)
when _T_1078 :
node _T_1079 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_28.io.enq.bits, _T_1079
node _T_1080 = eq(UInt<5>(0h1d), idx_15)
when _T_1080 :
node _T_1081 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_29.io.enq.bits, _T_1081
node _T_1082 = eq(UInt<5>(0h1e), idx_15)
when _T_1082 :
node _T_1083 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_30.io.enq.bits, _T_1083
node _T_1084 = eq(UInt<5>(0h1f), idx_15)
when _T_1084 :
node _T_1085 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_31.io.enq.bits, _T_1085
node _idx_T_80 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_81 = sub(_idx_T_80, write_start_index)
node _idx_T_82 = asUInt(_idx_T_81)
node _idx_T_83 = sub(_idx_T_82, UInt<5>(0h10))
node _idx_T_84 = asUInt(_idx_T_83)
node idx_16 = rem(_idx_T_84, UInt<6>(0h20))
node _T_1086 = eq(UInt<1>(0h0), idx_16)
when _T_1086 :
node _T_1087 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8.io.enq.bits, _T_1087
node _T_1088 = eq(UInt<1>(0h1), idx_16)
when _T_1088 :
node _T_1089 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_1.io.enq.bits, _T_1089
node _T_1090 = eq(UInt<2>(0h2), idx_16)
when _T_1090 :
node _T_1091 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_2.io.enq.bits, _T_1091
node _T_1092 = eq(UInt<2>(0h3), idx_16)
when _T_1092 :
node _T_1093 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_3.io.enq.bits, _T_1093
node _T_1094 = eq(UInt<3>(0h4), idx_16)
when _T_1094 :
node _T_1095 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_4.io.enq.bits, _T_1095
node _T_1096 = eq(UInt<3>(0h5), idx_16)
when _T_1096 :
node _T_1097 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_5.io.enq.bits, _T_1097
node _T_1098 = eq(UInt<3>(0h6), idx_16)
when _T_1098 :
node _T_1099 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_6.io.enq.bits, _T_1099
node _T_1100 = eq(UInt<3>(0h7), idx_16)
when _T_1100 :
node _T_1101 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_7.io.enq.bits, _T_1101
node _T_1102 = eq(UInt<4>(0h8), idx_16)
when _T_1102 :
node _T_1103 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_8.io.enq.bits, _T_1103
node _T_1104 = eq(UInt<4>(0h9), idx_16)
when _T_1104 :
node _T_1105 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_9.io.enq.bits, _T_1105
node _T_1106 = eq(UInt<4>(0ha), idx_16)
when _T_1106 :
node _T_1107 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_10.io.enq.bits, _T_1107
node _T_1108 = eq(UInt<4>(0hb), idx_16)
when _T_1108 :
node _T_1109 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_11.io.enq.bits, _T_1109
node _T_1110 = eq(UInt<4>(0hc), idx_16)
when _T_1110 :
node _T_1111 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_12.io.enq.bits, _T_1111
node _T_1112 = eq(UInt<4>(0hd), idx_16)
when _T_1112 :
node _T_1113 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_13.io.enq.bits, _T_1113
node _T_1114 = eq(UInt<4>(0he), idx_16)
when _T_1114 :
node _T_1115 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_14.io.enq.bits, _T_1115
node _T_1116 = eq(UInt<4>(0hf), idx_16)
when _T_1116 :
node _T_1117 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_15.io.enq.bits, _T_1117
node _T_1118 = eq(UInt<5>(0h10), idx_16)
when _T_1118 :
node _T_1119 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_16.io.enq.bits, _T_1119
node _T_1120 = eq(UInt<5>(0h11), idx_16)
when _T_1120 :
node _T_1121 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_17.io.enq.bits, _T_1121
node _T_1122 = eq(UInt<5>(0h12), idx_16)
when _T_1122 :
node _T_1123 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_18.io.enq.bits, _T_1123
node _T_1124 = eq(UInt<5>(0h13), idx_16)
when _T_1124 :
node _T_1125 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_19.io.enq.bits, _T_1125
node _T_1126 = eq(UInt<5>(0h14), idx_16)
when _T_1126 :
node _T_1127 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_20.io.enq.bits, _T_1127
node _T_1128 = eq(UInt<5>(0h15), idx_16)
when _T_1128 :
node _T_1129 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_21.io.enq.bits, _T_1129
node _T_1130 = eq(UInt<5>(0h16), idx_16)
when _T_1130 :
node _T_1131 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_22.io.enq.bits, _T_1131
node _T_1132 = eq(UInt<5>(0h17), idx_16)
when _T_1132 :
node _T_1133 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_23.io.enq.bits, _T_1133
node _T_1134 = eq(UInt<5>(0h18), idx_16)
when _T_1134 :
node _T_1135 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_24.io.enq.bits, _T_1135
node _T_1136 = eq(UInt<5>(0h19), idx_16)
when _T_1136 :
node _T_1137 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_25.io.enq.bits, _T_1137
node _T_1138 = eq(UInt<5>(0h1a), idx_16)
when _T_1138 :
node _T_1139 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_26.io.enq.bits, _T_1139
node _T_1140 = eq(UInt<5>(0h1b), idx_16)
when _T_1140 :
node _T_1141 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_27.io.enq.bits, _T_1141
node _T_1142 = eq(UInt<5>(0h1c), idx_16)
when _T_1142 :
node _T_1143 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_28.io.enq.bits, _T_1143
node _T_1144 = eq(UInt<5>(0h1d), idx_16)
when _T_1144 :
node _T_1145 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_29.io.enq.bits, _T_1145
node _T_1146 = eq(UInt<5>(0h1e), idx_16)
when _T_1146 :
node _T_1147 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_30.io.enq.bits, _T_1147
node _T_1148 = eq(UInt<5>(0h1f), idx_16)
when _T_1148 :
node _T_1149 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_31.io.enq.bits, _T_1149
node _idx_T_85 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_86 = sub(_idx_T_85, write_start_index)
node _idx_T_87 = asUInt(_idx_T_86)
node _idx_T_88 = sub(_idx_T_87, UInt<5>(0h11))
node _idx_T_89 = asUInt(_idx_T_88)
node idx_17 = rem(_idx_T_89, UInt<6>(0h20))
node _T_1150 = eq(UInt<1>(0h0), idx_17)
when _T_1150 :
node _T_1151 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8.io.enq.bits, _T_1151
node _T_1152 = eq(UInt<1>(0h1), idx_17)
when _T_1152 :
node _T_1153 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_1.io.enq.bits, _T_1153
node _T_1154 = eq(UInt<2>(0h2), idx_17)
when _T_1154 :
node _T_1155 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_2.io.enq.bits, _T_1155
node _T_1156 = eq(UInt<2>(0h3), idx_17)
when _T_1156 :
node _T_1157 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_3.io.enq.bits, _T_1157
node _T_1158 = eq(UInt<3>(0h4), idx_17)
when _T_1158 :
node _T_1159 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_4.io.enq.bits, _T_1159
node _T_1160 = eq(UInt<3>(0h5), idx_17)
when _T_1160 :
node _T_1161 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_5.io.enq.bits, _T_1161
node _T_1162 = eq(UInt<3>(0h6), idx_17)
when _T_1162 :
node _T_1163 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_6.io.enq.bits, _T_1163
node _T_1164 = eq(UInt<3>(0h7), idx_17)
when _T_1164 :
node _T_1165 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_7.io.enq.bits, _T_1165
node _T_1166 = eq(UInt<4>(0h8), idx_17)
when _T_1166 :
node _T_1167 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_8.io.enq.bits, _T_1167
node _T_1168 = eq(UInt<4>(0h9), idx_17)
when _T_1168 :
node _T_1169 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_9.io.enq.bits, _T_1169
node _T_1170 = eq(UInt<4>(0ha), idx_17)
when _T_1170 :
node _T_1171 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_10.io.enq.bits, _T_1171
node _T_1172 = eq(UInt<4>(0hb), idx_17)
when _T_1172 :
node _T_1173 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_11.io.enq.bits, _T_1173
node _T_1174 = eq(UInt<4>(0hc), idx_17)
when _T_1174 :
node _T_1175 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_12.io.enq.bits, _T_1175
node _T_1176 = eq(UInt<4>(0hd), idx_17)
when _T_1176 :
node _T_1177 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_13.io.enq.bits, _T_1177
node _T_1178 = eq(UInt<4>(0he), idx_17)
when _T_1178 :
node _T_1179 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_14.io.enq.bits, _T_1179
node _T_1180 = eq(UInt<4>(0hf), idx_17)
when _T_1180 :
node _T_1181 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_15.io.enq.bits, _T_1181
node _T_1182 = eq(UInt<5>(0h10), idx_17)
when _T_1182 :
node _T_1183 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_16.io.enq.bits, _T_1183
node _T_1184 = eq(UInt<5>(0h11), idx_17)
when _T_1184 :
node _T_1185 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_17.io.enq.bits, _T_1185
node _T_1186 = eq(UInt<5>(0h12), idx_17)
when _T_1186 :
node _T_1187 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_18.io.enq.bits, _T_1187
node _T_1188 = eq(UInt<5>(0h13), idx_17)
when _T_1188 :
node _T_1189 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_19.io.enq.bits, _T_1189
node _T_1190 = eq(UInt<5>(0h14), idx_17)
when _T_1190 :
node _T_1191 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_20.io.enq.bits, _T_1191
node _T_1192 = eq(UInt<5>(0h15), idx_17)
when _T_1192 :
node _T_1193 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_21.io.enq.bits, _T_1193
node _T_1194 = eq(UInt<5>(0h16), idx_17)
when _T_1194 :
node _T_1195 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_22.io.enq.bits, _T_1195
node _T_1196 = eq(UInt<5>(0h17), idx_17)
when _T_1196 :
node _T_1197 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_23.io.enq.bits, _T_1197
node _T_1198 = eq(UInt<5>(0h18), idx_17)
when _T_1198 :
node _T_1199 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_24.io.enq.bits, _T_1199
node _T_1200 = eq(UInt<5>(0h19), idx_17)
when _T_1200 :
node _T_1201 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_25.io.enq.bits, _T_1201
node _T_1202 = eq(UInt<5>(0h1a), idx_17)
when _T_1202 :
node _T_1203 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_26.io.enq.bits, _T_1203
node _T_1204 = eq(UInt<5>(0h1b), idx_17)
when _T_1204 :
node _T_1205 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_27.io.enq.bits, _T_1205
node _T_1206 = eq(UInt<5>(0h1c), idx_17)
when _T_1206 :
node _T_1207 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_28.io.enq.bits, _T_1207
node _T_1208 = eq(UInt<5>(0h1d), idx_17)
when _T_1208 :
node _T_1209 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_29.io.enq.bits, _T_1209
node _T_1210 = eq(UInt<5>(0h1e), idx_17)
when _T_1210 :
node _T_1211 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_30.io.enq.bits, _T_1211
node _T_1212 = eq(UInt<5>(0h1f), idx_17)
when _T_1212 :
node _T_1213 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_31.io.enq.bits, _T_1213
node _idx_T_90 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_91 = sub(_idx_T_90, write_start_index)
node _idx_T_92 = asUInt(_idx_T_91)
node _idx_T_93 = sub(_idx_T_92, UInt<5>(0h12))
node _idx_T_94 = asUInt(_idx_T_93)
node idx_18 = rem(_idx_T_94, UInt<6>(0h20))
node _T_1214 = eq(UInt<1>(0h0), idx_18)
when _T_1214 :
node _T_1215 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8.io.enq.bits, _T_1215
node _T_1216 = eq(UInt<1>(0h1), idx_18)
when _T_1216 :
node _T_1217 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_1.io.enq.bits, _T_1217
node _T_1218 = eq(UInt<2>(0h2), idx_18)
when _T_1218 :
node _T_1219 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_2.io.enq.bits, _T_1219
node _T_1220 = eq(UInt<2>(0h3), idx_18)
when _T_1220 :
node _T_1221 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_3.io.enq.bits, _T_1221
node _T_1222 = eq(UInt<3>(0h4), idx_18)
when _T_1222 :
node _T_1223 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_4.io.enq.bits, _T_1223
node _T_1224 = eq(UInt<3>(0h5), idx_18)
when _T_1224 :
node _T_1225 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_5.io.enq.bits, _T_1225
node _T_1226 = eq(UInt<3>(0h6), idx_18)
when _T_1226 :
node _T_1227 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_6.io.enq.bits, _T_1227
node _T_1228 = eq(UInt<3>(0h7), idx_18)
when _T_1228 :
node _T_1229 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_7.io.enq.bits, _T_1229
node _T_1230 = eq(UInt<4>(0h8), idx_18)
when _T_1230 :
node _T_1231 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_8.io.enq.bits, _T_1231
node _T_1232 = eq(UInt<4>(0h9), idx_18)
when _T_1232 :
node _T_1233 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_9.io.enq.bits, _T_1233
node _T_1234 = eq(UInt<4>(0ha), idx_18)
when _T_1234 :
node _T_1235 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_10.io.enq.bits, _T_1235
node _T_1236 = eq(UInt<4>(0hb), idx_18)
when _T_1236 :
node _T_1237 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_11.io.enq.bits, _T_1237
node _T_1238 = eq(UInt<4>(0hc), idx_18)
when _T_1238 :
node _T_1239 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_12.io.enq.bits, _T_1239
node _T_1240 = eq(UInt<4>(0hd), idx_18)
when _T_1240 :
node _T_1241 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_13.io.enq.bits, _T_1241
node _T_1242 = eq(UInt<4>(0he), idx_18)
when _T_1242 :
node _T_1243 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_14.io.enq.bits, _T_1243
node _T_1244 = eq(UInt<4>(0hf), idx_18)
when _T_1244 :
node _T_1245 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_15.io.enq.bits, _T_1245
node _T_1246 = eq(UInt<5>(0h10), idx_18)
when _T_1246 :
node _T_1247 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_16.io.enq.bits, _T_1247
node _T_1248 = eq(UInt<5>(0h11), idx_18)
when _T_1248 :
node _T_1249 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_17.io.enq.bits, _T_1249
node _T_1250 = eq(UInt<5>(0h12), idx_18)
when _T_1250 :
node _T_1251 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_18.io.enq.bits, _T_1251
node _T_1252 = eq(UInt<5>(0h13), idx_18)
when _T_1252 :
node _T_1253 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_19.io.enq.bits, _T_1253
node _T_1254 = eq(UInt<5>(0h14), idx_18)
when _T_1254 :
node _T_1255 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_20.io.enq.bits, _T_1255
node _T_1256 = eq(UInt<5>(0h15), idx_18)
when _T_1256 :
node _T_1257 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_21.io.enq.bits, _T_1257
node _T_1258 = eq(UInt<5>(0h16), idx_18)
when _T_1258 :
node _T_1259 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_22.io.enq.bits, _T_1259
node _T_1260 = eq(UInt<5>(0h17), idx_18)
when _T_1260 :
node _T_1261 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_23.io.enq.bits, _T_1261
node _T_1262 = eq(UInt<5>(0h18), idx_18)
when _T_1262 :
node _T_1263 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_24.io.enq.bits, _T_1263
node _T_1264 = eq(UInt<5>(0h19), idx_18)
when _T_1264 :
node _T_1265 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_25.io.enq.bits, _T_1265
node _T_1266 = eq(UInt<5>(0h1a), idx_18)
when _T_1266 :
node _T_1267 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_26.io.enq.bits, _T_1267
node _T_1268 = eq(UInt<5>(0h1b), idx_18)
when _T_1268 :
node _T_1269 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_27.io.enq.bits, _T_1269
node _T_1270 = eq(UInt<5>(0h1c), idx_18)
when _T_1270 :
node _T_1271 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_28.io.enq.bits, _T_1271
node _T_1272 = eq(UInt<5>(0h1d), idx_18)
when _T_1272 :
node _T_1273 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_29.io.enq.bits, _T_1273
node _T_1274 = eq(UInt<5>(0h1e), idx_18)
when _T_1274 :
node _T_1275 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_30.io.enq.bits, _T_1275
node _T_1276 = eq(UInt<5>(0h1f), idx_18)
when _T_1276 :
node _T_1277 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_31.io.enq.bits, _T_1277
node _idx_T_95 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_96 = sub(_idx_T_95, write_start_index)
node _idx_T_97 = asUInt(_idx_T_96)
node _idx_T_98 = sub(_idx_T_97, UInt<5>(0h13))
node _idx_T_99 = asUInt(_idx_T_98)
node idx_19 = rem(_idx_T_99, UInt<6>(0h20))
node _T_1278 = eq(UInt<1>(0h0), idx_19)
when _T_1278 :
node _T_1279 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8.io.enq.bits, _T_1279
node _T_1280 = eq(UInt<1>(0h1), idx_19)
when _T_1280 :
node _T_1281 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_1.io.enq.bits, _T_1281
node _T_1282 = eq(UInt<2>(0h2), idx_19)
when _T_1282 :
node _T_1283 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_2.io.enq.bits, _T_1283
node _T_1284 = eq(UInt<2>(0h3), idx_19)
when _T_1284 :
node _T_1285 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_3.io.enq.bits, _T_1285
node _T_1286 = eq(UInt<3>(0h4), idx_19)
when _T_1286 :
node _T_1287 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_4.io.enq.bits, _T_1287
node _T_1288 = eq(UInt<3>(0h5), idx_19)
when _T_1288 :
node _T_1289 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_5.io.enq.bits, _T_1289
node _T_1290 = eq(UInt<3>(0h6), idx_19)
when _T_1290 :
node _T_1291 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_6.io.enq.bits, _T_1291
node _T_1292 = eq(UInt<3>(0h7), idx_19)
when _T_1292 :
node _T_1293 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_7.io.enq.bits, _T_1293
node _T_1294 = eq(UInt<4>(0h8), idx_19)
when _T_1294 :
node _T_1295 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_8.io.enq.bits, _T_1295
node _T_1296 = eq(UInt<4>(0h9), idx_19)
when _T_1296 :
node _T_1297 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_9.io.enq.bits, _T_1297
node _T_1298 = eq(UInt<4>(0ha), idx_19)
when _T_1298 :
node _T_1299 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_10.io.enq.bits, _T_1299
node _T_1300 = eq(UInt<4>(0hb), idx_19)
when _T_1300 :
node _T_1301 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_11.io.enq.bits, _T_1301
node _T_1302 = eq(UInt<4>(0hc), idx_19)
when _T_1302 :
node _T_1303 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_12.io.enq.bits, _T_1303
node _T_1304 = eq(UInt<4>(0hd), idx_19)
when _T_1304 :
node _T_1305 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_13.io.enq.bits, _T_1305
node _T_1306 = eq(UInt<4>(0he), idx_19)
when _T_1306 :
node _T_1307 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_14.io.enq.bits, _T_1307
node _T_1308 = eq(UInt<4>(0hf), idx_19)
when _T_1308 :
node _T_1309 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_15.io.enq.bits, _T_1309
node _T_1310 = eq(UInt<5>(0h10), idx_19)
when _T_1310 :
node _T_1311 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_16.io.enq.bits, _T_1311
node _T_1312 = eq(UInt<5>(0h11), idx_19)
when _T_1312 :
node _T_1313 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_17.io.enq.bits, _T_1313
node _T_1314 = eq(UInt<5>(0h12), idx_19)
when _T_1314 :
node _T_1315 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_18.io.enq.bits, _T_1315
node _T_1316 = eq(UInt<5>(0h13), idx_19)
when _T_1316 :
node _T_1317 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_19.io.enq.bits, _T_1317
node _T_1318 = eq(UInt<5>(0h14), idx_19)
when _T_1318 :
node _T_1319 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_20.io.enq.bits, _T_1319
node _T_1320 = eq(UInt<5>(0h15), idx_19)
when _T_1320 :
node _T_1321 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_21.io.enq.bits, _T_1321
node _T_1322 = eq(UInt<5>(0h16), idx_19)
when _T_1322 :
node _T_1323 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_22.io.enq.bits, _T_1323
node _T_1324 = eq(UInt<5>(0h17), idx_19)
when _T_1324 :
node _T_1325 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_23.io.enq.bits, _T_1325
node _T_1326 = eq(UInt<5>(0h18), idx_19)
when _T_1326 :
node _T_1327 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_24.io.enq.bits, _T_1327
node _T_1328 = eq(UInt<5>(0h19), idx_19)
when _T_1328 :
node _T_1329 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_25.io.enq.bits, _T_1329
node _T_1330 = eq(UInt<5>(0h1a), idx_19)
when _T_1330 :
node _T_1331 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_26.io.enq.bits, _T_1331
node _T_1332 = eq(UInt<5>(0h1b), idx_19)
when _T_1332 :
node _T_1333 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_27.io.enq.bits, _T_1333
node _T_1334 = eq(UInt<5>(0h1c), idx_19)
when _T_1334 :
node _T_1335 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_28.io.enq.bits, _T_1335
node _T_1336 = eq(UInt<5>(0h1d), idx_19)
when _T_1336 :
node _T_1337 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_29.io.enq.bits, _T_1337
node _T_1338 = eq(UInt<5>(0h1e), idx_19)
when _T_1338 :
node _T_1339 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_30.io.enq.bits, _T_1339
node _T_1340 = eq(UInt<5>(0h1f), idx_19)
when _T_1340 :
node _T_1341 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_31.io.enq.bits, _T_1341
node _idx_T_100 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_101 = sub(_idx_T_100, write_start_index)
node _idx_T_102 = asUInt(_idx_T_101)
node _idx_T_103 = sub(_idx_T_102, UInt<5>(0h14))
node _idx_T_104 = asUInt(_idx_T_103)
node idx_20 = rem(_idx_T_104, UInt<6>(0h20))
node _T_1342 = eq(UInt<1>(0h0), idx_20)
when _T_1342 :
node _T_1343 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8.io.enq.bits, _T_1343
node _T_1344 = eq(UInt<1>(0h1), idx_20)
when _T_1344 :
node _T_1345 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_1.io.enq.bits, _T_1345
node _T_1346 = eq(UInt<2>(0h2), idx_20)
when _T_1346 :
node _T_1347 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_2.io.enq.bits, _T_1347
node _T_1348 = eq(UInt<2>(0h3), idx_20)
when _T_1348 :
node _T_1349 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_3.io.enq.bits, _T_1349
node _T_1350 = eq(UInt<3>(0h4), idx_20)
when _T_1350 :
node _T_1351 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_4.io.enq.bits, _T_1351
node _T_1352 = eq(UInt<3>(0h5), idx_20)
when _T_1352 :
node _T_1353 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_5.io.enq.bits, _T_1353
node _T_1354 = eq(UInt<3>(0h6), idx_20)
when _T_1354 :
node _T_1355 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_6.io.enq.bits, _T_1355
node _T_1356 = eq(UInt<3>(0h7), idx_20)
when _T_1356 :
node _T_1357 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_7.io.enq.bits, _T_1357
node _T_1358 = eq(UInt<4>(0h8), idx_20)
when _T_1358 :
node _T_1359 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_8.io.enq.bits, _T_1359
node _T_1360 = eq(UInt<4>(0h9), idx_20)
when _T_1360 :
node _T_1361 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_9.io.enq.bits, _T_1361
node _T_1362 = eq(UInt<4>(0ha), idx_20)
when _T_1362 :
node _T_1363 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_10.io.enq.bits, _T_1363
node _T_1364 = eq(UInt<4>(0hb), idx_20)
when _T_1364 :
node _T_1365 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_11.io.enq.bits, _T_1365
node _T_1366 = eq(UInt<4>(0hc), idx_20)
when _T_1366 :
node _T_1367 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_12.io.enq.bits, _T_1367
node _T_1368 = eq(UInt<4>(0hd), idx_20)
when _T_1368 :
node _T_1369 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_13.io.enq.bits, _T_1369
node _T_1370 = eq(UInt<4>(0he), idx_20)
when _T_1370 :
node _T_1371 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_14.io.enq.bits, _T_1371
node _T_1372 = eq(UInt<4>(0hf), idx_20)
when _T_1372 :
node _T_1373 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_15.io.enq.bits, _T_1373
node _T_1374 = eq(UInt<5>(0h10), idx_20)
when _T_1374 :
node _T_1375 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_16.io.enq.bits, _T_1375
node _T_1376 = eq(UInt<5>(0h11), idx_20)
when _T_1376 :
node _T_1377 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_17.io.enq.bits, _T_1377
node _T_1378 = eq(UInt<5>(0h12), idx_20)
when _T_1378 :
node _T_1379 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_18.io.enq.bits, _T_1379
node _T_1380 = eq(UInt<5>(0h13), idx_20)
when _T_1380 :
node _T_1381 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_19.io.enq.bits, _T_1381
node _T_1382 = eq(UInt<5>(0h14), idx_20)
when _T_1382 :
node _T_1383 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_20.io.enq.bits, _T_1383
node _T_1384 = eq(UInt<5>(0h15), idx_20)
when _T_1384 :
node _T_1385 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_21.io.enq.bits, _T_1385
node _T_1386 = eq(UInt<5>(0h16), idx_20)
when _T_1386 :
node _T_1387 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_22.io.enq.bits, _T_1387
node _T_1388 = eq(UInt<5>(0h17), idx_20)
when _T_1388 :
node _T_1389 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_23.io.enq.bits, _T_1389
node _T_1390 = eq(UInt<5>(0h18), idx_20)
when _T_1390 :
node _T_1391 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_24.io.enq.bits, _T_1391
node _T_1392 = eq(UInt<5>(0h19), idx_20)
when _T_1392 :
node _T_1393 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_25.io.enq.bits, _T_1393
node _T_1394 = eq(UInt<5>(0h1a), idx_20)
when _T_1394 :
node _T_1395 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_26.io.enq.bits, _T_1395
node _T_1396 = eq(UInt<5>(0h1b), idx_20)
when _T_1396 :
node _T_1397 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_27.io.enq.bits, _T_1397
node _T_1398 = eq(UInt<5>(0h1c), idx_20)
when _T_1398 :
node _T_1399 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_28.io.enq.bits, _T_1399
node _T_1400 = eq(UInt<5>(0h1d), idx_20)
when _T_1400 :
node _T_1401 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_29.io.enq.bits, _T_1401
node _T_1402 = eq(UInt<5>(0h1e), idx_20)
when _T_1402 :
node _T_1403 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_30.io.enq.bits, _T_1403
node _T_1404 = eq(UInt<5>(0h1f), idx_20)
when _T_1404 :
node _T_1405 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_31.io.enq.bits, _T_1405
node _idx_T_105 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_106 = sub(_idx_T_105, write_start_index)
node _idx_T_107 = asUInt(_idx_T_106)
node _idx_T_108 = sub(_idx_T_107, UInt<5>(0h15))
node _idx_T_109 = asUInt(_idx_T_108)
node idx_21 = rem(_idx_T_109, UInt<6>(0h20))
node _T_1406 = eq(UInt<1>(0h0), idx_21)
when _T_1406 :
node _T_1407 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8.io.enq.bits, _T_1407
node _T_1408 = eq(UInt<1>(0h1), idx_21)
when _T_1408 :
node _T_1409 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_1.io.enq.bits, _T_1409
node _T_1410 = eq(UInt<2>(0h2), idx_21)
when _T_1410 :
node _T_1411 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_2.io.enq.bits, _T_1411
node _T_1412 = eq(UInt<2>(0h3), idx_21)
when _T_1412 :
node _T_1413 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_3.io.enq.bits, _T_1413
node _T_1414 = eq(UInt<3>(0h4), idx_21)
when _T_1414 :
node _T_1415 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_4.io.enq.bits, _T_1415
node _T_1416 = eq(UInt<3>(0h5), idx_21)
when _T_1416 :
node _T_1417 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_5.io.enq.bits, _T_1417
node _T_1418 = eq(UInt<3>(0h6), idx_21)
when _T_1418 :
node _T_1419 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_6.io.enq.bits, _T_1419
node _T_1420 = eq(UInt<3>(0h7), idx_21)
when _T_1420 :
node _T_1421 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_7.io.enq.bits, _T_1421
node _T_1422 = eq(UInt<4>(0h8), idx_21)
when _T_1422 :
node _T_1423 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_8.io.enq.bits, _T_1423
node _T_1424 = eq(UInt<4>(0h9), idx_21)
when _T_1424 :
node _T_1425 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_9.io.enq.bits, _T_1425
node _T_1426 = eq(UInt<4>(0ha), idx_21)
when _T_1426 :
node _T_1427 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_10.io.enq.bits, _T_1427
node _T_1428 = eq(UInt<4>(0hb), idx_21)
when _T_1428 :
node _T_1429 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_11.io.enq.bits, _T_1429
node _T_1430 = eq(UInt<4>(0hc), idx_21)
when _T_1430 :
node _T_1431 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_12.io.enq.bits, _T_1431
node _T_1432 = eq(UInt<4>(0hd), idx_21)
when _T_1432 :
node _T_1433 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_13.io.enq.bits, _T_1433
node _T_1434 = eq(UInt<4>(0he), idx_21)
when _T_1434 :
node _T_1435 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_14.io.enq.bits, _T_1435
node _T_1436 = eq(UInt<4>(0hf), idx_21)
when _T_1436 :
node _T_1437 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_15.io.enq.bits, _T_1437
node _T_1438 = eq(UInt<5>(0h10), idx_21)
when _T_1438 :
node _T_1439 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_16.io.enq.bits, _T_1439
node _T_1440 = eq(UInt<5>(0h11), idx_21)
when _T_1440 :
node _T_1441 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_17.io.enq.bits, _T_1441
node _T_1442 = eq(UInt<5>(0h12), idx_21)
when _T_1442 :
node _T_1443 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_18.io.enq.bits, _T_1443
node _T_1444 = eq(UInt<5>(0h13), idx_21)
when _T_1444 :
node _T_1445 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_19.io.enq.bits, _T_1445
node _T_1446 = eq(UInt<5>(0h14), idx_21)
when _T_1446 :
node _T_1447 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_20.io.enq.bits, _T_1447
node _T_1448 = eq(UInt<5>(0h15), idx_21)
when _T_1448 :
node _T_1449 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_21.io.enq.bits, _T_1449
node _T_1450 = eq(UInt<5>(0h16), idx_21)
when _T_1450 :
node _T_1451 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_22.io.enq.bits, _T_1451
node _T_1452 = eq(UInt<5>(0h17), idx_21)
when _T_1452 :
node _T_1453 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_23.io.enq.bits, _T_1453
node _T_1454 = eq(UInt<5>(0h18), idx_21)
when _T_1454 :
node _T_1455 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_24.io.enq.bits, _T_1455
node _T_1456 = eq(UInt<5>(0h19), idx_21)
when _T_1456 :
node _T_1457 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_25.io.enq.bits, _T_1457
node _T_1458 = eq(UInt<5>(0h1a), idx_21)
when _T_1458 :
node _T_1459 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_26.io.enq.bits, _T_1459
node _T_1460 = eq(UInt<5>(0h1b), idx_21)
when _T_1460 :
node _T_1461 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_27.io.enq.bits, _T_1461
node _T_1462 = eq(UInt<5>(0h1c), idx_21)
when _T_1462 :
node _T_1463 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_28.io.enq.bits, _T_1463
node _T_1464 = eq(UInt<5>(0h1d), idx_21)
when _T_1464 :
node _T_1465 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_29.io.enq.bits, _T_1465
node _T_1466 = eq(UInt<5>(0h1e), idx_21)
when _T_1466 :
node _T_1467 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_30.io.enq.bits, _T_1467
node _T_1468 = eq(UInt<5>(0h1f), idx_21)
when _T_1468 :
node _T_1469 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_31.io.enq.bits, _T_1469
node _idx_T_110 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_111 = sub(_idx_T_110, write_start_index)
node _idx_T_112 = asUInt(_idx_T_111)
node _idx_T_113 = sub(_idx_T_112, UInt<5>(0h16))
node _idx_T_114 = asUInt(_idx_T_113)
node idx_22 = rem(_idx_T_114, UInt<6>(0h20))
node _T_1470 = eq(UInt<1>(0h0), idx_22)
when _T_1470 :
node _T_1471 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8.io.enq.bits, _T_1471
node _T_1472 = eq(UInt<1>(0h1), idx_22)
when _T_1472 :
node _T_1473 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_1.io.enq.bits, _T_1473
node _T_1474 = eq(UInt<2>(0h2), idx_22)
when _T_1474 :
node _T_1475 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_2.io.enq.bits, _T_1475
node _T_1476 = eq(UInt<2>(0h3), idx_22)
when _T_1476 :
node _T_1477 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_3.io.enq.bits, _T_1477
node _T_1478 = eq(UInt<3>(0h4), idx_22)
when _T_1478 :
node _T_1479 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_4.io.enq.bits, _T_1479
node _T_1480 = eq(UInt<3>(0h5), idx_22)
when _T_1480 :
node _T_1481 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_5.io.enq.bits, _T_1481
node _T_1482 = eq(UInt<3>(0h6), idx_22)
when _T_1482 :
node _T_1483 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_6.io.enq.bits, _T_1483
node _T_1484 = eq(UInt<3>(0h7), idx_22)
when _T_1484 :
node _T_1485 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_7.io.enq.bits, _T_1485
node _T_1486 = eq(UInt<4>(0h8), idx_22)
when _T_1486 :
node _T_1487 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_8.io.enq.bits, _T_1487
node _T_1488 = eq(UInt<4>(0h9), idx_22)
when _T_1488 :
node _T_1489 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_9.io.enq.bits, _T_1489
node _T_1490 = eq(UInt<4>(0ha), idx_22)
when _T_1490 :
node _T_1491 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_10.io.enq.bits, _T_1491
node _T_1492 = eq(UInt<4>(0hb), idx_22)
when _T_1492 :
node _T_1493 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_11.io.enq.bits, _T_1493
node _T_1494 = eq(UInt<4>(0hc), idx_22)
when _T_1494 :
node _T_1495 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_12.io.enq.bits, _T_1495
node _T_1496 = eq(UInt<4>(0hd), idx_22)
when _T_1496 :
node _T_1497 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_13.io.enq.bits, _T_1497
node _T_1498 = eq(UInt<4>(0he), idx_22)
when _T_1498 :
node _T_1499 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_14.io.enq.bits, _T_1499
node _T_1500 = eq(UInt<4>(0hf), idx_22)
when _T_1500 :
node _T_1501 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_15.io.enq.bits, _T_1501
node _T_1502 = eq(UInt<5>(0h10), idx_22)
when _T_1502 :
node _T_1503 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_16.io.enq.bits, _T_1503
node _T_1504 = eq(UInt<5>(0h11), idx_22)
when _T_1504 :
node _T_1505 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_17.io.enq.bits, _T_1505
node _T_1506 = eq(UInt<5>(0h12), idx_22)
when _T_1506 :
node _T_1507 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_18.io.enq.bits, _T_1507
node _T_1508 = eq(UInt<5>(0h13), idx_22)
when _T_1508 :
node _T_1509 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_19.io.enq.bits, _T_1509
node _T_1510 = eq(UInt<5>(0h14), idx_22)
when _T_1510 :
node _T_1511 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_20.io.enq.bits, _T_1511
node _T_1512 = eq(UInt<5>(0h15), idx_22)
when _T_1512 :
node _T_1513 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_21.io.enq.bits, _T_1513
node _T_1514 = eq(UInt<5>(0h16), idx_22)
when _T_1514 :
node _T_1515 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_22.io.enq.bits, _T_1515
node _T_1516 = eq(UInt<5>(0h17), idx_22)
when _T_1516 :
node _T_1517 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_23.io.enq.bits, _T_1517
node _T_1518 = eq(UInt<5>(0h18), idx_22)
when _T_1518 :
node _T_1519 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_24.io.enq.bits, _T_1519
node _T_1520 = eq(UInt<5>(0h19), idx_22)
when _T_1520 :
node _T_1521 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_25.io.enq.bits, _T_1521
node _T_1522 = eq(UInt<5>(0h1a), idx_22)
when _T_1522 :
node _T_1523 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_26.io.enq.bits, _T_1523
node _T_1524 = eq(UInt<5>(0h1b), idx_22)
when _T_1524 :
node _T_1525 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_27.io.enq.bits, _T_1525
node _T_1526 = eq(UInt<5>(0h1c), idx_22)
when _T_1526 :
node _T_1527 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_28.io.enq.bits, _T_1527
node _T_1528 = eq(UInt<5>(0h1d), idx_22)
when _T_1528 :
node _T_1529 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_29.io.enq.bits, _T_1529
node _T_1530 = eq(UInt<5>(0h1e), idx_22)
when _T_1530 :
node _T_1531 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_30.io.enq.bits, _T_1531
node _T_1532 = eq(UInt<5>(0h1f), idx_22)
when _T_1532 :
node _T_1533 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_31.io.enq.bits, _T_1533
node _idx_T_115 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_116 = sub(_idx_T_115, write_start_index)
node _idx_T_117 = asUInt(_idx_T_116)
node _idx_T_118 = sub(_idx_T_117, UInt<5>(0h17))
node _idx_T_119 = asUInt(_idx_T_118)
node idx_23 = rem(_idx_T_119, UInt<6>(0h20))
node _T_1534 = eq(UInt<1>(0h0), idx_23)
when _T_1534 :
node _T_1535 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8.io.enq.bits, _T_1535
node _T_1536 = eq(UInt<1>(0h1), idx_23)
when _T_1536 :
node _T_1537 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_1.io.enq.bits, _T_1537
node _T_1538 = eq(UInt<2>(0h2), idx_23)
when _T_1538 :
node _T_1539 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_2.io.enq.bits, _T_1539
node _T_1540 = eq(UInt<2>(0h3), idx_23)
when _T_1540 :
node _T_1541 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_3.io.enq.bits, _T_1541
node _T_1542 = eq(UInt<3>(0h4), idx_23)
when _T_1542 :
node _T_1543 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_4.io.enq.bits, _T_1543
node _T_1544 = eq(UInt<3>(0h5), idx_23)
when _T_1544 :
node _T_1545 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_5.io.enq.bits, _T_1545
node _T_1546 = eq(UInt<3>(0h6), idx_23)
when _T_1546 :
node _T_1547 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_6.io.enq.bits, _T_1547
node _T_1548 = eq(UInt<3>(0h7), idx_23)
when _T_1548 :
node _T_1549 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_7.io.enq.bits, _T_1549
node _T_1550 = eq(UInt<4>(0h8), idx_23)
when _T_1550 :
node _T_1551 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_8.io.enq.bits, _T_1551
node _T_1552 = eq(UInt<4>(0h9), idx_23)
when _T_1552 :
node _T_1553 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_9.io.enq.bits, _T_1553
node _T_1554 = eq(UInt<4>(0ha), idx_23)
when _T_1554 :
node _T_1555 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_10.io.enq.bits, _T_1555
node _T_1556 = eq(UInt<4>(0hb), idx_23)
when _T_1556 :
node _T_1557 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_11.io.enq.bits, _T_1557
node _T_1558 = eq(UInt<4>(0hc), idx_23)
when _T_1558 :
node _T_1559 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_12.io.enq.bits, _T_1559
node _T_1560 = eq(UInt<4>(0hd), idx_23)
when _T_1560 :
node _T_1561 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_13.io.enq.bits, _T_1561
node _T_1562 = eq(UInt<4>(0he), idx_23)
when _T_1562 :
node _T_1563 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_14.io.enq.bits, _T_1563
node _T_1564 = eq(UInt<4>(0hf), idx_23)
when _T_1564 :
node _T_1565 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_15.io.enq.bits, _T_1565
node _T_1566 = eq(UInt<5>(0h10), idx_23)
when _T_1566 :
node _T_1567 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_16.io.enq.bits, _T_1567
node _T_1568 = eq(UInt<5>(0h11), idx_23)
when _T_1568 :
node _T_1569 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_17.io.enq.bits, _T_1569
node _T_1570 = eq(UInt<5>(0h12), idx_23)
when _T_1570 :
node _T_1571 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_18.io.enq.bits, _T_1571
node _T_1572 = eq(UInt<5>(0h13), idx_23)
when _T_1572 :
node _T_1573 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_19.io.enq.bits, _T_1573
node _T_1574 = eq(UInt<5>(0h14), idx_23)
when _T_1574 :
node _T_1575 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_20.io.enq.bits, _T_1575
node _T_1576 = eq(UInt<5>(0h15), idx_23)
when _T_1576 :
node _T_1577 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_21.io.enq.bits, _T_1577
node _T_1578 = eq(UInt<5>(0h16), idx_23)
when _T_1578 :
node _T_1579 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_22.io.enq.bits, _T_1579
node _T_1580 = eq(UInt<5>(0h17), idx_23)
when _T_1580 :
node _T_1581 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_23.io.enq.bits, _T_1581
node _T_1582 = eq(UInt<5>(0h18), idx_23)
when _T_1582 :
node _T_1583 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_24.io.enq.bits, _T_1583
node _T_1584 = eq(UInt<5>(0h19), idx_23)
when _T_1584 :
node _T_1585 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_25.io.enq.bits, _T_1585
node _T_1586 = eq(UInt<5>(0h1a), idx_23)
when _T_1586 :
node _T_1587 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_26.io.enq.bits, _T_1587
node _T_1588 = eq(UInt<5>(0h1b), idx_23)
when _T_1588 :
node _T_1589 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_27.io.enq.bits, _T_1589
node _T_1590 = eq(UInt<5>(0h1c), idx_23)
when _T_1590 :
node _T_1591 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_28.io.enq.bits, _T_1591
node _T_1592 = eq(UInt<5>(0h1d), idx_23)
when _T_1592 :
node _T_1593 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_29.io.enq.bits, _T_1593
node _T_1594 = eq(UInt<5>(0h1e), idx_23)
when _T_1594 :
node _T_1595 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_30.io.enq.bits, _T_1595
node _T_1596 = eq(UInt<5>(0h1f), idx_23)
when _T_1596 :
node _T_1597 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_31.io.enq.bits, _T_1597
node _idx_T_120 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_121 = sub(_idx_T_120, write_start_index)
node _idx_T_122 = asUInt(_idx_T_121)
node _idx_T_123 = sub(_idx_T_122, UInt<5>(0h18))
node _idx_T_124 = asUInt(_idx_T_123)
node idx_24 = rem(_idx_T_124, UInt<6>(0h20))
node _T_1598 = eq(UInt<1>(0h0), idx_24)
when _T_1598 :
node _T_1599 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8.io.enq.bits, _T_1599
node _T_1600 = eq(UInt<1>(0h1), idx_24)
when _T_1600 :
node _T_1601 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_1.io.enq.bits, _T_1601
node _T_1602 = eq(UInt<2>(0h2), idx_24)
when _T_1602 :
node _T_1603 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_2.io.enq.bits, _T_1603
node _T_1604 = eq(UInt<2>(0h3), idx_24)
when _T_1604 :
node _T_1605 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_3.io.enq.bits, _T_1605
node _T_1606 = eq(UInt<3>(0h4), idx_24)
when _T_1606 :
node _T_1607 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_4.io.enq.bits, _T_1607
node _T_1608 = eq(UInt<3>(0h5), idx_24)
when _T_1608 :
node _T_1609 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_5.io.enq.bits, _T_1609
node _T_1610 = eq(UInt<3>(0h6), idx_24)
when _T_1610 :
node _T_1611 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_6.io.enq.bits, _T_1611
node _T_1612 = eq(UInt<3>(0h7), idx_24)
when _T_1612 :
node _T_1613 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_7.io.enq.bits, _T_1613
node _T_1614 = eq(UInt<4>(0h8), idx_24)
when _T_1614 :
node _T_1615 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_8.io.enq.bits, _T_1615
node _T_1616 = eq(UInt<4>(0h9), idx_24)
when _T_1616 :
node _T_1617 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_9.io.enq.bits, _T_1617
node _T_1618 = eq(UInt<4>(0ha), idx_24)
when _T_1618 :
node _T_1619 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_10.io.enq.bits, _T_1619
node _T_1620 = eq(UInt<4>(0hb), idx_24)
when _T_1620 :
node _T_1621 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_11.io.enq.bits, _T_1621
node _T_1622 = eq(UInt<4>(0hc), idx_24)
when _T_1622 :
node _T_1623 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_12.io.enq.bits, _T_1623
node _T_1624 = eq(UInt<4>(0hd), idx_24)
when _T_1624 :
node _T_1625 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_13.io.enq.bits, _T_1625
node _T_1626 = eq(UInt<4>(0he), idx_24)
when _T_1626 :
node _T_1627 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_14.io.enq.bits, _T_1627
node _T_1628 = eq(UInt<4>(0hf), idx_24)
when _T_1628 :
node _T_1629 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_15.io.enq.bits, _T_1629
node _T_1630 = eq(UInt<5>(0h10), idx_24)
when _T_1630 :
node _T_1631 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_16.io.enq.bits, _T_1631
node _T_1632 = eq(UInt<5>(0h11), idx_24)
when _T_1632 :
node _T_1633 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_17.io.enq.bits, _T_1633
node _T_1634 = eq(UInt<5>(0h12), idx_24)
when _T_1634 :
node _T_1635 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_18.io.enq.bits, _T_1635
node _T_1636 = eq(UInt<5>(0h13), idx_24)
when _T_1636 :
node _T_1637 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_19.io.enq.bits, _T_1637
node _T_1638 = eq(UInt<5>(0h14), idx_24)
when _T_1638 :
node _T_1639 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_20.io.enq.bits, _T_1639
node _T_1640 = eq(UInt<5>(0h15), idx_24)
when _T_1640 :
node _T_1641 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_21.io.enq.bits, _T_1641
node _T_1642 = eq(UInt<5>(0h16), idx_24)
when _T_1642 :
node _T_1643 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_22.io.enq.bits, _T_1643
node _T_1644 = eq(UInt<5>(0h17), idx_24)
when _T_1644 :
node _T_1645 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_23.io.enq.bits, _T_1645
node _T_1646 = eq(UInt<5>(0h18), idx_24)
when _T_1646 :
node _T_1647 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_24.io.enq.bits, _T_1647
node _T_1648 = eq(UInt<5>(0h19), idx_24)
when _T_1648 :
node _T_1649 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_25.io.enq.bits, _T_1649
node _T_1650 = eq(UInt<5>(0h1a), idx_24)
when _T_1650 :
node _T_1651 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_26.io.enq.bits, _T_1651
node _T_1652 = eq(UInt<5>(0h1b), idx_24)
when _T_1652 :
node _T_1653 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_27.io.enq.bits, _T_1653
node _T_1654 = eq(UInt<5>(0h1c), idx_24)
when _T_1654 :
node _T_1655 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_28.io.enq.bits, _T_1655
node _T_1656 = eq(UInt<5>(0h1d), idx_24)
when _T_1656 :
node _T_1657 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_29.io.enq.bits, _T_1657
node _T_1658 = eq(UInt<5>(0h1e), idx_24)
when _T_1658 :
node _T_1659 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_30.io.enq.bits, _T_1659
node _T_1660 = eq(UInt<5>(0h1f), idx_24)
when _T_1660 :
node _T_1661 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_31.io.enq.bits, _T_1661
node _idx_T_125 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_126 = sub(_idx_T_125, write_start_index)
node _idx_T_127 = asUInt(_idx_T_126)
node _idx_T_128 = sub(_idx_T_127, UInt<5>(0h19))
node _idx_T_129 = asUInt(_idx_T_128)
node idx_25 = rem(_idx_T_129, UInt<6>(0h20))
node _T_1662 = eq(UInt<1>(0h0), idx_25)
when _T_1662 :
node _T_1663 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8.io.enq.bits, _T_1663
node _T_1664 = eq(UInt<1>(0h1), idx_25)
when _T_1664 :
node _T_1665 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_1.io.enq.bits, _T_1665
node _T_1666 = eq(UInt<2>(0h2), idx_25)
when _T_1666 :
node _T_1667 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_2.io.enq.bits, _T_1667
node _T_1668 = eq(UInt<2>(0h3), idx_25)
when _T_1668 :
node _T_1669 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_3.io.enq.bits, _T_1669
node _T_1670 = eq(UInt<3>(0h4), idx_25)
when _T_1670 :
node _T_1671 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_4.io.enq.bits, _T_1671
node _T_1672 = eq(UInt<3>(0h5), idx_25)
when _T_1672 :
node _T_1673 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_5.io.enq.bits, _T_1673
node _T_1674 = eq(UInt<3>(0h6), idx_25)
when _T_1674 :
node _T_1675 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_6.io.enq.bits, _T_1675
node _T_1676 = eq(UInt<3>(0h7), idx_25)
when _T_1676 :
node _T_1677 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_7.io.enq.bits, _T_1677
node _T_1678 = eq(UInt<4>(0h8), idx_25)
when _T_1678 :
node _T_1679 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_8.io.enq.bits, _T_1679
node _T_1680 = eq(UInt<4>(0h9), idx_25)
when _T_1680 :
node _T_1681 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_9.io.enq.bits, _T_1681
node _T_1682 = eq(UInt<4>(0ha), idx_25)
when _T_1682 :
node _T_1683 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_10.io.enq.bits, _T_1683
node _T_1684 = eq(UInt<4>(0hb), idx_25)
when _T_1684 :
node _T_1685 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_11.io.enq.bits, _T_1685
node _T_1686 = eq(UInt<4>(0hc), idx_25)
when _T_1686 :
node _T_1687 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_12.io.enq.bits, _T_1687
node _T_1688 = eq(UInt<4>(0hd), idx_25)
when _T_1688 :
node _T_1689 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_13.io.enq.bits, _T_1689
node _T_1690 = eq(UInt<4>(0he), idx_25)
when _T_1690 :
node _T_1691 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_14.io.enq.bits, _T_1691
node _T_1692 = eq(UInt<4>(0hf), idx_25)
when _T_1692 :
node _T_1693 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_15.io.enq.bits, _T_1693
node _T_1694 = eq(UInt<5>(0h10), idx_25)
when _T_1694 :
node _T_1695 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_16.io.enq.bits, _T_1695
node _T_1696 = eq(UInt<5>(0h11), idx_25)
when _T_1696 :
node _T_1697 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_17.io.enq.bits, _T_1697
node _T_1698 = eq(UInt<5>(0h12), idx_25)
when _T_1698 :
node _T_1699 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_18.io.enq.bits, _T_1699
node _T_1700 = eq(UInt<5>(0h13), idx_25)
when _T_1700 :
node _T_1701 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_19.io.enq.bits, _T_1701
node _T_1702 = eq(UInt<5>(0h14), idx_25)
when _T_1702 :
node _T_1703 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_20.io.enq.bits, _T_1703
node _T_1704 = eq(UInt<5>(0h15), idx_25)
when _T_1704 :
node _T_1705 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_21.io.enq.bits, _T_1705
node _T_1706 = eq(UInt<5>(0h16), idx_25)
when _T_1706 :
node _T_1707 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_22.io.enq.bits, _T_1707
node _T_1708 = eq(UInt<5>(0h17), idx_25)
when _T_1708 :
node _T_1709 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_23.io.enq.bits, _T_1709
node _T_1710 = eq(UInt<5>(0h18), idx_25)
when _T_1710 :
node _T_1711 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_24.io.enq.bits, _T_1711
node _T_1712 = eq(UInt<5>(0h19), idx_25)
when _T_1712 :
node _T_1713 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_25.io.enq.bits, _T_1713
node _T_1714 = eq(UInt<5>(0h1a), idx_25)
when _T_1714 :
node _T_1715 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_26.io.enq.bits, _T_1715
node _T_1716 = eq(UInt<5>(0h1b), idx_25)
when _T_1716 :
node _T_1717 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_27.io.enq.bits, _T_1717
node _T_1718 = eq(UInt<5>(0h1c), idx_25)
when _T_1718 :
node _T_1719 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_28.io.enq.bits, _T_1719
node _T_1720 = eq(UInt<5>(0h1d), idx_25)
when _T_1720 :
node _T_1721 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_29.io.enq.bits, _T_1721
node _T_1722 = eq(UInt<5>(0h1e), idx_25)
when _T_1722 :
node _T_1723 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_30.io.enq.bits, _T_1723
node _T_1724 = eq(UInt<5>(0h1f), idx_25)
when _T_1724 :
node _T_1725 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_31.io.enq.bits, _T_1725
node _idx_T_130 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_131 = sub(_idx_T_130, write_start_index)
node _idx_T_132 = asUInt(_idx_T_131)
node _idx_T_133 = sub(_idx_T_132, UInt<5>(0h1a))
node _idx_T_134 = asUInt(_idx_T_133)
node idx_26 = rem(_idx_T_134, UInt<6>(0h20))
node _T_1726 = eq(UInt<1>(0h0), idx_26)
when _T_1726 :
node _T_1727 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8.io.enq.bits, _T_1727
node _T_1728 = eq(UInt<1>(0h1), idx_26)
when _T_1728 :
node _T_1729 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_1.io.enq.bits, _T_1729
node _T_1730 = eq(UInt<2>(0h2), idx_26)
when _T_1730 :
node _T_1731 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_2.io.enq.bits, _T_1731
node _T_1732 = eq(UInt<2>(0h3), idx_26)
when _T_1732 :
node _T_1733 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_3.io.enq.bits, _T_1733
node _T_1734 = eq(UInt<3>(0h4), idx_26)
when _T_1734 :
node _T_1735 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_4.io.enq.bits, _T_1735
node _T_1736 = eq(UInt<3>(0h5), idx_26)
when _T_1736 :
node _T_1737 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_5.io.enq.bits, _T_1737
node _T_1738 = eq(UInt<3>(0h6), idx_26)
when _T_1738 :
node _T_1739 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_6.io.enq.bits, _T_1739
node _T_1740 = eq(UInt<3>(0h7), idx_26)
when _T_1740 :
node _T_1741 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_7.io.enq.bits, _T_1741
node _T_1742 = eq(UInt<4>(0h8), idx_26)
when _T_1742 :
node _T_1743 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_8.io.enq.bits, _T_1743
node _T_1744 = eq(UInt<4>(0h9), idx_26)
when _T_1744 :
node _T_1745 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_9.io.enq.bits, _T_1745
node _T_1746 = eq(UInt<4>(0ha), idx_26)
when _T_1746 :
node _T_1747 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_10.io.enq.bits, _T_1747
node _T_1748 = eq(UInt<4>(0hb), idx_26)
when _T_1748 :
node _T_1749 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_11.io.enq.bits, _T_1749
node _T_1750 = eq(UInt<4>(0hc), idx_26)
when _T_1750 :
node _T_1751 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_12.io.enq.bits, _T_1751
node _T_1752 = eq(UInt<4>(0hd), idx_26)
when _T_1752 :
node _T_1753 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_13.io.enq.bits, _T_1753
node _T_1754 = eq(UInt<4>(0he), idx_26)
when _T_1754 :
node _T_1755 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_14.io.enq.bits, _T_1755
node _T_1756 = eq(UInt<4>(0hf), idx_26)
when _T_1756 :
node _T_1757 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_15.io.enq.bits, _T_1757
node _T_1758 = eq(UInt<5>(0h10), idx_26)
when _T_1758 :
node _T_1759 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_16.io.enq.bits, _T_1759
node _T_1760 = eq(UInt<5>(0h11), idx_26)
when _T_1760 :
node _T_1761 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_17.io.enq.bits, _T_1761
node _T_1762 = eq(UInt<5>(0h12), idx_26)
when _T_1762 :
node _T_1763 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_18.io.enq.bits, _T_1763
node _T_1764 = eq(UInt<5>(0h13), idx_26)
when _T_1764 :
node _T_1765 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_19.io.enq.bits, _T_1765
node _T_1766 = eq(UInt<5>(0h14), idx_26)
when _T_1766 :
node _T_1767 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_20.io.enq.bits, _T_1767
node _T_1768 = eq(UInt<5>(0h15), idx_26)
when _T_1768 :
node _T_1769 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_21.io.enq.bits, _T_1769
node _T_1770 = eq(UInt<5>(0h16), idx_26)
when _T_1770 :
node _T_1771 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_22.io.enq.bits, _T_1771
node _T_1772 = eq(UInt<5>(0h17), idx_26)
when _T_1772 :
node _T_1773 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_23.io.enq.bits, _T_1773
node _T_1774 = eq(UInt<5>(0h18), idx_26)
when _T_1774 :
node _T_1775 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_24.io.enq.bits, _T_1775
node _T_1776 = eq(UInt<5>(0h19), idx_26)
when _T_1776 :
node _T_1777 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_25.io.enq.bits, _T_1777
node _T_1778 = eq(UInt<5>(0h1a), idx_26)
when _T_1778 :
node _T_1779 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_26.io.enq.bits, _T_1779
node _T_1780 = eq(UInt<5>(0h1b), idx_26)
when _T_1780 :
node _T_1781 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_27.io.enq.bits, _T_1781
node _T_1782 = eq(UInt<5>(0h1c), idx_26)
when _T_1782 :
node _T_1783 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_28.io.enq.bits, _T_1783
node _T_1784 = eq(UInt<5>(0h1d), idx_26)
when _T_1784 :
node _T_1785 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_29.io.enq.bits, _T_1785
node _T_1786 = eq(UInt<5>(0h1e), idx_26)
when _T_1786 :
node _T_1787 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_30.io.enq.bits, _T_1787
node _T_1788 = eq(UInt<5>(0h1f), idx_26)
when _T_1788 :
node _T_1789 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_31.io.enq.bits, _T_1789
node _idx_T_135 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_136 = sub(_idx_T_135, write_start_index)
node _idx_T_137 = asUInt(_idx_T_136)
node _idx_T_138 = sub(_idx_T_137, UInt<5>(0h1b))
node _idx_T_139 = asUInt(_idx_T_138)
node idx_27 = rem(_idx_T_139, UInt<6>(0h20))
node _T_1790 = eq(UInt<1>(0h0), idx_27)
when _T_1790 :
node _T_1791 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8.io.enq.bits, _T_1791
node _T_1792 = eq(UInt<1>(0h1), idx_27)
when _T_1792 :
node _T_1793 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_1.io.enq.bits, _T_1793
node _T_1794 = eq(UInt<2>(0h2), idx_27)
when _T_1794 :
node _T_1795 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_2.io.enq.bits, _T_1795
node _T_1796 = eq(UInt<2>(0h3), idx_27)
when _T_1796 :
node _T_1797 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_3.io.enq.bits, _T_1797
node _T_1798 = eq(UInt<3>(0h4), idx_27)
when _T_1798 :
node _T_1799 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_4.io.enq.bits, _T_1799
node _T_1800 = eq(UInt<3>(0h5), idx_27)
when _T_1800 :
node _T_1801 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_5.io.enq.bits, _T_1801
node _T_1802 = eq(UInt<3>(0h6), idx_27)
when _T_1802 :
node _T_1803 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_6.io.enq.bits, _T_1803
node _T_1804 = eq(UInt<3>(0h7), idx_27)
when _T_1804 :
node _T_1805 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_7.io.enq.bits, _T_1805
node _T_1806 = eq(UInt<4>(0h8), idx_27)
when _T_1806 :
node _T_1807 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_8.io.enq.bits, _T_1807
node _T_1808 = eq(UInt<4>(0h9), idx_27)
when _T_1808 :
node _T_1809 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_9.io.enq.bits, _T_1809
node _T_1810 = eq(UInt<4>(0ha), idx_27)
when _T_1810 :
node _T_1811 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_10.io.enq.bits, _T_1811
node _T_1812 = eq(UInt<4>(0hb), idx_27)
when _T_1812 :
node _T_1813 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_11.io.enq.bits, _T_1813
node _T_1814 = eq(UInt<4>(0hc), idx_27)
when _T_1814 :
node _T_1815 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_12.io.enq.bits, _T_1815
node _T_1816 = eq(UInt<4>(0hd), idx_27)
when _T_1816 :
node _T_1817 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_13.io.enq.bits, _T_1817
node _T_1818 = eq(UInt<4>(0he), idx_27)
when _T_1818 :
node _T_1819 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_14.io.enq.bits, _T_1819
node _T_1820 = eq(UInt<4>(0hf), idx_27)
when _T_1820 :
node _T_1821 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_15.io.enq.bits, _T_1821
node _T_1822 = eq(UInt<5>(0h10), idx_27)
when _T_1822 :
node _T_1823 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_16.io.enq.bits, _T_1823
node _T_1824 = eq(UInt<5>(0h11), idx_27)
when _T_1824 :
node _T_1825 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_17.io.enq.bits, _T_1825
node _T_1826 = eq(UInt<5>(0h12), idx_27)
when _T_1826 :
node _T_1827 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_18.io.enq.bits, _T_1827
node _T_1828 = eq(UInt<5>(0h13), idx_27)
when _T_1828 :
node _T_1829 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_19.io.enq.bits, _T_1829
node _T_1830 = eq(UInt<5>(0h14), idx_27)
when _T_1830 :
node _T_1831 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_20.io.enq.bits, _T_1831
node _T_1832 = eq(UInt<5>(0h15), idx_27)
when _T_1832 :
node _T_1833 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_21.io.enq.bits, _T_1833
node _T_1834 = eq(UInt<5>(0h16), idx_27)
when _T_1834 :
node _T_1835 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_22.io.enq.bits, _T_1835
node _T_1836 = eq(UInt<5>(0h17), idx_27)
when _T_1836 :
node _T_1837 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_23.io.enq.bits, _T_1837
node _T_1838 = eq(UInt<5>(0h18), idx_27)
when _T_1838 :
node _T_1839 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_24.io.enq.bits, _T_1839
node _T_1840 = eq(UInt<5>(0h19), idx_27)
when _T_1840 :
node _T_1841 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_25.io.enq.bits, _T_1841
node _T_1842 = eq(UInt<5>(0h1a), idx_27)
when _T_1842 :
node _T_1843 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_26.io.enq.bits, _T_1843
node _T_1844 = eq(UInt<5>(0h1b), idx_27)
when _T_1844 :
node _T_1845 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_27.io.enq.bits, _T_1845
node _T_1846 = eq(UInt<5>(0h1c), idx_27)
when _T_1846 :
node _T_1847 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_28.io.enq.bits, _T_1847
node _T_1848 = eq(UInt<5>(0h1d), idx_27)
when _T_1848 :
node _T_1849 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_29.io.enq.bits, _T_1849
node _T_1850 = eq(UInt<5>(0h1e), idx_27)
when _T_1850 :
node _T_1851 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_30.io.enq.bits, _T_1851
node _T_1852 = eq(UInt<5>(0h1f), idx_27)
when _T_1852 :
node _T_1853 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_31.io.enq.bits, _T_1853
node _idx_T_140 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_141 = sub(_idx_T_140, write_start_index)
node _idx_T_142 = asUInt(_idx_T_141)
node _idx_T_143 = sub(_idx_T_142, UInt<5>(0h1c))
node _idx_T_144 = asUInt(_idx_T_143)
node idx_28 = rem(_idx_T_144, UInt<6>(0h20))
node _T_1854 = eq(UInt<1>(0h0), idx_28)
when _T_1854 :
node _T_1855 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8.io.enq.bits, _T_1855
node _T_1856 = eq(UInt<1>(0h1), idx_28)
when _T_1856 :
node _T_1857 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_1.io.enq.bits, _T_1857
node _T_1858 = eq(UInt<2>(0h2), idx_28)
when _T_1858 :
node _T_1859 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_2.io.enq.bits, _T_1859
node _T_1860 = eq(UInt<2>(0h3), idx_28)
when _T_1860 :
node _T_1861 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_3.io.enq.bits, _T_1861
node _T_1862 = eq(UInt<3>(0h4), idx_28)
when _T_1862 :
node _T_1863 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_4.io.enq.bits, _T_1863
node _T_1864 = eq(UInt<3>(0h5), idx_28)
when _T_1864 :
node _T_1865 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_5.io.enq.bits, _T_1865
node _T_1866 = eq(UInt<3>(0h6), idx_28)
when _T_1866 :
node _T_1867 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_6.io.enq.bits, _T_1867
node _T_1868 = eq(UInt<3>(0h7), idx_28)
when _T_1868 :
node _T_1869 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_7.io.enq.bits, _T_1869
node _T_1870 = eq(UInt<4>(0h8), idx_28)
when _T_1870 :
node _T_1871 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_8.io.enq.bits, _T_1871
node _T_1872 = eq(UInt<4>(0h9), idx_28)
when _T_1872 :
node _T_1873 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_9.io.enq.bits, _T_1873
node _T_1874 = eq(UInt<4>(0ha), idx_28)
when _T_1874 :
node _T_1875 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_10.io.enq.bits, _T_1875
node _T_1876 = eq(UInt<4>(0hb), idx_28)
when _T_1876 :
node _T_1877 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_11.io.enq.bits, _T_1877
node _T_1878 = eq(UInt<4>(0hc), idx_28)
when _T_1878 :
node _T_1879 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_12.io.enq.bits, _T_1879
node _T_1880 = eq(UInt<4>(0hd), idx_28)
when _T_1880 :
node _T_1881 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_13.io.enq.bits, _T_1881
node _T_1882 = eq(UInt<4>(0he), idx_28)
when _T_1882 :
node _T_1883 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_14.io.enq.bits, _T_1883
node _T_1884 = eq(UInt<4>(0hf), idx_28)
when _T_1884 :
node _T_1885 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_15.io.enq.bits, _T_1885
node _T_1886 = eq(UInt<5>(0h10), idx_28)
when _T_1886 :
node _T_1887 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_16.io.enq.bits, _T_1887
node _T_1888 = eq(UInt<5>(0h11), idx_28)
when _T_1888 :
node _T_1889 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_17.io.enq.bits, _T_1889
node _T_1890 = eq(UInt<5>(0h12), idx_28)
when _T_1890 :
node _T_1891 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_18.io.enq.bits, _T_1891
node _T_1892 = eq(UInt<5>(0h13), idx_28)
when _T_1892 :
node _T_1893 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_19.io.enq.bits, _T_1893
node _T_1894 = eq(UInt<5>(0h14), idx_28)
when _T_1894 :
node _T_1895 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_20.io.enq.bits, _T_1895
node _T_1896 = eq(UInt<5>(0h15), idx_28)
when _T_1896 :
node _T_1897 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_21.io.enq.bits, _T_1897
node _T_1898 = eq(UInt<5>(0h16), idx_28)
when _T_1898 :
node _T_1899 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_22.io.enq.bits, _T_1899
node _T_1900 = eq(UInt<5>(0h17), idx_28)
when _T_1900 :
node _T_1901 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_23.io.enq.bits, _T_1901
node _T_1902 = eq(UInt<5>(0h18), idx_28)
when _T_1902 :
node _T_1903 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_24.io.enq.bits, _T_1903
node _T_1904 = eq(UInt<5>(0h19), idx_28)
when _T_1904 :
node _T_1905 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_25.io.enq.bits, _T_1905
node _T_1906 = eq(UInt<5>(0h1a), idx_28)
when _T_1906 :
node _T_1907 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_26.io.enq.bits, _T_1907
node _T_1908 = eq(UInt<5>(0h1b), idx_28)
when _T_1908 :
node _T_1909 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_27.io.enq.bits, _T_1909
node _T_1910 = eq(UInt<5>(0h1c), idx_28)
when _T_1910 :
node _T_1911 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_28.io.enq.bits, _T_1911
node _T_1912 = eq(UInt<5>(0h1d), idx_28)
when _T_1912 :
node _T_1913 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_29.io.enq.bits, _T_1913
node _T_1914 = eq(UInt<5>(0h1e), idx_28)
when _T_1914 :
node _T_1915 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_30.io.enq.bits, _T_1915
node _T_1916 = eq(UInt<5>(0h1f), idx_28)
when _T_1916 :
node _T_1917 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_31.io.enq.bits, _T_1917
node _idx_T_145 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_146 = sub(_idx_T_145, write_start_index)
node _idx_T_147 = asUInt(_idx_T_146)
node _idx_T_148 = sub(_idx_T_147, UInt<5>(0h1d))
node _idx_T_149 = asUInt(_idx_T_148)
node idx_29 = rem(_idx_T_149, UInt<6>(0h20))
node _T_1918 = eq(UInt<1>(0h0), idx_29)
when _T_1918 :
node _T_1919 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8.io.enq.bits, _T_1919
node _T_1920 = eq(UInt<1>(0h1), idx_29)
when _T_1920 :
node _T_1921 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_1.io.enq.bits, _T_1921
node _T_1922 = eq(UInt<2>(0h2), idx_29)
when _T_1922 :
node _T_1923 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_2.io.enq.bits, _T_1923
node _T_1924 = eq(UInt<2>(0h3), idx_29)
when _T_1924 :
node _T_1925 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_3.io.enq.bits, _T_1925
node _T_1926 = eq(UInt<3>(0h4), idx_29)
when _T_1926 :
node _T_1927 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_4.io.enq.bits, _T_1927
node _T_1928 = eq(UInt<3>(0h5), idx_29)
when _T_1928 :
node _T_1929 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_5.io.enq.bits, _T_1929
node _T_1930 = eq(UInt<3>(0h6), idx_29)
when _T_1930 :
node _T_1931 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_6.io.enq.bits, _T_1931
node _T_1932 = eq(UInt<3>(0h7), idx_29)
when _T_1932 :
node _T_1933 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_7.io.enq.bits, _T_1933
node _T_1934 = eq(UInt<4>(0h8), idx_29)
when _T_1934 :
node _T_1935 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_8.io.enq.bits, _T_1935
node _T_1936 = eq(UInt<4>(0h9), idx_29)
when _T_1936 :
node _T_1937 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_9.io.enq.bits, _T_1937
node _T_1938 = eq(UInt<4>(0ha), idx_29)
when _T_1938 :
node _T_1939 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_10.io.enq.bits, _T_1939
node _T_1940 = eq(UInt<4>(0hb), idx_29)
when _T_1940 :
node _T_1941 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_11.io.enq.bits, _T_1941
node _T_1942 = eq(UInt<4>(0hc), idx_29)
when _T_1942 :
node _T_1943 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_12.io.enq.bits, _T_1943
node _T_1944 = eq(UInt<4>(0hd), idx_29)
when _T_1944 :
node _T_1945 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_13.io.enq.bits, _T_1945
node _T_1946 = eq(UInt<4>(0he), idx_29)
when _T_1946 :
node _T_1947 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_14.io.enq.bits, _T_1947
node _T_1948 = eq(UInt<4>(0hf), idx_29)
when _T_1948 :
node _T_1949 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_15.io.enq.bits, _T_1949
node _T_1950 = eq(UInt<5>(0h10), idx_29)
when _T_1950 :
node _T_1951 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_16.io.enq.bits, _T_1951
node _T_1952 = eq(UInt<5>(0h11), idx_29)
when _T_1952 :
node _T_1953 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_17.io.enq.bits, _T_1953
node _T_1954 = eq(UInt<5>(0h12), idx_29)
when _T_1954 :
node _T_1955 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_18.io.enq.bits, _T_1955
node _T_1956 = eq(UInt<5>(0h13), idx_29)
when _T_1956 :
node _T_1957 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_19.io.enq.bits, _T_1957
node _T_1958 = eq(UInt<5>(0h14), idx_29)
when _T_1958 :
node _T_1959 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_20.io.enq.bits, _T_1959
node _T_1960 = eq(UInt<5>(0h15), idx_29)
when _T_1960 :
node _T_1961 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_21.io.enq.bits, _T_1961
node _T_1962 = eq(UInt<5>(0h16), idx_29)
when _T_1962 :
node _T_1963 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_22.io.enq.bits, _T_1963
node _T_1964 = eq(UInt<5>(0h17), idx_29)
when _T_1964 :
node _T_1965 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_23.io.enq.bits, _T_1965
node _T_1966 = eq(UInt<5>(0h18), idx_29)
when _T_1966 :
node _T_1967 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_24.io.enq.bits, _T_1967
node _T_1968 = eq(UInt<5>(0h19), idx_29)
when _T_1968 :
node _T_1969 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_25.io.enq.bits, _T_1969
node _T_1970 = eq(UInt<5>(0h1a), idx_29)
when _T_1970 :
node _T_1971 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_26.io.enq.bits, _T_1971
node _T_1972 = eq(UInt<5>(0h1b), idx_29)
when _T_1972 :
node _T_1973 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_27.io.enq.bits, _T_1973
node _T_1974 = eq(UInt<5>(0h1c), idx_29)
when _T_1974 :
node _T_1975 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_28.io.enq.bits, _T_1975
node _T_1976 = eq(UInt<5>(0h1d), idx_29)
when _T_1976 :
node _T_1977 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_29.io.enq.bits, _T_1977
node _T_1978 = eq(UInt<5>(0h1e), idx_29)
when _T_1978 :
node _T_1979 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_30.io.enq.bits, _T_1979
node _T_1980 = eq(UInt<5>(0h1f), idx_29)
when _T_1980 :
node _T_1981 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_31.io.enq.bits, _T_1981
node _idx_T_150 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_151 = sub(_idx_T_150, write_start_index)
node _idx_T_152 = asUInt(_idx_T_151)
node _idx_T_153 = sub(_idx_T_152, UInt<5>(0h1e))
node _idx_T_154 = asUInt(_idx_T_153)
node idx_30 = rem(_idx_T_154, UInt<6>(0h20))
node _T_1982 = eq(UInt<1>(0h0), idx_30)
when _T_1982 :
node _T_1983 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8.io.enq.bits, _T_1983
node _T_1984 = eq(UInt<1>(0h1), idx_30)
when _T_1984 :
node _T_1985 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_1.io.enq.bits, _T_1985
node _T_1986 = eq(UInt<2>(0h2), idx_30)
when _T_1986 :
node _T_1987 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_2.io.enq.bits, _T_1987
node _T_1988 = eq(UInt<2>(0h3), idx_30)
when _T_1988 :
node _T_1989 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_3.io.enq.bits, _T_1989
node _T_1990 = eq(UInt<3>(0h4), idx_30)
when _T_1990 :
node _T_1991 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_4.io.enq.bits, _T_1991
node _T_1992 = eq(UInt<3>(0h5), idx_30)
when _T_1992 :
node _T_1993 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_5.io.enq.bits, _T_1993
node _T_1994 = eq(UInt<3>(0h6), idx_30)
when _T_1994 :
node _T_1995 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_6.io.enq.bits, _T_1995
node _T_1996 = eq(UInt<3>(0h7), idx_30)
when _T_1996 :
node _T_1997 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_7.io.enq.bits, _T_1997
node _T_1998 = eq(UInt<4>(0h8), idx_30)
when _T_1998 :
node _T_1999 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_8.io.enq.bits, _T_1999
node _T_2000 = eq(UInt<4>(0h9), idx_30)
when _T_2000 :
node _T_2001 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_9.io.enq.bits, _T_2001
node _T_2002 = eq(UInt<4>(0ha), idx_30)
when _T_2002 :
node _T_2003 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_10.io.enq.bits, _T_2003
node _T_2004 = eq(UInt<4>(0hb), idx_30)
when _T_2004 :
node _T_2005 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_11.io.enq.bits, _T_2005
node _T_2006 = eq(UInt<4>(0hc), idx_30)
when _T_2006 :
node _T_2007 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_12.io.enq.bits, _T_2007
node _T_2008 = eq(UInt<4>(0hd), idx_30)
when _T_2008 :
node _T_2009 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_13.io.enq.bits, _T_2009
node _T_2010 = eq(UInt<4>(0he), idx_30)
when _T_2010 :
node _T_2011 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_14.io.enq.bits, _T_2011
node _T_2012 = eq(UInt<4>(0hf), idx_30)
when _T_2012 :
node _T_2013 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_15.io.enq.bits, _T_2013
node _T_2014 = eq(UInt<5>(0h10), idx_30)
when _T_2014 :
node _T_2015 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_16.io.enq.bits, _T_2015
node _T_2016 = eq(UInt<5>(0h11), idx_30)
when _T_2016 :
node _T_2017 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_17.io.enq.bits, _T_2017
node _T_2018 = eq(UInt<5>(0h12), idx_30)
when _T_2018 :
node _T_2019 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_18.io.enq.bits, _T_2019
node _T_2020 = eq(UInt<5>(0h13), idx_30)
when _T_2020 :
node _T_2021 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_19.io.enq.bits, _T_2021
node _T_2022 = eq(UInt<5>(0h14), idx_30)
when _T_2022 :
node _T_2023 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_20.io.enq.bits, _T_2023
node _T_2024 = eq(UInt<5>(0h15), idx_30)
when _T_2024 :
node _T_2025 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_21.io.enq.bits, _T_2025
node _T_2026 = eq(UInt<5>(0h16), idx_30)
when _T_2026 :
node _T_2027 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_22.io.enq.bits, _T_2027
node _T_2028 = eq(UInt<5>(0h17), idx_30)
when _T_2028 :
node _T_2029 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_23.io.enq.bits, _T_2029
node _T_2030 = eq(UInt<5>(0h18), idx_30)
when _T_2030 :
node _T_2031 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_24.io.enq.bits, _T_2031
node _T_2032 = eq(UInt<5>(0h19), idx_30)
when _T_2032 :
node _T_2033 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_25.io.enq.bits, _T_2033
node _T_2034 = eq(UInt<5>(0h1a), idx_30)
when _T_2034 :
node _T_2035 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_26.io.enq.bits, _T_2035
node _T_2036 = eq(UInt<5>(0h1b), idx_30)
when _T_2036 :
node _T_2037 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_27.io.enq.bits, _T_2037
node _T_2038 = eq(UInt<5>(0h1c), idx_30)
when _T_2038 :
node _T_2039 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_28.io.enq.bits, _T_2039
node _T_2040 = eq(UInt<5>(0h1d), idx_30)
when _T_2040 :
node _T_2041 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_29.io.enq.bits, _T_2041
node _T_2042 = eq(UInt<5>(0h1e), idx_30)
when _T_2042 :
node _T_2043 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_30.io.enq.bits, _T_2043
node _T_2044 = eq(UInt<5>(0h1f), idx_30)
when _T_2044 :
node _T_2045 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_31.io.enq.bits, _T_2045
node _idx_T_155 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _idx_T_156 = sub(_idx_T_155, write_start_index)
node _idx_T_157 = asUInt(_idx_T_156)
node _idx_T_158 = sub(_idx_T_157, UInt<5>(0h1f))
node _idx_T_159 = asUInt(_idx_T_158)
node idx_31 = rem(_idx_T_159, UInt<6>(0h20))
node _T_2046 = eq(UInt<1>(0h0), idx_31)
when _T_2046 :
node _T_2047 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8.io.enq.bits, _T_2047
node _T_2048 = eq(UInt<1>(0h1), idx_31)
when _T_2048 :
node _T_2049 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_1.io.enq.bits, _T_2049
node _T_2050 = eq(UInt<2>(0h2), idx_31)
when _T_2050 :
node _T_2051 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_2.io.enq.bits, _T_2051
node _T_2052 = eq(UInt<2>(0h3), idx_31)
when _T_2052 :
node _T_2053 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_3.io.enq.bits, _T_2053
node _T_2054 = eq(UInt<3>(0h4), idx_31)
when _T_2054 :
node _T_2055 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_4.io.enq.bits, _T_2055
node _T_2056 = eq(UInt<3>(0h5), idx_31)
when _T_2056 :
node _T_2057 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_5.io.enq.bits, _T_2057
node _T_2058 = eq(UInt<3>(0h6), idx_31)
when _T_2058 :
node _T_2059 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_6.io.enq.bits, _T_2059
node _T_2060 = eq(UInt<3>(0h7), idx_31)
when _T_2060 :
node _T_2061 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_7.io.enq.bits, _T_2061
node _T_2062 = eq(UInt<4>(0h8), idx_31)
when _T_2062 :
node _T_2063 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_8.io.enq.bits, _T_2063
node _T_2064 = eq(UInt<4>(0h9), idx_31)
when _T_2064 :
node _T_2065 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_9.io.enq.bits, _T_2065
node _T_2066 = eq(UInt<4>(0ha), idx_31)
when _T_2066 :
node _T_2067 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_10.io.enq.bits, _T_2067
node _T_2068 = eq(UInt<4>(0hb), idx_31)
when _T_2068 :
node _T_2069 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_11.io.enq.bits, _T_2069
node _T_2070 = eq(UInt<4>(0hc), idx_31)
when _T_2070 :
node _T_2071 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_12.io.enq.bits, _T_2071
node _T_2072 = eq(UInt<4>(0hd), idx_31)
when _T_2072 :
node _T_2073 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_13.io.enq.bits, _T_2073
node _T_2074 = eq(UInt<4>(0he), idx_31)
when _T_2074 :
node _T_2075 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_14.io.enq.bits, _T_2075
node _T_2076 = eq(UInt<4>(0hf), idx_31)
when _T_2076 :
node _T_2077 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_15.io.enq.bits, _T_2077
node _T_2078 = eq(UInt<5>(0h10), idx_31)
when _T_2078 :
node _T_2079 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_16.io.enq.bits, _T_2079
node _T_2080 = eq(UInt<5>(0h11), idx_31)
when _T_2080 :
node _T_2081 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_17.io.enq.bits, _T_2081
node _T_2082 = eq(UInt<5>(0h12), idx_31)
when _T_2082 :
node _T_2083 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_18.io.enq.bits, _T_2083
node _T_2084 = eq(UInt<5>(0h13), idx_31)
when _T_2084 :
node _T_2085 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_19.io.enq.bits, _T_2085
node _T_2086 = eq(UInt<5>(0h14), idx_31)
when _T_2086 :
node _T_2087 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_20.io.enq.bits, _T_2087
node _T_2088 = eq(UInt<5>(0h15), idx_31)
when _T_2088 :
node _T_2089 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_21.io.enq.bits, _T_2089
node _T_2090 = eq(UInt<5>(0h16), idx_31)
when _T_2090 :
node _T_2091 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_22.io.enq.bits, _T_2091
node _T_2092 = eq(UInt<5>(0h17), idx_31)
when _T_2092 :
node _T_2093 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_23.io.enq.bits, _T_2093
node _T_2094 = eq(UInt<5>(0h18), idx_31)
when _T_2094 :
node _T_2095 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_24.io.enq.bits, _T_2095
node _T_2096 = eq(UInt<5>(0h19), idx_31)
when _T_2096 :
node _T_2097 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_25.io.enq.bits, _T_2097
node _T_2098 = eq(UInt<5>(0h1a), idx_31)
when _T_2098 :
node _T_2099 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_26.io.enq.bits, _T_2099
node _T_2100 = eq(UInt<5>(0h1b), idx_31)
when _T_2100 :
node _T_2101 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_27.io.enq.bits, _T_2101
node _T_2102 = eq(UInt<5>(0h1c), idx_31)
when _T_2102 :
node _T_2103 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_28.io.enq.bits, _T_2103
node _T_2104 = eq(UInt<5>(0h1d), idx_31)
when _T_2104 :
node _T_2105 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_29.io.enq.bits, _T_2105
node _T_2106 = eq(UInt<5>(0h1e), idx_31)
when _T_2106 :
node _T_2107 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_30.io.enq.bits, _T_2107
node _T_2108 = eq(UInt<5>(0h1f), idx_31)
when _T_2108 :
node _T_2109 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_31.io.enq.bits, _T_2109
node _len_to_write_T = sub(load_info_queue.io.deq.bits.end_byte, load_info_queue.io.deq.bits.start_byte)
node _len_to_write_T_1 = tail(_len_to_write_T, 1)
node len_to_write = add(_len_to_write_T_1, UInt<1>(0h1))
node _wrap_len_index_wide_T = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _wrap_len_index_wide_T_1 = sub(_wrap_len_index_wide_T, write_start_index)
node _wrap_len_index_wide_T_2 = asUInt(_wrap_len_index_wide_T_1)
node _wrap_len_index_wide_T_3 = sub(_wrap_len_index_wide_T_2, len_to_write)
node wrap_len_index_wide = asUInt(_wrap_len_index_wide_T_3)
node wrap_len_index_end = rem(wrap_len_index_wide, UInt<6>(0h20))
node wrapped = lt(wrap_len_index_wide, MAX_QUEUE_IDX)
when load_info_queue.io.deq.valid :
regreset loginfo_cycles_13 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_26 = add(loginfo_cycles_13, UInt<1>(0h1))
node _loginfo_cycles_T_27 = tail(_loginfo_cycles_T_26, 1)
connect loginfo_cycles_13, _loginfo_cycles_T_27
node _T_2110 = asUInt(reset)
node _T_2111 = eq(_T_2110, UInt<1>(0h0))
when _T_2111 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_13) : printf_26
node _T_2112 = asUInt(reset)
node _T_2113 = eq(_T_2112, UInt<1>(0h0))
when _T_2113 :
printf(clock, UInt<1>(0h1), "seq-revmemloader start %x, end %x\n", load_info_queue.io.deq.bits.start_byte, load_info_queue.io.deq.bits.end_byte) : printf_27
node _all_queues_ready_T = and(Queue64_UInt8.io.enq.ready, Queue64_UInt8_1.io.enq.ready)
node _all_queues_ready_T_1 = and(_all_queues_ready_T, Queue64_UInt8_2.io.enq.ready)
node _all_queues_ready_T_2 = and(_all_queues_ready_T_1, Queue64_UInt8_3.io.enq.ready)
node _all_queues_ready_T_3 = and(_all_queues_ready_T_2, Queue64_UInt8_4.io.enq.ready)
node _all_queues_ready_T_4 = and(_all_queues_ready_T_3, Queue64_UInt8_5.io.enq.ready)
node _all_queues_ready_T_5 = and(_all_queues_ready_T_4, Queue64_UInt8_6.io.enq.ready)
node _all_queues_ready_T_6 = and(_all_queues_ready_T_5, Queue64_UInt8_7.io.enq.ready)
node _all_queues_ready_T_7 = and(_all_queues_ready_T_6, Queue64_UInt8_8.io.enq.ready)
node _all_queues_ready_T_8 = and(_all_queues_ready_T_7, Queue64_UInt8_9.io.enq.ready)
node _all_queues_ready_T_9 = and(_all_queues_ready_T_8, Queue64_UInt8_10.io.enq.ready)
node _all_queues_ready_T_10 = and(_all_queues_ready_T_9, Queue64_UInt8_11.io.enq.ready)
node _all_queues_ready_T_11 = and(_all_queues_ready_T_10, Queue64_UInt8_12.io.enq.ready)
node _all_queues_ready_T_12 = and(_all_queues_ready_T_11, Queue64_UInt8_13.io.enq.ready)
node _all_queues_ready_T_13 = and(_all_queues_ready_T_12, Queue64_UInt8_14.io.enq.ready)
node _all_queues_ready_T_14 = and(_all_queues_ready_T_13, Queue64_UInt8_15.io.enq.ready)
node _all_queues_ready_T_15 = and(_all_queues_ready_T_14, Queue64_UInt8_16.io.enq.ready)
node _all_queues_ready_T_16 = and(_all_queues_ready_T_15, Queue64_UInt8_17.io.enq.ready)
node _all_queues_ready_T_17 = and(_all_queues_ready_T_16, Queue64_UInt8_18.io.enq.ready)
node _all_queues_ready_T_18 = and(_all_queues_ready_T_17, Queue64_UInt8_19.io.enq.ready)
node _all_queues_ready_T_19 = and(_all_queues_ready_T_18, Queue64_UInt8_20.io.enq.ready)
node _all_queues_ready_T_20 = and(_all_queues_ready_T_19, Queue64_UInt8_21.io.enq.ready)
node _all_queues_ready_T_21 = and(_all_queues_ready_T_20, Queue64_UInt8_22.io.enq.ready)
node _all_queues_ready_T_22 = and(_all_queues_ready_T_21, Queue64_UInt8_23.io.enq.ready)
node _all_queues_ready_T_23 = and(_all_queues_ready_T_22, Queue64_UInt8_24.io.enq.ready)
node _all_queues_ready_T_24 = and(_all_queues_ready_T_23, Queue64_UInt8_25.io.enq.ready)
node _all_queues_ready_T_25 = and(_all_queues_ready_T_24, Queue64_UInt8_26.io.enq.ready)
node _all_queues_ready_T_26 = and(_all_queues_ready_T_25, Queue64_UInt8_27.io.enq.ready)
node _all_queues_ready_T_27 = and(_all_queues_ready_T_26, Queue64_UInt8_28.io.enq.ready)
node _all_queues_ready_T_28 = and(_all_queues_ready_T_27, Queue64_UInt8_29.io.enq.ready)
node _all_queues_ready_T_29 = and(_all_queues_ready_T_28, Queue64_UInt8_30.io.enq.ready)
node all_queues_ready = and(_all_queues_ready_T_29, Queue64_UInt8_31.io.enq.ready)
node _load_info_queue_io_deq_ready_T = and(io.l2helperUser.resp.valid, all_queues_ready)
connect load_info_queue.io.deq.ready, _load_info_queue_io_deq_ready_T
node _io_l2helperUser_resp_ready_T = and(load_info_queue.io.deq.valid, all_queues_ready)
connect io.l2helperUser.resp.ready, _io_l2helperUser_resp_ready_T
node _resp_fire_allqueues_T = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node resp_fire_allqueues = and(_resp_fire_allqueues_T, all_queues_ready)
when resp_fire_allqueues :
node _write_start_index_T = sub(MAX_QUEUE_IDX, wrap_len_index_end)
node _write_start_index_T_1 = tail(_write_start_index_T, 1)
connect write_start_index, _write_start_index_T_1
node _use_this_queue_T = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_1 = tail(_use_this_queue_T, 1)
node _use_this_queue_T_2 = leq(UInt<1>(0h0), _use_this_queue_T_1)
node _use_this_queue_T_3 = gt(UInt<1>(0h0), wrap_len_index_end)
node _use_this_queue_T_4 = or(_use_this_queue_T_2, _use_this_queue_T_3)
node _use_this_queue_T_5 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_6 = tail(_use_this_queue_T_5, 1)
node _use_this_queue_T_7 = leq(UInt<1>(0h0), _use_this_queue_T_6)
node _use_this_queue_T_8 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_9 = tail(_use_this_queue_T_8, 1)
node _use_this_queue_T_10 = sub(_use_this_queue_T_9, len_to_write)
node _use_this_queue_T_11 = tail(_use_this_queue_T_10, 1)
node _use_this_queue_T_12 = geq(UInt<1>(0h0), _use_this_queue_T_11)
node _use_this_queue_T_13 = and(_use_this_queue_T_7, _use_this_queue_T_12)
node use_this_queue = mux(wrapped, _use_this_queue_T_4, _use_this_queue_T_13)
node _cur_queue_valid_T = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_1 = and(_cur_queue_valid_T, use_this_queue)
node cur_queue_valid = and(_cur_queue_valid_T_1, all_queues_ready)
connect Queue64_UInt8.io.enq.valid, cur_queue_valid
node _use_this_queue_T_14 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_15 = tail(_use_this_queue_T_14, 1)
node _use_this_queue_T_16 = leq(UInt<1>(0h1), _use_this_queue_T_15)
node _use_this_queue_T_17 = gt(UInt<1>(0h1), wrap_len_index_end)
node _use_this_queue_T_18 = or(_use_this_queue_T_16, _use_this_queue_T_17)
node _use_this_queue_T_19 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_20 = tail(_use_this_queue_T_19, 1)
node _use_this_queue_T_21 = leq(UInt<1>(0h1), _use_this_queue_T_20)
node _use_this_queue_T_22 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_23 = tail(_use_this_queue_T_22, 1)
node _use_this_queue_T_24 = sub(_use_this_queue_T_23, len_to_write)
node _use_this_queue_T_25 = tail(_use_this_queue_T_24, 1)
node _use_this_queue_T_26 = geq(UInt<1>(0h1), _use_this_queue_T_25)
node _use_this_queue_T_27 = and(_use_this_queue_T_21, _use_this_queue_T_26)
node use_this_queue_1 = mux(wrapped, _use_this_queue_T_18, _use_this_queue_T_27)
node _cur_queue_valid_T_2 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_3 = and(_cur_queue_valid_T_2, use_this_queue_1)
node cur_queue_valid_1 = and(_cur_queue_valid_T_3, all_queues_ready)
connect Queue64_UInt8_1.io.enq.valid, cur_queue_valid_1
node _use_this_queue_T_28 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_29 = tail(_use_this_queue_T_28, 1)
node _use_this_queue_T_30 = leq(UInt<2>(0h2), _use_this_queue_T_29)
node _use_this_queue_T_31 = gt(UInt<2>(0h2), wrap_len_index_end)
node _use_this_queue_T_32 = or(_use_this_queue_T_30, _use_this_queue_T_31)
node _use_this_queue_T_33 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_34 = tail(_use_this_queue_T_33, 1)
node _use_this_queue_T_35 = leq(UInt<2>(0h2), _use_this_queue_T_34)
node _use_this_queue_T_36 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_37 = tail(_use_this_queue_T_36, 1)
node _use_this_queue_T_38 = sub(_use_this_queue_T_37, len_to_write)
node _use_this_queue_T_39 = tail(_use_this_queue_T_38, 1)
node _use_this_queue_T_40 = geq(UInt<2>(0h2), _use_this_queue_T_39)
node _use_this_queue_T_41 = and(_use_this_queue_T_35, _use_this_queue_T_40)
node use_this_queue_2 = mux(wrapped, _use_this_queue_T_32, _use_this_queue_T_41)
node _cur_queue_valid_T_4 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_5 = and(_cur_queue_valid_T_4, use_this_queue_2)
node cur_queue_valid_2 = and(_cur_queue_valid_T_5, all_queues_ready)
connect Queue64_UInt8_2.io.enq.valid, cur_queue_valid_2
node _use_this_queue_T_42 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_43 = tail(_use_this_queue_T_42, 1)
node _use_this_queue_T_44 = leq(UInt<2>(0h3), _use_this_queue_T_43)
node _use_this_queue_T_45 = gt(UInt<2>(0h3), wrap_len_index_end)
node _use_this_queue_T_46 = or(_use_this_queue_T_44, _use_this_queue_T_45)
node _use_this_queue_T_47 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_48 = tail(_use_this_queue_T_47, 1)
node _use_this_queue_T_49 = leq(UInt<2>(0h3), _use_this_queue_T_48)
node _use_this_queue_T_50 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_51 = tail(_use_this_queue_T_50, 1)
node _use_this_queue_T_52 = sub(_use_this_queue_T_51, len_to_write)
node _use_this_queue_T_53 = tail(_use_this_queue_T_52, 1)
node _use_this_queue_T_54 = geq(UInt<2>(0h3), _use_this_queue_T_53)
node _use_this_queue_T_55 = and(_use_this_queue_T_49, _use_this_queue_T_54)
node use_this_queue_3 = mux(wrapped, _use_this_queue_T_46, _use_this_queue_T_55)
node _cur_queue_valid_T_6 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_7 = and(_cur_queue_valid_T_6, use_this_queue_3)
node cur_queue_valid_3 = and(_cur_queue_valid_T_7, all_queues_ready)
connect Queue64_UInt8_3.io.enq.valid, cur_queue_valid_3
node _use_this_queue_T_56 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_57 = tail(_use_this_queue_T_56, 1)
node _use_this_queue_T_58 = leq(UInt<3>(0h4), _use_this_queue_T_57)
node _use_this_queue_T_59 = gt(UInt<3>(0h4), wrap_len_index_end)
node _use_this_queue_T_60 = or(_use_this_queue_T_58, _use_this_queue_T_59)
node _use_this_queue_T_61 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_62 = tail(_use_this_queue_T_61, 1)
node _use_this_queue_T_63 = leq(UInt<3>(0h4), _use_this_queue_T_62)
node _use_this_queue_T_64 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_65 = tail(_use_this_queue_T_64, 1)
node _use_this_queue_T_66 = sub(_use_this_queue_T_65, len_to_write)
node _use_this_queue_T_67 = tail(_use_this_queue_T_66, 1)
node _use_this_queue_T_68 = geq(UInt<3>(0h4), _use_this_queue_T_67)
node _use_this_queue_T_69 = and(_use_this_queue_T_63, _use_this_queue_T_68)
node use_this_queue_4 = mux(wrapped, _use_this_queue_T_60, _use_this_queue_T_69)
node _cur_queue_valid_T_8 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_9 = and(_cur_queue_valid_T_8, use_this_queue_4)
node cur_queue_valid_4 = and(_cur_queue_valid_T_9, all_queues_ready)
connect Queue64_UInt8_4.io.enq.valid, cur_queue_valid_4
node _use_this_queue_T_70 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_71 = tail(_use_this_queue_T_70, 1)
node _use_this_queue_T_72 = leq(UInt<3>(0h5), _use_this_queue_T_71)
node _use_this_queue_T_73 = gt(UInt<3>(0h5), wrap_len_index_end)
node _use_this_queue_T_74 = or(_use_this_queue_T_72, _use_this_queue_T_73)
node _use_this_queue_T_75 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_76 = tail(_use_this_queue_T_75, 1)
node _use_this_queue_T_77 = leq(UInt<3>(0h5), _use_this_queue_T_76)
node _use_this_queue_T_78 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_79 = tail(_use_this_queue_T_78, 1)
node _use_this_queue_T_80 = sub(_use_this_queue_T_79, len_to_write)
node _use_this_queue_T_81 = tail(_use_this_queue_T_80, 1)
node _use_this_queue_T_82 = geq(UInt<3>(0h5), _use_this_queue_T_81)
node _use_this_queue_T_83 = and(_use_this_queue_T_77, _use_this_queue_T_82)
node use_this_queue_5 = mux(wrapped, _use_this_queue_T_74, _use_this_queue_T_83)
node _cur_queue_valid_T_10 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_11 = and(_cur_queue_valid_T_10, use_this_queue_5)
node cur_queue_valid_5 = and(_cur_queue_valid_T_11, all_queues_ready)
connect Queue64_UInt8_5.io.enq.valid, cur_queue_valid_5
node _use_this_queue_T_84 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_85 = tail(_use_this_queue_T_84, 1)
node _use_this_queue_T_86 = leq(UInt<3>(0h6), _use_this_queue_T_85)
node _use_this_queue_T_87 = gt(UInt<3>(0h6), wrap_len_index_end)
node _use_this_queue_T_88 = or(_use_this_queue_T_86, _use_this_queue_T_87)
node _use_this_queue_T_89 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_90 = tail(_use_this_queue_T_89, 1)
node _use_this_queue_T_91 = leq(UInt<3>(0h6), _use_this_queue_T_90)
node _use_this_queue_T_92 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_93 = tail(_use_this_queue_T_92, 1)
node _use_this_queue_T_94 = sub(_use_this_queue_T_93, len_to_write)
node _use_this_queue_T_95 = tail(_use_this_queue_T_94, 1)
node _use_this_queue_T_96 = geq(UInt<3>(0h6), _use_this_queue_T_95)
node _use_this_queue_T_97 = and(_use_this_queue_T_91, _use_this_queue_T_96)
node use_this_queue_6 = mux(wrapped, _use_this_queue_T_88, _use_this_queue_T_97)
node _cur_queue_valid_T_12 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_13 = and(_cur_queue_valid_T_12, use_this_queue_6)
node cur_queue_valid_6 = and(_cur_queue_valid_T_13, all_queues_ready)
connect Queue64_UInt8_6.io.enq.valid, cur_queue_valid_6
node _use_this_queue_T_98 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_99 = tail(_use_this_queue_T_98, 1)
node _use_this_queue_T_100 = leq(UInt<3>(0h7), _use_this_queue_T_99)
node _use_this_queue_T_101 = gt(UInt<3>(0h7), wrap_len_index_end)
node _use_this_queue_T_102 = or(_use_this_queue_T_100, _use_this_queue_T_101)
node _use_this_queue_T_103 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_104 = tail(_use_this_queue_T_103, 1)
node _use_this_queue_T_105 = leq(UInt<3>(0h7), _use_this_queue_T_104)
node _use_this_queue_T_106 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_107 = tail(_use_this_queue_T_106, 1)
node _use_this_queue_T_108 = sub(_use_this_queue_T_107, len_to_write)
node _use_this_queue_T_109 = tail(_use_this_queue_T_108, 1)
node _use_this_queue_T_110 = geq(UInt<3>(0h7), _use_this_queue_T_109)
node _use_this_queue_T_111 = and(_use_this_queue_T_105, _use_this_queue_T_110)
node use_this_queue_7 = mux(wrapped, _use_this_queue_T_102, _use_this_queue_T_111)
node _cur_queue_valid_T_14 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_15 = and(_cur_queue_valid_T_14, use_this_queue_7)
node cur_queue_valid_7 = and(_cur_queue_valid_T_15, all_queues_ready)
connect Queue64_UInt8_7.io.enq.valid, cur_queue_valid_7
node _use_this_queue_T_112 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_113 = tail(_use_this_queue_T_112, 1)
node _use_this_queue_T_114 = leq(UInt<4>(0h8), _use_this_queue_T_113)
node _use_this_queue_T_115 = gt(UInt<4>(0h8), wrap_len_index_end)
node _use_this_queue_T_116 = or(_use_this_queue_T_114, _use_this_queue_T_115)
node _use_this_queue_T_117 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_118 = tail(_use_this_queue_T_117, 1)
node _use_this_queue_T_119 = leq(UInt<4>(0h8), _use_this_queue_T_118)
node _use_this_queue_T_120 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_121 = tail(_use_this_queue_T_120, 1)
node _use_this_queue_T_122 = sub(_use_this_queue_T_121, len_to_write)
node _use_this_queue_T_123 = tail(_use_this_queue_T_122, 1)
node _use_this_queue_T_124 = geq(UInt<4>(0h8), _use_this_queue_T_123)
node _use_this_queue_T_125 = and(_use_this_queue_T_119, _use_this_queue_T_124)
node use_this_queue_8 = mux(wrapped, _use_this_queue_T_116, _use_this_queue_T_125)
node _cur_queue_valid_T_16 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_17 = and(_cur_queue_valid_T_16, use_this_queue_8)
node cur_queue_valid_8 = and(_cur_queue_valid_T_17, all_queues_ready)
connect Queue64_UInt8_8.io.enq.valid, cur_queue_valid_8
node _use_this_queue_T_126 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_127 = tail(_use_this_queue_T_126, 1)
node _use_this_queue_T_128 = leq(UInt<4>(0h9), _use_this_queue_T_127)
node _use_this_queue_T_129 = gt(UInt<4>(0h9), wrap_len_index_end)
node _use_this_queue_T_130 = or(_use_this_queue_T_128, _use_this_queue_T_129)
node _use_this_queue_T_131 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_132 = tail(_use_this_queue_T_131, 1)
node _use_this_queue_T_133 = leq(UInt<4>(0h9), _use_this_queue_T_132)
node _use_this_queue_T_134 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_135 = tail(_use_this_queue_T_134, 1)
node _use_this_queue_T_136 = sub(_use_this_queue_T_135, len_to_write)
node _use_this_queue_T_137 = tail(_use_this_queue_T_136, 1)
node _use_this_queue_T_138 = geq(UInt<4>(0h9), _use_this_queue_T_137)
node _use_this_queue_T_139 = and(_use_this_queue_T_133, _use_this_queue_T_138)
node use_this_queue_9 = mux(wrapped, _use_this_queue_T_130, _use_this_queue_T_139)
node _cur_queue_valid_T_18 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_19 = and(_cur_queue_valid_T_18, use_this_queue_9)
node cur_queue_valid_9 = and(_cur_queue_valid_T_19, all_queues_ready)
connect Queue64_UInt8_9.io.enq.valid, cur_queue_valid_9
node _use_this_queue_T_140 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_141 = tail(_use_this_queue_T_140, 1)
node _use_this_queue_T_142 = leq(UInt<4>(0ha), _use_this_queue_T_141)
node _use_this_queue_T_143 = gt(UInt<4>(0ha), wrap_len_index_end)
node _use_this_queue_T_144 = or(_use_this_queue_T_142, _use_this_queue_T_143)
node _use_this_queue_T_145 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_146 = tail(_use_this_queue_T_145, 1)
node _use_this_queue_T_147 = leq(UInt<4>(0ha), _use_this_queue_T_146)
node _use_this_queue_T_148 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_149 = tail(_use_this_queue_T_148, 1)
node _use_this_queue_T_150 = sub(_use_this_queue_T_149, len_to_write)
node _use_this_queue_T_151 = tail(_use_this_queue_T_150, 1)
node _use_this_queue_T_152 = geq(UInt<4>(0ha), _use_this_queue_T_151)
node _use_this_queue_T_153 = and(_use_this_queue_T_147, _use_this_queue_T_152)
node use_this_queue_10 = mux(wrapped, _use_this_queue_T_144, _use_this_queue_T_153)
node _cur_queue_valid_T_20 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_21 = and(_cur_queue_valid_T_20, use_this_queue_10)
node cur_queue_valid_10 = and(_cur_queue_valid_T_21, all_queues_ready)
connect Queue64_UInt8_10.io.enq.valid, cur_queue_valid_10
node _use_this_queue_T_154 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_155 = tail(_use_this_queue_T_154, 1)
node _use_this_queue_T_156 = leq(UInt<4>(0hb), _use_this_queue_T_155)
node _use_this_queue_T_157 = gt(UInt<4>(0hb), wrap_len_index_end)
node _use_this_queue_T_158 = or(_use_this_queue_T_156, _use_this_queue_T_157)
node _use_this_queue_T_159 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_160 = tail(_use_this_queue_T_159, 1)
node _use_this_queue_T_161 = leq(UInt<4>(0hb), _use_this_queue_T_160)
node _use_this_queue_T_162 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_163 = tail(_use_this_queue_T_162, 1)
node _use_this_queue_T_164 = sub(_use_this_queue_T_163, len_to_write)
node _use_this_queue_T_165 = tail(_use_this_queue_T_164, 1)
node _use_this_queue_T_166 = geq(UInt<4>(0hb), _use_this_queue_T_165)
node _use_this_queue_T_167 = and(_use_this_queue_T_161, _use_this_queue_T_166)
node use_this_queue_11 = mux(wrapped, _use_this_queue_T_158, _use_this_queue_T_167)
node _cur_queue_valid_T_22 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_23 = and(_cur_queue_valid_T_22, use_this_queue_11)
node cur_queue_valid_11 = and(_cur_queue_valid_T_23, all_queues_ready)
connect Queue64_UInt8_11.io.enq.valid, cur_queue_valid_11
node _use_this_queue_T_168 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_169 = tail(_use_this_queue_T_168, 1)
node _use_this_queue_T_170 = leq(UInt<4>(0hc), _use_this_queue_T_169)
node _use_this_queue_T_171 = gt(UInt<4>(0hc), wrap_len_index_end)
node _use_this_queue_T_172 = or(_use_this_queue_T_170, _use_this_queue_T_171)
node _use_this_queue_T_173 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_174 = tail(_use_this_queue_T_173, 1)
node _use_this_queue_T_175 = leq(UInt<4>(0hc), _use_this_queue_T_174)
node _use_this_queue_T_176 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_177 = tail(_use_this_queue_T_176, 1)
node _use_this_queue_T_178 = sub(_use_this_queue_T_177, len_to_write)
node _use_this_queue_T_179 = tail(_use_this_queue_T_178, 1)
node _use_this_queue_T_180 = geq(UInt<4>(0hc), _use_this_queue_T_179)
node _use_this_queue_T_181 = and(_use_this_queue_T_175, _use_this_queue_T_180)
node use_this_queue_12 = mux(wrapped, _use_this_queue_T_172, _use_this_queue_T_181)
node _cur_queue_valid_T_24 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_25 = and(_cur_queue_valid_T_24, use_this_queue_12)
node cur_queue_valid_12 = and(_cur_queue_valid_T_25, all_queues_ready)
connect Queue64_UInt8_12.io.enq.valid, cur_queue_valid_12
node _use_this_queue_T_182 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_183 = tail(_use_this_queue_T_182, 1)
node _use_this_queue_T_184 = leq(UInt<4>(0hd), _use_this_queue_T_183)
node _use_this_queue_T_185 = gt(UInt<4>(0hd), wrap_len_index_end)
node _use_this_queue_T_186 = or(_use_this_queue_T_184, _use_this_queue_T_185)
node _use_this_queue_T_187 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_188 = tail(_use_this_queue_T_187, 1)
node _use_this_queue_T_189 = leq(UInt<4>(0hd), _use_this_queue_T_188)
node _use_this_queue_T_190 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_191 = tail(_use_this_queue_T_190, 1)
node _use_this_queue_T_192 = sub(_use_this_queue_T_191, len_to_write)
node _use_this_queue_T_193 = tail(_use_this_queue_T_192, 1)
node _use_this_queue_T_194 = geq(UInt<4>(0hd), _use_this_queue_T_193)
node _use_this_queue_T_195 = and(_use_this_queue_T_189, _use_this_queue_T_194)
node use_this_queue_13 = mux(wrapped, _use_this_queue_T_186, _use_this_queue_T_195)
node _cur_queue_valid_T_26 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_27 = and(_cur_queue_valid_T_26, use_this_queue_13)
node cur_queue_valid_13 = and(_cur_queue_valid_T_27, all_queues_ready)
connect Queue64_UInt8_13.io.enq.valid, cur_queue_valid_13
node _use_this_queue_T_196 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_197 = tail(_use_this_queue_T_196, 1)
node _use_this_queue_T_198 = leq(UInt<4>(0he), _use_this_queue_T_197)
node _use_this_queue_T_199 = gt(UInt<4>(0he), wrap_len_index_end)
node _use_this_queue_T_200 = or(_use_this_queue_T_198, _use_this_queue_T_199)
node _use_this_queue_T_201 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_202 = tail(_use_this_queue_T_201, 1)
node _use_this_queue_T_203 = leq(UInt<4>(0he), _use_this_queue_T_202)
node _use_this_queue_T_204 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_205 = tail(_use_this_queue_T_204, 1)
node _use_this_queue_T_206 = sub(_use_this_queue_T_205, len_to_write)
node _use_this_queue_T_207 = tail(_use_this_queue_T_206, 1)
node _use_this_queue_T_208 = geq(UInt<4>(0he), _use_this_queue_T_207)
node _use_this_queue_T_209 = and(_use_this_queue_T_203, _use_this_queue_T_208)
node use_this_queue_14 = mux(wrapped, _use_this_queue_T_200, _use_this_queue_T_209)
node _cur_queue_valid_T_28 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_29 = and(_cur_queue_valid_T_28, use_this_queue_14)
node cur_queue_valid_14 = and(_cur_queue_valid_T_29, all_queues_ready)
connect Queue64_UInt8_14.io.enq.valid, cur_queue_valid_14
node _use_this_queue_T_210 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_211 = tail(_use_this_queue_T_210, 1)
node _use_this_queue_T_212 = leq(UInt<4>(0hf), _use_this_queue_T_211)
node _use_this_queue_T_213 = gt(UInt<4>(0hf), wrap_len_index_end)
node _use_this_queue_T_214 = or(_use_this_queue_T_212, _use_this_queue_T_213)
node _use_this_queue_T_215 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_216 = tail(_use_this_queue_T_215, 1)
node _use_this_queue_T_217 = leq(UInt<4>(0hf), _use_this_queue_T_216)
node _use_this_queue_T_218 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_219 = tail(_use_this_queue_T_218, 1)
node _use_this_queue_T_220 = sub(_use_this_queue_T_219, len_to_write)
node _use_this_queue_T_221 = tail(_use_this_queue_T_220, 1)
node _use_this_queue_T_222 = geq(UInt<4>(0hf), _use_this_queue_T_221)
node _use_this_queue_T_223 = and(_use_this_queue_T_217, _use_this_queue_T_222)
node use_this_queue_15 = mux(wrapped, _use_this_queue_T_214, _use_this_queue_T_223)
node _cur_queue_valid_T_30 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_31 = and(_cur_queue_valid_T_30, use_this_queue_15)
node cur_queue_valid_15 = and(_cur_queue_valid_T_31, all_queues_ready)
connect Queue64_UInt8_15.io.enq.valid, cur_queue_valid_15
node _use_this_queue_T_224 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_225 = tail(_use_this_queue_T_224, 1)
node _use_this_queue_T_226 = leq(UInt<5>(0h10), _use_this_queue_T_225)
node _use_this_queue_T_227 = gt(UInt<5>(0h10), wrap_len_index_end)
node _use_this_queue_T_228 = or(_use_this_queue_T_226, _use_this_queue_T_227)
node _use_this_queue_T_229 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_230 = tail(_use_this_queue_T_229, 1)
node _use_this_queue_T_231 = leq(UInt<5>(0h10), _use_this_queue_T_230)
node _use_this_queue_T_232 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_233 = tail(_use_this_queue_T_232, 1)
node _use_this_queue_T_234 = sub(_use_this_queue_T_233, len_to_write)
node _use_this_queue_T_235 = tail(_use_this_queue_T_234, 1)
node _use_this_queue_T_236 = geq(UInt<5>(0h10), _use_this_queue_T_235)
node _use_this_queue_T_237 = and(_use_this_queue_T_231, _use_this_queue_T_236)
node use_this_queue_16 = mux(wrapped, _use_this_queue_T_228, _use_this_queue_T_237)
node _cur_queue_valid_T_32 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_33 = and(_cur_queue_valid_T_32, use_this_queue_16)
node cur_queue_valid_16 = and(_cur_queue_valid_T_33, all_queues_ready)
connect Queue64_UInt8_16.io.enq.valid, cur_queue_valid_16
node _use_this_queue_T_238 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_239 = tail(_use_this_queue_T_238, 1)
node _use_this_queue_T_240 = leq(UInt<5>(0h11), _use_this_queue_T_239)
node _use_this_queue_T_241 = gt(UInt<5>(0h11), wrap_len_index_end)
node _use_this_queue_T_242 = or(_use_this_queue_T_240, _use_this_queue_T_241)
node _use_this_queue_T_243 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_244 = tail(_use_this_queue_T_243, 1)
node _use_this_queue_T_245 = leq(UInt<5>(0h11), _use_this_queue_T_244)
node _use_this_queue_T_246 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_247 = tail(_use_this_queue_T_246, 1)
node _use_this_queue_T_248 = sub(_use_this_queue_T_247, len_to_write)
node _use_this_queue_T_249 = tail(_use_this_queue_T_248, 1)
node _use_this_queue_T_250 = geq(UInt<5>(0h11), _use_this_queue_T_249)
node _use_this_queue_T_251 = and(_use_this_queue_T_245, _use_this_queue_T_250)
node use_this_queue_17 = mux(wrapped, _use_this_queue_T_242, _use_this_queue_T_251)
node _cur_queue_valid_T_34 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_35 = and(_cur_queue_valid_T_34, use_this_queue_17)
node cur_queue_valid_17 = and(_cur_queue_valid_T_35, all_queues_ready)
connect Queue64_UInt8_17.io.enq.valid, cur_queue_valid_17
node _use_this_queue_T_252 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_253 = tail(_use_this_queue_T_252, 1)
node _use_this_queue_T_254 = leq(UInt<5>(0h12), _use_this_queue_T_253)
node _use_this_queue_T_255 = gt(UInt<5>(0h12), wrap_len_index_end)
node _use_this_queue_T_256 = or(_use_this_queue_T_254, _use_this_queue_T_255)
node _use_this_queue_T_257 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_258 = tail(_use_this_queue_T_257, 1)
node _use_this_queue_T_259 = leq(UInt<5>(0h12), _use_this_queue_T_258)
node _use_this_queue_T_260 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_261 = tail(_use_this_queue_T_260, 1)
node _use_this_queue_T_262 = sub(_use_this_queue_T_261, len_to_write)
node _use_this_queue_T_263 = tail(_use_this_queue_T_262, 1)
node _use_this_queue_T_264 = geq(UInt<5>(0h12), _use_this_queue_T_263)
node _use_this_queue_T_265 = and(_use_this_queue_T_259, _use_this_queue_T_264)
node use_this_queue_18 = mux(wrapped, _use_this_queue_T_256, _use_this_queue_T_265)
node _cur_queue_valid_T_36 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_37 = and(_cur_queue_valid_T_36, use_this_queue_18)
node cur_queue_valid_18 = and(_cur_queue_valid_T_37, all_queues_ready)
connect Queue64_UInt8_18.io.enq.valid, cur_queue_valid_18
node _use_this_queue_T_266 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_267 = tail(_use_this_queue_T_266, 1)
node _use_this_queue_T_268 = leq(UInt<5>(0h13), _use_this_queue_T_267)
node _use_this_queue_T_269 = gt(UInt<5>(0h13), wrap_len_index_end)
node _use_this_queue_T_270 = or(_use_this_queue_T_268, _use_this_queue_T_269)
node _use_this_queue_T_271 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_272 = tail(_use_this_queue_T_271, 1)
node _use_this_queue_T_273 = leq(UInt<5>(0h13), _use_this_queue_T_272)
node _use_this_queue_T_274 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_275 = tail(_use_this_queue_T_274, 1)
node _use_this_queue_T_276 = sub(_use_this_queue_T_275, len_to_write)
node _use_this_queue_T_277 = tail(_use_this_queue_T_276, 1)
node _use_this_queue_T_278 = geq(UInt<5>(0h13), _use_this_queue_T_277)
node _use_this_queue_T_279 = and(_use_this_queue_T_273, _use_this_queue_T_278)
node use_this_queue_19 = mux(wrapped, _use_this_queue_T_270, _use_this_queue_T_279)
node _cur_queue_valid_T_38 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_39 = and(_cur_queue_valid_T_38, use_this_queue_19)
node cur_queue_valid_19 = and(_cur_queue_valid_T_39, all_queues_ready)
connect Queue64_UInt8_19.io.enq.valid, cur_queue_valid_19
node _use_this_queue_T_280 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_281 = tail(_use_this_queue_T_280, 1)
node _use_this_queue_T_282 = leq(UInt<5>(0h14), _use_this_queue_T_281)
node _use_this_queue_T_283 = gt(UInt<5>(0h14), wrap_len_index_end)
node _use_this_queue_T_284 = or(_use_this_queue_T_282, _use_this_queue_T_283)
node _use_this_queue_T_285 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_286 = tail(_use_this_queue_T_285, 1)
node _use_this_queue_T_287 = leq(UInt<5>(0h14), _use_this_queue_T_286)
node _use_this_queue_T_288 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_289 = tail(_use_this_queue_T_288, 1)
node _use_this_queue_T_290 = sub(_use_this_queue_T_289, len_to_write)
node _use_this_queue_T_291 = tail(_use_this_queue_T_290, 1)
node _use_this_queue_T_292 = geq(UInt<5>(0h14), _use_this_queue_T_291)
node _use_this_queue_T_293 = and(_use_this_queue_T_287, _use_this_queue_T_292)
node use_this_queue_20 = mux(wrapped, _use_this_queue_T_284, _use_this_queue_T_293)
node _cur_queue_valid_T_40 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_41 = and(_cur_queue_valid_T_40, use_this_queue_20)
node cur_queue_valid_20 = and(_cur_queue_valid_T_41, all_queues_ready)
connect Queue64_UInt8_20.io.enq.valid, cur_queue_valid_20
node _use_this_queue_T_294 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_295 = tail(_use_this_queue_T_294, 1)
node _use_this_queue_T_296 = leq(UInt<5>(0h15), _use_this_queue_T_295)
node _use_this_queue_T_297 = gt(UInt<5>(0h15), wrap_len_index_end)
node _use_this_queue_T_298 = or(_use_this_queue_T_296, _use_this_queue_T_297)
node _use_this_queue_T_299 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_300 = tail(_use_this_queue_T_299, 1)
node _use_this_queue_T_301 = leq(UInt<5>(0h15), _use_this_queue_T_300)
node _use_this_queue_T_302 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_303 = tail(_use_this_queue_T_302, 1)
node _use_this_queue_T_304 = sub(_use_this_queue_T_303, len_to_write)
node _use_this_queue_T_305 = tail(_use_this_queue_T_304, 1)
node _use_this_queue_T_306 = geq(UInt<5>(0h15), _use_this_queue_T_305)
node _use_this_queue_T_307 = and(_use_this_queue_T_301, _use_this_queue_T_306)
node use_this_queue_21 = mux(wrapped, _use_this_queue_T_298, _use_this_queue_T_307)
node _cur_queue_valid_T_42 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_43 = and(_cur_queue_valid_T_42, use_this_queue_21)
node cur_queue_valid_21 = and(_cur_queue_valid_T_43, all_queues_ready)
connect Queue64_UInt8_21.io.enq.valid, cur_queue_valid_21
node _use_this_queue_T_308 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_309 = tail(_use_this_queue_T_308, 1)
node _use_this_queue_T_310 = leq(UInt<5>(0h16), _use_this_queue_T_309)
node _use_this_queue_T_311 = gt(UInt<5>(0h16), wrap_len_index_end)
node _use_this_queue_T_312 = or(_use_this_queue_T_310, _use_this_queue_T_311)
node _use_this_queue_T_313 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_314 = tail(_use_this_queue_T_313, 1)
node _use_this_queue_T_315 = leq(UInt<5>(0h16), _use_this_queue_T_314)
node _use_this_queue_T_316 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_317 = tail(_use_this_queue_T_316, 1)
node _use_this_queue_T_318 = sub(_use_this_queue_T_317, len_to_write)
node _use_this_queue_T_319 = tail(_use_this_queue_T_318, 1)
node _use_this_queue_T_320 = geq(UInt<5>(0h16), _use_this_queue_T_319)
node _use_this_queue_T_321 = and(_use_this_queue_T_315, _use_this_queue_T_320)
node use_this_queue_22 = mux(wrapped, _use_this_queue_T_312, _use_this_queue_T_321)
node _cur_queue_valid_T_44 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_45 = and(_cur_queue_valid_T_44, use_this_queue_22)
node cur_queue_valid_22 = and(_cur_queue_valid_T_45, all_queues_ready)
connect Queue64_UInt8_22.io.enq.valid, cur_queue_valid_22
node _use_this_queue_T_322 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_323 = tail(_use_this_queue_T_322, 1)
node _use_this_queue_T_324 = leq(UInt<5>(0h17), _use_this_queue_T_323)
node _use_this_queue_T_325 = gt(UInt<5>(0h17), wrap_len_index_end)
node _use_this_queue_T_326 = or(_use_this_queue_T_324, _use_this_queue_T_325)
node _use_this_queue_T_327 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_328 = tail(_use_this_queue_T_327, 1)
node _use_this_queue_T_329 = leq(UInt<5>(0h17), _use_this_queue_T_328)
node _use_this_queue_T_330 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_331 = tail(_use_this_queue_T_330, 1)
node _use_this_queue_T_332 = sub(_use_this_queue_T_331, len_to_write)
node _use_this_queue_T_333 = tail(_use_this_queue_T_332, 1)
node _use_this_queue_T_334 = geq(UInt<5>(0h17), _use_this_queue_T_333)
node _use_this_queue_T_335 = and(_use_this_queue_T_329, _use_this_queue_T_334)
node use_this_queue_23 = mux(wrapped, _use_this_queue_T_326, _use_this_queue_T_335)
node _cur_queue_valid_T_46 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_47 = and(_cur_queue_valid_T_46, use_this_queue_23)
node cur_queue_valid_23 = and(_cur_queue_valid_T_47, all_queues_ready)
connect Queue64_UInt8_23.io.enq.valid, cur_queue_valid_23
node _use_this_queue_T_336 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_337 = tail(_use_this_queue_T_336, 1)
node _use_this_queue_T_338 = leq(UInt<5>(0h18), _use_this_queue_T_337)
node _use_this_queue_T_339 = gt(UInt<5>(0h18), wrap_len_index_end)
node _use_this_queue_T_340 = or(_use_this_queue_T_338, _use_this_queue_T_339)
node _use_this_queue_T_341 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_342 = tail(_use_this_queue_T_341, 1)
node _use_this_queue_T_343 = leq(UInt<5>(0h18), _use_this_queue_T_342)
node _use_this_queue_T_344 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_345 = tail(_use_this_queue_T_344, 1)
node _use_this_queue_T_346 = sub(_use_this_queue_T_345, len_to_write)
node _use_this_queue_T_347 = tail(_use_this_queue_T_346, 1)
node _use_this_queue_T_348 = geq(UInt<5>(0h18), _use_this_queue_T_347)
node _use_this_queue_T_349 = and(_use_this_queue_T_343, _use_this_queue_T_348)
node use_this_queue_24 = mux(wrapped, _use_this_queue_T_340, _use_this_queue_T_349)
node _cur_queue_valid_T_48 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_49 = and(_cur_queue_valid_T_48, use_this_queue_24)
node cur_queue_valid_24 = and(_cur_queue_valid_T_49, all_queues_ready)
connect Queue64_UInt8_24.io.enq.valid, cur_queue_valid_24
node _use_this_queue_T_350 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_351 = tail(_use_this_queue_T_350, 1)
node _use_this_queue_T_352 = leq(UInt<5>(0h19), _use_this_queue_T_351)
node _use_this_queue_T_353 = gt(UInt<5>(0h19), wrap_len_index_end)
node _use_this_queue_T_354 = or(_use_this_queue_T_352, _use_this_queue_T_353)
node _use_this_queue_T_355 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_356 = tail(_use_this_queue_T_355, 1)
node _use_this_queue_T_357 = leq(UInt<5>(0h19), _use_this_queue_T_356)
node _use_this_queue_T_358 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_359 = tail(_use_this_queue_T_358, 1)
node _use_this_queue_T_360 = sub(_use_this_queue_T_359, len_to_write)
node _use_this_queue_T_361 = tail(_use_this_queue_T_360, 1)
node _use_this_queue_T_362 = geq(UInt<5>(0h19), _use_this_queue_T_361)
node _use_this_queue_T_363 = and(_use_this_queue_T_357, _use_this_queue_T_362)
node use_this_queue_25 = mux(wrapped, _use_this_queue_T_354, _use_this_queue_T_363)
node _cur_queue_valid_T_50 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_51 = and(_cur_queue_valid_T_50, use_this_queue_25)
node cur_queue_valid_25 = and(_cur_queue_valid_T_51, all_queues_ready)
connect Queue64_UInt8_25.io.enq.valid, cur_queue_valid_25
node _use_this_queue_T_364 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_365 = tail(_use_this_queue_T_364, 1)
node _use_this_queue_T_366 = leq(UInt<5>(0h1a), _use_this_queue_T_365)
node _use_this_queue_T_367 = gt(UInt<5>(0h1a), wrap_len_index_end)
node _use_this_queue_T_368 = or(_use_this_queue_T_366, _use_this_queue_T_367)
node _use_this_queue_T_369 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_370 = tail(_use_this_queue_T_369, 1)
node _use_this_queue_T_371 = leq(UInt<5>(0h1a), _use_this_queue_T_370)
node _use_this_queue_T_372 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_373 = tail(_use_this_queue_T_372, 1)
node _use_this_queue_T_374 = sub(_use_this_queue_T_373, len_to_write)
node _use_this_queue_T_375 = tail(_use_this_queue_T_374, 1)
node _use_this_queue_T_376 = geq(UInt<5>(0h1a), _use_this_queue_T_375)
node _use_this_queue_T_377 = and(_use_this_queue_T_371, _use_this_queue_T_376)
node use_this_queue_26 = mux(wrapped, _use_this_queue_T_368, _use_this_queue_T_377)
node _cur_queue_valid_T_52 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_53 = and(_cur_queue_valid_T_52, use_this_queue_26)
node cur_queue_valid_26 = and(_cur_queue_valid_T_53, all_queues_ready)
connect Queue64_UInt8_26.io.enq.valid, cur_queue_valid_26
node _use_this_queue_T_378 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_379 = tail(_use_this_queue_T_378, 1)
node _use_this_queue_T_380 = leq(UInt<5>(0h1b), _use_this_queue_T_379)
node _use_this_queue_T_381 = gt(UInt<5>(0h1b), wrap_len_index_end)
node _use_this_queue_T_382 = or(_use_this_queue_T_380, _use_this_queue_T_381)
node _use_this_queue_T_383 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_384 = tail(_use_this_queue_T_383, 1)
node _use_this_queue_T_385 = leq(UInt<5>(0h1b), _use_this_queue_T_384)
node _use_this_queue_T_386 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_387 = tail(_use_this_queue_T_386, 1)
node _use_this_queue_T_388 = sub(_use_this_queue_T_387, len_to_write)
node _use_this_queue_T_389 = tail(_use_this_queue_T_388, 1)
node _use_this_queue_T_390 = geq(UInt<5>(0h1b), _use_this_queue_T_389)
node _use_this_queue_T_391 = and(_use_this_queue_T_385, _use_this_queue_T_390)
node use_this_queue_27 = mux(wrapped, _use_this_queue_T_382, _use_this_queue_T_391)
node _cur_queue_valid_T_54 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_55 = and(_cur_queue_valid_T_54, use_this_queue_27)
node cur_queue_valid_27 = and(_cur_queue_valid_T_55, all_queues_ready)
connect Queue64_UInt8_27.io.enq.valid, cur_queue_valid_27
node _use_this_queue_T_392 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_393 = tail(_use_this_queue_T_392, 1)
node _use_this_queue_T_394 = leq(UInt<5>(0h1c), _use_this_queue_T_393)
node _use_this_queue_T_395 = gt(UInt<5>(0h1c), wrap_len_index_end)
node _use_this_queue_T_396 = or(_use_this_queue_T_394, _use_this_queue_T_395)
node _use_this_queue_T_397 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_398 = tail(_use_this_queue_T_397, 1)
node _use_this_queue_T_399 = leq(UInt<5>(0h1c), _use_this_queue_T_398)
node _use_this_queue_T_400 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_401 = tail(_use_this_queue_T_400, 1)
node _use_this_queue_T_402 = sub(_use_this_queue_T_401, len_to_write)
node _use_this_queue_T_403 = tail(_use_this_queue_T_402, 1)
node _use_this_queue_T_404 = geq(UInt<5>(0h1c), _use_this_queue_T_403)
node _use_this_queue_T_405 = and(_use_this_queue_T_399, _use_this_queue_T_404)
node use_this_queue_28 = mux(wrapped, _use_this_queue_T_396, _use_this_queue_T_405)
node _cur_queue_valid_T_56 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_57 = and(_cur_queue_valid_T_56, use_this_queue_28)
node cur_queue_valid_28 = and(_cur_queue_valid_T_57, all_queues_ready)
connect Queue64_UInt8_28.io.enq.valid, cur_queue_valid_28
node _use_this_queue_T_406 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_407 = tail(_use_this_queue_T_406, 1)
node _use_this_queue_T_408 = leq(UInt<5>(0h1d), _use_this_queue_T_407)
node _use_this_queue_T_409 = gt(UInt<5>(0h1d), wrap_len_index_end)
node _use_this_queue_T_410 = or(_use_this_queue_T_408, _use_this_queue_T_409)
node _use_this_queue_T_411 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_412 = tail(_use_this_queue_T_411, 1)
node _use_this_queue_T_413 = leq(UInt<5>(0h1d), _use_this_queue_T_412)
node _use_this_queue_T_414 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_415 = tail(_use_this_queue_T_414, 1)
node _use_this_queue_T_416 = sub(_use_this_queue_T_415, len_to_write)
node _use_this_queue_T_417 = tail(_use_this_queue_T_416, 1)
node _use_this_queue_T_418 = geq(UInt<5>(0h1d), _use_this_queue_T_417)
node _use_this_queue_T_419 = and(_use_this_queue_T_413, _use_this_queue_T_418)
node use_this_queue_29 = mux(wrapped, _use_this_queue_T_410, _use_this_queue_T_419)
node _cur_queue_valid_T_58 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_59 = and(_cur_queue_valid_T_58, use_this_queue_29)
node cur_queue_valid_29 = and(_cur_queue_valid_T_59, all_queues_ready)
connect Queue64_UInt8_29.io.enq.valid, cur_queue_valid_29
node _use_this_queue_T_420 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_421 = tail(_use_this_queue_T_420, 1)
node _use_this_queue_T_422 = leq(UInt<5>(0h1e), _use_this_queue_T_421)
node _use_this_queue_T_423 = gt(UInt<5>(0h1e), wrap_len_index_end)
node _use_this_queue_T_424 = or(_use_this_queue_T_422, _use_this_queue_T_423)
node _use_this_queue_T_425 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_426 = tail(_use_this_queue_T_425, 1)
node _use_this_queue_T_427 = leq(UInt<5>(0h1e), _use_this_queue_T_426)
node _use_this_queue_T_428 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_429 = tail(_use_this_queue_T_428, 1)
node _use_this_queue_T_430 = sub(_use_this_queue_T_429, len_to_write)
node _use_this_queue_T_431 = tail(_use_this_queue_T_430, 1)
node _use_this_queue_T_432 = geq(UInt<5>(0h1e), _use_this_queue_T_431)
node _use_this_queue_T_433 = and(_use_this_queue_T_427, _use_this_queue_T_432)
node use_this_queue_30 = mux(wrapped, _use_this_queue_T_424, _use_this_queue_T_433)
node _cur_queue_valid_T_60 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_61 = and(_cur_queue_valid_T_60, use_this_queue_30)
node cur_queue_valid_30 = and(_cur_queue_valid_T_61, all_queues_ready)
connect Queue64_UInt8_30.io.enq.valid, cur_queue_valid_30
node _use_this_queue_T_434 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_435 = tail(_use_this_queue_T_434, 1)
node _use_this_queue_T_436 = leq(UInt<5>(0h1f), _use_this_queue_T_435)
node _use_this_queue_T_437 = gt(UInt<5>(0h1f), wrap_len_index_end)
node _use_this_queue_T_438 = or(_use_this_queue_T_436, _use_this_queue_T_437)
node _use_this_queue_T_439 = sub(MAX_QUEUE_IDX, write_start_index)
node _use_this_queue_T_440 = tail(_use_this_queue_T_439, 1)
node _use_this_queue_T_441 = leq(UInt<5>(0h1f), _use_this_queue_T_440)
node _use_this_queue_T_442 = sub(UInt<6>(0h20), write_start_index)
node _use_this_queue_T_443 = tail(_use_this_queue_T_442, 1)
node _use_this_queue_T_444 = sub(_use_this_queue_T_443, len_to_write)
node _use_this_queue_T_445 = tail(_use_this_queue_T_444, 1)
node _use_this_queue_T_446 = geq(UInt<5>(0h1f), _use_this_queue_T_445)
node _use_this_queue_T_447 = and(_use_this_queue_T_441, _use_this_queue_T_446)
node use_this_queue_31 = mux(wrapped, _use_this_queue_T_438, _use_this_queue_T_447)
node _cur_queue_valid_T_62 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _cur_queue_valid_T_63 = and(_cur_queue_valid_T_62, use_this_queue_31)
node cur_queue_valid_31 = and(_cur_queue_valid_T_63, all_queues_ready)
connect Queue64_UInt8_31.io.enq.valid, cur_queue_valid_31
regreset read_start_index : UInt<6>, clock, reset, UInt<6>(0h0)
regreset len_already_consumed : UInt<64>, clock, reset, UInt<64>(0h0)
wire remapVecData : UInt<8>[32]
wire remapVecValids : UInt<1>[32]
wire remapVecReadys : UInt<1>[32]
connect remapVecData[0], UInt<1>(0h0)
connect remapVecValids[0], UInt<1>(0h0)
connect Queue64_UInt8.io.deq.ready, UInt<1>(0h0)
connect remapVecData[1], UInt<1>(0h0)
connect remapVecValids[1], UInt<1>(0h0)
connect Queue64_UInt8_1.io.deq.ready, UInt<1>(0h0)
connect remapVecData[2], UInt<1>(0h0)
connect remapVecValids[2], UInt<1>(0h0)
connect Queue64_UInt8_2.io.deq.ready, UInt<1>(0h0)
connect remapVecData[3], UInt<1>(0h0)
connect remapVecValids[3], UInt<1>(0h0)
connect Queue64_UInt8_3.io.deq.ready, UInt<1>(0h0)
connect remapVecData[4], UInt<1>(0h0)
connect remapVecValids[4], UInt<1>(0h0)
connect Queue64_UInt8_4.io.deq.ready, UInt<1>(0h0)
connect remapVecData[5], UInt<1>(0h0)
connect remapVecValids[5], UInt<1>(0h0)
connect Queue64_UInt8_5.io.deq.ready, UInt<1>(0h0)
connect remapVecData[6], UInt<1>(0h0)
connect remapVecValids[6], UInt<1>(0h0)
connect Queue64_UInt8_6.io.deq.ready, UInt<1>(0h0)
connect remapVecData[7], UInt<1>(0h0)
connect remapVecValids[7], UInt<1>(0h0)
connect Queue64_UInt8_7.io.deq.ready, UInt<1>(0h0)
connect remapVecData[8], UInt<1>(0h0)
connect remapVecValids[8], UInt<1>(0h0)
connect Queue64_UInt8_8.io.deq.ready, UInt<1>(0h0)
connect remapVecData[9], UInt<1>(0h0)
connect remapVecValids[9], UInt<1>(0h0)
connect Queue64_UInt8_9.io.deq.ready, UInt<1>(0h0)
connect remapVecData[10], UInt<1>(0h0)
connect remapVecValids[10], UInt<1>(0h0)
connect Queue64_UInt8_10.io.deq.ready, UInt<1>(0h0)
connect remapVecData[11], UInt<1>(0h0)
connect remapVecValids[11], UInt<1>(0h0)
connect Queue64_UInt8_11.io.deq.ready, UInt<1>(0h0)
connect remapVecData[12], UInt<1>(0h0)
connect remapVecValids[12], UInt<1>(0h0)
connect Queue64_UInt8_12.io.deq.ready, UInt<1>(0h0)
connect remapVecData[13], UInt<1>(0h0)
connect remapVecValids[13], UInt<1>(0h0)
connect Queue64_UInt8_13.io.deq.ready, UInt<1>(0h0)
connect remapVecData[14], UInt<1>(0h0)
connect remapVecValids[14], UInt<1>(0h0)
connect Queue64_UInt8_14.io.deq.ready, UInt<1>(0h0)
connect remapVecData[15], UInt<1>(0h0)
connect remapVecValids[15], UInt<1>(0h0)
connect Queue64_UInt8_15.io.deq.ready, UInt<1>(0h0)
connect remapVecData[16], UInt<1>(0h0)
connect remapVecValids[16], UInt<1>(0h0)
connect Queue64_UInt8_16.io.deq.ready, UInt<1>(0h0)
connect remapVecData[17], UInt<1>(0h0)
connect remapVecValids[17], UInt<1>(0h0)
connect Queue64_UInt8_17.io.deq.ready, UInt<1>(0h0)
connect remapVecData[18], UInt<1>(0h0)
connect remapVecValids[18], UInt<1>(0h0)
connect Queue64_UInt8_18.io.deq.ready, UInt<1>(0h0)
connect remapVecData[19], UInt<1>(0h0)
connect remapVecValids[19], UInt<1>(0h0)
connect Queue64_UInt8_19.io.deq.ready, UInt<1>(0h0)
connect remapVecData[20], UInt<1>(0h0)
connect remapVecValids[20], UInt<1>(0h0)
connect Queue64_UInt8_20.io.deq.ready, UInt<1>(0h0)
connect remapVecData[21], UInt<1>(0h0)
connect remapVecValids[21], UInt<1>(0h0)
connect Queue64_UInt8_21.io.deq.ready, UInt<1>(0h0)
connect remapVecData[22], UInt<1>(0h0)
connect remapVecValids[22], UInt<1>(0h0)
connect Queue64_UInt8_22.io.deq.ready, UInt<1>(0h0)
connect remapVecData[23], UInt<1>(0h0)
connect remapVecValids[23], UInt<1>(0h0)
connect Queue64_UInt8_23.io.deq.ready, UInt<1>(0h0)
connect remapVecData[24], UInt<1>(0h0)
connect remapVecValids[24], UInt<1>(0h0)
connect Queue64_UInt8_24.io.deq.ready, UInt<1>(0h0)
connect remapVecData[25], UInt<1>(0h0)
connect remapVecValids[25], UInt<1>(0h0)
connect Queue64_UInt8_25.io.deq.ready, UInt<1>(0h0)
connect remapVecData[26], UInt<1>(0h0)
connect remapVecValids[26], UInt<1>(0h0)
connect Queue64_UInt8_26.io.deq.ready, UInt<1>(0h0)
connect remapVecData[27], UInt<1>(0h0)
connect remapVecValids[27], UInt<1>(0h0)
connect Queue64_UInt8_27.io.deq.ready, UInt<1>(0h0)
connect remapVecData[28], UInt<1>(0h0)
connect remapVecValids[28], UInt<1>(0h0)
connect Queue64_UInt8_28.io.deq.ready, UInt<1>(0h0)
connect remapVecData[29], UInt<1>(0h0)
connect remapVecValids[29], UInt<1>(0h0)
connect Queue64_UInt8_29.io.deq.ready, UInt<1>(0h0)
connect remapVecData[30], UInt<1>(0h0)
connect remapVecValids[30], UInt<1>(0h0)
connect Queue64_UInt8_30.io.deq.ready, UInt<1>(0h0)
connect remapVecData[31], UInt<1>(0h0)
connect remapVecValids[31], UInt<1>(0h0)
connect Queue64_UInt8_31.io.deq.ready, UInt<1>(0h0)
node _remapindex_T = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_1 = sub(_remapindex_T, UInt<1>(0h0))
node _remapindex_T_2 = asUInt(_remapindex_T_1)
node _remapindex_T_3 = sub(_remapindex_T_2, read_start_index)
node _remapindex_T_4 = asUInt(_remapindex_T_3)
node remapindex = rem(_remapindex_T_4, UInt<6>(0h20))
node _T_2114 = eq(UInt<1>(0h0), remapindex)
when _T_2114 :
connect remapVecData[0], Queue64_UInt8.io.deq.bits
connect remapVecValids[0], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[0]
node _T_2115 = eq(UInt<1>(0h1), remapindex)
when _T_2115 :
connect remapVecData[0], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[0]
node _T_2116 = eq(UInt<2>(0h2), remapindex)
when _T_2116 :
connect remapVecData[0], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[0]
node _T_2117 = eq(UInt<2>(0h3), remapindex)
when _T_2117 :
connect remapVecData[0], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[0]
node _T_2118 = eq(UInt<3>(0h4), remapindex)
when _T_2118 :
connect remapVecData[0], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[0]
node _T_2119 = eq(UInt<3>(0h5), remapindex)
when _T_2119 :
connect remapVecData[0], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[0]
node _T_2120 = eq(UInt<3>(0h6), remapindex)
when _T_2120 :
connect remapVecData[0], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[0]
node _T_2121 = eq(UInt<3>(0h7), remapindex)
when _T_2121 :
connect remapVecData[0], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[0]
node _T_2122 = eq(UInt<4>(0h8), remapindex)
when _T_2122 :
connect remapVecData[0], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[0]
node _T_2123 = eq(UInt<4>(0h9), remapindex)
when _T_2123 :
connect remapVecData[0], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[0]
node _T_2124 = eq(UInt<4>(0ha), remapindex)
when _T_2124 :
connect remapVecData[0], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[0]
node _T_2125 = eq(UInt<4>(0hb), remapindex)
when _T_2125 :
connect remapVecData[0], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[0]
node _T_2126 = eq(UInt<4>(0hc), remapindex)
when _T_2126 :
connect remapVecData[0], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[0]
node _T_2127 = eq(UInt<4>(0hd), remapindex)
when _T_2127 :
connect remapVecData[0], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[0]
node _T_2128 = eq(UInt<4>(0he), remapindex)
when _T_2128 :
connect remapVecData[0], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[0]
node _T_2129 = eq(UInt<4>(0hf), remapindex)
when _T_2129 :
connect remapVecData[0], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[0]
node _T_2130 = eq(UInt<5>(0h10), remapindex)
when _T_2130 :
connect remapVecData[0], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[0]
node _T_2131 = eq(UInt<5>(0h11), remapindex)
when _T_2131 :
connect remapVecData[0], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[0]
node _T_2132 = eq(UInt<5>(0h12), remapindex)
when _T_2132 :
connect remapVecData[0], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[0]
node _T_2133 = eq(UInt<5>(0h13), remapindex)
when _T_2133 :
connect remapVecData[0], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[0]
node _T_2134 = eq(UInt<5>(0h14), remapindex)
when _T_2134 :
connect remapVecData[0], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[0]
node _T_2135 = eq(UInt<5>(0h15), remapindex)
when _T_2135 :
connect remapVecData[0], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[0]
node _T_2136 = eq(UInt<5>(0h16), remapindex)
when _T_2136 :
connect remapVecData[0], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[0]
node _T_2137 = eq(UInt<5>(0h17), remapindex)
when _T_2137 :
connect remapVecData[0], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[0]
node _T_2138 = eq(UInt<5>(0h18), remapindex)
when _T_2138 :
connect remapVecData[0], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[0]
node _T_2139 = eq(UInt<5>(0h19), remapindex)
when _T_2139 :
connect remapVecData[0], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[0]
node _T_2140 = eq(UInt<5>(0h1a), remapindex)
when _T_2140 :
connect remapVecData[0], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[0]
node _T_2141 = eq(UInt<5>(0h1b), remapindex)
when _T_2141 :
connect remapVecData[0], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[0]
node _T_2142 = eq(UInt<5>(0h1c), remapindex)
when _T_2142 :
connect remapVecData[0], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[0]
node _T_2143 = eq(UInt<5>(0h1d), remapindex)
when _T_2143 :
connect remapVecData[0], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[0]
node _T_2144 = eq(UInt<5>(0h1e), remapindex)
when _T_2144 :
connect remapVecData[0], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[0]
node _T_2145 = eq(UInt<5>(0h1f), remapindex)
when _T_2145 :
connect remapVecData[0], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[0]
node _remapindex_T_5 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_6 = sub(_remapindex_T_5, UInt<1>(0h1))
node _remapindex_T_7 = asUInt(_remapindex_T_6)
node _remapindex_T_8 = sub(_remapindex_T_7, read_start_index)
node _remapindex_T_9 = asUInt(_remapindex_T_8)
node remapindex_1 = rem(_remapindex_T_9, UInt<6>(0h20))
node _T_2146 = eq(UInt<1>(0h0), remapindex_1)
when _T_2146 :
connect remapVecData[1], Queue64_UInt8.io.deq.bits
connect remapVecValids[1], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[1]
node _T_2147 = eq(UInt<1>(0h1), remapindex_1)
when _T_2147 :
connect remapVecData[1], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[1]
node _T_2148 = eq(UInt<2>(0h2), remapindex_1)
when _T_2148 :
connect remapVecData[1], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[1]
node _T_2149 = eq(UInt<2>(0h3), remapindex_1)
when _T_2149 :
connect remapVecData[1], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[1]
node _T_2150 = eq(UInt<3>(0h4), remapindex_1)
when _T_2150 :
connect remapVecData[1], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[1]
node _T_2151 = eq(UInt<3>(0h5), remapindex_1)
when _T_2151 :
connect remapVecData[1], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[1]
node _T_2152 = eq(UInt<3>(0h6), remapindex_1)
when _T_2152 :
connect remapVecData[1], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[1]
node _T_2153 = eq(UInt<3>(0h7), remapindex_1)
when _T_2153 :
connect remapVecData[1], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[1]
node _T_2154 = eq(UInt<4>(0h8), remapindex_1)
when _T_2154 :
connect remapVecData[1], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[1]
node _T_2155 = eq(UInt<4>(0h9), remapindex_1)
when _T_2155 :
connect remapVecData[1], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[1]
node _T_2156 = eq(UInt<4>(0ha), remapindex_1)
when _T_2156 :
connect remapVecData[1], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[1]
node _T_2157 = eq(UInt<4>(0hb), remapindex_1)
when _T_2157 :
connect remapVecData[1], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[1]
node _T_2158 = eq(UInt<4>(0hc), remapindex_1)
when _T_2158 :
connect remapVecData[1], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[1]
node _T_2159 = eq(UInt<4>(0hd), remapindex_1)
when _T_2159 :
connect remapVecData[1], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[1]
node _T_2160 = eq(UInt<4>(0he), remapindex_1)
when _T_2160 :
connect remapVecData[1], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[1]
node _T_2161 = eq(UInt<4>(0hf), remapindex_1)
when _T_2161 :
connect remapVecData[1], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[1]
node _T_2162 = eq(UInt<5>(0h10), remapindex_1)
when _T_2162 :
connect remapVecData[1], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[1]
node _T_2163 = eq(UInt<5>(0h11), remapindex_1)
when _T_2163 :
connect remapVecData[1], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[1]
node _T_2164 = eq(UInt<5>(0h12), remapindex_1)
when _T_2164 :
connect remapVecData[1], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[1]
node _T_2165 = eq(UInt<5>(0h13), remapindex_1)
when _T_2165 :
connect remapVecData[1], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[1]
node _T_2166 = eq(UInt<5>(0h14), remapindex_1)
when _T_2166 :
connect remapVecData[1], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[1]
node _T_2167 = eq(UInt<5>(0h15), remapindex_1)
when _T_2167 :
connect remapVecData[1], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[1]
node _T_2168 = eq(UInt<5>(0h16), remapindex_1)
when _T_2168 :
connect remapVecData[1], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[1]
node _T_2169 = eq(UInt<5>(0h17), remapindex_1)
when _T_2169 :
connect remapVecData[1], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[1]
node _T_2170 = eq(UInt<5>(0h18), remapindex_1)
when _T_2170 :
connect remapVecData[1], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[1]
node _T_2171 = eq(UInt<5>(0h19), remapindex_1)
when _T_2171 :
connect remapVecData[1], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[1]
node _T_2172 = eq(UInt<5>(0h1a), remapindex_1)
when _T_2172 :
connect remapVecData[1], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[1]
node _T_2173 = eq(UInt<5>(0h1b), remapindex_1)
when _T_2173 :
connect remapVecData[1], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[1]
node _T_2174 = eq(UInt<5>(0h1c), remapindex_1)
when _T_2174 :
connect remapVecData[1], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[1]
node _T_2175 = eq(UInt<5>(0h1d), remapindex_1)
when _T_2175 :
connect remapVecData[1], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[1]
node _T_2176 = eq(UInt<5>(0h1e), remapindex_1)
when _T_2176 :
connect remapVecData[1], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[1]
node _T_2177 = eq(UInt<5>(0h1f), remapindex_1)
when _T_2177 :
connect remapVecData[1], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[1]
node _remapindex_T_10 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_11 = sub(_remapindex_T_10, UInt<2>(0h2))
node _remapindex_T_12 = asUInt(_remapindex_T_11)
node _remapindex_T_13 = sub(_remapindex_T_12, read_start_index)
node _remapindex_T_14 = asUInt(_remapindex_T_13)
node remapindex_2 = rem(_remapindex_T_14, UInt<6>(0h20))
node _T_2178 = eq(UInt<1>(0h0), remapindex_2)
when _T_2178 :
connect remapVecData[2], Queue64_UInt8.io.deq.bits
connect remapVecValids[2], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[2]
node _T_2179 = eq(UInt<1>(0h1), remapindex_2)
when _T_2179 :
connect remapVecData[2], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[2]
node _T_2180 = eq(UInt<2>(0h2), remapindex_2)
when _T_2180 :
connect remapVecData[2], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[2]
node _T_2181 = eq(UInt<2>(0h3), remapindex_2)
when _T_2181 :
connect remapVecData[2], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[2]
node _T_2182 = eq(UInt<3>(0h4), remapindex_2)
when _T_2182 :
connect remapVecData[2], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[2]
node _T_2183 = eq(UInt<3>(0h5), remapindex_2)
when _T_2183 :
connect remapVecData[2], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[2]
node _T_2184 = eq(UInt<3>(0h6), remapindex_2)
when _T_2184 :
connect remapVecData[2], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[2]
node _T_2185 = eq(UInt<3>(0h7), remapindex_2)
when _T_2185 :
connect remapVecData[2], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[2]
node _T_2186 = eq(UInt<4>(0h8), remapindex_2)
when _T_2186 :
connect remapVecData[2], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[2]
node _T_2187 = eq(UInt<4>(0h9), remapindex_2)
when _T_2187 :
connect remapVecData[2], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[2]
node _T_2188 = eq(UInt<4>(0ha), remapindex_2)
when _T_2188 :
connect remapVecData[2], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[2]
node _T_2189 = eq(UInt<4>(0hb), remapindex_2)
when _T_2189 :
connect remapVecData[2], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[2]
node _T_2190 = eq(UInt<4>(0hc), remapindex_2)
when _T_2190 :
connect remapVecData[2], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[2]
node _T_2191 = eq(UInt<4>(0hd), remapindex_2)
when _T_2191 :
connect remapVecData[2], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[2]
node _T_2192 = eq(UInt<4>(0he), remapindex_2)
when _T_2192 :
connect remapVecData[2], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[2]
node _T_2193 = eq(UInt<4>(0hf), remapindex_2)
when _T_2193 :
connect remapVecData[2], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[2]
node _T_2194 = eq(UInt<5>(0h10), remapindex_2)
when _T_2194 :
connect remapVecData[2], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[2]
node _T_2195 = eq(UInt<5>(0h11), remapindex_2)
when _T_2195 :
connect remapVecData[2], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[2]
node _T_2196 = eq(UInt<5>(0h12), remapindex_2)
when _T_2196 :
connect remapVecData[2], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[2]
node _T_2197 = eq(UInt<5>(0h13), remapindex_2)
when _T_2197 :
connect remapVecData[2], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[2]
node _T_2198 = eq(UInt<5>(0h14), remapindex_2)
when _T_2198 :
connect remapVecData[2], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[2]
node _T_2199 = eq(UInt<5>(0h15), remapindex_2)
when _T_2199 :
connect remapVecData[2], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[2]
node _T_2200 = eq(UInt<5>(0h16), remapindex_2)
when _T_2200 :
connect remapVecData[2], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[2]
node _T_2201 = eq(UInt<5>(0h17), remapindex_2)
when _T_2201 :
connect remapVecData[2], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[2]
node _T_2202 = eq(UInt<5>(0h18), remapindex_2)
when _T_2202 :
connect remapVecData[2], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[2]
node _T_2203 = eq(UInt<5>(0h19), remapindex_2)
when _T_2203 :
connect remapVecData[2], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[2]
node _T_2204 = eq(UInt<5>(0h1a), remapindex_2)
when _T_2204 :
connect remapVecData[2], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[2]
node _T_2205 = eq(UInt<5>(0h1b), remapindex_2)
when _T_2205 :
connect remapVecData[2], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[2]
node _T_2206 = eq(UInt<5>(0h1c), remapindex_2)
when _T_2206 :
connect remapVecData[2], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[2]
node _T_2207 = eq(UInt<5>(0h1d), remapindex_2)
when _T_2207 :
connect remapVecData[2], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[2]
node _T_2208 = eq(UInt<5>(0h1e), remapindex_2)
when _T_2208 :
connect remapVecData[2], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[2]
node _T_2209 = eq(UInt<5>(0h1f), remapindex_2)
when _T_2209 :
connect remapVecData[2], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[2]
node _remapindex_T_15 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_16 = sub(_remapindex_T_15, UInt<2>(0h3))
node _remapindex_T_17 = asUInt(_remapindex_T_16)
node _remapindex_T_18 = sub(_remapindex_T_17, read_start_index)
node _remapindex_T_19 = asUInt(_remapindex_T_18)
node remapindex_3 = rem(_remapindex_T_19, UInt<6>(0h20))
node _T_2210 = eq(UInt<1>(0h0), remapindex_3)
when _T_2210 :
connect remapVecData[3], Queue64_UInt8.io.deq.bits
connect remapVecValids[3], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[3]
node _T_2211 = eq(UInt<1>(0h1), remapindex_3)
when _T_2211 :
connect remapVecData[3], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[3]
node _T_2212 = eq(UInt<2>(0h2), remapindex_3)
when _T_2212 :
connect remapVecData[3], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[3]
node _T_2213 = eq(UInt<2>(0h3), remapindex_3)
when _T_2213 :
connect remapVecData[3], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[3]
node _T_2214 = eq(UInt<3>(0h4), remapindex_3)
when _T_2214 :
connect remapVecData[3], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[3]
node _T_2215 = eq(UInt<3>(0h5), remapindex_3)
when _T_2215 :
connect remapVecData[3], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[3]
node _T_2216 = eq(UInt<3>(0h6), remapindex_3)
when _T_2216 :
connect remapVecData[3], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[3]
node _T_2217 = eq(UInt<3>(0h7), remapindex_3)
when _T_2217 :
connect remapVecData[3], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[3]
node _T_2218 = eq(UInt<4>(0h8), remapindex_3)
when _T_2218 :
connect remapVecData[3], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[3]
node _T_2219 = eq(UInt<4>(0h9), remapindex_3)
when _T_2219 :
connect remapVecData[3], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[3]
node _T_2220 = eq(UInt<4>(0ha), remapindex_3)
when _T_2220 :
connect remapVecData[3], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[3]
node _T_2221 = eq(UInt<4>(0hb), remapindex_3)
when _T_2221 :
connect remapVecData[3], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[3]
node _T_2222 = eq(UInt<4>(0hc), remapindex_3)
when _T_2222 :
connect remapVecData[3], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[3]
node _T_2223 = eq(UInt<4>(0hd), remapindex_3)
when _T_2223 :
connect remapVecData[3], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[3]
node _T_2224 = eq(UInt<4>(0he), remapindex_3)
when _T_2224 :
connect remapVecData[3], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[3]
node _T_2225 = eq(UInt<4>(0hf), remapindex_3)
when _T_2225 :
connect remapVecData[3], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[3]
node _T_2226 = eq(UInt<5>(0h10), remapindex_3)
when _T_2226 :
connect remapVecData[3], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[3]
node _T_2227 = eq(UInt<5>(0h11), remapindex_3)
when _T_2227 :
connect remapVecData[3], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[3]
node _T_2228 = eq(UInt<5>(0h12), remapindex_3)
when _T_2228 :
connect remapVecData[3], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[3]
node _T_2229 = eq(UInt<5>(0h13), remapindex_3)
when _T_2229 :
connect remapVecData[3], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[3]
node _T_2230 = eq(UInt<5>(0h14), remapindex_3)
when _T_2230 :
connect remapVecData[3], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[3]
node _T_2231 = eq(UInt<5>(0h15), remapindex_3)
when _T_2231 :
connect remapVecData[3], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[3]
node _T_2232 = eq(UInt<5>(0h16), remapindex_3)
when _T_2232 :
connect remapVecData[3], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[3]
node _T_2233 = eq(UInt<5>(0h17), remapindex_3)
when _T_2233 :
connect remapVecData[3], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[3]
node _T_2234 = eq(UInt<5>(0h18), remapindex_3)
when _T_2234 :
connect remapVecData[3], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[3]
node _T_2235 = eq(UInt<5>(0h19), remapindex_3)
when _T_2235 :
connect remapVecData[3], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[3]
node _T_2236 = eq(UInt<5>(0h1a), remapindex_3)
when _T_2236 :
connect remapVecData[3], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[3]
node _T_2237 = eq(UInt<5>(0h1b), remapindex_3)
when _T_2237 :
connect remapVecData[3], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[3]
node _T_2238 = eq(UInt<5>(0h1c), remapindex_3)
when _T_2238 :
connect remapVecData[3], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[3]
node _T_2239 = eq(UInt<5>(0h1d), remapindex_3)
when _T_2239 :
connect remapVecData[3], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[3]
node _T_2240 = eq(UInt<5>(0h1e), remapindex_3)
when _T_2240 :
connect remapVecData[3], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[3]
node _T_2241 = eq(UInt<5>(0h1f), remapindex_3)
when _T_2241 :
connect remapVecData[3], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[3]
node _remapindex_T_20 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_21 = sub(_remapindex_T_20, UInt<3>(0h4))
node _remapindex_T_22 = asUInt(_remapindex_T_21)
node _remapindex_T_23 = sub(_remapindex_T_22, read_start_index)
node _remapindex_T_24 = asUInt(_remapindex_T_23)
node remapindex_4 = rem(_remapindex_T_24, UInt<6>(0h20))
node _T_2242 = eq(UInt<1>(0h0), remapindex_4)
when _T_2242 :
connect remapVecData[4], Queue64_UInt8.io.deq.bits
connect remapVecValids[4], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[4]
node _T_2243 = eq(UInt<1>(0h1), remapindex_4)
when _T_2243 :
connect remapVecData[4], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[4]
node _T_2244 = eq(UInt<2>(0h2), remapindex_4)
when _T_2244 :
connect remapVecData[4], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[4]
node _T_2245 = eq(UInt<2>(0h3), remapindex_4)
when _T_2245 :
connect remapVecData[4], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[4]
node _T_2246 = eq(UInt<3>(0h4), remapindex_4)
when _T_2246 :
connect remapVecData[4], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[4]
node _T_2247 = eq(UInt<3>(0h5), remapindex_4)
when _T_2247 :
connect remapVecData[4], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[4]
node _T_2248 = eq(UInt<3>(0h6), remapindex_4)
when _T_2248 :
connect remapVecData[4], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[4]
node _T_2249 = eq(UInt<3>(0h7), remapindex_4)
when _T_2249 :
connect remapVecData[4], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[4]
node _T_2250 = eq(UInt<4>(0h8), remapindex_4)
when _T_2250 :
connect remapVecData[4], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[4]
node _T_2251 = eq(UInt<4>(0h9), remapindex_4)
when _T_2251 :
connect remapVecData[4], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[4]
node _T_2252 = eq(UInt<4>(0ha), remapindex_4)
when _T_2252 :
connect remapVecData[4], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[4]
node _T_2253 = eq(UInt<4>(0hb), remapindex_4)
when _T_2253 :
connect remapVecData[4], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[4]
node _T_2254 = eq(UInt<4>(0hc), remapindex_4)
when _T_2254 :
connect remapVecData[4], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[4]
node _T_2255 = eq(UInt<4>(0hd), remapindex_4)
when _T_2255 :
connect remapVecData[4], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[4]
node _T_2256 = eq(UInt<4>(0he), remapindex_4)
when _T_2256 :
connect remapVecData[4], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[4]
node _T_2257 = eq(UInt<4>(0hf), remapindex_4)
when _T_2257 :
connect remapVecData[4], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[4]
node _T_2258 = eq(UInt<5>(0h10), remapindex_4)
when _T_2258 :
connect remapVecData[4], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[4]
node _T_2259 = eq(UInt<5>(0h11), remapindex_4)
when _T_2259 :
connect remapVecData[4], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[4]
node _T_2260 = eq(UInt<5>(0h12), remapindex_4)
when _T_2260 :
connect remapVecData[4], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[4]
node _T_2261 = eq(UInt<5>(0h13), remapindex_4)
when _T_2261 :
connect remapVecData[4], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[4]
node _T_2262 = eq(UInt<5>(0h14), remapindex_4)
when _T_2262 :
connect remapVecData[4], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[4]
node _T_2263 = eq(UInt<5>(0h15), remapindex_4)
when _T_2263 :
connect remapVecData[4], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[4]
node _T_2264 = eq(UInt<5>(0h16), remapindex_4)
when _T_2264 :
connect remapVecData[4], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[4]
node _T_2265 = eq(UInt<5>(0h17), remapindex_4)
when _T_2265 :
connect remapVecData[4], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[4]
node _T_2266 = eq(UInt<5>(0h18), remapindex_4)
when _T_2266 :
connect remapVecData[4], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[4]
node _T_2267 = eq(UInt<5>(0h19), remapindex_4)
when _T_2267 :
connect remapVecData[4], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[4]
node _T_2268 = eq(UInt<5>(0h1a), remapindex_4)
when _T_2268 :
connect remapVecData[4], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[4]
node _T_2269 = eq(UInt<5>(0h1b), remapindex_4)
when _T_2269 :
connect remapVecData[4], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[4]
node _T_2270 = eq(UInt<5>(0h1c), remapindex_4)
when _T_2270 :
connect remapVecData[4], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[4]
node _T_2271 = eq(UInt<5>(0h1d), remapindex_4)
when _T_2271 :
connect remapVecData[4], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[4]
node _T_2272 = eq(UInt<5>(0h1e), remapindex_4)
when _T_2272 :
connect remapVecData[4], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[4]
node _T_2273 = eq(UInt<5>(0h1f), remapindex_4)
when _T_2273 :
connect remapVecData[4], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[4]
node _remapindex_T_25 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_26 = sub(_remapindex_T_25, UInt<3>(0h5))
node _remapindex_T_27 = asUInt(_remapindex_T_26)
node _remapindex_T_28 = sub(_remapindex_T_27, read_start_index)
node _remapindex_T_29 = asUInt(_remapindex_T_28)
node remapindex_5 = rem(_remapindex_T_29, UInt<6>(0h20))
node _T_2274 = eq(UInt<1>(0h0), remapindex_5)
when _T_2274 :
connect remapVecData[5], Queue64_UInt8.io.deq.bits
connect remapVecValids[5], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[5]
node _T_2275 = eq(UInt<1>(0h1), remapindex_5)
when _T_2275 :
connect remapVecData[5], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[5]
node _T_2276 = eq(UInt<2>(0h2), remapindex_5)
when _T_2276 :
connect remapVecData[5], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[5]
node _T_2277 = eq(UInt<2>(0h3), remapindex_5)
when _T_2277 :
connect remapVecData[5], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[5]
node _T_2278 = eq(UInt<3>(0h4), remapindex_5)
when _T_2278 :
connect remapVecData[5], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[5]
node _T_2279 = eq(UInt<3>(0h5), remapindex_5)
when _T_2279 :
connect remapVecData[5], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[5]
node _T_2280 = eq(UInt<3>(0h6), remapindex_5)
when _T_2280 :
connect remapVecData[5], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[5]
node _T_2281 = eq(UInt<3>(0h7), remapindex_5)
when _T_2281 :
connect remapVecData[5], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[5]
node _T_2282 = eq(UInt<4>(0h8), remapindex_5)
when _T_2282 :
connect remapVecData[5], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[5]
node _T_2283 = eq(UInt<4>(0h9), remapindex_5)
when _T_2283 :
connect remapVecData[5], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[5]
node _T_2284 = eq(UInt<4>(0ha), remapindex_5)
when _T_2284 :
connect remapVecData[5], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[5]
node _T_2285 = eq(UInt<4>(0hb), remapindex_5)
when _T_2285 :
connect remapVecData[5], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[5]
node _T_2286 = eq(UInt<4>(0hc), remapindex_5)
when _T_2286 :
connect remapVecData[5], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[5]
node _T_2287 = eq(UInt<4>(0hd), remapindex_5)
when _T_2287 :
connect remapVecData[5], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[5]
node _T_2288 = eq(UInt<4>(0he), remapindex_5)
when _T_2288 :
connect remapVecData[5], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[5]
node _T_2289 = eq(UInt<4>(0hf), remapindex_5)
when _T_2289 :
connect remapVecData[5], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[5]
node _T_2290 = eq(UInt<5>(0h10), remapindex_5)
when _T_2290 :
connect remapVecData[5], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[5]
node _T_2291 = eq(UInt<5>(0h11), remapindex_5)
when _T_2291 :
connect remapVecData[5], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[5]
node _T_2292 = eq(UInt<5>(0h12), remapindex_5)
when _T_2292 :
connect remapVecData[5], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[5]
node _T_2293 = eq(UInt<5>(0h13), remapindex_5)
when _T_2293 :
connect remapVecData[5], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[5]
node _T_2294 = eq(UInt<5>(0h14), remapindex_5)
when _T_2294 :
connect remapVecData[5], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[5]
node _T_2295 = eq(UInt<5>(0h15), remapindex_5)
when _T_2295 :
connect remapVecData[5], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[5]
node _T_2296 = eq(UInt<5>(0h16), remapindex_5)
when _T_2296 :
connect remapVecData[5], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[5]
node _T_2297 = eq(UInt<5>(0h17), remapindex_5)
when _T_2297 :
connect remapVecData[5], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[5]
node _T_2298 = eq(UInt<5>(0h18), remapindex_5)
when _T_2298 :
connect remapVecData[5], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[5]
node _T_2299 = eq(UInt<5>(0h19), remapindex_5)
when _T_2299 :
connect remapVecData[5], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[5]
node _T_2300 = eq(UInt<5>(0h1a), remapindex_5)
when _T_2300 :
connect remapVecData[5], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[5]
node _T_2301 = eq(UInt<5>(0h1b), remapindex_5)
when _T_2301 :
connect remapVecData[5], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[5]
node _T_2302 = eq(UInt<5>(0h1c), remapindex_5)
when _T_2302 :
connect remapVecData[5], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[5]
node _T_2303 = eq(UInt<5>(0h1d), remapindex_5)
when _T_2303 :
connect remapVecData[5], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[5]
node _T_2304 = eq(UInt<5>(0h1e), remapindex_5)
when _T_2304 :
connect remapVecData[5], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[5]
node _T_2305 = eq(UInt<5>(0h1f), remapindex_5)
when _T_2305 :
connect remapVecData[5], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[5]
node _remapindex_T_30 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_31 = sub(_remapindex_T_30, UInt<3>(0h6))
node _remapindex_T_32 = asUInt(_remapindex_T_31)
node _remapindex_T_33 = sub(_remapindex_T_32, read_start_index)
node _remapindex_T_34 = asUInt(_remapindex_T_33)
node remapindex_6 = rem(_remapindex_T_34, UInt<6>(0h20))
node _T_2306 = eq(UInt<1>(0h0), remapindex_6)
when _T_2306 :
connect remapVecData[6], Queue64_UInt8.io.deq.bits
connect remapVecValids[6], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[6]
node _T_2307 = eq(UInt<1>(0h1), remapindex_6)
when _T_2307 :
connect remapVecData[6], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[6]
node _T_2308 = eq(UInt<2>(0h2), remapindex_6)
when _T_2308 :
connect remapVecData[6], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[6]
node _T_2309 = eq(UInt<2>(0h3), remapindex_6)
when _T_2309 :
connect remapVecData[6], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[6]
node _T_2310 = eq(UInt<3>(0h4), remapindex_6)
when _T_2310 :
connect remapVecData[6], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[6]
node _T_2311 = eq(UInt<3>(0h5), remapindex_6)
when _T_2311 :
connect remapVecData[6], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[6]
node _T_2312 = eq(UInt<3>(0h6), remapindex_6)
when _T_2312 :
connect remapVecData[6], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[6]
node _T_2313 = eq(UInt<3>(0h7), remapindex_6)
when _T_2313 :
connect remapVecData[6], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[6]
node _T_2314 = eq(UInt<4>(0h8), remapindex_6)
when _T_2314 :
connect remapVecData[6], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[6]
node _T_2315 = eq(UInt<4>(0h9), remapindex_6)
when _T_2315 :
connect remapVecData[6], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[6]
node _T_2316 = eq(UInt<4>(0ha), remapindex_6)
when _T_2316 :
connect remapVecData[6], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[6]
node _T_2317 = eq(UInt<4>(0hb), remapindex_6)
when _T_2317 :
connect remapVecData[6], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[6]
node _T_2318 = eq(UInt<4>(0hc), remapindex_6)
when _T_2318 :
connect remapVecData[6], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[6]
node _T_2319 = eq(UInt<4>(0hd), remapindex_6)
when _T_2319 :
connect remapVecData[6], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[6]
node _T_2320 = eq(UInt<4>(0he), remapindex_6)
when _T_2320 :
connect remapVecData[6], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[6]
node _T_2321 = eq(UInt<4>(0hf), remapindex_6)
when _T_2321 :
connect remapVecData[6], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[6]
node _T_2322 = eq(UInt<5>(0h10), remapindex_6)
when _T_2322 :
connect remapVecData[6], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[6]
node _T_2323 = eq(UInt<5>(0h11), remapindex_6)
when _T_2323 :
connect remapVecData[6], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[6]
node _T_2324 = eq(UInt<5>(0h12), remapindex_6)
when _T_2324 :
connect remapVecData[6], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[6]
node _T_2325 = eq(UInt<5>(0h13), remapindex_6)
when _T_2325 :
connect remapVecData[6], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[6]
node _T_2326 = eq(UInt<5>(0h14), remapindex_6)
when _T_2326 :
connect remapVecData[6], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[6]
node _T_2327 = eq(UInt<5>(0h15), remapindex_6)
when _T_2327 :
connect remapVecData[6], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[6]
node _T_2328 = eq(UInt<5>(0h16), remapindex_6)
when _T_2328 :
connect remapVecData[6], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[6]
node _T_2329 = eq(UInt<5>(0h17), remapindex_6)
when _T_2329 :
connect remapVecData[6], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[6]
node _T_2330 = eq(UInt<5>(0h18), remapindex_6)
when _T_2330 :
connect remapVecData[6], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[6]
node _T_2331 = eq(UInt<5>(0h19), remapindex_6)
when _T_2331 :
connect remapVecData[6], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[6]
node _T_2332 = eq(UInt<5>(0h1a), remapindex_6)
when _T_2332 :
connect remapVecData[6], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[6]
node _T_2333 = eq(UInt<5>(0h1b), remapindex_6)
when _T_2333 :
connect remapVecData[6], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[6]
node _T_2334 = eq(UInt<5>(0h1c), remapindex_6)
when _T_2334 :
connect remapVecData[6], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[6]
node _T_2335 = eq(UInt<5>(0h1d), remapindex_6)
when _T_2335 :
connect remapVecData[6], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[6]
node _T_2336 = eq(UInt<5>(0h1e), remapindex_6)
when _T_2336 :
connect remapVecData[6], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[6]
node _T_2337 = eq(UInt<5>(0h1f), remapindex_6)
when _T_2337 :
connect remapVecData[6], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[6]
node _remapindex_T_35 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_36 = sub(_remapindex_T_35, UInt<3>(0h7))
node _remapindex_T_37 = asUInt(_remapindex_T_36)
node _remapindex_T_38 = sub(_remapindex_T_37, read_start_index)
node _remapindex_T_39 = asUInt(_remapindex_T_38)
node remapindex_7 = rem(_remapindex_T_39, UInt<6>(0h20))
node _T_2338 = eq(UInt<1>(0h0), remapindex_7)
when _T_2338 :
connect remapVecData[7], Queue64_UInt8.io.deq.bits
connect remapVecValids[7], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[7]
node _T_2339 = eq(UInt<1>(0h1), remapindex_7)
when _T_2339 :
connect remapVecData[7], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[7]
node _T_2340 = eq(UInt<2>(0h2), remapindex_7)
when _T_2340 :
connect remapVecData[7], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[7]
node _T_2341 = eq(UInt<2>(0h3), remapindex_7)
when _T_2341 :
connect remapVecData[7], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[7]
node _T_2342 = eq(UInt<3>(0h4), remapindex_7)
when _T_2342 :
connect remapVecData[7], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[7]
node _T_2343 = eq(UInt<3>(0h5), remapindex_7)
when _T_2343 :
connect remapVecData[7], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[7]
node _T_2344 = eq(UInt<3>(0h6), remapindex_7)
when _T_2344 :
connect remapVecData[7], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[7]
node _T_2345 = eq(UInt<3>(0h7), remapindex_7)
when _T_2345 :
connect remapVecData[7], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[7]
node _T_2346 = eq(UInt<4>(0h8), remapindex_7)
when _T_2346 :
connect remapVecData[7], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[7]
node _T_2347 = eq(UInt<4>(0h9), remapindex_7)
when _T_2347 :
connect remapVecData[7], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[7]
node _T_2348 = eq(UInt<4>(0ha), remapindex_7)
when _T_2348 :
connect remapVecData[7], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[7]
node _T_2349 = eq(UInt<4>(0hb), remapindex_7)
when _T_2349 :
connect remapVecData[7], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[7]
node _T_2350 = eq(UInt<4>(0hc), remapindex_7)
when _T_2350 :
connect remapVecData[7], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[7]
node _T_2351 = eq(UInt<4>(0hd), remapindex_7)
when _T_2351 :
connect remapVecData[7], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[7]
node _T_2352 = eq(UInt<4>(0he), remapindex_7)
when _T_2352 :
connect remapVecData[7], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[7]
node _T_2353 = eq(UInt<4>(0hf), remapindex_7)
when _T_2353 :
connect remapVecData[7], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[7]
node _T_2354 = eq(UInt<5>(0h10), remapindex_7)
when _T_2354 :
connect remapVecData[7], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[7]
node _T_2355 = eq(UInt<5>(0h11), remapindex_7)
when _T_2355 :
connect remapVecData[7], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[7]
node _T_2356 = eq(UInt<5>(0h12), remapindex_7)
when _T_2356 :
connect remapVecData[7], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[7]
node _T_2357 = eq(UInt<5>(0h13), remapindex_7)
when _T_2357 :
connect remapVecData[7], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[7]
node _T_2358 = eq(UInt<5>(0h14), remapindex_7)
when _T_2358 :
connect remapVecData[7], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[7]
node _T_2359 = eq(UInt<5>(0h15), remapindex_7)
when _T_2359 :
connect remapVecData[7], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[7]
node _T_2360 = eq(UInt<5>(0h16), remapindex_7)
when _T_2360 :
connect remapVecData[7], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[7]
node _T_2361 = eq(UInt<5>(0h17), remapindex_7)
when _T_2361 :
connect remapVecData[7], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[7]
node _T_2362 = eq(UInt<5>(0h18), remapindex_7)
when _T_2362 :
connect remapVecData[7], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[7]
node _T_2363 = eq(UInt<5>(0h19), remapindex_7)
when _T_2363 :
connect remapVecData[7], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[7]
node _T_2364 = eq(UInt<5>(0h1a), remapindex_7)
when _T_2364 :
connect remapVecData[7], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[7]
node _T_2365 = eq(UInt<5>(0h1b), remapindex_7)
when _T_2365 :
connect remapVecData[7], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[7]
node _T_2366 = eq(UInt<5>(0h1c), remapindex_7)
when _T_2366 :
connect remapVecData[7], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[7]
node _T_2367 = eq(UInt<5>(0h1d), remapindex_7)
when _T_2367 :
connect remapVecData[7], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[7]
node _T_2368 = eq(UInt<5>(0h1e), remapindex_7)
when _T_2368 :
connect remapVecData[7], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[7]
node _T_2369 = eq(UInt<5>(0h1f), remapindex_7)
when _T_2369 :
connect remapVecData[7], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[7]
node _remapindex_T_40 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_41 = sub(_remapindex_T_40, UInt<4>(0h8))
node _remapindex_T_42 = asUInt(_remapindex_T_41)
node _remapindex_T_43 = sub(_remapindex_T_42, read_start_index)
node _remapindex_T_44 = asUInt(_remapindex_T_43)
node remapindex_8 = rem(_remapindex_T_44, UInt<6>(0h20))
node _T_2370 = eq(UInt<1>(0h0), remapindex_8)
when _T_2370 :
connect remapVecData[8], Queue64_UInt8.io.deq.bits
connect remapVecValids[8], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[8]
node _T_2371 = eq(UInt<1>(0h1), remapindex_8)
when _T_2371 :
connect remapVecData[8], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[8]
node _T_2372 = eq(UInt<2>(0h2), remapindex_8)
when _T_2372 :
connect remapVecData[8], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[8]
node _T_2373 = eq(UInt<2>(0h3), remapindex_8)
when _T_2373 :
connect remapVecData[8], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[8]
node _T_2374 = eq(UInt<3>(0h4), remapindex_8)
when _T_2374 :
connect remapVecData[8], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[8]
node _T_2375 = eq(UInt<3>(0h5), remapindex_8)
when _T_2375 :
connect remapVecData[8], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[8]
node _T_2376 = eq(UInt<3>(0h6), remapindex_8)
when _T_2376 :
connect remapVecData[8], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[8]
node _T_2377 = eq(UInt<3>(0h7), remapindex_8)
when _T_2377 :
connect remapVecData[8], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[8]
node _T_2378 = eq(UInt<4>(0h8), remapindex_8)
when _T_2378 :
connect remapVecData[8], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[8]
node _T_2379 = eq(UInt<4>(0h9), remapindex_8)
when _T_2379 :
connect remapVecData[8], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[8]
node _T_2380 = eq(UInt<4>(0ha), remapindex_8)
when _T_2380 :
connect remapVecData[8], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[8]
node _T_2381 = eq(UInt<4>(0hb), remapindex_8)
when _T_2381 :
connect remapVecData[8], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[8]
node _T_2382 = eq(UInt<4>(0hc), remapindex_8)
when _T_2382 :
connect remapVecData[8], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[8]
node _T_2383 = eq(UInt<4>(0hd), remapindex_8)
when _T_2383 :
connect remapVecData[8], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[8]
node _T_2384 = eq(UInt<4>(0he), remapindex_8)
when _T_2384 :
connect remapVecData[8], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[8]
node _T_2385 = eq(UInt<4>(0hf), remapindex_8)
when _T_2385 :
connect remapVecData[8], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[8]
node _T_2386 = eq(UInt<5>(0h10), remapindex_8)
when _T_2386 :
connect remapVecData[8], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[8]
node _T_2387 = eq(UInt<5>(0h11), remapindex_8)
when _T_2387 :
connect remapVecData[8], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[8]
node _T_2388 = eq(UInt<5>(0h12), remapindex_8)
when _T_2388 :
connect remapVecData[8], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[8]
node _T_2389 = eq(UInt<5>(0h13), remapindex_8)
when _T_2389 :
connect remapVecData[8], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[8]
node _T_2390 = eq(UInt<5>(0h14), remapindex_8)
when _T_2390 :
connect remapVecData[8], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[8]
node _T_2391 = eq(UInt<5>(0h15), remapindex_8)
when _T_2391 :
connect remapVecData[8], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[8]
node _T_2392 = eq(UInt<5>(0h16), remapindex_8)
when _T_2392 :
connect remapVecData[8], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[8]
node _T_2393 = eq(UInt<5>(0h17), remapindex_8)
when _T_2393 :
connect remapVecData[8], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[8]
node _T_2394 = eq(UInt<5>(0h18), remapindex_8)
when _T_2394 :
connect remapVecData[8], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[8]
node _T_2395 = eq(UInt<5>(0h19), remapindex_8)
when _T_2395 :
connect remapVecData[8], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[8]
node _T_2396 = eq(UInt<5>(0h1a), remapindex_8)
when _T_2396 :
connect remapVecData[8], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[8]
node _T_2397 = eq(UInt<5>(0h1b), remapindex_8)
when _T_2397 :
connect remapVecData[8], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[8]
node _T_2398 = eq(UInt<5>(0h1c), remapindex_8)
when _T_2398 :
connect remapVecData[8], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[8]
node _T_2399 = eq(UInt<5>(0h1d), remapindex_8)
when _T_2399 :
connect remapVecData[8], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[8]
node _T_2400 = eq(UInt<5>(0h1e), remapindex_8)
when _T_2400 :
connect remapVecData[8], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[8]
node _T_2401 = eq(UInt<5>(0h1f), remapindex_8)
when _T_2401 :
connect remapVecData[8], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[8]
node _remapindex_T_45 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_46 = sub(_remapindex_T_45, UInt<4>(0h9))
node _remapindex_T_47 = asUInt(_remapindex_T_46)
node _remapindex_T_48 = sub(_remapindex_T_47, read_start_index)
node _remapindex_T_49 = asUInt(_remapindex_T_48)
node remapindex_9 = rem(_remapindex_T_49, UInt<6>(0h20))
node _T_2402 = eq(UInt<1>(0h0), remapindex_9)
when _T_2402 :
connect remapVecData[9], Queue64_UInt8.io.deq.bits
connect remapVecValids[9], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[9]
node _T_2403 = eq(UInt<1>(0h1), remapindex_9)
when _T_2403 :
connect remapVecData[9], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[9]
node _T_2404 = eq(UInt<2>(0h2), remapindex_9)
when _T_2404 :
connect remapVecData[9], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[9]
node _T_2405 = eq(UInt<2>(0h3), remapindex_9)
when _T_2405 :
connect remapVecData[9], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[9]
node _T_2406 = eq(UInt<3>(0h4), remapindex_9)
when _T_2406 :
connect remapVecData[9], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[9]
node _T_2407 = eq(UInt<3>(0h5), remapindex_9)
when _T_2407 :
connect remapVecData[9], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[9]
node _T_2408 = eq(UInt<3>(0h6), remapindex_9)
when _T_2408 :
connect remapVecData[9], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[9]
node _T_2409 = eq(UInt<3>(0h7), remapindex_9)
when _T_2409 :
connect remapVecData[9], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[9]
node _T_2410 = eq(UInt<4>(0h8), remapindex_9)
when _T_2410 :
connect remapVecData[9], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[9]
node _T_2411 = eq(UInt<4>(0h9), remapindex_9)
when _T_2411 :
connect remapVecData[9], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[9]
node _T_2412 = eq(UInt<4>(0ha), remapindex_9)
when _T_2412 :
connect remapVecData[9], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[9]
node _T_2413 = eq(UInt<4>(0hb), remapindex_9)
when _T_2413 :
connect remapVecData[9], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[9]
node _T_2414 = eq(UInt<4>(0hc), remapindex_9)
when _T_2414 :
connect remapVecData[9], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[9]
node _T_2415 = eq(UInt<4>(0hd), remapindex_9)
when _T_2415 :
connect remapVecData[9], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[9]
node _T_2416 = eq(UInt<4>(0he), remapindex_9)
when _T_2416 :
connect remapVecData[9], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[9]
node _T_2417 = eq(UInt<4>(0hf), remapindex_9)
when _T_2417 :
connect remapVecData[9], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[9]
node _T_2418 = eq(UInt<5>(0h10), remapindex_9)
when _T_2418 :
connect remapVecData[9], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[9]
node _T_2419 = eq(UInt<5>(0h11), remapindex_9)
when _T_2419 :
connect remapVecData[9], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[9]
node _T_2420 = eq(UInt<5>(0h12), remapindex_9)
when _T_2420 :
connect remapVecData[9], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[9]
node _T_2421 = eq(UInt<5>(0h13), remapindex_9)
when _T_2421 :
connect remapVecData[9], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[9]
node _T_2422 = eq(UInt<5>(0h14), remapindex_9)
when _T_2422 :
connect remapVecData[9], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[9]
node _T_2423 = eq(UInt<5>(0h15), remapindex_9)
when _T_2423 :
connect remapVecData[9], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[9]
node _T_2424 = eq(UInt<5>(0h16), remapindex_9)
when _T_2424 :
connect remapVecData[9], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[9]
node _T_2425 = eq(UInt<5>(0h17), remapindex_9)
when _T_2425 :
connect remapVecData[9], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[9]
node _T_2426 = eq(UInt<5>(0h18), remapindex_9)
when _T_2426 :
connect remapVecData[9], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[9]
node _T_2427 = eq(UInt<5>(0h19), remapindex_9)
when _T_2427 :
connect remapVecData[9], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[9]
node _T_2428 = eq(UInt<5>(0h1a), remapindex_9)
when _T_2428 :
connect remapVecData[9], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[9]
node _T_2429 = eq(UInt<5>(0h1b), remapindex_9)
when _T_2429 :
connect remapVecData[9], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[9]
node _T_2430 = eq(UInt<5>(0h1c), remapindex_9)
when _T_2430 :
connect remapVecData[9], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[9]
node _T_2431 = eq(UInt<5>(0h1d), remapindex_9)
when _T_2431 :
connect remapVecData[9], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[9]
node _T_2432 = eq(UInt<5>(0h1e), remapindex_9)
when _T_2432 :
connect remapVecData[9], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[9]
node _T_2433 = eq(UInt<5>(0h1f), remapindex_9)
when _T_2433 :
connect remapVecData[9], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[9]
node _remapindex_T_50 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_51 = sub(_remapindex_T_50, UInt<4>(0ha))
node _remapindex_T_52 = asUInt(_remapindex_T_51)
node _remapindex_T_53 = sub(_remapindex_T_52, read_start_index)
node _remapindex_T_54 = asUInt(_remapindex_T_53)
node remapindex_10 = rem(_remapindex_T_54, UInt<6>(0h20))
node _T_2434 = eq(UInt<1>(0h0), remapindex_10)
when _T_2434 :
connect remapVecData[10], Queue64_UInt8.io.deq.bits
connect remapVecValids[10], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[10]
node _T_2435 = eq(UInt<1>(0h1), remapindex_10)
when _T_2435 :
connect remapVecData[10], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[10]
node _T_2436 = eq(UInt<2>(0h2), remapindex_10)
when _T_2436 :
connect remapVecData[10], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[10]
node _T_2437 = eq(UInt<2>(0h3), remapindex_10)
when _T_2437 :
connect remapVecData[10], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[10]
node _T_2438 = eq(UInt<3>(0h4), remapindex_10)
when _T_2438 :
connect remapVecData[10], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[10]
node _T_2439 = eq(UInt<3>(0h5), remapindex_10)
when _T_2439 :
connect remapVecData[10], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[10]
node _T_2440 = eq(UInt<3>(0h6), remapindex_10)
when _T_2440 :
connect remapVecData[10], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[10]
node _T_2441 = eq(UInt<3>(0h7), remapindex_10)
when _T_2441 :
connect remapVecData[10], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[10]
node _T_2442 = eq(UInt<4>(0h8), remapindex_10)
when _T_2442 :
connect remapVecData[10], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[10]
node _T_2443 = eq(UInt<4>(0h9), remapindex_10)
when _T_2443 :
connect remapVecData[10], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[10]
node _T_2444 = eq(UInt<4>(0ha), remapindex_10)
when _T_2444 :
connect remapVecData[10], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[10]
node _T_2445 = eq(UInt<4>(0hb), remapindex_10)
when _T_2445 :
connect remapVecData[10], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[10]
node _T_2446 = eq(UInt<4>(0hc), remapindex_10)
when _T_2446 :
connect remapVecData[10], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[10]
node _T_2447 = eq(UInt<4>(0hd), remapindex_10)
when _T_2447 :
connect remapVecData[10], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[10]
node _T_2448 = eq(UInt<4>(0he), remapindex_10)
when _T_2448 :
connect remapVecData[10], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[10]
node _T_2449 = eq(UInt<4>(0hf), remapindex_10)
when _T_2449 :
connect remapVecData[10], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[10]
node _T_2450 = eq(UInt<5>(0h10), remapindex_10)
when _T_2450 :
connect remapVecData[10], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[10]
node _T_2451 = eq(UInt<5>(0h11), remapindex_10)
when _T_2451 :
connect remapVecData[10], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[10]
node _T_2452 = eq(UInt<5>(0h12), remapindex_10)
when _T_2452 :
connect remapVecData[10], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[10]
node _T_2453 = eq(UInt<5>(0h13), remapindex_10)
when _T_2453 :
connect remapVecData[10], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[10]
node _T_2454 = eq(UInt<5>(0h14), remapindex_10)
when _T_2454 :
connect remapVecData[10], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[10]
node _T_2455 = eq(UInt<5>(0h15), remapindex_10)
when _T_2455 :
connect remapVecData[10], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[10]
node _T_2456 = eq(UInt<5>(0h16), remapindex_10)
when _T_2456 :
connect remapVecData[10], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[10]
node _T_2457 = eq(UInt<5>(0h17), remapindex_10)
when _T_2457 :
connect remapVecData[10], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[10]
node _T_2458 = eq(UInt<5>(0h18), remapindex_10)
when _T_2458 :
connect remapVecData[10], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[10]
node _T_2459 = eq(UInt<5>(0h19), remapindex_10)
when _T_2459 :
connect remapVecData[10], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[10]
node _T_2460 = eq(UInt<5>(0h1a), remapindex_10)
when _T_2460 :
connect remapVecData[10], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[10]
node _T_2461 = eq(UInt<5>(0h1b), remapindex_10)
when _T_2461 :
connect remapVecData[10], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[10]
node _T_2462 = eq(UInt<5>(0h1c), remapindex_10)
when _T_2462 :
connect remapVecData[10], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[10]
node _T_2463 = eq(UInt<5>(0h1d), remapindex_10)
when _T_2463 :
connect remapVecData[10], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[10]
node _T_2464 = eq(UInt<5>(0h1e), remapindex_10)
when _T_2464 :
connect remapVecData[10], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[10]
node _T_2465 = eq(UInt<5>(0h1f), remapindex_10)
when _T_2465 :
connect remapVecData[10], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[10]
node _remapindex_T_55 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_56 = sub(_remapindex_T_55, UInt<4>(0hb))
node _remapindex_T_57 = asUInt(_remapindex_T_56)
node _remapindex_T_58 = sub(_remapindex_T_57, read_start_index)
node _remapindex_T_59 = asUInt(_remapindex_T_58)
node remapindex_11 = rem(_remapindex_T_59, UInt<6>(0h20))
node _T_2466 = eq(UInt<1>(0h0), remapindex_11)
when _T_2466 :
connect remapVecData[11], Queue64_UInt8.io.deq.bits
connect remapVecValids[11], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[11]
node _T_2467 = eq(UInt<1>(0h1), remapindex_11)
when _T_2467 :
connect remapVecData[11], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[11]
node _T_2468 = eq(UInt<2>(0h2), remapindex_11)
when _T_2468 :
connect remapVecData[11], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[11]
node _T_2469 = eq(UInt<2>(0h3), remapindex_11)
when _T_2469 :
connect remapVecData[11], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[11]
node _T_2470 = eq(UInt<3>(0h4), remapindex_11)
when _T_2470 :
connect remapVecData[11], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[11]
node _T_2471 = eq(UInt<3>(0h5), remapindex_11)
when _T_2471 :
connect remapVecData[11], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[11]
node _T_2472 = eq(UInt<3>(0h6), remapindex_11)
when _T_2472 :
connect remapVecData[11], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[11]
node _T_2473 = eq(UInt<3>(0h7), remapindex_11)
when _T_2473 :
connect remapVecData[11], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[11]
node _T_2474 = eq(UInt<4>(0h8), remapindex_11)
when _T_2474 :
connect remapVecData[11], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[11]
node _T_2475 = eq(UInt<4>(0h9), remapindex_11)
when _T_2475 :
connect remapVecData[11], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[11]
node _T_2476 = eq(UInt<4>(0ha), remapindex_11)
when _T_2476 :
connect remapVecData[11], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[11]
node _T_2477 = eq(UInt<4>(0hb), remapindex_11)
when _T_2477 :
connect remapVecData[11], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[11]
node _T_2478 = eq(UInt<4>(0hc), remapindex_11)
when _T_2478 :
connect remapVecData[11], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[11]
node _T_2479 = eq(UInt<4>(0hd), remapindex_11)
when _T_2479 :
connect remapVecData[11], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[11]
node _T_2480 = eq(UInt<4>(0he), remapindex_11)
when _T_2480 :
connect remapVecData[11], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[11]
node _T_2481 = eq(UInt<4>(0hf), remapindex_11)
when _T_2481 :
connect remapVecData[11], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[11]
node _T_2482 = eq(UInt<5>(0h10), remapindex_11)
when _T_2482 :
connect remapVecData[11], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[11]
node _T_2483 = eq(UInt<5>(0h11), remapindex_11)
when _T_2483 :
connect remapVecData[11], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[11]
node _T_2484 = eq(UInt<5>(0h12), remapindex_11)
when _T_2484 :
connect remapVecData[11], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[11]
node _T_2485 = eq(UInt<5>(0h13), remapindex_11)
when _T_2485 :
connect remapVecData[11], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[11]
node _T_2486 = eq(UInt<5>(0h14), remapindex_11)
when _T_2486 :
connect remapVecData[11], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[11]
node _T_2487 = eq(UInt<5>(0h15), remapindex_11)
when _T_2487 :
connect remapVecData[11], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[11]
node _T_2488 = eq(UInt<5>(0h16), remapindex_11)
when _T_2488 :
connect remapVecData[11], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[11]
node _T_2489 = eq(UInt<5>(0h17), remapindex_11)
when _T_2489 :
connect remapVecData[11], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[11]
node _T_2490 = eq(UInt<5>(0h18), remapindex_11)
when _T_2490 :
connect remapVecData[11], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[11]
node _T_2491 = eq(UInt<5>(0h19), remapindex_11)
when _T_2491 :
connect remapVecData[11], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[11]
node _T_2492 = eq(UInt<5>(0h1a), remapindex_11)
when _T_2492 :
connect remapVecData[11], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[11]
node _T_2493 = eq(UInt<5>(0h1b), remapindex_11)
when _T_2493 :
connect remapVecData[11], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[11]
node _T_2494 = eq(UInt<5>(0h1c), remapindex_11)
when _T_2494 :
connect remapVecData[11], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[11]
node _T_2495 = eq(UInt<5>(0h1d), remapindex_11)
when _T_2495 :
connect remapVecData[11], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[11]
node _T_2496 = eq(UInt<5>(0h1e), remapindex_11)
when _T_2496 :
connect remapVecData[11], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[11]
node _T_2497 = eq(UInt<5>(0h1f), remapindex_11)
when _T_2497 :
connect remapVecData[11], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[11]
node _remapindex_T_60 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_61 = sub(_remapindex_T_60, UInt<4>(0hc))
node _remapindex_T_62 = asUInt(_remapindex_T_61)
node _remapindex_T_63 = sub(_remapindex_T_62, read_start_index)
node _remapindex_T_64 = asUInt(_remapindex_T_63)
node remapindex_12 = rem(_remapindex_T_64, UInt<6>(0h20))
node _T_2498 = eq(UInt<1>(0h0), remapindex_12)
when _T_2498 :
connect remapVecData[12], Queue64_UInt8.io.deq.bits
connect remapVecValids[12], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[12]
node _T_2499 = eq(UInt<1>(0h1), remapindex_12)
when _T_2499 :
connect remapVecData[12], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[12]
node _T_2500 = eq(UInt<2>(0h2), remapindex_12)
when _T_2500 :
connect remapVecData[12], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[12]
node _T_2501 = eq(UInt<2>(0h3), remapindex_12)
when _T_2501 :
connect remapVecData[12], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[12]
node _T_2502 = eq(UInt<3>(0h4), remapindex_12)
when _T_2502 :
connect remapVecData[12], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[12]
node _T_2503 = eq(UInt<3>(0h5), remapindex_12)
when _T_2503 :
connect remapVecData[12], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[12]
node _T_2504 = eq(UInt<3>(0h6), remapindex_12)
when _T_2504 :
connect remapVecData[12], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[12]
node _T_2505 = eq(UInt<3>(0h7), remapindex_12)
when _T_2505 :
connect remapVecData[12], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[12]
node _T_2506 = eq(UInt<4>(0h8), remapindex_12)
when _T_2506 :
connect remapVecData[12], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[12]
node _T_2507 = eq(UInt<4>(0h9), remapindex_12)
when _T_2507 :
connect remapVecData[12], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[12]
node _T_2508 = eq(UInt<4>(0ha), remapindex_12)
when _T_2508 :
connect remapVecData[12], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[12]
node _T_2509 = eq(UInt<4>(0hb), remapindex_12)
when _T_2509 :
connect remapVecData[12], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[12]
node _T_2510 = eq(UInt<4>(0hc), remapindex_12)
when _T_2510 :
connect remapVecData[12], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[12]
node _T_2511 = eq(UInt<4>(0hd), remapindex_12)
when _T_2511 :
connect remapVecData[12], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[12]
node _T_2512 = eq(UInt<4>(0he), remapindex_12)
when _T_2512 :
connect remapVecData[12], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[12]
node _T_2513 = eq(UInt<4>(0hf), remapindex_12)
when _T_2513 :
connect remapVecData[12], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[12]
node _T_2514 = eq(UInt<5>(0h10), remapindex_12)
when _T_2514 :
connect remapVecData[12], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[12]
node _T_2515 = eq(UInt<5>(0h11), remapindex_12)
when _T_2515 :
connect remapVecData[12], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[12]
node _T_2516 = eq(UInt<5>(0h12), remapindex_12)
when _T_2516 :
connect remapVecData[12], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[12]
node _T_2517 = eq(UInt<5>(0h13), remapindex_12)
when _T_2517 :
connect remapVecData[12], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[12]
node _T_2518 = eq(UInt<5>(0h14), remapindex_12)
when _T_2518 :
connect remapVecData[12], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[12]
node _T_2519 = eq(UInt<5>(0h15), remapindex_12)
when _T_2519 :
connect remapVecData[12], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[12]
node _T_2520 = eq(UInt<5>(0h16), remapindex_12)
when _T_2520 :
connect remapVecData[12], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[12]
node _T_2521 = eq(UInt<5>(0h17), remapindex_12)
when _T_2521 :
connect remapVecData[12], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[12]
node _T_2522 = eq(UInt<5>(0h18), remapindex_12)
when _T_2522 :
connect remapVecData[12], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[12]
node _T_2523 = eq(UInt<5>(0h19), remapindex_12)
when _T_2523 :
connect remapVecData[12], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[12]
node _T_2524 = eq(UInt<5>(0h1a), remapindex_12)
when _T_2524 :
connect remapVecData[12], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[12]
node _T_2525 = eq(UInt<5>(0h1b), remapindex_12)
when _T_2525 :
connect remapVecData[12], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[12]
node _T_2526 = eq(UInt<5>(0h1c), remapindex_12)
when _T_2526 :
connect remapVecData[12], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[12]
node _T_2527 = eq(UInt<5>(0h1d), remapindex_12)
when _T_2527 :
connect remapVecData[12], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[12]
node _T_2528 = eq(UInt<5>(0h1e), remapindex_12)
when _T_2528 :
connect remapVecData[12], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[12]
node _T_2529 = eq(UInt<5>(0h1f), remapindex_12)
when _T_2529 :
connect remapVecData[12], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[12]
node _remapindex_T_65 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_66 = sub(_remapindex_T_65, UInt<4>(0hd))
node _remapindex_T_67 = asUInt(_remapindex_T_66)
node _remapindex_T_68 = sub(_remapindex_T_67, read_start_index)
node _remapindex_T_69 = asUInt(_remapindex_T_68)
node remapindex_13 = rem(_remapindex_T_69, UInt<6>(0h20))
node _T_2530 = eq(UInt<1>(0h0), remapindex_13)
when _T_2530 :
connect remapVecData[13], Queue64_UInt8.io.deq.bits
connect remapVecValids[13], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[13]
node _T_2531 = eq(UInt<1>(0h1), remapindex_13)
when _T_2531 :
connect remapVecData[13], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[13]
node _T_2532 = eq(UInt<2>(0h2), remapindex_13)
when _T_2532 :
connect remapVecData[13], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[13]
node _T_2533 = eq(UInt<2>(0h3), remapindex_13)
when _T_2533 :
connect remapVecData[13], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[13]
node _T_2534 = eq(UInt<3>(0h4), remapindex_13)
when _T_2534 :
connect remapVecData[13], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[13]
node _T_2535 = eq(UInt<3>(0h5), remapindex_13)
when _T_2535 :
connect remapVecData[13], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[13]
node _T_2536 = eq(UInt<3>(0h6), remapindex_13)
when _T_2536 :
connect remapVecData[13], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[13]
node _T_2537 = eq(UInt<3>(0h7), remapindex_13)
when _T_2537 :
connect remapVecData[13], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[13]
node _T_2538 = eq(UInt<4>(0h8), remapindex_13)
when _T_2538 :
connect remapVecData[13], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[13]
node _T_2539 = eq(UInt<4>(0h9), remapindex_13)
when _T_2539 :
connect remapVecData[13], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[13]
node _T_2540 = eq(UInt<4>(0ha), remapindex_13)
when _T_2540 :
connect remapVecData[13], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[13]
node _T_2541 = eq(UInt<4>(0hb), remapindex_13)
when _T_2541 :
connect remapVecData[13], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[13]
node _T_2542 = eq(UInt<4>(0hc), remapindex_13)
when _T_2542 :
connect remapVecData[13], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[13]
node _T_2543 = eq(UInt<4>(0hd), remapindex_13)
when _T_2543 :
connect remapVecData[13], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[13]
node _T_2544 = eq(UInt<4>(0he), remapindex_13)
when _T_2544 :
connect remapVecData[13], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[13]
node _T_2545 = eq(UInt<4>(0hf), remapindex_13)
when _T_2545 :
connect remapVecData[13], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[13]
node _T_2546 = eq(UInt<5>(0h10), remapindex_13)
when _T_2546 :
connect remapVecData[13], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[13]
node _T_2547 = eq(UInt<5>(0h11), remapindex_13)
when _T_2547 :
connect remapVecData[13], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[13]
node _T_2548 = eq(UInt<5>(0h12), remapindex_13)
when _T_2548 :
connect remapVecData[13], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[13]
node _T_2549 = eq(UInt<5>(0h13), remapindex_13)
when _T_2549 :
connect remapVecData[13], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[13]
node _T_2550 = eq(UInt<5>(0h14), remapindex_13)
when _T_2550 :
connect remapVecData[13], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[13]
node _T_2551 = eq(UInt<5>(0h15), remapindex_13)
when _T_2551 :
connect remapVecData[13], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[13]
node _T_2552 = eq(UInt<5>(0h16), remapindex_13)
when _T_2552 :
connect remapVecData[13], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[13]
node _T_2553 = eq(UInt<5>(0h17), remapindex_13)
when _T_2553 :
connect remapVecData[13], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[13]
node _T_2554 = eq(UInt<5>(0h18), remapindex_13)
when _T_2554 :
connect remapVecData[13], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[13]
node _T_2555 = eq(UInt<5>(0h19), remapindex_13)
when _T_2555 :
connect remapVecData[13], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[13]
node _T_2556 = eq(UInt<5>(0h1a), remapindex_13)
when _T_2556 :
connect remapVecData[13], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[13]
node _T_2557 = eq(UInt<5>(0h1b), remapindex_13)
when _T_2557 :
connect remapVecData[13], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[13]
node _T_2558 = eq(UInt<5>(0h1c), remapindex_13)
when _T_2558 :
connect remapVecData[13], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[13]
node _T_2559 = eq(UInt<5>(0h1d), remapindex_13)
when _T_2559 :
connect remapVecData[13], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[13]
node _T_2560 = eq(UInt<5>(0h1e), remapindex_13)
when _T_2560 :
connect remapVecData[13], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[13]
node _T_2561 = eq(UInt<5>(0h1f), remapindex_13)
when _T_2561 :
connect remapVecData[13], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[13]
node _remapindex_T_70 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_71 = sub(_remapindex_T_70, UInt<4>(0he))
node _remapindex_T_72 = asUInt(_remapindex_T_71)
node _remapindex_T_73 = sub(_remapindex_T_72, read_start_index)
node _remapindex_T_74 = asUInt(_remapindex_T_73)
node remapindex_14 = rem(_remapindex_T_74, UInt<6>(0h20))
node _T_2562 = eq(UInt<1>(0h0), remapindex_14)
when _T_2562 :
connect remapVecData[14], Queue64_UInt8.io.deq.bits
connect remapVecValids[14], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[14]
node _T_2563 = eq(UInt<1>(0h1), remapindex_14)
when _T_2563 :
connect remapVecData[14], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[14]
node _T_2564 = eq(UInt<2>(0h2), remapindex_14)
when _T_2564 :
connect remapVecData[14], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[14]
node _T_2565 = eq(UInt<2>(0h3), remapindex_14)
when _T_2565 :
connect remapVecData[14], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[14]
node _T_2566 = eq(UInt<3>(0h4), remapindex_14)
when _T_2566 :
connect remapVecData[14], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[14]
node _T_2567 = eq(UInt<3>(0h5), remapindex_14)
when _T_2567 :
connect remapVecData[14], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[14]
node _T_2568 = eq(UInt<3>(0h6), remapindex_14)
when _T_2568 :
connect remapVecData[14], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[14]
node _T_2569 = eq(UInt<3>(0h7), remapindex_14)
when _T_2569 :
connect remapVecData[14], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[14]
node _T_2570 = eq(UInt<4>(0h8), remapindex_14)
when _T_2570 :
connect remapVecData[14], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[14]
node _T_2571 = eq(UInt<4>(0h9), remapindex_14)
when _T_2571 :
connect remapVecData[14], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[14]
node _T_2572 = eq(UInt<4>(0ha), remapindex_14)
when _T_2572 :
connect remapVecData[14], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[14]
node _T_2573 = eq(UInt<4>(0hb), remapindex_14)
when _T_2573 :
connect remapVecData[14], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[14]
node _T_2574 = eq(UInt<4>(0hc), remapindex_14)
when _T_2574 :
connect remapVecData[14], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[14]
node _T_2575 = eq(UInt<4>(0hd), remapindex_14)
when _T_2575 :
connect remapVecData[14], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[14]
node _T_2576 = eq(UInt<4>(0he), remapindex_14)
when _T_2576 :
connect remapVecData[14], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[14]
node _T_2577 = eq(UInt<4>(0hf), remapindex_14)
when _T_2577 :
connect remapVecData[14], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[14]
node _T_2578 = eq(UInt<5>(0h10), remapindex_14)
when _T_2578 :
connect remapVecData[14], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[14]
node _T_2579 = eq(UInt<5>(0h11), remapindex_14)
when _T_2579 :
connect remapVecData[14], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[14]
node _T_2580 = eq(UInt<5>(0h12), remapindex_14)
when _T_2580 :
connect remapVecData[14], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[14]
node _T_2581 = eq(UInt<5>(0h13), remapindex_14)
when _T_2581 :
connect remapVecData[14], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[14]
node _T_2582 = eq(UInt<5>(0h14), remapindex_14)
when _T_2582 :
connect remapVecData[14], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[14]
node _T_2583 = eq(UInt<5>(0h15), remapindex_14)
when _T_2583 :
connect remapVecData[14], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[14]
node _T_2584 = eq(UInt<5>(0h16), remapindex_14)
when _T_2584 :
connect remapVecData[14], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[14]
node _T_2585 = eq(UInt<5>(0h17), remapindex_14)
when _T_2585 :
connect remapVecData[14], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[14]
node _T_2586 = eq(UInt<5>(0h18), remapindex_14)
when _T_2586 :
connect remapVecData[14], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[14]
node _T_2587 = eq(UInt<5>(0h19), remapindex_14)
when _T_2587 :
connect remapVecData[14], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[14]
node _T_2588 = eq(UInt<5>(0h1a), remapindex_14)
when _T_2588 :
connect remapVecData[14], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[14]
node _T_2589 = eq(UInt<5>(0h1b), remapindex_14)
when _T_2589 :
connect remapVecData[14], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[14]
node _T_2590 = eq(UInt<5>(0h1c), remapindex_14)
when _T_2590 :
connect remapVecData[14], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[14]
node _T_2591 = eq(UInt<5>(0h1d), remapindex_14)
when _T_2591 :
connect remapVecData[14], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[14]
node _T_2592 = eq(UInt<5>(0h1e), remapindex_14)
when _T_2592 :
connect remapVecData[14], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[14]
node _T_2593 = eq(UInt<5>(0h1f), remapindex_14)
when _T_2593 :
connect remapVecData[14], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[14]
node _remapindex_T_75 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_76 = sub(_remapindex_T_75, UInt<4>(0hf))
node _remapindex_T_77 = asUInt(_remapindex_T_76)
node _remapindex_T_78 = sub(_remapindex_T_77, read_start_index)
node _remapindex_T_79 = asUInt(_remapindex_T_78)
node remapindex_15 = rem(_remapindex_T_79, UInt<6>(0h20))
node _T_2594 = eq(UInt<1>(0h0), remapindex_15)
when _T_2594 :
connect remapVecData[15], Queue64_UInt8.io.deq.bits
connect remapVecValids[15], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[15]
node _T_2595 = eq(UInt<1>(0h1), remapindex_15)
when _T_2595 :
connect remapVecData[15], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[15]
node _T_2596 = eq(UInt<2>(0h2), remapindex_15)
when _T_2596 :
connect remapVecData[15], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[15]
node _T_2597 = eq(UInt<2>(0h3), remapindex_15)
when _T_2597 :
connect remapVecData[15], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[15]
node _T_2598 = eq(UInt<3>(0h4), remapindex_15)
when _T_2598 :
connect remapVecData[15], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[15]
node _T_2599 = eq(UInt<3>(0h5), remapindex_15)
when _T_2599 :
connect remapVecData[15], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[15]
node _T_2600 = eq(UInt<3>(0h6), remapindex_15)
when _T_2600 :
connect remapVecData[15], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[15]
node _T_2601 = eq(UInt<3>(0h7), remapindex_15)
when _T_2601 :
connect remapVecData[15], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[15]
node _T_2602 = eq(UInt<4>(0h8), remapindex_15)
when _T_2602 :
connect remapVecData[15], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[15]
node _T_2603 = eq(UInt<4>(0h9), remapindex_15)
when _T_2603 :
connect remapVecData[15], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[15]
node _T_2604 = eq(UInt<4>(0ha), remapindex_15)
when _T_2604 :
connect remapVecData[15], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[15]
node _T_2605 = eq(UInt<4>(0hb), remapindex_15)
when _T_2605 :
connect remapVecData[15], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[15]
node _T_2606 = eq(UInt<4>(0hc), remapindex_15)
when _T_2606 :
connect remapVecData[15], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[15]
node _T_2607 = eq(UInt<4>(0hd), remapindex_15)
when _T_2607 :
connect remapVecData[15], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[15]
node _T_2608 = eq(UInt<4>(0he), remapindex_15)
when _T_2608 :
connect remapVecData[15], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[15]
node _T_2609 = eq(UInt<4>(0hf), remapindex_15)
when _T_2609 :
connect remapVecData[15], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[15]
node _T_2610 = eq(UInt<5>(0h10), remapindex_15)
when _T_2610 :
connect remapVecData[15], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[15]
node _T_2611 = eq(UInt<5>(0h11), remapindex_15)
when _T_2611 :
connect remapVecData[15], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[15]
node _T_2612 = eq(UInt<5>(0h12), remapindex_15)
when _T_2612 :
connect remapVecData[15], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[15]
node _T_2613 = eq(UInt<5>(0h13), remapindex_15)
when _T_2613 :
connect remapVecData[15], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[15]
node _T_2614 = eq(UInt<5>(0h14), remapindex_15)
when _T_2614 :
connect remapVecData[15], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[15]
node _T_2615 = eq(UInt<5>(0h15), remapindex_15)
when _T_2615 :
connect remapVecData[15], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[15]
node _T_2616 = eq(UInt<5>(0h16), remapindex_15)
when _T_2616 :
connect remapVecData[15], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[15]
node _T_2617 = eq(UInt<5>(0h17), remapindex_15)
when _T_2617 :
connect remapVecData[15], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[15]
node _T_2618 = eq(UInt<5>(0h18), remapindex_15)
when _T_2618 :
connect remapVecData[15], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[15]
node _T_2619 = eq(UInt<5>(0h19), remapindex_15)
when _T_2619 :
connect remapVecData[15], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[15]
node _T_2620 = eq(UInt<5>(0h1a), remapindex_15)
when _T_2620 :
connect remapVecData[15], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[15]
node _T_2621 = eq(UInt<5>(0h1b), remapindex_15)
when _T_2621 :
connect remapVecData[15], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[15]
node _T_2622 = eq(UInt<5>(0h1c), remapindex_15)
when _T_2622 :
connect remapVecData[15], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[15]
node _T_2623 = eq(UInt<5>(0h1d), remapindex_15)
when _T_2623 :
connect remapVecData[15], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[15]
node _T_2624 = eq(UInt<5>(0h1e), remapindex_15)
when _T_2624 :
connect remapVecData[15], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[15]
node _T_2625 = eq(UInt<5>(0h1f), remapindex_15)
when _T_2625 :
connect remapVecData[15], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[15]
node _remapindex_T_80 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_81 = sub(_remapindex_T_80, UInt<5>(0h10))
node _remapindex_T_82 = asUInt(_remapindex_T_81)
node _remapindex_T_83 = sub(_remapindex_T_82, read_start_index)
node _remapindex_T_84 = asUInt(_remapindex_T_83)
node remapindex_16 = rem(_remapindex_T_84, UInt<6>(0h20))
node _T_2626 = eq(UInt<1>(0h0), remapindex_16)
when _T_2626 :
connect remapVecData[16], Queue64_UInt8.io.deq.bits
connect remapVecValids[16], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[16]
node _T_2627 = eq(UInt<1>(0h1), remapindex_16)
when _T_2627 :
connect remapVecData[16], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[16]
node _T_2628 = eq(UInt<2>(0h2), remapindex_16)
when _T_2628 :
connect remapVecData[16], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[16]
node _T_2629 = eq(UInt<2>(0h3), remapindex_16)
when _T_2629 :
connect remapVecData[16], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[16]
node _T_2630 = eq(UInt<3>(0h4), remapindex_16)
when _T_2630 :
connect remapVecData[16], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[16]
node _T_2631 = eq(UInt<3>(0h5), remapindex_16)
when _T_2631 :
connect remapVecData[16], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[16]
node _T_2632 = eq(UInt<3>(0h6), remapindex_16)
when _T_2632 :
connect remapVecData[16], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[16]
node _T_2633 = eq(UInt<3>(0h7), remapindex_16)
when _T_2633 :
connect remapVecData[16], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[16]
node _T_2634 = eq(UInt<4>(0h8), remapindex_16)
when _T_2634 :
connect remapVecData[16], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[16]
node _T_2635 = eq(UInt<4>(0h9), remapindex_16)
when _T_2635 :
connect remapVecData[16], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[16]
node _T_2636 = eq(UInt<4>(0ha), remapindex_16)
when _T_2636 :
connect remapVecData[16], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[16]
node _T_2637 = eq(UInt<4>(0hb), remapindex_16)
when _T_2637 :
connect remapVecData[16], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[16]
node _T_2638 = eq(UInt<4>(0hc), remapindex_16)
when _T_2638 :
connect remapVecData[16], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[16]
node _T_2639 = eq(UInt<4>(0hd), remapindex_16)
when _T_2639 :
connect remapVecData[16], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[16]
node _T_2640 = eq(UInt<4>(0he), remapindex_16)
when _T_2640 :
connect remapVecData[16], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[16]
node _T_2641 = eq(UInt<4>(0hf), remapindex_16)
when _T_2641 :
connect remapVecData[16], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[16]
node _T_2642 = eq(UInt<5>(0h10), remapindex_16)
when _T_2642 :
connect remapVecData[16], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[16]
node _T_2643 = eq(UInt<5>(0h11), remapindex_16)
when _T_2643 :
connect remapVecData[16], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[16]
node _T_2644 = eq(UInt<5>(0h12), remapindex_16)
when _T_2644 :
connect remapVecData[16], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[16]
node _T_2645 = eq(UInt<5>(0h13), remapindex_16)
when _T_2645 :
connect remapVecData[16], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[16]
node _T_2646 = eq(UInt<5>(0h14), remapindex_16)
when _T_2646 :
connect remapVecData[16], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[16]
node _T_2647 = eq(UInt<5>(0h15), remapindex_16)
when _T_2647 :
connect remapVecData[16], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[16]
node _T_2648 = eq(UInt<5>(0h16), remapindex_16)
when _T_2648 :
connect remapVecData[16], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[16]
node _T_2649 = eq(UInt<5>(0h17), remapindex_16)
when _T_2649 :
connect remapVecData[16], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[16]
node _T_2650 = eq(UInt<5>(0h18), remapindex_16)
when _T_2650 :
connect remapVecData[16], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[16]
node _T_2651 = eq(UInt<5>(0h19), remapindex_16)
when _T_2651 :
connect remapVecData[16], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[16]
node _T_2652 = eq(UInt<5>(0h1a), remapindex_16)
when _T_2652 :
connect remapVecData[16], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[16]
node _T_2653 = eq(UInt<5>(0h1b), remapindex_16)
when _T_2653 :
connect remapVecData[16], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[16]
node _T_2654 = eq(UInt<5>(0h1c), remapindex_16)
when _T_2654 :
connect remapVecData[16], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[16]
node _T_2655 = eq(UInt<5>(0h1d), remapindex_16)
when _T_2655 :
connect remapVecData[16], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[16]
node _T_2656 = eq(UInt<5>(0h1e), remapindex_16)
when _T_2656 :
connect remapVecData[16], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[16]
node _T_2657 = eq(UInt<5>(0h1f), remapindex_16)
when _T_2657 :
connect remapVecData[16], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[16]
node _remapindex_T_85 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_86 = sub(_remapindex_T_85, UInt<5>(0h11))
node _remapindex_T_87 = asUInt(_remapindex_T_86)
node _remapindex_T_88 = sub(_remapindex_T_87, read_start_index)
node _remapindex_T_89 = asUInt(_remapindex_T_88)
node remapindex_17 = rem(_remapindex_T_89, UInt<6>(0h20))
node _T_2658 = eq(UInt<1>(0h0), remapindex_17)
when _T_2658 :
connect remapVecData[17], Queue64_UInt8.io.deq.bits
connect remapVecValids[17], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[17]
node _T_2659 = eq(UInt<1>(0h1), remapindex_17)
when _T_2659 :
connect remapVecData[17], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[17]
node _T_2660 = eq(UInt<2>(0h2), remapindex_17)
when _T_2660 :
connect remapVecData[17], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[17]
node _T_2661 = eq(UInt<2>(0h3), remapindex_17)
when _T_2661 :
connect remapVecData[17], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[17]
node _T_2662 = eq(UInt<3>(0h4), remapindex_17)
when _T_2662 :
connect remapVecData[17], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[17]
node _T_2663 = eq(UInt<3>(0h5), remapindex_17)
when _T_2663 :
connect remapVecData[17], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[17]
node _T_2664 = eq(UInt<3>(0h6), remapindex_17)
when _T_2664 :
connect remapVecData[17], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[17]
node _T_2665 = eq(UInt<3>(0h7), remapindex_17)
when _T_2665 :
connect remapVecData[17], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[17]
node _T_2666 = eq(UInt<4>(0h8), remapindex_17)
when _T_2666 :
connect remapVecData[17], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[17]
node _T_2667 = eq(UInt<4>(0h9), remapindex_17)
when _T_2667 :
connect remapVecData[17], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[17]
node _T_2668 = eq(UInt<4>(0ha), remapindex_17)
when _T_2668 :
connect remapVecData[17], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[17]
node _T_2669 = eq(UInt<4>(0hb), remapindex_17)
when _T_2669 :
connect remapVecData[17], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[17]
node _T_2670 = eq(UInt<4>(0hc), remapindex_17)
when _T_2670 :
connect remapVecData[17], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[17]
node _T_2671 = eq(UInt<4>(0hd), remapindex_17)
when _T_2671 :
connect remapVecData[17], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[17]
node _T_2672 = eq(UInt<4>(0he), remapindex_17)
when _T_2672 :
connect remapVecData[17], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[17]
node _T_2673 = eq(UInt<4>(0hf), remapindex_17)
when _T_2673 :
connect remapVecData[17], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[17]
node _T_2674 = eq(UInt<5>(0h10), remapindex_17)
when _T_2674 :
connect remapVecData[17], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[17]
node _T_2675 = eq(UInt<5>(0h11), remapindex_17)
when _T_2675 :
connect remapVecData[17], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[17]
node _T_2676 = eq(UInt<5>(0h12), remapindex_17)
when _T_2676 :
connect remapVecData[17], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[17]
node _T_2677 = eq(UInt<5>(0h13), remapindex_17)
when _T_2677 :
connect remapVecData[17], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[17]
node _T_2678 = eq(UInt<5>(0h14), remapindex_17)
when _T_2678 :
connect remapVecData[17], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[17]
node _T_2679 = eq(UInt<5>(0h15), remapindex_17)
when _T_2679 :
connect remapVecData[17], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[17]
node _T_2680 = eq(UInt<5>(0h16), remapindex_17)
when _T_2680 :
connect remapVecData[17], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[17]
node _T_2681 = eq(UInt<5>(0h17), remapindex_17)
when _T_2681 :
connect remapVecData[17], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[17]
node _T_2682 = eq(UInt<5>(0h18), remapindex_17)
when _T_2682 :
connect remapVecData[17], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[17]
node _T_2683 = eq(UInt<5>(0h19), remapindex_17)
when _T_2683 :
connect remapVecData[17], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[17]
node _T_2684 = eq(UInt<5>(0h1a), remapindex_17)
when _T_2684 :
connect remapVecData[17], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[17]
node _T_2685 = eq(UInt<5>(0h1b), remapindex_17)
when _T_2685 :
connect remapVecData[17], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[17]
node _T_2686 = eq(UInt<5>(0h1c), remapindex_17)
when _T_2686 :
connect remapVecData[17], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[17]
node _T_2687 = eq(UInt<5>(0h1d), remapindex_17)
when _T_2687 :
connect remapVecData[17], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[17]
node _T_2688 = eq(UInt<5>(0h1e), remapindex_17)
when _T_2688 :
connect remapVecData[17], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[17]
node _T_2689 = eq(UInt<5>(0h1f), remapindex_17)
when _T_2689 :
connect remapVecData[17], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[17]
node _remapindex_T_90 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_91 = sub(_remapindex_T_90, UInt<5>(0h12))
node _remapindex_T_92 = asUInt(_remapindex_T_91)
node _remapindex_T_93 = sub(_remapindex_T_92, read_start_index)
node _remapindex_T_94 = asUInt(_remapindex_T_93)
node remapindex_18 = rem(_remapindex_T_94, UInt<6>(0h20))
node _T_2690 = eq(UInt<1>(0h0), remapindex_18)
when _T_2690 :
connect remapVecData[18], Queue64_UInt8.io.deq.bits
connect remapVecValids[18], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[18]
node _T_2691 = eq(UInt<1>(0h1), remapindex_18)
when _T_2691 :
connect remapVecData[18], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[18]
node _T_2692 = eq(UInt<2>(0h2), remapindex_18)
when _T_2692 :
connect remapVecData[18], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[18]
node _T_2693 = eq(UInt<2>(0h3), remapindex_18)
when _T_2693 :
connect remapVecData[18], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[18]
node _T_2694 = eq(UInt<3>(0h4), remapindex_18)
when _T_2694 :
connect remapVecData[18], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[18]
node _T_2695 = eq(UInt<3>(0h5), remapindex_18)
when _T_2695 :
connect remapVecData[18], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[18]
node _T_2696 = eq(UInt<3>(0h6), remapindex_18)
when _T_2696 :
connect remapVecData[18], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[18]
node _T_2697 = eq(UInt<3>(0h7), remapindex_18)
when _T_2697 :
connect remapVecData[18], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[18]
node _T_2698 = eq(UInt<4>(0h8), remapindex_18)
when _T_2698 :
connect remapVecData[18], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[18]
node _T_2699 = eq(UInt<4>(0h9), remapindex_18)
when _T_2699 :
connect remapVecData[18], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[18]
node _T_2700 = eq(UInt<4>(0ha), remapindex_18)
when _T_2700 :
connect remapVecData[18], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[18]
node _T_2701 = eq(UInt<4>(0hb), remapindex_18)
when _T_2701 :
connect remapVecData[18], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[18]
node _T_2702 = eq(UInt<4>(0hc), remapindex_18)
when _T_2702 :
connect remapVecData[18], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[18]
node _T_2703 = eq(UInt<4>(0hd), remapindex_18)
when _T_2703 :
connect remapVecData[18], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[18]
node _T_2704 = eq(UInt<4>(0he), remapindex_18)
when _T_2704 :
connect remapVecData[18], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[18]
node _T_2705 = eq(UInt<4>(0hf), remapindex_18)
when _T_2705 :
connect remapVecData[18], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[18]
node _T_2706 = eq(UInt<5>(0h10), remapindex_18)
when _T_2706 :
connect remapVecData[18], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[18]
node _T_2707 = eq(UInt<5>(0h11), remapindex_18)
when _T_2707 :
connect remapVecData[18], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[18]
node _T_2708 = eq(UInt<5>(0h12), remapindex_18)
when _T_2708 :
connect remapVecData[18], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[18]
node _T_2709 = eq(UInt<5>(0h13), remapindex_18)
when _T_2709 :
connect remapVecData[18], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[18]
node _T_2710 = eq(UInt<5>(0h14), remapindex_18)
when _T_2710 :
connect remapVecData[18], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[18]
node _T_2711 = eq(UInt<5>(0h15), remapindex_18)
when _T_2711 :
connect remapVecData[18], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[18]
node _T_2712 = eq(UInt<5>(0h16), remapindex_18)
when _T_2712 :
connect remapVecData[18], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[18]
node _T_2713 = eq(UInt<5>(0h17), remapindex_18)
when _T_2713 :
connect remapVecData[18], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[18]
node _T_2714 = eq(UInt<5>(0h18), remapindex_18)
when _T_2714 :
connect remapVecData[18], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[18]
node _T_2715 = eq(UInt<5>(0h19), remapindex_18)
when _T_2715 :
connect remapVecData[18], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[18]
node _T_2716 = eq(UInt<5>(0h1a), remapindex_18)
when _T_2716 :
connect remapVecData[18], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[18]
node _T_2717 = eq(UInt<5>(0h1b), remapindex_18)
when _T_2717 :
connect remapVecData[18], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[18]
node _T_2718 = eq(UInt<5>(0h1c), remapindex_18)
when _T_2718 :
connect remapVecData[18], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[18]
node _T_2719 = eq(UInt<5>(0h1d), remapindex_18)
when _T_2719 :
connect remapVecData[18], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[18]
node _T_2720 = eq(UInt<5>(0h1e), remapindex_18)
when _T_2720 :
connect remapVecData[18], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[18]
node _T_2721 = eq(UInt<5>(0h1f), remapindex_18)
when _T_2721 :
connect remapVecData[18], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[18]
node _remapindex_T_95 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_96 = sub(_remapindex_T_95, UInt<5>(0h13))
node _remapindex_T_97 = asUInt(_remapindex_T_96)
node _remapindex_T_98 = sub(_remapindex_T_97, read_start_index)
node _remapindex_T_99 = asUInt(_remapindex_T_98)
node remapindex_19 = rem(_remapindex_T_99, UInt<6>(0h20))
node _T_2722 = eq(UInt<1>(0h0), remapindex_19)
when _T_2722 :
connect remapVecData[19], Queue64_UInt8.io.deq.bits
connect remapVecValids[19], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[19]
node _T_2723 = eq(UInt<1>(0h1), remapindex_19)
when _T_2723 :
connect remapVecData[19], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[19]
node _T_2724 = eq(UInt<2>(0h2), remapindex_19)
when _T_2724 :
connect remapVecData[19], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[19]
node _T_2725 = eq(UInt<2>(0h3), remapindex_19)
when _T_2725 :
connect remapVecData[19], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[19]
node _T_2726 = eq(UInt<3>(0h4), remapindex_19)
when _T_2726 :
connect remapVecData[19], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[19]
node _T_2727 = eq(UInt<3>(0h5), remapindex_19)
when _T_2727 :
connect remapVecData[19], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[19]
node _T_2728 = eq(UInt<3>(0h6), remapindex_19)
when _T_2728 :
connect remapVecData[19], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[19]
node _T_2729 = eq(UInt<3>(0h7), remapindex_19)
when _T_2729 :
connect remapVecData[19], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[19]
node _T_2730 = eq(UInt<4>(0h8), remapindex_19)
when _T_2730 :
connect remapVecData[19], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[19]
node _T_2731 = eq(UInt<4>(0h9), remapindex_19)
when _T_2731 :
connect remapVecData[19], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[19]
node _T_2732 = eq(UInt<4>(0ha), remapindex_19)
when _T_2732 :
connect remapVecData[19], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[19]
node _T_2733 = eq(UInt<4>(0hb), remapindex_19)
when _T_2733 :
connect remapVecData[19], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[19]
node _T_2734 = eq(UInt<4>(0hc), remapindex_19)
when _T_2734 :
connect remapVecData[19], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[19]
node _T_2735 = eq(UInt<4>(0hd), remapindex_19)
when _T_2735 :
connect remapVecData[19], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[19]
node _T_2736 = eq(UInt<4>(0he), remapindex_19)
when _T_2736 :
connect remapVecData[19], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[19]
node _T_2737 = eq(UInt<4>(0hf), remapindex_19)
when _T_2737 :
connect remapVecData[19], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[19]
node _T_2738 = eq(UInt<5>(0h10), remapindex_19)
when _T_2738 :
connect remapVecData[19], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[19]
node _T_2739 = eq(UInt<5>(0h11), remapindex_19)
when _T_2739 :
connect remapVecData[19], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[19]
node _T_2740 = eq(UInt<5>(0h12), remapindex_19)
when _T_2740 :
connect remapVecData[19], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[19]
node _T_2741 = eq(UInt<5>(0h13), remapindex_19)
when _T_2741 :
connect remapVecData[19], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[19]
node _T_2742 = eq(UInt<5>(0h14), remapindex_19)
when _T_2742 :
connect remapVecData[19], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[19]
node _T_2743 = eq(UInt<5>(0h15), remapindex_19)
when _T_2743 :
connect remapVecData[19], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[19]
node _T_2744 = eq(UInt<5>(0h16), remapindex_19)
when _T_2744 :
connect remapVecData[19], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[19]
node _T_2745 = eq(UInt<5>(0h17), remapindex_19)
when _T_2745 :
connect remapVecData[19], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[19]
node _T_2746 = eq(UInt<5>(0h18), remapindex_19)
when _T_2746 :
connect remapVecData[19], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[19]
node _T_2747 = eq(UInt<5>(0h19), remapindex_19)
when _T_2747 :
connect remapVecData[19], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[19]
node _T_2748 = eq(UInt<5>(0h1a), remapindex_19)
when _T_2748 :
connect remapVecData[19], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[19]
node _T_2749 = eq(UInt<5>(0h1b), remapindex_19)
when _T_2749 :
connect remapVecData[19], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[19]
node _T_2750 = eq(UInt<5>(0h1c), remapindex_19)
when _T_2750 :
connect remapVecData[19], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[19]
node _T_2751 = eq(UInt<5>(0h1d), remapindex_19)
when _T_2751 :
connect remapVecData[19], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[19]
node _T_2752 = eq(UInt<5>(0h1e), remapindex_19)
when _T_2752 :
connect remapVecData[19], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[19]
node _T_2753 = eq(UInt<5>(0h1f), remapindex_19)
when _T_2753 :
connect remapVecData[19], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[19]
node _remapindex_T_100 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_101 = sub(_remapindex_T_100, UInt<5>(0h14))
node _remapindex_T_102 = asUInt(_remapindex_T_101)
node _remapindex_T_103 = sub(_remapindex_T_102, read_start_index)
node _remapindex_T_104 = asUInt(_remapindex_T_103)
node remapindex_20 = rem(_remapindex_T_104, UInt<6>(0h20))
node _T_2754 = eq(UInt<1>(0h0), remapindex_20)
when _T_2754 :
connect remapVecData[20], Queue64_UInt8.io.deq.bits
connect remapVecValids[20], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[20]
node _T_2755 = eq(UInt<1>(0h1), remapindex_20)
when _T_2755 :
connect remapVecData[20], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[20]
node _T_2756 = eq(UInt<2>(0h2), remapindex_20)
when _T_2756 :
connect remapVecData[20], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[20]
node _T_2757 = eq(UInt<2>(0h3), remapindex_20)
when _T_2757 :
connect remapVecData[20], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[20]
node _T_2758 = eq(UInt<3>(0h4), remapindex_20)
when _T_2758 :
connect remapVecData[20], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[20]
node _T_2759 = eq(UInt<3>(0h5), remapindex_20)
when _T_2759 :
connect remapVecData[20], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[20]
node _T_2760 = eq(UInt<3>(0h6), remapindex_20)
when _T_2760 :
connect remapVecData[20], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[20]
node _T_2761 = eq(UInt<3>(0h7), remapindex_20)
when _T_2761 :
connect remapVecData[20], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[20]
node _T_2762 = eq(UInt<4>(0h8), remapindex_20)
when _T_2762 :
connect remapVecData[20], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[20]
node _T_2763 = eq(UInt<4>(0h9), remapindex_20)
when _T_2763 :
connect remapVecData[20], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[20]
node _T_2764 = eq(UInt<4>(0ha), remapindex_20)
when _T_2764 :
connect remapVecData[20], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[20]
node _T_2765 = eq(UInt<4>(0hb), remapindex_20)
when _T_2765 :
connect remapVecData[20], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[20]
node _T_2766 = eq(UInt<4>(0hc), remapindex_20)
when _T_2766 :
connect remapVecData[20], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[20]
node _T_2767 = eq(UInt<4>(0hd), remapindex_20)
when _T_2767 :
connect remapVecData[20], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[20]
node _T_2768 = eq(UInt<4>(0he), remapindex_20)
when _T_2768 :
connect remapVecData[20], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[20]
node _T_2769 = eq(UInt<4>(0hf), remapindex_20)
when _T_2769 :
connect remapVecData[20], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[20]
node _T_2770 = eq(UInt<5>(0h10), remapindex_20)
when _T_2770 :
connect remapVecData[20], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[20]
node _T_2771 = eq(UInt<5>(0h11), remapindex_20)
when _T_2771 :
connect remapVecData[20], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[20]
node _T_2772 = eq(UInt<5>(0h12), remapindex_20)
when _T_2772 :
connect remapVecData[20], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[20]
node _T_2773 = eq(UInt<5>(0h13), remapindex_20)
when _T_2773 :
connect remapVecData[20], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[20]
node _T_2774 = eq(UInt<5>(0h14), remapindex_20)
when _T_2774 :
connect remapVecData[20], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[20]
node _T_2775 = eq(UInt<5>(0h15), remapindex_20)
when _T_2775 :
connect remapVecData[20], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[20]
node _T_2776 = eq(UInt<5>(0h16), remapindex_20)
when _T_2776 :
connect remapVecData[20], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[20]
node _T_2777 = eq(UInt<5>(0h17), remapindex_20)
when _T_2777 :
connect remapVecData[20], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[20]
node _T_2778 = eq(UInt<5>(0h18), remapindex_20)
when _T_2778 :
connect remapVecData[20], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[20]
node _T_2779 = eq(UInt<5>(0h19), remapindex_20)
when _T_2779 :
connect remapVecData[20], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[20]
node _T_2780 = eq(UInt<5>(0h1a), remapindex_20)
when _T_2780 :
connect remapVecData[20], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[20]
node _T_2781 = eq(UInt<5>(0h1b), remapindex_20)
when _T_2781 :
connect remapVecData[20], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[20]
node _T_2782 = eq(UInt<5>(0h1c), remapindex_20)
when _T_2782 :
connect remapVecData[20], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[20]
node _T_2783 = eq(UInt<5>(0h1d), remapindex_20)
when _T_2783 :
connect remapVecData[20], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[20]
node _T_2784 = eq(UInt<5>(0h1e), remapindex_20)
when _T_2784 :
connect remapVecData[20], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[20]
node _T_2785 = eq(UInt<5>(0h1f), remapindex_20)
when _T_2785 :
connect remapVecData[20], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[20]
node _remapindex_T_105 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_106 = sub(_remapindex_T_105, UInt<5>(0h15))
node _remapindex_T_107 = asUInt(_remapindex_T_106)
node _remapindex_T_108 = sub(_remapindex_T_107, read_start_index)
node _remapindex_T_109 = asUInt(_remapindex_T_108)
node remapindex_21 = rem(_remapindex_T_109, UInt<6>(0h20))
node _T_2786 = eq(UInt<1>(0h0), remapindex_21)
when _T_2786 :
connect remapVecData[21], Queue64_UInt8.io.deq.bits
connect remapVecValids[21], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[21]
node _T_2787 = eq(UInt<1>(0h1), remapindex_21)
when _T_2787 :
connect remapVecData[21], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[21]
node _T_2788 = eq(UInt<2>(0h2), remapindex_21)
when _T_2788 :
connect remapVecData[21], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[21]
node _T_2789 = eq(UInt<2>(0h3), remapindex_21)
when _T_2789 :
connect remapVecData[21], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[21]
node _T_2790 = eq(UInt<3>(0h4), remapindex_21)
when _T_2790 :
connect remapVecData[21], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[21]
node _T_2791 = eq(UInt<3>(0h5), remapindex_21)
when _T_2791 :
connect remapVecData[21], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[21]
node _T_2792 = eq(UInt<3>(0h6), remapindex_21)
when _T_2792 :
connect remapVecData[21], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[21]
node _T_2793 = eq(UInt<3>(0h7), remapindex_21)
when _T_2793 :
connect remapVecData[21], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[21]
node _T_2794 = eq(UInt<4>(0h8), remapindex_21)
when _T_2794 :
connect remapVecData[21], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[21]
node _T_2795 = eq(UInt<4>(0h9), remapindex_21)
when _T_2795 :
connect remapVecData[21], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[21]
node _T_2796 = eq(UInt<4>(0ha), remapindex_21)
when _T_2796 :
connect remapVecData[21], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[21]
node _T_2797 = eq(UInt<4>(0hb), remapindex_21)
when _T_2797 :
connect remapVecData[21], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[21]
node _T_2798 = eq(UInt<4>(0hc), remapindex_21)
when _T_2798 :
connect remapVecData[21], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[21]
node _T_2799 = eq(UInt<4>(0hd), remapindex_21)
when _T_2799 :
connect remapVecData[21], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[21]
node _T_2800 = eq(UInt<4>(0he), remapindex_21)
when _T_2800 :
connect remapVecData[21], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[21]
node _T_2801 = eq(UInt<4>(0hf), remapindex_21)
when _T_2801 :
connect remapVecData[21], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[21]
node _T_2802 = eq(UInt<5>(0h10), remapindex_21)
when _T_2802 :
connect remapVecData[21], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[21]
node _T_2803 = eq(UInt<5>(0h11), remapindex_21)
when _T_2803 :
connect remapVecData[21], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[21]
node _T_2804 = eq(UInt<5>(0h12), remapindex_21)
when _T_2804 :
connect remapVecData[21], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[21]
node _T_2805 = eq(UInt<5>(0h13), remapindex_21)
when _T_2805 :
connect remapVecData[21], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[21]
node _T_2806 = eq(UInt<5>(0h14), remapindex_21)
when _T_2806 :
connect remapVecData[21], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[21]
node _T_2807 = eq(UInt<5>(0h15), remapindex_21)
when _T_2807 :
connect remapVecData[21], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[21]
node _T_2808 = eq(UInt<5>(0h16), remapindex_21)
when _T_2808 :
connect remapVecData[21], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[21]
node _T_2809 = eq(UInt<5>(0h17), remapindex_21)
when _T_2809 :
connect remapVecData[21], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[21]
node _T_2810 = eq(UInt<5>(0h18), remapindex_21)
when _T_2810 :
connect remapVecData[21], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[21]
node _T_2811 = eq(UInt<5>(0h19), remapindex_21)
when _T_2811 :
connect remapVecData[21], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[21]
node _T_2812 = eq(UInt<5>(0h1a), remapindex_21)
when _T_2812 :
connect remapVecData[21], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[21]
node _T_2813 = eq(UInt<5>(0h1b), remapindex_21)
when _T_2813 :
connect remapVecData[21], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[21]
node _T_2814 = eq(UInt<5>(0h1c), remapindex_21)
when _T_2814 :
connect remapVecData[21], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[21]
node _T_2815 = eq(UInt<5>(0h1d), remapindex_21)
when _T_2815 :
connect remapVecData[21], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[21]
node _T_2816 = eq(UInt<5>(0h1e), remapindex_21)
when _T_2816 :
connect remapVecData[21], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[21]
node _T_2817 = eq(UInt<5>(0h1f), remapindex_21)
when _T_2817 :
connect remapVecData[21], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[21]
node _remapindex_T_110 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_111 = sub(_remapindex_T_110, UInt<5>(0h16))
node _remapindex_T_112 = asUInt(_remapindex_T_111)
node _remapindex_T_113 = sub(_remapindex_T_112, read_start_index)
node _remapindex_T_114 = asUInt(_remapindex_T_113)
node remapindex_22 = rem(_remapindex_T_114, UInt<6>(0h20))
node _T_2818 = eq(UInt<1>(0h0), remapindex_22)
when _T_2818 :
connect remapVecData[22], Queue64_UInt8.io.deq.bits
connect remapVecValids[22], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[22]
node _T_2819 = eq(UInt<1>(0h1), remapindex_22)
when _T_2819 :
connect remapVecData[22], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[22]
node _T_2820 = eq(UInt<2>(0h2), remapindex_22)
when _T_2820 :
connect remapVecData[22], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[22]
node _T_2821 = eq(UInt<2>(0h3), remapindex_22)
when _T_2821 :
connect remapVecData[22], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[22]
node _T_2822 = eq(UInt<3>(0h4), remapindex_22)
when _T_2822 :
connect remapVecData[22], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[22]
node _T_2823 = eq(UInt<3>(0h5), remapindex_22)
when _T_2823 :
connect remapVecData[22], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[22]
node _T_2824 = eq(UInt<3>(0h6), remapindex_22)
when _T_2824 :
connect remapVecData[22], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[22]
node _T_2825 = eq(UInt<3>(0h7), remapindex_22)
when _T_2825 :
connect remapVecData[22], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[22]
node _T_2826 = eq(UInt<4>(0h8), remapindex_22)
when _T_2826 :
connect remapVecData[22], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[22]
node _T_2827 = eq(UInt<4>(0h9), remapindex_22)
when _T_2827 :
connect remapVecData[22], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[22]
node _T_2828 = eq(UInt<4>(0ha), remapindex_22)
when _T_2828 :
connect remapVecData[22], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[22]
node _T_2829 = eq(UInt<4>(0hb), remapindex_22)
when _T_2829 :
connect remapVecData[22], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[22]
node _T_2830 = eq(UInt<4>(0hc), remapindex_22)
when _T_2830 :
connect remapVecData[22], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[22]
node _T_2831 = eq(UInt<4>(0hd), remapindex_22)
when _T_2831 :
connect remapVecData[22], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[22]
node _T_2832 = eq(UInt<4>(0he), remapindex_22)
when _T_2832 :
connect remapVecData[22], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[22]
node _T_2833 = eq(UInt<4>(0hf), remapindex_22)
when _T_2833 :
connect remapVecData[22], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[22]
node _T_2834 = eq(UInt<5>(0h10), remapindex_22)
when _T_2834 :
connect remapVecData[22], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[22]
node _T_2835 = eq(UInt<5>(0h11), remapindex_22)
when _T_2835 :
connect remapVecData[22], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[22]
node _T_2836 = eq(UInt<5>(0h12), remapindex_22)
when _T_2836 :
connect remapVecData[22], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[22]
node _T_2837 = eq(UInt<5>(0h13), remapindex_22)
when _T_2837 :
connect remapVecData[22], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[22]
node _T_2838 = eq(UInt<5>(0h14), remapindex_22)
when _T_2838 :
connect remapVecData[22], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[22]
node _T_2839 = eq(UInt<5>(0h15), remapindex_22)
when _T_2839 :
connect remapVecData[22], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[22]
node _T_2840 = eq(UInt<5>(0h16), remapindex_22)
when _T_2840 :
connect remapVecData[22], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[22]
node _T_2841 = eq(UInt<5>(0h17), remapindex_22)
when _T_2841 :
connect remapVecData[22], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[22]
node _T_2842 = eq(UInt<5>(0h18), remapindex_22)
when _T_2842 :
connect remapVecData[22], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[22]
node _T_2843 = eq(UInt<5>(0h19), remapindex_22)
when _T_2843 :
connect remapVecData[22], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[22]
node _T_2844 = eq(UInt<5>(0h1a), remapindex_22)
when _T_2844 :
connect remapVecData[22], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[22]
node _T_2845 = eq(UInt<5>(0h1b), remapindex_22)
when _T_2845 :
connect remapVecData[22], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[22]
node _T_2846 = eq(UInt<5>(0h1c), remapindex_22)
when _T_2846 :
connect remapVecData[22], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[22]
node _T_2847 = eq(UInt<5>(0h1d), remapindex_22)
when _T_2847 :
connect remapVecData[22], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[22]
node _T_2848 = eq(UInt<5>(0h1e), remapindex_22)
when _T_2848 :
connect remapVecData[22], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[22]
node _T_2849 = eq(UInt<5>(0h1f), remapindex_22)
when _T_2849 :
connect remapVecData[22], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[22]
node _remapindex_T_115 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_116 = sub(_remapindex_T_115, UInt<5>(0h17))
node _remapindex_T_117 = asUInt(_remapindex_T_116)
node _remapindex_T_118 = sub(_remapindex_T_117, read_start_index)
node _remapindex_T_119 = asUInt(_remapindex_T_118)
node remapindex_23 = rem(_remapindex_T_119, UInt<6>(0h20))
node _T_2850 = eq(UInt<1>(0h0), remapindex_23)
when _T_2850 :
connect remapVecData[23], Queue64_UInt8.io.deq.bits
connect remapVecValids[23], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[23]
node _T_2851 = eq(UInt<1>(0h1), remapindex_23)
when _T_2851 :
connect remapVecData[23], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[23]
node _T_2852 = eq(UInt<2>(0h2), remapindex_23)
when _T_2852 :
connect remapVecData[23], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[23]
node _T_2853 = eq(UInt<2>(0h3), remapindex_23)
when _T_2853 :
connect remapVecData[23], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[23]
node _T_2854 = eq(UInt<3>(0h4), remapindex_23)
when _T_2854 :
connect remapVecData[23], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[23]
node _T_2855 = eq(UInt<3>(0h5), remapindex_23)
when _T_2855 :
connect remapVecData[23], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[23]
node _T_2856 = eq(UInt<3>(0h6), remapindex_23)
when _T_2856 :
connect remapVecData[23], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[23]
node _T_2857 = eq(UInt<3>(0h7), remapindex_23)
when _T_2857 :
connect remapVecData[23], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[23]
node _T_2858 = eq(UInt<4>(0h8), remapindex_23)
when _T_2858 :
connect remapVecData[23], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[23]
node _T_2859 = eq(UInt<4>(0h9), remapindex_23)
when _T_2859 :
connect remapVecData[23], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[23]
node _T_2860 = eq(UInt<4>(0ha), remapindex_23)
when _T_2860 :
connect remapVecData[23], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[23]
node _T_2861 = eq(UInt<4>(0hb), remapindex_23)
when _T_2861 :
connect remapVecData[23], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[23]
node _T_2862 = eq(UInt<4>(0hc), remapindex_23)
when _T_2862 :
connect remapVecData[23], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[23]
node _T_2863 = eq(UInt<4>(0hd), remapindex_23)
when _T_2863 :
connect remapVecData[23], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[23]
node _T_2864 = eq(UInt<4>(0he), remapindex_23)
when _T_2864 :
connect remapVecData[23], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[23]
node _T_2865 = eq(UInt<4>(0hf), remapindex_23)
when _T_2865 :
connect remapVecData[23], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[23]
node _T_2866 = eq(UInt<5>(0h10), remapindex_23)
when _T_2866 :
connect remapVecData[23], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[23]
node _T_2867 = eq(UInt<5>(0h11), remapindex_23)
when _T_2867 :
connect remapVecData[23], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[23]
node _T_2868 = eq(UInt<5>(0h12), remapindex_23)
when _T_2868 :
connect remapVecData[23], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[23]
node _T_2869 = eq(UInt<5>(0h13), remapindex_23)
when _T_2869 :
connect remapVecData[23], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[23]
node _T_2870 = eq(UInt<5>(0h14), remapindex_23)
when _T_2870 :
connect remapVecData[23], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[23]
node _T_2871 = eq(UInt<5>(0h15), remapindex_23)
when _T_2871 :
connect remapVecData[23], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[23]
node _T_2872 = eq(UInt<5>(0h16), remapindex_23)
when _T_2872 :
connect remapVecData[23], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[23]
node _T_2873 = eq(UInt<5>(0h17), remapindex_23)
when _T_2873 :
connect remapVecData[23], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[23]
node _T_2874 = eq(UInt<5>(0h18), remapindex_23)
when _T_2874 :
connect remapVecData[23], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[23]
node _T_2875 = eq(UInt<5>(0h19), remapindex_23)
when _T_2875 :
connect remapVecData[23], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[23]
node _T_2876 = eq(UInt<5>(0h1a), remapindex_23)
when _T_2876 :
connect remapVecData[23], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[23]
node _T_2877 = eq(UInt<5>(0h1b), remapindex_23)
when _T_2877 :
connect remapVecData[23], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[23]
node _T_2878 = eq(UInt<5>(0h1c), remapindex_23)
when _T_2878 :
connect remapVecData[23], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[23]
node _T_2879 = eq(UInt<5>(0h1d), remapindex_23)
when _T_2879 :
connect remapVecData[23], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[23]
node _T_2880 = eq(UInt<5>(0h1e), remapindex_23)
when _T_2880 :
connect remapVecData[23], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[23]
node _T_2881 = eq(UInt<5>(0h1f), remapindex_23)
when _T_2881 :
connect remapVecData[23], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[23]
node _remapindex_T_120 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_121 = sub(_remapindex_T_120, UInt<5>(0h18))
node _remapindex_T_122 = asUInt(_remapindex_T_121)
node _remapindex_T_123 = sub(_remapindex_T_122, read_start_index)
node _remapindex_T_124 = asUInt(_remapindex_T_123)
node remapindex_24 = rem(_remapindex_T_124, UInt<6>(0h20))
node _T_2882 = eq(UInt<1>(0h0), remapindex_24)
when _T_2882 :
connect remapVecData[24], Queue64_UInt8.io.deq.bits
connect remapVecValids[24], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[24]
node _T_2883 = eq(UInt<1>(0h1), remapindex_24)
when _T_2883 :
connect remapVecData[24], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[24]
node _T_2884 = eq(UInt<2>(0h2), remapindex_24)
when _T_2884 :
connect remapVecData[24], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[24]
node _T_2885 = eq(UInt<2>(0h3), remapindex_24)
when _T_2885 :
connect remapVecData[24], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[24]
node _T_2886 = eq(UInt<3>(0h4), remapindex_24)
when _T_2886 :
connect remapVecData[24], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[24]
node _T_2887 = eq(UInt<3>(0h5), remapindex_24)
when _T_2887 :
connect remapVecData[24], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[24]
node _T_2888 = eq(UInt<3>(0h6), remapindex_24)
when _T_2888 :
connect remapVecData[24], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[24]
node _T_2889 = eq(UInt<3>(0h7), remapindex_24)
when _T_2889 :
connect remapVecData[24], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[24]
node _T_2890 = eq(UInt<4>(0h8), remapindex_24)
when _T_2890 :
connect remapVecData[24], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[24]
node _T_2891 = eq(UInt<4>(0h9), remapindex_24)
when _T_2891 :
connect remapVecData[24], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[24]
node _T_2892 = eq(UInt<4>(0ha), remapindex_24)
when _T_2892 :
connect remapVecData[24], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[24]
node _T_2893 = eq(UInt<4>(0hb), remapindex_24)
when _T_2893 :
connect remapVecData[24], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[24]
node _T_2894 = eq(UInt<4>(0hc), remapindex_24)
when _T_2894 :
connect remapVecData[24], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[24]
node _T_2895 = eq(UInt<4>(0hd), remapindex_24)
when _T_2895 :
connect remapVecData[24], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[24]
node _T_2896 = eq(UInt<4>(0he), remapindex_24)
when _T_2896 :
connect remapVecData[24], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[24]
node _T_2897 = eq(UInt<4>(0hf), remapindex_24)
when _T_2897 :
connect remapVecData[24], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[24]
node _T_2898 = eq(UInt<5>(0h10), remapindex_24)
when _T_2898 :
connect remapVecData[24], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[24]
node _T_2899 = eq(UInt<5>(0h11), remapindex_24)
when _T_2899 :
connect remapVecData[24], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[24]
node _T_2900 = eq(UInt<5>(0h12), remapindex_24)
when _T_2900 :
connect remapVecData[24], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[24]
node _T_2901 = eq(UInt<5>(0h13), remapindex_24)
when _T_2901 :
connect remapVecData[24], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[24]
node _T_2902 = eq(UInt<5>(0h14), remapindex_24)
when _T_2902 :
connect remapVecData[24], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[24]
node _T_2903 = eq(UInt<5>(0h15), remapindex_24)
when _T_2903 :
connect remapVecData[24], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[24]
node _T_2904 = eq(UInt<5>(0h16), remapindex_24)
when _T_2904 :
connect remapVecData[24], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[24]
node _T_2905 = eq(UInt<5>(0h17), remapindex_24)
when _T_2905 :
connect remapVecData[24], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[24]
node _T_2906 = eq(UInt<5>(0h18), remapindex_24)
when _T_2906 :
connect remapVecData[24], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[24]
node _T_2907 = eq(UInt<5>(0h19), remapindex_24)
when _T_2907 :
connect remapVecData[24], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[24]
node _T_2908 = eq(UInt<5>(0h1a), remapindex_24)
when _T_2908 :
connect remapVecData[24], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[24]
node _T_2909 = eq(UInt<5>(0h1b), remapindex_24)
when _T_2909 :
connect remapVecData[24], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[24]
node _T_2910 = eq(UInt<5>(0h1c), remapindex_24)
when _T_2910 :
connect remapVecData[24], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[24]
node _T_2911 = eq(UInt<5>(0h1d), remapindex_24)
when _T_2911 :
connect remapVecData[24], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[24]
node _T_2912 = eq(UInt<5>(0h1e), remapindex_24)
when _T_2912 :
connect remapVecData[24], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[24]
node _T_2913 = eq(UInt<5>(0h1f), remapindex_24)
when _T_2913 :
connect remapVecData[24], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[24]
node _remapindex_T_125 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_126 = sub(_remapindex_T_125, UInt<5>(0h19))
node _remapindex_T_127 = asUInt(_remapindex_T_126)
node _remapindex_T_128 = sub(_remapindex_T_127, read_start_index)
node _remapindex_T_129 = asUInt(_remapindex_T_128)
node remapindex_25 = rem(_remapindex_T_129, UInt<6>(0h20))
node _T_2914 = eq(UInt<1>(0h0), remapindex_25)
when _T_2914 :
connect remapVecData[25], Queue64_UInt8.io.deq.bits
connect remapVecValids[25], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[25]
node _T_2915 = eq(UInt<1>(0h1), remapindex_25)
when _T_2915 :
connect remapVecData[25], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[25]
node _T_2916 = eq(UInt<2>(0h2), remapindex_25)
when _T_2916 :
connect remapVecData[25], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[25]
node _T_2917 = eq(UInt<2>(0h3), remapindex_25)
when _T_2917 :
connect remapVecData[25], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[25]
node _T_2918 = eq(UInt<3>(0h4), remapindex_25)
when _T_2918 :
connect remapVecData[25], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[25]
node _T_2919 = eq(UInt<3>(0h5), remapindex_25)
when _T_2919 :
connect remapVecData[25], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[25]
node _T_2920 = eq(UInt<3>(0h6), remapindex_25)
when _T_2920 :
connect remapVecData[25], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[25]
node _T_2921 = eq(UInt<3>(0h7), remapindex_25)
when _T_2921 :
connect remapVecData[25], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[25]
node _T_2922 = eq(UInt<4>(0h8), remapindex_25)
when _T_2922 :
connect remapVecData[25], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[25]
node _T_2923 = eq(UInt<4>(0h9), remapindex_25)
when _T_2923 :
connect remapVecData[25], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[25]
node _T_2924 = eq(UInt<4>(0ha), remapindex_25)
when _T_2924 :
connect remapVecData[25], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[25]
node _T_2925 = eq(UInt<4>(0hb), remapindex_25)
when _T_2925 :
connect remapVecData[25], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[25]
node _T_2926 = eq(UInt<4>(0hc), remapindex_25)
when _T_2926 :
connect remapVecData[25], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[25]
node _T_2927 = eq(UInt<4>(0hd), remapindex_25)
when _T_2927 :
connect remapVecData[25], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[25]
node _T_2928 = eq(UInt<4>(0he), remapindex_25)
when _T_2928 :
connect remapVecData[25], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[25]
node _T_2929 = eq(UInt<4>(0hf), remapindex_25)
when _T_2929 :
connect remapVecData[25], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[25]
node _T_2930 = eq(UInt<5>(0h10), remapindex_25)
when _T_2930 :
connect remapVecData[25], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[25]
node _T_2931 = eq(UInt<5>(0h11), remapindex_25)
when _T_2931 :
connect remapVecData[25], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[25]
node _T_2932 = eq(UInt<5>(0h12), remapindex_25)
when _T_2932 :
connect remapVecData[25], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[25]
node _T_2933 = eq(UInt<5>(0h13), remapindex_25)
when _T_2933 :
connect remapVecData[25], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[25]
node _T_2934 = eq(UInt<5>(0h14), remapindex_25)
when _T_2934 :
connect remapVecData[25], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[25]
node _T_2935 = eq(UInt<5>(0h15), remapindex_25)
when _T_2935 :
connect remapVecData[25], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[25]
node _T_2936 = eq(UInt<5>(0h16), remapindex_25)
when _T_2936 :
connect remapVecData[25], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[25]
node _T_2937 = eq(UInt<5>(0h17), remapindex_25)
when _T_2937 :
connect remapVecData[25], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[25]
node _T_2938 = eq(UInt<5>(0h18), remapindex_25)
when _T_2938 :
connect remapVecData[25], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[25]
node _T_2939 = eq(UInt<5>(0h19), remapindex_25)
when _T_2939 :
connect remapVecData[25], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[25]
node _T_2940 = eq(UInt<5>(0h1a), remapindex_25)
when _T_2940 :
connect remapVecData[25], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[25]
node _T_2941 = eq(UInt<5>(0h1b), remapindex_25)
when _T_2941 :
connect remapVecData[25], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[25]
node _T_2942 = eq(UInt<5>(0h1c), remapindex_25)
when _T_2942 :
connect remapVecData[25], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[25]
node _T_2943 = eq(UInt<5>(0h1d), remapindex_25)
when _T_2943 :
connect remapVecData[25], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[25]
node _T_2944 = eq(UInt<5>(0h1e), remapindex_25)
when _T_2944 :
connect remapVecData[25], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[25]
node _T_2945 = eq(UInt<5>(0h1f), remapindex_25)
when _T_2945 :
connect remapVecData[25], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[25]
node _remapindex_T_130 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_131 = sub(_remapindex_T_130, UInt<5>(0h1a))
node _remapindex_T_132 = asUInt(_remapindex_T_131)
node _remapindex_T_133 = sub(_remapindex_T_132, read_start_index)
node _remapindex_T_134 = asUInt(_remapindex_T_133)
node remapindex_26 = rem(_remapindex_T_134, UInt<6>(0h20))
node _T_2946 = eq(UInt<1>(0h0), remapindex_26)
when _T_2946 :
connect remapVecData[26], Queue64_UInt8.io.deq.bits
connect remapVecValids[26], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[26]
node _T_2947 = eq(UInt<1>(0h1), remapindex_26)
when _T_2947 :
connect remapVecData[26], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[26]
node _T_2948 = eq(UInt<2>(0h2), remapindex_26)
when _T_2948 :
connect remapVecData[26], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[26]
node _T_2949 = eq(UInt<2>(0h3), remapindex_26)
when _T_2949 :
connect remapVecData[26], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[26]
node _T_2950 = eq(UInt<3>(0h4), remapindex_26)
when _T_2950 :
connect remapVecData[26], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[26]
node _T_2951 = eq(UInt<3>(0h5), remapindex_26)
when _T_2951 :
connect remapVecData[26], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[26]
node _T_2952 = eq(UInt<3>(0h6), remapindex_26)
when _T_2952 :
connect remapVecData[26], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[26]
node _T_2953 = eq(UInt<3>(0h7), remapindex_26)
when _T_2953 :
connect remapVecData[26], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[26]
node _T_2954 = eq(UInt<4>(0h8), remapindex_26)
when _T_2954 :
connect remapVecData[26], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[26]
node _T_2955 = eq(UInt<4>(0h9), remapindex_26)
when _T_2955 :
connect remapVecData[26], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[26]
node _T_2956 = eq(UInt<4>(0ha), remapindex_26)
when _T_2956 :
connect remapVecData[26], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[26]
node _T_2957 = eq(UInt<4>(0hb), remapindex_26)
when _T_2957 :
connect remapVecData[26], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[26]
node _T_2958 = eq(UInt<4>(0hc), remapindex_26)
when _T_2958 :
connect remapVecData[26], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[26]
node _T_2959 = eq(UInt<4>(0hd), remapindex_26)
when _T_2959 :
connect remapVecData[26], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[26]
node _T_2960 = eq(UInt<4>(0he), remapindex_26)
when _T_2960 :
connect remapVecData[26], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[26]
node _T_2961 = eq(UInt<4>(0hf), remapindex_26)
when _T_2961 :
connect remapVecData[26], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[26]
node _T_2962 = eq(UInt<5>(0h10), remapindex_26)
when _T_2962 :
connect remapVecData[26], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[26]
node _T_2963 = eq(UInt<5>(0h11), remapindex_26)
when _T_2963 :
connect remapVecData[26], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[26]
node _T_2964 = eq(UInt<5>(0h12), remapindex_26)
when _T_2964 :
connect remapVecData[26], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[26]
node _T_2965 = eq(UInt<5>(0h13), remapindex_26)
when _T_2965 :
connect remapVecData[26], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[26]
node _T_2966 = eq(UInt<5>(0h14), remapindex_26)
when _T_2966 :
connect remapVecData[26], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[26]
node _T_2967 = eq(UInt<5>(0h15), remapindex_26)
when _T_2967 :
connect remapVecData[26], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[26]
node _T_2968 = eq(UInt<5>(0h16), remapindex_26)
when _T_2968 :
connect remapVecData[26], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[26]
node _T_2969 = eq(UInt<5>(0h17), remapindex_26)
when _T_2969 :
connect remapVecData[26], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[26]
node _T_2970 = eq(UInt<5>(0h18), remapindex_26)
when _T_2970 :
connect remapVecData[26], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[26]
node _T_2971 = eq(UInt<5>(0h19), remapindex_26)
when _T_2971 :
connect remapVecData[26], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[26]
node _T_2972 = eq(UInt<5>(0h1a), remapindex_26)
when _T_2972 :
connect remapVecData[26], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[26]
node _T_2973 = eq(UInt<5>(0h1b), remapindex_26)
when _T_2973 :
connect remapVecData[26], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[26]
node _T_2974 = eq(UInt<5>(0h1c), remapindex_26)
when _T_2974 :
connect remapVecData[26], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[26]
node _T_2975 = eq(UInt<5>(0h1d), remapindex_26)
when _T_2975 :
connect remapVecData[26], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[26]
node _T_2976 = eq(UInt<5>(0h1e), remapindex_26)
when _T_2976 :
connect remapVecData[26], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[26]
node _T_2977 = eq(UInt<5>(0h1f), remapindex_26)
when _T_2977 :
connect remapVecData[26], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[26]
node _remapindex_T_135 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_136 = sub(_remapindex_T_135, UInt<5>(0h1b))
node _remapindex_T_137 = asUInt(_remapindex_T_136)
node _remapindex_T_138 = sub(_remapindex_T_137, read_start_index)
node _remapindex_T_139 = asUInt(_remapindex_T_138)
node remapindex_27 = rem(_remapindex_T_139, UInt<6>(0h20))
node _T_2978 = eq(UInt<1>(0h0), remapindex_27)
when _T_2978 :
connect remapVecData[27], Queue64_UInt8.io.deq.bits
connect remapVecValids[27], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[27]
node _T_2979 = eq(UInt<1>(0h1), remapindex_27)
when _T_2979 :
connect remapVecData[27], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[27]
node _T_2980 = eq(UInt<2>(0h2), remapindex_27)
when _T_2980 :
connect remapVecData[27], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[27]
node _T_2981 = eq(UInt<2>(0h3), remapindex_27)
when _T_2981 :
connect remapVecData[27], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[27]
node _T_2982 = eq(UInt<3>(0h4), remapindex_27)
when _T_2982 :
connect remapVecData[27], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[27]
node _T_2983 = eq(UInt<3>(0h5), remapindex_27)
when _T_2983 :
connect remapVecData[27], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[27]
node _T_2984 = eq(UInt<3>(0h6), remapindex_27)
when _T_2984 :
connect remapVecData[27], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[27]
node _T_2985 = eq(UInt<3>(0h7), remapindex_27)
when _T_2985 :
connect remapVecData[27], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[27]
node _T_2986 = eq(UInt<4>(0h8), remapindex_27)
when _T_2986 :
connect remapVecData[27], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[27]
node _T_2987 = eq(UInt<4>(0h9), remapindex_27)
when _T_2987 :
connect remapVecData[27], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[27]
node _T_2988 = eq(UInt<4>(0ha), remapindex_27)
when _T_2988 :
connect remapVecData[27], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[27]
node _T_2989 = eq(UInt<4>(0hb), remapindex_27)
when _T_2989 :
connect remapVecData[27], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[27]
node _T_2990 = eq(UInt<4>(0hc), remapindex_27)
when _T_2990 :
connect remapVecData[27], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[27]
node _T_2991 = eq(UInt<4>(0hd), remapindex_27)
when _T_2991 :
connect remapVecData[27], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[27]
node _T_2992 = eq(UInt<4>(0he), remapindex_27)
when _T_2992 :
connect remapVecData[27], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[27]
node _T_2993 = eq(UInt<4>(0hf), remapindex_27)
when _T_2993 :
connect remapVecData[27], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[27]
node _T_2994 = eq(UInt<5>(0h10), remapindex_27)
when _T_2994 :
connect remapVecData[27], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[27]
node _T_2995 = eq(UInt<5>(0h11), remapindex_27)
when _T_2995 :
connect remapVecData[27], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[27]
node _T_2996 = eq(UInt<5>(0h12), remapindex_27)
when _T_2996 :
connect remapVecData[27], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[27]
node _T_2997 = eq(UInt<5>(0h13), remapindex_27)
when _T_2997 :
connect remapVecData[27], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[27]
node _T_2998 = eq(UInt<5>(0h14), remapindex_27)
when _T_2998 :
connect remapVecData[27], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[27]
node _T_2999 = eq(UInt<5>(0h15), remapindex_27)
when _T_2999 :
connect remapVecData[27], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[27]
node _T_3000 = eq(UInt<5>(0h16), remapindex_27)
when _T_3000 :
connect remapVecData[27], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[27]
node _T_3001 = eq(UInt<5>(0h17), remapindex_27)
when _T_3001 :
connect remapVecData[27], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[27]
node _T_3002 = eq(UInt<5>(0h18), remapindex_27)
when _T_3002 :
connect remapVecData[27], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[27]
node _T_3003 = eq(UInt<5>(0h19), remapindex_27)
when _T_3003 :
connect remapVecData[27], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[27]
node _T_3004 = eq(UInt<5>(0h1a), remapindex_27)
when _T_3004 :
connect remapVecData[27], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[27]
node _T_3005 = eq(UInt<5>(0h1b), remapindex_27)
when _T_3005 :
connect remapVecData[27], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[27]
node _T_3006 = eq(UInt<5>(0h1c), remapindex_27)
when _T_3006 :
connect remapVecData[27], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[27]
node _T_3007 = eq(UInt<5>(0h1d), remapindex_27)
when _T_3007 :
connect remapVecData[27], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[27]
node _T_3008 = eq(UInt<5>(0h1e), remapindex_27)
when _T_3008 :
connect remapVecData[27], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[27]
node _T_3009 = eq(UInt<5>(0h1f), remapindex_27)
when _T_3009 :
connect remapVecData[27], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[27]
node _remapindex_T_140 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_141 = sub(_remapindex_T_140, UInt<5>(0h1c))
node _remapindex_T_142 = asUInt(_remapindex_T_141)
node _remapindex_T_143 = sub(_remapindex_T_142, read_start_index)
node _remapindex_T_144 = asUInt(_remapindex_T_143)
node remapindex_28 = rem(_remapindex_T_144, UInt<6>(0h20))
node _T_3010 = eq(UInt<1>(0h0), remapindex_28)
when _T_3010 :
connect remapVecData[28], Queue64_UInt8.io.deq.bits
connect remapVecValids[28], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[28]
node _T_3011 = eq(UInt<1>(0h1), remapindex_28)
when _T_3011 :
connect remapVecData[28], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[28]
node _T_3012 = eq(UInt<2>(0h2), remapindex_28)
when _T_3012 :
connect remapVecData[28], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[28]
node _T_3013 = eq(UInt<2>(0h3), remapindex_28)
when _T_3013 :
connect remapVecData[28], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[28]
node _T_3014 = eq(UInt<3>(0h4), remapindex_28)
when _T_3014 :
connect remapVecData[28], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[28]
node _T_3015 = eq(UInt<3>(0h5), remapindex_28)
when _T_3015 :
connect remapVecData[28], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[28]
node _T_3016 = eq(UInt<3>(0h6), remapindex_28)
when _T_3016 :
connect remapVecData[28], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[28]
node _T_3017 = eq(UInt<3>(0h7), remapindex_28)
when _T_3017 :
connect remapVecData[28], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[28]
node _T_3018 = eq(UInt<4>(0h8), remapindex_28)
when _T_3018 :
connect remapVecData[28], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[28]
node _T_3019 = eq(UInt<4>(0h9), remapindex_28)
when _T_3019 :
connect remapVecData[28], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[28]
node _T_3020 = eq(UInt<4>(0ha), remapindex_28)
when _T_3020 :
connect remapVecData[28], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[28]
node _T_3021 = eq(UInt<4>(0hb), remapindex_28)
when _T_3021 :
connect remapVecData[28], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[28]
node _T_3022 = eq(UInt<4>(0hc), remapindex_28)
when _T_3022 :
connect remapVecData[28], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[28]
node _T_3023 = eq(UInt<4>(0hd), remapindex_28)
when _T_3023 :
connect remapVecData[28], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[28]
node _T_3024 = eq(UInt<4>(0he), remapindex_28)
when _T_3024 :
connect remapVecData[28], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[28]
node _T_3025 = eq(UInt<4>(0hf), remapindex_28)
when _T_3025 :
connect remapVecData[28], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[28]
node _T_3026 = eq(UInt<5>(0h10), remapindex_28)
when _T_3026 :
connect remapVecData[28], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[28]
node _T_3027 = eq(UInt<5>(0h11), remapindex_28)
when _T_3027 :
connect remapVecData[28], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[28]
node _T_3028 = eq(UInt<5>(0h12), remapindex_28)
when _T_3028 :
connect remapVecData[28], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[28]
node _T_3029 = eq(UInt<5>(0h13), remapindex_28)
when _T_3029 :
connect remapVecData[28], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[28]
node _T_3030 = eq(UInt<5>(0h14), remapindex_28)
when _T_3030 :
connect remapVecData[28], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[28]
node _T_3031 = eq(UInt<5>(0h15), remapindex_28)
when _T_3031 :
connect remapVecData[28], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[28]
node _T_3032 = eq(UInt<5>(0h16), remapindex_28)
when _T_3032 :
connect remapVecData[28], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[28]
node _T_3033 = eq(UInt<5>(0h17), remapindex_28)
when _T_3033 :
connect remapVecData[28], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[28]
node _T_3034 = eq(UInt<5>(0h18), remapindex_28)
when _T_3034 :
connect remapVecData[28], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[28]
node _T_3035 = eq(UInt<5>(0h19), remapindex_28)
when _T_3035 :
connect remapVecData[28], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[28]
node _T_3036 = eq(UInt<5>(0h1a), remapindex_28)
when _T_3036 :
connect remapVecData[28], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[28]
node _T_3037 = eq(UInt<5>(0h1b), remapindex_28)
when _T_3037 :
connect remapVecData[28], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[28]
node _T_3038 = eq(UInt<5>(0h1c), remapindex_28)
when _T_3038 :
connect remapVecData[28], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[28]
node _T_3039 = eq(UInt<5>(0h1d), remapindex_28)
when _T_3039 :
connect remapVecData[28], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[28]
node _T_3040 = eq(UInt<5>(0h1e), remapindex_28)
when _T_3040 :
connect remapVecData[28], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[28]
node _T_3041 = eq(UInt<5>(0h1f), remapindex_28)
when _T_3041 :
connect remapVecData[28], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[28]
node _remapindex_T_145 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_146 = sub(_remapindex_T_145, UInt<5>(0h1d))
node _remapindex_T_147 = asUInt(_remapindex_T_146)
node _remapindex_T_148 = sub(_remapindex_T_147, read_start_index)
node _remapindex_T_149 = asUInt(_remapindex_T_148)
node remapindex_29 = rem(_remapindex_T_149, UInt<6>(0h20))
node _T_3042 = eq(UInt<1>(0h0), remapindex_29)
when _T_3042 :
connect remapVecData[29], Queue64_UInt8.io.deq.bits
connect remapVecValids[29], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[29]
node _T_3043 = eq(UInt<1>(0h1), remapindex_29)
when _T_3043 :
connect remapVecData[29], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[29]
node _T_3044 = eq(UInt<2>(0h2), remapindex_29)
when _T_3044 :
connect remapVecData[29], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[29]
node _T_3045 = eq(UInt<2>(0h3), remapindex_29)
when _T_3045 :
connect remapVecData[29], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[29]
node _T_3046 = eq(UInt<3>(0h4), remapindex_29)
when _T_3046 :
connect remapVecData[29], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[29]
node _T_3047 = eq(UInt<3>(0h5), remapindex_29)
when _T_3047 :
connect remapVecData[29], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[29]
node _T_3048 = eq(UInt<3>(0h6), remapindex_29)
when _T_3048 :
connect remapVecData[29], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[29]
node _T_3049 = eq(UInt<3>(0h7), remapindex_29)
when _T_3049 :
connect remapVecData[29], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[29]
node _T_3050 = eq(UInt<4>(0h8), remapindex_29)
when _T_3050 :
connect remapVecData[29], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[29]
node _T_3051 = eq(UInt<4>(0h9), remapindex_29)
when _T_3051 :
connect remapVecData[29], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[29]
node _T_3052 = eq(UInt<4>(0ha), remapindex_29)
when _T_3052 :
connect remapVecData[29], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[29]
node _T_3053 = eq(UInt<4>(0hb), remapindex_29)
when _T_3053 :
connect remapVecData[29], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[29]
node _T_3054 = eq(UInt<4>(0hc), remapindex_29)
when _T_3054 :
connect remapVecData[29], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[29]
node _T_3055 = eq(UInt<4>(0hd), remapindex_29)
when _T_3055 :
connect remapVecData[29], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[29]
node _T_3056 = eq(UInt<4>(0he), remapindex_29)
when _T_3056 :
connect remapVecData[29], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[29]
node _T_3057 = eq(UInt<4>(0hf), remapindex_29)
when _T_3057 :
connect remapVecData[29], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[29]
node _T_3058 = eq(UInt<5>(0h10), remapindex_29)
when _T_3058 :
connect remapVecData[29], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[29]
node _T_3059 = eq(UInt<5>(0h11), remapindex_29)
when _T_3059 :
connect remapVecData[29], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[29]
node _T_3060 = eq(UInt<5>(0h12), remapindex_29)
when _T_3060 :
connect remapVecData[29], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[29]
node _T_3061 = eq(UInt<5>(0h13), remapindex_29)
when _T_3061 :
connect remapVecData[29], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[29]
node _T_3062 = eq(UInt<5>(0h14), remapindex_29)
when _T_3062 :
connect remapVecData[29], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[29]
node _T_3063 = eq(UInt<5>(0h15), remapindex_29)
when _T_3063 :
connect remapVecData[29], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[29]
node _T_3064 = eq(UInt<5>(0h16), remapindex_29)
when _T_3064 :
connect remapVecData[29], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[29]
node _T_3065 = eq(UInt<5>(0h17), remapindex_29)
when _T_3065 :
connect remapVecData[29], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[29]
node _T_3066 = eq(UInt<5>(0h18), remapindex_29)
when _T_3066 :
connect remapVecData[29], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[29]
node _T_3067 = eq(UInt<5>(0h19), remapindex_29)
when _T_3067 :
connect remapVecData[29], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[29]
node _T_3068 = eq(UInt<5>(0h1a), remapindex_29)
when _T_3068 :
connect remapVecData[29], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[29]
node _T_3069 = eq(UInt<5>(0h1b), remapindex_29)
when _T_3069 :
connect remapVecData[29], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[29]
node _T_3070 = eq(UInt<5>(0h1c), remapindex_29)
when _T_3070 :
connect remapVecData[29], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[29]
node _T_3071 = eq(UInt<5>(0h1d), remapindex_29)
when _T_3071 :
connect remapVecData[29], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[29]
node _T_3072 = eq(UInt<5>(0h1e), remapindex_29)
when _T_3072 :
connect remapVecData[29], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[29]
node _T_3073 = eq(UInt<5>(0h1f), remapindex_29)
when _T_3073 :
connect remapVecData[29], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[29]
node _remapindex_T_150 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_151 = sub(_remapindex_T_150, UInt<5>(0h1e))
node _remapindex_T_152 = asUInt(_remapindex_T_151)
node _remapindex_T_153 = sub(_remapindex_T_152, read_start_index)
node _remapindex_T_154 = asUInt(_remapindex_T_153)
node remapindex_30 = rem(_remapindex_T_154, UInt<6>(0h20))
node _T_3074 = eq(UInt<1>(0h0), remapindex_30)
when _T_3074 :
connect remapVecData[30], Queue64_UInt8.io.deq.bits
connect remapVecValids[30], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[30]
node _T_3075 = eq(UInt<1>(0h1), remapindex_30)
when _T_3075 :
connect remapVecData[30], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[30]
node _T_3076 = eq(UInt<2>(0h2), remapindex_30)
when _T_3076 :
connect remapVecData[30], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[30]
node _T_3077 = eq(UInt<2>(0h3), remapindex_30)
when _T_3077 :
connect remapVecData[30], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[30]
node _T_3078 = eq(UInt<3>(0h4), remapindex_30)
when _T_3078 :
connect remapVecData[30], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[30]
node _T_3079 = eq(UInt<3>(0h5), remapindex_30)
when _T_3079 :
connect remapVecData[30], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[30]
node _T_3080 = eq(UInt<3>(0h6), remapindex_30)
when _T_3080 :
connect remapVecData[30], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[30]
node _T_3081 = eq(UInt<3>(0h7), remapindex_30)
when _T_3081 :
connect remapVecData[30], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[30]
node _T_3082 = eq(UInt<4>(0h8), remapindex_30)
when _T_3082 :
connect remapVecData[30], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[30]
node _T_3083 = eq(UInt<4>(0h9), remapindex_30)
when _T_3083 :
connect remapVecData[30], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[30]
node _T_3084 = eq(UInt<4>(0ha), remapindex_30)
when _T_3084 :
connect remapVecData[30], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[30]
node _T_3085 = eq(UInt<4>(0hb), remapindex_30)
when _T_3085 :
connect remapVecData[30], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[30]
node _T_3086 = eq(UInt<4>(0hc), remapindex_30)
when _T_3086 :
connect remapVecData[30], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[30]
node _T_3087 = eq(UInt<4>(0hd), remapindex_30)
when _T_3087 :
connect remapVecData[30], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[30]
node _T_3088 = eq(UInt<4>(0he), remapindex_30)
when _T_3088 :
connect remapVecData[30], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[30]
node _T_3089 = eq(UInt<4>(0hf), remapindex_30)
when _T_3089 :
connect remapVecData[30], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[30]
node _T_3090 = eq(UInt<5>(0h10), remapindex_30)
when _T_3090 :
connect remapVecData[30], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[30]
node _T_3091 = eq(UInt<5>(0h11), remapindex_30)
when _T_3091 :
connect remapVecData[30], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[30]
node _T_3092 = eq(UInt<5>(0h12), remapindex_30)
when _T_3092 :
connect remapVecData[30], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[30]
node _T_3093 = eq(UInt<5>(0h13), remapindex_30)
when _T_3093 :
connect remapVecData[30], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[30]
node _T_3094 = eq(UInt<5>(0h14), remapindex_30)
when _T_3094 :
connect remapVecData[30], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[30]
node _T_3095 = eq(UInt<5>(0h15), remapindex_30)
when _T_3095 :
connect remapVecData[30], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[30]
node _T_3096 = eq(UInt<5>(0h16), remapindex_30)
when _T_3096 :
connect remapVecData[30], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[30]
node _T_3097 = eq(UInt<5>(0h17), remapindex_30)
when _T_3097 :
connect remapVecData[30], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[30]
node _T_3098 = eq(UInt<5>(0h18), remapindex_30)
when _T_3098 :
connect remapVecData[30], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[30]
node _T_3099 = eq(UInt<5>(0h19), remapindex_30)
when _T_3099 :
connect remapVecData[30], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[30]
node _T_3100 = eq(UInt<5>(0h1a), remapindex_30)
when _T_3100 :
connect remapVecData[30], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[30]
node _T_3101 = eq(UInt<5>(0h1b), remapindex_30)
when _T_3101 :
connect remapVecData[30], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[30]
node _T_3102 = eq(UInt<5>(0h1c), remapindex_30)
when _T_3102 :
connect remapVecData[30], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[30]
node _T_3103 = eq(UInt<5>(0h1d), remapindex_30)
when _T_3103 :
connect remapVecData[30], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[30]
node _T_3104 = eq(UInt<5>(0h1e), remapindex_30)
when _T_3104 :
connect remapVecData[30], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[30]
node _T_3105 = eq(UInt<5>(0h1f), remapindex_30)
when _T_3105 :
connect remapVecData[30], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[30]
node _remapindex_T_155 = add(UInt<6>(0h20), MAX_QUEUE_IDX)
node _remapindex_T_156 = sub(_remapindex_T_155, UInt<5>(0h1f))
node _remapindex_T_157 = asUInt(_remapindex_T_156)
node _remapindex_T_158 = sub(_remapindex_T_157, read_start_index)
node _remapindex_T_159 = asUInt(_remapindex_T_158)
node remapindex_31 = rem(_remapindex_T_159, UInt<6>(0h20))
node _T_3106 = eq(UInt<1>(0h0), remapindex_31)
when _T_3106 :
connect remapVecData[31], Queue64_UInt8.io.deq.bits
connect remapVecValids[31], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[31]
node _T_3107 = eq(UInt<1>(0h1), remapindex_31)
when _T_3107 :
connect remapVecData[31], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[31]
node _T_3108 = eq(UInt<2>(0h2), remapindex_31)
when _T_3108 :
connect remapVecData[31], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[31]
node _T_3109 = eq(UInt<2>(0h3), remapindex_31)
when _T_3109 :
connect remapVecData[31], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[31]
node _T_3110 = eq(UInt<3>(0h4), remapindex_31)
when _T_3110 :
connect remapVecData[31], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[31]
node _T_3111 = eq(UInt<3>(0h5), remapindex_31)
when _T_3111 :
connect remapVecData[31], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[31]
node _T_3112 = eq(UInt<3>(0h6), remapindex_31)
when _T_3112 :
connect remapVecData[31], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[31]
node _T_3113 = eq(UInt<3>(0h7), remapindex_31)
when _T_3113 :
connect remapVecData[31], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[31]
node _T_3114 = eq(UInt<4>(0h8), remapindex_31)
when _T_3114 :
connect remapVecData[31], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[31]
node _T_3115 = eq(UInt<4>(0h9), remapindex_31)
when _T_3115 :
connect remapVecData[31], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[31]
node _T_3116 = eq(UInt<4>(0ha), remapindex_31)
when _T_3116 :
connect remapVecData[31], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[31]
node _T_3117 = eq(UInt<4>(0hb), remapindex_31)
when _T_3117 :
connect remapVecData[31], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[31]
node _T_3118 = eq(UInt<4>(0hc), remapindex_31)
when _T_3118 :
connect remapVecData[31], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[31]
node _T_3119 = eq(UInt<4>(0hd), remapindex_31)
when _T_3119 :
connect remapVecData[31], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[31]
node _T_3120 = eq(UInt<4>(0he), remapindex_31)
when _T_3120 :
connect remapVecData[31], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[31]
node _T_3121 = eq(UInt<4>(0hf), remapindex_31)
when _T_3121 :
connect remapVecData[31], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[31]
node _T_3122 = eq(UInt<5>(0h10), remapindex_31)
when _T_3122 :
connect remapVecData[31], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[31]
node _T_3123 = eq(UInt<5>(0h11), remapindex_31)
when _T_3123 :
connect remapVecData[31], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[31]
node _T_3124 = eq(UInt<5>(0h12), remapindex_31)
when _T_3124 :
connect remapVecData[31], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[31]
node _T_3125 = eq(UInt<5>(0h13), remapindex_31)
when _T_3125 :
connect remapVecData[31], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[31]
node _T_3126 = eq(UInt<5>(0h14), remapindex_31)
when _T_3126 :
connect remapVecData[31], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[31]
node _T_3127 = eq(UInt<5>(0h15), remapindex_31)
when _T_3127 :
connect remapVecData[31], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[31]
node _T_3128 = eq(UInt<5>(0h16), remapindex_31)
when _T_3128 :
connect remapVecData[31], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[31]
node _T_3129 = eq(UInt<5>(0h17), remapindex_31)
when _T_3129 :
connect remapVecData[31], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[31]
node _T_3130 = eq(UInt<5>(0h18), remapindex_31)
when _T_3130 :
connect remapVecData[31], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[31]
node _T_3131 = eq(UInt<5>(0h19), remapindex_31)
when _T_3131 :
connect remapVecData[31], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[31]
node _T_3132 = eq(UInt<5>(0h1a), remapindex_31)
when _T_3132 :
connect remapVecData[31], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[31]
node _T_3133 = eq(UInt<5>(0h1b), remapindex_31)
when _T_3133 :
connect remapVecData[31], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[31]
node _T_3134 = eq(UInt<5>(0h1c), remapindex_31)
when _T_3134 :
connect remapVecData[31], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[31]
node _T_3135 = eq(UInt<5>(0h1d), remapindex_31)
when _T_3135 :
connect remapVecData[31], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[31]
node _T_3136 = eq(UInt<5>(0h1e), remapindex_31)
when _T_3136 :
connect remapVecData[31], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[31]
node _T_3137 = eq(UInt<5>(0h1f), remapindex_31)
when _T_3137 :
connect remapVecData[31], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[31]
node io_consumer_output_data_lo_lo_lo_lo = cat(remapVecData[30], remapVecData[31])
node io_consumer_output_data_lo_lo_lo_hi = cat(remapVecData[28], remapVecData[29])
node io_consumer_output_data_lo_lo_lo = cat(io_consumer_output_data_lo_lo_lo_hi, io_consumer_output_data_lo_lo_lo_lo)
node io_consumer_output_data_lo_lo_hi_lo = cat(remapVecData[26], remapVecData[27])
node io_consumer_output_data_lo_lo_hi_hi = cat(remapVecData[24], remapVecData[25])
node io_consumer_output_data_lo_lo_hi = cat(io_consumer_output_data_lo_lo_hi_hi, io_consumer_output_data_lo_lo_hi_lo)
node io_consumer_output_data_lo_lo = cat(io_consumer_output_data_lo_lo_hi, io_consumer_output_data_lo_lo_lo)
node io_consumer_output_data_lo_hi_lo_lo = cat(remapVecData[22], remapVecData[23])
node io_consumer_output_data_lo_hi_lo_hi = cat(remapVecData[20], remapVecData[21])
node io_consumer_output_data_lo_hi_lo = cat(io_consumer_output_data_lo_hi_lo_hi, io_consumer_output_data_lo_hi_lo_lo)
node io_consumer_output_data_lo_hi_hi_lo = cat(remapVecData[18], remapVecData[19])
node io_consumer_output_data_lo_hi_hi_hi = cat(remapVecData[16], remapVecData[17])
node io_consumer_output_data_lo_hi_hi = cat(io_consumer_output_data_lo_hi_hi_hi, io_consumer_output_data_lo_hi_hi_lo)
node io_consumer_output_data_lo_hi = cat(io_consumer_output_data_lo_hi_hi, io_consumer_output_data_lo_hi_lo)
node io_consumer_output_data_lo = cat(io_consumer_output_data_lo_hi, io_consumer_output_data_lo_lo)
node io_consumer_output_data_hi_lo_lo_lo = cat(remapVecData[14], remapVecData[15])
node io_consumer_output_data_hi_lo_lo_hi = cat(remapVecData[12], remapVecData[13])
node io_consumer_output_data_hi_lo_lo = cat(io_consumer_output_data_hi_lo_lo_hi, io_consumer_output_data_hi_lo_lo_lo)
node io_consumer_output_data_hi_lo_hi_lo = cat(remapVecData[10], remapVecData[11])
node io_consumer_output_data_hi_lo_hi_hi = cat(remapVecData[8], remapVecData[9])
node io_consumer_output_data_hi_lo_hi = cat(io_consumer_output_data_hi_lo_hi_hi, io_consumer_output_data_hi_lo_hi_lo)
node io_consumer_output_data_hi_lo = cat(io_consumer_output_data_hi_lo_hi, io_consumer_output_data_hi_lo_lo)
node io_consumer_output_data_hi_hi_lo_lo = cat(remapVecData[6], remapVecData[7])
node io_consumer_output_data_hi_hi_lo_hi = cat(remapVecData[4], remapVecData[5])
node io_consumer_output_data_hi_hi_lo = cat(io_consumer_output_data_hi_hi_lo_hi, io_consumer_output_data_hi_hi_lo_lo)
node io_consumer_output_data_hi_hi_hi_lo = cat(remapVecData[2], remapVecData[3])
node io_consumer_output_data_hi_hi_hi_hi = cat(remapVecData[0], remapVecData[1])
node io_consumer_output_data_hi_hi_hi = cat(io_consumer_output_data_hi_hi_hi_hi, io_consumer_output_data_hi_hi_hi_lo)
node io_consumer_output_data_hi_hi = cat(io_consumer_output_data_hi_hi_hi, io_consumer_output_data_hi_hi_lo)
node io_consumer_output_data_hi = cat(io_consumer_output_data_hi_hi, io_consumer_output_data_hi_lo)
node _io_consumer_output_data_T = cat(io_consumer_output_data_hi, io_consumer_output_data_lo)
connect io.consumer.output_data, _io_consumer_output_data_T
node _buf_last_T = add(len_already_consumed, io.consumer.user_consumed_bytes)
node _buf_last_T_1 = tail(_buf_last_T, 1)
node buf_last = eq(_buf_last_T_1, buf_info_queue.io.deq.bits.len_bytes)
node _count_valids_T = add(remapVecValids[0], remapVecValids[1])
node _count_valids_T_1 = add(_count_valids_T, remapVecValids[2])
node _count_valids_T_2 = add(_count_valids_T_1, remapVecValids[3])
node _count_valids_T_3 = add(_count_valids_T_2, remapVecValids[4])
node _count_valids_T_4 = add(_count_valids_T_3, remapVecValids[5])
node _count_valids_T_5 = add(_count_valids_T_4, remapVecValids[6])
node _count_valids_T_6 = add(_count_valids_T_5, remapVecValids[7])
node _count_valids_T_7 = add(_count_valids_T_6, remapVecValids[8])
node _count_valids_T_8 = add(_count_valids_T_7, remapVecValids[9])
node _count_valids_T_9 = add(_count_valids_T_8, remapVecValids[10])
node _count_valids_T_10 = add(_count_valids_T_9, remapVecValids[11])
node _count_valids_T_11 = add(_count_valids_T_10, remapVecValids[12])
node _count_valids_T_12 = add(_count_valids_T_11, remapVecValids[13])
node _count_valids_T_13 = add(_count_valids_T_12, remapVecValids[14])
node _count_valids_T_14 = add(_count_valids_T_13, remapVecValids[15])
node _count_valids_T_15 = add(_count_valids_T_14, remapVecValids[16])
node _count_valids_T_16 = add(_count_valids_T_15, remapVecValids[17])
node _count_valids_T_17 = add(_count_valids_T_16, remapVecValids[18])
node _count_valids_T_18 = add(_count_valids_T_17, remapVecValids[19])
node _count_valids_T_19 = add(_count_valids_T_18, remapVecValids[20])
node _count_valids_T_20 = add(_count_valids_T_19, remapVecValids[21])
node _count_valids_T_21 = add(_count_valids_T_20, remapVecValids[22])
node _count_valids_T_22 = add(_count_valids_T_21, remapVecValids[23])
node _count_valids_T_23 = add(_count_valids_T_22, remapVecValids[24])
node _count_valids_T_24 = add(_count_valids_T_23, remapVecValids[25])
node _count_valids_T_25 = add(_count_valids_T_24, remapVecValids[26])
node _count_valids_T_26 = add(_count_valids_T_25, remapVecValids[27])
node _count_valids_T_27 = add(_count_valids_T_26, remapVecValids[28])
node _count_valids_T_28 = add(_count_valids_T_27, remapVecValids[29])
node _count_valids_T_29 = add(_count_valids_T_28, remapVecValids[30])
node count_valids = add(_count_valids_T_29, remapVecValids[31])
node _unconsumed_bytes_so_far_T = sub(buf_info_queue.io.deq.bits.len_bytes, len_already_consumed)
node unconsumed_bytes_so_far = tail(_unconsumed_bytes_so_far_T, 1)
node _enough_data_T = geq(unconsumed_bytes_so_far, UInt<6>(0h20))
node _enough_data_T_1 = eq(count_valids, UInt<6>(0h20))
node _enough_data_T_2 = geq(count_valids, unconsumed_bytes_so_far)
node enough_data = mux(_enough_data_T, _enough_data_T_1, _enough_data_T_2)
node _io_consumer_available_output_bytes_T = geq(unconsumed_bytes_so_far, UInt<6>(0h20))
node _io_consumer_available_output_bytes_T_1 = mux(_io_consumer_available_output_bytes_T, UInt<6>(0h20), unconsumed_bytes_so_far)
connect io.consumer.available_output_bytes, _io_consumer_available_output_bytes_T_1
node _io_consumer_output_last_chunk_T = leq(unconsumed_bytes_so_far, UInt<6>(0h20))
connect io.consumer.output_last_chunk, _io_consumer_output_last_chunk_T
node _T_3138 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _T_3139 = and(_T_3138, enough_data)
when _T_3139 :
regreset loginfo_cycles_14 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_28 = add(loginfo_cycles_14, UInt<1>(0h1))
node _loginfo_cycles_T_29 = tail(_loginfo_cycles_T_28, 1)
connect loginfo_cycles_14, _loginfo_cycles_T_29
node _T_3140 = asUInt(reset)
node _T_3141 = eq(_T_3140, UInt<1>(0h0))
when _T_3141 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_14) : printf_28
node _T_3142 = asUInt(reset)
node _T_3143 = eq(_T_3142, UInt<1>(0h0))
when _T_3143 :
printf(clock, UInt<1>(0h1), "seq-revmemloader read: bytesread %d\n", io.consumer.user_consumed_bytes) : printf_29
node _io_consumer_output_valid_T = and(buf_info_queue.io.deq.valid, enough_data)
connect io.consumer.output_valid, _io_consumer_output_valid_T
node _remapVecReadys_0_T = lt(UInt<1>(0h0), io.consumer.user_consumed_bytes)
node _remapVecReadys_0_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_0_T_2 = and(_remapVecReadys_0_T_1, enough_data)
node _remapVecReadys_0_T_3 = and(_remapVecReadys_0_T, _remapVecReadys_0_T_2)
connect remapVecReadys[0], _remapVecReadys_0_T_3
node _remapVecReadys_1_T = lt(UInt<1>(0h1), io.consumer.user_consumed_bytes)
node _remapVecReadys_1_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_1_T_2 = and(_remapVecReadys_1_T_1, enough_data)
node _remapVecReadys_1_T_3 = and(_remapVecReadys_1_T, _remapVecReadys_1_T_2)
connect remapVecReadys[1], _remapVecReadys_1_T_3
node _remapVecReadys_2_T = lt(UInt<2>(0h2), io.consumer.user_consumed_bytes)
node _remapVecReadys_2_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_2_T_2 = and(_remapVecReadys_2_T_1, enough_data)
node _remapVecReadys_2_T_3 = and(_remapVecReadys_2_T, _remapVecReadys_2_T_2)
connect remapVecReadys[2], _remapVecReadys_2_T_3
node _remapVecReadys_3_T = lt(UInt<2>(0h3), io.consumer.user_consumed_bytes)
node _remapVecReadys_3_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_3_T_2 = and(_remapVecReadys_3_T_1, enough_data)
node _remapVecReadys_3_T_3 = and(_remapVecReadys_3_T, _remapVecReadys_3_T_2)
connect remapVecReadys[3], _remapVecReadys_3_T_3
node _remapVecReadys_4_T = lt(UInt<3>(0h4), io.consumer.user_consumed_bytes)
node _remapVecReadys_4_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_4_T_2 = and(_remapVecReadys_4_T_1, enough_data)
node _remapVecReadys_4_T_3 = and(_remapVecReadys_4_T, _remapVecReadys_4_T_2)
connect remapVecReadys[4], _remapVecReadys_4_T_3
node _remapVecReadys_5_T = lt(UInt<3>(0h5), io.consumer.user_consumed_bytes)
node _remapVecReadys_5_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_5_T_2 = and(_remapVecReadys_5_T_1, enough_data)
node _remapVecReadys_5_T_3 = and(_remapVecReadys_5_T, _remapVecReadys_5_T_2)
connect remapVecReadys[5], _remapVecReadys_5_T_3
node _remapVecReadys_6_T = lt(UInt<3>(0h6), io.consumer.user_consumed_bytes)
node _remapVecReadys_6_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_6_T_2 = and(_remapVecReadys_6_T_1, enough_data)
node _remapVecReadys_6_T_3 = and(_remapVecReadys_6_T, _remapVecReadys_6_T_2)
connect remapVecReadys[6], _remapVecReadys_6_T_3
node _remapVecReadys_7_T = lt(UInt<3>(0h7), io.consumer.user_consumed_bytes)
node _remapVecReadys_7_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_7_T_2 = and(_remapVecReadys_7_T_1, enough_data)
node _remapVecReadys_7_T_3 = and(_remapVecReadys_7_T, _remapVecReadys_7_T_2)
connect remapVecReadys[7], _remapVecReadys_7_T_3
node _remapVecReadys_8_T = lt(UInt<4>(0h8), io.consumer.user_consumed_bytes)
node _remapVecReadys_8_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_8_T_2 = and(_remapVecReadys_8_T_1, enough_data)
node _remapVecReadys_8_T_3 = and(_remapVecReadys_8_T, _remapVecReadys_8_T_2)
connect remapVecReadys[8], _remapVecReadys_8_T_3
node _remapVecReadys_9_T = lt(UInt<4>(0h9), io.consumer.user_consumed_bytes)
node _remapVecReadys_9_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_9_T_2 = and(_remapVecReadys_9_T_1, enough_data)
node _remapVecReadys_9_T_3 = and(_remapVecReadys_9_T, _remapVecReadys_9_T_2)
connect remapVecReadys[9], _remapVecReadys_9_T_3
node _remapVecReadys_10_T = lt(UInt<4>(0ha), io.consumer.user_consumed_bytes)
node _remapVecReadys_10_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_10_T_2 = and(_remapVecReadys_10_T_1, enough_data)
node _remapVecReadys_10_T_3 = and(_remapVecReadys_10_T, _remapVecReadys_10_T_2)
connect remapVecReadys[10], _remapVecReadys_10_T_3
node _remapVecReadys_11_T = lt(UInt<4>(0hb), io.consumer.user_consumed_bytes)
node _remapVecReadys_11_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_11_T_2 = and(_remapVecReadys_11_T_1, enough_data)
node _remapVecReadys_11_T_3 = and(_remapVecReadys_11_T, _remapVecReadys_11_T_2)
connect remapVecReadys[11], _remapVecReadys_11_T_3
node _remapVecReadys_12_T = lt(UInt<4>(0hc), io.consumer.user_consumed_bytes)
node _remapVecReadys_12_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_12_T_2 = and(_remapVecReadys_12_T_1, enough_data)
node _remapVecReadys_12_T_3 = and(_remapVecReadys_12_T, _remapVecReadys_12_T_2)
connect remapVecReadys[12], _remapVecReadys_12_T_3
node _remapVecReadys_13_T = lt(UInt<4>(0hd), io.consumer.user_consumed_bytes)
node _remapVecReadys_13_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_13_T_2 = and(_remapVecReadys_13_T_1, enough_data)
node _remapVecReadys_13_T_3 = and(_remapVecReadys_13_T, _remapVecReadys_13_T_2)
connect remapVecReadys[13], _remapVecReadys_13_T_3
node _remapVecReadys_14_T = lt(UInt<4>(0he), io.consumer.user_consumed_bytes)
node _remapVecReadys_14_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_14_T_2 = and(_remapVecReadys_14_T_1, enough_data)
node _remapVecReadys_14_T_3 = and(_remapVecReadys_14_T, _remapVecReadys_14_T_2)
connect remapVecReadys[14], _remapVecReadys_14_T_3
node _remapVecReadys_15_T = lt(UInt<4>(0hf), io.consumer.user_consumed_bytes)
node _remapVecReadys_15_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_15_T_2 = and(_remapVecReadys_15_T_1, enough_data)
node _remapVecReadys_15_T_3 = and(_remapVecReadys_15_T, _remapVecReadys_15_T_2)
connect remapVecReadys[15], _remapVecReadys_15_T_3
node _remapVecReadys_16_T = lt(UInt<5>(0h10), io.consumer.user_consumed_bytes)
node _remapVecReadys_16_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_16_T_2 = and(_remapVecReadys_16_T_1, enough_data)
node _remapVecReadys_16_T_3 = and(_remapVecReadys_16_T, _remapVecReadys_16_T_2)
connect remapVecReadys[16], _remapVecReadys_16_T_3
node _remapVecReadys_17_T = lt(UInt<5>(0h11), io.consumer.user_consumed_bytes)
node _remapVecReadys_17_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_17_T_2 = and(_remapVecReadys_17_T_1, enough_data)
node _remapVecReadys_17_T_3 = and(_remapVecReadys_17_T, _remapVecReadys_17_T_2)
connect remapVecReadys[17], _remapVecReadys_17_T_3
node _remapVecReadys_18_T = lt(UInt<5>(0h12), io.consumer.user_consumed_bytes)
node _remapVecReadys_18_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_18_T_2 = and(_remapVecReadys_18_T_1, enough_data)
node _remapVecReadys_18_T_3 = and(_remapVecReadys_18_T, _remapVecReadys_18_T_2)
connect remapVecReadys[18], _remapVecReadys_18_T_3
node _remapVecReadys_19_T = lt(UInt<5>(0h13), io.consumer.user_consumed_bytes)
node _remapVecReadys_19_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_19_T_2 = and(_remapVecReadys_19_T_1, enough_data)
node _remapVecReadys_19_T_3 = and(_remapVecReadys_19_T, _remapVecReadys_19_T_2)
connect remapVecReadys[19], _remapVecReadys_19_T_3
node _remapVecReadys_20_T = lt(UInt<5>(0h14), io.consumer.user_consumed_bytes)
node _remapVecReadys_20_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_20_T_2 = and(_remapVecReadys_20_T_1, enough_data)
node _remapVecReadys_20_T_3 = and(_remapVecReadys_20_T, _remapVecReadys_20_T_2)
connect remapVecReadys[20], _remapVecReadys_20_T_3
node _remapVecReadys_21_T = lt(UInt<5>(0h15), io.consumer.user_consumed_bytes)
node _remapVecReadys_21_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_21_T_2 = and(_remapVecReadys_21_T_1, enough_data)
node _remapVecReadys_21_T_3 = and(_remapVecReadys_21_T, _remapVecReadys_21_T_2)
connect remapVecReadys[21], _remapVecReadys_21_T_3
node _remapVecReadys_22_T = lt(UInt<5>(0h16), io.consumer.user_consumed_bytes)
node _remapVecReadys_22_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_22_T_2 = and(_remapVecReadys_22_T_1, enough_data)
node _remapVecReadys_22_T_3 = and(_remapVecReadys_22_T, _remapVecReadys_22_T_2)
connect remapVecReadys[22], _remapVecReadys_22_T_3
node _remapVecReadys_23_T = lt(UInt<5>(0h17), io.consumer.user_consumed_bytes)
node _remapVecReadys_23_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_23_T_2 = and(_remapVecReadys_23_T_1, enough_data)
node _remapVecReadys_23_T_3 = and(_remapVecReadys_23_T, _remapVecReadys_23_T_2)
connect remapVecReadys[23], _remapVecReadys_23_T_3
node _remapVecReadys_24_T = lt(UInt<5>(0h18), io.consumer.user_consumed_bytes)
node _remapVecReadys_24_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_24_T_2 = and(_remapVecReadys_24_T_1, enough_data)
node _remapVecReadys_24_T_3 = and(_remapVecReadys_24_T, _remapVecReadys_24_T_2)
connect remapVecReadys[24], _remapVecReadys_24_T_3
node _remapVecReadys_25_T = lt(UInt<5>(0h19), io.consumer.user_consumed_bytes)
node _remapVecReadys_25_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_25_T_2 = and(_remapVecReadys_25_T_1, enough_data)
node _remapVecReadys_25_T_3 = and(_remapVecReadys_25_T, _remapVecReadys_25_T_2)
connect remapVecReadys[25], _remapVecReadys_25_T_3
node _remapVecReadys_26_T = lt(UInt<5>(0h1a), io.consumer.user_consumed_bytes)
node _remapVecReadys_26_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_26_T_2 = and(_remapVecReadys_26_T_1, enough_data)
node _remapVecReadys_26_T_3 = and(_remapVecReadys_26_T, _remapVecReadys_26_T_2)
connect remapVecReadys[26], _remapVecReadys_26_T_3
node _remapVecReadys_27_T = lt(UInt<5>(0h1b), io.consumer.user_consumed_bytes)
node _remapVecReadys_27_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_27_T_2 = and(_remapVecReadys_27_T_1, enough_data)
node _remapVecReadys_27_T_3 = and(_remapVecReadys_27_T, _remapVecReadys_27_T_2)
connect remapVecReadys[27], _remapVecReadys_27_T_3
node _remapVecReadys_28_T = lt(UInt<5>(0h1c), io.consumer.user_consumed_bytes)
node _remapVecReadys_28_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_28_T_2 = and(_remapVecReadys_28_T_1, enough_data)
node _remapVecReadys_28_T_3 = and(_remapVecReadys_28_T, _remapVecReadys_28_T_2)
connect remapVecReadys[28], _remapVecReadys_28_T_3
node _remapVecReadys_29_T = lt(UInt<5>(0h1d), io.consumer.user_consumed_bytes)
node _remapVecReadys_29_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_29_T_2 = and(_remapVecReadys_29_T_1, enough_data)
node _remapVecReadys_29_T_3 = and(_remapVecReadys_29_T, _remapVecReadys_29_T_2)
connect remapVecReadys[29], _remapVecReadys_29_T_3
node _remapVecReadys_30_T = lt(UInt<5>(0h1e), io.consumer.user_consumed_bytes)
node _remapVecReadys_30_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_30_T_2 = and(_remapVecReadys_30_T_1, enough_data)
node _remapVecReadys_30_T_3 = and(_remapVecReadys_30_T, _remapVecReadys_30_T_2)
connect remapVecReadys[30], _remapVecReadys_30_T_3
node _remapVecReadys_31_T = lt(UInt<5>(0h1f), io.consumer.user_consumed_bytes)
node _remapVecReadys_31_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_31_T_2 = and(_remapVecReadys_31_T_1, enough_data)
node _remapVecReadys_31_T_3 = and(_remapVecReadys_31_T, _remapVecReadys_31_T_2)
connect remapVecReadys[31], _remapVecReadys_31_T_3
node _T_3144 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _T_3145 = and(_T_3144, enough_data)
when _T_3145 :
node _read_start_index_T = add(read_start_index, io.consumer.user_consumed_bytes)
node _read_start_index_T_1 = rem(_read_start_index_T, UInt<6>(0h20))
connect read_start_index, _read_start_index_T_1
node _buf_info_queue_io_deq_ready_T = and(io.consumer.output_ready, enough_data)
node _buf_info_queue_io_deq_ready_T_1 = and(_buf_info_queue_io_deq_ready_T, buf_last)
connect buf_info_queue.io.deq.ready, _buf_info_queue_io_deq_ready_T_1
node _T_3146 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _T_3147 = and(_T_3146, enough_data)
when _T_3147 :
when buf_last :
connect len_already_consumed, UInt<1>(0h0)
else :
node _len_already_consumed_T = add(len_already_consumed, io.consumer.user_consumed_bytes)
node _len_already_consumed_T_1 = tail(_len_already_consumed_T, 1)
connect len_already_consumed, _len_already_consumed_T_1 | module ReverseMemLoader_1( // @[ReverseMemLoader.scala:13:7]
input clock, // @[ReverseMemLoader.scala:13:7]
input reset, // @[ReverseMemLoader.scala:13:7]
input io_l2helperUser_req_ready, // @[ReverseMemLoader.scala:16:14]
output io_l2helperUser_req_valid, // @[ReverseMemLoader.scala:16:14]
output [70:0] io_l2helperUser_req_bits_addr, // @[ReverseMemLoader.scala:16:14]
output io_l2helperUser_resp_ready, // @[ReverseMemLoader.scala:16:14]
input io_l2helperUser_resp_valid, // @[ReverseMemLoader.scala:16:14]
input [255:0] io_l2helperUser_resp_bits_data, // @[ReverseMemLoader.scala:16:14]
input io_l2helperUser_no_memops_inflight, // @[ReverseMemLoader.scala:16:14]
output io_src_info_ready, // @[ReverseMemLoader.scala:16:14]
input io_src_info_valid, // @[ReverseMemLoader.scala:16:14]
input [63:0] io_src_info_bits_ip, // @[ReverseMemLoader.scala:16:14]
input [63:0] io_src_info_bits_isize, // @[ReverseMemLoader.scala:16:14]
output [5:0] io_consumer_available_output_bytes, // @[ReverseMemLoader.scala:16:14]
output io_consumer_output_valid, // @[ReverseMemLoader.scala:16:14]
input io_consumer_output_ready, // @[ReverseMemLoader.scala:16:14]
output [255:0] io_consumer_output_data, // @[ReverseMemLoader.scala:16:14]
output io_consumer_output_last_chunk // @[ReverseMemLoader.scala:16:14]
);
wire _Queue64_UInt8_31_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_31_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_31_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_30_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_30_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_30_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_29_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_29_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_29_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_28_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_28_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_28_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_27_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_27_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_27_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_26_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_26_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_26_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_25_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_25_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_25_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_24_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_24_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_24_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_23_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_23_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_23_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_22_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_22_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_22_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_21_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_21_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_21_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_20_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_20_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_20_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_19_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_19_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_19_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_18_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_18_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_18_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_17_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_17_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_17_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_16_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_16_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_16_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_15_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_15_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_15_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_14_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_14_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_14_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_13_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_13_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_13_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_12_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_12_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_12_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_11_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_11_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_11_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_10_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_10_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_10_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_9_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_9_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_9_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_8_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_8_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_8_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_7_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_7_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_7_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_6_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_6_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_6_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_5_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_5_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_5_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_4_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_4_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_4_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_3_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_3_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_3_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_2_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_2_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_2_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_1_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_1_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_1_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_io_enq_ready; // @[ReverseMemLoader.scala:104:52]
wire _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52]
wire [7:0] _Queue64_UInt8_io_deq_bits; // @[ReverseMemLoader.scala:104:52]
wire _load_info_queue_io_enq_ready; // @[ReverseMemLoader.scala:25:31]
wire _load_info_queue_io_deq_valid; // @[ReverseMemLoader.scala:25:31]
wire [4:0] _load_info_queue_io_deq_bits_start_byte; // @[ReverseMemLoader.scala:25:31]
wire [4:0] _load_info_queue_io_deq_bits_end_byte; // @[ReverseMemLoader.scala:25:31]
wire _buf_info_queue_io_enq_ready; // @[ReverseMemLoader.scala:23:30]
wire _buf_info_queue_io_deq_valid; // @[ReverseMemLoader.scala:23:30]
wire [63:0] _buf_info_queue_io_deq_bits_len_bytes; // @[ReverseMemLoader.scala:23:30]
wire io_l2helperUser_req_ready_0 = io_l2helperUser_req_ready; // @[ReverseMemLoader.scala:13:7]
wire io_l2helperUser_resp_valid_0 = io_l2helperUser_resp_valid; // @[ReverseMemLoader.scala:13:7]
wire [255:0] io_l2helperUser_resp_bits_data_0 = io_l2helperUser_resp_bits_data; // @[ReverseMemLoader.scala:13:7]
wire io_l2helperUser_no_memops_inflight_0 = io_l2helperUser_no_memops_inflight; // @[ReverseMemLoader.scala:13:7]
wire io_src_info_valid_0 = io_src_info_valid; // @[ReverseMemLoader.scala:13:7]
wire [63:0] io_src_info_bits_ip_0 = io_src_info_bits_ip; // @[ReverseMemLoader.scala:13:7]
wire [63:0] io_src_info_bits_isize_0 = io_src_info_bits_isize; // @[ReverseMemLoader.scala:13:7]
wire io_consumer_output_ready_0 = io_consumer_output_ready; // @[ReverseMemLoader.scala:13:7]
wire [2:0] io_l2helperUser_req_bits_size = 3'h5; // @[ReverseMemLoader.scala:13:7]
wire [255:0] io_l2helperUser_req_bits_data = 256'h0; // @[ReverseMemLoader.scala:13:7]
wire io_l2helperUser_req_bits_cmd = 1'h0; // @[ReverseMemLoader.scala:13:7]
wire _use_this_queue_T_3 = 1'h0; // @[ReverseMemLoader.scala:150:91]
wire remapVecReadys_12 = 1'h0; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_13 = 1'h0; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_14 = 1'h0; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_15 = 1'h0; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_16 = 1'h0; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_17 = 1'h0; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_18 = 1'h0; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_19 = 1'h0; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_20 = 1'h0; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_21 = 1'h0; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_22 = 1'h0; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_23 = 1'h0; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_24 = 1'h0; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_25 = 1'h0; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_26 = 1'h0; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_27 = 1'h0; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_28 = 1'h0; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_29 = 1'h0; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_30 = 1'h0; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_31 = 1'h0; // @[ReverseMemLoader.scala:163:28]
wire _remapVecReadys_12_T = 1'h0; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_12_T_3 = 1'h0; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_13_T = 1'h0; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_13_T_3 = 1'h0; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_14_T = 1'h0; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_14_T_3 = 1'h0; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_15_T = 1'h0; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_15_T_3 = 1'h0; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_16_T = 1'h0; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_16_T_3 = 1'h0; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_17_T = 1'h0; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_17_T_3 = 1'h0; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_18_T = 1'h0; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_18_T_3 = 1'h0; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_19_T = 1'h0; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_19_T_3 = 1'h0; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_20_T = 1'h0; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_20_T_3 = 1'h0; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_21_T = 1'h0; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_21_T_3 = 1'h0; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_22_T = 1'h0; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_22_T_3 = 1'h0; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_23_T = 1'h0; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_23_T_3 = 1'h0; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_24_T = 1'h0; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_24_T_3 = 1'h0; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_25_T = 1'h0; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_25_T_3 = 1'h0; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_26_T = 1'h0; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_26_T_3 = 1'h0; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_27_T = 1'h0; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_27_T_3 = 1'h0; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_28_T = 1'h0; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_28_T_3 = 1'h0; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_29_T = 1'h0; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_29_T_3 = 1'h0; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_30_T = 1'h0; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_30_T_3 = 1'h0; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_31_T = 1'h0; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_31_T_3 = 1'h0; // @[ReverseMemLoader.scala:210:78]
wire [5:0] io_consumer_user_consumed_bytes = 6'hC; // @[ReverseMemLoader.scala:13:7]
wire _use_this_queue_T_2 = 1'h1; // @[ReverseMemLoader.scala:150:41]
wire _use_this_queue_T_4 = 1'h1; // @[ReverseMemLoader.scala:150:77]
wire _use_this_queue_T_7 = 1'h1; // @[ReverseMemLoader.scala:151:41]
wire _remapVecReadys_0_T = 1'h1; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_1_T = 1'h1; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_2_T = 1'h1; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_3_T = 1'h1; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_4_T = 1'h1; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_5_T = 1'h1; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_6_T = 1'h1; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_7_T = 1'h1; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_8_T = 1'h1; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_9_T = 1'h1; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_10_T = 1'h1; // @[ReverseMemLoader.scala:210:43]
wire _remapVecReadys_11_T = 1'h1; // @[ReverseMemLoader.scala:210:43]
wire [7:0] _remapindex_T_156 = 8'h20; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_157 = 8'h20; // @[ReverseMemLoader.scala:172:53]
wire [6:0] _idx_T = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_5 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_10 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_15 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_20 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_25 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_30 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_35 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_40 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_45 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_50 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_55 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_60 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_65 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_70 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_75 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_80 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_85 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_90 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_95 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_100 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_105 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_110 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_115 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_120 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_125 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_130 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_135 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_140 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_145 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_150 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _idx_T_155 = 7'h3F; // @[ReverseMemLoader.scala:115:29]
wire [6:0] _wrap_len_index_wide_T = 7'h3F; // @[ReverseMemLoader.scala:125:42]
wire [6:0] _remapindex_T = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_5 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_10 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_15 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_20 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_25 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_30 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_35 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_40 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_45 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_50 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_55 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_60 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_65 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_70 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_75 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_80 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_85 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_90 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_95 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_100 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_105 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_110 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_115 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_120 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_125 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_130 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_135 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_140 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_145 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_150 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [6:0] _remapindex_T_155 = 7'h3F; // @[ReverseMemLoader.scala:172:36]
wire [7:0] _remapindex_T_151 = 8'h21; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_152 = 8'h21; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_146 = 8'h22; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_147 = 8'h22; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_141 = 8'h23; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_142 = 8'h23; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_136 = 8'h24; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_137 = 8'h24; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_131 = 8'h25; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_132 = 8'h25; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_126 = 8'h26; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_127 = 8'h26; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_121 = 8'h27; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_122 = 8'h27; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_116 = 8'h28; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_117 = 8'h28; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_111 = 8'h29; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_112 = 8'h29; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_106 = 8'h2A; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_107 = 8'h2A; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_101 = 8'h2B; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_102 = 8'h2B; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_96 = 8'h2C; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_97 = 8'h2C; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_91 = 8'h2D; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_92 = 8'h2D; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_86 = 8'h2E; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_87 = 8'h2E; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_81 = 8'h2F; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_82 = 8'h2F; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_76 = 8'h30; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_77 = 8'h30; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_71 = 8'h31; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_72 = 8'h31; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_66 = 8'h32; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_67 = 8'h32; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_61 = 8'h33; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_62 = 8'h33; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_56 = 8'h34; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_57 = 8'h34; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_51 = 8'h35; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_52 = 8'h35; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_46 = 8'h36; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_47 = 8'h36; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_41 = 8'h37; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_42 = 8'h37; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_36 = 8'h38; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_37 = 8'h38; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_31 = 8'h39; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_32 = 8'h39; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_26 = 8'h3A; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_27 = 8'h3A; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_21 = 8'h3B; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_22 = 8'h3B; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_16 = 8'h3C; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_17 = 8'h3C; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_11 = 8'h3D; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_12 = 8'h3D; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_6 = 8'h3E; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_7 = 8'h3E; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_1 = 8'h3F; // @[ReverseMemLoader.scala:172:53]
wire [7:0] _remapindex_T_2 = 8'h3F; // @[ReverseMemLoader.scala:172:53]
wire [5:0] MAX_QUEUE_IDX = 6'h1F; // @[ReverseMemLoader.scala:108:36]
wire [6:0] _MAX_QUEUE_IDX_T = 7'h1F; // @[ReverseMemLoader.scala:108:36]
wire _io_l2helperUser_req_valid_T_1; // @[Misc.scala:26:53]
wire [70:0] _io_l2helperUser_req_bits_addr_T_2; // @[ReverseMemLoader.scala:98:61]
wire _io_l2helperUser_resp_ready_T; // @[Misc.scala:26:53]
wire _io_src_info_ready_T_3; // @[Misc.scala:26:53]
wire _io_consumer_output_valid_T; // @[Misc.scala:26:53]
wire [255:0] _io_consumer_output_data_T; // @[ReverseMemLoader.scala:181:33]
wire _io_consumer_output_last_chunk_T; // @[ReverseMemLoader.scala:194:61]
wire [70:0] io_l2helperUser_req_bits_addr_0; // @[ReverseMemLoader.scala:13:7]
wire io_l2helperUser_req_valid_0; // @[ReverseMemLoader.scala:13:7]
wire io_l2helperUser_resp_ready_0; // @[ReverseMemLoader.scala:13:7]
wire io_src_info_ready_0; // @[ReverseMemLoader.scala:13:7]
wire [5:0] io_consumer_available_output_bytes_0; // @[ReverseMemLoader.scala:13:7]
wire io_consumer_output_valid_0; // @[ReverseMemLoader.scala:13:7]
wire [255:0] io_consumer_output_data_0; // @[ReverseMemLoader.scala:13:7]
wire io_consumer_output_last_chunk_0; // @[ReverseMemLoader.scala:13:7]
wire [63:0] base_addr_start_index = {59'h0, io_src_info_bits_ip_0[4:0]}; // @[ReverseMemLoader.scala:13:7, :29:51]
wire [64:0] _GEN = {1'h0, io_src_info_bits_isize_0}; // @[ReverseMemLoader.scala:13:7, :30:35]
wire [64:0] _GEN_0 = _GEN + {1'h0, base_addr_start_index}; // @[ReverseMemLoader.scala:29:51, :30:35]
wire [64:0] _aligned_loadlen_T; // @[ReverseMemLoader.scala:30:35]
assign _aligned_loadlen_T = _GEN_0; // @[ReverseMemLoader.scala:30:35]
wire [64:0] _base_addr_end_index_T; // @[ReverseMemLoader.scala:31:39]
assign _base_addr_end_index_T = _GEN_0; // @[ReverseMemLoader.scala:30:35, :31:39]
wire [64:0] _base_addr_end_index_inclusive_T; // @[ReverseMemLoader.scala:32:49]
assign _base_addr_end_index_inclusive_T = _GEN_0; // @[ReverseMemLoader.scala:30:35, :32:49]
wire [63:0] aligned_loadlen = _aligned_loadlen_T[63:0]; // @[ReverseMemLoader.scala:30:35]
wire [63:0] _base_addr_end_index_T_1 = _base_addr_end_index_T[63:0]; // @[ReverseMemLoader.scala:31:39]
wire [63:0] base_addr_end_index = {59'h0, _base_addr_end_index_T_1[4:0]}; // @[ReverseMemLoader.scala:31:{39,64}]
wire [63:0] _base_addr_end_index_inclusive_T_1 = _base_addr_end_index_inclusive_T[63:0]; // @[ReverseMemLoader.scala:32:49]
wire [64:0] _base_addr_end_index_inclusive_T_2 = {1'h0, _base_addr_end_index_inclusive_T_1} - 65'h1; // @[ReverseMemLoader.scala:32:{49,73}]
wire [63:0] _base_addr_end_index_inclusive_T_3 = _base_addr_end_index_inclusive_T_2[63:0]; // @[ReverseMemLoader.scala:32:73]
wire [63:0] base_addr_end_index_inclusive = {59'h0, _base_addr_end_index_inclusive_T_3[4:0]}; // @[ReverseMemLoader.scala:32:{73,80}]
wire [63:0] _extra_word_T = {59'h0, aligned_loadlen[4:0]}; // @[ReverseMemLoader.scala:30:35, :33:38]
wire extra_word = |_extra_word_T; // @[ReverseMemLoader.scala:33:{38,48}]
wire [63:0] _base_addr_bytes_aligned_T = {5'h0, io_src_info_bits_ip_0[63:5]}; // @[ReverseMemLoader.scala:13:7, :35:50]
wire [70:0] base_addr_bytes_aligned = {2'h0, _base_addr_bytes_aligned_T, 5'h0}; // @[ReverseMemLoader.scala:35:{50,58}]
wire [63:0] _words_to_load_T = {5'h0, aligned_loadlen[63:5]}; // @[ReverseMemLoader.scala:30:35, :36:40]
wire [64:0] _words_to_load_T_1 = {1'h0, _words_to_load_T} + {64'h0, extra_word}; // @[ReverseMemLoader.scala:33:48, :36:{40,48}]
wire [63:0] words_to_load = _words_to_load_T_1[63:0]; // @[ReverseMemLoader.scala:36:48]
wire [64:0] _words_to_load_minus_one_T = {1'h0, words_to_load} - 65'h1; // @[ReverseMemLoader.scala:36:48, :37:47]
wire [63:0] words_to_load_minus_one = _words_to_load_minus_one_T[63:0]; // @[ReverseMemLoader.scala:37:47]
wire [64:0] _end_addr_bytes_aligned_T = {1'h0, io_src_info_bits_ip_0} + _GEN; // @[ReverseMemLoader.scala:13:7, :30:35, :39:50]
wire [63:0] _end_addr_bytes_aligned_T_1 = _end_addr_bytes_aligned_T[63:0]; // @[ReverseMemLoader.scala:39:50]
wire [64:0] _end_addr_bytes_aligned_T_2 = {1'h0, _end_addr_bytes_aligned_T_1} - 65'h1; // @[ReverseMemLoader.scala:39:{50,61}]
wire [63:0] _end_addr_bytes_aligned_T_3 = _end_addr_bytes_aligned_T_2[63:0]; // @[ReverseMemLoader.scala:39:61]
wire [63:0] _end_addr_bytes_aligned_T_4 = {5'h0, _end_addr_bytes_aligned_T_3[63:5]}; // @[ReverseMemLoader.scala:39:{61,68}]
wire [70:0] end_addr_bytes_aligned = {2'h0, _end_addr_bytes_aligned_T_4, 5'h0}; // @[ReverseMemLoader.scala:39:{68,76}]
reg print_not_done; // @[ReverseMemLoader.scala:41:31]
wire _T = io_src_info_valid_0 & print_not_done; // @[ReverseMemLoader.scala:13:7, :41:31, :43:27]
reg [63:0] loginfo_cycles; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38]
reg [63:0] addrinc; // @[ReverseMemLoader.scala:74:24]
wire _T_52 = addrinc == words_to_load_minus_one; // @[ReverseMemLoader.scala:37:47, :74:24, :76:57]
wire _load_info_queue_io_enq_bits_start_byte_T; // @[ReverseMemLoader.scala:76:57]
assign _load_info_queue_io_enq_bits_start_byte_T = _T_52; // @[ReverseMemLoader.scala:76:57]
wire _io_src_info_ready_T; // @[ReverseMemLoader.scala:90:53]
assign _io_src_info_ready_T = _T_52; // @[ReverseMemLoader.scala:76:57, :90:53]
wire [63:0] _load_info_queue_io_enq_bits_start_byte_T_1 = _load_info_queue_io_enq_bits_start_byte_T ? base_addr_start_index : 64'h0; // @[ReverseMemLoader.scala:29:51, :76:{48,57}]
wire _GEN_1 = addrinc == 64'h0; // @[ReverseMemLoader.scala:74:24, :77:55]
wire _load_info_queue_io_enq_bits_end_byte_T; // @[ReverseMemLoader.scala:77:55]
assign _load_info_queue_io_enq_bits_end_byte_T = _GEN_1; // @[ReverseMemLoader.scala:77:55]
wire _buf_info_queue_io_enq_valid_T; // @[ReverseMemLoader.scala:93:53]
assign _buf_info_queue_io_enq_valid_T = _GEN_1; // @[ReverseMemLoader.scala:77:55, :93:53]
wire [63:0] _load_info_queue_io_enq_bits_end_byte_T_1 = _load_info_queue_io_enq_bits_end_byte_T ? base_addr_end_index_inclusive : 64'h1F; // @[ReverseMemLoader.scala:32:80, :77:{46,55}]
wire _T_54 = io_l2helperUser_req_ready_0 & io_src_info_valid_0; // @[Misc.scala:29:18]
wire _buf_info_queue_io_enq_valid_T_1; // @[Misc.scala:26:53]
assign _buf_info_queue_io_enq_valid_T_1 = _T_54; // @[Misc.scala:26:53, :29:18]
wire _load_info_queue_io_enq_valid_T; // @[Misc.scala:26:53]
assign _load_info_queue_io_enq_valid_T = _T_54; // @[Misc.scala:26:53, :29:18]
wire [64:0] _addrinc_T = {1'h0, addrinc} + 65'h1; // @[ReverseMemLoader.scala:74:24, :82:24]
wire [63:0] _addrinc_T_1 = _addrinc_T[63:0]; // @[ReverseMemLoader.scala:82:24]
reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38]
wire _io_src_info_ready_T_1 = io_l2helperUser_req_ready_0 & _buf_info_queue_io_enq_ready; // @[Misc.scala:26:53]
wire _io_src_info_ready_T_2 = _io_src_info_ready_T_1 & _load_info_queue_io_enq_ready; // @[Misc.scala:26:53]
assign _io_src_info_ready_T_3 = _io_src_info_ready_T_2 & _io_src_info_ready_T; // @[Misc.scala:26:53]
assign io_src_info_ready_0 = _io_src_info_ready_T_3; // @[Misc.scala:26:53]
wire _buf_info_queue_io_enq_valid_T_2 = _buf_info_queue_io_enq_valid_T_1 & _load_info_queue_io_enq_ready; // @[Misc.scala:26:53]
wire _buf_info_queue_io_enq_valid_T_3 = _buf_info_queue_io_enq_valid_T_2 & _buf_info_queue_io_enq_valid_T; // @[Misc.scala:26:53]
wire _load_info_queue_io_enq_valid_T_1 = _load_info_queue_io_enq_valid_T & _buf_info_queue_io_enq_ready; // @[Misc.scala:26:53]
wire [68:0] _io_l2helperUser_req_bits_addr_T = {addrinc, 5'h0}; // @[ReverseMemLoader.scala:74:24, :98:72]
wire [71:0] _io_l2helperUser_req_bits_addr_T_1 = {1'h0, end_addr_bytes_aligned} - {3'h0, _io_l2helperUser_req_bits_addr_T}; // @[ReverseMemLoader.scala:39:76, :98:{61,72}]
assign _io_l2helperUser_req_bits_addr_T_2 = _io_l2helperUser_req_bits_addr_T_1[70:0]; // @[ReverseMemLoader.scala:98:61]
assign io_l2helperUser_req_bits_addr_0 = _io_l2helperUser_req_bits_addr_T_2; // @[ReverseMemLoader.scala:13:7, :98:61]
wire _io_l2helperUser_req_valid_T = io_src_info_valid_0 & _buf_info_queue_io_enq_ready; // @[Misc.scala:26:53]
assign _io_l2helperUser_req_valid_T_1 = _io_l2helperUser_req_valid_T & _load_info_queue_io_enq_ready; // @[Misc.scala:26:53]
assign io_l2helperUser_req_valid_0 = _io_l2helperUser_req_valid_T_1; // @[Misc.scala:26:53]
reg [5:0] write_start_index; // @[ReverseMemLoader.scala:103:34]
wire [5:0] _GEN_2 = {1'h0, _load_info_queue_io_deq_bits_end_byte}; // @[ReverseMemLoader.scala:25:31, :105:28]
wire [5:0] _align_shamt_T = 6'h1F - _GEN_2; // @[ReverseMemLoader.scala:105:28]
wire [4:0] _align_shamt_T_1 = _align_shamt_T[4:0]; // @[ReverseMemLoader.scala:105:28]
wire [7:0] align_shamt = {_align_shamt_T_1, 3'h0}; // @[ReverseMemLoader.scala:105:{28,68}]
wire [510:0] memresp_bits_shifted = {255'h0, io_l2helperUser_resp_bits_data_0} << align_shamt; // @[ReverseMemLoader.scala:13:7, :105:68, :106:61]
wire [7:0] _GEN_3 = 8'h3F - {2'h0, write_start_index}; // @[ReverseMemLoader.scala:103:34, :115:46]
wire [7:0] _idx_T_1; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_1 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_6; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_6 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_11; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_11 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_16; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_16 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_21; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_21 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_26; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_26 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_31; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_31 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_36; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_36 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_41; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_41 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_46; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_46 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_51; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_51 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_56; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_56 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_61; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_61 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_66; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_66 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_71; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_71 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_76; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_76 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_81; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_81 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_86; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_86 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_91; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_91 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_96; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_96 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_101; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_101 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_106; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_106 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_111; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_111 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_116; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_116 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_121; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_121 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_126; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_126 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_131; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_131 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_136; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_136 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_141; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_141 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_146; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_146 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_151; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_151 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _idx_T_156; // @[ReverseMemLoader.scala:115:46]
assign _idx_T_156 = _GEN_3; // @[ReverseMemLoader.scala:115:46]
wire [7:0] _wrap_len_index_wide_T_1; // @[ReverseMemLoader.scala:125:59]
assign _wrap_len_index_wide_T_1 = _GEN_3; // @[ReverseMemLoader.scala:115:46, :125:59]
wire [7:0] _idx_T_2 = _idx_T_1; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_3 = {1'h0, _idx_T_2}; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_4 = _idx_T_3; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_4 = _idx_T_4 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx = _GEN_4[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_7 = _idx_T_6; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_8 = {1'h0, _idx_T_7} - 9'h1; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_9 = _idx_T_8; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_5 = _idx_T_9 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_1 = _GEN_5[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_12 = _idx_T_11; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_13 = {1'h0, _idx_T_12} - 9'h2; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_14 = _idx_T_13; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_6 = _idx_T_14 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_2 = _GEN_6[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_17 = _idx_T_16; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_18 = {1'h0, _idx_T_17} - 9'h3; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_19 = _idx_T_18; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_7 = _idx_T_19 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_3 = _GEN_7[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_22 = _idx_T_21; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_23 = {1'h0, _idx_T_22} - 9'h4; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_24 = _idx_T_23; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_8 = _idx_T_24 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_4 = _GEN_8[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_27 = _idx_T_26; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_28 = {1'h0, _idx_T_27} - 9'h5; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_29 = _idx_T_28; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_9 = _idx_T_29 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_5 = _GEN_9[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_32 = _idx_T_31; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_33 = {1'h0, _idx_T_32} - 9'h6; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_34 = _idx_T_33; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_10 = _idx_T_34 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_6 = _GEN_10[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_37 = _idx_T_36; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_38 = {1'h0, _idx_T_37} - 9'h7; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_39 = _idx_T_38; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_11 = _idx_T_39 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_7 = _GEN_11[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_42 = _idx_T_41; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_43 = {1'h0, _idx_T_42} - 9'h8; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_44 = _idx_T_43; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_12 = _idx_T_44 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_8 = _GEN_12[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_47 = _idx_T_46; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_48 = {1'h0, _idx_T_47} - 9'h9; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_49 = _idx_T_48; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_13 = _idx_T_49 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_9 = _GEN_13[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_52 = _idx_T_51; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_53 = {1'h0, _idx_T_52} - 9'hA; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_54 = _idx_T_53; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_14 = _idx_T_54 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_10 = _GEN_14[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_57 = _idx_T_56; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_58 = {1'h0, _idx_T_57} - 9'hB; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_59 = _idx_T_58; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_15 = _idx_T_59 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_11 = _GEN_15[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_62 = _idx_T_61; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_63 = {1'h0, _idx_T_62} - 9'hC; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_64 = _idx_T_63; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_16 = _idx_T_64 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_12 = _GEN_16[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_67 = _idx_T_66; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_68 = {1'h0, _idx_T_67} - 9'hD; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_69 = _idx_T_68; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_17 = _idx_T_69 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_13 = _GEN_17[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_72 = _idx_T_71; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_73 = {1'h0, _idx_T_72} - 9'hE; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_74 = _idx_T_73; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_18 = _idx_T_74 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_14 = _GEN_18[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_77 = _idx_T_76; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_78 = {1'h0, _idx_T_77} - 9'hF; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_79 = _idx_T_78; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_19 = _idx_T_79 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_15 = _GEN_19[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_82 = _idx_T_81; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_83 = {1'h0, _idx_T_82} - 9'h10; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_84 = _idx_T_83; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_20 = _idx_T_84 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_16 = _GEN_20[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_87 = _idx_T_86; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_88 = {1'h0, _idx_T_87} - 9'h11; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_89 = _idx_T_88; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_21 = _idx_T_89 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_17 = _GEN_21[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_92 = _idx_T_91; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_93 = {1'h0, _idx_T_92} - 9'h12; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_94 = _idx_T_93; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_22 = _idx_T_94 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_18 = _GEN_22[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_97 = _idx_T_96; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_98 = {1'h0, _idx_T_97} - 9'h13; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_99 = _idx_T_98; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_23 = _idx_T_99 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_19 = _GEN_23[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_102 = _idx_T_101; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_103 = {1'h0, _idx_T_102} - 9'h14; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_104 = _idx_T_103; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_24 = _idx_T_104 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_20 = _GEN_24[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_107 = _idx_T_106; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_108 = {1'h0, _idx_T_107} - 9'h15; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_109 = _idx_T_108; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_25 = _idx_T_109 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_21 = _GEN_25[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_112 = _idx_T_111; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_113 = {1'h0, _idx_T_112} - 9'h16; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_114 = _idx_T_113; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_26 = _idx_T_114 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_22 = _GEN_26[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_117 = _idx_T_116; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_118 = {1'h0, _idx_T_117} - 9'h17; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_119 = _idx_T_118; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_27 = _idx_T_119 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_23 = _GEN_27[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_122 = _idx_T_121; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_123 = {1'h0, _idx_T_122} - 9'h18; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_124 = _idx_T_123; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_28 = _idx_T_124 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_24 = _GEN_28[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_127 = _idx_T_126; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_128 = {1'h0, _idx_T_127} - 9'h19; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_129 = _idx_T_128; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_29 = _idx_T_129 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_25 = _GEN_29[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_132 = _idx_T_131; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_133 = {1'h0, _idx_T_132} - 9'h1A; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_134 = _idx_T_133; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_30 = _idx_T_134 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_26 = _GEN_30[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_137 = _idx_T_136; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_138 = {1'h0, _idx_T_137} - 9'h1B; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_139 = _idx_T_138; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_31 = _idx_T_139 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_27 = _GEN_31[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_142 = _idx_T_141; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_143 = {1'h0, _idx_T_142} - 9'h1C; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_144 = _idx_T_143; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_32 = _idx_T_144 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_28 = _GEN_32[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_147 = _idx_T_146; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_148 = {1'h0, _idx_T_147} - 9'h1D; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_149 = _idx_T_148; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_33 = _idx_T_149 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_29 = _GEN_33[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_152 = _idx_T_151; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_153 = {1'h0, _idx_T_152} - 9'h1E; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_154 = _idx_T_153; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_34 = _idx_T_154 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_30 = _GEN_34[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [7:0] _idx_T_157 = _idx_T_156; // @[ReverseMemLoader.scala:115:46]
wire [8:0] _idx_T_158 = {1'h0, _idx_T_157} - 9'h1F; // @[ReverseMemLoader.scala:115:{46,67}]
wire [8:0] _idx_T_159 = _idx_T_158; // @[ReverseMemLoader.scala:115:67]
wire [8:0] _GEN_35 = _idx_T_159 % 9'h20; // @[ReverseMemLoader.scala:115:{67,81}]
wire [5:0] idx_31 = _GEN_35[5:0]; // @[ReverseMemLoader.scala:115:81]
wire [5:0] _len_to_write_T = _GEN_2 - {1'h0, _load_info_queue_io_deq_bits_start_byte}; // @[ReverseMemLoader.scala:25:31, :105:28, :123:60]
wire [4:0] _len_to_write_T_1 = _len_to_write_T[4:0]; // @[ReverseMemLoader.scala:123:60]
wire [5:0] len_to_write = {1'h0, _len_to_write_T_1} + 6'h1; // @[ReverseMemLoader.scala:123:{60,102}]
wire [7:0] _wrap_len_index_wide_T_2 = _wrap_len_index_wide_T_1; // @[ReverseMemLoader.scala:125:59]
wire [8:0] _wrap_len_index_wide_T_3 = {1'h0, _wrap_len_index_wide_T_2} - {3'h0, len_to_write}; // @[ReverseMemLoader.scala:123:102, :125:{59,80}]
wire [8:0] wrap_len_index_wide = _wrap_len_index_wide_T_3; // @[ReverseMemLoader.scala:125:80]
wire [8:0] _GEN_36 = wrap_len_index_wide % 9'h20; // @[ReverseMemLoader.scala:125:80, :126:48]
wire [5:0] wrap_len_index_end = _GEN_36[5:0]; // @[ReverseMemLoader.scala:126:48]
wire wrapped = wrap_len_index_wide < 9'h1F; // @[ReverseMemLoader.scala:125:80, :127:37]
reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38]
wire _all_queues_ready_T = _Queue64_UInt8_io_enq_ready & _Queue64_UInt8_1_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_1 = _all_queues_ready_T & _Queue64_UInt8_2_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_2 = _all_queues_ready_T_1 & _Queue64_UInt8_3_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_3 = _all_queues_ready_T_2 & _Queue64_UInt8_4_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_4 = _all_queues_ready_T_3 & _Queue64_UInt8_5_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_5 = _all_queues_ready_T_4 & _Queue64_UInt8_6_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_6 = _all_queues_ready_T_5 & _Queue64_UInt8_7_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_7 = _all_queues_ready_T_6 & _Queue64_UInt8_8_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_8 = _all_queues_ready_T_7 & _Queue64_UInt8_9_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_9 = _all_queues_ready_T_8 & _Queue64_UInt8_10_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_10 = _all_queues_ready_T_9 & _Queue64_UInt8_11_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_11 = _all_queues_ready_T_10 & _Queue64_UInt8_12_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_12 = _all_queues_ready_T_11 & _Queue64_UInt8_13_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_13 = _all_queues_ready_T_12 & _Queue64_UInt8_14_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_14 = _all_queues_ready_T_13 & _Queue64_UInt8_15_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_15 = _all_queues_ready_T_14 & _Queue64_UInt8_16_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_16 = _all_queues_ready_T_15 & _Queue64_UInt8_17_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_17 = _all_queues_ready_T_16 & _Queue64_UInt8_18_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_18 = _all_queues_ready_T_17 & _Queue64_UInt8_19_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_19 = _all_queues_ready_T_18 & _Queue64_UInt8_20_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_20 = _all_queues_ready_T_19 & _Queue64_UInt8_21_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_21 = _all_queues_ready_T_20 & _Queue64_UInt8_22_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_22 = _all_queues_ready_T_21 & _Queue64_UInt8_23_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_23 = _all_queues_ready_T_22 & _Queue64_UInt8_24_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_24 = _all_queues_ready_T_23 & _Queue64_UInt8_25_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_25 = _all_queues_ready_T_24 & _Queue64_UInt8_26_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_26 = _all_queues_ready_T_25 & _Queue64_UInt8_27_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_27 = _all_queues_ready_T_26 & _Queue64_UInt8_28_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_28 = _all_queues_ready_T_27 & _Queue64_UInt8_29_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _all_queues_ready_T_29 = _all_queues_ready_T_28 & _Queue64_UInt8_30_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire all_queues_ready = _all_queues_ready_T_29 & _Queue64_UInt8_31_io_enq_ready; // @[ReverseMemLoader.scala:104:52, :138:68]
wire _load_info_queue_io_deq_ready_T = io_l2helperUser_resp_valid_0 & all_queues_ready; // @[Misc.scala:26:53]
assign _io_l2helperUser_resp_ready_T = _load_info_queue_io_deq_valid & all_queues_ready; // @[Misc.scala:26:53]
assign io_l2helperUser_resp_ready_0 = _io_l2helperUser_resp_ready_T; // @[Misc.scala:26:53]
wire _GEN_37 = io_l2helperUser_resp_valid_0 & _load_info_queue_io_deq_valid; // @[Misc.scala:29:18]
wire _resp_fire_allqueues_T; // @[Misc.scala:29:18]
assign _resp_fire_allqueues_T = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T; // @[Misc.scala:29:18]
assign _cur_queue_valid_T = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_2; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_2 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_4; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_4 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_6; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_6 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_8; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_8 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_10; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_10 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_12; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_12 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_14; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_14 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_16; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_16 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_18; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_18 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_20; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_20 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_22; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_22 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_24; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_24 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_26; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_26 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_28; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_28 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_30; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_30 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_32; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_32 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_34; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_34 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_36; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_36 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_38; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_38 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_40; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_40 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_42; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_42 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_44; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_44 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_46; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_46 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_48; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_48 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_50; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_50 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_52; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_52 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_54; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_54 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_56; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_56 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_58; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_58 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_60; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_60 = _GEN_37; // @[Misc.scala:29:18]
wire _cur_queue_valid_T_62; // @[Misc.scala:29:18]
assign _cur_queue_valid_T_62 = _GEN_37; // @[Misc.scala:29:18]
wire resp_fire_allqueues = _resp_fire_allqueues_T & all_queues_ready; // @[Misc.scala:29:18]
wire [6:0] _write_start_index_T = 7'h1F - {1'h0, wrap_len_index_end}; // @[ReverseMemLoader.scala:126:48, :145:40]
wire [5:0] _write_start_index_T_1 = _write_start_index_T[5:0]; // @[ReverseMemLoader.scala:145:40]
wire [6:0] _GEN_38 = {1'h0, write_start_index}; // @[ReverseMemLoader.scala:103:34, :150:57]
wire [6:0] _GEN_39 = 7'h1F - _GEN_38; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_5; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_5 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_14; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_14 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_19; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_19 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_28; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_28 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_33; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_33 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_42; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_42 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_47; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_47 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_56; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_56 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_61; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_61 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_70; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_70 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_75; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_75 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_84; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_84 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_89; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_89 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_98; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_98 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_103; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_103 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_112; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_112 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_117; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_117 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_126; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_126 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_131; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_131 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_140; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_140 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_145; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_145 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_154; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_154 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_159; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_159 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_168; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_168 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_173; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_173 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_182; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_182 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_187; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_187 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_196; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_196 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_201; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_201 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_210; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_210 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_215; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_215 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_224; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_224 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_229; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_229 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_238; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_238 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_243; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_243 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_252; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_252 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_257; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_257 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_266; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_266 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_271; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_271 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_280; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_280 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_285; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_285 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_294; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_294 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_299; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_299 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_308; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_308 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_313; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_313 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_322; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_322 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_327; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_327 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_336; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_336 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_341; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_341 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_350; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_350 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_355; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_355 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_364; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_364 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_369; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_369 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_378; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_378 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_383; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_383 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_392; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_392 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_397; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_397 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_406; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_406 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_411; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_411 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_420; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_420 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_425; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_425 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [6:0] _use_this_queue_T_434; // @[ReverseMemLoader.scala:150:57]
assign _use_this_queue_T_434 = _GEN_39; // @[ReverseMemLoader.scala:150:57]
wire [6:0] _use_this_queue_T_439; // @[ReverseMemLoader.scala:151:57]
assign _use_this_queue_T_439 = _GEN_39; // @[ReverseMemLoader.scala:150:57, :151:57]
wire [5:0] _use_this_queue_T_1 = _use_this_queue_T[5:0]; // @[ReverseMemLoader.scala:150:57]
wire [5:0] _use_this_queue_T_6 = _use_this_queue_T_5[5:0]; // @[ReverseMemLoader.scala:151:57]
wire [6:0] _GEN_40 = 7'h20 - _GEN_38; // @[ReverseMemLoader.scala:150:57, :151:106]
wire [6:0] _use_this_queue_T_8; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_8 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_22; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_22 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_36; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_36 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_50; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_50 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_64; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_64 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_78; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_78 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_92; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_92 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_106; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_106 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_120; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_120 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_134; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_134 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_148; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_148 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_162; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_162 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_176; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_176 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_190; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_190 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_204; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_204 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_218; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_218 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_232; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_232 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_246; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_246 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_260; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_260 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_274; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_274 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_288; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_288 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_302; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_302 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_316; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_316 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_330; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_330 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_344; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_344 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_358; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_358 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_372; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_372 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_386; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_386 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_400; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_400 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_414; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_414 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_428; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_428 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_442; // @[ReverseMemLoader.scala:151:106]
assign _use_this_queue_T_442 = _GEN_40; // @[ReverseMemLoader.scala:151:106]
wire [5:0] _use_this_queue_T_9 = _use_this_queue_T_8[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _GEN_41 = {1'h0, len_to_write}; // @[ReverseMemLoader.scala:123:102, :151:124]
wire [6:0] _use_this_queue_T_10 = {1'h0, _use_this_queue_T_9} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_11 = _use_this_queue_T_10[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_12 = _use_this_queue_T_11 == 6'h0; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_13 = _use_this_queue_T_12; // @[ReverseMemLoader.scala:151:{77,91}]
wire use_this_queue = wrapped | _use_this_queue_T_13; // @[ReverseMemLoader.scala:127:37, :149:29, :151:77]
wire _cur_queue_valid_T_1 = _cur_queue_valid_T & use_this_queue; // @[Misc.scala:29:18]
wire cur_queue_valid = _cur_queue_valid_T_1 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_15 = _use_this_queue_T_14[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_16 = |_use_this_queue_T_15; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_17 = wrap_len_index_end == 6'h0; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_18 = _use_this_queue_T_16 | _use_this_queue_T_17; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_20 = _use_this_queue_T_19[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_21 = |_use_this_queue_T_20; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_23 = _use_this_queue_T_22[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_24 = {1'h0, _use_this_queue_T_23} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_25 = _use_this_queue_T_24[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_26 = _use_this_queue_T_25 < 6'h2; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_27 = _use_this_queue_T_21 & _use_this_queue_T_26; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_1 = wrapped ? _use_this_queue_T_18 : _use_this_queue_T_27; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_3 = _cur_queue_valid_T_2 & use_this_queue_1; // @[Misc.scala:29:18]
wire cur_queue_valid_1 = _cur_queue_valid_T_3 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_29 = _use_this_queue_T_28[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_30 = |(_use_this_queue_T_29[5:1]); // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_31 = wrap_len_index_end < 6'h2; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_32 = _use_this_queue_T_30 | _use_this_queue_T_31; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_34 = _use_this_queue_T_33[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_35 = |(_use_this_queue_T_34[5:1]); // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_37 = _use_this_queue_T_36[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_38 = {1'h0, _use_this_queue_T_37} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_39 = _use_this_queue_T_38[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_40 = _use_this_queue_T_39 < 6'h3; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_41 = _use_this_queue_T_35 & _use_this_queue_T_40; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_2 = wrapped ? _use_this_queue_T_32 : _use_this_queue_T_41; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_5 = _cur_queue_valid_T_4 & use_this_queue_2; // @[Misc.scala:29:18]
wire cur_queue_valid_2 = _cur_queue_valid_T_5 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_43 = _use_this_queue_T_42[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_44 = _use_this_queue_T_43 > 6'h2; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_45 = wrap_len_index_end < 6'h3; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_46 = _use_this_queue_T_44 | _use_this_queue_T_45; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_48 = _use_this_queue_T_47[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_49 = _use_this_queue_T_48 > 6'h2; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_51 = _use_this_queue_T_50[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_52 = {1'h0, _use_this_queue_T_51} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_53 = _use_this_queue_T_52[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_54 = _use_this_queue_T_53 < 6'h4; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_55 = _use_this_queue_T_49 & _use_this_queue_T_54; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_3 = wrapped ? _use_this_queue_T_46 : _use_this_queue_T_55; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_7 = _cur_queue_valid_T_6 & use_this_queue_3; // @[Misc.scala:29:18]
wire cur_queue_valid_3 = _cur_queue_valid_T_7 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_57 = _use_this_queue_T_56[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_58 = |(_use_this_queue_T_57[5:2]); // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_59 = wrap_len_index_end < 6'h4; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_60 = _use_this_queue_T_58 | _use_this_queue_T_59; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_62 = _use_this_queue_T_61[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_63 = |(_use_this_queue_T_62[5:2]); // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_65 = _use_this_queue_T_64[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_66 = {1'h0, _use_this_queue_T_65} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_67 = _use_this_queue_T_66[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_68 = _use_this_queue_T_67 < 6'h5; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_69 = _use_this_queue_T_63 & _use_this_queue_T_68; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_4 = wrapped ? _use_this_queue_T_60 : _use_this_queue_T_69; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_9 = _cur_queue_valid_T_8 & use_this_queue_4; // @[Misc.scala:29:18]
wire cur_queue_valid_4 = _cur_queue_valid_T_9 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_71 = _use_this_queue_T_70[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_72 = _use_this_queue_T_71 > 6'h4; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_73 = wrap_len_index_end < 6'h5; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_74 = _use_this_queue_T_72 | _use_this_queue_T_73; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_76 = _use_this_queue_T_75[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_77 = _use_this_queue_T_76 > 6'h4; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_79 = _use_this_queue_T_78[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_80 = {1'h0, _use_this_queue_T_79} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_81 = _use_this_queue_T_80[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_82 = _use_this_queue_T_81 < 6'h6; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_83 = _use_this_queue_T_77 & _use_this_queue_T_82; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_5 = wrapped ? _use_this_queue_T_74 : _use_this_queue_T_83; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_11 = _cur_queue_valid_T_10 & use_this_queue_5; // @[Misc.scala:29:18]
wire cur_queue_valid_5 = _cur_queue_valid_T_11 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_85 = _use_this_queue_T_84[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_86 = _use_this_queue_T_85 > 6'h5; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_87 = wrap_len_index_end < 6'h6; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_88 = _use_this_queue_T_86 | _use_this_queue_T_87; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_90 = _use_this_queue_T_89[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_91 = _use_this_queue_T_90 > 6'h5; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_93 = _use_this_queue_T_92[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_94 = {1'h0, _use_this_queue_T_93} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_95 = _use_this_queue_T_94[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_96 = _use_this_queue_T_95 < 6'h7; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_97 = _use_this_queue_T_91 & _use_this_queue_T_96; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_6 = wrapped ? _use_this_queue_T_88 : _use_this_queue_T_97; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_13 = _cur_queue_valid_T_12 & use_this_queue_6; // @[Misc.scala:29:18]
wire cur_queue_valid_6 = _cur_queue_valid_T_13 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_99 = _use_this_queue_T_98[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_100 = _use_this_queue_T_99 > 6'h6; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_101 = wrap_len_index_end < 6'h7; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_102 = _use_this_queue_T_100 | _use_this_queue_T_101; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_104 = _use_this_queue_T_103[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_105 = _use_this_queue_T_104 > 6'h6; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_107 = _use_this_queue_T_106[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_108 = {1'h0, _use_this_queue_T_107} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_109 = _use_this_queue_T_108[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_110 = _use_this_queue_T_109 < 6'h8; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_111 = _use_this_queue_T_105 & _use_this_queue_T_110; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_7 = wrapped ? _use_this_queue_T_102 : _use_this_queue_T_111; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_15 = _cur_queue_valid_T_14 & use_this_queue_7; // @[Misc.scala:29:18]
wire cur_queue_valid_7 = _cur_queue_valid_T_15 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_113 = _use_this_queue_T_112[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_114 = |(_use_this_queue_T_113[5:3]); // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_115 = wrap_len_index_end < 6'h8; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_116 = _use_this_queue_T_114 | _use_this_queue_T_115; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_118 = _use_this_queue_T_117[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_119 = |(_use_this_queue_T_118[5:3]); // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_121 = _use_this_queue_T_120[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_122 = {1'h0, _use_this_queue_T_121} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_123 = _use_this_queue_T_122[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_124 = _use_this_queue_T_123 < 6'h9; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_125 = _use_this_queue_T_119 & _use_this_queue_T_124; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_8 = wrapped ? _use_this_queue_T_116 : _use_this_queue_T_125; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_17 = _cur_queue_valid_T_16 & use_this_queue_8; // @[Misc.scala:29:18]
wire cur_queue_valid_8 = _cur_queue_valid_T_17 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_127 = _use_this_queue_T_126[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_128 = _use_this_queue_T_127 > 6'h8; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_129 = wrap_len_index_end < 6'h9; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_130 = _use_this_queue_T_128 | _use_this_queue_T_129; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_132 = _use_this_queue_T_131[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_133 = _use_this_queue_T_132 > 6'h8; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_135 = _use_this_queue_T_134[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_136 = {1'h0, _use_this_queue_T_135} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_137 = _use_this_queue_T_136[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_138 = _use_this_queue_T_137 < 6'hA; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_139 = _use_this_queue_T_133 & _use_this_queue_T_138; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_9 = wrapped ? _use_this_queue_T_130 : _use_this_queue_T_139; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_19 = _cur_queue_valid_T_18 & use_this_queue_9; // @[Misc.scala:29:18]
wire cur_queue_valid_9 = _cur_queue_valid_T_19 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_141 = _use_this_queue_T_140[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_142 = _use_this_queue_T_141 > 6'h9; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_143 = wrap_len_index_end < 6'hA; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_144 = _use_this_queue_T_142 | _use_this_queue_T_143; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_146 = _use_this_queue_T_145[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_147 = _use_this_queue_T_146 > 6'h9; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_149 = _use_this_queue_T_148[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_150 = {1'h0, _use_this_queue_T_149} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_151 = _use_this_queue_T_150[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_152 = _use_this_queue_T_151 < 6'hB; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_153 = _use_this_queue_T_147 & _use_this_queue_T_152; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_10 = wrapped ? _use_this_queue_T_144 : _use_this_queue_T_153; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_21 = _cur_queue_valid_T_20 & use_this_queue_10; // @[Misc.scala:29:18]
wire cur_queue_valid_10 = _cur_queue_valid_T_21 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_155 = _use_this_queue_T_154[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_156 = _use_this_queue_T_155 > 6'hA; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_157 = wrap_len_index_end < 6'hB; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_158 = _use_this_queue_T_156 | _use_this_queue_T_157; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_160 = _use_this_queue_T_159[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_161 = _use_this_queue_T_160 > 6'hA; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_163 = _use_this_queue_T_162[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_164 = {1'h0, _use_this_queue_T_163} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_165 = _use_this_queue_T_164[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_166 = _use_this_queue_T_165 < 6'hC; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_167 = _use_this_queue_T_161 & _use_this_queue_T_166; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_11 = wrapped ? _use_this_queue_T_158 : _use_this_queue_T_167; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_23 = _cur_queue_valid_T_22 & use_this_queue_11; // @[Misc.scala:29:18]
wire cur_queue_valid_11 = _cur_queue_valid_T_23 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_169 = _use_this_queue_T_168[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_170 = _use_this_queue_T_169 > 6'hB; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_171 = wrap_len_index_end < 6'hC; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_172 = _use_this_queue_T_170 | _use_this_queue_T_171; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_174 = _use_this_queue_T_173[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_175 = _use_this_queue_T_174 > 6'hB; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_177 = _use_this_queue_T_176[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_178 = {1'h0, _use_this_queue_T_177} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_179 = _use_this_queue_T_178[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_180 = _use_this_queue_T_179 < 6'hD; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_181 = _use_this_queue_T_175 & _use_this_queue_T_180; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_12 = wrapped ? _use_this_queue_T_172 : _use_this_queue_T_181; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_25 = _cur_queue_valid_T_24 & use_this_queue_12; // @[Misc.scala:29:18]
wire cur_queue_valid_12 = _cur_queue_valid_T_25 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_183 = _use_this_queue_T_182[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_184 = _use_this_queue_T_183 > 6'hC; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_185 = wrap_len_index_end < 6'hD; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_186 = _use_this_queue_T_184 | _use_this_queue_T_185; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_188 = _use_this_queue_T_187[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_189 = _use_this_queue_T_188 > 6'hC; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_191 = _use_this_queue_T_190[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_192 = {1'h0, _use_this_queue_T_191} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_193 = _use_this_queue_T_192[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_194 = _use_this_queue_T_193 < 6'hE; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_195 = _use_this_queue_T_189 & _use_this_queue_T_194; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_13 = wrapped ? _use_this_queue_T_186 : _use_this_queue_T_195; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_27 = _cur_queue_valid_T_26 & use_this_queue_13; // @[Misc.scala:29:18]
wire cur_queue_valid_13 = _cur_queue_valid_T_27 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_197 = _use_this_queue_T_196[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_198 = _use_this_queue_T_197 > 6'hD; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_199 = wrap_len_index_end < 6'hE; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_200 = _use_this_queue_T_198 | _use_this_queue_T_199; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_202 = _use_this_queue_T_201[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_203 = _use_this_queue_T_202 > 6'hD; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_205 = _use_this_queue_T_204[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_206 = {1'h0, _use_this_queue_T_205} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_207 = _use_this_queue_T_206[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_208 = _use_this_queue_T_207 < 6'hF; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_209 = _use_this_queue_T_203 & _use_this_queue_T_208; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_14 = wrapped ? _use_this_queue_T_200 : _use_this_queue_T_209; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_29 = _cur_queue_valid_T_28 & use_this_queue_14; // @[Misc.scala:29:18]
wire cur_queue_valid_14 = _cur_queue_valid_T_29 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_211 = _use_this_queue_T_210[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_212 = _use_this_queue_T_211 > 6'hE; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_213 = wrap_len_index_end < 6'hF; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_214 = _use_this_queue_T_212 | _use_this_queue_T_213; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_216 = _use_this_queue_T_215[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_217 = _use_this_queue_T_216 > 6'hE; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_219 = _use_this_queue_T_218[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_220 = {1'h0, _use_this_queue_T_219} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_221 = _use_this_queue_T_220[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_222 = _use_this_queue_T_221 < 6'h10; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_223 = _use_this_queue_T_217 & _use_this_queue_T_222; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_15 = wrapped ? _use_this_queue_T_214 : _use_this_queue_T_223; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_31 = _cur_queue_valid_T_30 & use_this_queue_15; // @[Misc.scala:29:18]
wire cur_queue_valid_15 = _cur_queue_valid_T_31 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_225 = _use_this_queue_T_224[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_226 = |(_use_this_queue_T_225[5:4]); // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_227 = wrap_len_index_end < 6'h10; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_228 = _use_this_queue_T_226 | _use_this_queue_T_227; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_230 = _use_this_queue_T_229[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_231 = |(_use_this_queue_T_230[5:4]); // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_233 = _use_this_queue_T_232[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_234 = {1'h0, _use_this_queue_T_233} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_235 = _use_this_queue_T_234[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_236 = _use_this_queue_T_235 < 6'h11; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_237 = _use_this_queue_T_231 & _use_this_queue_T_236; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_16 = wrapped ? _use_this_queue_T_228 : _use_this_queue_T_237; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_33 = _cur_queue_valid_T_32 & use_this_queue_16; // @[Misc.scala:29:18]
wire cur_queue_valid_16 = _cur_queue_valid_T_33 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_239 = _use_this_queue_T_238[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_240 = _use_this_queue_T_239 > 6'h10; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_241 = wrap_len_index_end < 6'h11; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_242 = _use_this_queue_T_240 | _use_this_queue_T_241; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_244 = _use_this_queue_T_243[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_245 = _use_this_queue_T_244 > 6'h10; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_247 = _use_this_queue_T_246[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_248 = {1'h0, _use_this_queue_T_247} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_249 = _use_this_queue_T_248[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_250 = _use_this_queue_T_249 < 6'h12; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_251 = _use_this_queue_T_245 & _use_this_queue_T_250; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_17 = wrapped ? _use_this_queue_T_242 : _use_this_queue_T_251; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_35 = _cur_queue_valid_T_34 & use_this_queue_17; // @[Misc.scala:29:18]
wire cur_queue_valid_17 = _cur_queue_valid_T_35 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_253 = _use_this_queue_T_252[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_254 = _use_this_queue_T_253 > 6'h11; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_255 = wrap_len_index_end < 6'h12; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_256 = _use_this_queue_T_254 | _use_this_queue_T_255; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_258 = _use_this_queue_T_257[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_259 = _use_this_queue_T_258 > 6'h11; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_261 = _use_this_queue_T_260[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_262 = {1'h0, _use_this_queue_T_261} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_263 = _use_this_queue_T_262[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_264 = _use_this_queue_T_263 < 6'h13; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_265 = _use_this_queue_T_259 & _use_this_queue_T_264; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_18 = wrapped ? _use_this_queue_T_256 : _use_this_queue_T_265; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_37 = _cur_queue_valid_T_36 & use_this_queue_18; // @[Misc.scala:29:18]
wire cur_queue_valid_18 = _cur_queue_valid_T_37 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_267 = _use_this_queue_T_266[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_268 = _use_this_queue_T_267 > 6'h12; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_269 = wrap_len_index_end < 6'h13; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_270 = _use_this_queue_T_268 | _use_this_queue_T_269; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_272 = _use_this_queue_T_271[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_273 = _use_this_queue_T_272 > 6'h12; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_275 = _use_this_queue_T_274[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_276 = {1'h0, _use_this_queue_T_275} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_277 = _use_this_queue_T_276[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_278 = _use_this_queue_T_277 < 6'h14; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_279 = _use_this_queue_T_273 & _use_this_queue_T_278; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_19 = wrapped ? _use_this_queue_T_270 : _use_this_queue_T_279; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_39 = _cur_queue_valid_T_38 & use_this_queue_19; // @[Misc.scala:29:18]
wire cur_queue_valid_19 = _cur_queue_valid_T_39 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_281 = _use_this_queue_T_280[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_282 = _use_this_queue_T_281 > 6'h13; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_283 = wrap_len_index_end < 6'h14; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_284 = _use_this_queue_T_282 | _use_this_queue_T_283; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_286 = _use_this_queue_T_285[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_287 = _use_this_queue_T_286 > 6'h13; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_289 = _use_this_queue_T_288[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_290 = {1'h0, _use_this_queue_T_289} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_291 = _use_this_queue_T_290[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_292 = _use_this_queue_T_291 < 6'h15; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_293 = _use_this_queue_T_287 & _use_this_queue_T_292; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_20 = wrapped ? _use_this_queue_T_284 : _use_this_queue_T_293; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_41 = _cur_queue_valid_T_40 & use_this_queue_20; // @[Misc.scala:29:18]
wire cur_queue_valid_20 = _cur_queue_valid_T_41 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_295 = _use_this_queue_T_294[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_296 = _use_this_queue_T_295 > 6'h14; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_297 = wrap_len_index_end < 6'h15; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_298 = _use_this_queue_T_296 | _use_this_queue_T_297; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_300 = _use_this_queue_T_299[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_301 = _use_this_queue_T_300 > 6'h14; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_303 = _use_this_queue_T_302[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_304 = {1'h0, _use_this_queue_T_303} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_305 = _use_this_queue_T_304[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_306 = _use_this_queue_T_305 < 6'h16; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_307 = _use_this_queue_T_301 & _use_this_queue_T_306; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_21 = wrapped ? _use_this_queue_T_298 : _use_this_queue_T_307; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_43 = _cur_queue_valid_T_42 & use_this_queue_21; // @[Misc.scala:29:18]
wire cur_queue_valid_21 = _cur_queue_valid_T_43 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_309 = _use_this_queue_T_308[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_310 = _use_this_queue_T_309 > 6'h15; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_311 = wrap_len_index_end < 6'h16; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_312 = _use_this_queue_T_310 | _use_this_queue_T_311; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_314 = _use_this_queue_T_313[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_315 = _use_this_queue_T_314 > 6'h15; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_317 = _use_this_queue_T_316[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_318 = {1'h0, _use_this_queue_T_317} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_319 = _use_this_queue_T_318[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_320 = _use_this_queue_T_319 < 6'h17; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_321 = _use_this_queue_T_315 & _use_this_queue_T_320; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_22 = wrapped ? _use_this_queue_T_312 : _use_this_queue_T_321; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_45 = _cur_queue_valid_T_44 & use_this_queue_22; // @[Misc.scala:29:18]
wire cur_queue_valid_22 = _cur_queue_valid_T_45 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_323 = _use_this_queue_T_322[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_324 = _use_this_queue_T_323 > 6'h16; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_325 = wrap_len_index_end < 6'h17; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_326 = _use_this_queue_T_324 | _use_this_queue_T_325; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_328 = _use_this_queue_T_327[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_329 = _use_this_queue_T_328 > 6'h16; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_331 = _use_this_queue_T_330[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_332 = {1'h0, _use_this_queue_T_331} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_333 = _use_this_queue_T_332[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_334 = _use_this_queue_T_333 < 6'h18; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_335 = _use_this_queue_T_329 & _use_this_queue_T_334; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_23 = wrapped ? _use_this_queue_T_326 : _use_this_queue_T_335; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_47 = _cur_queue_valid_T_46 & use_this_queue_23; // @[Misc.scala:29:18]
wire cur_queue_valid_23 = _cur_queue_valid_T_47 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_337 = _use_this_queue_T_336[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_338 = _use_this_queue_T_337 > 6'h17; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_339 = wrap_len_index_end < 6'h18; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_340 = _use_this_queue_T_338 | _use_this_queue_T_339; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_342 = _use_this_queue_T_341[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_343 = _use_this_queue_T_342 > 6'h17; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_345 = _use_this_queue_T_344[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_346 = {1'h0, _use_this_queue_T_345} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_347 = _use_this_queue_T_346[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_348 = _use_this_queue_T_347 < 6'h19; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_349 = _use_this_queue_T_343 & _use_this_queue_T_348; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_24 = wrapped ? _use_this_queue_T_340 : _use_this_queue_T_349; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_49 = _cur_queue_valid_T_48 & use_this_queue_24; // @[Misc.scala:29:18]
wire cur_queue_valid_24 = _cur_queue_valid_T_49 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_351 = _use_this_queue_T_350[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_352 = _use_this_queue_T_351 > 6'h18; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_353 = wrap_len_index_end < 6'h19; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_354 = _use_this_queue_T_352 | _use_this_queue_T_353; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_356 = _use_this_queue_T_355[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_357 = _use_this_queue_T_356 > 6'h18; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_359 = _use_this_queue_T_358[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_360 = {1'h0, _use_this_queue_T_359} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_361 = _use_this_queue_T_360[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_362 = _use_this_queue_T_361 < 6'h1A; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_363 = _use_this_queue_T_357 & _use_this_queue_T_362; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_25 = wrapped ? _use_this_queue_T_354 : _use_this_queue_T_363; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_51 = _cur_queue_valid_T_50 & use_this_queue_25; // @[Misc.scala:29:18]
wire cur_queue_valid_25 = _cur_queue_valid_T_51 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_365 = _use_this_queue_T_364[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_366 = _use_this_queue_T_365 > 6'h19; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_367 = wrap_len_index_end < 6'h1A; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_368 = _use_this_queue_T_366 | _use_this_queue_T_367; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_370 = _use_this_queue_T_369[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_371 = _use_this_queue_T_370 > 6'h19; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_373 = _use_this_queue_T_372[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_374 = {1'h0, _use_this_queue_T_373} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_375 = _use_this_queue_T_374[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_376 = _use_this_queue_T_375 < 6'h1B; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_377 = _use_this_queue_T_371 & _use_this_queue_T_376; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_26 = wrapped ? _use_this_queue_T_368 : _use_this_queue_T_377; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_53 = _cur_queue_valid_T_52 & use_this_queue_26; // @[Misc.scala:29:18]
wire cur_queue_valid_26 = _cur_queue_valid_T_53 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_379 = _use_this_queue_T_378[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_380 = _use_this_queue_T_379 > 6'h1A; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_381 = wrap_len_index_end < 6'h1B; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_382 = _use_this_queue_T_380 | _use_this_queue_T_381; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_384 = _use_this_queue_T_383[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_385 = _use_this_queue_T_384 > 6'h1A; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_387 = _use_this_queue_T_386[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_388 = {1'h0, _use_this_queue_T_387} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_389 = _use_this_queue_T_388[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_390 = _use_this_queue_T_389 < 6'h1C; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_391 = _use_this_queue_T_385 & _use_this_queue_T_390; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_27 = wrapped ? _use_this_queue_T_382 : _use_this_queue_T_391; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_55 = _cur_queue_valid_T_54 & use_this_queue_27; // @[Misc.scala:29:18]
wire cur_queue_valid_27 = _cur_queue_valid_T_55 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_393 = _use_this_queue_T_392[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_394 = _use_this_queue_T_393 > 6'h1B; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_395 = wrap_len_index_end < 6'h1C; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_396 = _use_this_queue_T_394 | _use_this_queue_T_395; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_398 = _use_this_queue_T_397[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_399 = _use_this_queue_T_398 > 6'h1B; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_401 = _use_this_queue_T_400[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_402 = {1'h0, _use_this_queue_T_401} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_403 = _use_this_queue_T_402[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_404 = _use_this_queue_T_403 < 6'h1D; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_405 = _use_this_queue_T_399 & _use_this_queue_T_404; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_28 = wrapped ? _use_this_queue_T_396 : _use_this_queue_T_405; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_57 = _cur_queue_valid_T_56 & use_this_queue_28; // @[Misc.scala:29:18]
wire cur_queue_valid_28 = _cur_queue_valid_T_57 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_407 = _use_this_queue_T_406[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_408 = _use_this_queue_T_407 > 6'h1C; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_409 = wrap_len_index_end < 6'h1D; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_410 = _use_this_queue_T_408 | _use_this_queue_T_409; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_412 = _use_this_queue_T_411[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_413 = _use_this_queue_T_412 > 6'h1C; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_415 = _use_this_queue_T_414[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_416 = {1'h0, _use_this_queue_T_415} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_417 = _use_this_queue_T_416[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_418 = _use_this_queue_T_417 < 6'h1E; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_419 = _use_this_queue_T_413 & _use_this_queue_T_418; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_29 = wrapped ? _use_this_queue_T_410 : _use_this_queue_T_419; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_59 = _cur_queue_valid_T_58 & use_this_queue_29; // @[Misc.scala:29:18]
wire cur_queue_valid_29 = _cur_queue_valid_T_59 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_421 = _use_this_queue_T_420[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_422 = _use_this_queue_T_421 > 6'h1D; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_423 = wrap_len_index_end < 6'h1E; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_424 = _use_this_queue_T_422 | _use_this_queue_T_423; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_426 = _use_this_queue_T_425[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_427 = _use_this_queue_T_426 > 6'h1D; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_429 = _use_this_queue_T_428[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_430 = {1'h0, _use_this_queue_T_429} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_431 = _use_this_queue_T_430[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_432 = _use_this_queue_T_431 < 6'h1F; // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_433 = _use_this_queue_T_427 & _use_this_queue_T_432; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_30 = wrapped ? _use_this_queue_T_424 : _use_this_queue_T_433; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_61 = _cur_queue_valid_T_60 & use_this_queue_30; // @[Misc.scala:29:18]
wire cur_queue_valid_30 = _cur_queue_valid_T_61 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
wire [5:0] _use_this_queue_T_435 = _use_this_queue_T_434[5:0]; // @[ReverseMemLoader.scala:150:57]
wire _use_this_queue_T_436 = _use_this_queue_T_435 > 6'h1E; // @[ReverseMemLoader.scala:150:{41,57}]
wire _use_this_queue_T_437 = wrap_len_index_end < 6'h1F; // @[ReverseMemLoader.scala:126:48, :150:91]
wire _use_this_queue_T_438 = _use_this_queue_T_436 | _use_this_queue_T_437; // @[ReverseMemLoader.scala:150:{41,77,91}]
wire [5:0] _use_this_queue_T_440 = _use_this_queue_T_439[5:0]; // @[ReverseMemLoader.scala:151:57]
wire _use_this_queue_T_441 = _use_this_queue_T_440 > 6'h1E; // @[ReverseMemLoader.scala:151:{41,57}]
wire [5:0] _use_this_queue_T_443 = _use_this_queue_T_442[5:0]; // @[ReverseMemLoader.scala:151:106]
wire [6:0] _use_this_queue_T_444 = {1'h0, _use_this_queue_T_443} - _GEN_41; // @[ReverseMemLoader.scala:151:{106,124}]
wire [5:0] _use_this_queue_T_445 = _use_this_queue_T_444[5:0]; // @[ReverseMemLoader.scala:151:124]
wire _use_this_queue_T_446 = ~(_use_this_queue_T_445[5]); // @[ReverseMemLoader.scala:151:{91,124}]
wire _use_this_queue_T_447 = _use_this_queue_T_441 & _use_this_queue_T_446; // @[ReverseMemLoader.scala:151:{41,77,91}]
wire use_this_queue_31 = wrapped ? _use_this_queue_T_438 : _use_this_queue_T_447; // @[ReverseMemLoader.scala:127:37, :149:29, :150:77, :151:77]
wire _cur_queue_valid_T_63 = _cur_queue_valid_T_62 & use_this_queue_31; // @[Misc.scala:29:18]
wire cur_queue_valid_31 = _cur_queue_valid_T_63 & all_queues_ready; // @[ReverseMemLoader.scala:138:68, :154:{51,69}]
reg [5:0] read_start_index; // @[ReverseMemLoader.scala:158:33]
reg [63:0] len_already_consumed; // @[ReverseMemLoader.scala:159:37]
wire [7:0] remapVecData_0; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_1; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_2; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_3; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_4; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_5; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_6; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_7; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_8; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_9; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_10; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_11; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_12; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_13; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_14; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_15; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_16; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_17; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_18; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_19; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_20; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_21; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_22; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_23; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_24; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_25; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_26; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_27; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_28; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_29; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_30; // @[ReverseMemLoader.scala:161:26]
wire [7:0] remapVecData_31; // @[ReverseMemLoader.scala:161:26]
wire remapVecValids_0; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_1; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_2; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_3; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_4; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_5; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_6; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_7; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_8; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_9; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_10; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_11; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_12; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_13; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_14; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_15; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_16; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_17; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_18; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_19; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_20; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_21; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_22; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_23; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_24; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_25; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_26; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_27; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_28; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_29; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_30; // @[ReverseMemLoader.scala:162:28]
wire remapVecValids_31; // @[ReverseMemLoader.scala:162:28]
wire _remapVecReadys_0_T_3; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_1_T_3; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_2_T_3; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_3_T_3; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_4_T_3; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_5_T_3; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_6_T_3; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_7_T_3; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_8_T_3; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_9_T_3; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_10_T_3; // @[ReverseMemLoader.scala:210:78]
wire _remapVecReadys_11_T_3; // @[ReverseMemLoader.scala:210:78]
wire remapVecReadys_0; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_1; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_2; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_3; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_4; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_5; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_6; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_7; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_8; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_9; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_10; // @[ReverseMemLoader.scala:163:28]
wire remapVecReadys_11; // @[ReverseMemLoader.scala:163:28]
wire [8:0] _GEN_42 = {3'h0, read_start_index}; // @[ReverseMemLoader.scala:158:33, :172:66]
wire [8:0] _remapindex_T_3 = 9'h3F - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_4 = _remapindex_T_3; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_43 = _remapindex_T_4 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex = _GEN_43[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2114 = remapindex == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2115 = remapindex == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2116 = remapindex == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2117 = remapindex == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2118 = remapindex == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2119 = remapindex == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2120 = remapindex == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2121 = remapindex == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2122 = remapindex == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2123 = remapindex == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2124 = remapindex == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2125 = remapindex == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2126 = remapindex == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2127 = remapindex == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2128 = remapindex == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2129 = remapindex == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2130 = remapindex == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2131 = remapindex == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2132 = remapindex == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2133 = remapindex == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2134 = remapindex == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2135 = remapindex == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2136 = remapindex == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2137 = remapindex == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2138 = remapindex == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2139 = remapindex == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2140 = remapindex == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2141 = remapindex == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2142 = remapindex == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2143 = remapindex == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2144 = remapindex == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2145 = remapindex == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_0 = _T_2145 ? _Queue64_UInt8_31_io_deq_bits : _T_2144 ? _Queue64_UInt8_30_io_deq_bits : _T_2143 ? _Queue64_UInt8_29_io_deq_bits : _T_2142 ? _Queue64_UInt8_28_io_deq_bits : _T_2141 ? _Queue64_UInt8_27_io_deq_bits : _T_2140 ? _Queue64_UInt8_26_io_deq_bits : _T_2139 ? _Queue64_UInt8_25_io_deq_bits : _T_2138 ? _Queue64_UInt8_24_io_deq_bits : _T_2137 ? _Queue64_UInt8_23_io_deq_bits : _T_2136 ? _Queue64_UInt8_22_io_deq_bits : _T_2135 ? _Queue64_UInt8_21_io_deq_bits : _T_2134 ? _Queue64_UInt8_20_io_deq_bits : _T_2133 ? _Queue64_UInt8_19_io_deq_bits : _T_2132 ? _Queue64_UInt8_18_io_deq_bits : _T_2131 ? _Queue64_UInt8_17_io_deq_bits : _T_2130 ? _Queue64_UInt8_16_io_deq_bits : _T_2129 ? _Queue64_UInt8_15_io_deq_bits : _T_2128 ? _Queue64_UInt8_14_io_deq_bits : _T_2127 ? _Queue64_UInt8_13_io_deq_bits : _T_2126 ? _Queue64_UInt8_12_io_deq_bits : _T_2125 ? _Queue64_UInt8_11_io_deq_bits : _T_2124 ? _Queue64_UInt8_10_io_deq_bits : _T_2123 ? _Queue64_UInt8_9_io_deq_bits : _T_2122 ? _Queue64_UInt8_8_io_deq_bits : _T_2121 ? _Queue64_UInt8_7_io_deq_bits : _T_2120 ? _Queue64_UInt8_6_io_deq_bits : _T_2119 ? _Queue64_UInt8_5_io_deq_bits : _T_2118 ? _Queue64_UInt8_4_io_deq_bits : _T_2117 ? _Queue64_UInt8_3_io_deq_bits : _T_2116 ? _Queue64_UInt8_2_io_deq_bits : _T_2115 ? _Queue64_UInt8_1_io_deq_bits : _T_2114 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_0 = _T_2145 ? _Queue64_UInt8_31_io_deq_valid : _T_2144 ? _Queue64_UInt8_30_io_deq_valid : _T_2143 ? _Queue64_UInt8_29_io_deq_valid : _T_2142 ? _Queue64_UInt8_28_io_deq_valid : _T_2141 ? _Queue64_UInt8_27_io_deq_valid : _T_2140 ? _Queue64_UInt8_26_io_deq_valid : _T_2139 ? _Queue64_UInt8_25_io_deq_valid : _T_2138 ? _Queue64_UInt8_24_io_deq_valid : _T_2137 ? _Queue64_UInt8_23_io_deq_valid : _T_2136 ? _Queue64_UInt8_22_io_deq_valid : _T_2135 ? _Queue64_UInt8_21_io_deq_valid : _T_2134 ? _Queue64_UInt8_20_io_deq_valid : _T_2133 ? _Queue64_UInt8_19_io_deq_valid : _T_2132 ? _Queue64_UInt8_18_io_deq_valid : _T_2131 ? _Queue64_UInt8_17_io_deq_valid : _T_2130 ? _Queue64_UInt8_16_io_deq_valid : _T_2129 ? _Queue64_UInt8_15_io_deq_valid : _T_2128 ? _Queue64_UInt8_14_io_deq_valid : _T_2127 ? _Queue64_UInt8_13_io_deq_valid : _T_2126 ? _Queue64_UInt8_12_io_deq_valid : _T_2125 ? _Queue64_UInt8_11_io_deq_valid : _T_2124 ? _Queue64_UInt8_10_io_deq_valid : _T_2123 ? _Queue64_UInt8_9_io_deq_valid : _T_2122 ? _Queue64_UInt8_8_io_deq_valid : _T_2121 ? _Queue64_UInt8_7_io_deq_valid : _T_2120 ? _Queue64_UInt8_6_io_deq_valid : _T_2119 ? _Queue64_UInt8_5_io_deq_valid : _T_2118 ? _Queue64_UInt8_4_io_deq_valid : _T_2117 ? _Queue64_UInt8_3_io_deq_valid : _T_2116 ? _Queue64_UInt8_2_io_deq_valid : _T_2115 ? _Queue64_UInt8_1_io_deq_valid : _T_2114 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_8 = 9'h3E - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_9 = _remapindex_T_8; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_44 = _remapindex_T_9 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_1 = _GEN_44[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2146 = remapindex_1 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2147 = remapindex_1 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2148 = remapindex_1 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2149 = remapindex_1 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2150 = remapindex_1 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2151 = remapindex_1 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2152 = remapindex_1 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2153 = remapindex_1 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2154 = remapindex_1 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2155 = remapindex_1 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2156 = remapindex_1 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2157 = remapindex_1 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2158 = remapindex_1 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2159 = remapindex_1 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2160 = remapindex_1 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2161 = remapindex_1 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2162 = remapindex_1 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2163 = remapindex_1 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2164 = remapindex_1 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2165 = remapindex_1 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2166 = remapindex_1 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2167 = remapindex_1 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2168 = remapindex_1 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2169 = remapindex_1 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2170 = remapindex_1 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2171 = remapindex_1 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2172 = remapindex_1 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2173 = remapindex_1 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2174 = remapindex_1 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2175 = remapindex_1 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2176 = remapindex_1 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2177 = remapindex_1 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_1 = _T_2177 ? _Queue64_UInt8_31_io_deq_bits : _T_2176 ? _Queue64_UInt8_30_io_deq_bits : _T_2175 ? _Queue64_UInt8_29_io_deq_bits : _T_2174 ? _Queue64_UInt8_28_io_deq_bits : _T_2173 ? _Queue64_UInt8_27_io_deq_bits : _T_2172 ? _Queue64_UInt8_26_io_deq_bits : _T_2171 ? _Queue64_UInt8_25_io_deq_bits : _T_2170 ? _Queue64_UInt8_24_io_deq_bits : _T_2169 ? _Queue64_UInt8_23_io_deq_bits : _T_2168 ? _Queue64_UInt8_22_io_deq_bits : _T_2167 ? _Queue64_UInt8_21_io_deq_bits : _T_2166 ? _Queue64_UInt8_20_io_deq_bits : _T_2165 ? _Queue64_UInt8_19_io_deq_bits : _T_2164 ? _Queue64_UInt8_18_io_deq_bits : _T_2163 ? _Queue64_UInt8_17_io_deq_bits : _T_2162 ? _Queue64_UInt8_16_io_deq_bits : _T_2161 ? _Queue64_UInt8_15_io_deq_bits : _T_2160 ? _Queue64_UInt8_14_io_deq_bits : _T_2159 ? _Queue64_UInt8_13_io_deq_bits : _T_2158 ? _Queue64_UInt8_12_io_deq_bits : _T_2157 ? _Queue64_UInt8_11_io_deq_bits : _T_2156 ? _Queue64_UInt8_10_io_deq_bits : _T_2155 ? _Queue64_UInt8_9_io_deq_bits : _T_2154 ? _Queue64_UInt8_8_io_deq_bits : _T_2153 ? _Queue64_UInt8_7_io_deq_bits : _T_2152 ? _Queue64_UInt8_6_io_deq_bits : _T_2151 ? _Queue64_UInt8_5_io_deq_bits : _T_2150 ? _Queue64_UInt8_4_io_deq_bits : _T_2149 ? _Queue64_UInt8_3_io_deq_bits : _T_2148 ? _Queue64_UInt8_2_io_deq_bits : _T_2147 ? _Queue64_UInt8_1_io_deq_bits : _T_2146 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_1 = _T_2177 ? _Queue64_UInt8_31_io_deq_valid : _T_2176 ? _Queue64_UInt8_30_io_deq_valid : _T_2175 ? _Queue64_UInt8_29_io_deq_valid : _T_2174 ? _Queue64_UInt8_28_io_deq_valid : _T_2173 ? _Queue64_UInt8_27_io_deq_valid : _T_2172 ? _Queue64_UInt8_26_io_deq_valid : _T_2171 ? _Queue64_UInt8_25_io_deq_valid : _T_2170 ? _Queue64_UInt8_24_io_deq_valid : _T_2169 ? _Queue64_UInt8_23_io_deq_valid : _T_2168 ? _Queue64_UInt8_22_io_deq_valid : _T_2167 ? _Queue64_UInt8_21_io_deq_valid : _T_2166 ? _Queue64_UInt8_20_io_deq_valid : _T_2165 ? _Queue64_UInt8_19_io_deq_valid : _T_2164 ? _Queue64_UInt8_18_io_deq_valid : _T_2163 ? _Queue64_UInt8_17_io_deq_valid : _T_2162 ? _Queue64_UInt8_16_io_deq_valid : _T_2161 ? _Queue64_UInt8_15_io_deq_valid : _T_2160 ? _Queue64_UInt8_14_io_deq_valid : _T_2159 ? _Queue64_UInt8_13_io_deq_valid : _T_2158 ? _Queue64_UInt8_12_io_deq_valid : _T_2157 ? _Queue64_UInt8_11_io_deq_valid : _T_2156 ? _Queue64_UInt8_10_io_deq_valid : _T_2155 ? _Queue64_UInt8_9_io_deq_valid : _T_2154 ? _Queue64_UInt8_8_io_deq_valid : _T_2153 ? _Queue64_UInt8_7_io_deq_valid : _T_2152 ? _Queue64_UInt8_6_io_deq_valid : _T_2151 ? _Queue64_UInt8_5_io_deq_valid : _T_2150 ? _Queue64_UInt8_4_io_deq_valid : _T_2149 ? _Queue64_UInt8_3_io_deq_valid : _T_2148 ? _Queue64_UInt8_2_io_deq_valid : _T_2147 ? _Queue64_UInt8_1_io_deq_valid : _T_2146 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_13 = 9'h3D - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_14 = _remapindex_T_13; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_45 = _remapindex_T_14 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_2 = _GEN_45[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2178 = remapindex_2 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2179 = remapindex_2 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2180 = remapindex_2 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2181 = remapindex_2 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2182 = remapindex_2 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2183 = remapindex_2 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2184 = remapindex_2 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2185 = remapindex_2 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2186 = remapindex_2 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2187 = remapindex_2 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2188 = remapindex_2 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2189 = remapindex_2 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2190 = remapindex_2 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2191 = remapindex_2 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2192 = remapindex_2 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2193 = remapindex_2 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2194 = remapindex_2 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2195 = remapindex_2 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2196 = remapindex_2 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2197 = remapindex_2 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2198 = remapindex_2 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2199 = remapindex_2 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2200 = remapindex_2 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2201 = remapindex_2 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2202 = remapindex_2 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2203 = remapindex_2 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2204 = remapindex_2 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2205 = remapindex_2 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2206 = remapindex_2 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2207 = remapindex_2 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2208 = remapindex_2 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2209 = remapindex_2 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_2 = _T_2209 ? _Queue64_UInt8_31_io_deq_bits : _T_2208 ? _Queue64_UInt8_30_io_deq_bits : _T_2207 ? _Queue64_UInt8_29_io_deq_bits : _T_2206 ? _Queue64_UInt8_28_io_deq_bits : _T_2205 ? _Queue64_UInt8_27_io_deq_bits : _T_2204 ? _Queue64_UInt8_26_io_deq_bits : _T_2203 ? _Queue64_UInt8_25_io_deq_bits : _T_2202 ? _Queue64_UInt8_24_io_deq_bits : _T_2201 ? _Queue64_UInt8_23_io_deq_bits : _T_2200 ? _Queue64_UInt8_22_io_deq_bits : _T_2199 ? _Queue64_UInt8_21_io_deq_bits : _T_2198 ? _Queue64_UInt8_20_io_deq_bits : _T_2197 ? _Queue64_UInt8_19_io_deq_bits : _T_2196 ? _Queue64_UInt8_18_io_deq_bits : _T_2195 ? _Queue64_UInt8_17_io_deq_bits : _T_2194 ? _Queue64_UInt8_16_io_deq_bits : _T_2193 ? _Queue64_UInt8_15_io_deq_bits : _T_2192 ? _Queue64_UInt8_14_io_deq_bits : _T_2191 ? _Queue64_UInt8_13_io_deq_bits : _T_2190 ? _Queue64_UInt8_12_io_deq_bits : _T_2189 ? _Queue64_UInt8_11_io_deq_bits : _T_2188 ? _Queue64_UInt8_10_io_deq_bits : _T_2187 ? _Queue64_UInt8_9_io_deq_bits : _T_2186 ? _Queue64_UInt8_8_io_deq_bits : _T_2185 ? _Queue64_UInt8_7_io_deq_bits : _T_2184 ? _Queue64_UInt8_6_io_deq_bits : _T_2183 ? _Queue64_UInt8_5_io_deq_bits : _T_2182 ? _Queue64_UInt8_4_io_deq_bits : _T_2181 ? _Queue64_UInt8_3_io_deq_bits : _T_2180 ? _Queue64_UInt8_2_io_deq_bits : _T_2179 ? _Queue64_UInt8_1_io_deq_bits : _T_2178 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_2 = _T_2209 ? _Queue64_UInt8_31_io_deq_valid : _T_2208 ? _Queue64_UInt8_30_io_deq_valid : _T_2207 ? _Queue64_UInt8_29_io_deq_valid : _T_2206 ? _Queue64_UInt8_28_io_deq_valid : _T_2205 ? _Queue64_UInt8_27_io_deq_valid : _T_2204 ? _Queue64_UInt8_26_io_deq_valid : _T_2203 ? _Queue64_UInt8_25_io_deq_valid : _T_2202 ? _Queue64_UInt8_24_io_deq_valid : _T_2201 ? _Queue64_UInt8_23_io_deq_valid : _T_2200 ? _Queue64_UInt8_22_io_deq_valid : _T_2199 ? _Queue64_UInt8_21_io_deq_valid : _T_2198 ? _Queue64_UInt8_20_io_deq_valid : _T_2197 ? _Queue64_UInt8_19_io_deq_valid : _T_2196 ? _Queue64_UInt8_18_io_deq_valid : _T_2195 ? _Queue64_UInt8_17_io_deq_valid : _T_2194 ? _Queue64_UInt8_16_io_deq_valid : _T_2193 ? _Queue64_UInt8_15_io_deq_valid : _T_2192 ? _Queue64_UInt8_14_io_deq_valid : _T_2191 ? _Queue64_UInt8_13_io_deq_valid : _T_2190 ? _Queue64_UInt8_12_io_deq_valid : _T_2189 ? _Queue64_UInt8_11_io_deq_valid : _T_2188 ? _Queue64_UInt8_10_io_deq_valid : _T_2187 ? _Queue64_UInt8_9_io_deq_valid : _T_2186 ? _Queue64_UInt8_8_io_deq_valid : _T_2185 ? _Queue64_UInt8_7_io_deq_valid : _T_2184 ? _Queue64_UInt8_6_io_deq_valid : _T_2183 ? _Queue64_UInt8_5_io_deq_valid : _T_2182 ? _Queue64_UInt8_4_io_deq_valid : _T_2181 ? _Queue64_UInt8_3_io_deq_valid : _T_2180 ? _Queue64_UInt8_2_io_deq_valid : _T_2179 ? _Queue64_UInt8_1_io_deq_valid : _T_2178 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_18 = 9'h3C - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_19 = _remapindex_T_18; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_46 = _remapindex_T_19 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_3 = _GEN_46[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2210 = remapindex_3 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2211 = remapindex_3 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2212 = remapindex_3 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2213 = remapindex_3 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2214 = remapindex_3 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2215 = remapindex_3 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2216 = remapindex_3 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2217 = remapindex_3 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2218 = remapindex_3 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2219 = remapindex_3 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2220 = remapindex_3 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2221 = remapindex_3 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2222 = remapindex_3 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2223 = remapindex_3 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2224 = remapindex_3 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2225 = remapindex_3 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2226 = remapindex_3 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2227 = remapindex_3 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2228 = remapindex_3 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2229 = remapindex_3 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2230 = remapindex_3 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2231 = remapindex_3 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2232 = remapindex_3 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2233 = remapindex_3 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2234 = remapindex_3 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2235 = remapindex_3 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2236 = remapindex_3 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2237 = remapindex_3 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2238 = remapindex_3 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2239 = remapindex_3 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2240 = remapindex_3 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2241 = remapindex_3 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_3 = _T_2241 ? _Queue64_UInt8_31_io_deq_bits : _T_2240 ? _Queue64_UInt8_30_io_deq_bits : _T_2239 ? _Queue64_UInt8_29_io_deq_bits : _T_2238 ? _Queue64_UInt8_28_io_deq_bits : _T_2237 ? _Queue64_UInt8_27_io_deq_bits : _T_2236 ? _Queue64_UInt8_26_io_deq_bits : _T_2235 ? _Queue64_UInt8_25_io_deq_bits : _T_2234 ? _Queue64_UInt8_24_io_deq_bits : _T_2233 ? _Queue64_UInt8_23_io_deq_bits : _T_2232 ? _Queue64_UInt8_22_io_deq_bits : _T_2231 ? _Queue64_UInt8_21_io_deq_bits : _T_2230 ? _Queue64_UInt8_20_io_deq_bits : _T_2229 ? _Queue64_UInt8_19_io_deq_bits : _T_2228 ? _Queue64_UInt8_18_io_deq_bits : _T_2227 ? _Queue64_UInt8_17_io_deq_bits : _T_2226 ? _Queue64_UInt8_16_io_deq_bits : _T_2225 ? _Queue64_UInt8_15_io_deq_bits : _T_2224 ? _Queue64_UInt8_14_io_deq_bits : _T_2223 ? _Queue64_UInt8_13_io_deq_bits : _T_2222 ? _Queue64_UInt8_12_io_deq_bits : _T_2221 ? _Queue64_UInt8_11_io_deq_bits : _T_2220 ? _Queue64_UInt8_10_io_deq_bits : _T_2219 ? _Queue64_UInt8_9_io_deq_bits : _T_2218 ? _Queue64_UInt8_8_io_deq_bits : _T_2217 ? _Queue64_UInt8_7_io_deq_bits : _T_2216 ? _Queue64_UInt8_6_io_deq_bits : _T_2215 ? _Queue64_UInt8_5_io_deq_bits : _T_2214 ? _Queue64_UInt8_4_io_deq_bits : _T_2213 ? _Queue64_UInt8_3_io_deq_bits : _T_2212 ? _Queue64_UInt8_2_io_deq_bits : _T_2211 ? _Queue64_UInt8_1_io_deq_bits : _T_2210 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_3 = _T_2241 ? _Queue64_UInt8_31_io_deq_valid : _T_2240 ? _Queue64_UInt8_30_io_deq_valid : _T_2239 ? _Queue64_UInt8_29_io_deq_valid : _T_2238 ? _Queue64_UInt8_28_io_deq_valid : _T_2237 ? _Queue64_UInt8_27_io_deq_valid : _T_2236 ? _Queue64_UInt8_26_io_deq_valid : _T_2235 ? _Queue64_UInt8_25_io_deq_valid : _T_2234 ? _Queue64_UInt8_24_io_deq_valid : _T_2233 ? _Queue64_UInt8_23_io_deq_valid : _T_2232 ? _Queue64_UInt8_22_io_deq_valid : _T_2231 ? _Queue64_UInt8_21_io_deq_valid : _T_2230 ? _Queue64_UInt8_20_io_deq_valid : _T_2229 ? _Queue64_UInt8_19_io_deq_valid : _T_2228 ? _Queue64_UInt8_18_io_deq_valid : _T_2227 ? _Queue64_UInt8_17_io_deq_valid : _T_2226 ? _Queue64_UInt8_16_io_deq_valid : _T_2225 ? _Queue64_UInt8_15_io_deq_valid : _T_2224 ? _Queue64_UInt8_14_io_deq_valid : _T_2223 ? _Queue64_UInt8_13_io_deq_valid : _T_2222 ? _Queue64_UInt8_12_io_deq_valid : _T_2221 ? _Queue64_UInt8_11_io_deq_valid : _T_2220 ? _Queue64_UInt8_10_io_deq_valid : _T_2219 ? _Queue64_UInt8_9_io_deq_valid : _T_2218 ? _Queue64_UInt8_8_io_deq_valid : _T_2217 ? _Queue64_UInt8_7_io_deq_valid : _T_2216 ? _Queue64_UInt8_6_io_deq_valid : _T_2215 ? _Queue64_UInt8_5_io_deq_valid : _T_2214 ? _Queue64_UInt8_4_io_deq_valid : _T_2213 ? _Queue64_UInt8_3_io_deq_valid : _T_2212 ? _Queue64_UInt8_2_io_deq_valid : _T_2211 ? _Queue64_UInt8_1_io_deq_valid : _T_2210 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_23 = 9'h3B - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_24 = _remapindex_T_23; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_47 = _remapindex_T_24 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_4 = _GEN_47[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2242 = remapindex_4 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2243 = remapindex_4 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2244 = remapindex_4 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2245 = remapindex_4 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2246 = remapindex_4 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2247 = remapindex_4 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2248 = remapindex_4 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2249 = remapindex_4 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2250 = remapindex_4 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2251 = remapindex_4 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2252 = remapindex_4 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2253 = remapindex_4 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2254 = remapindex_4 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2255 = remapindex_4 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2256 = remapindex_4 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2257 = remapindex_4 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2258 = remapindex_4 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2259 = remapindex_4 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2260 = remapindex_4 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2261 = remapindex_4 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2262 = remapindex_4 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2263 = remapindex_4 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2264 = remapindex_4 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2265 = remapindex_4 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2266 = remapindex_4 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2267 = remapindex_4 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2268 = remapindex_4 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2269 = remapindex_4 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2270 = remapindex_4 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2271 = remapindex_4 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2272 = remapindex_4 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2273 = remapindex_4 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_4 = _T_2273 ? _Queue64_UInt8_31_io_deq_bits : _T_2272 ? _Queue64_UInt8_30_io_deq_bits : _T_2271 ? _Queue64_UInt8_29_io_deq_bits : _T_2270 ? _Queue64_UInt8_28_io_deq_bits : _T_2269 ? _Queue64_UInt8_27_io_deq_bits : _T_2268 ? _Queue64_UInt8_26_io_deq_bits : _T_2267 ? _Queue64_UInt8_25_io_deq_bits : _T_2266 ? _Queue64_UInt8_24_io_deq_bits : _T_2265 ? _Queue64_UInt8_23_io_deq_bits : _T_2264 ? _Queue64_UInt8_22_io_deq_bits : _T_2263 ? _Queue64_UInt8_21_io_deq_bits : _T_2262 ? _Queue64_UInt8_20_io_deq_bits : _T_2261 ? _Queue64_UInt8_19_io_deq_bits : _T_2260 ? _Queue64_UInt8_18_io_deq_bits : _T_2259 ? _Queue64_UInt8_17_io_deq_bits : _T_2258 ? _Queue64_UInt8_16_io_deq_bits : _T_2257 ? _Queue64_UInt8_15_io_deq_bits : _T_2256 ? _Queue64_UInt8_14_io_deq_bits : _T_2255 ? _Queue64_UInt8_13_io_deq_bits : _T_2254 ? _Queue64_UInt8_12_io_deq_bits : _T_2253 ? _Queue64_UInt8_11_io_deq_bits : _T_2252 ? _Queue64_UInt8_10_io_deq_bits : _T_2251 ? _Queue64_UInt8_9_io_deq_bits : _T_2250 ? _Queue64_UInt8_8_io_deq_bits : _T_2249 ? _Queue64_UInt8_7_io_deq_bits : _T_2248 ? _Queue64_UInt8_6_io_deq_bits : _T_2247 ? _Queue64_UInt8_5_io_deq_bits : _T_2246 ? _Queue64_UInt8_4_io_deq_bits : _T_2245 ? _Queue64_UInt8_3_io_deq_bits : _T_2244 ? _Queue64_UInt8_2_io_deq_bits : _T_2243 ? _Queue64_UInt8_1_io_deq_bits : _T_2242 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_4 = _T_2273 ? _Queue64_UInt8_31_io_deq_valid : _T_2272 ? _Queue64_UInt8_30_io_deq_valid : _T_2271 ? _Queue64_UInt8_29_io_deq_valid : _T_2270 ? _Queue64_UInt8_28_io_deq_valid : _T_2269 ? _Queue64_UInt8_27_io_deq_valid : _T_2268 ? _Queue64_UInt8_26_io_deq_valid : _T_2267 ? _Queue64_UInt8_25_io_deq_valid : _T_2266 ? _Queue64_UInt8_24_io_deq_valid : _T_2265 ? _Queue64_UInt8_23_io_deq_valid : _T_2264 ? _Queue64_UInt8_22_io_deq_valid : _T_2263 ? _Queue64_UInt8_21_io_deq_valid : _T_2262 ? _Queue64_UInt8_20_io_deq_valid : _T_2261 ? _Queue64_UInt8_19_io_deq_valid : _T_2260 ? _Queue64_UInt8_18_io_deq_valid : _T_2259 ? _Queue64_UInt8_17_io_deq_valid : _T_2258 ? _Queue64_UInt8_16_io_deq_valid : _T_2257 ? _Queue64_UInt8_15_io_deq_valid : _T_2256 ? _Queue64_UInt8_14_io_deq_valid : _T_2255 ? _Queue64_UInt8_13_io_deq_valid : _T_2254 ? _Queue64_UInt8_12_io_deq_valid : _T_2253 ? _Queue64_UInt8_11_io_deq_valid : _T_2252 ? _Queue64_UInt8_10_io_deq_valid : _T_2251 ? _Queue64_UInt8_9_io_deq_valid : _T_2250 ? _Queue64_UInt8_8_io_deq_valid : _T_2249 ? _Queue64_UInt8_7_io_deq_valid : _T_2248 ? _Queue64_UInt8_6_io_deq_valid : _T_2247 ? _Queue64_UInt8_5_io_deq_valid : _T_2246 ? _Queue64_UInt8_4_io_deq_valid : _T_2245 ? _Queue64_UInt8_3_io_deq_valid : _T_2244 ? _Queue64_UInt8_2_io_deq_valid : _T_2243 ? _Queue64_UInt8_1_io_deq_valid : _T_2242 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_28 = 9'h3A - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_29 = _remapindex_T_28; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_48 = _remapindex_T_29 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_5 = _GEN_48[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2274 = remapindex_5 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2275 = remapindex_5 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2276 = remapindex_5 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2277 = remapindex_5 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2278 = remapindex_5 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2279 = remapindex_5 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2280 = remapindex_5 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2281 = remapindex_5 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2282 = remapindex_5 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2283 = remapindex_5 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2284 = remapindex_5 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2285 = remapindex_5 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2286 = remapindex_5 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2287 = remapindex_5 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2288 = remapindex_5 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2289 = remapindex_5 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2290 = remapindex_5 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2291 = remapindex_5 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2292 = remapindex_5 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2293 = remapindex_5 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2294 = remapindex_5 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2295 = remapindex_5 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2296 = remapindex_5 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2297 = remapindex_5 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2298 = remapindex_5 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2299 = remapindex_5 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2300 = remapindex_5 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2301 = remapindex_5 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2302 = remapindex_5 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2303 = remapindex_5 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2304 = remapindex_5 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2305 = remapindex_5 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_5 = _T_2305 ? _Queue64_UInt8_31_io_deq_bits : _T_2304 ? _Queue64_UInt8_30_io_deq_bits : _T_2303 ? _Queue64_UInt8_29_io_deq_bits : _T_2302 ? _Queue64_UInt8_28_io_deq_bits : _T_2301 ? _Queue64_UInt8_27_io_deq_bits : _T_2300 ? _Queue64_UInt8_26_io_deq_bits : _T_2299 ? _Queue64_UInt8_25_io_deq_bits : _T_2298 ? _Queue64_UInt8_24_io_deq_bits : _T_2297 ? _Queue64_UInt8_23_io_deq_bits : _T_2296 ? _Queue64_UInt8_22_io_deq_bits : _T_2295 ? _Queue64_UInt8_21_io_deq_bits : _T_2294 ? _Queue64_UInt8_20_io_deq_bits : _T_2293 ? _Queue64_UInt8_19_io_deq_bits : _T_2292 ? _Queue64_UInt8_18_io_deq_bits : _T_2291 ? _Queue64_UInt8_17_io_deq_bits : _T_2290 ? _Queue64_UInt8_16_io_deq_bits : _T_2289 ? _Queue64_UInt8_15_io_deq_bits : _T_2288 ? _Queue64_UInt8_14_io_deq_bits : _T_2287 ? _Queue64_UInt8_13_io_deq_bits : _T_2286 ? _Queue64_UInt8_12_io_deq_bits : _T_2285 ? _Queue64_UInt8_11_io_deq_bits : _T_2284 ? _Queue64_UInt8_10_io_deq_bits : _T_2283 ? _Queue64_UInt8_9_io_deq_bits : _T_2282 ? _Queue64_UInt8_8_io_deq_bits : _T_2281 ? _Queue64_UInt8_7_io_deq_bits : _T_2280 ? _Queue64_UInt8_6_io_deq_bits : _T_2279 ? _Queue64_UInt8_5_io_deq_bits : _T_2278 ? _Queue64_UInt8_4_io_deq_bits : _T_2277 ? _Queue64_UInt8_3_io_deq_bits : _T_2276 ? _Queue64_UInt8_2_io_deq_bits : _T_2275 ? _Queue64_UInt8_1_io_deq_bits : _T_2274 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_5 = _T_2305 ? _Queue64_UInt8_31_io_deq_valid : _T_2304 ? _Queue64_UInt8_30_io_deq_valid : _T_2303 ? _Queue64_UInt8_29_io_deq_valid : _T_2302 ? _Queue64_UInt8_28_io_deq_valid : _T_2301 ? _Queue64_UInt8_27_io_deq_valid : _T_2300 ? _Queue64_UInt8_26_io_deq_valid : _T_2299 ? _Queue64_UInt8_25_io_deq_valid : _T_2298 ? _Queue64_UInt8_24_io_deq_valid : _T_2297 ? _Queue64_UInt8_23_io_deq_valid : _T_2296 ? _Queue64_UInt8_22_io_deq_valid : _T_2295 ? _Queue64_UInt8_21_io_deq_valid : _T_2294 ? _Queue64_UInt8_20_io_deq_valid : _T_2293 ? _Queue64_UInt8_19_io_deq_valid : _T_2292 ? _Queue64_UInt8_18_io_deq_valid : _T_2291 ? _Queue64_UInt8_17_io_deq_valid : _T_2290 ? _Queue64_UInt8_16_io_deq_valid : _T_2289 ? _Queue64_UInt8_15_io_deq_valid : _T_2288 ? _Queue64_UInt8_14_io_deq_valid : _T_2287 ? _Queue64_UInt8_13_io_deq_valid : _T_2286 ? _Queue64_UInt8_12_io_deq_valid : _T_2285 ? _Queue64_UInt8_11_io_deq_valid : _T_2284 ? _Queue64_UInt8_10_io_deq_valid : _T_2283 ? _Queue64_UInt8_9_io_deq_valid : _T_2282 ? _Queue64_UInt8_8_io_deq_valid : _T_2281 ? _Queue64_UInt8_7_io_deq_valid : _T_2280 ? _Queue64_UInt8_6_io_deq_valid : _T_2279 ? _Queue64_UInt8_5_io_deq_valid : _T_2278 ? _Queue64_UInt8_4_io_deq_valid : _T_2277 ? _Queue64_UInt8_3_io_deq_valid : _T_2276 ? _Queue64_UInt8_2_io_deq_valid : _T_2275 ? _Queue64_UInt8_1_io_deq_valid : _T_2274 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_33 = 9'h39 - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_34 = _remapindex_T_33; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_49 = _remapindex_T_34 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_6 = _GEN_49[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2306 = remapindex_6 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2307 = remapindex_6 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2308 = remapindex_6 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2309 = remapindex_6 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2310 = remapindex_6 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2311 = remapindex_6 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2312 = remapindex_6 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2313 = remapindex_6 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2314 = remapindex_6 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2315 = remapindex_6 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2316 = remapindex_6 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2317 = remapindex_6 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2318 = remapindex_6 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2319 = remapindex_6 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2320 = remapindex_6 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2321 = remapindex_6 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2322 = remapindex_6 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2323 = remapindex_6 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2324 = remapindex_6 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2325 = remapindex_6 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2326 = remapindex_6 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2327 = remapindex_6 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2328 = remapindex_6 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2329 = remapindex_6 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2330 = remapindex_6 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2331 = remapindex_6 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2332 = remapindex_6 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2333 = remapindex_6 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2334 = remapindex_6 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2335 = remapindex_6 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2336 = remapindex_6 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2337 = remapindex_6 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_6 = _T_2337 ? _Queue64_UInt8_31_io_deq_bits : _T_2336 ? _Queue64_UInt8_30_io_deq_bits : _T_2335 ? _Queue64_UInt8_29_io_deq_bits : _T_2334 ? _Queue64_UInt8_28_io_deq_bits : _T_2333 ? _Queue64_UInt8_27_io_deq_bits : _T_2332 ? _Queue64_UInt8_26_io_deq_bits : _T_2331 ? _Queue64_UInt8_25_io_deq_bits : _T_2330 ? _Queue64_UInt8_24_io_deq_bits : _T_2329 ? _Queue64_UInt8_23_io_deq_bits : _T_2328 ? _Queue64_UInt8_22_io_deq_bits : _T_2327 ? _Queue64_UInt8_21_io_deq_bits : _T_2326 ? _Queue64_UInt8_20_io_deq_bits : _T_2325 ? _Queue64_UInt8_19_io_deq_bits : _T_2324 ? _Queue64_UInt8_18_io_deq_bits : _T_2323 ? _Queue64_UInt8_17_io_deq_bits : _T_2322 ? _Queue64_UInt8_16_io_deq_bits : _T_2321 ? _Queue64_UInt8_15_io_deq_bits : _T_2320 ? _Queue64_UInt8_14_io_deq_bits : _T_2319 ? _Queue64_UInt8_13_io_deq_bits : _T_2318 ? _Queue64_UInt8_12_io_deq_bits : _T_2317 ? _Queue64_UInt8_11_io_deq_bits : _T_2316 ? _Queue64_UInt8_10_io_deq_bits : _T_2315 ? _Queue64_UInt8_9_io_deq_bits : _T_2314 ? _Queue64_UInt8_8_io_deq_bits : _T_2313 ? _Queue64_UInt8_7_io_deq_bits : _T_2312 ? _Queue64_UInt8_6_io_deq_bits : _T_2311 ? _Queue64_UInt8_5_io_deq_bits : _T_2310 ? _Queue64_UInt8_4_io_deq_bits : _T_2309 ? _Queue64_UInt8_3_io_deq_bits : _T_2308 ? _Queue64_UInt8_2_io_deq_bits : _T_2307 ? _Queue64_UInt8_1_io_deq_bits : _T_2306 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_6 = _T_2337 ? _Queue64_UInt8_31_io_deq_valid : _T_2336 ? _Queue64_UInt8_30_io_deq_valid : _T_2335 ? _Queue64_UInt8_29_io_deq_valid : _T_2334 ? _Queue64_UInt8_28_io_deq_valid : _T_2333 ? _Queue64_UInt8_27_io_deq_valid : _T_2332 ? _Queue64_UInt8_26_io_deq_valid : _T_2331 ? _Queue64_UInt8_25_io_deq_valid : _T_2330 ? _Queue64_UInt8_24_io_deq_valid : _T_2329 ? _Queue64_UInt8_23_io_deq_valid : _T_2328 ? _Queue64_UInt8_22_io_deq_valid : _T_2327 ? _Queue64_UInt8_21_io_deq_valid : _T_2326 ? _Queue64_UInt8_20_io_deq_valid : _T_2325 ? _Queue64_UInt8_19_io_deq_valid : _T_2324 ? _Queue64_UInt8_18_io_deq_valid : _T_2323 ? _Queue64_UInt8_17_io_deq_valid : _T_2322 ? _Queue64_UInt8_16_io_deq_valid : _T_2321 ? _Queue64_UInt8_15_io_deq_valid : _T_2320 ? _Queue64_UInt8_14_io_deq_valid : _T_2319 ? _Queue64_UInt8_13_io_deq_valid : _T_2318 ? _Queue64_UInt8_12_io_deq_valid : _T_2317 ? _Queue64_UInt8_11_io_deq_valid : _T_2316 ? _Queue64_UInt8_10_io_deq_valid : _T_2315 ? _Queue64_UInt8_9_io_deq_valid : _T_2314 ? _Queue64_UInt8_8_io_deq_valid : _T_2313 ? _Queue64_UInt8_7_io_deq_valid : _T_2312 ? _Queue64_UInt8_6_io_deq_valid : _T_2311 ? _Queue64_UInt8_5_io_deq_valid : _T_2310 ? _Queue64_UInt8_4_io_deq_valid : _T_2309 ? _Queue64_UInt8_3_io_deq_valid : _T_2308 ? _Queue64_UInt8_2_io_deq_valid : _T_2307 ? _Queue64_UInt8_1_io_deq_valid : _T_2306 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_38 = 9'h38 - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_39 = _remapindex_T_38; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_50 = _remapindex_T_39 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_7 = _GEN_50[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2338 = remapindex_7 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2339 = remapindex_7 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2340 = remapindex_7 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2341 = remapindex_7 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2342 = remapindex_7 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2343 = remapindex_7 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2344 = remapindex_7 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2345 = remapindex_7 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2346 = remapindex_7 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2347 = remapindex_7 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2348 = remapindex_7 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2349 = remapindex_7 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2350 = remapindex_7 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2351 = remapindex_7 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2352 = remapindex_7 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2353 = remapindex_7 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2354 = remapindex_7 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2355 = remapindex_7 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2356 = remapindex_7 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2357 = remapindex_7 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2358 = remapindex_7 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2359 = remapindex_7 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2360 = remapindex_7 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2361 = remapindex_7 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2362 = remapindex_7 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2363 = remapindex_7 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2364 = remapindex_7 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2365 = remapindex_7 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2366 = remapindex_7 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2367 = remapindex_7 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2368 = remapindex_7 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2369 = remapindex_7 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_7 = _T_2369 ? _Queue64_UInt8_31_io_deq_bits : _T_2368 ? _Queue64_UInt8_30_io_deq_bits : _T_2367 ? _Queue64_UInt8_29_io_deq_bits : _T_2366 ? _Queue64_UInt8_28_io_deq_bits : _T_2365 ? _Queue64_UInt8_27_io_deq_bits : _T_2364 ? _Queue64_UInt8_26_io_deq_bits : _T_2363 ? _Queue64_UInt8_25_io_deq_bits : _T_2362 ? _Queue64_UInt8_24_io_deq_bits : _T_2361 ? _Queue64_UInt8_23_io_deq_bits : _T_2360 ? _Queue64_UInt8_22_io_deq_bits : _T_2359 ? _Queue64_UInt8_21_io_deq_bits : _T_2358 ? _Queue64_UInt8_20_io_deq_bits : _T_2357 ? _Queue64_UInt8_19_io_deq_bits : _T_2356 ? _Queue64_UInt8_18_io_deq_bits : _T_2355 ? _Queue64_UInt8_17_io_deq_bits : _T_2354 ? _Queue64_UInt8_16_io_deq_bits : _T_2353 ? _Queue64_UInt8_15_io_deq_bits : _T_2352 ? _Queue64_UInt8_14_io_deq_bits : _T_2351 ? _Queue64_UInt8_13_io_deq_bits : _T_2350 ? _Queue64_UInt8_12_io_deq_bits : _T_2349 ? _Queue64_UInt8_11_io_deq_bits : _T_2348 ? _Queue64_UInt8_10_io_deq_bits : _T_2347 ? _Queue64_UInt8_9_io_deq_bits : _T_2346 ? _Queue64_UInt8_8_io_deq_bits : _T_2345 ? _Queue64_UInt8_7_io_deq_bits : _T_2344 ? _Queue64_UInt8_6_io_deq_bits : _T_2343 ? _Queue64_UInt8_5_io_deq_bits : _T_2342 ? _Queue64_UInt8_4_io_deq_bits : _T_2341 ? _Queue64_UInt8_3_io_deq_bits : _T_2340 ? _Queue64_UInt8_2_io_deq_bits : _T_2339 ? _Queue64_UInt8_1_io_deq_bits : _T_2338 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_7 = _T_2369 ? _Queue64_UInt8_31_io_deq_valid : _T_2368 ? _Queue64_UInt8_30_io_deq_valid : _T_2367 ? _Queue64_UInt8_29_io_deq_valid : _T_2366 ? _Queue64_UInt8_28_io_deq_valid : _T_2365 ? _Queue64_UInt8_27_io_deq_valid : _T_2364 ? _Queue64_UInt8_26_io_deq_valid : _T_2363 ? _Queue64_UInt8_25_io_deq_valid : _T_2362 ? _Queue64_UInt8_24_io_deq_valid : _T_2361 ? _Queue64_UInt8_23_io_deq_valid : _T_2360 ? _Queue64_UInt8_22_io_deq_valid : _T_2359 ? _Queue64_UInt8_21_io_deq_valid : _T_2358 ? _Queue64_UInt8_20_io_deq_valid : _T_2357 ? _Queue64_UInt8_19_io_deq_valid : _T_2356 ? _Queue64_UInt8_18_io_deq_valid : _T_2355 ? _Queue64_UInt8_17_io_deq_valid : _T_2354 ? _Queue64_UInt8_16_io_deq_valid : _T_2353 ? _Queue64_UInt8_15_io_deq_valid : _T_2352 ? _Queue64_UInt8_14_io_deq_valid : _T_2351 ? _Queue64_UInt8_13_io_deq_valid : _T_2350 ? _Queue64_UInt8_12_io_deq_valid : _T_2349 ? _Queue64_UInt8_11_io_deq_valid : _T_2348 ? _Queue64_UInt8_10_io_deq_valid : _T_2347 ? _Queue64_UInt8_9_io_deq_valid : _T_2346 ? _Queue64_UInt8_8_io_deq_valid : _T_2345 ? _Queue64_UInt8_7_io_deq_valid : _T_2344 ? _Queue64_UInt8_6_io_deq_valid : _T_2343 ? _Queue64_UInt8_5_io_deq_valid : _T_2342 ? _Queue64_UInt8_4_io_deq_valid : _T_2341 ? _Queue64_UInt8_3_io_deq_valid : _T_2340 ? _Queue64_UInt8_2_io_deq_valid : _T_2339 ? _Queue64_UInt8_1_io_deq_valid : _T_2338 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_43 = 9'h37 - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_44 = _remapindex_T_43; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_51 = _remapindex_T_44 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_8 = _GEN_51[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2370 = remapindex_8 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2371 = remapindex_8 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2372 = remapindex_8 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2373 = remapindex_8 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2374 = remapindex_8 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2375 = remapindex_8 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2376 = remapindex_8 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2377 = remapindex_8 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2378 = remapindex_8 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2379 = remapindex_8 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2380 = remapindex_8 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2381 = remapindex_8 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2382 = remapindex_8 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2383 = remapindex_8 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2384 = remapindex_8 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2385 = remapindex_8 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2386 = remapindex_8 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2387 = remapindex_8 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2388 = remapindex_8 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2389 = remapindex_8 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2390 = remapindex_8 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2391 = remapindex_8 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2392 = remapindex_8 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2393 = remapindex_8 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2394 = remapindex_8 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2395 = remapindex_8 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2396 = remapindex_8 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2397 = remapindex_8 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2398 = remapindex_8 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2399 = remapindex_8 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2400 = remapindex_8 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2401 = remapindex_8 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_8 = _T_2401 ? _Queue64_UInt8_31_io_deq_bits : _T_2400 ? _Queue64_UInt8_30_io_deq_bits : _T_2399 ? _Queue64_UInt8_29_io_deq_bits : _T_2398 ? _Queue64_UInt8_28_io_deq_bits : _T_2397 ? _Queue64_UInt8_27_io_deq_bits : _T_2396 ? _Queue64_UInt8_26_io_deq_bits : _T_2395 ? _Queue64_UInt8_25_io_deq_bits : _T_2394 ? _Queue64_UInt8_24_io_deq_bits : _T_2393 ? _Queue64_UInt8_23_io_deq_bits : _T_2392 ? _Queue64_UInt8_22_io_deq_bits : _T_2391 ? _Queue64_UInt8_21_io_deq_bits : _T_2390 ? _Queue64_UInt8_20_io_deq_bits : _T_2389 ? _Queue64_UInt8_19_io_deq_bits : _T_2388 ? _Queue64_UInt8_18_io_deq_bits : _T_2387 ? _Queue64_UInt8_17_io_deq_bits : _T_2386 ? _Queue64_UInt8_16_io_deq_bits : _T_2385 ? _Queue64_UInt8_15_io_deq_bits : _T_2384 ? _Queue64_UInt8_14_io_deq_bits : _T_2383 ? _Queue64_UInt8_13_io_deq_bits : _T_2382 ? _Queue64_UInt8_12_io_deq_bits : _T_2381 ? _Queue64_UInt8_11_io_deq_bits : _T_2380 ? _Queue64_UInt8_10_io_deq_bits : _T_2379 ? _Queue64_UInt8_9_io_deq_bits : _T_2378 ? _Queue64_UInt8_8_io_deq_bits : _T_2377 ? _Queue64_UInt8_7_io_deq_bits : _T_2376 ? _Queue64_UInt8_6_io_deq_bits : _T_2375 ? _Queue64_UInt8_5_io_deq_bits : _T_2374 ? _Queue64_UInt8_4_io_deq_bits : _T_2373 ? _Queue64_UInt8_3_io_deq_bits : _T_2372 ? _Queue64_UInt8_2_io_deq_bits : _T_2371 ? _Queue64_UInt8_1_io_deq_bits : _T_2370 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_8 = _T_2401 ? _Queue64_UInt8_31_io_deq_valid : _T_2400 ? _Queue64_UInt8_30_io_deq_valid : _T_2399 ? _Queue64_UInt8_29_io_deq_valid : _T_2398 ? _Queue64_UInt8_28_io_deq_valid : _T_2397 ? _Queue64_UInt8_27_io_deq_valid : _T_2396 ? _Queue64_UInt8_26_io_deq_valid : _T_2395 ? _Queue64_UInt8_25_io_deq_valid : _T_2394 ? _Queue64_UInt8_24_io_deq_valid : _T_2393 ? _Queue64_UInt8_23_io_deq_valid : _T_2392 ? _Queue64_UInt8_22_io_deq_valid : _T_2391 ? _Queue64_UInt8_21_io_deq_valid : _T_2390 ? _Queue64_UInt8_20_io_deq_valid : _T_2389 ? _Queue64_UInt8_19_io_deq_valid : _T_2388 ? _Queue64_UInt8_18_io_deq_valid : _T_2387 ? _Queue64_UInt8_17_io_deq_valid : _T_2386 ? _Queue64_UInt8_16_io_deq_valid : _T_2385 ? _Queue64_UInt8_15_io_deq_valid : _T_2384 ? _Queue64_UInt8_14_io_deq_valid : _T_2383 ? _Queue64_UInt8_13_io_deq_valid : _T_2382 ? _Queue64_UInt8_12_io_deq_valid : _T_2381 ? _Queue64_UInt8_11_io_deq_valid : _T_2380 ? _Queue64_UInt8_10_io_deq_valid : _T_2379 ? _Queue64_UInt8_9_io_deq_valid : _T_2378 ? _Queue64_UInt8_8_io_deq_valid : _T_2377 ? _Queue64_UInt8_7_io_deq_valid : _T_2376 ? _Queue64_UInt8_6_io_deq_valid : _T_2375 ? _Queue64_UInt8_5_io_deq_valid : _T_2374 ? _Queue64_UInt8_4_io_deq_valid : _T_2373 ? _Queue64_UInt8_3_io_deq_valid : _T_2372 ? _Queue64_UInt8_2_io_deq_valid : _T_2371 ? _Queue64_UInt8_1_io_deq_valid : _T_2370 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_48 = 9'h36 - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_49 = _remapindex_T_48; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_52 = _remapindex_T_49 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_9 = _GEN_52[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2402 = remapindex_9 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2403 = remapindex_9 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2404 = remapindex_9 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2405 = remapindex_9 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2406 = remapindex_9 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2407 = remapindex_9 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2408 = remapindex_9 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2409 = remapindex_9 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2410 = remapindex_9 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2411 = remapindex_9 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2412 = remapindex_9 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2413 = remapindex_9 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2414 = remapindex_9 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2415 = remapindex_9 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2416 = remapindex_9 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2417 = remapindex_9 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2418 = remapindex_9 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2419 = remapindex_9 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2420 = remapindex_9 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2421 = remapindex_9 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2422 = remapindex_9 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2423 = remapindex_9 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2424 = remapindex_9 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2425 = remapindex_9 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2426 = remapindex_9 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2427 = remapindex_9 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2428 = remapindex_9 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2429 = remapindex_9 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2430 = remapindex_9 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2431 = remapindex_9 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2432 = remapindex_9 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2433 = remapindex_9 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_9 = _T_2433 ? _Queue64_UInt8_31_io_deq_bits : _T_2432 ? _Queue64_UInt8_30_io_deq_bits : _T_2431 ? _Queue64_UInt8_29_io_deq_bits : _T_2430 ? _Queue64_UInt8_28_io_deq_bits : _T_2429 ? _Queue64_UInt8_27_io_deq_bits : _T_2428 ? _Queue64_UInt8_26_io_deq_bits : _T_2427 ? _Queue64_UInt8_25_io_deq_bits : _T_2426 ? _Queue64_UInt8_24_io_deq_bits : _T_2425 ? _Queue64_UInt8_23_io_deq_bits : _T_2424 ? _Queue64_UInt8_22_io_deq_bits : _T_2423 ? _Queue64_UInt8_21_io_deq_bits : _T_2422 ? _Queue64_UInt8_20_io_deq_bits : _T_2421 ? _Queue64_UInt8_19_io_deq_bits : _T_2420 ? _Queue64_UInt8_18_io_deq_bits : _T_2419 ? _Queue64_UInt8_17_io_deq_bits : _T_2418 ? _Queue64_UInt8_16_io_deq_bits : _T_2417 ? _Queue64_UInt8_15_io_deq_bits : _T_2416 ? _Queue64_UInt8_14_io_deq_bits : _T_2415 ? _Queue64_UInt8_13_io_deq_bits : _T_2414 ? _Queue64_UInt8_12_io_deq_bits : _T_2413 ? _Queue64_UInt8_11_io_deq_bits : _T_2412 ? _Queue64_UInt8_10_io_deq_bits : _T_2411 ? _Queue64_UInt8_9_io_deq_bits : _T_2410 ? _Queue64_UInt8_8_io_deq_bits : _T_2409 ? _Queue64_UInt8_7_io_deq_bits : _T_2408 ? _Queue64_UInt8_6_io_deq_bits : _T_2407 ? _Queue64_UInt8_5_io_deq_bits : _T_2406 ? _Queue64_UInt8_4_io_deq_bits : _T_2405 ? _Queue64_UInt8_3_io_deq_bits : _T_2404 ? _Queue64_UInt8_2_io_deq_bits : _T_2403 ? _Queue64_UInt8_1_io_deq_bits : _T_2402 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_9 = _T_2433 ? _Queue64_UInt8_31_io_deq_valid : _T_2432 ? _Queue64_UInt8_30_io_deq_valid : _T_2431 ? _Queue64_UInt8_29_io_deq_valid : _T_2430 ? _Queue64_UInt8_28_io_deq_valid : _T_2429 ? _Queue64_UInt8_27_io_deq_valid : _T_2428 ? _Queue64_UInt8_26_io_deq_valid : _T_2427 ? _Queue64_UInt8_25_io_deq_valid : _T_2426 ? _Queue64_UInt8_24_io_deq_valid : _T_2425 ? _Queue64_UInt8_23_io_deq_valid : _T_2424 ? _Queue64_UInt8_22_io_deq_valid : _T_2423 ? _Queue64_UInt8_21_io_deq_valid : _T_2422 ? _Queue64_UInt8_20_io_deq_valid : _T_2421 ? _Queue64_UInt8_19_io_deq_valid : _T_2420 ? _Queue64_UInt8_18_io_deq_valid : _T_2419 ? _Queue64_UInt8_17_io_deq_valid : _T_2418 ? _Queue64_UInt8_16_io_deq_valid : _T_2417 ? _Queue64_UInt8_15_io_deq_valid : _T_2416 ? _Queue64_UInt8_14_io_deq_valid : _T_2415 ? _Queue64_UInt8_13_io_deq_valid : _T_2414 ? _Queue64_UInt8_12_io_deq_valid : _T_2413 ? _Queue64_UInt8_11_io_deq_valid : _T_2412 ? _Queue64_UInt8_10_io_deq_valid : _T_2411 ? _Queue64_UInt8_9_io_deq_valid : _T_2410 ? _Queue64_UInt8_8_io_deq_valid : _T_2409 ? _Queue64_UInt8_7_io_deq_valid : _T_2408 ? _Queue64_UInt8_6_io_deq_valid : _T_2407 ? _Queue64_UInt8_5_io_deq_valid : _T_2406 ? _Queue64_UInt8_4_io_deq_valid : _T_2405 ? _Queue64_UInt8_3_io_deq_valid : _T_2404 ? _Queue64_UInt8_2_io_deq_valid : _T_2403 ? _Queue64_UInt8_1_io_deq_valid : _T_2402 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_53 = 9'h35 - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_54 = _remapindex_T_53; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_53 = _remapindex_T_54 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_10 = _GEN_53[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2434 = remapindex_10 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2435 = remapindex_10 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2436 = remapindex_10 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2437 = remapindex_10 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2438 = remapindex_10 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2439 = remapindex_10 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2440 = remapindex_10 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2441 = remapindex_10 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2442 = remapindex_10 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2443 = remapindex_10 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2444 = remapindex_10 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2445 = remapindex_10 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2446 = remapindex_10 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2447 = remapindex_10 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2448 = remapindex_10 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2449 = remapindex_10 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2450 = remapindex_10 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2451 = remapindex_10 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2452 = remapindex_10 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2453 = remapindex_10 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2454 = remapindex_10 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2455 = remapindex_10 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2456 = remapindex_10 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2457 = remapindex_10 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2458 = remapindex_10 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2459 = remapindex_10 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2460 = remapindex_10 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2461 = remapindex_10 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2462 = remapindex_10 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2463 = remapindex_10 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2464 = remapindex_10 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2465 = remapindex_10 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_10 = _T_2465 ? _Queue64_UInt8_31_io_deq_bits : _T_2464 ? _Queue64_UInt8_30_io_deq_bits : _T_2463 ? _Queue64_UInt8_29_io_deq_bits : _T_2462 ? _Queue64_UInt8_28_io_deq_bits : _T_2461 ? _Queue64_UInt8_27_io_deq_bits : _T_2460 ? _Queue64_UInt8_26_io_deq_bits : _T_2459 ? _Queue64_UInt8_25_io_deq_bits : _T_2458 ? _Queue64_UInt8_24_io_deq_bits : _T_2457 ? _Queue64_UInt8_23_io_deq_bits : _T_2456 ? _Queue64_UInt8_22_io_deq_bits : _T_2455 ? _Queue64_UInt8_21_io_deq_bits : _T_2454 ? _Queue64_UInt8_20_io_deq_bits : _T_2453 ? _Queue64_UInt8_19_io_deq_bits : _T_2452 ? _Queue64_UInt8_18_io_deq_bits : _T_2451 ? _Queue64_UInt8_17_io_deq_bits : _T_2450 ? _Queue64_UInt8_16_io_deq_bits : _T_2449 ? _Queue64_UInt8_15_io_deq_bits : _T_2448 ? _Queue64_UInt8_14_io_deq_bits : _T_2447 ? _Queue64_UInt8_13_io_deq_bits : _T_2446 ? _Queue64_UInt8_12_io_deq_bits : _T_2445 ? _Queue64_UInt8_11_io_deq_bits : _T_2444 ? _Queue64_UInt8_10_io_deq_bits : _T_2443 ? _Queue64_UInt8_9_io_deq_bits : _T_2442 ? _Queue64_UInt8_8_io_deq_bits : _T_2441 ? _Queue64_UInt8_7_io_deq_bits : _T_2440 ? _Queue64_UInt8_6_io_deq_bits : _T_2439 ? _Queue64_UInt8_5_io_deq_bits : _T_2438 ? _Queue64_UInt8_4_io_deq_bits : _T_2437 ? _Queue64_UInt8_3_io_deq_bits : _T_2436 ? _Queue64_UInt8_2_io_deq_bits : _T_2435 ? _Queue64_UInt8_1_io_deq_bits : _T_2434 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_10 = _T_2465 ? _Queue64_UInt8_31_io_deq_valid : _T_2464 ? _Queue64_UInt8_30_io_deq_valid : _T_2463 ? _Queue64_UInt8_29_io_deq_valid : _T_2462 ? _Queue64_UInt8_28_io_deq_valid : _T_2461 ? _Queue64_UInt8_27_io_deq_valid : _T_2460 ? _Queue64_UInt8_26_io_deq_valid : _T_2459 ? _Queue64_UInt8_25_io_deq_valid : _T_2458 ? _Queue64_UInt8_24_io_deq_valid : _T_2457 ? _Queue64_UInt8_23_io_deq_valid : _T_2456 ? _Queue64_UInt8_22_io_deq_valid : _T_2455 ? _Queue64_UInt8_21_io_deq_valid : _T_2454 ? _Queue64_UInt8_20_io_deq_valid : _T_2453 ? _Queue64_UInt8_19_io_deq_valid : _T_2452 ? _Queue64_UInt8_18_io_deq_valid : _T_2451 ? _Queue64_UInt8_17_io_deq_valid : _T_2450 ? _Queue64_UInt8_16_io_deq_valid : _T_2449 ? _Queue64_UInt8_15_io_deq_valid : _T_2448 ? _Queue64_UInt8_14_io_deq_valid : _T_2447 ? _Queue64_UInt8_13_io_deq_valid : _T_2446 ? _Queue64_UInt8_12_io_deq_valid : _T_2445 ? _Queue64_UInt8_11_io_deq_valid : _T_2444 ? _Queue64_UInt8_10_io_deq_valid : _T_2443 ? _Queue64_UInt8_9_io_deq_valid : _T_2442 ? _Queue64_UInt8_8_io_deq_valid : _T_2441 ? _Queue64_UInt8_7_io_deq_valid : _T_2440 ? _Queue64_UInt8_6_io_deq_valid : _T_2439 ? _Queue64_UInt8_5_io_deq_valid : _T_2438 ? _Queue64_UInt8_4_io_deq_valid : _T_2437 ? _Queue64_UInt8_3_io_deq_valid : _T_2436 ? _Queue64_UInt8_2_io_deq_valid : _T_2435 ? _Queue64_UInt8_1_io_deq_valid : _T_2434 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_58 = 9'h34 - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_59 = _remapindex_T_58; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_54 = _remapindex_T_59 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_11 = _GEN_54[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2466 = remapindex_11 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2467 = remapindex_11 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2468 = remapindex_11 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2469 = remapindex_11 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2470 = remapindex_11 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2471 = remapindex_11 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2472 = remapindex_11 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2473 = remapindex_11 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2474 = remapindex_11 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2475 = remapindex_11 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2476 = remapindex_11 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2477 = remapindex_11 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2478 = remapindex_11 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2479 = remapindex_11 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2480 = remapindex_11 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2481 = remapindex_11 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2482 = remapindex_11 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2483 = remapindex_11 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2484 = remapindex_11 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2485 = remapindex_11 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2486 = remapindex_11 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2487 = remapindex_11 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2488 = remapindex_11 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2489 = remapindex_11 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2490 = remapindex_11 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2491 = remapindex_11 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2492 = remapindex_11 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2493 = remapindex_11 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2494 = remapindex_11 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2495 = remapindex_11 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2496 = remapindex_11 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2497 = remapindex_11 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_11 = _T_2497 ? _Queue64_UInt8_31_io_deq_bits : _T_2496 ? _Queue64_UInt8_30_io_deq_bits : _T_2495 ? _Queue64_UInt8_29_io_deq_bits : _T_2494 ? _Queue64_UInt8_28_io_deq_bits : _T_2493 ? _Queue64_UInt8_27_io_deq_bits : _T_2492 ? _Queue64_UInt8_26_io_deq_bits : _T_2491 ? _Queue64_UInt8_25_io_deq_bits : _T_2490 ? _Queue64_UInt8_24_io_deq_bits : _T_2489 ? _Queue64_UInt8_23_io_deq_bits : _T_2488 ? _Queue64_UInt8_22_io_deq_bits : _T_2487 ? _Queue64_UInt8_21_io_deq_bits : _T_2486 ? _Queue64_UInt8_20_io_deq_bits : _T_2485 ? _Queue64_UInt8_19_io_deq_bits : _T_2484 ? _Queue64_UInt8_18_io_deq_bits : _T_2483 ? _Queue64_UInt8_17_io_deq_bits : _T_2482 ? _Queue64_UInt8_16_io_deq_bits : _T_2481 ? _Queue64_UInt8_15_io_deq_bits : _T_2480 ? _Queue64_UInt8_14_io_deq_bits : _T_2479 ? _Queue64_UInt8_13_io_deq_bits : _T_2478 ? _Queue64_UInt8_12_io_deq_bits : _T_2477 ? _Queue64_UInt8_11_io_deq_bits : _T_2476 ? _Queue64_UInt8_10_io_deq_bits : _T_2475 ? _Queue64_UInt8_9_io_deq_bits : _T_2474 ? _Queue64_UInt8_8_io_deq_bits : _T_2473 ? _Queue64_UInt8_7_io_deq_bits : _T_2472 ? _Queue64_UInt8_6_io_deq_bits : _T_2471 ? _Queue64_UInt8_5_io_deq_bits : _T_2470 ? _Queue64_UInt8_4_io_deq_bits : _T_2469 ? _Queue64_UInt8_3_io_deq_bits : _T_2468 ? _Queue64_UInt8_2_io_deq_bits : _T_2467 ? _Queue64_UInt8_1_io_deq_bits : _T_2466 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_11 = _T_2497 ? _Queue64_UInt8_31_io_deq_valid : _T_2496 ? _Queue64_UInt8_30_io_deq_valid : _T_2495 ? _Queue64_UInt8_29_io_deq_valid : _T_2494 ? _Queue64_UInt8_28_io_deq_valid : _T_2493 ? _Queue64_UInt8_27_io_deq_valid : _T_2492 ? _Queue64_UInt8_26_io_deq_valid : _T_2491 ? _Queue64_UInt8_25_io_deq_valid : _T_2490 ? _Queue64_UInt8_24_io_deq_valid : _T_2489 ? _Queue64_UInt8_23_io_deq_valid : _T_2488 ? _Queue64_UInt8_22_io_deq_valid : _T_2487 ? _Queue64_UInt8_21_io_deq_valid : _T_2486 ? _Queue64_UInt8_20_io_deq_valid : _T_2485 ? _Queue64_UInt8_19_io_deq_valid : _T_2484 ? _Queue64_UInt8_18_io_deq_valid : _T_2483 ? _Queue64_UInt8_17_io_deq_valid : _T_2482 ? _Queue64_UInt8_16_io_deq_valid : _T_2481 ? _Queue64_UInt8_15_io_deq_valid : _T_2480 ? _Queue64_UInt8_14_io_deq_valid : _T_2479 ? _Queue64_UInt8_13_io_deq_valid : _T_2478 ? _Queue64_UInt8_12_io_deq_valid : _T_2477 ? _Queue64_UInt8_11_io_deq_valid : _T_2476 ? _Queue64_UInt8_10_io_deq_valid : _T_2475 ? _Queue64_UInt8_9_io_deq_valid : _T_2474 ? _Queue64_UInt8_8_io_deq_valid : _T_2473 ? _Queue64_UInt8_7_io_deq_valid : _T_2472 ? _Queue64_UInt8_6_io_deq_valid : _T_2471 ? _Queue64_UInt8_5_io_deq_valid : _T_2470 ? _Queue64_UInt8_4_io_deq_valid : _T_2469 ? _Queue64_UInt8_3_io_deq_valid : _T_2468 ? _Queue64_UInt8_2_io_deq_valid : _T_2467 ? _Queue64_UInt8_1_io_deq_valid : _T_2466 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_63 = 9'h33 - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_64 = _remapindex_T_63; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_55 = _remapindex_T_64 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_12 = _GEN_55[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2498 = remapindex_12 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2499 = remapindex_12 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2500 = remapindex_12 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2501 = remapindex_12 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2502 = remapindex_12 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2503 = remapindex_12 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2504 = remapindex_12 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2505 = remapindex_12 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2506 = remapindex_12 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2507 = remapindex_12 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2508 = remapindex_12 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2509 = remapindex_12 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2510 = remapindex_12 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2511 = remapindex_12 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2512 = remapindex_12 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2513 = remapindex_12 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2514 = remapindex_12 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2515 = remapindex_12 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2516 = remapindex_12 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2517 = remapindex_12 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2518 = remapindex_12 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2519 = remapindex_12 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2520 = remapindex_12 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2521 = remapindex_12 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2522 = remapindex_12 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2523 = remapindex_12 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2524 = remapindex_12 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2525 = remapindex_12 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2526 = remapindex_12 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2527 = remapindex_12 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2528 = remapindex_12 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2529 = remapindex_12 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_12 = _T_2529 ? _Queue64_UInt8_31_io_deq_bits : _T_2528 ? _Queue64_UInt8_30_io_deq_bits : _T_2527 ? _Queue64_UInt8_29_io_deq_bits : _T_2526 ? _Queue64_UInt8_28_io_deq_bits : _T_2525 ? _Queue64_UInt8_27_io_deq_bits : _T_2524 ? _Queue64_UInt8_26_io_deq_bits : _T_2523 ? _Queue64_UInt8_25_io_deq_bits : _T_2522 ? _Queue64_UInt8_24_io_deq_bits : _T_2521 ? _Queue64_UInt8_23_io_deq_bits : _T_2520 ? _Queue64_UInt8_22_io_deq_bits : _T_2519 ? _Queue64_UInt8_21_io_deq_bits : _T_2518 ? _Queue64_UInt8_20_io_deq_bits : _T_2517 ? _Queue64_UInt8_19_io_deq_bits : _T_2516 ? _Queue64_UInt8_18_io_deq_bits : _T_2515 ? _Queue64_UInt8_17_io_deq_bits : _T_2514 ? _Queue64_UInt8_16_io_deq_bits : _T_2513 ? _Queue64_UInt8_15_io_deq_bits : _T_2512 ? _Queue64_UInt8_14_io_deq_bits : _T_2511 ? _Queue64_UInt8_13_io_deq_bits : _T_2510 ? _Queue64_UInt8_12_io_deq_bits : _T_2509 ? _Queue64_UInt8_11_io_deq_bits : _T_2508 ? _Queue64_UInt8_10_io_deq_bits : _T_2507 ? _Queue64_UInt8_9_io_deq_bits : _T_2506 ? _Queue64_UInt8_8_io_deq_bits : _T_2505 ? _Queue64_UInt8_7_io_deq_bits : _T_2504 ? _Queue64_UInt8_6_io_deq_bits : _T_2503 ? _Queue64_UInt8_5_io_deq_bits : _T_2502 ? _Queue64_UInt8_4_io_deq_bits : _T_2501 ? _Queue64_UInt8_3_io_deq_bits : _T_2500 ? _Queue64_UInt8_2_io_deq_bits : _T_2499 ? _Queue64_UInt8_1_io_deq_bits : _T_2498 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_12 = _T_2529 ? _Queue64_UInt8_31_io_deq_valid : _T_2528 ? _Queue64_UInt8_30_io_deq_valid : _T_2527 ? _Queue64_UInt8_29_io_deq_valid : _T_2526 ? _Queue64_UInt8_28_io_deq_valid : _T_2525 ? _Queue64_UInt8_27_io_deq_valid : _T_2524 ? _Queue64_UInt8_26_io_deq_valid : _T_2523 ? _Queue64_UInt8_25_io_deq_valid : _T_2522 ? _Queue64_UInt8_24_io_deq_valid : _T_2521 ? _Queue64_UInt8_23_io_deq_valid : _T_2520 ? _Queue64_UInt8_22_io_deq_valid : _T_2519 ? _Queue64_UInt8_21_io_deq_valid : _T_2518 ? _Queue64_UInt8_20_io_deq_valid : _T_2517 ? _Queue64_UInt8_19_io_deq_valid : _T_2516 ? _Queue64_UInt8_18_io_deq_valid : _T_2515 ? _Queue64_UInt8_17_io_deq_valid : _T_2514 ? _Queue64_UInt8_16_io_deq_valid : _T_2513 ? _Queue64_UInt8_15_io_deq_valid : _T_2512 ? _Queue64_UInt8_14_io_deq_valid : _T_2511 ? _Queue64_UInt8_13_io_deq_valid : _T_2510 ? _Queue64_UInt8_12_io_deq_valid : _T_2509 ? _Queue64_UInt8_11_io_deq_valid : _T_2508 ? _Queue64_UInt8_10_io_deq_valid : _T_2507 ? _Queue64_UInt8_9_io_deq_valid : _T_2506 ? _Queue64_UInt8_8_io_deq_valid : _T_2505 ? _Queue64_UInt8_7_io_deq_valid : _T_2504 ? _Queue64_UInt8_6_io_deq_valid : _T_2503 ? _Queue64_UInt8_5_io_deq_valid : _T_2502 ? _Queue64_UInt8_4_io_deq_valid : _T_2501 ? _Queue64_UInt8_3_io_deq_valid : _T_2500 ? _Queue64_UInt8_2_io_deq_valid : _T_2499 ? _Queue64_UInt8_1_io_deq_valid : _T_2498 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_68 = 9'h32 - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_69 = _remapindex_T_68; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_56 = _remapindex_T_69 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_13 = _GEN_56[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2530 = remapindex_13 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2531 = remapindex_13 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2532 = remapindex_13 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2533 = remapindex_13 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2534 = remapindex_13 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2535 = remapindex_13 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2536 = remapindex_13 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2537 = remapindex_13 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2538 = remapindex_13 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2539 = remapindex_13 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2540 = remapindex_13 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2541 = remapindex_13 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2542 = remapindex_13 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2543 = remapindex_13 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2544 = remapindex_13 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2545 = remapindex_13 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2546 = remapindex_13 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2547 = remapindex_13 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2548 = remapindex_13 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2549 = remapindex_13 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2550 = remapindex_13 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2551 = remapindex_13 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2552 = remapindex_13 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2553 = remapindex_13 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2554 = remapindex_13 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2555 = remapindex_13 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2556 = remapindex_13 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2557 = remapindex_13 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2558 = remapindex_13 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2559 = remapindex_13 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2560 = remapindex_13 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2561 = remapindex_13 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_13 = _T_2561 ? _Queue64_UInt8_31_io_deq_bits : _T_2560 ? _Queue64_UInt8_30_io_deq_bits : _T_2559 ? _Queue64_UInt8_29_io_deq_bits : _T_2558 ? _Queue64_UInt8_28_io_deq_bits : _T_2557 ? _Queue64_UInt8_27_io_deq_bits : _T_2556 ? _Queue64_UInt8_26_io_deq_bits : _T_2555 ? _Queue64_UInt8_25_io_deq_bits : _T_2554 ? _Queue64_UInt8_24_io_deq_bits : _T_2553 ? _Queue64_UInt8_23_io_deq_bits : _T_2552 ? _Queue64_UInt8_22_io_deq_bits : _T_2551 ? _Queue64_UInt8_21_io_deq_bits : _T_2550 ? _Queue64_UInt8_20_io_deq_bits : _T_2549 ? _Queue64_UInt8_19_io_deq_bits : _T_2548 ? _Queue64_UInt8_18_io_deq_bits : _T_2547 ? _Queue64_UInt8_17_io_deq_bits : _T_2546 ? _Queue64_UInt8_16_io_deq_bits : _T_2545 ? _Queue64_UInt8_15_io_deq_bits : _T_2544 ? _Queue64_UInt8_14_io_deq_bits : _T_2543 ? _Queue64_UInt8_13_io_deq_bits : _T_2542 ? _Queue64_UInt8_12_io_deq_bits : _T_2541 ? _Queue64_UInt8_11_io_deq_bits : _T_2540 ? _Queue64_UInt8_10_io_deq_bits : _T_2539 ? _Queue64_UInt8_9_io_deq_bits : _T_2538 ? _Queue64_UInt8_8_io_deq_bits : _T_2537 ? _Queue64_UInt8_7_io_deq_bits : _T_2536 ? _Queue64_UInt8_6_io_deq_bits : _T_2535 ? _Queue64_UInt8_5_io_deq_bits : _T_2534 ? _Queue64_UInt8_4_io_deq_bits : _T_2533 ? _Queue64_UInt8_3_io_deq_bits : _T_2532 ? _Queue64_UInt8_2_io_deq_bits : _T_2531 ? _Queue64_UInt8_1_io_deq_bits : _T_2530 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_13 = _T_2561 ? _Queue64_UInt8_31_io_deq_valid : _T_2560 ? _Queue64_UInt8_30_io_deq_valid : _T_2559 ? _Queue64_UInt8_29_io_deq_valid : _T_2558 ? _Queue64_UInt8_28_io_deq_valid : _T_2557 ? _Queue64_UInt8_27_io_deq_valid : _T_2556 ? _Queue64_UInt8_26_io_deq_valid : _T_2555 ? _Queue64_UInt8_25_io_deq_valid : _T_2554 ? _Queue64_UInt8_24_io_deq_valid : _T_2553 ? _Queue64_UInt8_23_io_deq_valid : _T_2552 ? _Queue64_UInt8_22_io_deq_valid : _T_2551 ? _Queue64_UInt8_21_io_deq_valid : _T_2550 ? _Queue64_UInt8_20_io_deq_valid : _T_2549 ? _Queue64_UInt8_19_io_deq_valid : _T_2548 ? _Queue64_UInt8_18_io_deq_valid : _T_2547 ? _Queue64_UInt8_17_io_deq_valid : _T_2546 ? _Queue64_UInt8_16_io_deq_valid : _T_2545 ? _Queue64_UInt8_15_io_deq_valid : _T_2544 ? _Queue64_UInt8_14_io_deq_valid : _T_2543 ? _Queue64_UInt8_13_io_deq_valid : _T_2542 ? _Queue64_UInt8_12_io_deq_valid : _T_2541 ? _Queue64_UInt8_11_io_deq_valid : _T_2540 ? _Queue64_UInt8_10_io_deq_valid : _T_2539 ? _Queue64_UInt8_9_io_deq_valid : _T_2538 ? _Queue64_UInt8_8_io_deq_valid : _T_2537 ? _Queue64_UInt8_7_io_deq_valid : _T_2536 ? _Queue64_UInt8_6_io_deq_valid : _T_2535 ? _Queue64_UInt8_5_io_deq_valid : _T_2534 ? _Queue64_UInt8_4_io_deq_valid : _T_2533 ? _Queue64_UInt8_3_io_deq_valid : _T_2532 ? _Queue64_UInt8_2_io_deq_valid : _T_2531 ? _Queue64_UInt8_1_io_deq_valid : _T_2530 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_73 = 9'h31 - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_74 = _remapindex_T_73; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_57 = _remapindex_T_74 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_14 = _GEN_57[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2562 = remapindex_14 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2563 = remapindex_14 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2564 = remapindex_14 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2565 = remapindex_14 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2566 = remapindex_14 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2567 = remapindex_14 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2568 = remapindex_14 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2569 = remapindex_14 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2570 = remapindex_14 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2571 = remapindex_14 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2572 = remapindex_14 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2573 = remapindex_14 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2574 = remapindex_14 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2575 = remapindex_14 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2576 = remapindex_14 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2577 = remapindex_14 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2578 = remapindex_14 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2579 = remapindex_14 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2580 = remapindex_14 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2581 = remapindex_14 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2582 = remapindex_14 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2583 = remapindex_14 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2584 = remapindex_14 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2585 = remapindex_14 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2586 = remapindex_14 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2587 = remapindex_14 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2588 = remapindex_14 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2589 = remapindex_14 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2590 = remapindex_14 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2591 = remapindex_14 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2592 = remapindex_14 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2593 = remapindex_14 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_14 = _T_2593 ? _Queue64_UInt8_31_io_deq_bits : _T_2592 ? _Queue64_UInt8_30_io_deq_bits : _T_2591 ? _Queue64_UInt8_29_io_deq_bits : _T_2590 ? _Queue64_UInt8_28_io_deq_bits : _T_2589 ? _Queue64_UInt8_27_io_deq_bits : _T_2588 ? _Queue64_UInt8_26_io_deq_bits : _T_2587 ? _Queue64_UInt8_25_io_deq_bits : _T_2586 ? _Queue64_UInt8_24_io_deq_bits : _T_2585 ? _Queue64_UInt8_23_io_deq_bits : _T_2584 ? _Queue64_UInt8_22_io_deq_bits : _T_2583 ? _Queue64_UInt8_21_io_deq_bits : _T_2582 ? _Queue64_UInt8_20_io_deq_bits : _T_2581 ? _Queue64_UInt8_19_io_deq_bits : _T_2580 ? _Queue64_UInt8_18_io_deq_bits : _T_2579 ? _Queue64_UInt8_17_io_deq_bits : _T_2578 ? _Queue64_UInt8_16_io_deq_bits : _T_2577 ? _Queue64_UInt8_15_io_deq_bits : _T_2576 ? _Queue64_UInt8_14_io_deq_bits : _T_2575 ? _Queue64_UInt8_13_io_deq_bits : _T_2574 ? _Queue64_UInt8_12_io_deq_bits : _T_2573 ? _Queue64_UInt8_11_io_deq_bits : _T_2572 ? _Queue64_UInt8_10_io_deq_bits : _T_2571 ? _Queue64_UInt8_9_io_deq_bits : _T_2570 ? _Queue64_UInt8_8_io_deq_bits : _T_2569 ? _Queue64_UInt8_7_io_deq_bits : _T_2568 ? _Queue64_UInt8_6_io_deq_bits : _T_2567 ? _Queue64_UInt8_5_io_deq_bits : _T_2566 ? _Queue64_UInt8_4_io_deq_bits : _T_2565 ? _Queue64_UInt8_3_io_deq_bits : _T_2564 ? _Queue64_UInt8_2_io_deq_bits : _T_2563 ? _Queue64_UInt8_1_io_deq_bits : _T_2562 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_14 = _T_2593 ? _Queue64_UInt8_31_io_deq_valid : _T_2592 ? _Queue64_UInt8_30_io_deq_valid : _T_2591 ? _Queue64_UInt8_29_io_deq_valid : _T_2590 ? _Queue64_UInt8_28_io_deq_valid : _T_2589 ? _Queue64_UInt8_27_io_deq_valid : _T_2588 ? _Queue64_UInt8_26_io_deq_valid : _T_2587 ? _Queue64_UInt8_25_io_deq_valid : _T_2586 ? _Queue64_UInt8_24_io_deq_valid : _T_2585 ? _Queue64_UInt8_23_io_deq_valid : _T_2584 ? _Queue64_UInt8_22_io_deq_valid : _T_2583 ? _Queue64_UInt8_21_io_deq_valid : _T_2582 ? _Queue64_UInt8_20_io_deq_valid : _T_2581 ? _Queue64_UInt8_19_io_deq_valid : _T_2580 ? _Queue64_UInt8_18_io_deq_valid : _T_2579 ? _Queue64_UInt8_17_io_deq_valid : _T_2578 ? _Queue64_UInt8_16_io_deq_valid : _T_2577 ? _Queue64_UInt8_15_io_deq_valid : _T_2576 ? _Queue64_UInt8_14_io_deq_valid : _T_2575 ? _Queue64_UInt8_13_io_deq_valid : _T_2574 ? _Queue64_UInt8_12_io_deq_valid : _T_2573 ? _Queue64_UInt8_11_io_deq_valid : _T_2572 ? _Queue64_UInt8_10_io_deq_valid : _T_2571 ? _Queue64_UInt8_9_io_deq_valid : _T_2570 ? _Queue64_UInt8_8_io_deq_valid : _T_2569 ? _Queue64_UInt8_7_io_deq_valid : _T_2568 ? _Queue64_UInt8_6_io_deq_valid : _T_2567 ? _Queue64_UInt8_5_io_deq_valid : _T_2566 ? _Queue64_UInt8_4_io_deq_valid : _T_2565 ? _Queue64_UInt8_3_io_deq_valid : _T_2564 ? _Queue64_UInt8_2_io_deq_valid : _T_2563 ? _Queue64_UInt8_1_io_deq_valid : _T_2562 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_78 = 9'h30 - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_79 = _remapindex_T_78; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_58 = _remapindex_T_79 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_15 = _GEN_58[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2594 = remapindex_15 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2595 = remapindex_15 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2596 = remapindex_15 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2597 = remapindex_15 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2598 = remapindex_15 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2599 = remapindex_15 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2600 = remapindex_15 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2601 = remapindex_15 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2602 = remapindex_15 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2603 = remapindex_15 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2604 = remapindex_15 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2605 = remapindex_15 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2606 = remapindex_15 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2607 = remapindex_15 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2608 = remapindex_15 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2609 = remapindex_15 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2610 = remapindex_15 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2611 = remapindex_15 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2612 = remapindex_15 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2613 = remapindex_15 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2614 = remapindex_15 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2615 = remapindex_15 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2616 = remapindex_15 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2617 = remapindex_15 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2618 = remapindex_15 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2619 = remapindex_15 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2620 = remapindex_15 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2621 = remapindex_15 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2622 = remapindex_15 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2623 = remapindex_15 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2624 = remapindex_15 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2625 = remapindex_15 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_15 = _T_2625 ? _Queue64_UInt8_31_io_deq_bits : _T_2624 ? _Queue64_UInt8_30_io_deq_bits : _T_2623 ? _Queue64_UInt8_29_io_deq_bits : _T_2622 ? _Queue64_UInt8_28_io_deq_bits : _T_2621 ? _Queue64_UInt8_27_io_deq_bits : _T_2620 ? _Queue64_UInt8_26_io_deq_bits : _T_2619 ? _Queue64_UInt8_25_io_deq_bits : _T_2618 ? _Queue64_UInt8_24_io_deq_bits : _T_2617 ? _Queue64_UInt8_23_io_deq_bits : _T_2616 ? _Queue64_UInt8_22_io_deq_bits : _T_2615 ? _Queue64_UInt8_21_io_deq_bits : _T_2614 ? _Queue64_UInt8_20_io_deq_bits : _T_2613 ? _Queue64_UInt8_19_io_deq_bits : _T_2612 ? _Queue64_UInt8_18_io_deq_bits : _T_2611 ? _Queue64_UInt8_17_io_deq_bits : _T_2610 ? _Queue64_UInt8_16_io_deq_bits : _T_2609 ? _Queue64_UInt8_15_io_deq_bits : _T_2608 ? _Queue64_UInt8_14_io_deq_bits : _T_2607 ? _Queue64_UInt8_13_io_deq_bits : _T_2606 ? _Queue64_UInt8_12_io_deq_bits : _T_2605 ? _Queue64_UInt8_11_io_deq_bits : _T_2604 ? _Queue64_UInt8_10_io_deq_bits : _T_2603 ? _Queue64_UInt8_9_io_deq_bits : _T_2602 ? _Queue64_UInt8_8_io_deq_bits : _T_2601 ? _Queue64_UInt8_7_io_deq_bits : _T_2600 ? _Queue64_UInt8_6_io_deq_bits : _T_2599 ? _Queue64_UInt8_5_io_deq_bits : _T_2598 ? _Queue64_UInt8_4_io_deq_bits : _T_2597 ? _Queue64_UInt8_3_io_deq_bits : _T_2596 ? _Queue64_UInt8_2_io_deq_bits : _T_2595 ? _Queue64_UInt8_1_io_deq_bits : _T_2594 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_15 = _T_2625 ? _Queue64_UInt8_31_io_deq_valid : _T_2624 ? _Queue64_UInt8_30_io_deq_valid : _T_2623 ? _Queue64_UInt8_29_io_deq_valid : _T_2622 ? _Queue64_UInt8_28_io_deq_valid : _T_2621 ? _Queue64_UInt8_27_io_deq_valid : _T_2620 ? _Queue64_UInt8_26_io_deq_valid : _T_2619 ? _Queue64_UInt8_25_io_deq_valid : _T_2618 ? _Queue64_UInt8_24_io_deq_valid : _T_2617 ? _Queue64_UInt8_23_io_deq_valid : _T_2616 ? _Queue64_UInt8_22_io_deq_valid : _T_2615 ? _Queue64_UInt8_21_io_deq_valid : _T_2614 ? _Queue64_UInt8_20_io_deq_valid : _T_2613 ? _Queue64_UInt8_19_io_deq_valid : _T_2612 ? _Queue64_UInt8_18_io_deq_valid : _T_2611 ? _Queue64_UInt8_17_io_deq_valid : _T_2610 ? _Queue64_UInt8_16_io_deq_valid : _T_2609 ? _Queue64_UInt8_15_io_deq_valid : _T_2608 ? _Queue64_UInt8_14_io_deq_valid : _T_2607 ? _Queue64_UInt8_13_io_deq_valid : _T_2606 ? _Queue64_UInt8_12_io_deq_valid : _T_2605 ? _Queue64_UInt8_11_io_deq_valid : _T_2604 ? _Queue64_UInt8_10_io_deq_valid : _T_2603 ? _Queue64_UInt8_9_io_deq_valid : _T_2602 ? _Queue64_UInt8_8_io_deq_valid : _T_2601 ? _Queue64_UInt8_7_io_deq_valid : _T_2600 ? _Queue64_UInt8_6_io_deq_valid : _T_2599 ? _Queue64_UInt8_5_io_deq_valid : _T_2598 ? _Queue64_UInt8_4_io_deq_valid : _T_2597 ? _Queue64_UInt8_3_io_deq_valid : _T_2596 ? _Queue64_UInt8_2_io_deq_valid : _T_2595 ? _Queue64_UInt8_1_io_deq_valid : _T_2594 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_83 = 9'h2F - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_84 = _remapindex_T_83; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_59 = _remapindex_T_84 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_16 = _GEN_59[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2626 = remapindex_16 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2627 = remapindex_16 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2628 = remapindex_16 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2629 = remapindex_16 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2630 = remapindex_16 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2631 = remapindex_16 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2632 = remapindex_16 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2633 = remapindex_16 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2634 = remapindex_16 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2635 = remapindex_16 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2636 = remapindex_16 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2637 = remapindex_16 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2638 = remapindex_16 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2639 = remapindex_16 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2640 = remapindex_16 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2641 = remapindex_16 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2642 = remapindex_16 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2643 = remapindex_16 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2644 = remapindex_16 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2645 = remapindex_16 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2646 = remapindex_16 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2647 = remapindex_16 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2648 = remapindex_16 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2649 = remapindex_16 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2650 = remapindex_16 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2651 = remapindex_16 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2652 = remapindex_16 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2653 = remapindex_16 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2654 = remapindex_16 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2655 = remapindex_16 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2656 = remapindex_16 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2657 = remapindex_16 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_16 = _T_2657 ? _Queue64_UInt8_31_io_deq_bits : _T_2656 ? _Queue64_UInt8_30_io_deq_bits : _T_2655 ? _Queue64_UInt8_29_io_deq_bits : _T_2654 ? _Queue64_UInt8_28_io_deq_bits : _T_2653 ? _Queue64_UInt8_27_io_deq_bits : _T_2652 ? _Queue64_UInt8_26_io_deq_bits : _T_2651 ? _Queue64_UInt8_25_io_deq_bits : _T_2650 ? _Queue64_UInt8_24_io_deq_bits : _T_2649 ? _Queue64_UInt8_23_io_deq_bits : _T_2648 ? _Queue64_UInt8_22_io_deq_bits : _T_2647 ? _Queue64_UInt8_21_io_deq_bits : _T_2646 ? _Queue64_UInt8_20_io_deq_bits : _T_2645 ? _Queue64_UInt8_19_io_deq_bits : _T_2644 ? _Queue64_UInt8_18_io_deq_bits : _T_2643 ? _Queue64_UInt8_17_io_deq_bits : _T_2642 ? _Queue64_UInt8_16_io_deq_bits : _T_2641 ? _Queue64_UInt8_15_io_deq_bits : _T_2640 ? _Queue64_UInt8_14_io_deq_bits : _T_2639 ? _Queue64_UInt8_13_io_deq_bits : _T_2638 ? _Queue64_UInt8_12_io_deq_bits : _T_2637 ? _Queue64_UInt8_11_io_deq_bits : _T_2636 ? _Queue64_UInt8_10_io_deq_bits : _T_2635 ? _Queue64_UInt8_9_io_deq_bits : _T_2634 ? _Queue64_UInt8_8_io_deq_bits : _T_2633 ? _Queue64_UInt8_7_io_deq_bits : _T_2632 ? _Queue64_UInt8_6_io_deq_bits : _T_2631 ? _Queue64_UInt8_5_io_deq_bits : _T_2630 ? _Queue64_UInt8_4_io_deq_bits : _T_2629 ? _Queue64_UInt8_3_io_deq_bits : _T_2628 ? _Queue64_UInt8_2_io_deq_bits : _T_2627 ? _Queue64_UInt8_1_io_deq_bits : _T_2626 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_16 = _T_2657 ? _Queue64_UInt8_31_io_deq_valid : _T_2656 ? _Queue64_UInt8_30_io_deq_valid : _T_2655 ? _Queue64_UInt8_29_io_deq_valid : _T_2654 ? _Queue64_UInt8_28_io_deq_valid : _T_2653 ? _Queue64_UInt8_27_io_deq_valid : _T_2652 ? _Queue64_UInt8_26_io_deq_valid : _T_2651 ? _Queue64_UInt8_25_io_deq_valid : _T_2650 ? _Queue64_UInt8_24_io_deq_valid : _T_2649 ? _Queue64_UInt8_23_io_deq_valid : _T_2648 ? _Queue64_UInt8_22_io_deq_valid : _T_2647 ? _Queue64_UInt8_21_io_deq_valid : _T_2646 ? _Queue64_UInt8_20_io_deq_valid : _T_2645 ? _Queue64_UInt8_19_io_deq_valid : _T_2644 ? _Queue64_UInt8_18_io_deq_valid : _T_2643 ? _Queue64_UInt8_17_io_deq_valid : _T_2642 ? _Queue64_UInt8_16_io_deq_valid : _T_2641 ? _Queue64_UInt8_15_io_deq_valid : _T_2640 ? _Queue64_UInt8_14_io_deq_valid : _T_2639 ? _Queue64_UInt8_13_io_deq_valid : _T_2638 ? _Queue64_UInt8_12_io_deq_valid : _T_2637 ? _Queue64_UInt8_11_io_deq_valid : _T_2636 ? _Queue64_UInt8_10_io_deq_valid : _T_2635 ? _Queue64_UInt8_9_io_deq_valid : _T_2634 ? _Queue64_UInt8_8_io_deq_valid : _T_2633 ? _Queue64_UInt8_7_io_deq_valid : _T_2632 ? _Queue64_UInt8_6_io_deq_valid : _T_2631 ? _Queue64_UInt8_5_io_deq_valid : _T_2630 ? _Queue64_UInt8_4_io_deq_valid : _T_2629 ? _Queue64_UInt8_3_io_deq_valid : _T_2628 ? _Queue64_UInt8_2_io_deq_valid : _T_2627 ? _Queue64_UInt8_1_io_deq_valid : _T_2626 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_88 = 9'h2E - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_89 = _remapindex_T_88; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_60 = _remapindex_T_89 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_17 = _GEN_60[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2658 = remapindex_17 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2659 = remapindex_17 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2660 = remapindex_17 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2661 = remapindex_17 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2662 = remapindex_17 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2663 = remapindex_17 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2664 = remapindex_17 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2665 = remapindex_17 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2666 = remapindex_17 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2667 = remapindex_17 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2668 = remapindex_17 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2669 = remapindex_17 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2670 = remapindex_17 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2671 = remapindex_17 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2672 = remapindex_17 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2673 = remapindex_17 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2674 = remapindex_17 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2675 = remapindex_17 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2676 = remapindex_17 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2677 = remapindex_17 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2678 = remapindex_17 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2679 = remapindex_17 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2680 = remapindex_17 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2681 = remapindex_17 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2682 = remapindex_17 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2683 = remapindex_17 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2684 = remapindex_17 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2685 = remapindex_17 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2686 = remapindex_17 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2687 = remapindex_17 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2688 = remapindex_17 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2689 = remapindex_17 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_17 = _T_2689 ? _Queue64_UInt8_31_io_deq_bits : _T_2688 ? _Queue64_UInt8_30_io_deq_bits : _T_2687 ? _Queue64_UInt8_29_io_deq_bits : _T_2686 ? _Queue64_UInt8_28_io_deq_bits : _T_2685 ? _Queue64_UInt8_27_io_deq_bits : _T_2684 ? _Queue64_UInt8_26_io_deq_bits : _T_2683 ? _Queue64_UInt8_25_io_deq_bits : _T_2682 ? _Queue64_UInt8_24_io_deq_bits : _T_2681 ? _Queue64_UInt8_23_io_deq_bits : _T_2680 ? _Queue64_UInt8_22_io_deq_bits : _T_2679 ? _Queue64_UInt8_21_io_deq_bits : _T_2678 ? _Queue64_UInt8_20_io_deq_bits : _T_2677 ? _Queue64_UInt8_19_io_deq_bits : _T_2676 ? _Queue64_UInt8_18_io_deq_bits : _T_2675 ? _Queue64_UInt8_17_io_deq_bits : _T_2674 ? _Queue64_UInt8_16_io_deq_bits : _T_2673 ? _Queue64_UInt8_15_io_deq_bits : _T_2672 ? _Queue64_UInt8_14_io_deq_bits : _T_2671 ? _Queue64_UInt8_13_io_deq_bits : _T_2670 ? _Queue64_UInt8_12_io_deq_bits : _T_2669 ? _Queue64_UInt8_11_io_deq_bits : _T_2668 ? _Queue64_UInt8_10_io_deq_bits : _T_2667 ? _Queue64_UInt8_9_io_deq_bits : _T_2666 ? _Queue64_UInt8_8_io_deq_bits : _T_2665 ? _Queue64_UInt8_7_io_deq_bits : _T_2664 ? _Queue64_UInt8_6_io_deq_bits : _T_2663 ? _Queue64_UInt8_5_io_deq_bits : _T_2662 ? _Queue64_UInt8_4_io_deq_bits : _T_2661 ? _Queue64_UInt8_3_io_deq_bits : _T_2660 ? _Queue64_UInt8_2_io_deq_bits : _T_2659 ? _Queue64_UInt8_1_io_deq_bits : _T_2658 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_17 = _T_2689 ? _Queue64_UInt8_31_io_deq_valid : _T_2688 ? _Queue64_UInt8_30_io_deq_valid : _T_2687 ? _Queue64_UInt8_29_io_deq_valid : _T_2686 ? _Queue64_UInt8_28_io_deq_valid : _T_2685 ? _Queue64_UInt8_27_io_deq_valid : _T_2684 ? _Queue64_UInt8_26_io_deq_valid : _T_2683 ? _Queue64_UInt8_25_io_deq_valid : _T_2682 ? _Queue64_UInt8_24_io_deq_valid : _T_2681 ? _Queue64_UInt8_23_io_deq_valid : _T_2680 ? _Queue64_UInt8_22_io_deq_valid : _T_2679 ? _Queue64_UInt8_21_io_deq_valid : _T_2678 ? _Queue64_UInt8_20_io_deq_valid : _T_2677 ? _Queue64_UInt8_19_io_deq_valid : _T_2676 ? _Queue64_UInt8_18_io_deq_valid : _T_2675 ? _Queue64_UInt8_17_io_deq_valid : _T_2674 ? _Queue64_UInt8_16_io_deq_valid : _T_2673 ? _Queue64_UInt8_15_io_deq_valid : _T_2672 ? _Queue64_UInt8_14_io_deq_valid : _T_2671 ? _Queue64_UInt8_13_io_deq_valid : _T_2670 ? _Queue64_UInt8_12_io_deq_valid : _T_2669 ? _Queue64_UInt8_11_io_deq_valid : _T_2668 ? _Queue64_UInt8_10_io_deq_valid : _T_2667 ? _Queue64_UInt8_9_io_deq_valid : _T_2666 ? _Queue64_UInt8_8_io_deq_valid : _T_2665 ? _Queue64_UInt8_7_io_deq_valid : _T_2664 ? _Queue64_UInt8_6_io_deq_valid : _T_2663 ? _Queue64_UInt8_5_io_deq_valid : _T_2662 ? _Queue64_UInt8_4_io_deq_valid : _T_2661 ? _Queue64_UInt8_3_io_deq_valid : _T_2660 ? _Queue64_UInt8_2_io_deq_valid : _T_2659 ? _Queue64_UInt8_1_io_deq_valid : _T_2658 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_93 = 9'h2D - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_94 = _remapindex_T_93; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_61 = _remapindex_T_94 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_18 = _GEN_61[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2690 = remapindex_18 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2691 = remapindex_18 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2692 = remapindex_18 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2693 = remapindex_18 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2694 = remapindex_18 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2695 = remapindex_18 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2696 = remapindex_18 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2697 = remapindex_18 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2698 = remapindex_18 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2699 = remapindex_18 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2700 = remapindex_18 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2701 = remapindex_18 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2702 = remapindex_18 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2703 = remapindex_18 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2704 = remapindex_18 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2705 = remapindex_18 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2706 = remapindex_18 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2707 = remapindex_18 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2708 = remapindex_18 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2709 = remapindex_18 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2710 = remapindex_18 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2711 = remapindex_18 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2712 = remapindex_18 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2713 = remapindex_18 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2714 = remapindex_18 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2715 = remapindex_18 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2716 = remapindex_18 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2717 = remapindex_18 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2718 = remapindex_18 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2719 = remapindex_18 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2720 = remapindex_18 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2721 = remapindex_18 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_18 = _T_2721 ? _Queue64_UInt8_31_io_deq_bits : _T_2720 ? _Queue64_UInt8_30_io_deq_bits : _T_2719 ? _Queue64_UInt8_29_io_deq_bits : _T_2718 ? _Queue64_UInt8_28_io_deq_bits : _T_2717 ? _Queue64_UInt8_27_io_deq_bits : _T_2716 ? _Queue64_UInt8_26_io_deq_bits : _T_2715 ? _Queue64_UInt8_25_io_deq_bits : _T_2714 ? _Queue64_UInt8_24_io_deq_bits : _T_2713 ? _Queue64_UInt8_23_io_deq_bits : _T_2712 ? _Queue64_UInt8_22_io_deq_bits : _T_2711 ? _Queue64_UInt8_21_io_deq_bits : _T_2710 ? _Queue64_UInt8_20_io_deq_bits : _T_2709 ? _Queue64_UInt8_19_io_deq_bits : _T_2708 ? _Queue64_UInt8_18_io_deq_bits : _T_2707 ? _Queue64_UInt8_17_io_deq_bits : _T_2706 ? _Queue64_UInt8_16_io_deq_bits : _T_2705 ? _Queue64_UInt8_15_io_deq_bits : _T_2704 ? _Queue64_UInt8_14_io_deq_bits : _T_2703 ? _Queue64_UInt8_13_io_deq_bits : _T_2702 ? _Queue64_UInt8_12_io_deq_bits : _T_2701 ? _Queue64_UInt8_11_io_deq_bits : _T_2700 ? _Queue64_UInt8_10_io_deq_bits : _T_2699 ? _Queue64_UInt8_9_io_deq_bits : _T_2698 ? _Queue64_UInt8_8_io_deq_bits : _T_2697 ? _Queue64_UInt8_7_io_deq_bits : _T_2696 ? _Queue64_UInt8_6_io_deq_bits : _T_2695 ? _Queue64_UInt8_5_io_deq_bits : _T_2694 ? _Queue64_UInt8_4_io_deq_bits : _T_2693 ? _Queue64_UInt8_3_io_deq_bits : _T_2692 ? _Queue64_UInt8_2_io_deq_bits : _T_2691 ? _Queue64_UInt8_1_io_deq_bits : _T_2690 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_18 = _T_2721 ? _Queue64_UInt8_31_io_deq_valid : _T_2720 ? _Queue64_UInt8_30_io_deq_valid : _T_2719 ? _Queue64_UInt8_29_io_deq_valid : _T_2718 ? _Queue64_UInt8_28_io_deq_valid : _T_2717 ? _Queue64_UInt8_27_io_deq_valid : _T_2716 ? _Queue64_UInt8_26_io_deq_valid : _T_2715 ? _Queue64_UInt8_25_io_deq_valid : _T_2714 ? _Queue64_UInt8_24_io_deq_valid : _T_2713 ? _Queue64_UInt8_23_io_deq_valid : _T_2712 ? _Queue64_UInt8_22_io_deq_valid : _T_2711 ? _Queue64_UInt8_21_io_deq_valid : _T_2710 ? _Queue64_UInt8_20_io_deq_valid : _T_2709 ? _Queue64_UInt8_19_io_deq_valid : _T_2708 ? _Queue64_UInt8_18_io_deq_valid : _T_2707 ? _Queue64_UInt8_17_io_deq_valid : _T_2706 ? _Queue64_UInt8_16_io_deq_valid : _T_2705 ? _Queue64_UInt8_15_io_deq_valid : _T_2704 ? _Queue64_UInt8_14_io_deq_valid : _T_2703 ? _Queue64_UInt8_13_io_deq_valid : _T_2702 ? _Queue64_UInt8_12_io_deq_valid : _T_2701 ? _Queue64_UInt8_11_io_deq_valid : _T_2700 ? _Queue64_UInt8_10_io_deq_valid : _T_2699 ? _Queue64_UInt8_9_io_deq_valid : _T_2698 ? _Queue64_UInt8_8_io_deq_valid : _T_2697 ? _Queue64_UInt8_7_io_deq_valid : _T_2696 ? _Queue64_UInt8_6_io_deq_valid : _T_2695 ? _Queue64_UInt8_5_io_deq_valid : _T_2694 ? _Queue64_UInt8_4_io_deq_valid : _T_2693 ? _Queue64_UInt8_3_io_deq_valid : _T_2692 ? _Queue64_UInt8_2_io_deq_valid : _T_2691 ? _Queue64_UInt8_1_io_deq_valid : _T_2690 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_98 = 9'h2C - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_99 = _remapindex_T_98; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_62 = _remapindex_T_99 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_19 = _GEN_62[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2722 = remapindex_19 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2723 = remapindex_19 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2724 = remapindex_19 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2725 = remapindex_19 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2726 = remapindex_19 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2727 = remapindex_19 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2728 = remapindex_19 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2729 = remapindex_19 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2730 = remapindex_19 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2731 = remapindex_19 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2732 = remapindex_19 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2733 = remapindex_19 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2734 = remapindex_19 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2735 = remapindex_19 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2736 = remapindex_19 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2737 = remapindex_19 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2738 = remapindex_19 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2739 = remapindex_19 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2740 = remapindex_19 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2741 = remapindex_19 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2742 = remapindex_19 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2743 = remapindex_19 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2744 = remapindex_19 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2745 = remapindex_19 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2746 = remapindex_19 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2747 = remapindex_19 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2748 = remapindex_19 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2749 = remapindex_19 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2750 = remapindex_19 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2751 = remapindex_19 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2752 = remapindex_19 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2753 = remapindex_19 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_19 = _T_2753 ? _Queue64_UInt8_31_io_deq_bits : _T_2752 ? _Queue64_UInt8_30_io_deq_bits : _T_2751 ? _Queue64_UInt8_29_io_deq_bits : _T_2750 ? _Queue64_UInt8_28_io_deq_bits : _T_2749 ? _Queue64_UInt8_27_io_deq_bits : _T_2748 ? _Queue64_UInt8_26_io_deq_bits : _T_2747 ? _Queue64_UInt8_25_io_deq_bits : _T_2746 ? _Queue64_UInt8_24_io_deq_bits : _T_2745 ? _Queue64_UInt8_23_io_deq_bits : _T_2744 ? _Queue64_UInt8_22_io_deq_bits : _T_2743 ? _Queue64_UInt8_21_io_deq_bits : _T_2742 ? _Queue64_UInt8_20_io_deq_bits : _T_2741 ? _Queue64_UInt8_19_io_deq_bits : _T_2740 ? _Queue64_UInt8_18_io_deq_bits : _T_2739 ? _Queue64_UInt8_17_io_deq_bits : _T_2738 ? _Queue64_UInt8_16_io_deq_bits : _T_2737 ? _Queue64_UInt8_15_io_deq_bits : _T_2736 ? _Queue64_UInt8_14_io_deq_bits : _T_2735 ? _Queue64_UInt8_13_io_deq_bits : _T_2734 ? _Queue64_UInt8_12_io_deq_bits : _T_2733 ? _Queue64_UInt8_11_io_deq_bits : _T_2732 ? _Queue64_UInt8_10_io_deq_bits : _T_2731 ? _Queue64_UInt8_9_io_deq_bits : _T_2730 ? _Queue64_UInt8_8_io_deq_bits : _T_2729 ? _Queue64_UInt8_7_io_deq_bits : _T_2728 ? _Queue64_UInt8_6_io_deq_bits : _T_2727 ? _Queue64_UInt8_5_io_deq_bits : _T_2726 ? _Queue64_UInt8_4_io_deq_bits : _T_2725 ? _Queue64_UInt8_3_io_deq_bits : _T_2724 ? _Queue64_UInt8_2_io_deq_bits : _T_2723 ? _Queue64_UInt8_1_io_deq_bits : _T_2722 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_19 = _T_2753 ? _Queue64_UInt8_31_io_deq_valid : _T_2752 ? _Queue64_UInt8_30_io_deq_valid : _T_2751 ? _Queue64_UInt8_29_io_deq_valid : _T_2750 ? _Queue64_UInt8_28_io_deq_valid : _T_2749 ? _Queue64_UInt8_27_io_deq_valid : _T_2748 ? _Queue64_UInt8_26_io_deq_valid : _T_2747 ? _Queue64_UInt8_25_io_deq_valid : _T_2746 ? _Queue64_UInt8_24_io_deq_valid : _T_2745 ? _Queue64_UInt8_23_io_deq_valid : _T_2744 ? _Queue64_UInt8_22_io_deq_valid : _T_2743 ? _Queue64_UInt8_21_io_deq_valid : _T_2742 ? _Queue64_UInt8_20_io_deq_valid : _T_2741 ? _Queue64_UInt8_19_io_deq_valid : _T_2740 ? _Queue64_UInt8_18_io_deq_valid : _T_2739 ? _Queue64_UInt8_17_io_deq_valid : _T_2738 ? _Queue64_UInt8_16_io_deq_valid : _T_2737 ? _Queue64_UInt8_15_io_deq_valid : _T_2736 ? _Queue64_UInt8_14_io_deq_valid : _T_2735 ? _Queue64_UInt8_13_io_deq_valid : _T_2734 ? _Queue64_UInt8_12_io_deq_valid : _T_2733 ? _Queue64_UInt8_11_io_deq_valid : _T_2732 ? _Queue64_UInt8_10_io_deq_valid : _T_2731 ? _Queue64_UInt8_9_io_deq_valid : _T_2730 ? _Queue64_UInt8_8_io_deq_valid : _T_2729 ? _Queue64_UInt8_7_io_deq_valid : _T_2728 ? _Queue64_UInt8_6_io_deq_valid : _T_2727 ? _Queue64_UInt8_5_io_deq_valid : _T_2726 ? _Queue64_UInt8_4_io_deq_valid : _T_2725 ? _Queue64_UInt8_3_io_deq_valid : _T_2724 ? _Queue64_UInt8_2_io_deq_valid : _T_2723 ? _Queue64_UInt8_1_io_deq_valid : _T_2722 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_103 = 9'h2B - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_104 = _remapindex_T_103; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_63 = _remapindex_T_104 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_20 = _GEN_63[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2754 = remapindex_20 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2755 = remapindex_20 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2756 = remapindex_20 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2757 = remapindex_20 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2758 = remapindex_20 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2759 = remapindex_20 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2760 = remapindex_20 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2761 = remapindex_20 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2762 = remapindex_20 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2763 = remapindex_20 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2764 = remapindex_20 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2765 = remapindex_20 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2766 = remapindex_20 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2767 = remapindex_20 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2768 = remapindex_20 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2769 = remapindex_20 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2770 = remapindex_20 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2771 = remapindex_20 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2772 = remapindex_20 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2773 = remapindex_20 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2774 = remapindex_20 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2775 = remapindex_20 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2776 = remapindex_20 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2777 = remapindex_20 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2778 = remapindex_20 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2779 = remapindex_20 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2780 = remapindex_20 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2781 = remapindex_20 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2782 = remapindex_20 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2783 = remapindex_20 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2784 = remapindex_20 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2785 = remapindex_20 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_20 = _T_2785 ? _Queue64_UInt8_31_io_deq_bits : _T_2784 ? _Queue64_UInt8_30_io_deq_bits : _T_2783 ? _Queue64_UInt8_29_io_deq_bits : _T_2782 ? _Queue64_UInt8_28_io_deq_bits : _T_2781 ? _Queue64_UInt8_27_io_deq_bits : _T_2780 ? _Queue64_UInt8_26_io_deq_bits : _T_2779 ? _Queue64_UInt8_25_io_deq_bits : _T_2778 ? _Queue64_UInt8_24_io_deq_bits : _T_2777 ? _Queue64_UInt8_23_io_deq_bits : _T_2776 ? _Queue64_UInt8_22_io_deq_bits : _T_2775 ? _Queue64_UInt8_21_io_deq_bits : _T_2774 ? _Queue64_UInt8_20_io_deq_bits : _T_2773 ? _Queue64_UInt8_19_io_deq_bits : _T_2772 ? _Queue64_UInt8_18_io_deq_bits : _T_2771 ? _Queue64_UInt8_17_io_deq_bits : _T_2770 ? _Queue64_UInt8_16_io_deq_bits : _T_2769 ? _Queue64_UInt8_15_io_deq_bits : _T_2768 ? _Queue64_UInt8_14_io_deq_bits : _T_2767 ? _Queue64_UInt8_13_io_deq_bits : _T_2766 ? _Queue64_UInt8_12_io_deq_bits : _T_2765 ? _Queue64_UInt8_11_io_deq_bits : _T_2764 ? _Queue64_UInt8_10_io_deq_bits : _T_2763 ? _Queue64_UInt8_9_io_deq_bits : _T_2762 ? _Queue64_UInt8_8_io_deq_bits : _T_2761 ? _Queue64_UInt8_7_io_deq_bits : _T_2760 ? _Queue64_UInt8_6_io_deq_bits : _T_2759 ? _Queue64_UInt8_5_io_deq_bits : _T_2758 ? _Queue64_UInt8_4_io_deq_bits : _T_2757 ? _Queue64_UInt8_3_io_deq_bits : _T_2756 ? _Queue64_UInt8_2_io_deq_bits : _T_2755 ? _Queue64_UInt8_1_io_deq_bits : _T_2754 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_20 = _T_2785 ? _Queue64_UInt8_31_io_deq_valid : _T_2784 ? _Queue64_UInt8_30_io_deq_valid : _T_2783 ? _Queue64_UInt8_29_io_deq_valid : _T_2782 ? _Queue64_UInt8_28_io_deq_valid : _T_2781 ? _Queue64_UInt8_27_io_deq_valid : _T_2780 ? _Queue64_UInt8_26_io_deq_valid : _T_2779 ? _Queue64_UInt8_25_io_deq_valid : _T_2778 ? _Queue64_UInt8_24_io_deq_valid : _T_2777 ? _Queue64_UInt8_23_io_deq_valid : _T_2776 ? _Queue64_UInt8_22_io_deq_valid : _T_2775 ? _Queue64_UInt8_21_io_deq_valid : _T_2774 ? _Queue64_UInt8_20_io_deq_valid : _T_2773 ? _Queue64_UInt8_19_io_deq_valid : _T_2772 ? _Queue64_UInt8_18_io_deq_valid : _T_2771 ? _Queue64_UInt8_17_io_deq_valid : _T_2770 ? _Queue64_UInt8_16_io_deq_valid : _T_2769 ? _Queue64_UInt8_15_io_deq_valid : _T_2768 ? _Queue64_UInt8_14_io_deq_valid : _T_2767 ? _Queue64_UInt8_13_io_deq_valid : _T_2766 ? _Queue64_UInt8_12_io_deq_valid : _T_2765 ? _Queue64_UInt8_11_io_deq_valid : _T_2764 ? _Queue64_UInt8_10_io_deq_valid : _T_2763 ? _Queue64_UInt8_9_io_deq_valid : _T_2762 ? _Queue64_UInt8_8_io_deq_valid : _T_2761 ? _Queue64_UInt8_7_io_deq_valid : _T_2760 ? _Queue64_UInt8_6_io_deq_valid : _T_2759 ? _Queue64_UInt8_5_io_deq_valid : _T_2758 ? _Queue64_UInt8_4_io_deq_valid : _T_2757 ? _Queue64_UInt8_3_io_deq_valid : _T_2756 ? _Queue64_UInt8_2_io_deq_valid : _T_2755 ? _Queue64_UInt8_1_io_deq_valid : _T_2754 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_108 = 9'h2A - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_109 = _remapindex_T_108; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_64 = _remapindex_T_109 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_21 = _GEN_64[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2786 = remapindex_21 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2787 = remapindex_21 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2788 = remapindex_21 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2789 = remapindex_21 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2790 = remapindex_21 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2791 = remapindex_21 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2792 = remapindex_21 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2793 = remapindex_21 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2794 = remapindex_21 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2795 = remapindex_21 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2796 = remapindex_21 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2797 = remapindex_21 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2798 = remapindex_21 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2799 = remapindex_21 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2800 = remapindex_21 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2801 = remapindex_21 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2802 = remapindex_21 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2803 = remapindex_21 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2804 = remapindex_21 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2805 = remapindex_21 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2806 = remapindex_21 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2807 = remapindex_21 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2808 = remapindex_21 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2809 = remapindex_21 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2810 = remapindex_21 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2811 = remapindex_21 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2812 = remapindex_21 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2813 = remapindex_21 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2814 = remapindex_21 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2815 = remapindex_21 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2816 = remapindex_21 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2817 = remapindex_21 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_21 = _T_2817 ? _Queue64_UInt8_31_io_deq_bits : _T_2816 ? _Queue64_UInt8_30_io_deq_bits : _T_2815 ? _Queue64_UInt8_29_io_deq_bits : _T_2814 ? _Queue64_UInt8_28_io_deq_bits : _T_2813 ? _Queue64_UInt8_27_io_deq_bits : _T_2812 ? _Queue64_UInt8_26_io_deq_bits : _T_2811 ? _Queue64_UInt8_25_io_deq_bits : _T_2810 ? _Queue64_UInt8_24_io_deq_bits : _T_2809 ? _Queue64_UInt8_23_io_deq_bits : _T_2808 ? _Queue64_UInt8_22_io_deq_bits : _T_2807 ? _Queue64_UInt8_21_io_deq_bits : _T_2806 ? _Queue64_UInt8_20_io_deq_bits : _T_2805 ? _Queue64_UInt8_19_io_deq_bits : _T_2804 ? _Queue64_UInt8_18_io_deq_bits : _T_2803 ? _Queue64_UInt8_17_io_deq_bits : _T_2802 ? _Queue64_UInt8_16_io_deq_bits : _T_2801 ? _Queue64_UInt8_15_io_deq_bits : _T_2800 ? _Queue64_UInt8_14_io_deq_bits : _T_2799 ? _Queue64_UInt8_13_io_deq_bits : _T_2798 ? _Queue64_UInt8_12_io_deq_bits : _T_2797 ? _Queue64_UInt8_11_io_deq_bits : _T_2796 ? _Queue64_UInt8_10_io_deq_bits : _T_2795 ? _Queue64_UInt8_9_io_deq_bits : _T_2794 ? _Queue64_UInt8_8_io_deq_bits : _T_2793 ? _Queue64_UInt8_7_io_deq_bits : _T_2792 ? _Queue64_UInt8_6_io_deq_bits : _T_2791 ? _Queue64_UInt8_5_io_deq_bits : _T_2790 ? _Queue64_UInt8_4_io_deq_bits : _T_2789 ? _Queue64_UInt8_3_io_deq_bits : _T_2788 ? _Queue64_UInt8_2_io_deq_bits : _T_2787 ? _Queue64_UInt8_1_io_deq_bits : _T_2786 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_21 = _T_2817 ? _Queue64_UInt8_31_io_deq_valid : _T_2816 ? _Queue64_UInt8_30_io_deq_valid : _T_2815 ? _Queue64_UInt8_29_io_deq_valid : _T_2814 ? _Queue64_UInt8_28_io_deq_valid : _T_2813 ? _Queue64_UInt8_27_io_deq_valid : _T_2812 ? _Queue64_UInt8_26_io_deq_valid : _T_2811 ? _Queue64_UInt8_25_io_deq_valid : _T_2810 ? _Queue64_UInt8_24_io_deq_valid : _T_2809 ? _Queue64_UInt8_23_io_deq_valid : _T_2808 ? _Queue64_UInt8_22_io_deq_valid : _T_2807 ? _Queue64_UInt8_21_io_deq_valid : _T_2806 ? _Queue64_UInt8_20_io_deq_valid : _T_2805 ? _Queue64_UInt8_19_io_deq_valid : _T_2804 ? _Queue64_UInt8_18_io_deq_valid : _T_2803 ? _Queue64_UInt8_17_io_deq_valid : _T_2802 ? _Queue64_UInt8_16_io_deq_valid : _T_2801 ? _Queue64_UInt8_15_io_deq_valid : _T_2800 ? _Queue64_UInt8_14_io_deq_valid : _T_2799 ? _Queue64_UInt8_13_io_deq_valid : _T_2798 ? _Queue64_UInt8_12_io_deq_valid : _T_2797 ? _Queue64_UInt8_11_io_deq_valid : _T_2796 ? _Queue64_UInt8_10_io_deq_valid : _T_2795 ? _Queue64_UInt8_9_io_deq_valid : _T_2794 ? _Queue64_UInt8_8_io_deq_valid : _T_2793 ? _Queue64_UInt8_7_io_deq_valid : _T_2792 ? _Queue64_UInt8_6_io_deq_valid : _T_2791 ? _Queue64_UInt8_5_io_deq_valid : _T_2790 ? _Queue64_UInt8_4_io_deq_valid : _T_2789 ? _Queue64_UInt8_3_io_deq_valid : _T_2788 ? _Queue64_UInt8_2_io_deq_valid : _T_2787 ? _Queue64_UInt8_1_io_deq_valid : _T_2786 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_113 = 9'h29 - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_114 = _remapindex_T_113; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_65 = _remapindex_T_114 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_22 = _GEN_65[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2818 = remapindex_22 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2819 = remapindex_22 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2820 = remapindex_22 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2821 = remapindex_22 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2822 = remapindex_22 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2823 = remapindex_22 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2824 = remapindex_22 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2825 = remapindex_22 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2826 = remapindex_22 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2827 = remapindex_22 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2828 = remapindex_22 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2829 = remapindex_22 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2830 = remapindex_22 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2831 = remapindex_22 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2832 = remapindex_22 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2833 = remapindex_22 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2834 = remapindex_22 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2835 = remapindex_22 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2836 = remapindex_22 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2837 = remapindex_22 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2838 = remapindex_22 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2839 = remapindex_22 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2840 = remapindex_22 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2841 = remapindex_22 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2842 = remapindex_22 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2843 = remapindex_22 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2844 = remapindex_22 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2845 = remapindex_22 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2846 = remapindex_22 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2847 = remapindex_22 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2848 = remapindex_22 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2849 = remapindex_22 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_22 = _T_2849 ? _Queue64_UInt8_31_io_deq_bits : _T_2848 ? _Queue64_UInt8_30_io_deq_bits : _T_2847 ? _Queue64_UInt8_29_io_deq_bits : _T_2846 ? _Queue64_UInt8_28_io_deq_bits : _T_2845 ? _Queue64_UInt8_27_io_deq_bits : _T_2844 ? _Queue64_UInt8_26_io_deq_bits : _T_2843 ? _Queue64_UInt8_25_io_deq_bits : _T_2842 ? _Queue64_UInt8_24_io_deq_bits : _T_2841 ? _Queue64_UInt8_23_io_deq_bits : _T_2840 ? _Queue64_UInt8_22_io_deq_bits : _T_2839 ? _Queue64_UInt8_21_io_deq_bits : _T_2838 ? _Queue64_UInt8_20_io_deq_bits : _T_2837 ? _Queue64_UInt8_19_io_deq_bits : _T_2836 ? _Queue64_UInt8_18_io_deq_bits : _T_2835 ? _Queue64_UInt8_17_io_deq_bits : _T_2834 ? _Queue64_UInt8_16_io_deq_bits : _T_2833 ? _Queue64_UInt8_15_io_deq_bits : _T_2832 ? _Queue64_UInt8_14_io_deq_bits : _T_2831 ? _Queue64_UInt8_13_io_deq_bits : _T_2830 ? _Queue64_UInt8_12_io_deq_bits : _T_2829 ? _Queue64_UInt8_11_io_deq_bits : _T_2828 ? _Queue64_UInt8_10_io_deq_bits : _T_2827 ? _Queue64_UInt8_9_io_deq_bits : _T_2826 ? _Queue64_UInt8_8_io_deq_bits : _T_2825 ? _Queue64_UInt8_7_io_deq_bits : _T_2824 ? _Queue64_UInt8_6_io_deq_bits : _T_2823 ? _Queue64_UInt8_5_io_deq_bits : _T_2822 ? _Queue64_UInt8_4_io_deq_bits : _T_2821 ? _Queue64_UInt8_3_io_deq_bits : _T_2820 ? _Queue64_UInt8_2_io_deq_bits : _T_2819 ? _Queue64_UInt8_1_io_deq_bits : _T_2818 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_22 = _T_2849 ? _Queue64_UInt8_31_io_deq_valid : _T_2848 ? _Queue64_UInt8_30_io_deq_valid : _T_2847 ? _Queue64_UInt8_29_io_deq_valid : _T_2846 ? _Queue64_UInt8_28_io_deq_valid : _T_2845 ? _Queue64_UInt8_27_io_deq_valid : _T_2844 ? _Queue64_UInt8_26_io_deq_valid : _T_2843 ? _Queue64_UInt8_25_io_deq_valid : _T_2842 ? _Queue64_UInt8_24_io_deq_valid : _T_2841 ? _Queue64_UInt8_23_io_deq_valid : _T_2840 ? _Queue64_UInt8_22_io_deq_valid : _T_2839 ? _Queue64_UInt8_21_io_deq_valid : _T_2838 ? _Queue64_UInt8_20_io_deq_valid : _T_2837 ? _Queue64_UInt8_19_io_deq_valid : _T_2836 ? _Queue64_UInt8_18_io_deq_valid : _T_2835 ? _Queue64_UInt8_17_io_deq_valid : _T_2834 ? _Queue64_UInt8_16_io_deq_valid : _T_2833 ? _Queue64_UInt8_15_io_deq_valid : _T_2832 ? _Queue64_UInt8_14_io_deq_valid : _T_2831 ? _Queue64_UInt8_13_io_deq_valid : _T_2830 ? _Queue64_UInt8_12_io_deq_valid : _T_2829 ? _Queue64_UInt8_11_io_deq_valid : _T_2828 ? _Queue64_UInt8_10_io_deq_valid : _T_2827 ? _Queue64_UInt8_9_io_deq_valid : _T_2826 ? _Queue64_UInt8_8_io_deq_valid : _T_2825 ? _Queue64_UInt8_7_io_deq_valid : _T_2824 ? _Queue64_UInt8_6_io_deq_valid : _T_2823 ? _Queue64_UInt8_5_io_deq_valid : _T_2822 ? _Queue64_UInt8_4_io_deq_valid : _T_2821 ? _Queue64_UInt8_3_io_deq_valid : _T_2820 ? _Queue64_UInt8_2_io_deq_valid : _T_2819 ? _Queue64_UInt8_1_io_deq_valid : _T_2818 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_118 = 9'h28 - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_119 = _remapindex_T_118; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_66 = _remapindex_T_119 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_23 = _GEN_66[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2850 = remapindex_23 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2851 = remapindex_23 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2852 = remapindex_23 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2853 = remapindex_23 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2854 = remapindex_23 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2855 = remapindex_23 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2856 = remapindex_23 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2857 = remapindex_23 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2858 = remapindex_23 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2859 = remapindex_23 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2860 = remapindex_23 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2861 = remapindex_23 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2862 = remapindex_23 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2863 = remapindex_23 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2864 = remapindex_23 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2865 = remapindex_23 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2866 = remapindex_23 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2867 = remapindex_23 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2868 = remapindex_23 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2869 = remapindex_23 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2870 = remapindex_23 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2871 = remapindex_23 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2872 = remapindex_23 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2873 = remapindex_23 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2874 = remapindex_23 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2875 = remapindex_23 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2876 = remapindex_23 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2877 = remapindex_23 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2878 = remapindex_23 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2879 = remapindex_23 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2880 = remapindex_23 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2881 = remapindex_23 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_23 = _T_2881 ? _Queue64_UInt8_31_io_deq_bits : _T_2880 ? _Queue64_UInt8_30_io_deq_bits : _T_2879 ? _Queue64_UInt8_29_io_deq_bits : _T_2878 ? _Queue64_UInt8_28_io_deq_bits : _T_2877 ? _Queue64_UInt8_27_io_deq_bits : _T_2876 ? _Queue64_UInt8_26_io_deq_bits : _T_2875 ? _Queue64_UInt8_25_io_deq_bits : _T_2874 ? _Queue64_UInt8_24_io_deq_bits : _T_2873 ? _Queue64_UInt8_23_io_deq_bits : _T_2872 ? _Queue64_UInt8_22_io_deq_bits : _T_2871 ? _Queue64_UInt8_21_io_deq_bits : _T_2870 ? _Queue64_UInt8_20_io_deq_bits : _T_2869 ? _Queue64_UInt8_19_io_deq_bits : _T_2868 ? _Queue64_UInt8_18_io_deq_bits : _T_2867 ? _Queue64_UInt8_17_io_deq_bits : _T_2866 ? _Queue64_UInt8_16_io_deq_bits : _T_2865 ? _Queue64_UInt8_15_io_deq_bits : _T_2864 ? _Queue64_UInt8_14_io_deq_bits : _T_2863 ? _Queue64_UInt8_13_io_deq_bits : _T_2862 ? _Queue64_UInt8_12_io_deq_bits : _T_2861 ? _Queue64_UInt8_11_io_deq_bits : _T_2860 ? _Queue64_UInt8_10_io_deq_bits : _T_2859 ? _Queue64_UInt8_9_io_deq_bits : _T_2858 ? _Queue64_UInt8_8_io_deq_bits : _T_2857 ? _Queue64_UInt8_7_io_deq_bits : _T_2856 ? _Queue64_UInt8_6_io_deq_bits : _T_2855 ? _Queue64_UInt8_5_io_deq_bits : _T_2854 ? _Queue64_UInt8_4_io_deq_bits : _T_2853 ? _Queue64_UInt8_3_io_deq_bits : _T_2852 ? _Queue64_UInt8_2_io_deq_bits : _T_2851 ? _Queue64_UInt8_1_io_deq_bits : _T_2850 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_23 = _T_2881 ? _Queue64_UInt8_31_io_deq_valid : _T_2880 ? _Queue64_UInt8_30_io_deq_valid : _T_2879 ? _Queue64_UInt8_29_io_deq_valid : _T_2878 ? _Queue64_UInt8_28_io_deq_valid : _T_2877 ? _Queue64_UInt8_27_io_deq_valid : _T_2876 ? _Queue64_UInt8_26_io_deq_valid : _T_2875 ? _Queue64_UInt8_25_io_deq_valid : _T_2874 ? _Queue64_UInt8_24_io_deq_valid : _T_2873 ? _Queue64_UInt8_23_io_deq_valid : _T_2872 ? _Queue64_UInt8_22_io_deq_valid : _T_2871 ? _Queue64_UInt8_21_io_deq_valid : _T_2870 ? _Queue64_UInt8_20_io_deq_valid : _T_2869 ? _Queue64_UInt8_19_io_deq_valid : _T_2868 ? _Queue64_UInt8_18_io_deq_valid : _T_2867 ? _Queue64_UInt8_17_io_deq_valid : _T_2866 ? _Queue64_UInt8_16_io_deq_valid : _T_2865 ? _Queue64_UInt8_15_io_deq_valid : _T_2864 ? _Queue64_UInt8_14_io_deq_valid : _T_2863 ? _Queue64_UInt8_13_io_deq_valid : _T_2862 ? _Queue64_UInt8_12_io_deq_valid : _T_2861 ? _Queue64_UInt8_11_io_deq_valid : _T_2860 ? _Queue64_UInt8_10_io_deq_valid : _T_2859 ? _Queue64_UInt8_9_io_deq_valid : _T_2858 ? _Queue64_UInt8_8_io_deq_valid : _T_2857 ? _Queue64_UInt8_7_io_deq_valid : _T_2856 ? _Queue64_UInt8_6_io_deq_valid : _T_2855 ? _Queue64_UInt8_5_io_deq_valid : _T_2854 ? _Queue64_UInt8_4_io_deq_valid : _T_2853 ? _Queue64_UInt8_3_io_deq_valid : _T_2852 ? _Queue64_UInt8_2_io_deq_valid : _T_2851 ? _Queue64_UInt8_1_io_deq_valid : _T_2850 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_123 = 9'h27 - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_124 = _remapindex_T_123; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_67 = _remapindex_T_124 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_24 = _GEN_67[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2882 = remapindex_24 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2883 = remapindex_24 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2884 = remapindex_24 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2885 = remapindex_24 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2886 = remapindex_24 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2887 = remapindex_24 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2888 = remapindex_24 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2889 = remapindex_24 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2890 = remapindex_24 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2891 = remapindex_24 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2892 = remapindex_24 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2893 = remapindex_24 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2894 = remapindex_24 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2895 = remapindex_24 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2896 = remapindex_24 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2897 = remapindex_24 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2898 = remapindex_24 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2899 = remapindex_24 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2900 = remapindex_24 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2901 = remapindex_24 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2902 = remapindex_24 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2903 = remapindex_24 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2904 = remapindex_24 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2905 = remapindex_24 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2906 = remapindex_24 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2907 = remapindex_24 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2908 = remapindex_24 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2909 = remapindex_24 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2910 = remapindex_24 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2911 = remapindex_24 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2912 = remapindex_24 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2913 = remapindex_24 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_24 = _T_2913 ? _Queue64_UInt8_31_io_deq_bits : _T_2912 ? _Queue64_UInt8_30_io_deq_bits : _T_2911 ? _Queue64_UInt8_29_io_deq_bits : _T_2910 ? _Queue64_UInt8_28_io_deq_bits : _T_2909 ? _Queue64_UInt8_27_io_deq_bits : _T_2908 ? _Queue64_UInt8_26_io_deq_bits : _T_2907 ? _Queue64_UInt8_25_io_deq_bits : _T_2906 ? _Queue64_UInt8_24_io_deq_bits : _T_2905 ? _Queue64_UInt8_23_io_deq_bits : _T_2904 ? _Queue64_UInt8_22_io_deq_bits : _T_2903 ? _Queue64_UInt8_21_io_deq_bits : _T_2902 ? _Queue64_UInt8_20_io_deq_bits : _T_2901 ? _Queue64_UInt8_19_io_deq_bits : _T_2900 ? _Queue64_UInt8_18_io_deq_bits : _T_2899 ? _Queue64_UInt8_17_io_deq_bits : _T_2898 ? _Queue64_UInt8_16_io_deq_bits : _T_2897 ? _Queue64_UInt8_15_io_deq_bits : _T_2896 ? _Queue64_UInt8_14_io_deq_bits : _T_2895 ? _Queue64_UInt8_13_io_deq_bits : _T_2894 ? _Queue64_UInt8_12_io_deq_bits : _T_2893 ? _Queue64_UInt8_11_io_deq_bits : _T_2892 ? _Queue64_UInt8_10_io_deq_bits : _T_2891 ? _Queue64_UInt8_9_io_deq_bits : _T_2890 ? _Queue64_UInt8_8_io_deq_bits : _T_2889 ? _Queue64_UInt8_7_io_deq_bits : _T_2888 ? _Queue64_UInt8_6_io_deq_bits : _T_2887 ? _Queue64_UInt8_5_io_deq_bits : _T_2886 ? _Queue64_UInt8_4_io_deq_bits : _T_2885 ? _Queue64_UInt8_3_io_deq_bits : _T_2884 ? _Queue64_UInt8_2_io_deq_bits : _T_2883 ? _Queue64_UInt8_1_io_deq_bits : _T_2882 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_24 = _T_2913 ? _Queue64_UInt8_31_io_deq_valid : _T_2912 ? _Queue64_UInt8_30_io_deq_valid : _T_2911 ? _Queue64_UInt8_29_io_deq_valid : _T_2910 ? _Queue64_UInt8_28_io_deq_valid : _T_2909 ? _Queue64_UInt8_27_io_deq_valid : _T_2908 ? _Queue64_UInt8_26_io_deq_valid : _T_2907 ? _Queue64_UInt8_25_io_deq_valid : _T_2906 ? _Queue64_UInt8_24_io_deq_valid : _T_2905 ? _Queue64_UInt8_23_io_deq_valid : _T_2904 ? _Queue64_UInt8_22_io_deq_valid : _T_2903 ? _Queue64_UInt8_21_io_deq_valid : _T_2902 ? _Queue64_UInt8_20_io_deq_valid : _T_2901 ? _Queue64_UInt8_19_io_deq_valid : _T_2900 ? _Queue64_UInt8_18_io_deq_valid : _T_2899 ? _Queue64_UInt8_17_io_deq_valid : _T_2898 ? _Queue64_UInt8_16_io_deq_valid : _T_2897 ? _Queue64_UInt8_15_io_deq_valid : _T_2896 ? _Queue64_UInt8_14_io_deq_valid : _T_2895 ? _Queue64_UInt8_13_io_deq_valid : _T_2894 ? _Queue64_UInt8_12_io_deq_valid : _T_2893 ? _Queue64_UInt8_11_io_deq_valid : _T_2892 ? _Queue64_UInt8_10_io_deq_valid : _T_2891 ? _Queue64_UInt8_9_io_deq_valid : _T_2890 ? _Queue64_UInt8_8_io_deq_valid : _T_2889 ? _Queue64_UInt8_7_io_deq_valid : _T_2888 ? _Queue64_UInt8_6_io_deq_valid : _T_2887 ? _Queue64_UInt8_5_io_deq_valid : _T_2886 ? _Queue64_UInt8_4_io_deq_valid : _T_2885 ? _Queue64_UInt8_3_io_deq_valid : _T_2884 ? _Queue64_UInt8_2_io_deq_valid : _T_2883 ? _Queue64_UInt8_1_io_deq_valid : _T_2882 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_128 = 9'h26 - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_129 = _remapindex_T_128; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_68 = _remapindex_T_129 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_25 = _GEN_68[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2914 = remapindex_25 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2915 = remapindex_25 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2916 = remapindex_25 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2917 = remapindex_25 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2918 = remapindex_25 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2919 = remapindex_25 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2920 = remapindex_25 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2921 = remapindex_25 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2922 = remapindex_25 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2923 = remapindex_25 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2924 = remapindex_25 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2925 = remapindex_25 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2926 = remapindex_25 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2927 = remapindex_25 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2928 = remapindex_25 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2929 = remapindex_25 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2930 = remapindex_25 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2931 = remapindex_25 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2932 = remapindex_25 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2933 = remapindex_25 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2934 = remapindex_25 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2935 = remapindex_25 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2936 = remapindex_25 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2937 = remapindex_25 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2938 = remapindex_25 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2939 = remapindex_25 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2940 = remapindex_25 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2941 = remapindex_25 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2942 = remapindex_25 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2943 = remapindex_25 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2944 = remapindex_25 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2945 = remapindex_25 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_25 = _T_2945 ? _Queue64_UInt8_31_io_deq_bits : _T_2944 ? _Queue64_UInt8_30_io_deq_bits : _T_2943 ? _Queue64_UInt8_29_io_deq_bits : _T_2942 ? _Queue64_UInt8_28_io_deq_bits : _T_2941 ? _Queue64_UInt8_27_io_deq_bits : _T_2940 ? _Queue64_UInt8_26_io_deq_bits : _T_2939 ? _Queue64_UInt8_25_io_deq_bits : _T_2938 ? _Queue64_UInt8_24_io_deq_bits : _T_2937 ? _Queue64_UInt8_23_io_deq_bits : _T_2936 ? _Queue64_UInt8_22_io_deq_bits : _T_2935 ? _Queue64_UInt8_21_io_deq_bits : _T_2934 ? _Queue64_UInt8_20_io_deq_bits : _T_2933 ? _Queue64_UInt8_19_io_deq_bits : _T_2932 ? _Queue64_UInt8_18_io_deq_bits : _T_2931 ? _Queue64_UInt8_17_io_deq_bits : _T_2930 ? _Queue64_UInt8_16_io_deq_bits : _T_2929 ? _Queue64_UInt8_15_io_deq_bits : _T_2928 ? _Queue64_UInt8_14_io_deq_bits : _T_2927 ? _Queue64_UInt8_13_io_deq_bits : _T_2926 ? _Queue64_UInt8_12_io_deq_bits : _T_2925 ? _Queue64_UInt8_11_io_deq_bits : _T_2924 ? _Queue64_UInt8_10_io_deq_bits : _T_2923 ? _Queue64_UInt8_9_io_deq_bits : _T_2922 ? _Queue64_UInt8_8_io_deq_bits : _T_2921 ? _Queue64_UInt8_7_io_deq_bits : _T_2920 ? _Queue64_UInt8_6_io_deq_bits : _T_2919 ? _Queue64_UInt8_5_io_deq_bits : _T_2918 ? _Queue64_UInt8_4_io_deq_bits : _T_2917 ? _Queue64_UInt8_3_io_deq_bits : _T_2916 ? _Queue64_UInt8_2_io_deq_bits : _T_2915 ? _Queue64_UInt8_1_io_deq_bits : _T_2914 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_25 = _T_2945 ? _Queue64_UInt8_31_io_deq_valid : _T_2944 ? _Queue64_UInt8_30_io_deq_valid : _T_2943 ? _Queue64_UInt8_29_io_deq_valid : _T_2942 ? _Queue64_UInt8_28_io_deq_valid : _T_2941 ? _Queue64_UInt8_27_io_deq_valid : _T_2940 ? _Queue64_UInt8_26_io_deq_valid : _T_2939 ? _Queue64_UInt8_25_io_deq_valid : _T_2938 ? _Queue64_UInt8_24_io_deq_valid : _T_2937 ? _Queue64_UInt8_23_io_deq_valid : _T_2936 ? _Queue64_UInt8_22_io_deq_valid : _T_2935 ? _Queue64_UInt8_21_io_deq_valid : _T_2934 ? _Queue64_UInt8_20_io_deq_valid : _T_2933 ? _Queue64_UInt8_19_io_deq_valid : _T_2932 ? _Queue64_UInt8_18_io_deq_valid : _T_2931 ? _Queue64_UInt8_17_io_deq_valid : _T_2930 ? _Queue64_UInt8_16_io_deq_valid : _T_2929 ? _Queue64_UInt8_15_io_deq_valid : _T_2928 ? _Queue64_UInt8_14_io_deq_valid : _T_2927 ? _Queue64_UInt8_13_io_deq_valid : _T_2926 ? _Queue64_UInt8_12_io_deq_valid : _T_2925 ? _Queue64_UInt8_11_io_deq_valid : _T_2924 ? _Queue64_UInt8_10_io_deq_valid : _T_2923 ? _Queue64_UInt8_9_io_deq_valid : _T_2922 ? _Queue64_UInt8_8_io_deq_valid : _T_2921 ? _Queue64_UInt8_7_io_deq_valid : _T_2920 ? _Queue64_UInt8_6_io_deq_valid : _T_2919 ? _Queue64_UInt8_5_io_deq_valid : _T_2918 ? _Queue64_UInt8_4_io_deq_valid : _T_2917 ? _Queue64_UInt8_3_io_deq_valid : _T_2916 ? _Queue64_UInt8_2_io_deq_valid : _T_2915 ? _Queue64_UInt8_1_io_deq_valid : _T_2914 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_133 = 9'h25 - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_134 = _remapindex_T_133; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_69 = _remapindex_T_134 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_26 = _GEN_69[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2946 = remapindex_26 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2947 = remapindex_26 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2948 = remapindex_26 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2949 = remapindex_26 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2950 = remapindex_26 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2951 = remapindex_26 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2952 = remapindex_26 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2953 = remapindex_26 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2954 = remapindex_26 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2955 = remapindex_26 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2956 = remapindex_26 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2957 = remapindex_26 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2958 = remapindex_26 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2959 = remapindex_26 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2960 = remapindex_26 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2961 = remapindex_26 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2962 = remapindex_26 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2963 = remapindex_26 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2964 = remapindex_26 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2965 = remapindex_26 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2966 = remapindex_26 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2967 = remapindex_26 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2968 = remapindex_26 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2969 = remapindex_26 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2970 = remapindex_26 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2971 = remapindex_26 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2972 = remapindex_26 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2973 = remapindex_26 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2974 = remapindex_26 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2975 = remapindex_26 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2976 = remapindex_26 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2977 = remapindex_26 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_26 = _T_2977 ? _Queue64_UInt8_31_io_deq_bits : _T_2976 ? _Queue64_UInt8_30_io_deq_bits : _T_2975 ? _Queue64_UInt8_29_io_deq_bits : _T_2974 ? _Queue64_UInt8_28_io_deq_bits : _T_2973 ? _Queue64_UInt8_27_io_deq_bits : _T_2972 ? _Queue64_UInt8_26_io_deq_bits : _T_2971 ? _Queue64_UInt8_25_io_deq_bits : _T_2970 ? _Queue64_UInt8_24_io_deq_bits : _T_2969 ? _Queue64_UInt8_23_io_deq_bits : _T_2968 ? _Queue64_UInt8_22_io_deq_bits : _T_2967 ? _Queue64_UInt8_21_io_deq_bits : _T_2966 ? _Queue64_UInt8_20_io_deq_bits : _T_2965 ? _Queue64_UInt8_19_io_deq_bits : _T_2964 ? _Queue64_UInt8_18_io_deq_bits : _T_2963 ? _Queue64_UInt8_17_io_deq_bits : _T_2962 ? _Queue64_UInt8_16_io_deq_bits : _T_2961 ? _Queue64_UInt8_15_io_deq_bits : _T_2960 ? _Queue64_UInt8_14_io_deq_bits : _T_2959 ? _Queue64_UInt8_13_io_deq_bits : _T_2958 ? _Queue64_UInt8_12_io_deq_bits : _T_2957 ? _Queue64_UInt8_11_io_deq_bits : _T_2956 ? _Queue64_UInt8_10_io_deq_bits : _T_2955 ? _Queue64_UInt8_9_io_deq_bits : _T_2954 ? _Queue64_UInt8_8_io_deq_bits : _T_2953 ? _Queue64_UInt8_7_io_deq_bits : _T_2952 ? _Queue64_UInt8_6_io_deq_bits : _T_2951 ? _Queue64_UInt8_5_io_deq_bits : _T_2950 ? _Queue64_UInt8_4_io_deq_bits : _T_2949 ? _Queue64_UInt8_3_io_deq_bits : _T_2948 ? _Queue64_UInt8_2_io_deq_bits : _T_2947 ? _Queue64_UInt8_1_io_deq_bits : _T_2946 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_26 = _T_2977 ? _Queue64_UInt8_31_io_deq_valid : _T_2976 ? _Queue64_UInt8_30_io_deq_valid : _T_2975 ? _Queue64_UInt8_29_io_deq_valid : _T_2974 ? _Queue64_UInt8_28_io_deq_valid : _T_2973 ? _Queue64_UInt8_27_io_deq_valid : _T_2972 ? _Queue64_UInt8_26_io_deq_valid : _T_2971 ? _Queue64_UInt8_25_io_deq_valid : _T_2970 ? _Queue64_UInt8_24_io_deq_valid : _T_2969 ? _Queue64_UInt8_23_io_deq_valid : _T_2968 ? _Queue64_UInt8_22_io_deq_valid : _T_2967 ? _Queue64_UInt8_21_io_deq_valid : _T_2966 ? _Queue64_UInt8_20_io_deq_valid : _T_2965 ? _Queue64_UInt8_19_io_deq_valid : _T_2964 ? _Queue64_UInt8_18_io_deq_valid : _T_2963 ? _Queue64_UInt8_17_io_deq_valid : _T_2962 ? _Queue64_UInt8_16_io_deq_valid : _T_2961 ? _Queue64_UInt8_15_io_deq_valid : _T_2960 ? _Queue64_UInt8_14_io_deq_valid : _T_2959 ? _Queue64_UInt8_13_io_deq_valid : _T_2958 ? _Queue64_UInt8_12_io_deq_valid : _T_2957 ? _Queue64_UInt8_11_io_deq_valid : _T_2956 ? _Queue64_UInt8_10_io_deq_valid : _T_2955 ? _Queue64_UInt8_9_io_deq_valid : _T_2954 ? _Queue64_UInt8_8_io_deq_valid : _T_2953 ? _Queue64_UInt8_7_io_deq_valid : _T_2952 ? _Queue64_UInt8_6_io_deq_valid : _T_2951 ? _Queue64_UInt8_5_io_deq_valid : _T_2950 ? _Queue64_UInt8_4_io_deq_valid : _T_2949 ? _Queue64_UInt8_3_io_deq_valid : _T_2948 ? _Queue64_UInt8_2_io_deq_valid : _T_2947 ? _Queue64_UInt8_1_io_deq_valid : _T_2946 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_138 = 9'h24 - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_139 = _remapindex_T_138; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_70 = _remapindex_T_139 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_27 = _GEN_70[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_2978 = remapindex_27 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2979 = remapindex_27 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2980 = remapindex_27 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2981 = remapindex_27 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2982 = remapindex_27 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2983 = remapindex_27 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2984 = remapindex_27 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2985 = remapindex_27 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2986 = remapindex_27 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2987 = remapindex_27 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2988 = remapindex_27 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2989 = remapindex_27 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2990 = remapindex_27 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2991 = remapindex_27 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2992 = remapindex_27 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2993 = remapindex_27 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2994 = remapindex_27 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2995 = remapindex_27 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2996 = remapindex_27 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2997 = remapindex_27 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2998 = remapindex_27 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_2999 = remapindex_27 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3000 = remapindex_27 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3001 = remapindex_27 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3002 = remapindex_27 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3003 = remapindex_27 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3004 = remapindex_27 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3005 = remapindex_27 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3006 = remapindex_27 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3007 = remapindex_27 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3008 = remapindex_27 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3009 = remapindex_27 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_27 = _T_3009 ? _Queue64_UInt8_31_io_deq_bits : _T_3008 ? _Queue64_UInt8_30_io_deq_bits : _T_3007 ? _Queue64_UInt8_29_io_deq_bits : _T_3006 ? _Queue64_UInt8_28_io_deq_bits : _T_3005 ? _Queue64_UInt8_27_io_deq_bits : _T_3004 ? _Queue64_UInt8_26_io_deq_bits : _T_3003 ? _Queue64_UInt8_25_io_deq_bits : _T_3002 ? _Queue64_UInt8_24_io_deq_bits : _T_3001 ? _Queue64_UInt8_23_io_deq_bits : _T_3000 ? _Queue64_UInt8_22_io_deq_bits : _T_2999 ? _Queue64_UInt8_21_io_deq_bits : _T_2998 ? _Queue64_UInt8_20_io_deq_bits : _T_2997 ? _Queue64_UInt8_19_io_deq_bits : _T_2996 ? _Queue64_UInt8_18_io_deq_bits : _T_2995 ? _Queue64_UInt8_17_io_deq_bits : _T_2994 ? _Queue64_UInt8_16_io_deq_bits : _T_2993 ? _Queue64_UInt8_15_io_deq_bits : _T_2992 ? _Queue64_UInt8_14_io_deq_bits : _T_2991 ? _Queue64_UInt8_13_io_deq_bits : _T_2990 ? _Queue64_UInt8_12_io_deq_bits : _T_2989 ? _Queue64_UInt8_11_io_deq_bits : _T_2988 ? _Queue64_UInt8_10_io_deq_bits : _T_2987 ? _Queue64_UInt8_9_io_deq_bits : _T_2986 ? _Queue64_UInt8_8_io_deq_bits : _T_2985 ? _Queue64_UInt8_7_io_deq_bits : _T_2984 ? _Queue64_UInt8_6_io_deq_bits : _T_2983 ? _Queue64_UInt8_5_io_deq_bits : _T_2982 ? _Queue64_UInt8_4_io_deq_bits : _T_2981 ? _Queue64_UInt8_3_io_deq_bits : _T_2980 ? _Queue64_UInt8_2_io_deq_bits : _T_2979 ? _Queue64_UInt8_1_io_deq_bits : _T_2978 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_27 = _T_3009 ? _Queue64_UInt8_31_io_deq_valid : _T_3008 ? _Queue64_UInt8_30_io_deq_valid : _T_3007 ? _Queue64_UInt8_29_io_deq_valid : _T_3006 ? _Queue64_UInt8_28_io_deq_valid : _T_3005 ? _Queue64_UInt8_27_io_deq_valid : _T_3004 ? _Queue64_UInt8_26_io_deq_valid : _T_3003 ? _Queue64_UInt8_25_io_deq_valid : _T_3002 ? _Queue64_UInt8_24_io_deq_valid : _T_3001 ? _Queue64_UInt8_23_io_deq_valid : _T_3000 ? _Queue64_UInt8_22_io_deq_valid : _T_2999 ? _Queue64_UInt8_21_io_deq_valid : _T_2998 ? _Queue64_UInt8_20_io_deq_valid : _T_2997 ? _Queue64_UInt8_19_io_deq_valid : _T_2996 ? _Queue64_UInt8_18_io_deq_valid : _T_2995 ? _Queue64_UInt8_17_io_deq_valid : _T_2994 ? _Queue64_UInt8_16_io_deq_valid : _T_2993 ? _Queue64_UInt8_15_io_deq_valid : _T_2992 ? _Queue64_UInt8_14_io_deq_valid : _T_2991 ? _Queue64_UInt8_13_io_deq_valid : _T_2990 ? _Queue64_UInt8_12_io_deq_valid : _T_2989 ? _Queue64_UInt8_11_io_deq_valid : _T_2988 ? _Queue64_UInt8_10_io_deq_valid : _T_2987 ? _Queue64_UInt8_9_io_deq_valid : _T_2986 ? _Queue64_UInt8_8_io_deq_valid : _T_2985 ? _Queue64_UInt8_7_io_deq_valid : _T_2984 ? _Queue64_UInt8_6_io_deq_valid : _T_2983 ? _Queue64_UInt8_5_io_deq_valid : _T_2982 ? _Queue64_UInt8_4_io_deq_valid : _T_2981 ? _Queue64_UInt8_3_io_deq_valid : _T_2980 ? _Queue64_UInt8_2_io_deq_valid : _T_2979 ? _Queue64_UInt8_1_io_deq_valid : _T_2978 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_143 = 9'h23 - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_144 = _remapindex_T_143; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_71 = _remapindex_T_144 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_28 = _GEN_71[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_3010 = remapindex_28 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3011 = remapindex_28 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3012 = remapindex_28 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3013 = remapindex_28 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3014 = remapindex_28 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3015 = remapindex_28 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3016 = remapindex_28 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3017 = remapindex_28 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3018 = remapindex_28 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3019 = remapindex_28 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3020 = remapindex_28 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3021 = remapindex_28 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3022 = remapindex_28 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3023 = remapindex_28 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3024 = remapindex_28 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3025 = remapindex_28 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3026 = remapindex_28 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3027 = remapindex_28 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3028 = remapindex_28 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3029 = remapindex_28 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3030 = remapindex_28 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3031 = remapindex_28 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3032 = remapindex_28 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3033 = remapindex_28 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3034 = remapindex_28 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3035 = remapindex_28 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3036 = remapindex_28 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3037 = remapindex_28 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3038 = remapindex_28 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3039 = remapindex_28 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3040 = remapindex_28 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3041 = remapindex_28 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_28 = _T_3041 ? _Queue64_UInt8_31_io_deq_bits : _T_3040 ? _Queue64_UInt8_30_io_deq_bits : _T_3039 ? _Queue64_UInt8_29_io_deq_bits : _T_3038 ? _Queue64_UInt8_28_io_deq_bits : _T_3037 ? _Queue64_UInt8_27_io_deq_bits : _T_3036 ? _Queue64_UInt8_26_io_deq_bits : _T_3035 ? _Queue64_UInt8_25_io_deq_bits : _T_3034 ? _Queue64_UInt8_24_io_deq_bits : _T_3033 ? _Queue64_UInt8_23_io_deq_bits : _T_3032 ? _Queue64_UInt8_22_io_deq_bits : _T_3031 ? _Queue64_UInt8_21_io_deq_bits : _T_3030 ? _Queue64_UInt8_20_io_deq_bits : _T_3029 ? _Queue64_UInt8_19_io_deq_bits : _T_3028 ? _Queue64_UInt8_18_io_deq_bits : _T_3027 ? _Queue64_UInt8_17_io_deq_bits : _T_3026 ? _Queue64_UInt8_16_io_deq_bits : _T_3025 ? _Queue64_UInt8_15_io_deq_bits : _T_3024 ? _Queue64_UInt8_14_io_deq_bits : _T_3023 ? _Queue64_UInt8_13_io_deq_bits : _T_3022 ? _Queue64_UInt8_12_io_deq_bits : _T_3021 ? _Queue64_UInt8_11_io_deq_bits : _T_3020 ? _Queue64_UInt8_10_io_deq_bits : _T_3019 ? _Queue64_UInt8_9_io_deq_bits : _T_3018 ? _Queue64_UInt8_8_io_deq_bits : _T_3017 ? _Queue64_UInt8_7_io_deq_bits : _T_3016 ? _Queue64_UInt8_6_io_deq_bits : _T_3015 ? _Queue64_UInt8_5_io_deq_bits : _T_3014 ? _Queue64_UInt8_4_io_deq_bits : _T_3013 ? _Queue64_UInt8_3_io_deq_bits : _T_3012 ? _Queue64_UInt8_2_io_deq_bits : _T_3011 ? _Queue64_UInt8_1_io_deq_bits : _T_3010 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_28 = _T_3041 ? _Queue64_UInt8_31_io_deq_valid : _T_3040 ? _Queue64_UInt8_30_io_deq_valid : _T_3039 ? _Queue64_UInt8_29_io_deq_valid : _T_3038 ? _Queue64_UInt8_28_io_deq_valid : _T_3037 ? _Queue64_UInt8_27_io_deq_valid : _T_3036 ? _Queue64_UInt8_26_io_deq_valid : _T_3035 ? _Queue64_UInt8_25_io_deq_valid : _T_3034 ? _Queue64_UInt8_24_io_deq_valid : _T_3033 ? _Queue64_UInt8_23_io_deq_valid : _T_3032 ? _Queue64_UInt8_22_io_deq_valid : _T_3031 ? _Queue64_UInt8_21_io_deq_valid : _T_3030 ? _Queue64_UInt8_20_io_deq_valid : _T_3029 ? _Queue64_UInt8_19_io_deq_valid : _T_3028 ? _Queue64_UInt8_18_io_deq_valid : _T_3027 ? _Queue64_UInt8_17_io_deq_valid : _T_3026 ? _Queue64_UInt8_16_io_deq_valid : _T_3025 ? _Queue64_UInt8_15_io_deq_valid : _T_3024 ? _Queue64_UInt8_14_io_deq_valid : _T_3023 ? _Queue64_UInt8_13_io_deq_valid : _T_3022 ? _Queue64_UInt8_12_io_deq_valid : _T_3021 ? _Queue64_UInt8_11_io_deq_valid : _T_3020 ? _Queue64_UInt8_10_io_deq_valid : _T_3019 ? _Queue64_UInt8_9_io_deq_valid : _T_3018 ? _Queue64_UInt8_8_io_deq_valid : _T_3017 ? _Queue64_UInt8_7_io_deq_valid : _T_3016 ? _Queue64_UInt8_6_io_deq_valid : _T_3015 ? _Queue64_UInt8_5_io_deq_valid : _T_3014 ? _Queue64_UInt8_4_io_deq_valid : _T_3013 ? _Queue64_UInt8_3_io_deq_valid : _T_3012 ? _Queue64_UInt8_2_io_deq_valid : _T_3011 ? _Queue64_UInt8_1_io_deq_valid : _T_3010 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_148 = 9'h22 - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_149 = _remapindex_T_148; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_72 = _remapindex_T_149 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_29 = _GEN_72[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_3042 = remapindex_29 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3043 = remapindex_29 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3044 = remapindex_29 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3045 = remapindex_29 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3046 = remapindex_29 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3047 = remapindex_29 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3048 = remapindex_29 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3049 = remapindex_29 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3050 = remapindex_29 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3051 = remapindex_29 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3052 = remapindex_29 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3053 = remapindex_29 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3054 = remapindex_29 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3055 = remapindex_29 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3056 = remapindex_29 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3057 = remapindex_29 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3058 = remapindex_29 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3059 = remapindex_29 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3060 = remapindex_29 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3061 = remapindex_29 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3062 = remapindex_29 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3063 = remapindex_29 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3064 = remapindex_29 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3065 = remapindex_29 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3066 = remapindex_29 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3067 = remapindex_29 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3068 = remapindex_29 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3069 = remapindex_29 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3070 = remapindex_29 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3071 = remapindex_29 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3072 = remapindex_29 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3073 = remapindex_29 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_29 = _T_3073 ? _Queue64_UInt8_31_io_deq_bits : _T_3072 ? _Queue64_UInt8_30_io_deq_bits : _T_3071 ? _Queue64_UInt8_29_io_deq_bits : _T_3070 ? _Queue64_UInt8_28_io_deq_bits : _T_3069 ? _Queue64_UInt8_27_io_deq_bits : _T_3068 ? _Queue64_UInt8_26_io_deq_bits : _T_3067 ? _Queue64_UInt8_25_io_deq_bits : _T_3066 ? _Queue64_UInt8_24_io_deq_bits : _T_3065 ? _Queue64_UInt8_23_io_deq_bits : _T_3064 ? _Queue64_UInt8_22_io_deq_bits : _T_3063 ? _Queue64_UInt8_21_io_deq_bits : _T_3062 ? _Queue64_UInt8_20_io_deq_bits : _T_3061 ? _Queue64_UInt8_19_io_deq_bits : _T_3060 ? _Queue64_UInt8_18_io_deq_bits : _T_3059 ? _Queue64_UInt8_17_io_deq_bits : _T_3058 ? _Queue64_UInt8_16_io_deq_bits : _T_3057 ? _Queue64_UInt8_15_io_deq_bits : _T_3056 ? _Queue64_UInt8_14_io_deq_bits : _T_3055 ? _Queue64_UInt8_13_io_deq_bits : _T_3054 ? _Queue64_UInt8_12_io_deq_bits : _T_3053 ? _Queue64_UInt8_11_io_deq_bits : _T_3052 ? _Queue64_UInt8_10_io_deq_bits : _T_3051 ? _Queue64_UInt8_9_io_deq_bits : _T_3050 ? _Queue64_UInt8_8_io_deq_bits : _T_3049 ? _Queue64_UInt8_7_io_deq_bits : _T_3048 ? _Queue64_UInt8_6_io_deq_bits : _T_3047 ? _Queue64_UInt8_5_io_deq_bits : _T_3046 ? _Queue64_UInt8_4_io_deq_bits : _T_3045 ? _Queue64_UInt8_3_io_deq_bits : _T_3044 ? _Queue64_UInt8_2_io_deq_bits : _T_3043 ? _Queue64_UInt8_1_io_deq_bits : _T_3042 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_29 = _T_3073 ? _Queue64_UInt8_31_io_deq_valid : _T_3072 ? _Queue64_UInt8_30_io_deq_valid : _T_3071 ? _Queue64_UInt8_29_io_deq_valid : _T_3070 ? _Queue64_UInt8_28_io_deq_valid : _T_3069 ? _Queue64_UInt8_27_io_deq_valid : _T_3068 ? _Queue64_UInt8_26_io_deq_valid : _T_3067 ? _Queue64_UInt8_25_io_deq_valid : _T_3066 ? _Queue64_UInt8_24_io_deq_valid : _T_3065 ? _Queue64_UInt8_23_io_deq_valid : _T_3064 ? _Queue64_UInt8_22_io_deq_valid : _T_3063 ? _Queue64_UInt8_21_io_deq_valid : _T_3062 ? _Queue64_UInt8_20_io_deq_valid : _T_3061 ? _Queue64_UInt8_19_io_deq_valid : _T_3060 ? _Queue64_UInt8_18_io_deq_valid : _T_3059 ? _Queue64_UInt8_17_io_deq_valid : _T_3058 ? _Queue64_UInt8_16_io_deq_valid : _T_3057 ? _Queue64_UInt8_15_io_deq_valid : _T_3056 ? _Queue64_UInt8_14_io_deq_valid : _T_3055 ? _Queue64_UInt8_13_io_deq_valid : _T_3054 ? _Queue64_UInt8_12_io_deq_valid : _T_3053 ? _Queue64_UInt8_11_io_deq_valid : _T_3052 ? _Queue64_UInt8_10_io_deq_valid : _T_3051 ? _Queue64_UInt8_9_io_deq_valid : _T_3050 ? _Queue64_UInt8_8_io_deq_valid : _T_3049 ? _Queue64_UInt8_7_io_deq_valid : _T_3048 ? _Queue64_UInt8_6_io_deq_valid : _T_3047 ? _Queue64_UInt8_5_io_deq_valid : _T_3046 ? _Queue64_UInt8_4_io_deq_valid : _T_3045 ? _Queue64_UInt8_3_io_deq_valid : _T_3044 ? _Queue64_UInt8_2_io_deq_valid : _T_3043 ? _Queue64_UInt8_1_io_deq_valid : _T_3042 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_153 = 9'h21 - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_154 = _remapindex_T_153; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_73 = _remapindex_T_154 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_30 = _GEN_73[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_3074 = remapindex_30 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3075 = remapindex_30 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3076 = remapindex_30 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3077 = remapindex_30 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3078 = remapindex_30 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3079 = remapindex_30 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3080 = remapindex_30 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3081 = remapindex_30 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3082 = remapindex_30 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3083 = remapindex_30 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3084 = remapindex_30 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3085 = remapindex_30 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3086 = remapindex_30 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3087 = remapindex_30 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3088 = remapindex_30 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3089 = remapindex_30 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3090 = remapindex_30 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3091 = remapindex_30 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3092 = remapindex_30 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3093 = remapindex_30 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3094 = remapindex_30 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3095 = remapindex_30 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3096 = remapindex_30 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3097 = remapindex_30 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3098 = remapindex_30 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3099 = remapindex_30 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3100 = remapindex_30 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3101 = remapindex_30 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3102 = remapindex_30 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3103 = remapindex_30 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3104 = remapindex_30 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3105 = remapindex_30 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_30 = _T_3105 ? _Queue64_UInt8_31_io_deq_bits : _T_3104 ? _Queue64_UInt8_30_io_deq_bits : _T_3103 ? _Queue64_UInt8_29_io_deq_bits : _T_3102 ? _Queue64_UInt8_28_io_deq_bits : _T_3101 ? _Queue64_UInt8_27_io_deq_bits : _T_3100 ? _Queue64_UInt8_26_io_deq_bits : _T_3099 ? _Queue64_UInt8_25_io_deq_bits : _T_3098 ? _Queue64_UInt8_24_io_deq_bits : _T_3097 ? _Queue64_UInt8_23_io_deq_bits : _T_3096 ? _Queue64_UInt8_22_io_deq_bits : _T_3095 ? _Queue64_UInt8_21_io_deq_bits : _T_3094 ? _Queue64_UInt8_20_io_deq_bits : _T_3093 ? _Queue64_UInt8_19_io_deq_bits : _T_3092 ? _Queue64_UInt8_18_io_deq_bits : _T_3091 ? _Queue64_UInt8_17_io_deq_bits : _T_3090 ? _Queue64_UInt8_16_io_deq_bits : _T_3089 ? _Queue64_UInt8_15_io_deq_bits : _T_3088 ? _Queue64_UInt8_14_io_deq_bits : _T_3087 ? _Queue64_UInt8_13_io_deq_bits : _T_3086 ? _Queue64_UInt8_12_io_deq_bits : _T_3085 ? _Queue64_UInt8_11_io_deq_bits : _T_3084 ? _Queue64_UInt8_10_io_deq_bits : _T_3083 ? _Queue64_UInt8_9_io_deq_bits : _T_3082 ? _Queue64_UInt8_8_io_deq_bits : _T_3081 ? _Queue64_UInt8_7_io_deq_bits : _T_3080 ? _Queue64_UInt8_6_io_deq_bits : _T_3079 ? _Queue64_UInt8_5_io_deq_bits : _T_3078 ? _Queue64_UInt8_4_io_deq_bits : _T_3077 ? _Queue64_UInt8_3_io_deq_bits : _T_3076 ? _Queue64_UInt8_2_io_deq_bits : _T_3075 ? _Queue64_UInt8_1_io_deq_bits : _T_3074 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_30 = _T_3105 ? _Queue64_UInt8_31_io_deq_valid : _T_3104 ? _Queue64_UInt8_30_io_deq_valid : _T_3103 ? _Queue64_UInt8_29_io_deq_valid : _T_3102 ? _Queue64_UInt8_28_io_deq_valid : _T_3101 ? _Queue64_UInt8_27_io_deq_valid : _T_3100 ? _Queue64_UInt8_26_io_deq_valid : _T_3099 ? _Queue64_UInt8_25_io_deq_valid : _T_3098 ? _Queue64_UInt8_24_io_deq_valid : _T_3097 ? _Queue64_UInt8_23_io_deq_valid : _T_3096 ? _Queue64_UInt8_22_io_deq_valid : _T_3095 ? _Queue64_UInt8_21_io_deq_valid : _T_3094 ? _Queue64_UInt8_20_io_deq_valid : _T_3093 ? _Queue64_UInt8_19_io_deq_valid : _T_3092 ? _Queue64_UInt8_18_io_deq_valid : _T_3091 ? _Queue64_UInt8_17_io_deq_valid : _T_3090 ? _Queue64_UInt8_16_io_deq_valid : _T_3089 ? _Queue64_UInt8_15_io_deq_valid : _T_3088 ? _Queue64_UInt8_14_io_deq_valid : _T_3087 ? _Queue64_UInt8_13_io_deq_valid : _T_3086 ? _Queue64_UInt8_12_io_deq_valid : _T_3085 ? _Queue64_UInt8_11_io_deq_valid : _T_3084 ? _Queue64_UInt8_10_io_deq_valid : _T_3083 ? _Queue64_UInt8_9_io_deq_valid : _T_3082 ? _Queue64_UInt8_8_io_deq_valid : _T_3081 ? _Queue64_UInt8_7_io_deq_valid : _T_3080 ? _Queue64_UInt8_6_io_deq_valid : _T_3079 ? _Queue64_UInt8_5_io_deq_valid : _T_3078 ? _Queue64_UInt8_4_io_deq_valid : _T_3077 ? _Queue64_UInt8_3_io_deq_valid : _T_3076 ? _Queue64_UInt8_2_io_deq_valid : _T_3075 ? _Queue64_UInt8_1_io_deq_valid : _T_3074 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [8:0] _remapindex_T_158 = 9'h20 - _GEN_42; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _remapindex_T_159 = _remapindex_T_158; // @[ReverseMemLoader.scala:172:66]
wire [8:0] _GEN_74 = _remapindex_T_159 % 9'h20; // @[ReverseMemLoader.scala:172:{66,87}]
wire [5:0] remapindex_31 = _GEN_74[5:0]; // @[ReverseMemLoader.scala:172:87]
wire _T_3106 = remapindex_31 == 6'h0; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3107 = remapindex_31 == 6'h1; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3108 = remapindex_31 == 6'h2; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3109 = remapindex_31 == 6'h3; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3110 = remapindex_31 == 6'h4; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3111 = remapindex_31 == 6'h5; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3112 = remapindex_31 == 6'h6; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3113 = remapindex_31 == 6'h7; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3114 = remapindex_31 == 6'h8; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3115 = remapindex_31 == 6'h9; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3116 = remapindex_31 == 6'hA; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3117 = remapindex_31 == 6'hB; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3118 = remapindex_31 == 6'hC; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3119 = remapindex_31 == 6'hD; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3120 = remapindex_31 == 6'hE; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3121 = remapindex_31 == 6'hF; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3122 = remapindex_31 == 6'h10; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3123 = remapindex_31 == 6'h11; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3124 = remapindex_31 == 6'h12; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3125 = remapindex_31 == 6'h13; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3126 = remapindex_31 == 6'h14; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3127 = remapindex_31 == 6'h15; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3128 = remapindex_31 == 6'h16; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3129 = remapindex_31 == 6'h17; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3130 = remapindex_31 == 6'h18; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3131 = remapindex_31 == 6'h19; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3132 = remapindex_31 == 6'h1A; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3133 = remapindex_31 == 6'h1B; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3134 = remapindex_31 == 6'h1C; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3135 = remapindex_31 == 6'h1D; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3136 = remapindex_31 == 6'h1E; // @[ReverseMemLoader.scala:172:87, :174:17]
wire _T_3137 = remapindex_31 == 6'h1F; // @[ReverseMemLoader.scala:172:87, :174:17]
assign remapVecData_31 = _T_3137 ? _Queue64_UInt8_31_io_deq_bits : _T_3136 ? _Queue64_UInt8_30_io_deq_bits : _T_3135 ? _Queue64_UInt8_29_io_deq_bits : _T_3134 ? _Queue64_UInt8_28_io_deq_bits : _T_3133 ? _Queue64_UInt8_27_io_deq_bits : _T_3132 ? _Queue64_UInt8_26_io_deq_bits : _T_3131 ? _Queue64_UInt8_25_io_deq_bits : _T_3130 ? _Queue64_UInt8_24_io_deq_bits : _T_3129 ? _Queue64_UInt8_23_io_deq_bits : _T_3128 ? _Queue64_UInt8_22_io_deq_bits : _T_3127 ? _Queue64_UInt8_21_io_deq_bits : _T_3126 ? _Queue64_UInt8_20_io_deq_bits : _T_3125 ? _Queue64_UInt8_19_io_deq_bits : _T_3124 ? _Queue64_UInt8_18_io_deq_bits : _T_3123 ? _Queue64_UInt8_17_io_deq_bits : _T_3122 ? _Queue64_UInt8_16_io_deq_bits : _T_3121 ? _Queue64_UInt8_15_io_deq_bits : _T_3120 ? _Queue64_UInt8_14_io_deq_bits : _T_3119 ? _Queue64_UInt8_13_io_deq_bits : _T_3118 ? _Queue64_UInt8_12_io_deq_bits : _T_3117 ? _Queue64_UInt8_11_io_deq_bits : _T_3116 ? _Queue64_UInt8_10_io_deq_bits : _T_3115 ? _Queue64_UInt8_9_io_deq_bits : _T_3114 ? _Queue64_UInt8_8_io_deq_bits : _T_3113 ? _Queue64_UInt8_7_io_deq_bits : _T_3112 ? _Queue64_UInt8_6_io_deq_bits : _T_3111 ? _Queue64_UInt8_5_io_deq_bits : _T_3110 ? _Queue64_UInt8_4_io_deq_bits : _T_3109 ? _Queue64_UInt8_3_io_deq_bits : _T_3108 ? _Queue64_UInt8_2_io_deq_bits : _T_3107 ? _Queue64_UInt8_1_io_deq_bits : _T_3106 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[ReverseMemLoader.scala:104:52, :161:26, :166:27, :174:{17,33}, :175:31]
assign remapVecValids_31 = _T_3137 ? _Queue64_UInt8_31_io_deq_valid : _T_3136 ? _Queue64_UInt8_30_io_deq_valid : _T_3135 ? _Queue64_UInt8_29_io_deq_valid : _T_3134 ? _Queue64_UInt8_28_io_deq_valid : _T_3133 ? _Queue64_UInt8_27_io_deq_valid : _T_3132 ? _Queue64_UInt8_26_io_deq_valid : _T_3131 ? _Queue64_UInt8_25_io_deq_valid : _T_3130 ? _Queue64_UInt8_24_io_deq_valid : _T_3129 ? _Queue64_UInt8_23_io_deq_valid : _T_3128 ? _Queue64_UInt8_22_io_deq_valid : _T_3127 ? _Queue64_UInt8_21_io_deq_valid : _T_3126 ? _Queue64_UInt8_20_io_deq_valid : _T_3125 ? _Queue64_UInt8_19_io_deq_valid : _T_3124 ? _Queue64_UInt8_18_io_deq_valid : _T_3123 ? _Queue64_UInt8_17_io_deq_valid : _T_3122 ? _Queue64_UInt8_16_io_deq_valid : _T_3121 ? _Queue64_UInt8_15_io_deq_valid : _T_3120 ? _Queue64_UInt8_14_io_deq_valid : _T_3119 ? _Queue64_UInt8_13_io_deq_valid : _T_3118 ? _Queue64_UInt8_12_io_deq_valid : _T_3117 ? _Queue64_UInt8_11_io_deq_valid : _T_3116 ? _Queue64_UInt8_10_io_deq_valid : _T_3115 ? _Queue64_UInt8_9_io_deq_valid : _T_3114 ? _Queue64_UInt8_8_io_deq_valid : _T_3113 ? _Queue64_UInt8_7_io_deq_valid : _T_3112 ? _Queue64_UInt8_6_io_deq_valid : _T_3111 ? _Queue64_UInt8_5_io_deq_valid : _T_3110 ? _Queue64_UInt8_4_io_deq_valid : _T_3109 ? _Queue64_UInt8_3_io_deq_valid : _T_3108 ? _Queue64_UInt8_2_io_deq_valid : _T_3107 ? _Queue64_UInt8_1_io_deq_valid : _T_3106 & _Queue64_UInt8_io_deq_valid; // @[ReverseMemLoader.scala:104:52, :162:28, :167:29, :174:{17,33}, :176:33]
wire [15:0] io_consumer_output_data_lo_lo_lo_lo = {remapVecData_30, remapVecData_31}; // @[ReverseMemLoader.scala:161:26, :181:33]
wire [15:0] io_consumer_output_data_lo_lo_lo_hi = {remapVecData_28, remapVecData_29}; // @[ReverseMemLoader.scala:161:26, :181:33]
wire [31:0] io_consumer_output_data_lo_lo_lo = {io_consumer_output_data_lo_lo_lo_hi, io_consumer_output_data_lo_lo_lo_lo}; // @[ReverseMemLoader.scala:181:33]
wire [15:0] io_consumer_output_data_lo_lo_hi_lo = {remapVecData_26, remapVecData_27}; // @[ReverseMemLoader.scala:161:26, :181:33]
wire [15:0] io_consumer_output_data_lo_lo_hi_hi = {remapVecData_24, remapVecData_25}; // @[ReverseMemLoader.scala:161:26, :181:33]
wire [31:0] io_consumer_output_data_lo_lo_hi = {io_consumer_output_data_lo_lo_hi_hi, io_consumer_output_data_lo_lo_hi_lo}; // @[ReverseMemLoader.scala:181:33]
wire [63:0] io_consumer_output_data_lo_lo = {io_consumer_output_data_lo_lo_hi, io_consumer_output_data_lo_lo_lo}; // @[ReverseMemLoader.scala:181:33]
wire [15:0] io_consumer_output_data_lo_hi_lo_lo = {remapVecData_22, remapVecData_23}; // @[ReverseMemLoader.scala:161:26, :181:33]
wire [15:0] io_consumer_output_data_lo_hi_lo_hi = {remapVecData_20, remapVecData_21}; // @[ReverseMemLoader.scala:161:26, :181:33]
wire [31:0] io_consumer_output_data_lo_hi_lo = {io_consumer_output_data_lo_hi_lo_hi, io_consumer_output_data_lo_hi_lo_lo}; // @[ReverseMemLoader.scala:181:33]
wire [15:0] io_consumer_output_data_lo_hi_hi_lo = {remapVecData_18, remapVecData_19}; // @[ReverseMemLoader.scala:161:26, :181:33]
wire [15:0] io_consumer_output_data_lo_hi_hi_hi = {remapVecData_16, remapVecData_17}; // @[ReverseMemLoader.scala:161:26, :181:33]
wire [31:0] io_consumer_output_data_lo_hi_hi = {io_consumer_output_data_lo_hi_hi_hi, io_consumer_output_data_lo_hi_hi_lo}; // @[ReverseMemLoader.scala:181:33]
wire [63:0] io_consumer_output_data_lo_hi = {io_consumer_output_data_lo_hi_hi, io_consumer_output_data_lo_hi_lo}; // @[ReverseMemLoader.scala:181:33]
wire [127:0] io_consumer_output_data_lo = {io_consumer_output_data_lo_hi, io_consumer_output_data_lo_lo}; // @[ReverseMemLoader.scala:181:33]
wire [15:0] io_consumer_output_data_hi_lo_lo_lo = {remapVecData_14, remapVecData_15}; // @[ReverseMemLoader.scala:161:26, :181:33]
wire [15:0] io_consumer_output_data_hi_lo_lo_hi = {remapVecData_12, remapVecData_13}; // @[ReverseMemLoader.scala:161:26, :181:33]
wire [31:0] io_consumer_output_data_hi_lo_lo = {io_consumer_output_data_hi_lo_lo_hi, io_consumer_output_data_hi_lo_lo_lo}; // @[ReverseMemLoader.scala:181:33]
wire [15:0] io_consumer_output_data_hi_lo_hi_lo = {remapVecData_10, remapVecData_11}; // @[ReverseMemLoader.scala:161:26, :181:33]
wire [15:0] io_consumer_output_data_hi_lo_hi_hi = {remapVecData_8, remapVecData_9}; // @[ReverseMemLoader.scala:161:26, :181:33]
wire [31:0] io_consumer_output_data_hi_lo_hi = {io_consumer_output_data_hi_lo_hi_hi, io_consumer_output_data_hi_lo_hi_lo}; // @[ReverseMemLoader.scala:181:33]
wire [63:0] io_consumer_output_data_hi_lo = {io_consumer_output_data_hi_lo_hi, io_consumer_output_data_hi_lo_lo}; // @[ReverseMemLoader.scala:181:33]
wire [15:0] io_consumer_output_data_hi_hi_lo_lo = {remapVecData_6, remapVecData_7}; // @[ReverseMemLoader.scala:161:26, :181:33]
wire [15:0] io_consumer_output_data_hi_hi_lo_hi = {remapVecData_4, remapVecData_5}; // @[ReverseMemLoader.scala:161:26, :181:33]
wire [31:0] io_consumer_output_data_hi_hi_lo = {io_consumer_output_data_hi_hi_lo_hi, io_consumer_output_data_hi_hi_lo_lo}; // @[ReverseMemLoader.scala:181:33]
wire [15:0] io_consumer_output_data_hi_hi_hi_lo = {remapVecData_2, remapVecData_3}; // @[ReverseMemLoader.scala:161:26, :181:33]
wire [15:0] io_consumer_output_data_hi_hi_hi_hi = {remapVecData_0, remapVecData_1}; // @[ReverseMemLoader.scala:161:26, :181:33]
wire [31:0] io_consumer_output_data_hi_hi_hi = {io_consumer_output_data_hi_hi_hi_hi, io_consumer_output_data_hi_hi_hi_lo}; // @[ReverseMemLoader.scala:181:33]
wire [63:0] io_consumer_output_data_hi_hi = {io_consumer_output_data_hi_hi_hi, io_consumer_output_data_hi_hi_lo}; // @[ReverseMemLoader.scala:181:33]
wire [127:0] io_consumer_output_data_hi = {io_consumer_output_data_hi_hi, io_consumer_output_data_hi_lo}; // @[ReverseMemLoader.scala:181:33]
assign _io_consumer_output_data_T = {io_consumer_output_data_hi, io_consumer_output_data_lo}; // @[ReverseMemLoader.scala:181:33]
assign io_consumer_output_data_0 = _io_consumer_output_data_T; // @[ReverseMemLoader.scala:13:7, :181:33]
wire [64:0] _GEN_75 = {1'h0, len_already_consumed}; // @[ReverseMemLoader.scala:159:37, :183:40]
wire [64:0] _GEN_76 = _GEN_75 + 65'hC; // @[ReverseMemLoader.scala:183:40]
wire [64:0] _buf_last_T; // @[ReverseMemLoader.scala:183:40]
assign _buf_last_T = _GEN_76; // @[ReverseMemLoader.scala:183:40]
wire [64:0] _len_already_consumed_T; // @[ReverseMemLoader.scala:223:52]
assign _len_already_consumed_T = _GEN_76; // @[ReverseMemLoader.scala:183:40, :223:52]
wire [63:0] _buf_last_T_1 = _buf_last_T[63:0]; // @[ReverseMemLoader.scala:183:40]
wire buf_last = _buf_last_T_1 == _buf_info_queue_io_deq_bits_len_bytes; // @[ReverseMemLoader.scala:23:30, :183:{40,75}]
wire [1:0] _count_valids_T = {1'h0, remapVecValids_0} + {1'h0, remapVecValids_1}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [2:0] _count_valids_T_1 = {1'h0, _count_valids_T} + {2'h0, remapVecValids_2}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [3:0] _count_valids_T_2 = {1'h0, _count_valids_T_1} + {3'h0, remapVecValids_3}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [4:0] _count_valids_T_3 = {1'h0, _count_valids_T_2} + {4'h0, remapVecValids_4}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [5:0] _count_valids_T_4 = {1'h0, _count_valids_T_3} + {5'h0, remapVecValids_5}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [6:0] _count_valids_T_5 = {1'h0, _count_valids_T_4} + {6'h0, remapVecValids_6}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [7:0] _count_valids_T_6 = {1'h0, _count_valids_T_5} + {7'h0, remapVecValids_7}; // @[ReverseMemLoader.scala:115:67, :162:28, :184:60]
wire [8:0] _count_valids_T_7 = {1'h0, _count_valids_T_6} + {8'h0, remapVecValids_8}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [9:0] _count_valids_T_8 = {1'h0, _count_valids_T_7} + {9'h0, remapVecValids_9}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [10:0] _count_valids_T_9 = {1'h0, _count_valids_T_8} + {10'h0, remapVecValids_10}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [11:0] _count_valids_T_10 = {1'h0, _count_valids_T_9} + {11'h0, remapVecValids_11}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [12:0] _count_valids_T_11 = {1'h0, _count_valids_T_10} + {12'h0, remapVecValids_12}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [13:0] _count_valids_T_12 = {1'h0, _count_valids_T_11} + {13'h0, remapVecValids_13}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [14:0] _count_valids_T_13 = {1'h0, _count_valids_T_12} + {14'h0, remapVecValids_14}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [15:0] _count_valids_T_14 = {1'h0, _count_valids_T_13} + {15'h0, remapVecValids_15}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [16:0] _count_valids_T_15 = {1'h0, _count_valids_T_14} + {16'h0, remapVecValids_16}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [17:0] _count_valids_T_16 = {1'h0, _count_valids_T_15} + {17'h0, remapVecValids_17}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [18:0] _count_valids_T_17 = {1'h0, _count_valids_T_16} + {18'h0, remapVecValids_18}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [19:0] _count_valids_T_18 = {1'h0, _count_valids_T_17} + {19'h0, remapVecValids_19}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [20:0] _count_valids_T_19 = {1'h0, _count_valids_T_18} + {20'h0, remapVecValids_20}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [21:0] _count_valids_T_20 = {1'h0, _count_valids_T_19} + {21'h0, remapVecValids_21}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [22:0] _count_valids_T_21 = {1'h0, _count_valids_T_20} + {22'h0, remapVecValids_22}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [23:0] _count_valids_T_22 = {1'h0, _count_valids_T_21} + {23'h0, remapVecValids_23}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [24:0] _count_valids_T_23 = {1'h0, _count_valids_T_22} + {24'h0, remapVecValids_24}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [25:0] _count_valids_T_24 = {1'h0, _count_valids_T_23} + {25'h0, remapVecValids_25}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [26:0] _count_valids_T_25 = {1'h0, _count_valids_T_24} + {26'h0, remapVecValids_26}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [27:0] _count_valids_T_26 = {1'h0, _count_valids_T_25} + {27'h0, remapVecValids_27}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [28:0] _count_valids_T_27 = {1'h0, _count_valids_T_26} + {28'h0, remapVecValids_28}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [29:0] _count_valids_T_28 = {1'h0, _count_valids_T_27} + {29'h0, remapVecValids_29}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [30:0] _count_valids_T_29 = {1'h0, _count_valids_T_28} + {30'h0, remapVecValids_30}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [31:0] count_valids = {1'h0, _count_valids_T_29} + {31'h0, remapVecValids_31}; // @[ReverseMemLoader.scala:162:28, :184:60]
wire [64:0] _unconsumed_bytes_so_far_T = {1'h0, _buf_info_queue_io_deq_bits_len_bytes} - _GEN_75; // @[ReverseMemLoader.scala:23:30, :183:40, :185:70]
wire [63:0] unconsumed_bytes_so_far = _unconsumed_bytes_so_far_T[63:0]; // @[ReverseMemLoader.scala:185:70]
wire _enough_data_T = |(unconsumed_bytes_so_far[63:5]); // @[ReverseMemLoader.scala:185:70, :186:49]
wire _enough_data_T_1 = count_valids == 32'h20; // @[ReverseMemLoader.scala:184:60, :187:38]
wire _enough_data_T_2 = {32'h0, count_valids} >= unconsumed_bytes_so_far; // @[ReverseMemLoader.scala:184:60, :185:70, :188:38]
wire enough_data = _enough_data_T ? _enough_data_T_1 : _enough_data_T_2; // @[ReverseMemLoader.scala:186:{24,49}, :187:38, :188:38]
wire _io_consumer_available_output_bytes_T = |(unconsumed_bytes_so_far[63:5]); // @[ReverseMemLoader.scala:185:70, :186:49, :190:69]
wire [63:0] _io_consumer_available_output_bytes_T_1 = _io_consumer_available_output_bytes_T ? 64'h20 : unconsumed_bytes_so_far; // @[ReverseMemLoader.scala:185:70, :190:{44,69}]
assign io_consumer_available_output_bytes_0 = _io_consumer_available_output_bytes_T_1[5:0]; // @[ReverseMemLoader.scala:13:7, :190:{38,44}]
assign _io_consumer_output_last_chunk_T = unconsumed_bytes_so_far < 64'h21; // @[ReverseMemLoader.scala:185:70, :194:61]
assign io_consumer_output_last_chunk_0 = _io_consumer_output_last_chunk_T; // @[ReverseMemLoader.scala:13:7, :194:61]
wire _T_3146 = io_consumer_output_ready_0 & _buf_info_queue_io_deq_valid; // @[Misc.scala:29:18]
wire _remapVecReadys_0_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_0_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_1_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_1_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_2_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_2_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_3_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_3_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_4_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_4_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_5_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_5_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_6_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_6_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_7_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_7_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_8_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_8_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_9_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_9_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_10_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_10_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_11_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_11_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_12_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_12_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_13_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_13_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_14_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_14_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_15_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_15_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_16_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_16_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_17_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_17_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_18_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_18_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_19_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_19_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_20_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_20_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_21_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_21_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_22_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_22_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_23_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_23_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_24_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_24_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_25_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_25_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_26_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_26_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_27_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_27_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_28_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_28_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_29_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_29_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_30_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_30_T_1 = _T_3146; // @[Misc.scala:29:18]
wire _remapVecReadys_31_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_31_T_1 = _T_3146; // @[Misc.scala:29:18]
reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_28 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>}
node _reg_T = asAsyncReset(reset)
regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0)
when io.en :
connect reg, io.d
connect io.q, reg | module AsyncResetRegVec_w1_i0_28( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input reset // @[AsyncResetReg.scala:56:7]
);
wire _reg_T = reset; // @[AsyncResetReg.scala:61:29]
wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14]
wire io_d = 1'h0; // @[AsyncResetReg.scala:56:7]
wire io_q = 1'h0; // @[AsyncResetReg.scala:56:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PixelRepeater :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { in : { bits : UInt<32>}[4], mask : UInt<1>[16], laddr : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, len : UInt<3>, pixel_repeats : UInt<8>, last : UInt<1>, tag : { vaddr : UInt<40>, laddr : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, cols : UInt<16>, repeats : UInt<16>, scale : UInt<32>, has_acc_bitwidth : UInt<1>, all_zeros : UInt<1>, block_stride : UInt<16>, pixel_repeats : UInt<8>, cmd_id : UInt<8>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { out : { bits : UInt<32>}[4], mask : UInt<1>[16], laddr : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, last : UInt<1>, tag : { vaddr : UInt<40>, laddr : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, cols : UInt<16>, repeats : UInt<16>, scale : UInt<32>, has_acc_bitwidth : UInt<1>, all_zeros : UInt<1>, block_stride : UInt<16>, pixel_repeats : UInt<8>, cmd_id : UInt<8>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}}}
reg req : { valid : UInt<1>, bits : { in : { bits : UInt<32>}[4], mask : UInt<1>[16], laddr : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, len : UInt<3>, pixel_repeats : UInt<8>, last : UInt<1>, tag : { vaddr : UInt<40>, laddr : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, cols : UInt<16>, repeats : UInt<16>, scale : UInt<32>, has_acc_bitwidth : UInt<1>, all_zeros : UInt<1>, block_stride : UInt<16>, pixel_repeats : UInt<8>, cmd_id : UInt<8>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}}, clock
node _io_req_ready_T = eq(req.valid, UInt<1>(0h0))
node _io_req_ready_T_1 = eq(req.bits.pixel_repeats, UInt<1>(0h0))
node _io_req_ready_T_2 = and(io.resp.ready, _io_req_ready_T_1)
node _io_req_ready_T_3 = or(_io_req_ready_T, _io_req_ready_T_2)
connect io.req.ready, _io_req_ready_T_3
wire out_shift : UInt<2>
node _out_shift_T = mul(req.bits.pixel_repeats, req.bits.len)
connect out_shift, _out_shift_T
node lo = cat(req.bits.in[1].bits, req.bits.in[0].bits)
node hi = cat(req.bits.in[3].bits, req.bits.in[2].bits)
node _T = cat(hi, lo)
node _T_1 = mul(out_shift, UInt<6>(0h20))
node _T_2 = dshl(_T, _T_1)
wire _WIRE : { bits : UInt<32>}[4]
wire _WIRE_1 : UInt<128>
connect _WIRE_1, _T_2
node _T_3 = bits(_WIRE_1, 31, 0)
connect _WIRE[0].bits, _T_3
node _T_4 = bits(_WIRE_1, 63, 32)
connect _WIRE[1].bits, _T_4
node _T_5 = bits(_WIRE_1, 95, 64)
connect _WIRE[2].bits, _T_5
node _T_6 = bits(_WIRE_1, 127, 96)
connect _WIRE[3].bits, _T_6
connect io.resp.bits.out, _WIRE
node lo_lo_lo = cat(req.bits.mask[1], req.bits.mask[0])
node lo_lo_hi = cat(req.bits.mask[3], req.bits.mask[2])
node lo_lo = cat(lo_lo_hi, lo_lo_lo)
node lo_hi_lo = cat(req.bits.mask[5], req.bits.mask[4])
node lo_hi_hi = cat(req.bits.mask[7], req.bits.mask[6])
node lo_hi = cat(lo_hi_hi, lo_hi_lo)
node lo_1 = cat(lo_hi, lo_lo)
node hi_lo_lo = cat(req.bits.mask[9], req.bits.mask[8])
node hi_lo_hi = cat(req.bits.mask[11], req.bits.mask[10])
node hi_lo = cat(hi_lo_hi, hi_lo_lo)
node hi_hi_lo = cat(req.bits.mask[13], req.bits.mask[12])
node hi_hi_hi = cat(req.bits.mask[15], req.bits.mask[14])
node hi_hi = cat(hi_hi_hi, hi_hi_lo)
node hi_1 = cat(hi_hi, hi_lo)
node _T_7 = cat(hi_1, lo_1)
node _T_8 = mul(out_shift, UInt<3>(0h4))
node _T_9 = dshl(_T_7, _T_8)
wire _WIRE_2 : UInt<1>[16]
wire _WIRE_3 : UInt<16>
connect _WIRE_3, _T_9
node _T_10 = bits(_WIRE_3, 0, 0)
connect _WIRE_2[0], _T_10
node _T_11 = bits(_WIRE_3, 1, 1)
connect _WIRE_2[1], _T_11
node _T_12 = bits(_WIRE_3, 2, 2)
connect _WIRE_2[2], _T_12
node _T_13 = bits(_WIRE_3, 3, 3)
connect _WIRE_2[3], _T_13
node _T_14 = bits(_WIRE_3, 4, 4)
connect _WIRE_2[4], _T_14
node _T_15 = bits(_WIRE_3, 5, 5)
connect _WIRE_2[5], _T_15
node _T_16 = bits(_WIRE_3, 6, 6)
connect _WIRE_2[6], _T_16
node _T_17 = bits(_WIRE_3, 7, 7)
connect _WIRE_2[7], _T_17
node _T_18 = bits(_WIRE_3, 8, 8)
connect _WIRE_2[8], _T_18
node _T_19 = bits(_WIRE_3, 9, 9)
connect _WIRE_2[9], _T_19
node _T_20 = bits(_WIRE_3, 10, 10)
connect _WIRE_2[10], _T_20
node _T_21 = bits(_WIRE_3, 11, 11)
connect _WIRE_2[11], _T_21
node _T_22 = bits(_WIRE_3, 12, 12)
connect _WIRE_2[12], _T_22
node _T_23 = bits(_WIRE_3, 13, 13)
connect _WIRE_2[13], _T_23
node _T_24 = bits(_WIRE_3, 14, 14)
connect _WIRE_2[14], _T_24
node _T_25 = bits(_WIRE_3, 15, 15)
connect _WIRE_2[15], _T_25
connect io.resp.bits.mask, _WIRE_2
node _io_resp_bits_last_T = eq(req.bits.pixel_repeats, UInt<1>(0h0))
node _io_resp_bits_last_T_1 = and(req.bits.last, _io_resp_bits_last_T)
connect io.resp.bits.last, _io_resp_bits_last_T_1
connect io.resp.bits.tag, req.bits.tag
node _T_26 = and(req.valid, req.bits.laddr.is_acc_addr)
node _T_27 = gt(req.bits.pixel_repeats, UInt<1>(0h0))
node _T_28 = and(_T_26, _T_27)
node _T_29 = eq(_T_28, UInt<1>(0h0))
node _T_30 = asUInt(reset)
node _T_31 = eq(_T_30, UInt<1>(0h0))
when _T_31 :
node _T_32 = eq(_T_29, UInt<1>(0h0))
when _T_32 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at PixelRepeater.scala:58 assert(!(req.valid && is_acc_addr && req.bits.pixel_repeats > 0.U))\n") : printf
assert(clock, _T_29, UInt<1>(0h1), "") : assert
node _sp_addr_T = bits(req.bits.laddr.data, 13, 0)
node _sp_addr_T_1 = lt(_sp_addr_T, UInt<14>(0h2000))
node _sp_addr_underflow_T = add(UInt<1>(0h0), req.bits.pixel_repeats)
node sp_addr_underflow = lt(req.bits.laddr.data, _sp_addr_underflow_T)
wire sp_addr_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
connect sp_addr_result, req.bits.laddr
node _sp_addr_result_data_T = sub(req.bits.laddr.data, req.bits.pixel_repeats)
node _sp_addr_result_data_T_1 = tail(_sp_addr_result_data_T, 1)
node _sp_addr_result_data_T_2 = mux(sp_addr_underflow, UInt<1>(0h0), _sp_addr_result_data_T_1)
connect sp_addr_result.data, _sp_addr_result_data_T_2
node _sp_addr_underflow_T_1 = add(UInt<14>(0h2000), req.bits.pixel_repeats)
node sp_addr_underflow_1 = lt(req.bits.laddr.data, _sp_addr_underflow_T_1)
wire sp_addr_result_1 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
connect sp_addr_result_1, req.bits.laddr
node _sp_addr_result_data_T_3 = sub(req.bits.laddr.data, req.bits.pixel_repeats)
node _sp_addr_result_data_T_4 = tail(_sp_addr_result_data_T_3, 1)
node _sp_addr_result_data_T_5 = mux(sp_addr_underflow_1, UInt<14>(0h2000), _sp_addr_result_data_T_4)
connect sp_addr_result_1.data, _sp_addr_result_data_T_5
node sp_addr = mux(_sp_addr_T_1, sp_addr_result, sp_addr_result_1)
node _underflow_T = eq(req.bits.laddr.is_acc_addr, UInt<1>(0h0))
node _underflow_T_1 = bits(req.bits.laddr.data, 13, 0)
node _underflow_T_2 = lt(_underflow_T_1, UInt<14>(0h2000))
node _underflow_underflow_T = add(UInt<1>(0h0), req.bits.pixel_repeats)
node underflow_underflow = lt(req.bits.laddr.data, _underflow_underflow_T)
wire underflow_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
connect underflow_result, req.bits.laddr
node _underflow_result_data_T = sub(req.bits.laddr.data, req.bits.pixel_repeats)
node _underflow_result_data_T_1 = tail(_underflow_result_data_T, 1)
node _underflow_result_data_T_2 = mux(underflow_underflow, UInt<1>(0h0), _underflow_result_data_T_1)
connect underflow_result.data, _underflow_result_data_T_2
node _underflow_underflow_T_1 = add(UInt<14>(0h2000), req.bits.pixel_repeats)
node underflow_underflow_1 = lt(req.bits.laddr.data, _underflow_underflow_T_1)
wire underflow_result_1 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}
connect underflow_result_1, req.bits.laddr
node _underflow_result_data_T_3 = sub(req.bits.laddr.data, req.bits.pixel_repeats)
node _underflow_result_data_T_4 = tail(_underflow_result_data_T_3, 1)
node _underflow_result_data_T_5 = mux(underflow_underflow_1, UInt<14>(0h2000), _underflow_result_data_T_4)
connect underflow_result_1.data, _underflow_result_data_T_5
node _underflow_T_3 = mux(_underflow_T_2, underflow_underflow, underflow_underflow_1)
node underflow = and(_underflow_T, _underflow_T_3)
node _io_resp_bits_laddr_T = mux(req.bits.laddr.is_acc_addr, req.bits.laddr, sp_addr)
connect io.resp.bits.laddr, _io_resp_bits_laddr_T
node _io_resp_valid_T = eq(underflow, UInt<1>(0h0))
node _io_resp_valid_T_1 = and(req.valid, _io_resp_valid_T)
connect io.resp.valid, _io_resp_valid_T_1
node _T_33 = and(io.resp.ready, io.resp.valid)
node _T_34 = or(_T_33, underflow)
when _T_34 :
node _req_bits_pixel_repeats_T = sub(req.bits.pixel_repeats, UInt<1>(0h1))
node _req_bits_pixel_repeats_T_1 = tail(_req_bits_pixel_repeats_T, 1)
connect req.bits.pixel_repeats, _req_bits_pixel_repeats_T_1
node _T_35 = eq(req.bits.pixel_repeats, UInt<1>(0h0))
when _T_35 :
connect req.valid, UInt<1>(0h0)
node _T_36 = and(io.req.ready, io.req.valid)
when _T_36 :
connect req.valid, UInt<1>(0h1)
connect req.bits, io.req.bits
node _req_bits_pixel_repeats_T_2 = sub(io.req.bits.pixel_repeats, UInt<1>(0h1))
node _req_bits_pixel_repeats_T_3 = tail(_req_bits_pixel_repeats_T_2, 1)
connect req.bits.pixel_repeats, _req_bits_pixel_repeats_T_3
node _T_37 = asUInt(reset)
when _T_37 :
connect req.valid, UInt<1>(0h0) | module PixelRepeater( // @[PixelRepeater.scala:28:7]
input clock, // @[PixelRepeater.scala:28:7]
input reset, // @[PixelRepeater.scala:28:7]
output io_req_ready, // @[PixelRepeater.scala:29:14]
input io_req_valid, // @[PixelRepeater.scala:29:14]
input io_req_bits_mask_0, // @[PixelRepeater.scala:29:14]
input io_req_bits_mask_1, // @[PixelRepeater.scala:29:14]
input io_req_bits_mask_2, // @[PixelRepeater.scala:29:14]
input io_req_bits_mask_3, // @[PixelRepeater.scala:29:14]
input io_req_bits_mask_4, // @[PixelRepeater.scala:29:14]
input io_req_bits_mask_5, // @[PixelRepeater.scala:29:14]
input io_req_bits_mask_6, // @[PixelRepeater.scala:29:14]
input io_req_bits_mask_7, // @[PixelRepeater.scala:29:14]
input io_req_bits_mask_8, // @[PixelRepeater.scala:29:14]
input io_req_bits_mask_9, // @[PixelRepeater.scala:29:14]
input io_req_bits_mask_10, // @[PixelRepeater.scala:29:14]
input io_req_bits_mask_11, // @[PixelRepeater.scala:29:14]
input io_req_bits_mask_12, // @[PixelRepeater.scala:29:14]
input io_req_bits_mask_13, // @[PixelRepeater.scala:29:14]
input io_req_bits_mask_14, // @[PixelRepeater.scala:29:14]
input io_req_bits_mask_15, // @[PixelRepeater.scala:29:14]
input io_req_bits_laddr_is_acc_addr, // @[PixelRepeater.scala:29:14]
input io_req_bits_laddr_accumulate, // @[PixelRepeater.scala:29:14]
input io_req_bits_laddr_read_full_acc_row, // @[PixelRepeater.scala:29:14]
input [2:0] io_req_bits_laddr_norm_cmd, // @[PixelRepeater.scala:29:14]
input [10:0] io_req_bits_laddr_garbage, // @[PixelRepeater.scala:29:14]
input io_req_bits_laddr_garbage_bit, // @[PixelRepeater.scala:29:14]
input [13:0] io_req_bits_laddr_data, // @[PixelRepeater.scala:29:14]
input [2:0] io_req_bits_len, // @[PixelRepeater.scala:29:14]
input [7:0] io_req_bits_pixel_repeats, // @[PixelRepeater.scala:29:14]
input io_req_bits_last, // @[PixelRepeater.scala:29:14]
input [39:0] io_req_bits_tag_vaddr, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_laddr_is_acc_addr, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_laddr_accumulate, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_laddr_read_full_acc_row, // @[PixelRepeater.scala:29:14]
input [2:0] io_req_bits_tag_laddr_norm_cmd, // @[PixelRepeater.scala:29:14]
input [10:0] io_req_bits_tag_laddr_garbage, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_laddr_garbage_bit, // @[PixelRepeater.scala:29:14]
input [13:0] io_req_bits_tag_laddr_data, // @[PixelRepeater.scala:29:14]
input [15:0] io_req_bits_tag_cols, // @[PixelRepeater.scala:29:14]
input [15:0] io_req_bits_tag_repeats, // @[PixelRepeater.scala:29:14]
input [31:0] io_req_bits_tag_scale, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_has_acc_bitwidth, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_all_zeros, // @[PixelRepeater.scala:29:14]
input [15:0] io_req_bits_tag_block_stride, // @[PixelRepeater.scala:29:14]
input [7:0] io_req_bits_tag_pixel_repeats, // @[PixelRepeater.scala:29:14]
input [7:0] io_req_bits_tag_cmd_id, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_debug, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_cease, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_wfi, // @[PixelRepeater.scala:29:14]
input [31:0] io_req_bits_tag_status_isa, // @[PixelRepeater.scala:29:14]
input [1:0] io_req_bits_tag_status_dprv, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_dv, // @[PixelRepeater.scala:29:14]
input [1:0] io_req_bits_tag_status_prv, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_v, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_sd, // @[PixelRepeater.scala:29:14]
input [22:0] io_req_bits_tag_status_zero2, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_mpv, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_gva, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_mbe, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_sbe, // @[PixelRepeater.scala:29:14]
input [1:0] io_req_bits_tag_status_sxl, // @[PixelRepeater.scala:29:14]
input [1:0] io_req_bits_tag_status_uxl, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_sd_rv32, // @[PixelRepeater.scala:29:14]
input [7:0] io_req_bits_tag_status_zero1, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_tsr, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_tw, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_tvm, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_mxr, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_sum, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_mprv, // @[PixelRepeater.scala:29:14]
input [1:0] io_req_bits_tag_status_xs, // @[PixelRepeater.scala:29:14]
input [1:0] io_req_bits_tag_status_fs, // @[PixelRepeater.scala:29:14]
input [1:0] io_req_bits_tag_status_mpp, // @[PixelRepeater.scala:29:14]
input [1:0] io_req_bits_tag_status_vs, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_spp, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_mpie, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_ube, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_spie, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_upie, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_mie, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_hie, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_sie, // @[PixelRepeater.scala:29:14]
input io_req_bits_tag_status_uie, // @[PixelRepeater.scala:29:14]
input io_resp_ready, // @[PixelRepeater.scala:29:14]
output io_resp_valid, // @[PixelRepeater.scala:29:14]
output io_resp_bits_mask_0, // @[PixelRepeater.scala:29:14]
output io_resp_bits_mask_1, // @[PixelRepeater.scala:29:14]
output io_resp_bits_mask_2, // @[PixelRepeater.scala:29:14]
output io_resp_bits_mask_3, // @[PixelRepeater.scala:29:14]
output io_resp_bits_mask_4, // @[PixelRepeater.scala:29:14]
output io_resp_bits_mask_5, // @[PixelRepeater.scala:29:14]
output io_resp_bits_mask_6, // @[PixelRepeater.scala:29:14]
output io_resp_bits_mask_7, // @[PixelRepeater.scala:29:14]
output io_resp_bits_mask_8, // @[PixelRepeater.scala:29:14]
output io_resp_bits_mask_9, // @[PixelRepeater.scala:29:14]
output io_resp_bits_mask_10, // @[PixelRepeater.scala:29:14]
output io_resp_bits_mask_11, // @[PixelRepeater.scala:29:14]
output io_resp_bits_mask_12, // @[PixelRepeater.scala:29:14]
output io_resp_bits_mask_13, // @[PixelRepeater.scala:29:14]
output io_resp_bits_mask_14, // @[PixelRepeater.scala:29:14]
output io_resp_bits_mask_15, // @[PixelRepeater.scala:29:14]
output io_resp_bits_laddr_is_acc_addr, // @[PixelRepeater.scala:29:14]
output io_resp_bits_laddr_accumulate, // @[PixelRepeater.scala:29:14]
output [13:0] io_resp_bits_laddr_data, // @[PixelRepeater.scala:29:14]
output io_resp_bits_last, // @[PixelRepeater.scala:29:14]
output [15:0] io_resp_bits_tag_cols, // @[PixelRepeater.scala:29:14]
output [7:0] io_resp_bits_tag_cmd_id // @[PixelRepeater.scala:29:14]
);
wire io_req_valid_0 = io_req_valid; // @[PixelRepeater.scala:28:7]
wire io_req_bits_mask_0_0 = io_req_bits_mask_0; // @[PixelRepeater.scala:28:7]
wire io_req_bits_mask_1_0 = io_req_bits_mask_1; // @[PixelRepeater.scala:28:7]
wire io_req_bits_mask_2_0 = io_req_bits_mask_2; // @[PixelRepeater.scala:28:7]
wire io_req_bits_mask_3_0 = io_req_bits_mask_3; // @[PixelRepeater.scala:28:7]
wire io_req_bits_mask_4_0 = io_req_bits_mask_4; // @[PixelRepeater.scala:28:7]
wire io_req_bits_mask_5_0 = io_req_bits_mask_5; // @[PixelRepeater.scala:28:7]
wire io_req_bits_mask_6_0 = io_req_bits_mask_6; // @[PixelRepeater.scala:28:7]
wire io_req_bits_mask_7_0 = io_req_bits_mask_7; // @[PixelRepeater.scala:28:7]
wire io_req_bits_mask_8_0 = io_req_bits_mask_8; // @[PixelRepeater.scala:28:7]
wire io_req_bits_mask_9_0 = io_req_bits_mask_9; // @[PixelRepeater.scala:28:7]
wire io_req_bits_mask_10_0 = io_req_bits_mask_10; // @[PixelRepeater.scala:28:7]
wire io_req_bits_mask_11_0 = io_req_bits_mask_11; // @[PixelRepeater.scala:28:7]
wire io_req_bits_mask_12_0 = io_req_bits_mask_12; // @[PixelRepeater.scala:28:7]
wire io_req_bits_mask_13_0 = io_req_bits_mask_13; // @[PixelRepeater.scala:28:7]
wire io_req_bits_mask_14_0 = io_req_bits_mask_14; // @[PixelRepeater.scala:28:7]
wire io_req_bits_mask_15_0 = io_req_bits_mask_15; // @[PixelRepeater.scala:28:7]
wire io_req_bits_laddr_is_acc_addr_0 = io_req_bits_laddr_is_acc_addr; // @[PixelRepeater.scala:28:7]
wire io_req_bits_laddr_accumulate_0 = io_req_bits_laddr_accumulate; // @[PixelRepeater.scala:28:7]
wire io_req_bits_laddr_read_full_acc_row_0 = io_req_bits_laddr_read_full_acc_row; // @[PixelRepeater.scala:28:7]
wire [2:0] io_req_bits_laddr_norm_cmd_0 = io_req_bits_laddr_norm_cmd; // @[PixelRepeater.scala:28:7]
wire [10:0] io_req_bits_laddr_garbage_0 = io_req_bits_laddr_garbage; // @[PixelRepeater.scala:28:7]
wire io_req_bits_laddr_garbage_bit_0 = io_req_bits_laddr_garbage_bit; // @[PixelRepeater.scala:28:7]
wire [13:0] io_req_bits_laddr_data_0 = io_req_bits_laddr_data; // @[PixelRepeater.scala:28:7]
wire [2:0] io_req_bits_len_0 = io_req_bits_len; // @[PixelRepeater.scala:28:7]
wire [7:0] io_req_bits_pixel_repeats_0 = io_req_bits_pixel_repeats; // @[PixelRepeater.scala:28:7]
wire io_req_bits_last_0 = io_req_bits_last; // @[PixelRepeater.scala:28:7]
wire [39:0] io_req_bits_tag_vaddr_0 = io_req_bits_tag_vaddr; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_laddr_is_acc_addr_0 = io_req_bits_tag_laddr_is_acc_addr; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_laddr_accumulate_0 = io_req_bits_tag_laddr_accumulate; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_laddr_read_full_acc_row_0 = io_req_bits_tag_laddr_read_full_acc_row; // @[PixelRepeater.scala:28:7]
wire [2:0] io_req_bits_tag_laddr_norm_cmd_0 = io_req_bits_tag_laddr_norm_cmd; // @[PixelRepeater.scala:28:7]
wire [10:0] io_req_bits_tag_laddr_garbage_0 = io_req_bits_tag_laddr_garbage; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_laddr_garbage_bit_0 = io_req_bits_tag_laddr_garbage_bit; // @[PixelRepeater.scala:28:7]
wire [13:0] io_req_bits_tag_laddr_data_0 = io_req_bits_tag_laddr_data; // @[PixelRepeater.scala:28:7]
wire [15:0] io_req_bits_tag_cols_0 = io_req_bits_tag_cols; // @[PixelRepeater.scala:28:7]
wire [15:0] io_req_bits_tag_repeats_0 = io_req_bits_tag_repeats; // @[PixelRepeater.scala:28:7]
wire [31:0] io_req_bits_tag_scale_0 = io_req_bits_tag_scale; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_has_acc_bitwidth_0 = io_req_bits_tag_has_acc_bitwidth; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_all_zeros_0 = io_req_bits_tag_all_zeros; // @[PixelRepeater.scala:28:7]
wire [15:0] io_req_bits_tag_block_stride_0 = io_req_bits_tag_block_stride; // @[PixelRepeater.scala:28:7]
wire [7:0] io_req_bits_tag_pixel_repeats_0 = io_req_bits_tag_pixel_repeats; // @[PixelRepeater.scala:28:7]
wire [7:0] io_req_bits_tag_cmd_id_0 = io_req_bits_tag_cmd_id; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_debug_0 = io_req_bits_tag_status_debug; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_cease_0 = io_req_bits_tag_status_cease; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_wfi_0 = io_req_bits_tag_status_wfi; // @[PixelRepeater.scala:28:7]
wire [31:0] io_req_bits_tag_status_isa_0 = io_req_bits_tag_status_isa; // @[PixelRepeater.scala:28:7]
wire [1:0] io_req_bits_tag_status_dprv_0 = io_req_bits_tag_status_dprv; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_dv_0 = io_req_bits_tag_status_dv; // @[PixelRepeater.scala:28:7]
wire [1:0] io_req_bits_tag_status_prv_0 = io_req_bits_tag_status_prv; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_v_0 = io_req_bits_tag_status_v; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_sd_0 = io_req_bits_tag_status_sd; // @[PixelRepeater.scala:28:7]
wire [22:0] io_req_bits_tag_status_zero2_0 = io_req_bits_tag_status_zero2; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_mpv_0 = io_req_bits_tag_status_mpv; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_gva_0 = io_req_bits_tag_status_gva; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_mbe_0 = io_req_bits_tag_status_mbe; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_sbe_0 = io_req_bits_tag_status_sbe; // @[PixelRepeater.scala:28:7]
wire [1:0] io_req_bits_tag_status_sxl_0 = io_req_bits_tag_status_sxl; // @[PixelRepeater.scala:28:7]
wire [1:0] io_req_bits_tag_status_uxl_0 = io_req_bits_tag_status_uxl; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_sd_rv32_0 = io_req_bits_tag_status_sd_rv32; // @[PixelRepeater.scala:28:7]
wire [7:0] io_req_bits_tag_status_zero1_0 = io_req_bits_tag_status_zero1; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_tsr_0 = io_req_bits_tag_status_tsr; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_tw_0 = io_req_bits_tag_status_tw; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_tvm_0 = io_req_bits_tag_status_tvm; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_mxr_0 = io_req_bits_tag_status_mxr; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_sum_0 = io_req_bits_tag_status_sum; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_mprv_0 = io_req_bits_tag_status_mprv; // @[PixelRepeater.scala:28:7]
wire [1:0] io_req_bits_tag_status_xs_0 = io_req_bits_tag_status_xs; // @[PixelRepeater.scala:28:7]
wire [1:0] io_req_bits_tag_status_fs_0 = io_req_bits_tag_status_fs; // @[PixelRepeater.scala:28:7]
wire [1:0] io_req_bits_tag_status_mpp_0 = io_req_bits_tag_status_mpp; // @[PixelRepeater.scala:28:7]
wire [1:0] io_req_bits_tag_status_vs_0 = io_req_bits_tag_status_vs; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_spp_0 = io_req_bits_tag_status_spp; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_mpie_0 = io_req_bits_tag_status_mpie; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_ube_0 = io_req_bits_tag_status_ube; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_spie_0 = io_req_bits_tag_status_spie; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_upie_0 = io_req_bits_tag_status_upie; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_mie_0 = io_req_bits_tag_status_mie; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_hie_0 = io_req_bits_tag_status_hie; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_sie_0 = io_req_bits_tag_status_sie; // @[PixelRepeater.scala:28:7]
wire io_req_bits_tag_status_uie_0 = io_req_bits_tag_status_uie; // @[PixelRepeater.scala:28:7]
wire io_resp_ready_0 = io_resp_ready; // @[PixelRepeater.scala:28:7]
wire [63:0] lo = 64'h0; // @[PixelRepeater.scala:51:38]
wire [63:0] hi = 64'h0; // @[PixelRepeater.scala:51:38]
wire [31:0] io_req_bits_in_0_bits = 32'h0; // @[PixelRepeater.scala:28:7]
wire [31:0] io_req_bits_in_1_bits = 32'h0; // @[PixelRepeater.scala:28:7]
wire [31:0] io_req_bits_in_2_bits = 32'h0; // @[PixelRepeater.scala:28:7]
wire [31:0] io_req_bits_in_3_bits = 32'h0; // @[PixelRepeater.scala:28:7]
wire _io_req_ready_T_3; // @[PixelRepeater.scala:46:32]
wire _io_resp_valid_T_1; // @[PixelRepeater.scala:72:32]
wire _io_resp_bits_laddr_T_is_acc_addr; // @[PixelRepeater.scala:70:30]
wire _io_resp_bits_laddr_T_accumulate; // @[PixelRepeater.scala:70:30]
wire _io_resp_bits_laddr_T_read_full_acc_row; // @[PixelRepeater.scala:70:30]
wire [2:0] _io_resp_bits_laddr_T_norm_cmd; // @[PixelRepeater.scala:70:30]
wire [10:0] _io_resp_bits_laddr_T_garbage; // @[PixelRepeater.scala:70:30]
wire _io_resp_bits_laddr_T_garbage_bit; // @[PixelRepeater.scala:70:30]
wire [13:0] _io_resp_bits_laddr_T_data; // @[PixelRepeater.scala:70:30]
wire _io_resp_bits_last_T_1; // @[PixelRepeater.scala:54:40]
wire io_req_ready_0; // @[PixelRepeater.scala:28:7]
wire [31:0] io_resp_bits_out_0_bits; // @[PixelRepeater.scala:28:7]
wire [31:0] io_resp_bits_out_1_bits; // @[PixelRepeater.scala:28:7]
wire [31:0] io_resp_bits_out_2_bits; // @[PixelRepeater.scala:28:7]
wire [31:0] io_resp_bits_out_3_bits; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_mask_0_0; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_mask_1_0; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_mask_2_0; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_mask_3_0; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_mask_4_0; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_mask_5_0; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_mask_6_0; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_mask_7_0; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_mask_8_0; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_mask_9_0; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_mask_10_0; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_mask_11_0; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_mask_12_0; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_mask_13_0; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_mask_14_0; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_mask_15_0; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_laddr_is_acc_addr_0; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_laddr_accumulate_0; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_laddr_read_full_acc_row; // @[PixelRepeater.scala:28:7]
wire [2:0] io_resp_bits_laddr_norm_cmd; // @[PixelRepeater.scala:28:7]
wire [10:0] io_resp_bits_laddr_garbage; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_laddr_garbage_bit; // @[PixelRepeater.scala:28:7]
wire [13:0] io_resp_bits_laddr_data_0; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_laddr_is_acc_addr; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_laddr_accumulate; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_laddr_read_full_acc_row; // @[PixelRepeater.scala:28:7]
wire [2:0] io_resp_bits_tag_laddr_norm_cmd; // @[PixelRepeater.scala:28:7]
wire [10:0] io_resp_bits_tag_laddr_garbage; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_laddr_garbage_bit; // @[PixelRepeater.scala:28:7]
wire [13:0] io_resp_bits_tag_laddr_data; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_debug; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_cease; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_wfi; // @[PixelRepeater.scala:28:7]
wire [31:0] io_resp_bits_tag_status_isa; // @[PixelRepeater.scala:28:7]
wire [1:0] io_resp_bits_tag_status_dprv; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_dv; // @[PixelRepeater.scala:28:7]
wire [1:0] io_resp_bits_tag_status_prv; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_v; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_sd; // @[PixelRepeater.scala:28:7]
wire [22:0] io_resp_bits_tag_status_zero2; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_mpv; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_gva; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_mbe; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_sbe; // @[PixelRepeater.scala:28:7]
wire [1:0] io_resp_bits_tag_status_sxl; // @[PixelRepeater.scala:28:7]
wire [1:0] io_resp_bits_tag_status_uxl; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_sd_rv32; // @[PixelRepeater.scala:28:7]
wire [7:0] io_resp_bits_tag_status_zero1; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_tsr; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_tw; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_tvm; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_mxr; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_sum; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_mprv; // @[PixelRepeater.scala:28:7]
wire [1:0] io_resp_bits_tag_status_xs; // @[PixelRepeater.scala:28:7]
wire [1:0] io_resp_bits_tag_status_fs; // @[PixelRepeater.scala:28:7]
wire [1:0] io_resp_bits_tag_status_mpp; // @[PixelRepeater.scala:28:7]
wire [1:0] io_resp_bits_tag_status_vs; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_spp; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_mpie; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_ube; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_spie; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_upie; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_mie; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_hie; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_sie; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_status_uie; // @[PixelRepeater.scala:28:7]
wire [39:0] io_resp_bits_tag_vaddr; // @[PixelRepeater.scala:28:7]
wire [15:0] io_resp_bits_tag_cols_0; // @[PixelRepeater.scala:28:7]
wire [15:0] io_resp_bits_tag_repeats; // @[PixelRepeater.scala:28:7]
wire [31:0] io_resp_bits_tag_scale; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_has_acc_bitwidth; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_tag_all_zeros; // @[PixelRepeater.scala:28:7]
wire [15:0] io_resp_bits_tag_block_stride; // @[PixelRepeater.scala:28:7]
wire [7:0] io_resp_bits_tag_pixel_repeats; // @[PixelRepeater.scala:28:7]
wire [7:0] io_resp_bits_tag_cmd_id_0; // @[PixelRepeater.scala:28:7]
wire io_resp_bits_last_0; // @[PixelRepeater.scala:28:7]
wire io_resp_valid_0; // @[PixelRepeater.scala:28:7]
reg req_valid; // @[PixelRepeater.scala:44:18]
reg req_bits_mask_0; // @[PixelRepeater.scala:44:18]
reg req_bits_mask_1; // @[PixelRepeater.scala:44:18]
reg req_bits_mask_2; // @[PixelRepeater.scala:44:18]
reg req_bits_mask_3; // @[PixelRepeater.scala:44:18]
reg req_bits_mask_4; // @[PixelRepeater.scala:44:18]
reg req_bits_mask_5; // @[PixelRepeater.scala:44:18]
reg req_bits_mask_6; // @[PixelRepeater.scala:44:18]
reg req_bits_mask_7; // @[PixelRepeater.scala:44:18]
reg req_bits_mask_8; // @[PixelRepeater.scala:44:18]
reg req_bits_mask_9; // @[PixelRepeater.scala:44:18]
reg req_bits_mask_10; // @[PixelRepeater.scala:44:18]
reg req_bits_mask_11; // @[PixelRepeater.scala:44:18]
reg req_bits_mask_12; // @[PixelRepeater.scala:44:18]
reg req_bits_mask_13; // @[PixelRepeater.scala:44:18]
reg req_bits_mask_14; // @[PixelRepeater.scala:44:18]
reg req_bits_mask_15; // @[PixelRepeater.scala:44:18]
reg req_bits_laddr_is_acc_addr; // @[PixelRepeater.scala:44:18]
wire sp_addr_result_is_acc_addr = req_bits_laddr_is_acc_addr; // @[PixelRepeater.scala:44:18]
wire sp_addr_result_1_is_acc_addr = req_bits_laddr_is_acc_addr; // @[PixelRepeater.scala:44:18]
wire underflow_result_is_acc_addr = req_bits_laddr_is_acc_addr; // @[PixelRepeater.scala:44:18]
wire underflow_result_1_is_acc_addr = req_bits_laddr_is_acc_addr; // @[PixelRepeater.scala:44:18]
reg req_bits_laddr_accumulate; // @[PixelRepeater.scala:44:18]
wire sp_addr_result_accumulate = req_bits_laddr_accumulate; // @[PixelRepeater.scala:44:18]
wire sp_addr_result_1_accumulate = req_bits_laddr_accumulate; // @[PixelRepeater.scala:44:18]
wire underflow_result_accumulate = req_bits_laddr_accumulate; // @[PixelRepeater.scala:44:18]
wire underflow_result_1_accumulate = req_bits_laddr_accumulate; // @[PixelRepeater.scala:44:18]
reg req_bits_laddr_read_full_acc_row; // @[PixelRepeater.scala:44:18]
wire sp_addr_result_read_full_acc_row = req_bits_laddr_read_full_acc_row; // @[PixelRepeater.scala:44:18]
wire sp_addr_result_1_read_full_acc_row = req_bits_laddr_read_full_acc_row; // @[PixelRepeater.scala:44:18]
wire underflow_result_read_full_acc_row = req_bits_laddr_read_full_acc_row; // @[PixelRepeater.scala:44:18]
wire underflow_result_1_read_full_acc_row = req_bits_laddr_read_full_acc_row; // @[PixelRepeater.scala:44:18]
reg [2:0] req_bits_laddr_norm_cmd; // @[PixelRepeater.scala:44:18]
wire [2:0] sp_addr_result_norm_cmd = req_bits_laddr_norm_cmd; // @[PixelRepeater.scala:44:18]
wire [2:0] sp_addr_result_1_norm_cmd = req_bits_laddr_norm_cmd; // @[PixelRepeater.scala:44:18]
wire [2:0] underflow_result_norm_cmd = req_bits_laddr_norm_cmd; // @[PixelRepeater.scala:44:18]
wire [2:0] underflow_result_1_norm_cmd = req_bits_laddr_norm_cmd; // @[PixelRepeater.scala:44:18]
reg [10:0] req_bits_laddr_garbage; // @[PixelRepeater.scala:44:18]
wire [10:0] sp_addr_result_garbage = req_bits_laddr_garbage; // @[PixelRepeater.scala:44:18]
wire [10:0] sp_addr_result_1_garbage = req_bits_laddr_garbage; // @[PixelRepeater.scala:44:18]
wire [10:0] underflow_result_garbage = req_bits_laddr_garbage; // @[PixelRepeater.scala:44:18]
wire [10:0] underflow_result_1_garbage = req_bits_laddr_garbage; // @[PixelRepeater.scala:44:18]
reg req_bits_laddr_garbage_bit; // @[PixelRepeater.scala:44:18]
wire sp_addr_result_garbage_bit = req_bits_laddr_garbage_bit; // @[PixelRepeater.scala:44:18]
wire sp_addr_result_1_garbage_bit = req_bits_laddr_garbage_bit; // @[PixelRepeater.scala:44:18]
wire underflow_result_garbage_bit = req_bits_laddr_garbage_bit; // @[PixelRepeater.scala:44:18]
wire underflow_result_1_garbage_bit = req_bits_laddr_garbage_bit; // @[PixelRepeater.scala:44:18]
reg [13:0] req_bits_laddr_data; // @[PixelRepeater.scala:44:18]
wire [13:0] _sp_addr_T = req_bits_laddr_data; // @[PixelRepeater.scala:44:18]
wire [13:0] _underflow_T_1 = req_bits_laddr_data; // @[PixelRepeater.scala:44:18]
reg [2:0] req_bits_len; // @[PixelRepeater.scala:44:18]
reg [7:0] req_bits_pixel_repeats; // @[PixelRepeater.scala:44:18]
reg req_bits_last; // @[PixelRepeater.scala:44:18]
reg [39:0] req_bits_tag_vaddr; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_vaddr = req_bits_tag_vaddr; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_laddr_is_acc_addr; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_laddr_is_acc_addr = req_bits_tag_laddr_is_acc_addr; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_laddr_accumulate; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_laddr_accumulate = req_bits_tag_laddr_accumulate; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_laddr_read_full_acc_row; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_laddr_read_full_acc_row = req_bits_tag_laddr_read_full_acc_row; // @[PixelRepeater.scala:28:7, :44:18]
reg [2:0] req_bits_tag_laddr_norm_cmd; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_laddr_norm_cmd = req_bits_tag_laddr_norm_cmd; // @[PixelRepeater.scala:28:7, :44:18]
reg [10:0] req_bits_tag_laddr_garbage; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_laddr_garbage = req_bits_tag_laddr_garbage; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_laddr_garbage_bit; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_laddr_garbage_bit = req_bits_tag_laddr_garbage_bit; // @[PixelRepeater.scala:28:7, :44:18]
reg [13:0] req_bits_tag_laddr_data; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_laddr_data = req_bits_tag_laddr_data; // @[PixelRepeater.scala:28:7, :44:18]
reg [15:0] req_bits_tag_cols; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_cols_0 = req_bits_tag_cols; // @[PixelRepeater.scala:28:7, :44:18]
reg [15:0] req_bits_tag_repeats; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_repeats = req_bits_tag_repeats; // @[PixelRepeater.scala:28:7, :44:18]
reg [31:0] req_bits_tag_scale; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_scale = req_bits_tag_scale; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_has_acc_bitwidth; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_has_acc_bitwidth = req_bits_tag_has_acc_bitwidth; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_all_zeros; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_all_zeros = req_bits_tag_all_zeros; // @[PixelRepeater.scala:28:7, :44:18]
reg [15:0] req_bits_tag_block_stride; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_block_stride = req_bits_tag_block_stride; // @[PixelRepeater.scala:28:7, :44:18]
reg [7:0] req_bits_tag_pixel_repeats; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_pixel_repeats = req_bits_tag_pixel_repeats; // @[PixelRepeater.scala:28:7, :44:18]
reg [7:0] req_bits_tag_cmd_id; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_cmd_id_0 = req_bits_tag_cmd_id; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_debug; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_debug = req_bits_tag_status_debug; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_cease; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_cease = req_bits_tag_status_cease; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_wfi; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_wfi = req_bits_tag_status_wfi; // @[PixelRepeater.scala:28:7, :44:18]
reg [31:0] req_bits_tag_status_isa; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_isa = req_bits_tag_status_isa; // @[PixelRepeater.scala:28:7, :44:18]
reg [1:0] req_bits_tag_status_dprv; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_dprv = req_bits_tag_status_dprv; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_dv; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_dv = req_bits_tag_status_dv; // @[PixelRepeater.scala:28:7, :44:18]
reg [1:0] req_bits_tag_status_prv; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_prv = req_bits_tag_status_prv; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_v; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_v = req_bits_tag_status_v; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_sd; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_sd = req_bits_tag_status_sd; // @[PixelRepeater.scala:28:7, :44:18]
reg [22:0] req_bits_tag_status_zero2; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_zero2 = req_bits_tag_status_zero2; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_mpv; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_mpv = req_bits_tag_status_mpv; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_gva; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_gva = req_bits_tag_status_gva; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_mbe; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_mbe = req_bits_tag_status_mbe; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_sbe; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_sbe = req_bits_tag_status_sbe; // @[PixelRepeater.scala:28:7, :44:18]
reg [1:0] req_bits_tag_status_sxl; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_sxl = req_bits_tag_status_sxl; // @[PixelRepeater.scala:28:7, :44:18]
reg [1:0] req_bits_tag_status_uxl; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_uxl = req_bits_tag_status_uxl; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_sd_rv32; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_sd_rv32 = req_bits_tag_status_sd_rv32; // @[PixelRepeater.scala:28:7, :44:18]
reg [7:0] req_bits_tag_status_zero1; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_zero1 = req_bits_tag_status_zero1; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_tsr; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_tsr = req_bits_tag_status_tsr; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_tw; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_tw = req_bits_tag_status_tw; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_tvm; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_tvm = req_bits_tag_status_tvm; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_mxr; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_mxr = req_bits_tag_status_mxr; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_sum; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_sum = req_bits_tag_status_sum; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_mprv; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_mprv = req_bits_tag_status_mprv; // @[PixelRepeater.scala:28:7, :44:18]
reg [1:0] req_bits_tag_status_xs; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_xs = req_bits_tag_status_xs; // @[PixelRepeater.scala:28:7, :44:18]
reg [1:0] req_bits_tag_status_fs; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_fs = req_bits_tag_status_fs; // @[PixelRepeater.scala:28:7, :44:18]
reg [1:0] req_bits_tag_status_mpp; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_mpp = req_bits_tag_status_mpp; // @[PixelRepeater.scala:28:7, :44:18]
reg [1:0] req_bits_tag_status_vs; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_vs = req_bits_tag_status_vs; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_spp; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_spp = req_bits_tag_status_spp; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_mpie; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_mpie = req_bits_tag_status_mpie; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_ube; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_ube = req_bits_tag_status_ube; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_spie; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_spie = req_bits_tag_status_spie; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_upie; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_upie = req_bits_tag_status_upie; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_mie; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_mie = req_bits_tag_status_mie; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_hie; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_hie = req_bits_tag_status_hie; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_sie; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_sie = req_bits_tag_status_sie; // @[PixelRepeater.scala:28:7, :44:18]
reg req_bits_tag_status_uie; // @[PixelRepeater.scala:44:18]
assign io_resp_bits_tag_status_uie = req_bits_tag_status_uie; // @[PixelRepeater.scala:28:7, :44:18]
wire _io_req_ready_T = ~req_valid; // @[PixelRepeater.scala:44:18, :46:21]
wire _T_35 = req_bits_pixel_repeats == 8'h0; // @[PixelRepeater.scala:44:18, :46:76]
wire _io_req_ready_T_1; // @[PixelRepeater.scala:46:76]
assign _io_req_ready_T_1 = _T_35; // @[PixelRepeater.scala:46:76]
wire _io_resp_bits_last_T; // @[PixelRepeater.scala:54:67]
assign _io_resp_bits_last_T = _T_35; // @[PixelRepeater.scala:46:76, :54:67]
wire _io_req_ready_T_2 = io_resp_ready_0 & _io_req_ready_T_1; // @[PixelRepeater.scala:28:7, :46:{50,76}]
assign _io_req_ready_T_3 = _io_req_ready_T | _io_req_ready_T_2; // @[PixelRepeater.scala:46:{21,32,50}]
assign io_req_ready_0 = _io_req_ready_T_3; // @[PixelRepeater.scala:28:7, :46:32]
wire [1:0] out_shift; // @[PixelRepeater.scala:48:25]
wire [10:0] _out_shift_T = {3'h0, req_bits_pixel_repeats} * {8'h0, req_bits_len}; // @[PixelRepeater.scala:44:18, :49:41]
assign out_shift = _out_shift_T[1:0]; // @[PixelRepeater.scala:48:25, :49:{15,41}]
wire [382:0] _T_2 = 383'h0 << {376'h0, out_shift, 5'h0}; // @[PixelRepeater.scala:48:25, :51:45]
assign io_resp_bits_out_0_bits = _T_2[31:0]; // @[PixelRepeater.scala:28:7, :51:{45,84}]
assign io_resp_bits_out_1_bits = _T_2[63:32]; // @[PixelRepeater.scala:28:7, :51:{45,84}]
assign io_resp_bits_out_2_bits = _T_2[95:64]; // @[PixelRepeater.scala:28:7, :51:{45,84}]
assign io_resp_bits_out_3_bits = _T_2[127:96]; // @[PixelRepeater.scala:28:7, :51:{45,84}]
wire [1:0] lo_lo_lo = {req_bits_mask_1, req_bits_mask_0}; // @[PixelRepeater.scala:44:18, :52:41]
wire [1:0] lo_lo_hi = {req_bits_mask_3, req_bits_mask_2}; // @[PixelRepeater.scala:44:18, :52:41]
wire [3:0] lo_lo = {lo_lo_hi, lo_lo_lo}; // @[PixelRepeater.scala:52:41]
wire [1:0] lo_hi_lo = {req_bits_mask_5, req_bits_mask_4}; // @[PixelRepeater.scala:44:18, :52:41]
wire [1:0] lo_hi_hi = {req_bits_mask_7, req_bits_mask_6}; // @[PixelRepeater.scala:44:18, :52:41]
wire [3:0] lo_hi = {lo_hi_hi, lo_hi_lo}; // @[PixelRepeater.scala:52:41]
wire [7:0] lo_1 = {lo_hi, lo_lo}; // @[PixelRepeater.scala:52:41]
wire [1:0] hi_lo_lo = {req_bits_mask_9, req_bits_mask_8}; // @[PixelRepeater.scala:44:18, :52:41]
wire [1:0] hi_lo_hi = {req_bits_mask_11, req_bits_mask_10}; // @[PixelRepeater.scala:44:18, :52:41]
wire [3:0] hi_lo = {hi_lo_hi, hi_lo_lo}; // @[PixelRepeater.scala:52:41]
wire [1:0] hi_hi_lo = {req_bits_mask_13, req_bits_mask_12}; // @[PixelRepeater.scala:44:18, :52:41]
wire [1:0] hi_hi_hi = {req_bits_mask_15, req_bits_mask_14}; // @[PixelRepeater.scala:44:18, :52:41]
wire [3:0] hi_hi = {hi_hi_hi, hi_hi_lo}; // @[PixelRepeater.scala:52:41]
wire [7:0] hi_1 = {hi_hi, hi_lo}; // @[PixelRepeater.scala:52:41]
wire [46:0] _T_9 = {31'h0, hi_1, lo_1} << {43'h0, out_shift, 2'h0}; // @[PixelRepeater.scala:48:25, :52:{41,48}]
assign io_resp_bits_mask_0_0 = _T_9[0]; // @[PixelRepeater.scala:28:7, :52:{48,108}]
assign io_resp_bits_mask_1_0 = _T_9[1]; // @[PixelRepeater.scala:28:7, :52:{48,108}]
assign io_resp_bits_mask_2_0 = _T_9[2]; // @[PixelRepeater.scala:28:7, :52:{48,108}]
assign io_resp_bits_mask_3_0 = _T_9[3]; // @[PixelRepeater.scala:28:7, :52:{48,108}]
assign io_resp_bits_mask_4_0 = _T_9[4]; // @[PixelRepeater.scala:28:7, :52:{48,108}]
assign io_resp_bits_mask_5_0 = _T_9[5]; // @[PixelRepeater.scala:28:7, :52:{48,108}]
assign io_resp_bits_mask_6_0 = _T_9[6]; // @[PixelRepeater.scala:28:7, :52:{48,108}]
assign io_resp_bits_mask_7_0 = _T_9[7]; // @[PixelRepeater.scala:28:7, :52:{48,108}]
assign io_resp_bits_mask_8_0 = _T_9[8]; // @[PixelRepeater.scala:28:7, :52:{48,108}]
assign io_resp_bits_mask_9_0 = _T_9[9]; // @[PixelRepeater.scala:28:7, :52:{48,108}]
assign io_resp_bits_mask_10_0 = _T_9[10]; // @[PixelRepeater.scala:28:7, :52:{48,108}]
assign io_resp_bits_mask_11_0 = _T_9[11]; // @[PixelRepeater.scala:28:7, :52:{48,108}]
assign io_resp_bits_mask_12_0 = _T_9[12]; // @[PixelRepeater.scala:28:7, :52:{48,108}]
assign io_resp_bits_mask_13_0 = _T_9[13]; // @[PixelRepeater.scala:28:7, :52:{48,108}]
assign io_resp_bits_mask_14_0 = _T_9[14]; // @[PixelRepeater.scala:28:7, :52:{48,108}]
assign io_resp_bits_mask_15_0 = _T_9[15]; // @[PixelRepeater.scala:28:7, :52:{48,108}]
assign _io_resp_bits_last_T_1 = req_bits_last & _io_resp_bits_last_T; // @[PixelRepeater.scala:44:18, :54:{40,67}]
assign io_resp_bits_last_0 = _io_resp_bits_last_T_1; // @[PixelRepeater.scala:28:7, :54:40] |
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_35 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, in_vc : UInt<0>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}, flip out_credit_available : { `1` : UInt<1>[1], `0` : UInt<1>[4]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}}
inst route_buffer of Queue2_Flit_70
connect route_buffer.clock, clock
connect route_buffer.reset, reset
inst route_q of Queue2_RouteComputerResp_35
connect route_q.clock, clock
connect route_q.reset, reset
node _T = eq(UInt<2>(0h2), io.in.bits.egress_id)
node _T_1 = eq(UInt<3>(0h6), io.in.bits.egress_id)
node _T_2 = eq(UInt<3>(0h7), io.in.bits.egress_id)
node _T_3 = eq(UInt<4>(0h8), io.in.bits.egress_id)
node _T_4 = eq(UInt<3>(0h5), io.in.bits.egress_id)
node _T_5 = eq(UInt<2>(0h3), io.in.bits.egress_id)
node _T_6 = eq(UInt<1>(0h1), io.in.bits.egress_id)
node _T_7 = eq(UInt<3>(0h4), io.in.bits.egress_id)
node _T_8 = or(_T, _T_1)
node _T_9 = or(_T_8, _T_2)
node _T_10 = or(_T_9, _T_3)
node _T_11 = or(_T_10, _T_4)
node _T_12 = or(_T_11, _T_5)
node _T_13 = or(_T_12, _T_6)
node _T_14 = or(_T_13, _T_7)
node _T_15 = eq(_T_14, UInt<1>(0h0))
node _T_16 = and(io.in.valid, _T_15)
node _T_17 = eq(_T_16, UInt<1>(0h0))
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
node _T_20 = eq(_T_17, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf
assert(clock, _T_17, UInt<1>(0h1), "") : assert
connect route_buffer.io.enq.bits.head, io.in.bits.head
connect route_buffer.io.enq.bits.tail, io.in.bits.tail
connect route_buffer.io.enq.bits.flow.ingress_node, UInt<4>(0hb)
connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0)
connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h1)
node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<2>(0h2), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<3>(0h6), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<3>(0h7), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<4>(0h8), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_4 = eq(UInt<3>(0h5), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_5 = eq(UInt<2>(0h3), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_6 = eq(UInt<1>(0h1), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_7 = eq(UInt<3>(0h4), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<1>(0h1), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h5), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_10 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<3>(0h6), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_11 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<3>(0h7), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_12 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_4, UInt<3>(0h4), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_13 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_5, UInt<2>(0h2), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_14 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_6, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_15 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_7, UInt<2>(0h3), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_16 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_9)
node _route_buffer_io_enq_bits_flow_egress_node_T_17 = or(_route_buffer_io_enq_bits_flow_egress_node_T_16, _route_buffer_io_enq_bits_flow_egress_node_T_10)
node _route_buffer_io_enq_bits_flow_egress_node_T_18 = or(_route_buffer_io_enq_bits_flow_egress_node_T_17, _route_buffer_io_enq_bits_flow_egress_node_T_11)
node _route_buffer_io_enq_bits_flow_egress_node_T_19 = or(_route_buffer_io_enq_bits_flow_egress_node_T_18, _route_buffer_io_enq_bits_flow_egress_node_T_12)
node _route_buffer_io_enq_bits_flow_egress_node_T_20 = or(_route_buffer_io_enq_bits_flow_egress_node_T_19, _route_buffer_io_enq_bits_flow_egress_node_T_13)
node _route_buffer_io_enq_bits_flow_egress_node_T_21 = or(_route_buffer_io_enq_bits_flow_egress_node_T_20, _route_buffer_io_enq_bits_flow_egress_node_T_14)
node _route_buffer_io_enq_bits_flow_egress_node_T_22 = or(_route_buffer_io_enq_bits_flow_egress_node_T_21, _route_buffer_io_enq_bits_flow_egress_node_T_15)
wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<3>
connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_22
connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE
node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<2>(0h2), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<3>(0h6), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<3>(0h7), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<4>(0h8), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = eq(UInt<3>(0h5), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = eq(UInt<2>(0h3), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = eq(UInt<1>(0h1), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = eq(UInt<3>(0h4), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_5, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_14 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_6, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_15 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_7, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_16 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_9)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_17 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_16, _route_buffer_io_enq_bits_flow_egress_node_id_T_10)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_18 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_17, _route_buffer_io_enq_bits_flow_egress_node_id_T_11)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_19 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_18, _route_buffer_io_enq_bits_flow_egress_node_id_T_12)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_20 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_19, _route_buffer_io_enq_bits_flow_egress_node_id_T_13)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_21 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_20, _route_buffer_io_enq_bits_flow_egress_node_id_T_14)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_22 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_21, _route_buffer_io_enq_bits_flow_egress_node_id_T_15)
wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1>
connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_22
connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE
connect route_buffer.io.enq.bits.payload, io.in.bits.payload
invalidate route_buffer.io.enq.bits.virt_channel_id
connect io.router_req.bits.src_virt_id, UInt<1>(0h0)
connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id
connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node
connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id
connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node
connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id
node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<4>(0hb))
node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0))
node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T)
node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest)
node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2)
connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3
node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready)
node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head)
node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0))
node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2)
connect io.router_req.valid, _io_router_req_valid_T_3
node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0))
node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T)
node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest)
node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2)
connect io.in.ready, _io_in_ready_T_3
node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid)
connect route_q.io.enq.valid, _route_q_io_enq_valid_T
connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0]
connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1]
connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2]
connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3]
connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0]
node _T_21 = and(io.in.ready, io.in.valid)
node _T_22 = and(_T_21, io.in.bits.head)
node _T_23 = and(_T_22, at_dest)
when _T_23 :
connect route_q.io.enq.valid, UInt<1>(0h1)
connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0)
node _T_24 = eq(UInt<4>(0hc), io.in.bits.egress_id)
when _T_24 :
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1)
node _T_25 = eq(route_q.io.enq.ready, UInt<1>(0h0))
node _T_26 = and(route_q.io.enq.valid, _T_25)
node _T_27 = eq(_T_26, UInt<1>(0h0))
node _T_28 = asUInt(reset)
node _T_29 = eq(_T_28, UInt<1>(0h0))
when _T_29 :
node _T_30 = eq(_T_27, UInt<1>(0h0))
when _T_30 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1
assert(clock, _T_27, UInt<1>(0h1), "") : assert_1
inst vcalloc_buffer of Queue2_Flit_71
connect vcalloc_buffer.clock, clock
connect vcalloc_buffer.reset, reset
inst vcalloc_q of Queue1_VCAllocResp_35
connect vcalloc_q.clock, clock
connect vcalloc_q.reset, reset
connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node
connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id
connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node
connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id
connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload
connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail
connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head
connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0`
connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1`
connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow
connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0)
node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T)
node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1)
node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3)
node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4)
connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5
node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid)
node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head)
node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready)
node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready)
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3
node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T)
node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1)
node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3)
node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4)
node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6)
node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7)
connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8
node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid)
node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail)
connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1
node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T
connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3]
connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0]
node _T_31 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0))
node _T_32 = and(vcalloc_q.io.enq.valid, _T_31)
node _T_33 = eq(_T_32, UInt<1>(0h0))
node _T_34 = asUInt(reset)
node _T_35 = eq(_T_34, UInt<1>(0h0))
when _T_35 :
node _T_36 = eq(_T_33, UInt<1>(0h0))
when _T_36 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2
assert(clock, _T_33, UInt<1>(0h1), "") : assert_2
connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0`
connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1`
connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail
node c_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node c_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _c_T = cat(c_hi, c_lo)
node _c_T_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T)
node c_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node c_hi_1 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node _c_T_2 = cat(c_hi_1, c_lo_1)
node _c_T_3 = cat(io.out_credit_available.`1`[0], _c_T_2)
node _c_T_4 = and(_c_T_1, _c_T_3)
node c = neq(_c_T_4, UInt<1>(0h0))
node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid)
node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c)
node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0))
node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2)
connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3
node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid)
node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c)
node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0))
node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2)
connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3
node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T)
connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1
reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}, clock
connect io.out[0], out_bundle
node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
connect out_bundle.valid, _out_bundle_valid_T
connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits
connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0)
node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1])
node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node out_channel_oh_0 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node out_bundle_bits_out_virt_channel_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node out_bundle_bits_out_virt_channel_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo)
node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 2)
node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 1, 0)
node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1)
node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1)
node _out_bundle_bits_out_virt_channel_T_3 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 1)
node _out_bundle_bits_out_virt_channel_T_4 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_3)
node _out_bundle_bits_out_virt_channel_T_5 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_4, UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_6 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_7 = or(_out_bundle_bits_out_virt_channel_T_5, _out_bundle_bits_out_virt_channel_T_6)
wire _out_bundle_bits_out_virt_channel_WIRE : UInt<2>
connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_7
connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE
node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0))
node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T)
connect io.debug.va_stall, _io_debug_va_stall_T_1
node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T)
connect io.debug.sa_stall, _io_debug_sa_stall_T_1 | module IngressUnit_35( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [36:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [36:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [3:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire [36:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [36:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 4'h2; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 4'h6; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 4'h7; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 4'h8; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 4'h5; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 4'h3; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = io_in_bits_egress_id == 4'h4; // @[IngressUnit.scala:30:72]
wire [2:0] _route_buffer_io_enq_bits_flow_egress_node_T_19 = (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 3'h5 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 3'h6 : 3'h0) | {3{_route_buffer_io_enq_bits_flow_egress_node_id_T_3}} | {_route_buffer_io_enq_bits_flow_egress_node_id_T_4, 1'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T}; // @[Mux.scala:30:73]
wire [3:0] route_buffer_io_enq_bits_flow_egress_node = {1'h0, _route_buffer_io_enq_bits_flow_egress_node_T_19[2], _route_buffer_io_enq_bits_flow_egress_node_T_19[1:0] | {_route_buffer_io_enq_bits_flow_egress_node_id_T_5, 1'h0} | {2{_route_buffer_io_enq_bits_flow_egress_node_id_T_7}}}; // @[Mux.scala:30:73]
wire _io_router_req_valid_T_1 = io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head; // @[IngressUnit.scala:26:28, :58:{38,67}]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to this FIRRTL code module SystemBus :
output auto : { flip coupler_from_rockettile_tl_master_clock_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bus_named_coh_widget_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip coupler_from_bus_named_fbus_bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bus_named_cbus_bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out_2 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_1 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_0 : { clock : Clock, reset : Reset}, flip sbus_clock_groups_in : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}}, sbus_clock_groups_out : { member : { coh_0 : { clock : Clock, reset : Reset}}}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst sbus_clock_groups of ClockGroupAggregator_sbus
inst clockGroup of ClockGroup
inst fixedClockNode of FixedClockBroadcast_4
inst broadcast of BundleBridgeNexus_NoOutput
inst system_bus_xbar of TLXbar_sbus_i2_o2_a32d64s6k3z4u
connect system_bus_xbar.clock, childClock
connect system_bus_xbar.reset, childReset
inst fixer of TLFIFOFixer
connect fixer.clock, childClock
connect fixer.reset, childReset
inst coupler_to_bus_named_cbus of TLInterconnectCoupler_sbus_to_bus_named_cbus
connect coupler_to_bus_named_cbus.clock, childClock
connect coupler_to_bus_named_cbus.reset, childReset
inst coupler_from_bus_named_fbus of TLInterconnectCoupler_sbus_from_bus_named_fbus
connect coupler_from_bus_named_fbus.clock, childClock
connect coupler_from_bus_named_fbus.reset, childReset
inst coupler_to_bus_named_coh of TLInterconnectCoupler_sbus_to_bus_named_coh
connect coupler_to_bus_named_coh.clock, childClock
connect coupler_to_bus_named_coh.reset, childReset
inst coupler_from_rockettile of TLInterconnectCoupler_sbus_from_rockettile
connect coupler_from_rockettile.clock, childClock
connect coupler_from_rockettile.reset, childReset
wire clockSinkNodeIn : { clock : Clock, reset : Reset}
invalidate clockSinkNodeIn.reset
invalidate clockSinkNodeIn.clock
connect clockGroup.auto.in, sbus_clock_groups.auto.out_0
connect fixedClockNode.auto.anon_in, clockGroup.auto.out
connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0
connect coupler_to_bus_named_cbus.auto.widget_anon_in, system_bus_xbar.auto.anon_out_0
connect coupler_to_bus_named_coh.auto.widget_anon_in, system_bus_xbar.auto.anon_out_1
connect system_bus_xbar.auto.anon_in_0, fixer.auto.anon_out_0
connect system_bus_xbar.auto.anon_in_1, fixer.auto.anon_out_1
connect fixer.auto.anon_in_0, coupler_from_bus_named_fbus.auto.widget_anon_out
connect fixer.auto.anon_in_1, coupler_from_rockettile.auto.tl_out
connect auto.sbus_clock_groups_out, sbus_clock_groups.auto.out_1
connect sbus_clock_groups.auto.in, auto.sbus_clock_groups_in
connect auto.fixedClockNode_anon_out_0, fixedClockNode.auto.anon_out_1
connect auto.fixedClockNode_anon_out_1, fixedClockNode.auto.anon_out_2
connect auto.fixedClockNode_anon_out_2, fixedClockNode.auto.anon_out_3
connect coupler_to_bus_named_cbus.auto.bus_xing_out.d, auto.coupler_to_bus_named_cbus_bus_xing_out.d
connect auto.coupler_to_bus_named_cbus_bus_xing_out.a.bits, coupler_to_bus_named_cbus.auto.bus_xing_out.a.bits
connect auto.coupler_to_bus_named_cbus_bus_xing_out.a.valid, coupler_to_bus_named_cbus.auto.bus_xing_out.a.valid
connect coupler_to_bus_named_cbus.auto.bus_xing_out.a.ready, auto.coupler_to_bus_named_cbus_bus_xing_out.a.ready
connect coupler_from_bus_named_fbus.auto.bus_xing_in, auto.coupler_from_bus_named_fbus_bus_xing_in
connect coupler_to_bus_named_coh.auto.widget_anon_out.d, auto.coupler_to_bus_named_coh_widget_anon_out.d
connect auto.coupler_to_bus_named_coh_widget_anon_out.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out.a.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out.a.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out.a.ready
connect coupler_from_rockettile.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in
connect childClock, clockSinkNodeIn.clock
connect childReset, clockSinkNodeIn.reset
connect clock, clockSinkNodeIn.clock
connect reset, clockSinkNodeIn.reset | module SystemBus( // @[ClockDomain.scala:14:9]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_2_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_2_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_1_clock, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_1_reset, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_0_clock, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_sbus_clock_groups_out_member_coh_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_sbus_clock_groups_out_member_coh_0_reset // @[LazyModuleImp.scala:107:25]
);
wire coupler_to_bus_named_coh_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire coupler_from_bus_named_fbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [4:0] coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [4:0] coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [28:0] coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [28:0] coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire fixer_auto_anon_out_0_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_0_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_0_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_auto_anon_out_0_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_0_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_0_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_0_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_1_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_1_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_1_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_1_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_1_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_0_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_0_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_auto_anon_in_0_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_0_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_0_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_0_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_0_a_bits_data; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_in_0_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_0_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_auto_anon_in_0_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_0_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_0_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_0_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_1_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_1_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_1_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_1_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_1_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_1_a_bits_data; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_in_1_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_1_a_bits_address; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_1_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_1_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_1_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire sbus_clock_groups_auto_out_0_member_sbus_0_reset; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_out_0_member_sbus_0_clock; // @[ClockGroup.scala:53:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_a_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_mask_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_d_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_a_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_d_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_in_member_sbus_1_clock_0 = auto_sbus_clock_groups_in_member_sbus_1_clock; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_in_member_sbus_1_reset_0 = auto_sbus_clock_groups_in_member_sbus_1_reset; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_in_member_sbus_0_clock_0 = auto_sbus_clock_groups_in_member_sbus_0_clock; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_in_member_sbus_0_reset_0 = auto_sbus_clock_groups_in_member_sbus_0_reset; // @[ClockDomain.scala:14:9]
wire [1:0] fixer__allIDs_FIFOed_T_1 = 2'h3; // @[FIFOFixer.scala:127:48]
wire fixer__a_id_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50]
wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47]
wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50]
wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47]
wire fixer__a_id_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire fixer__anonOut_a_valid_T_3 = 1'h1; // @[FIFOFixer.scala:95:50]
wire fixer__anonOut_a_valid_T_4 = 1'h1; // @[FIFOFixer.scala:95:47]
wire fixer__anonIn_a_ready_T_3 = 1'h1; // @[FIFOFixer.scala:96:50]
wire fixer__anonIn_a_ready_T_4 = 1'h1; // @[FIFOFixer.scala:96:47]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire sbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire sbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire sbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire fixer__a_notFIFO_T_40 = 1'h0; // @[Mux.scala:30:73]
wire fixer_a_noDomain = 1'h0; // @[FIFOFixer.scala:63:29]
wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__a_notFIFO_T_83 = 1'h0; // @[Mux.scala:30:73]
wire fixer_a_noDomain_1 = 1'h0; // @[FIFOFixer.scala:63:29]
wire fixer__flight_WIRE_1_0 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_1 = 1'h0; // @[FIFOFixer.scala:79:35]
wire [16:0] fixer__allIDs_FIFOed_T = 17'h1FFFF; // @[FIFOFixer.scala:127:48]
wire [32:0] fixer__a_id_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] fixer__a_id_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] fixer__a_id_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] fixer__a_id_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_a_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_d_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_d_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_a_ready = auto_coupler_to_bus_named_coh_widget_anon_out_a_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_auto_widget_anon_out_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_d_valid = auto_coupler_to_bus_named_coh_widget_anon_out_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_denied = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_from_bus_named_fbus_auto_bus_xing_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coupler_from_bus_named_fbus_auto_bus_xing_in_a_valid = auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_opcode = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_param = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_size = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [4:0] coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_source = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_address = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_mask = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_data = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_corrupt = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coupler_from_bus_named_fbus_auto_bus_xing_in_d_ready = auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_from_bus_named_fbus_auto_bus_xing_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [4:0] coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_auto_bus_xing_out_a_ready = auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_cbus_auto_bus_xing_out_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [28:0] coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_auto_bus_xing_out_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_auto_bus_xing_out_d_valid = auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_opcode = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_param = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_size = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [5:0] coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_source = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_sink = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_denied = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_data = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_corrupt = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire sbus_clock_groups_auto_in_member_sbus_1_clock = auto_sbus_clock_groups_in_member_sbus_1_clock_0; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_in_member_sbus_1_reset = auto_sbus_clock_groups_in_member_sbus_1_reset_0; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_in_member_sbus_0_clock = auto_sbus_clock_groups_in_member_sbus_0_clock_0; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_in_member_sbus_0_reset = auto_sbus_clock_groups_in_member_sbus_0_reset_0; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_out_1_member_coh_0_clock; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_out_1_member_coh_0_reset; // @[ClockGroup.scala:53:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [28:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_out_member_coh_0_clock_0; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_out_member_coh_0_reset_0; // @[ClockDomain.scala:14:9]
wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
wire sbus_clock_groups_nodeIn_member_sbus_1_clock = sbus_clock_groups_auto_in_member_sbus_1_clock; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_nodeIn_member_sbus_1_reset = sbus_clock_groups_auto_in_member_sbus_1_reset; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_nodeIn_member_sbus_0_clock = sbus_clock_groups_auto_in_member_sbus_0_clock; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_nodeIn_member_sbus_0_reset = sbus_clock_groups_auto_in_member_sbus_0_reset; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_x1_nodeOut_member_coh_0_clock; // @[MixedNode.scala:542:17]
assign auto_sbus_clock_groups_out_member_coh_0_clock_0 = sbus_clock_groups_auto_out_1_member_coh_0_clock; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_x1_nodeOut_member_coh_0_reset; // @[MixedNode.scala:542:17]
assign auto_sbus_clock_groups_out_member_coh_0_reset_0 = sbus_clock_groups_auto_out_1_member_coh_0_reset; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_nodeOut_member_sbus_0_clock; // @[MixedNode.scala:542:17]
wire sbus_clock_groups_nodeOut_member_sbus_0_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_in_member_sbus_0_clock = sbus_clock_groups_auto_out_0_member_sbus_0_clock; // @[ClockGroup.scala:24:9, :53:9]
wire clockGroup_auto_in_member_sbus_0_reset = sbus_clock_groups_auto_out_0_member_sbus_0_reset; // @[ClockGroup.scala:24:9, :53:9]
assign sbus_clock_groups_x1_nodeOut_member_coh_0_clock = sbus_clock_groups_nodeIn_member_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17]
assign sbus_clock_groups_x1_nodeOut_member_coh_0_reset = sbus_clock_groups_nodeIn_member_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17]
assign sbus_clock_groups_nodeOut_member_sbus_0_clock = sbus_clock_groups_nodeIn_member_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign sbus_clock_groups_nodeOut_member_sbus_0_reset = sbus_clock_groups_nodeIn_member_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign sbus_clock_groups_auto_out_0_member_sbus_0_clock = sbus_clock_groups_nodeOut_member_sbus_0_clock; // @[ClockGroup.scala:53:9]
assign sbus_clock_groups_auto_out_0_member_sbus_0_reset = sbus_clock_groups_nodeOut_member_sbus_0_reset; // @[ClockGroup.scala:53:9]
assign sbus_clock_groups_auto_out_1_member_coh_0_clock = sbus_clock_groups_x1_nodeOut_member_coh_0_clock; // @[ClockGroup.scala:53:9]
assign sbus_clock_groups_auto_out_1_member_coh_0_reset = sbus_clock_groups_x1_nodeOut_member_coh_0_reset; // @[ClockGroup.scala:53:9]
wire clockGroup_nodeIn_member_sbus_0_clock = clockGroup_auto_in_member_sbus_0_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17]
wire clockGroup_nodeIn_member_sbus_0_reset = clockGroup_auto_in_member_sbus_0_reset; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire fixer_x1_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_auto_tl_out_a_ready = fixer_auto_anon_in_1_a_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_a_valid = fixer_auto_anon_in_1_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_auto_tl_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_a_bits_opcode = fixer_auto_anon_in_1_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_auto_tl_out_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_a_bits_param = fixer_auto_anon_in_1_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_auto_tl_out_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] fixer_x1_anonIn_a_bits_size = fixer_auto_anon_in_1_a_bits_size; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_a_bits_source = fixer_auto_anon_in_1_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [31:0] fixer_x1_anonIn_a_bits_address = fixer_auto_anon_in_1_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] coupler_from_rockettile_auto_tl_out_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [7:0] fixer_x1_anonIn_a_bits_mask = fixer_auto_anon_in_1_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] coupler_from_rockettile_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [63:0] fixer_x1_anonIn_a_bits_data = fixer_auto_anon_in_1_a_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_a_bits_corrupt = fixer_auto_anon_in_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_d_ready; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_d_ready = fixer_auto_anon_in_1_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] fixer_x1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_auto_tl_out_d_valid = fixer_auto_anon_in_1_d_valid; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_auto_tl_out_d_bits_opcode = fixer_auto_anon_in_1_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_auto_tl_out_d_bits_param = fixer_auto_anon_in_1_d_bits_param; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_auto_tl_out_d_bits_size = fixer_auto_anon_in_1_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_x1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_auto_tl_out_d_bits_source = fixer_auto_anon_in_1_d_bits_source; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_auto_tl_out_d_bits_sink = fixer_auto_anon_in_1_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_x1_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_auto_tl_out_d_bits_denied = fixer_auto_anon_in_1_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_rockettile_auto_tl_out_d_bits_data = fixer_auto_anon_in_1_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_auto_tl_out_d_bits_corrupt = fixer_auto_anon_in_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_bus_named_fbus_auto_widget_anon_out_a_ready = fixer_auto_anon_in_0_a_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_bus_named_fbus_auto_widget_anon_out_a_valid; // @[LazyModuleImp.scala:138:7]
wire fixer_anonIn_a_valid = fixer_auto_anon_in_0_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_0_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_0_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_0_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [4:0] coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [4:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_0_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [31:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_0_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_0_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_0_a_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_bus_named_fbus_auto_widget_anon_out_d_ready; // @[LazyModuleImp.scala:138:7]
wire fixer_anonIn_d_ready = fixer_auto_anon_in_0_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire coupler_from_bus_named_fbus_auto_widget_anon_out_d_valid = fixer_auto_anon_in_0_d_valid; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_opcode = fixer_auto_anon_in_0_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_param = fixer_auto_anon_in_0_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_size = fixer_auto_anon_in_0_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [4:0] coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_source = fixer_auto_anon_in_0_d_bits_source; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_sink = fixer_auto_anon_in_0_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_denied = fixer_auto_anon_in_0_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_data = fixer_auto_anon_in_0_d_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_corrupt = fixer_auto_anon_in_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_a_ready = fixer_auto_anon_out_1_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] fixer_x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] fixer_x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] fixer_x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] fixer_x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_d_valid = fixer_auto_anon_out_1_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_x1_anonOut_d_bits_opcode = fixer_auto_anon_out_1_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonOut_d_bits_param = fixer_auto_anon_out_1_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonOut_d_bits_size = fixer_auto_anon_out_1_d_bits_size; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_d_bits_source = fixer_auto_anon_out_1_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_x1_anonOut_d_bits_sink = fixer_auto_anon_out_1_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_d_bits_denied = fixer_auto_anon_out_1_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_x1_anonOut_d_bits_data = fixer_auto_anon_out_1_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_d_bits_corrupt = fixer_auto_anon_out_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_a_ready = fixer_auto_anon_out_0_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_valid = fixer_auto_anon_out_0_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_0_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_anonOut_d_bits_param = fixer_auto_anon_out_0_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_0_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_0_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonOut_d_bits_sink = fixer_auto_anon_out_0_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_d_bits_denied = fixer_auto_anon_out_0_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_0_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_d_bits_corrupt = fixer_auto_anon_out_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_1_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_1_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_1_a_bits_size; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_1_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_out_1_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_1_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_d_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_0_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_0_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_0_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_auto_anon_out_0_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_0_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_out_0_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_0_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33]
assign fixer_auto_anon_out_0_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9]
assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_param = fixer_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_sink = fixer_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_denied = fixer_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_corrupt = fixer_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire fixer__anonOut_a_valid_T_5; // @[FIFOFixer.scala:95:33]
wire fixer__anonIn_a_ready_T_5 = fixer_x1_anonOut_a_ready; // @[FIFOFixer.scala:96:33]
assign fixer_auto_anon_out_1_a_valid = fixer_x1_anonOut_a_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_opcode = fixer_x1_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_param = fixer_x1_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_size = fixer_x1_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_source = fixer_x1_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_address = fixer_x1_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_mask = fixer_x1_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_data = fixer_x1_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_corrupt = fixer_x1_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_d_ready = fixer_x1_anonOut_d_ready; // @[FIFOFixer.scala:50:9]
assign fixer_x1_anonIn_d_valid = fixer_x1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_opcode = fixer_x1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_param = fixer_x1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_size = fixer_x1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_source = fixer_x1_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_sink = fixer_x1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_denied = fixer_x1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_data = fixer_x1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_corrupt = fixer_x1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_0_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9]
assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33]
assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31]
assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_0_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_param = fixer_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_sink = fixer_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_denied = fixer_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_corrupt = fixer_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_a_ready = fixer_x1_anonIn_a_ready; // @[FIFOFixer.scala:50:9]
assign fixer__anonOut_a_valid_T_5 = fixer_x1_anonIn_a_valid; // @[FIFOFixer.scala:95:33]
assign fixer_x1_anonOut_a_bits_opcode = fixer_x1_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_param = fixer_x1_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_size = fixer_x1_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_source = fixer_x1_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_address = fixer_x1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] fixer__a_notFIFO_T_43 = fixer_x1_anonIn_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] fixer__a_id_T_5 = fixer_x1_anonIn_a_bits_address; // @[Parameters.scala:137:31]
assign fixer_x1_anonOut_a_bits_mask = fixer_x1_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_data = fixer_x1_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_corrupt = fixer_x1_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_d_ready = fixer_x1_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_1_d_valid = fixer_x1_anonIn_d_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_opcode = fixer_x1_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_param = fixer_x1_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_size = fixer_x1_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_source = fixer_x1_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_sink = fixer_x1_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_denied = fixer_x1_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_data = fixer_x1_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_corrupt = fixer_x1_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [32:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_2 = fixer__a_notFIFO_T_1 & 33'h8E000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_3 = fixer__a_notFIFO_T_2; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_4 = fixer__a_notFIFO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_5 = {fixer_anonIn_a_bits_address[31:21], fixer_anonIn_a_bits_address[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_6 = {1'h0, fixer__a_notFIFO_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_7 = fixer__a_notFIFO_T_6 & 33'h8E101000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_8 = fixer__a_notFIFO_T_7; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_9 = fixer__a_notFIFO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN = {fixer_anonIn_a_bits_address[31:26], fixer_anonIn_a_bits_address[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31]
wire [31:0] fixer__a_notFIFO_T_10; // @[Parameters.scala:137:31]
assign fixer__a_notFIFO_T_10 = _GEN; // @[Parameters.scala:137:31]
wire [31:0] fixer__a_notFIFO_T_15; // @[Parameters.scala:137:31]
assign fixer__a_notFIFO_T_15 = _GEN; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_11 = {1'h0, fixer__a_notFIFO_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_12 = fixer__a_notFIFO_T_11 & 33'h8E100000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_13 = fixer__a_notFIFO_T_12; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_14 = fixer__a_notFIFO_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] fixer__a_notFIFO_T_16 = {1'h0, fixer__a_notFIFO_T_15}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_17 = fixer__a_notFIFO_T_16 & 33'h8E101000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_18 = fixer__a_notFIFO_T_17; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_19 = fixer__a_notFIFO_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_20 = {fixer_anonIn_a_bits_address[31:28], fixer_anonIn_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_21 = {1'h0, fixer__a_notFIFO_T_20}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_22 = fixer__a_notFIFO_T_21 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_23 = fixer__a_notFIFO_T_22; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_24 = fixer__a_notFIFO_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_25 = fixer__a_notFIFO_T_4 | fixer__a_notFIFO_T_9; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_26 = fixer__a_notFIFO_T_25 | fixer__a_notFIFO_T_14; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_27 = fixer__a_notFIFO_T_26 | fixer__a_notFIFO_T_19; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_28 = fixer__a_notFIFO_T_27 | fixer__a_notFIFO_T_24; // @[Parameters.scala:629:89]
wire [31:0] fixer__a_notFIFO_T_29 = {fixer_anonIn_a_bits_address[31:28], fixer_anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_30 = {1'h0, fixer__a_notFIFO_T_29}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_31 = fixer__a_notFIFO_T_30 & 33'h8E100000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_32 = fixer__a_notFIFO_T_31; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_33 = fixer__a_notFIFO_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_34 = fixer_anonIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_35 = {1'h0, fixer__a_notFIFO_T_34}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_36 = fixer__a_notFIFO_T_35 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_37 = fixer__a_notFIFO_T_36; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_38 = fixer__a_notFIFO_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_39 = fixer__a_notFIFO_T_33 | fixer__a_notFIFO_T_38; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_41 = fixer__a_notFIFO_T_39; // @[Mux.scala:30:73]
wire fixer__a_notFIFO_T_42 = fixer__a_notFIFO_T_41; // @[Mux.scala:30:73]
wire fixer_a_notFIFO = fixer__a_notFIFO_T_42; // @[Mux.scala:30:73]
wire [32:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}]
wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__a_first_beats1_decode_T = 27'hFFF << fixer_anonIn_a_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] fixer_a_first_counter; // @[Edges.scala:229:27]
wire [9:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire fixer_a_first = fixer_a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__a_first_last_T = fixer_a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_a_first_last = fixer__a_first_last_T | fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__d_first_beats1_decode_T = 27'hFFF << fixer_anonOut_d_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [8:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] fixer_d_first_counter; // @[Edges.scala:229:27]
wire [9:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire fixer_d_first_first = fixer_d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__d_first_last_T = fixer_d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_d_first_last = fixer__d_first_last_T | fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63]
wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}]
reg fixer_flight_0; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1; // @[FIFOFixer.scala:79:27]
reg fixer_flight_2; // @[FIFOFixer.scala:79:27]
reg fixer_flight_3; // @[FIFOFixer.scala:79:27]
reg fixer_flight_4; // @[FIFOFixer.scala:79:27]
reg fixer_flight_5; // @[FIFOFixer.scala:79:27]
reg fixer_flight_6; // @[FIFOFixer.scala:79:27]
reg fixer_flight_7; // @[FIFOFixer.scala:79:27]
reg fixer_flight_8; // @[FIFOFixer.scala:79:27]
reg fixer_flight_9; // @[FIFOFixer.scala:79:27]
reg fixer_flight_10; // @[FIFOFixer.scala:79:27]
reg fixer_flight_11; // @[FIFOFixer.scala:79:27]
reg fixer_flight_12; // @[FIFOFixer.scala:79:27]
reg fixer_flight_13; // @[FIFOFixer.scala:79:27]
reg fixer_flight_14; // @[FIFOFixer.scala:79:27]
reg fixer_flight_15; // @[FIFOFixer.scala:79:27]
reg fixer_flight_16; // @[FIFOFixer.scala:79:27]
wire fixer__flight_T = ~fixer_a_notFIFO; // @[Mux.scala:30:73]
wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35]
assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33]
reg [16:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35]
wire [16:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36]
wire [16:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38]
wire [31:0] fixer__SourceIdSet_T = 32'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T & ~fixer_a_notFIFO ? fixer__SourceIdSet_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [31:0] fixer__SourceIdClear_T = 32'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [16:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed | fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40]
wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41]
wire [32:0] fixer__a_notFIFO_T_44 = {1'h0, fixer__a_notFIFO_T_43}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_45 = fixer__a_notFIFO_T_44 & 33'h8E000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_46 = fixer__a_notFIFO_T_45; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_47 = fixer__a_notFIFO_T_46 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_48 = {fixer_x1_anonIn_a_bits_address[31:21], fixer_x1_anonIn_a_bits_address[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_49 = {1'h0, fixer__a_notFIFO_T_48}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_50 = fixer__a_notFIFO_T_49 & 33'h8E101000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_51 = fixer__a_notFIFO_T_50; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_52 = fixer__a_notFIFO_T_51 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_0 = {fixer_x1_anonIn_a_bits_address[31:26], fixer_x1_anonIn_a_bits_address[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31]
wire [31:0] fixer__a_notFIFO_T_53; // @[Parameters.scala:137:31]
assign fixer__a_notFIFO_T_53 = _GEN_0; // @[Parameters.scala:137:31]
wire [31:0] fixer__a_notFIFO_T_58; // @[Parameters.scala:137:31]
assign fixer__a_notFIFO_T_58 = _GEN_0; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_54 = {1'h0, fixer__a_notFIFO_T_53}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_55 = fixer__a_notFIFO_T_54 & 33'h8E100000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_56 = fixer__a_notFIFO_T_55; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_57 = fixer__a_notFIFO_T_56 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] fixer__a_notFIFO_T_59 = {1'h0, fixer__a_notFIFO_T_58}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_60 = fixer__a_notFIFO_T_59 & 33'h8E101000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_61 = fixer__a_notFIFO_T_60; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_62 = fixer__a_notFIFO_T_61 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_63 = {fixer_x1_anonIn_a_bits_address[31:28], fixer_x1_anonIn_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_64 = {1'h0, fixer__a_notFIFO_T_63}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_65 = fixer__a_notFIFO_T_64 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_66 = fixer__a_notFIFO_T_65; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_67 = fixer__a_notFIFO_T_66 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_68 = fixer__a_notFIFO_T_47 | fixer__a_notFIFO_T_52; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_69 = fixer__a_notFIFO_T_68 | fixer__a_notFIFO_T_57; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_70 = fixer__a_notFIFO_T_69 | fixer__a_notFIFO_T_62; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_71 = fixer__a_notFIFO_T_70 | fixer__a_notFIFO_T_67; // @[Parameters.scala:629:89]
wire [31:0] fixer__a_notFIFO_T_72 = {fixer_x1_anonIn_a_bits_address[31:28], fixer_x1_anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_73 = {1'h0, fixer__a_notFIFO_T_72}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_74 = fixer__a_notFIFO_T_73 & 33'h8E100000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_75 = fixer__a_notFIFO_T_74; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_76 = fixer__a_notFIFO_T_75 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_77 = fixer_x1_anonIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_78 = {1'h0, fixer__a_notFIFO_T_77}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_79 = fixer__a_notFIFO_T_78 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_80 = fixer__a_notFIFO_T_79; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_81 = fixer__a_notFIFO_T_80 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_82 = fixer__a_notFIFO_T_76 | fixer__a_notFIFO_T_81; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_84 = fixer__a_notFIFO_T_82; // @[Mux.scala:30:73]
wire fixer__a_notFIFO_T_85 = fixer__a_notFIFO_T_84; // @[Mux.scala:30:73]
wire fixer_a_notFIFO_1 = fixer__a_notFIFO_T_85; // @[Mux.scala:30:73]
wire [32:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}]
wire fixer__a_first_T_1 = fixer_x1_anonIn_a_ready & fixer_x1_anonIn_a_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__a_first_beats1_decode_T_3 = 27'hFFF << fixer_x1_anonIn_a_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__a_first_beats1_decode_T_4 = fixer__a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__a_first_beats1_decode_T_5 = ~fixer__a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] fixer_a_first_beats1_decode_1 = fixer__a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire fixer__a_first_beats1_opdata_T_1 = fixer_x1_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire fixer_a_first_beats1_opdata_1 = ~fixer__a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] fixer_a_first_beats1_1 = fixer_a_first_beats1_opdata_1 ? fixer_a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] fixer_a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] fixer__a_first_counter1_T_1 = {1'h0, fixer_a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] fixer_a_first_counter1_1 = fixer__a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire fixer_a_first_1 = fixer_a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__a_first_last_T_2 = fixer_a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__a_first_last_T_3 = fixer_a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_a_first_last_1 = fixer__a_first_last_T_2 | fixer__a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire fixer_a_first_done_1 = fixer_a_first_last_1 & fixer__a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] fixer__a_first_count_T_1 = ~fixer_a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] fixer_a_first_count_1 = fixer_a_first_beats1_1 & fixer__a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] fixer__a_first_counter_T_1 = fixer_a_first_1 ? fixer_a_first_beats1_1 : fixer_a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_2 = fixer_x1_anonOut_d_ready & fixer_x1_anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__d_first_beats1_decode_T_3 = 27'hFFF << fixer_x1_anonOut_d_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__d_first_beats1_decode_T_4 = fixer__d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__d_first_beats1_decode_T_5 = ~fixer__d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] fixer_d_first_beats1_decode_1 = fixer__d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire fixer_d_first_beats1_opdata_1 = fixer_x1_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [8:0] fixer_d_first_beats1_1 = fixer_d_first_beats1_opdata_1 ? fixer_d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] fixer_d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] fixer__d_first_counter1_T_1 = {1'h0, fixer_d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] fixer_d_first_counter1_1 = fixer__d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire fixer_d_first_first_1 = fixer_d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__d_first_last_T_2 = fixer_d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__d_first_last_T_3 = fixer_d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_d_first_last_1 = fixer__d_first_last_T_2 | fixer__d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire fixer_d_first_done_1 = fixer_d_first_last_1 & fixer__d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] fixer__d_first_count_T_1 = ~fixer_d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] fixer_d_first_count_1 = fixer_d_first_beats1_1 & fixer__d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] fixer__d_first_counter_T_1 = fixer_d_first_first_1 ? fixer_d_first_beats1_1 : fixer_d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_3 = fixer_x1_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63]
wire fixer_d_first_1 = fixer_d_first_first_1 & fixer__d_first_T_3; // @[FIFOFixer.scala:75:{42,63}]
reg fixer_flight_1_0; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_1; // @[FIFOFixer.scala:79:27]
wire fixer__flight_T_1 = ~fixer_a_notFIFO_1; // @[Mux.scala:30:73]
wire fixer__T_32 = fixer_x1_anonIn_d_ready & fixer_x1_anonIn_d_valid; // @[Decoupled.scala:51:35]
assign fixer_x1_anonOut_a_valid = fixer__anonOut_a_valid_T_5; // @[FIFOFixer.scala:95:33]
assign fixer_x1_anonIn_a_ready = fixer__anonIn_a_ready_T_5; // @[FIFOFixer.scala:96:33]
reg [1:0] fixer_SourceIdFIFOed_1; // @[FIFOFixer.scala:115:35]
wire [1:0] fixer_SourceIdSet_1; // @[FIFOFixer.scala:116:36]
wire [1:0] fixer_SourceIdClear_1; // @[FIFOFixer.scala:117:38]
wire [1:0] fixer__SourceIdSet_T_1 = 2'h1 << fixer_x1_anonIn_a_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdSet_1 = fixer_a_first_1 & fixer__a_first_T_1 & ~fixer_a_notFIFO_1 ? fixer__SourceIdSet_T_1 : 2'h0; // @[OneHot.scala:58:35]
wire [1:0] fixer__SourceIdClear_T_1 = 2'h1 << fixer_x1_anonIn_d_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdClear_1 = fixer_d_first_1 & fixer__T_32 ? fixer__SourceIdClear_T_1 : 2'h0; // @[OneHot.scala:58:35]
wire [1:0] fixer__SourceIdFIFOed_T_1 = fixer_SourceIdFIFOed_1 | fixer_SourceIdSet_1; // @[FIFOFixer.scala:115:35, :116:36, :126:40]
wire fixer_allIDs_FIFOed_1 = &fixer_SourceIdFIFOed_1; // @[FIFOFixer.scala:115:35, :127:41]
wire coupler_to_bus_named_cbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_in_a_valid = coupler_to_bus_named_cbus_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [28:0] coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_in_d_ready = coupler_to_bus_named_cbus_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_bus_xingOut_a_ready = coupler_to_bus_named_cbus_auto_bus_xing_out_a_ready; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_cbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_cbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_cbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_to_bus_named_cbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_size; // @[ClockDomain.scala:14:9]
wire [5:0] coupler_to_bus_named_cbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_source; // @[ClockDomain.scala:14:9]
wire [28:0] coupler_to_bus_named_cbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_to_bus_named_cbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_cbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_cbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_cbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_d_ready; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_cbus_bus_xingOut_d_valid = coupler_to_bus_named_cbus_auto_bus_xing_out_d_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_cbus_bus_xingOut_d_bits_opcode = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_to_bus_named_cbus_bus_xingOut_d_bits_param = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_to_bus_named_cbus_bus_xingOut_d_bits_size = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_size; // @[MixedNode.scala:542:17]
wire [5:0] coupler_to_bus_named_cbus_bus_xingOut_d_bits_source = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_source; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_cbus_bus_xingOut_d_bits_sink = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_cbus_bus_xingOut_d_bits_denied = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_denied; // @[MixedNode.scala:542:17]
wire [63:0] coupler_to_bus_named_cbus_bus_xingOut_d_bits_data = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_data; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_cbus_bus_xingOut_d_bits_corrupt = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_cbus_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_cbus_auto_widget_anon_in_a_ready = coupler_to_bus_named_cbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_anonIn_a_valid = coupler_to_bus_named_cbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_widget_anonIn_a_bits_opcode = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_widget_anonIn_a_bits_param = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_cbus_widget_anonIn_a_bits_size = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_cbus_widget_anonIn_a_bits_source = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [28:0] coupler_to_bus_named_cbus_widget_anonIn_a_bits_address = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_cbus_widget_anonIn_a_bits_mask = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_cbus_widget_anonIn_a_bits_data = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_anonIn_d_ready = coupler_to_bus_named_cbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_valid = coupler_to_bus_named_cbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_cbus_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_cbus_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_cbus_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_cbus_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_cbus_widget_anonOut_a_ready = coupler_to_bus_named_cbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_cbus_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_cbus_bus_xingIn_a_valid = coupler_to_bus_named_cbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_cbus_bus_xingIn_a_bits_opcode = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_cbus_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_cbus_bus_xingIn_a_bits_param = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_cbus_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] coupler_to_bus_named_cbus_bus_xingIn_a_bits_size = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [28:0] coupler_to_bus_named_cbus_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [5:0] coupler_to_bus_named_cbus_bus_xingIn_a_bits_source = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_cbus_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [28:0] coupler_to_bus_named_cbus_bus_xingIn_a_bits_address = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_cbus_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] coupler_to_bus_named_cbus_bus_xingIn_a_bits_mask = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire [63:0] coupler_to_bus_named_cbus_bus_xingIn_a_bits_data = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_cbus_bus_xingIn_a_bits_corrupt = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_bus_xingIn_d_ready = coupler_to_bus_named_cbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_cbus_widget_anonOut_d_valid = coupler_to_bus_named_cbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_to_bus_named_cbus_widget_anonOut_d_bits_opcode = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_cbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] coupler_to_bus_named_cbus_widget_anonOut_d_bits_param = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_cbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] coupler_to_bus_named_cbus_widget_anonOut_d_bits_size = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_cbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [5:0] coupler_to_bus_named_cbus_widget_anonOut_d_bits_source = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_cbus_widget_anonOut_d_bits_sink = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_cbus_widget_anonOut_d_bits_denied = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_cbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [63:0] coupler_to_bus_named_cbus_widget_anonOut_d_bits_data = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_cbus_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_anonIn_a_ready = coupler_to_bus_named_cbus_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_valid = coupler_to_bus_named_cbus_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_cbus_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_cbus_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_cbus_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_cbus_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_cbus_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_cbus_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_cbus_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_cbus_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_ready = coupler_to_bus_named_cbus_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_anonIn_d_valid = coupler_to_bus_named_cbus_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_opcode = coupler_to_bus_named_cbus_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_param = coupler_to_bus_named_cbus_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_size = coupler_to_bus_named_cbus_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_source = coupler_to_bus_named_cbus_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_sink = coupler_to_bus_named_cbus_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_denied = coupler_to_bus_named_cbus_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_data = coupler_to_bus_named_cbus_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_cbus_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_auto_anon_in_a_ready = coupler_to_bus_named_cbus_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_anonOut_a_valid = coupler_to_bus_named_cbus_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_opcode = coupler_to_bus_named_cbus_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_param = coupler_to_bus_named_cbus_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_size = coupler_to_bus_named_cbus_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_source = coupler_to_bus_named_cbus_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_address = coupler_to_bus_named_cbus_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_mask = coupler_to_bus_named_cbus_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_data = coupler_to_bus_named_cbus_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_cbus_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonOut_d_ready = coupler_to_bus_named_cbus_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_valid = coupler_to_bus_named_cbus_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_cbus_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_cbus_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_cbus_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_cbus_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_cbus_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_cbus_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_cbus_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_cbus_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_bus_xingIn_a_ready = coupler_to_bus_named_cbus_bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_valid = coupler_to_bus_named_cbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_opcode = coupler_to_bus_named_cbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_param = coupler_to_bus_named_cbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_size = coupler_to_bus_named_cbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_source = coupler_to_bus_named_cbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_address = coupler_to_bus_named_cbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_mask = coupler_to_bus_named_cbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_data = coupler_to_bus_named_cbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_corrupt = coupler_to_bus_named_cbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_cbus_auto_bus_xing_out_d_ready = coupler_to_bus_named_cbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_cbus_bus_xingIn_d_valid = coupler_to_bus_named_cbus_bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_opcode = coupler_to_bus_named_cbus_bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_param = coupler_to_bus_named_cbus_bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_size = coupler_to_bus_named_cbus_bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_source = coupler_to_bus_named_cbus_bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_sink = coupler_to_bus_named_cbus_bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_denied = coupler_to_bus_named_cbus_bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_data = coupler_to_bus_named_cbus_bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_corrupt = coupler_to_bus_named_cbus_bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_ready = coupler_to_bus_named_cbus_bus_xingIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_bus_xingOut_a_valid = coupler_to_bus_named_cbus_bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_opcode = coupler_to_bus_named_cbus_bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_param = coupler_to_bus_named_cbus_bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_size = coupler_to_bus_named_cbus_bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_source = coupler_to_bus_named_cbus_bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_address = coupler_to_bus_named_cbus_bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_mask = coupler_to_bus_named_cbus_bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_data = coupler_to_bus_named_cbus_bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_corrupt = coupler_to_bus_named_cbus_bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingOut_d_ready = coupler_to_bus_named_cbus_bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_valid = coupler_to_bus_named_cbus_bus_xingIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_cbus_bus_xingIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_cbus_bus_xingIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_cbus_bus_xingIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_cbus_bus_xingIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_cbus_bus_xingIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_cbus_bus_xingIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_cbus_bus_xingIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_cbus_bus_xingIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_out_a_ready = coupler_from_bus_named_fbus_auto_widget_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
assign fixer_auto_anon_in_0_a_valid = coupler_from_bus_named_fbus_auto_widget_anon_out_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign fixer_auto_anon_in_0_a_bits_opcode = coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
assign fixer_auto_anon_in_0_a_bits_param = coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
assign fixer_auto_anon_in_0_a_bits_size = coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [4:0] coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
assign fixer_auto_anon_in_0_a_bits_source = coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
assign fixer_auto_anon_in_0_a_bits_address = coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
assign fixer_auto_anon_in_0_a_bits_mask = coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
assign fixer_auto_anon_in_0_a_bits_data = coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign fixer_auto_anon_in_0_a_bits_corrupt = coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
assign fixer_auto_anon_in_0_d_ready = coupler_from_bus_named_fbus_auto_widget_anon_out_d_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_out_d_valid = coupler_from_bus_named_fbus_auto_widget_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_opcode = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_param = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_size = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_source = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_sink = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_denied = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_data = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_corrupt = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_a_ready; // @[ClockDomain.scala:14:9]
wire coupler_from_bus_named_fbus_bus_xingIn_a_valid = coupler_from_bus_named_fbus_auto_bus_xing_in_a_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_bus_named_fbus_bus_xingIn_a_bits_opcode = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_bus_named_fbus_bus_xingIn_a_bits_param = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_bus_named_fbus_bus_xingIn_a_bits_size = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] coupler_from_bus_named_fbus_bus_xingIn_a_bits_source = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_bus_named_fbus_bus_xingIn_a_bits_address = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] coupler_from_bus_named_fbus_bus_xingIn_a_bits_mask = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_bus_named_fbus_bus_xingIn_a_bits_data = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_bus_named_fbus_bus_xingIn_a_bits_corrupt = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_from_bus_named_fbus_bus_xingIn_d_ready = coupler_from_bus_named_fbus_auto_bus_xing_in_d_ready; // @[MixedNode.scala:551:17]
wire coupler_from_bus_named_fbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_bus_named_fbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_bus_named_fbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_bus_named_fbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_size; // @[ClockDomain.scala:14:9]
wire [4:0] coupler_from_bus_named_fbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_source; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_bus_named_fbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_sink; // @[ClockDomain.scala:14:9]
wire coupler_from_bus_named_fbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_bus_named_fbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_from_bus_named_fbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_from_bus_named_fbus_widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire coupler_from_bus_named_fbus_bus_xingOut_a_ready = coupler_from_bus_named_fbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
wire coupler_from_bus_named_fbus_widget_anonIn_a_valid = coupler_from_bus_named_fbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_bus_named_fbus_widget_anonIn_a_bits_opcode = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_bus_named_fbus_widget_anonIn_a_bits_param = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_from_bus_named_fbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_bus_named_fbus_widget_anonIn_a_bits_size = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] coupler_from_bus_named_fbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [4:0] coupler_from_bus_named_fbus_widget_anonIn_a_bits_source = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_from_bus_named_fbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_bus_named_fbus_widget_anonIn_a_bits_address = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_from_bus_named_fbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [7:0] coupler_from_bus_named_fbus_widget_anonIn_a_bits_mask = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_from_bus_named_fbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_bus_named_fbus_widget_anonIn_a_bits_data = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_bus_named_fbus_widget_anonIn_a_bits_corrupt = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
wire coupler_from_bus_named_fbus_widget_anonIn_d_ready = coupler_from_bus_named_fbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_bus_named_fbus_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire coupler_from_bus_named_fbus_bus_xingOut_d_valid = coupler_from_bus_named_fbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_from_bus_named_fbus_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_bus_named_fbus_bus_xingOut_d_bits_opcode = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_from_bus_named_fbus_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_bus_named_fbus_bus_xingOut_d_bits_param = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [4:0] coupler_from_bus_named_fbus_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_bus_named_fbus_bus_xingOut_d_bits_size = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [4:0] coupler_from_bus_named_fbus_bus_xingOut_d_bits_source = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_bus_named_fbus_bus_xingOut_d_bits_sink = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_from_bus_named_fbus_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_bus_named_fbus_bus_xingOut_d_bits_denied = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_bus_named_fbus_bus_xingOut_d_bits_data = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_bus_xingOut_d_bits_corrupt = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_anonOut_a_ready = coupler_from_bus_named_fbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_valid = coupler_from_bus_named_fbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_opcode = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_param = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_from_bus_named_fbus_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_size = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] coupler_from_bus_named_fbus_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_source = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_from_bus_named_fbus_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_address = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_from_bus_named_fbus_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_mask = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_from_bus_named_fbus_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_data = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_corrupt = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_from_bus_named_fbus_auto_widget_anon_out_d_ready = coupler_from_bus_named_fbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_anonOut_d_valid = coupler_from_bus_named_fbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_anonOut_d_bits_opcode = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_from_bus_named_fbus_widget_anonOut_d_bits_param = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_from_bus_named_fbus_widget_anonOut_d_bits_size = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] coupler_from_bus_named_fbus_widget_anonOut_d_bits_source = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_anonOut_d_bits_sink = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_anonOut_d_bits_denied = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_from_bus_named_fbus_widget_anonOut_d_bits_data = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_anonOut_d_bits_corrupt = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_anonIn_a_ready = coupler_from_bus_named_fbus_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_valid = coupler_from_bus_named_fbus_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_opcode = coupler_from_bus_named_fbus_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_param = coupler_from_bus_named_fbus_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_size = coupler_from_bus_named_fbus_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_source = coupler_from_bus_named_fbus_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_address = coupler_from_bus_named_fbus_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_mask = coupler_from_bus_named_fbus_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_data = coupler_from_bus_named_fbus_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_corrupt = coupler_from_bus_named_fbus_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_out_d_ready = coupler_from_bus_named_fbus_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_anonIn_d_valid = coupler_from_bus_named_fbus_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_opcode = coupler_from_bus_named_fbus_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_param = coupler_from_bus_named_fbus_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_size = coupler_from_bus_named_fbus_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_source = coupler_from_bus_named_fbus_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_sink = coupler_from_bus_named_fbus_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_denied = coupler_from_bus_named_fbus_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_data = coupler_from_bus_named_fbus_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_corrupt = coupler_from_bus_named_fbus_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_ready = coupler_from_bus_named_fbus_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_anonOut_a_valid = coupler_from_bus_named_fbus_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_opcode = coupler_from_bus_named_fbus_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_param = coupler_from_bus_named_fbus_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_size = coupler_from_bus_named_fbus_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_source = coupler_from_bus_named_fbus_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_address = coupler_from_bus_named_fbus_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_mask = coupler_from_bus_named_fbus_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_data = coupler_from_bus_named_fbus_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_corrupt = coupler_from_bus_named_fbus_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonOut_d_ready = coupler_from_bus_named_fbus_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_valid = coupler_from_bus_named_fbus_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_opcode = coupler_from_bus_named_fbus_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_param = coupler_from_bus_named_fbus_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_size = coupler_from_bus_named_fbus_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_source = coupler_from_bus_named_fbus_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_sink = coupler_from_bus_named_fbus_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_denied = coupler_from_bus_named_fbus_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_data = coupler_from_bus_named_fbus_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_corrupt = coupler_from_bus_named_fbus_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_bus_xingIn_a_ready = coupler_from_bus_named_fbus_bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_valid = coupler_from_bus_named_fbus_bus_xingOut_a_valid; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_opcode = coupler_from_bus_named_fbus_bus_xingOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_param = coupler_from_bus_named_fbus_bus_xingOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_size = coupler_from_bus_named_fbus_bus_xingOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_source = coupler_from_bus_named_fbus_bus_xingOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_address = coupler_from_bus_named_fbus_bus_xingOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_mask = coupler_from_bus_named_fbus_bus_xingOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_data = coupler_from_bus_named_fbus_bus_xingOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_corrupt = coupler_from_bus_named_fbus_bus_xingOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_ready = coupler_from_bus_named_fbus_bus_xingOut_d_ready; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_bus_xingIn_d_valid = coupler_from_bus_named_fbus_bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_opcode = coupler_from_bus_named_fbus_bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_param = coupler_from_bus_named_fbus_bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_size = coupler_from_bus_named_fbus_bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_source = coupler_from_bus_named_fbus_bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_sink = coupler_from_bus_named_fbus_bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_denied = coupler_from_bus_named_fbus_bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_data = coupler_from_bus_named_fbus_bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_corrupt = coupler_from_bus_named_fbus_bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_auto_bus_xing_in_a_ready = coupler_from_bus_named_fbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_from_bus_named_fbus_bus_xingOut_a_valid = coupler_from_bus_named_fbus_bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_opcode = coupler_from_bus_named_fbus_bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_param = coupler_from_bus_named_fbus_bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_size = coupler_from_bus_named_fbus_bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_source = coupler_from_bus_named_fbus_bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_address = coupler_from_bus_named_fbus_bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_mask = coupler_from_bus_named_fbus_bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_data = coupler_from_bus_named_fbus_bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_corrupt = coupler_from_bus_named_fbus_bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingOut_d_ready = coupler_from_bus_named_fbus_bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_valid = coupler_from_bus_named_fbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_opcode = coupler_from_bus_named_fbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_param = coupler_from_bus_named_fbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_size = coupler_from_bus_named_fbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_source = coupler_from_bus_named_fbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_sink = coupler_from_bus_named_fbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_denied = coupler_from_bus_named_fbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_data = coupler_from_bus_named_fbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_corrupt = coupler_from_bus_named_fbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_coh_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_a_valid = coupler_to_bus_named_coh_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_d_ready = coupler_to_bus_named_coh_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_a_ready = coupler_to_bus_named_coh_auto_widget_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_size; // @[ClockDomain.scala:14:9]
wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_d_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_d_ready; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_d_valid = coupler_to_bus_named_coh_auto_widget_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_a_ready = coupler_to_bus_named_coh_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_a_valid = coupler_to_bus_named_coh_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_d_ready = coupler_to_bus_named_coh_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_valid = coupler_to_bus_named_coh_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_a_ready = coupler_to_bus_named_coh_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_valid = coupler_to_bus_named_coh_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_d_ready = coupler_to_bus_named_coh_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_d_valid = coupler_to_bus_named_coh_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_anonIn_a_ready = coupler_to_bus_named_coh_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_valid = coupler_to_bus_named_coh_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_coh_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_coh_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_coh_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_coh_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_coh_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_coh_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_coh_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_coh_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_d_ready = coupler_to_bus_named_coh_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_anonIn_d_valid = coupler_to_bus_named_coh_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_opcode = coupler_to_bus_named_coh_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_param = coupler_to_bus_named_coh_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_size = coupler_to_bus_named_coh_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_source = coupler_to_bus_named_coh_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_sink = coupler_to_bus_named_coh_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_denied = coupler_to_bus_named_coh_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_data = coupler_to_bus_named_coh_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_coh_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_auto_anon_in_a_ready = coupler_to_bus_named_coh_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_anonOut_a_valid = coupler_to_bus_named_coh_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_opcode = coupler_to_bus_named_coh_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_param = coupler_to_bus_named_coh_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_size = coupler_to_bus_named_coh_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_source = coupler_to_bus_named_coh_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_address = coupler_to_bus_named_coh_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_mask = coupler_to_bus_named_coh_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_data = coupler_to_bus_named_coh_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_coh_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_d_ready = coupler_to_bus_named_coh_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_valid = coupler_to_bus_named_coh_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_coh_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_coh_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_coh_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_coh_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_coh_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_coh_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_coh_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_coh_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_from_rockettile_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_a_ready_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_ready; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_tlMasterClockXingIn_a_valid = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_opcode = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_param = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_size = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_size; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_tlMasterClockXingIn_a_bits_source = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_address = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_mask = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_data = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_tlMasterClockXingIn_a_bits_corrupt = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_tlMasterClockXingIn_d_ready = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_valid_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_opcode_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_param_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_size_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_size; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_source_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_source; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_sink_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_sink; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_denied_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_data_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_corrupt_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_tlOut_a_ready = coupler_from_rockettile_auto_tl_out_a_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlOut_a_valid; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_valid = coupler_from_rockettile_auto_tl_out_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_opcode = coupler_from_rockettile_auto_tl_out_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_tlOut_a_bits_param; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_param = coupler_from_rockettile_auto_tl_out_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_tlOut_a_bits_size; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_size = coupler_from_rockettile_auto_tl_out_a_bits_size; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_tlOut_a_bits_source; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_source = coupler_from_rockettile_auto_tl_out_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_tlOut_a_bits_address; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_address = coupler_from_rockettile_auto_tl_out_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] coupler_from_rockettile_tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_mask = coupler_from_rockettile_auto_tl_out_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] coupler_from_rockettile_tlOut_a_bits_data; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_data = coupler_from_rockettile_auto_tl_out_a_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_corrupt = coupler_from_rockettile_auto_tl_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_tlOut_d_ready; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_d_ready = coupler_from_rockettile_auto_tl_out_d_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_tlOut_d_valid = coupler_from_rockettile_auto_tl_out_d_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_tlOut_d_bits_opcode = coupler_from_rockettile_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_tlOut_d_bits_param = coupler_from_rockettile_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_tlOut_d_bits_size = coupler_from_rockettile_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlOut_d_bits_source = coupler_from_rockettile_auto_tl_out_d_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_tlOut_d_bits_sink = coupler_from_rockettile_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlOut_d_bits_denied = coupler_from_rockettile_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_rockettile_tlOut_d_bits_data = coupler_from_rockettile_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlOut_d_bits_corrupt = coupler_from_rockettile_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlIn_a_ready = coupler_from_rockettile_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlIn_a_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_a_valid = coupler_from_rockettile_tlOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_tlIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_a_bits_opcode = coupler_from_rockettile_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_tlIn_a_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_a_bits_param = coupler_from_rockettile_tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_tlIn_a_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_a_bits_size = coupler_from_rockettile_tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlIn_a_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_a_bits_source = coupler_from_rockettile_tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_rockettile_tlIn_a_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_a_bits_address = coupler_from_rockettile_tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] coupler_from_rockettile_tlIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_a_bits_mask = coupler_from_rockettile_tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_rockettile_tlIn_a_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_a_bits_data = coupler_from_rockettile_tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_a_bits_corrupt = coupler_from_rockettile_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlIn_d_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_d_ready = coupler_from_rockettile_tlOut_d_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlIn_d_valid = coupler_from_rockettile_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_tlIn_d_bits_opcode = coupler_from_rockettile_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_tlIn_d_bits_param = coupler_from_rockettile_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_tlIn_d_bits_size = coupler_from_rockettile_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlIn_d_bits_source = coupler_from_rockettile_tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_tlIn_d_bits_sink = coupler_from_rockettile_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlIn_d_bits_denied = coupler_from_rockettile_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_tlIn_d_bits_data = coupler_from_rockettile_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlIn_d_bits_corrupt = coupler_from_rockettile_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_a_ready = coupler_from_rockettile_tlIn_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_valid = coupler_from_rockettile_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_opcode = coupler_from_rockettile_tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_param = coupler_from_rockettile_tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_size = coupler_from_rockettile_tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_source = coupler_from_rockettile_tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_address = coupler_from_rockettile_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_mask = coupler_from_rockettile_tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_data = coupler_from_rockettile_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_corrupt = coupler_from_rockettile_tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_d_ready = coupler_from_rockettile_tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_d_valid = coupler_from_rockettile_tlIn_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferOut_d_bits_opcode = coupler_from_rockettile_tlIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_no_bufferOut_d_bits_param = coupler_from_rockettile_tlIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_no_bufferOut_d_bits_size = coupler_from_rockettile_tlIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_d_bits_source = coupler_from_rockettile_tlIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferOut_d_bits_sink = coupler_from_rockettile_tlIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_d_bits_denied = coupler_from_rockettile_tlIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_no_bufferOut_d_bits_data = coupler_from_rockettile_tlIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_d_bits_corrupt = coupler_from_rockettile_tlIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_a_ready = coupler_from_rockettile_no_bufferOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_a_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_valid = coupler_from_rockettile_no_bufferOut_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_opcode = coupler_from_rockettile_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferIn_a_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_param = coupler_from_rockettile_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_no_bufferIn_a_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_size = coupler_from_rockettile_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_a_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_source = coupler_from_rockettile_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_no_bufferIn_a_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_address = coupler_from_rockettile_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_no_bufferIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_mask = coupler_from_rockettile_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_no_bufferIn_a_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_data = coupler_from_rockettile_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_corrupt = coupler_from_rockettile_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_d_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_d_ready = coupler_from_rockettile_no_bufferOut_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_d_valid = coupler_from_rockettile_no_bufferOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferIn_d_bits_opcode = coupler_from_rockettile_no_bufferOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_no_bufferIn_d_bits_param = coupler_from_rockettile_no_bufferOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_no_bufferIn_d_bits_size = coupler_from_rockettile_no_bufferOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_d_bits_source = coupler_from_rockettile_no_bufferOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferIn_d_bits_sink = coupler_from_rockettile_no_bufferOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_d_bits_denied = coupler_from_rockettile_no_bufferOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_no_bufferIn_d_bits_data = coupler_from_rockettile_no_bufferOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_d_bits_corrupt = coupler_from_rockettile_no_bufferOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_a_ready = coupler_from_rockettile_no_bufferIn_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_valid = coupler_from_rockettile_no_bufferIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_opcode = coupler_from_rockettile_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_param = coupler_from_rockettile_no_bufferIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_size = coupler_from_rockettile_no_bufferIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_source = coupler_from_rockettile_no_bufferIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_address = coupler_from_rockettile_no_bufferIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_mask = coupler_from_rockettile_no_bufferIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_data = coupler_from_rockettile_no_bufferIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_corrupt = coupler_from_rockettile_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_d_ready = coupler_from_rockettile_no_bufferIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_d_valid = coupler_from_rockettile_no_bufferIn_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_opcode = coupler_from_rockettile_no_bufferIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_param = coupler_from_rockettile_no_bufferIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_size = coupler_from_rockettile_no_bufferIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_d_bits_source = coupler_from_rockettile_no_bufferIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_sink = coupler_from_rockettile_no_bufferIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_d_bits_denied = coupler_from_rockettile_no_bufferIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_data = coupler_from_rockettile_no_bufferIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_d_bits_corrupt = coupler_from_rockettile_no_bufferIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_a_ready = coupler_from_rockettile_tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_valid = coupler_from_rockettile_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_opcode = coupler_from_rockettile_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_param = coupler_from_rockettile_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_size = coupler_from_rockettile_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_source = coupler_from_rockettile_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_address = coupler_from_rockettile_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_mask = coupler_from_rockettile_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_data = coupler_from_rockettile_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_corrupt = coupler_from_rockettile_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_d_ready = coupler_from_rockettile_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_valid = coupler_from_rockettile_tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_opcode = coupler_from_rockettile_tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_param = coupler_from_rockettile_tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_size = coupler_from_rockettile_tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_source = coupler_from_rockettile_tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_sink = coupler_from_rockettile_tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_denied = coupler_from_rockettile_tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_data = coupler_from_rockettile_tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_corrupt = coupler_from_rockettile_tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_a_ready = coupler_from_rockettile_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_valid = coupler_from_rockettile_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_opcode = coupler_from_rockettile_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_param = coupler_from_rockettile_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_size = coupler_from_rockettile_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_source = coupler_from_rockettile_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_address = coupler_from_rockettile_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_mask = coupler_from_rockettile_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_data = coupler_from_rockettile_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_corrupt = coupler_from_rockettile_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_d_ready = coupler_from_rockettile_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_valid = coupler_from_rockettile_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_opcode = coupler_from_rockettile_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_param = coupler_from_rockettile_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_size = coupler_from_rockettile_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_source = coupler_from_rockettile_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_sink = coupler_from_rockettile_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_denied = coupler_from_rockettile_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_data = coupler_from_rockettile_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_corrupt = coupler_from_rockettile_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35]
wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35]
wire fixer__T_31 = fixer_a_first_1 & fixer__a_first_T_1; // @[Decoupled.scala:51:35]
wire fixer__T_33 = fixer_d_first_1 & fixer__T_32; // @[Decoupled.scala:51:35]
always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31]
if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31]
fixer_a_first_counter <= 9'h0; // @[Edges.scala:229:27]
fixer_d_first_counter <= 9'h0; // @[Edges.scala:229:27]
fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_SourceIdFIFOed <= 17'h0; // @[FIFOFixer.scala:115:35]
fixer_a_first_counter_1 <= 9'h0; // @[Edges.scala:229:27]
fixer_d_first_counter_1 <= 9'h0; // @[Edges.scala:229:27]
fixer_flight_1_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_SourceIdFIFOed_1 <= 2'h0; // @[FIFOFixer.scala:115:35]
end
else begin // @[LazyModuleImp.scala:155:31]
if (fixer__a_first_T) // @[Decoupled.scala:51:35]
fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21]
if (fixer__d_first_T) // @[Decoupled.scala:51:35]
fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21]
fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h0 ? fixer__flight_T : fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h1 ? fixer__flight_T : fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h2 ? fixer__flight_T : fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h3 ? fixer__flight_T : fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h4 ? fixer__flight_T : fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h5 ? fixer__flight_T : fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h6 ? fixer__flight_T : fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h7 ? fixer__flight_T : fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h8 ? fixer__flight_T : fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h9 ? fixer__flight_T : fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_10 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hA ? fixer__flight_T : fixer_flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_11 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hB ? fixer__flight_T : fixer_flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_12 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hC ? fixer__flight_T : fixer_flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_13 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hD ? fixer__flight_T : fixer_flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_14 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hE ? fixer__flight_T : fixer_flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_15 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hF ? fixer__flight_T : fixer_flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_16 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h10) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h10 ? fixer__flight_T : fixer_flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40]
if (fixer__a_first_T_1) // @[Decoupled.scala:51:35]
fixer_a_first_counter_1 <= fixer__a_first_counter_T_1; // @[Edges.scala:229:27, :236:21]
if (fixer__d_first_T_2) // @[Decoupled.scala:51:35]
fixer_d_first_counter_1 <= fixer__d_first_counter_T_1; // @[Edges.scala:229:27, :236:21]
fixer_flight_1_0 <= ~(fixer__T_33 & ~fixer_x1_anonIn_d_bits_source) & (fixer__T_31 & ~fixer_x1_anonIn_a_bits_source ? fixer__flight_T_1 : fixer_flight_1_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_1 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source ? fixer__flight_T_1 : fixer_flight_1_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_SourceIdFIFOed_1 <= fixer__SourceIdFIFOed_T_1; // @[FIFOFixer.scala:115:35, :126:40]
end
always @(posedge)
FixedClockBroadcast_4 fixedClockNode ( // @[ClockGroup.scala:115:114]
.auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9]
.auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9]
.auto_anon_out_3_clock (auto_fixedClockNode_anon_out_2_clock_0),
.auto_anon_out_3_reset (auto_fixedClockNode_anon_out_2_reset_0),
.auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock_0),
.auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset_0),
.auto_anon_out_1_clock (auto_fixedClockNode_anon_out_0_clock_0),
.auto_anon_out_1_reset (auto_fixedClockNode_anon_out_0_reset_0),
.auto_anon_out_0_clock (clockSinkNodeIn_clock),
.auto_anon_out_0_reset (clockSinkNodeIn_reset)
); // @[ClockGroup.scala:115:114]
TLXbar_sbus_i2_o2_a32d64s6k3z4u system_bus_xbar ( // @[SystemBus.scala:47:43]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_1_a_ready (fixer_auto_anon_out_1_a_ready),
.auto_anon_in_1_a_valid (fixer_auto_anon_out_1_a_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_opcode (fixer_auto_anon_out_1_a_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_param (fixer_auto_anon_out_1_a_bits_param), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_size (fixer_auto_anon_out_1_a_bits_size), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_source (fixer_auto_anon_out_1_a_bits_source), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_address (fixer_auto_anon_out_1_a_bits_address), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_mask (fixer_auto_anon_out_1_a_bits_mask), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_data (fixer_auto_anon_out_1_a_bits_data), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_corrupt (fixer_auto_anon_out_1_a_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_d_ready (fixer_auto_anon_out_1_d_ready), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_d_valid (fixer_auto_anon_out_1_d_valid),
.auto_anon_in_1_d_bits_opcode (fixer_auto_anon_out_1_d_bits_opcode),
.auto_anon_in_1_d_bits_param (fixer_auto_anon_out_1_d_bits_param),
.auto_anon_in_1_d_bits_size (fixer_auto_anon_out_1_d_bits_size),
.auto_anon_in_1_d_bits_source (fixer_auto_anon_out_1_d_bits_source),
.auto_anon_in_1_d_bits_sink (fixer_auto_anon_out_1_d_bits_sink),
.auto_anon_in_1_d_bits_denied (fixer_auto_anon_out_1_d_bits_denied),
.auto_anon_in_1_d_bits_data (fixer_auto_anon_out_1_d_bits_data),
.auto_anon_in_1_d_bits_corrupt (fixer_auto_anon_out_1_d_bits_corrupt),
.auto_anon_in_0_a_ready (fixer_auto_anon_out_0_a_ready),
.auto_anon_in_0_a_valid (fixer_auto_anon_out_0_a_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_opcode (fixer_auto_anon_out_0_a_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_param (fixer_auto_anon_out_0_a_bits_param), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_size (fixer_auto_anon_out_0_a_bits_size), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_source (fixer_auto_anon_out_0_a_bits_source), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_address (fixer_auto_anon_out_0_a_bits_address), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_mask (fixer_auto_anon_out_0_a_bits_mask), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_data (fixer_auto_anon_out_0_a_bits_data), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_corrupt (fixer_auto_anon_out_0_a_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_d_ready (fixer_auto_anon_out_0_d_ready), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_d_valid (fixer_auto_anon_out_0_d_valid),
.auto_anon_in_0_d_bits_opcode (fixer_auto_anon_out_0_d_bits_opcode),
.auto_anon_in_0_d_bits_param (fixer_auto_anon_out_0_d_bits_param),
.auto_anon_in_0_d_bits_size (fixer_auto_anon_out_0_d_bits_size),
.auto_anon_in_0_d_bits_source (fixer_auto_anon_out_0_d_bits_source),
.auto_anon_in_0_d_bits_sink (fixer_auto_anon_out_0_d_bits_sink),
.auto_anon_in_0_d_bits_denied (fixer_auto_anon_out_0_d_bits_denied),
.auto_anon_in_0_d_bits_data (fixer_auto_anon_out_0_d_bits_data),
.auto_anon_in_0_d_bits_corrupt (fixer_auto_anon_out_0_d_bits_corrupt),
.auto_anon_out_1_a_ready (coupler_to_bus_named_coh_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_a_valid (coupler_to_bus_named_coh_auto_widget_anon_in_a_valid),
.auto_anon_out_1_a_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_opcode),
.auto_anon_out_1_a_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_param),
.auto_anon_out_1_a_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_size),
.auto_anon_out_1_a_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_source),
.auto_anon_out_1_a_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_address),
.auto_anon_out_1_a_bits_mask (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_mask),
.auto_anon_out_1_a_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_data),
.auto_anon_out_1_a_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_corrupt),
.auto_anon_out_1_d_ready (coupler_to_bus_named_coh_auto_widget_anon_in_d_ready),
.auto_anon_out_1_d_valid (coupler_to_bus_named_coh_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_denied (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_corrupt), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_0_a_ready (coupler_to_bus_named_cbus_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_0_a_valid (coupler_to_bus_named_cbus_auto_widget_anon_in_a_valid),
.auto_anon_out_0_a_bits_opcode (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_opcode),
.auto_anon_out_0_a_bits_param (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_param),
.auto_anon_out_0_a_bits_size (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_size),
.auto_anon_out_0_a_bits_source (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_source),
.auto_anon_out_0_a_bits_address (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_address),
.auto_anon_out_0_a_bits_mask (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_mask),
.auto_anon_out_0_a_bits_data (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_data),
.auto_anon_out_0_a_bits_corrupt (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_corrupt),
.auto_anon_out_0_d_ready (coupler_to_bus_named_cbus_auto_widget_anon_in_d_ready),
.auto_anon_out_0_d_valid (coupler_to_bus_named_cbus_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_0_d_bits_opcode (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_0_d_bits_param (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_0_d_bits_size (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_0_d_bits_source (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_0_d_bits_sink (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_0_d_bits_denied (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_0_d_bits_data (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_0_d_bits_corrupt (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_corrupt) // @[LazyModuleImp.scala:138:7]
); // @[SystemBus.scala:47:43]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_a_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_denied = auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_valid = auto_coupler_to_bus_named_coh_widget_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_d_ready = auto_coupler_to_bus_named_coh_widget_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready = auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid = auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid = auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready = auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_2_clock = auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_2_reset = auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_1_clock = auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_1_reset = auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_0_clock = auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_0_reset = auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9]
assign auto_sbus_clock_groups_out_member_coh_0_clock = auto_sbus_clock_groups_out_member_coh_0_clock_0; // @[ClockDomain.scala:14:9]
assign auto_sbus_clock_groups_out_member_coh_0_reset = auto_sbus_clock_groups_out_member_coh_0_reset_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_51 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_51
connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc
connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc
connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig
connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp
connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign
connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module RoundRawFNToRecFN_e8_s24_51( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_51 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PMPChecker_s3_11 :
input clock : Clock
input reset : Reset
output io : { flip prv : UInt<2>, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip addr : UInt<32>, flip size : UInt<2>, r : UInt<1>, w : UInt<1>, x : UInt<1>}
node default = gt(io.prv, UInt<1>(0h1))
wire _pmp0_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect _pmp0_WIRE.mask, UInt<32>(0h0)
connect _pmp0_WIRE.addr, UInt<30>(0h0)
connect _pmp0_WIRE.cfg.r, UInt<1>(0h0)
connect _pmp0_WIRE.cfg.w, UInt<1>(0h0)
connect _pmp0_WIRE.cfg.x, UInt<1>(0h0)
connect _pmp0_WIRE.cfg.a, UInt<2>(0h0)
connect _pmp0_WIRE.cfg.res, UInt<2>(0h0)
connect _pmp0_WIRE.cfg.l, UInt<1>(0h0)
wire pmp0 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp0, _pmp0_WIRE
connect pmp0.cfg.r, default
connect pmp0.cfg.w, default
connect pmp0.cfg.x, default
node _res_hit_T = bits(io.pmp[7].cfg.a, 1, 1)
node _res_hit_lsbMask_T = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_1 = bits(_res_hit_lsbMask_T, 2, 0)
node _res_hit_lsbMask_T_2 = not(_res_hit_lsbMask_T_1)
node res_hit_lsbMask = or(io.pmp[7].mask, _res_hit_lsbMask_T_2)
node _res_hit_msbMatch_T = shr(io.addr, 3)
node _res_hit_msbMatch_T_1 = shl(io.pmp[7].addr, 2)
node _res_hit_msbMatch_T_2 = not(_res_hit_msbMatch_T_1)
node _res_hit_msbMatch_T_3 = or(_res_hit_msbMatch_T_2, UInt<2>(0h3))
node _res_hit_msbMatch_T_4 = not(_res_hit_msbMatch_T_3)
node _res_hit_msbMatch_T_5 = shr(_res_hit_msbMatch_T_4, 3)
node _res_hit_msbMatch_T_6 = shr(io.pmp[7].mask, 3)
node _res_hit_msbMatch_T_7 = xor(_res_hit_msbMatch_T, _res_hit_msbMatch_T_5)
node _res_hit_msbMatch_T_8 = not(_res_hit_msbMatch_T_6)
node _res_hit_msbMatch_T_9 = and(_res_hit_msbMatch_T_7, _res_hit_msbMatch_T_8)
node res_hit_msbMatch = eq(_res_hit_msbMatch_T_9, UInt<1>(0h0))
node _res_hit_lsbMatch_T = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_1 = shl(io.pmp[7].addr, 2)
node _res_hit_lsbMatch_T_2 = not(_res_hit_lsbMatch_T_1)
node _res_hit_lsbMatch_T_3 = or(_res_hit_lsbMatch_T_2, UInt<2>(0h3))
node _res_hit_lsbMatch_T_4 = not(_res_hit_lsbMatch_T_3)
node _res_hit_lsbMatch_T_5 = bits(_res_hit_lsbMatch_T_4, 2, 0)
node _res_hit_lsbMatch_T_6 = bits(res_hit_lsbMask, 2, 0)
node _res_hit_lsbMatch_T_7 = xor(_res_hit_lsbMatch_T, _res_hit_lsbMatch_T_5)
node _res_hit_lsbMatch_T_8 = not(_res_hit_lsbMatch_T_6)
node _res_hit_lsbMatch_T_9 = and(_res_hit_lsbMatch_T_7, _res_hit_lsbMatch_T_8)
node res_hit_lsbMatch = eq(_res_hit_lsbMatch_T_9, UInt<1>(0h0))
node _res_hit_T_1 = and(res_hit_msbMatch, res_hit_lsbMatch)
node _res_hit_T_2 = bits(io.pmp[7].cfg.a, 0, 0)
node _res_hit_T_3 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_4 = bits(_res_hit_T_3, 2, 0)
node _res_hit_T_5 = not(_res_hit_T_4)
node _res_hit_msbsLess_T = shr(io.addr, 3)
node _res_hit_msbsLess_T_1 = shl(io.pmp[6].addr, 2)
node _res_hit_msbsLess_T_2 = not(_res_hit_msbsLess_T_1)
node _res_hit_msbsLess_T_3 = or(_res_hit_msbsLess_T_2, UInt<2>(0h3))
node _res_hit_msbsLess_T_4 = not(_res_hit_msbsLess_T_3)
node _res_hit_msbsLess_T_5 = shr(_res_hit_msbsLess_T_4, 3)
node res_hit_msbsLess = lt(_res_hit_msbsLess_T, _res_hit_msbsLess_T_5)
node _res_hit_msbsEqual_T = shr(io.addr, 3)
node _res_hit_msbsEqual_T_1 = shl(io.pmp[6].addr, 2)
node _res_hit_msbsEqual_T_2 = not(_res_hit_msbsEqual_T_1)
node _res_hit_msbsEqual_T_3 = or(_res_hit_msbsEqual_T_2, UInt<2>(0h3))
node _res_hit_msbsEqual_T_4 = not(_res_hit_msbsEqual_T_3)
node _res_hit_msbsEqual_T_5 = shr(_res_hit_msbsEqual_T_4, 3)
node _res_hit_msbsEqual_T_6 = xor(_res_hit_msbsEqual_T, _res_hit_msbsEqual_T_5)
node res_hit_msbsEqual = eq(_res_hit_msbsEqual_T_6, UInt<1>(0h0))
node _res_hit_lsbsLess_T = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_1 = or(_res_hit_lsbsLess_T, _res_hit_T_5)
node _res_hit_lsbsLess_T_2 = shl(io.pmp[6].addr, 2)
node _res_hit_lsbsLess_T_3 = not(_res_hit_lsbsLess_T_2)
node _res_hit_lsbsLess_T_4 = or(_res_hit_lsbsLess_T_3, UInt<2>(0h3))
node _res_hit_lsbsLess_T_5 = not(_res_hit_lsbsLess_T_4)
node _res_hit_lsbsLess_T_6 = bits(_res_hit_lsbsLess_T_5, 2, 0)
node res_hit_lsbsLess = lt(_res_hit_lsbsLess_T_1, _res_hit_lsbsLess_T_6)
node _res_hit_T_6 = and(res_hit_msbsEqual, res_hit_lsbsLess)
node _res_hit_T_7 = or(res_hit_msbsLess, _res_hit_T_6)
node _res_hit_T_8 = eq(_res_hit_T_7, UInt<1>(0h0))
node _res_hit_msbsLess_T_6 = shr(io.addr, 3)
node _res_hit_msbsLess_T_7 = shl(io.pmp[7].addr, 2)
node _res_hit_msbsLess_T_8 = not(_res_hit_msbsLess_T_7)
node _res_hit_msbsLess_T_9 = or(_res_hit_msbsLess_T_8, UInt<2>(0h3))
node _res_hit_msbsLess_T_10 = not(_res_hit_msbsLess_T_9)
node _res_hit_msbsLess_T_11 = shr(_res_hit_msbsLess_T_10, 3)
node res_hit_msbsLess_1 = lt(_res_hit_msbsLess_T_6, _res_hit_msbsLess_T_11)
node _res_hit_msbsEqual_T_7 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_8 = shl(io.pmp[7].addr, 2)
node _res_hit_msbsEqual_T_9 = not(_res_hit_msbsEqual_T_8)
node _res_hit_msbsEqual_T_10 = or(_res_hit_msbsEqual_T_9, UInt<2>(0h3))
node _res_hit_msbsEqual_T_11 = not(_res_hit_msbsEqual_T_10)
node _res_hit_msbsEqual_T_12 = shr(_res_hit_msbsEqual_T_11, 3)
node _res_hit_msbsEqual_T_13 = xor(_res_hit_msbsEqual_T_7, _res_hit_msbsEqual_T_12)
node res_hit_msbsEqual_1 = eq(_res_hit_msbsEqual_T_13, UInt<1>(0h0))
node _res_hit_lsbsLess_T_7 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_8 = or(_res_hit_lsbsLess_T_7, UInt<1>(0h0))
node _res_hit_lsbsLess_T_9 = shl(io.pmp[7].addr, 2)
node _res_hit_lsbsLess_T_10 = not(_res_hit_lsbsLess_T_9)
node _res_hit_lsbsLess_T_11 = or(_res_hit_lsbsLess_T_10, UInt<2>(0h3))
node _res_hit_lsbsLess_T_12 = not(_res_hit_lsbsLess_T_11)
node _res_hit_lsbsLess_T_13 = bits(_res_hit_lsbsLess_T_12, 2, 0)
node res_hit_lsbsLess_1 = lt(_res_hit_lsbsLess_T_8, _res_hit_lsbsLess_T_13)
node _res_hit_T_9 = and(res_hit_msbsEqual_1, res_hit_lsbsLess_1)
node _res_hit_T_10 = or(res_hit_msbsLess_1, _res_hit_T_9)
node _res_hit_T_11 = and(_res_hit_T_8, _res_hit_T_10)
node _res_hit_T_12 = and(_res_hit_T_2, _res_hit_T_11)
node res_hit = mux(_res_hit_T, _res_hit_T_1, _res_hit_T_12)
node _res_ignore_T = eq(io.pmp[7].cfg.l, UInt<1>(0h0))
node res_ignore = and(default, _res_ignore_T)
node _res_aligned_lsbMask_T = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_1 = bits(_res_aligned_lsbMask_T, 2, 0)
node res_aligned_lsbMask = not(_res_aligned_lsbMask_T_1)
node _res_aligned_straddlesLowerBound_T = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_1 = shl(io.pmp[6].addr, 2)
node _res_aligned_straddlesLowerBound_T_2 = not(_res_aligned_straddlesLowerBound_T_1)
node _res_aligned_straddlesLowerBound_T_3 = or(_res_aligned_straddlesLowerBound_T_2, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_4 = not(_res_aligned_straddlesLowerBound_T_3)
node _res_aligned_straddlesLowerBound_T_5 = shr(_res_aligned_straddlesLowerBound_T_4, 3)
node _res_aligned_straddlesLowerBound_T_6 = xor(_res_aligned_straddlesLowerBound_T, _res_aligned_straddlesLowerBound_T_5)
node _res_aligned_straddlesLowerBound_T_7 = eq(_res_aligned_straddlesLowerBound_T_6, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_8 = shl(io.pmp[6].addr, 2)
node _res_aligned_straddlesLowerBound_T_9 = not(_res_aligned_straddlesLowerBound_T_8)
node _res_aligned_straddlesLowerBound_T_10 = or(_res_aligned_straddlesLowerBound_T_9, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_11 = not(_res_aligned_straddlesLowerBound_T_10)
node _res_aligned_straddlesLowerBound_T_12 = bits(_res_aligned_straddlesLowerBound_T_11, 2, 0)
node _res_aligned_straddlesLowerBound_T_13 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_14 = not(_res_aligned_straddlesLowerBound_T_13)
node _res_aligned_straddlesLowerBound_T_15 = and(_res_aligned_straddlesLowerBound_T_12, _res_aligned_straddlesLowerBound_T_14)
node _res_aligned_straddlesLowerBound_T_16 = neq(_res_aligned_straddlesLowerBound_T_15, UInt<1>(0h0))
node res_aligned_straddlesLowerBound = and(_res_aligned_straddlesLowerBound_T_7, _res_aligned_straddlesLowerBound_T_16)
node _res_aligned_straddlesUpperBound_T = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_1 = shl(io.pmp[7].addr, 2)
node _res_aligned_straddlesUpperBound_T_2 = not(_res_aligned_straddlesUpperBound_T_1)
node _res_aligned_straddlesUpperBound_T_3 = or(_res_aligned_straddlesUpperBound_T_2, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_4 = not(_res_aligned_straddlesUpperBound_T_3)
node _res_aligned_straddlesUpperBound_T_5 = shr(_res_aligned_straddlesUpperBound_T_4, 3)
node _res_aligned_straddlesUpperBound_T_6 = xor(_res_aligned_straddlesUpperBound_T, _res_aligned_straddlesUpperBound_T_5)
node _res_aligned_straddlesUpperBound_T_7 = eq(_res_aligned_straddlesUpperBound_T_6, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_8 = shl(io.pmp[7].addr, 2)
node _res_aligned_straddlesUpperBound_T_9 = not(_res_aligned_straddlesUpperBound_T_8)
node _res_aligned_straddlesUpperBound_T_10 = or(_res_aligned_straddlesUpperBound_T_9, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_11 = not(_res_aligned_straddlesUpperBound_T_10)
node _res_aligned_straddlesUpperBound_T_12 = bits(_res_aligned_straddlesUpperBound_T_11, 2, 0)
node _res_aligned_straddlesUpperBound_T_13 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_14 = or(_res_aligned_straddlesUpperBound_T_13, res_aligned_lsbMask)
node _res_aligned_straddlesUpperBound_T_15 = and(_res_aligned_straddlesUpperBound_T_12, _res_aligned_straddlesUpperBound_T_14)
node _res_aligned_straddlesUpperBound_T_16 = neq(_res_aligned_straddlesUpperBound_T_15, UInt<1>(0h0))
node res_aligned_straddlesUpperBound = and(_res_aligned_straddlesUpperBound_T_7, _res_aligned_straddlesUpperBound_T_16)
node _res_aligned_rangeAligned_T = or(res_aligned_straddlesLowerBound, res_aligned_straddlesUpperBound)
node res_aligned_rangeAligned = eq(_res_aligned_rangeAligned_T, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T = bits(io.pmp[7].mask, 2, 0)
node _res_aligned_pow2Aligned_T_1 = not(_res_aligned_pow2Aligned_T)
node _res_aligned_pow2Aligned_T_2 = and(res_aligned_lsbMask, _res_aligned_pow2Aligned_T_1)
node res_aligned_pow2Aligned = eq(_res_aligned_pow2Aligned_T_2, UInt<1>(0h0))
node _res_aligned_T = bits(io.pmp[7].cfg.a, 1, 1)
node res_aligned = mux(_res_aligned_T, res_aligned_pow2Aligned, res_aligned_rangeAligned)
node _res_T = eq(io.pmp[7].cfg.a, UInt<1>(0h0))
node _res_T_1 = eq(io.pmp[7].cfg.a, UInt<1>(0h1))
node _res_T_2 = eq(io.pmp[7].cfg.a, UInt<2>(0h2))
node _res_T_3 = eq(io.pmp[7].cfg.a, UInt<2>(0h3))
node _res_T_4 = eq(io.pmp[7].cfg.l, UInt<1>(0h1))
node res_hi = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_5 = cat(res_hi, io.pmp[7].cfg.r)
node _res_T_6 = eq(_res_T_5, UInt<1>(0h0))
node res_hi_1 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_7 = cat(res_hi_1, io.pmp[7].cfg.r)
node _res_T_8 = eq(_res_T_7, UInt<1>(0h1))
node res_hi_2 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_9 = cat(res_hi_2, io.pmp[7].cfg.r)
node _res_T_10 = eq(_res_T_9, UInt<2>(0h3))
node res_hi_3 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_11 = cat(res_hi_3, io.pmp[7].cfg.r)
node _res_T_12 = eq(_res_T_11, UInt<3>(0h4))
node res_hi_4 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_13 = cat(res_hi_4, io.pmp[7].cfg.r)
node _res_T_14 = eq(_res_T_13, UInt<3>(0h5))
node res_hi_5 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_15 = cat(res_hi_5, io.pmp[7].cfg.r)
node _res_T_16 = eq(_res_T_15, UInt<3>(0h7))
node _res_T_17 = eq(res_ignore, UInt<1>(0h0))
node _res_T_18 = and(_res_T_17, res_hit)
node _res_T_19 = and(_res_T_18, res_aligned)
node _res_T_20 = eq(io.pmp[7].cfg.a, UInt<1>(0h1))
node _res_T_21 = and(_res_T_19, _res_T_20)
node _res_T_22 = and(io.pmp[7].cfg.l, res_hit)
node _res_T_23 = and(_res_T_22, res_aligned)
node _res_T_24 = eq(io.pmp[7].cfg.a, UInt<1>(0h1))
node _res_T_25 = and(_res_T_23, _res_T_24)
node _res_T_26 = eq(res_ignore, UInt<1>(0h0))
node _res_T_27 = and(_res_T_26, res_hit)
node _res_T_28 = and(_res_T_27, res_aligned)
node _res_T_29 = eq(io.pmp[7].cfg.a, UInt<2>(0h2))
node _res_T_30 = and(_res_T_28, _res_T_29)
node _res_T_31 = and(io.pmp[7].cfg.l, res_hit)
node _res_T_32 = and(_res_T_31, res_aligned)
node _res_T_33 = eq(io.pmp[7].cfg.a, UInt<2>(0h2))
node _res_T_34 = and(_res_T_32, _res_T_33)
node _res_T_35 = eq(res_ignore, UInt<1>(0h0))
node _res_T_36 = and(_res_T_35, res_hit)
node _res_T_37 = and(_res_T_36, res_aligned)
node _res_T_38 = eq(io.pmp[7].cfg.a, UInt<2>(0h3))
node _res_T_39 = and(_res_T_37, _res_T_38)
node _res_T_40 = and(io.pmp[7].cfg.l, res_hit)
node _res_T_41 = and(_res_T_40, res_aligned)
node _res_T_42 = eq(io.pmp[7].cfg.a, UInt<2>(0h3))
node _res_T_43 = and(_res_T_41, _res_T_42)
wire res_cur : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur, io.pmp[7]
node _res_cur_cfg_r_T = or(io.pmp[7].cfg.r, res_ignore)
node _res_cur_cfg_r_T_1 = and(res_aligned, _res_cur_cfg_r_T)
connect res_cur.cfg.r, _res_cur_cfg_r_T_1
node _res_cur_cfg_w_T = or(io.pmp[7].cfg.w, res_ignore)
node _res_cur_cfg_w_T_1 = and(res_aligned, _res_cur_cfg_w_T)
connect res_cur.cfg.w, _res_cur_cfg_w_T_1
node _res_cur_cfg_x_T = or(io.pmp[7].cfg.x, res_ignore)
node _res_cur_cfg_x_T_1 = and(res_aligned, _res_cur_cfg_x_T)
connect res_cur.cfg.x, _res_cur_cfg_x_T_1
node _res_T_44 = mux(res_hit, res_cur, pmp0)
node _res_hit_T_13 = bits(io.pmp[6].cfg.a, 1, 1)
node _res_hit_lsbMask_T_3 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_4 = bits(_res_hit_lsbMask_T_3, 2, 0)
node _res_hit_lsbMask_T_5 = not(_res_hit_lsbMask_T_4)
node res_hit_lsbMask_1 = or(io.pmp[6].mask, _res_hit_lsbMask_T_5)
node _res_hit_msbMatch_T_10 = shr(io.addr, 3)
node _res_hit_msbMatch_T_11 = shl(io.pmp[6].addr, 2)
node _res_hit_msbMatch_T_12 = not(_res_hit_msbMatch_T_11)
node _res_hit_msbMatch_T_13 = or(_res_hit_msbMatch_T_12, UInt<2>(0h3))
node _res_hit_msbMatch_T_14 = not(_res_hit_msbMatch_T_13)
node _res_hit_msbMatch_T_15 = shr(_res_hit_msbMatch_T_14, 3)
node _res_hit_msbMatch_T_16 = shr(io.pmp[6].mask, 3)
node _res_hit_msbMatch_T_17 = xor(_res_hit_msbMatch_T_10, _res_hit_msbMatch_T_15)
node _res_hit_msbMatch_T_18 = not(_res_hit_msbMatch_T_16)
node _res_hit_msbMatch_T_19 = and(_res_hit_msbMatch_T_17, _res_hit_msbMatch_T_18)
node res_hit_msbMatch_1 = eq(_res_hit_msbMatch_T_19, UInt<1>(0h0))
node _res_hit_lsbMatch_T_10 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_11 = shl(io.pmp[6].addr, 2)
node _res_hit_lsbMatch_T_12 = not(_res_hit_lsbMatch_T_11)
node _res_hit_lsbMatch_T_13 = or(_res_hit_lsbMatch_T_12, UInt<2>(0h3))
node _res_hit_lsbMatch_T_14 = not(_res_hit_lsbMatch_T_13)
node _res_hit_lsbMatch_T_15 = bits(_res_hit_lsbMatch_T_14, 2, 0)
node _res_hit_lsbMatch_T_16 = bits(res_hit_lsbMask_1, 2, 0)
node _res_hit_lsbMatch_T_17 = xor(_res_hit_lsbMatch_T_10, _res_hit_lsbMatch_T_15)
node _res_hit_lsbMatch_T_18 = not(_res_hit_lsbMatch_T_16)
node _res_hit_lsbMatch_T_19 = and(_res_hit_lsbMatch_T_17, _res_hit_lsbMatch_T_18)
node res_hit_lsbMatch_1 = eq(_res_hit_lsbMatch_T_19, UInt<1>(0h0))
node _res_hit_T_14 = and(res_hit_msbMatch_1, res_hit_lsbMatch_1)
node _res_hit_T_15 = bits(io.pmp[6].cfg.a, 0, 0)
node _res_hit_T_16 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_17 = bits(_res_hit_T_16, 2, 0)
node _res_hit_T_18 = not(_res_hit_T_17)
node _res_hit_msbsLess_T_12 = shr(io.addr, 3)
node _res_hit_msbsLess_T_13 = shl(io.pmp[5].addr, 2)
node _res_hit_msbsLess_T_14 = not(_res_hit_msbsLess_T_13)
node _res_hit_msbsLess_T_15 = or(_res_hit_msbsLess_T_14, UInt<2>(0h3))
node _res_hit_msbsLess_T_16 = not(_res_hit_msbsLess_T_15)
node _res_hit_msbsLess_T_17 = shr(_res_hit_msbsLess_T_16, 3)
node res_hit_msbsLess_2 = lt(_res_hit_msbsLess_T_12, _res_hit_msbsLess_T_17)
node _res_hit_msbsEqual_T_14 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_15 = shl(io.pmp[5].addr, 2)
node _res_hit_msbsEqual_T_16 = not(_res_hit_msbsEqual_T_15)
node _res_hit_msbsEqual_T_17 = or(_res_hit_msbsEqual_T_16, UInt<2>(0h3))
node _res_hit_msbsEqual_T_18 = not(_res_hit_msbsEqual_T_17)
node _res_hit_msbsEqual_T_19 = shr(_res_hit_msbsEqual_T_18, 3)
node _res_hit_msbsEqual_T_20 = xor(_res_hit_msbsEqual_T_14, _res_hit_msbsEqual_T_19)
node res_hit_msbsEqual_2 = eq(_res_hit_msbsEqual_T_20, UInt<1>(0h0))
node _res_hit_lsbsLess_T_14 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_15 = or(_res_hit_lsbsLess_T_14, _res_hit_T_18)
node _res_hit_lsbsLess_T_16 = shl(io.pmp[5].addr, 2)
node _res_hit_lsbsLess_T_17 = not(_res_hit_lsbsLess_T_16)
node _res_hit_lsbsLess_T_18 = or(_res_hit_lsbsLess_T_17, UInt<2>(0h3))
node _res_hit_lsbsLess_T_19 = not(_res_hit_lsbsLess_T_18)
node _res_hit_lsbsLess_T_20 = bits(_res_hit_lsbsLess_T_19, 2, 0)
node res_hit_lsbsLess_2 = lt(_res_hit_lsbsLess_T_15, _res_hit_lsbsLess_T_20)
node _res_hit_T_19 = and(res_hit_msbsEqual_2, res_hit_lsbsLess_2)
node _res_hit_T_20 = or(res_hit_msbsLess_2, _res_hit_T_19)
node _res_hit_T_21 = eq(_res_hit_T_20, UInt<1>(0h0))
node _res_hit_msbsLess_T_18 = shr(io.addr, 3)
node _res_hit_msbsLess_T_19 = shl(io.pmp[6].addr, 2)
node _res_hit_msbsLess_T_20 = not(_res_hit_msbsLess_T_19)
node _res_hit_msbsLess_T_21 = or(_res_hit_msbsLess_T_20, UInt<2>(0h3))
node _res_hit_msbsLess_T_22 = not(_res_hit_msbsLess_T_21)
node _res_hit_msbsLess_T_23 = shr(_res_hit_msbsLess_T_22, 3)
node res_hit_msbsLess_3 = lt(_res_hit_msbsLess_T_18, _res_hit_msbsLess_T_23)
node _res_hit_msbsEqual_T_21 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_22 = shl(io.pmp[6].addr, 2)
node _res_hit_msbsEqual_T_23 = not(_res_hit_msbsEqual_T_22)
node _res_hit_msbsEqual_T_24 = or(_res_hit_msbsEqual_T_23, UInt<2>(0h3))
node _res_hit_msbsEqual_T_25 = not(_res_hit_msbsEqual_T_24)
node _res_hit_msbsEqual_T_26 = shr(_res_hit_msbsEqual_T_25, 3)
node _res_hit_msbsEqual_T_27 = xor(_res_hit_msbsEqual_T_21, _res_hit_msbsEqual_T_26)
node res_hit_msbsEqual_3 = eq(_res_hit_msbsEqual_T_27, UInt<1>(0h0))
node _res_hit_lsbsLess_T_21 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_22 = or(_res_hit_lsbsLess_T_21, UInt<1>(0h0))
node _res_hit_lsbsLess_T_23 = shl(io.pmp[6].addr, 2)
node _res_hit_lsbsLess_T_24 = not(_res_hit_lsbsLess_T_23)
node _res_hit_lsbsLess_T_25 = or(_res_hit_lsbsLess_T_24, UInt<2>(0h3))
node _res_hit_lsbsLess_T_26 = not(_res_hit_lsbsLess_T_25)
node _res_hit_lsbsLess_T_27 = bits(_res_hit_lsbsLess_T_26, 2, 0)
node res_hit_lsbsLess_3 = lt(_res_hit_lsbsLess_T_22, _res_hit_lsbsLess_T_27)
node _res_hit_T_22 = and(res_hit_msbsEqual_3, res_hit_lsbsLess_3)
node _res_hit_T_23 = or(res_hit_msbsLess_3, _res_hit_T_22)
node _res_hit_T_24 = and(_res_hit_T_21, _res_hit_T_23)
node _res_hit_T_25 = and(_res_hit_T_15, _res_hit_T_24)
node res_hit_1 = mux(_res_hit_T_13, _res_hit_T_14, _res_hit_T_25)
node _res_ignore_T_1 = eq(io.pmp[6].cfg.l, UInt<1>(0h0))
node res_ignore_1 = and(default, _res_ignore_T_1)
node _res_aligned_lsbMask_T_2 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_3 = bits(_res_aligned_lsbMask_T_2, 2, 0)
node res_aligned_lsbMask_1 = not(_res_aligned_lsbMask_T_3)
node _res_aligned_straddlesLowerBound_T_17 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_18 = shl(io.pmp[5].addr, 2)
node _res_aligned_straddlesLowerBound_T_19 = not(_res_aligned_straddlesLowerBound_T_18)
node _res_aligned_straddlesLowerBound_T_20 = or(_res_aligned_straddlesLowerBound_T_19, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_21 = not(_res_aligned_straddlesLowerBound_T_20)
node _res_aligned_straddlesLowerBound_T_22 = shr(_res_aligned_straddlesLowerBound_T_21, 3)
node _res_aligned_straddlesLowerBound_T_23 = xor(_res_aligned_straddlesLowerBound_T_17, _res_aligned_straddlesLowerBound_T_22)
node _res_aligned_straddlesLowerBound_T_24 = eq(_res_aligned_straddlesLowerBound_T_23, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_25 = shl(io.pmp[5].addr, 2)
node _res_aligned_straddlesLowerBound_T_26 = not(_res_aligned_straddlesLowerBound_T_25)
node _res_aligned_straddlesLowerBound_T_27 = or(_res_aligned_straddlesLowerBound_T_26, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_28 = not(_res_aligned_straddlesLowerBound_T_27)
node _res_aligned_straddlesLowerBound_T_29 = bits(_res_aligned_straddlesLowerBound_T_28, 2, 0)
node _res_aligned_straddlesLowerBound_T_30 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_31 = not(_res_aligned_straddlesLowerBound_T_30)
node _res_aligned_straddlesLowerBound_T_32 = and(_res_aligned_straddlesLowerBound_T_29, _res_aligned_straddlesLowerBound_T_31)
node _res_aligned_straddlesLowerBound_T_33 = neq(_res_aligned_straddlesLowerBound_T_32, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_1 = and(_res_aligned_straddlesLowerBound_T_24, _res_aligned_straddlesLowerBound_T_33)
node _res_aligned_straddlesUpperBound_T_17 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_18 = shl(io.pmp[6].addr, 2)
node _res_aligned_straddlesUpperBound_T_19 = not(_res_aligned_straddlesUpperBound_T_18)
node _res_aligned_straddlesUpperBound_T_20 = or(_res_aligned_straddlesUpperBound_T_19, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_21 = not(_res_aligned_straddlesUpperBound_T_20)
node _res_aligned_straddlesUpperBound_T_22 = shr(_res_aligned_straddlesUpperBound_T_21, 3)
node _res_aligned_straddlesUpperBound_T_23 = xor(_res_aligned_straddlesUpperBound_T_17, _res_aligned_straddlesUpperBound_T_22)
node _res_aligned_straddlesUpperBound_T_24 = eq(_res_aligned_straddlesUpperBound_T_23, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_25 = shl(io.pmp[6].addr, 2)
node _res_aligned_straddlesUpperBound_T_26 = not(_res_aligned_straddlesUpperBound_T_25)
node _res_aligned_straddlesUpperBound_T_27 = or(_res_aligned_straddlesUpperBound_T_26, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_28 = not(_res_aligned_straddlesUpperBound_T_27)
node _res_aligned_straddlesUpperBound_T_29 = bits(_res_aligned_straddlesUpperBound_T_28, 2, 0)
node _res_aligned_straddlesUpperBound_T_30 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_31 = or(_res_aligned_straddlesUpperBound_T_30, res_aligned_lsbMask_1)
node _res_aligned_straddlesUpperBound_T_32 = and(_res_aligned_straddlesUpperBound_T_29, _res_aligned_straddlesUpperBound_T_31)
node _res_aligned_straddlesUpperBound_T_33 = neq(_res_aligned_straddlesUpperBound_T_32, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_1 = and(_res_aligned_straddlesUpperBound_T_24, _res_aligned_straddlesUpperBound_T_33)
node _res_aligned_rangeAligned_T_1 = or(res_aligned_straddlesLowerBound_1, res_aligned_straddlesUpperBound_1)
node res_aligned_rangeAligned_1 = eq(_res_aligned_rangeAligned_T_1, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_3 = bits(io.pmp[6].mask, 2, 0)
node _res_aligned_pow2Aligned_T_4 = not(_res_aligned_pow2Aligned_T_3)
node _res_aligned_pow2Aligned_T_5 = and(res_aligned_lsbMask_1, _res_aligned_pow2Aligned_T_4)
node res_aligned_pow2Aligned_1 = eq(_res_aligned_pow2Aligned_T_5, UInt<1>(0h0))
node _res_aligned_T_1 = bits(io.pmp[6].cfg.a, 1, 1)
node res_aligned_1 = mux(_res_aligned_T_1, res_aligned_pow2Aligned_1, res_aligned_rangeAligned_1)
node _res_T_45 = eq(io.pmp[6].cfg.a, UInt<1>(0h0))
node _res_T_46 = eq(io.pmp[6].cfg.a, UInt<1>(0h1))
node _res_T_47 = eq(io.pmp[6].cfg.a, UInt<2>(0h2))
node _res_T_48 = eq(io.pmp[6].cfg.a, UInt<2>(0h3))
node _res_T_49 = eq(io.pmp[6].cfg.l, UInt<1>(0h1))
node res_hi_6 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_50 = cat(res_hi_6, io.pmp[6].cfg.r)
node _res_T_51 = eq(_res_T_50, UInt<1>(0h0))
node res_hi_7 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_52 = cat(res_hi_7, io.pmp[6].cfg.r)
node _res_T_53 = eq(_res_T_52, UInt<1>(0h1))
node res_hi_8 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_54 = cat(res_hi_8, io.pmp[6].cfg.r)
node _res_T_55 = eq(_res_T_54, UInt<2>(0h3))
node res_hi_9 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_56 = cat(res_hi_9, io.pmp[6].cfg.r)
node _res_T_57 = eq(_res_T_56, UInt<3>(0h4))
node res_hi_10 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_58 = cat(res_hi_10, io.pmp[6].cfg.r)
node _res_T_59 = eq(_res_T_58, UInt<3>(0h5))
node res_hi_11 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_60 = cat(res_hi_11, io.pmp[6].cfg.r)
node _res_T_61 = eq(_res_T_60, UInt<3>(0h7))
node _res_T_62 = eq(res_ignore_1, UInt<1>(0h0))
node _res_T_63 = and(_res_T_62, res_hit_1)
node _res_T_64 = and(_res_T_63, res_aligned_1)
node _res_T_65 = eq(io.pmp[6].cfg.a, UInt<1>(0h1))
node _res_T_66 = and(_res_T_64, _res_T_65)
node _res_T_67 = and(io.pmp[6].cfg.l, res_hit_1)
node _res_T_68 = and(_res_T_67, res_aligned_1)
node _res_T_69 = eq(io.pmp[6].cfg.a, UInt<1>(0h1))
node _res_T_70 = and(_res_T_68, _res_T_69)
node _res_T_71 = eq(res_ignore_1, UInt<1>(0h0))
node _res_T_72 = and(_res_T_71, res_hit_1)
node _res_T_73 = and(_res_T_72, res_aligned_1)
node _res_T_74 = eq(io.pmp[6].cfg.a, UInt<2>(0h2))
node _res_T_75 = and(_res_T_73, _res_T_74)
node _res_T_76 = and(io.pmp[6].cfg.l, res_hit_1)
node _res_T_77 = and(_res_T_76, res_aligned_1)
node _res_T_78 = eq(io.pmp[6].cfg.a, UInt<2>(0h2))
node _res_T_79 = and(_res_T_77, _res_T_78)
node _res_T_80 = eq(res_ignore_1, UInt<1>(0h0))
node _res_T_81 = and(_res_T_80, res_hit_1)
node _res_T_82 = and(_res_T_81, res_aligned_1)
node _res_T_83 = eq(io.pmp[6].cfg.a, UInt<2>(0h3))
node _res_T_84 = and(_res_T_82, _res_T_83)
node _res_T_85 = and(io.pmp[6].cfg.l, res_hit_1)
node _res_T_86 = and(_res_T_85, res_aligned_1)
node _res_T_87 = eq(io.pmp[6].cfg.a, UInt<2>(0h3))
node _res_T_88 = and(_res_T_86, _res_T_87)
wire res_cur_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_1, io.pmp[6]
node _res_cur_cfg_r_T_2 = or(io.pmp[6].cfg.r, res_ignore_1)
node _res_cur_cfg_r_T_3 = and(res_aligned_1, _res_cur_cfg_r_T_2)
connect res_cur_1.cfg.r, _res_cur_cfg_r_T_3
node _res_cur_cfg_w_T_2 = or(io.pmp[6].cfg.w, res_ignore_1)
node _res_cur_cfg_w_T_3 = and(res_aligned_1, _res_cur_cfg_w_T_2)
connect res_cur_1.cfg.w, _res_cur_cfg_w_T_3
node _res_cur_cfg_x_T_2 = or(io.pmp[6].cfg.x, res_ignore_1)
node _res_cur_cfg_x_T_3 = and(res_aligned_1, _res_cur_cfg_x_T_2)
connect res_cur_1.cfg.x, _res_cur_cfg_x_T_3
node _res_T_89 = mux(res_hit_1, res_cur_1, _res_T_44)
node _res_hit_T_26 = bits(io.pmp[5].cfg.a, 1, 1)
node _res_hit_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_7 = bits(_res_hit_lsbMask_T_6, 2, 0)
node _res_hit_lsbMask_T_8 = not(_res_hit_lsbMask_T_7)
node res_hit_lsbMask_2 = or(io.pmp[5].mask, _res_hit_lsbMask_T_8)
node _res_hit_msbMatch_T_20 = shr(io.addr, 3)
node _res_hit_msbMatch_T_21 = shl(io.pmp[5].addr, 2)
node _res_hit_msbMatch_T_22 = not(_res_hit_msbMatch_T_21)
node _res_hit_msbMatch_T_23 = or(_res_hit_msbMatch_T_22, UInt<2>(0h3))
node _res_hit_msbMatch_T_24 = not(_res_hit_msbMatch_T_23)
node _res_hit_msbMatch_T_25 = shr(_res_hit_msbMatch_T_24, 3)
node _res_hit_msbMatch_T_26 = shr(io.pmp[5].mask, 3)
node _res_hit_msbMatch_T_27 = xor(_res_hit_msbMatch_T_20, _res_hit_msbMatch_T_25)
node _res_hit_msbMatch_T_28 = not(_res_hit_msbMatch_T_26)
node _res_hit_msbMatch_T_29 = and(_res_hit_msbMatch_T_27, _res_hit_msbMatch_T_28)
node res_hit_msbMatch_2 = eq(_res_hit_msbMatch_T_29, UInt<1>(0h0))
node _res_hit_lsbMatch_T_20 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_21 = shl(io.pmp[5].addr, 2)
node _res_hit_lsbMatch_T_22 = not(_res_hit_lsbMatch_T_21)
node _res_hit_lsbMatch_T_23 = or(_res_hit_lsbMatch_T_22, UInt<2>(0h3))
node _res_hit_lsbMatch_T_24 = not(_res_hit_lsbMatch_T_23)
node _res_hit_lsbMatch_T_25 = bits(_res_hit_lsbMatch_T_24, 2, 0)
node _res_hit_lsbMatch_T_26 = bits(res_hit_lsbMask_2, 2, 0)
node _res_hit_lsbMatch_T_27 = xor(_res_hit_lsbMatch_T_20, _res_hit_lsbMatch_T_25)
node _res_hit_lsbMatch_T_28 = not(_res_hit_lsbMatch_T_26)
node _res_hit_lsbMatch_T_29 = and(_res_hit_lsbMatch_T_27, _res_hit_lsbMatch_T_28)
node res_hit_lsbMatch_2 = eq(_res_hit_lsbMatch_T_29, UInt<1>(0h0))
node _res_hit_T_27 = and(res_hit_msbMatch_2, res_hit_lsbMatch_2)
node _res_hit_T_28 = bits(io.pmp[5].cfg.a, 0, 0)
node _res_hit_T_29 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_30 = bits(_res_hit_T_29, 2, 0)
node _res_hit_T_31 = not(_res_hit_T_30)
node _res_hit_msbsLess_T_24 = shr(io.addr, 3)
node _res_hit_msbsLess_T_25 = shl(io.pmp[4].addr, 2)
node _res_hit_msbsLess_T_26 = not(_res_hit_msbsLess_T_25)
node _res_hit_msbsLess_T_27 = or(_res_hit_msbsLess_T_26, UInt<2>(0h3))
node _res_hit_msbsLess_T_28 = not(_res_hit_msbsLess_T_27)
node _res_hit_msbsLess_T_29 = shr(_res_hit_msbsLess_T_28, 3)
node res_hit_msbsLess_4 = lt(_res_hit_msbsLess_T_24, _res_hit_msbsLess_T_29)
node _res_hit_msbsEqual_T_28 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_29 = shl(io.pmp[4].addr, 2)
node _res_hit_msbsEqual_T_30 = not(_res_hit_msbsEqual_T_29)
node _res_hit_msbsEqual_T_31 = or(_res_hit_msbsEqual_T_30, UInt<2>(0h3))
node _res_hit_msbsEqual_T_32 = not(_res_hit_msbsEqual_T_31)
node _res_hit_msbsEqual_T_33 = shr(_res_hit_msbsEqual_T_32, 3)
node _res_hit_msbsEqual_T_34 = xor(_res_hit_msbsEqual_T_28, _res_hit_msbsEqual_T_33)
node res_hit_msbsEqual_4 = eq(_res_hit_msbsEqual_T_34, UInt<1>(0h0))
node _res_hit_lsbsLess_T_28 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_29 = or(_res_hit_lsbsLess_T_28, _res_hit_T_31)
node _res_hit_lsbsLess_T_30 = shl(io.pmp[4].addr, 2)
node _res_hit_lsbsLess_T_31 = not(_res_hit_lsbsLess_T_30)
node _res_hit_lsbsLess_T_32 = or(_res_hit_lsbsLess_T_31, UInt<2>(0h3))
node _res_hit_lsbsLess_T_33 = not(_res_hit_lsbsLess_T_32)
node _res_hit_lsbsLess_T_34 = bits(_res_hit_lsbsLess_T_33, 2, 0)
node res_hit_lsbsLess_4 = lt(_res_hit_lsbsLess_T_29, _res_hit_lsbsLess_T_34)
node _res_hit_T_32 = and(res_hit_msbsEqual_4, res_hit_lsbsLess_4)
node _res_hit_T_33 = or(res_hit_msbsLess_4, _res_hit_T_32)
node _res_hit_T_34 = eq(_res_hit_T_33, UInt<1>(0h0))
node _res_hit_msbsLess_T_30 = shr(io.addr, 3)
node _res_hit_msbsLess_T_31 = shl(io.pmp[5].addr, 2)
node _res_hit_msbsLess_T_32 = not(_res_hit_msbsLess_T_31)
node _res_hit_msbsLess_T_33 = or(_res_hit_msbsLess_T_32, UInt<2>(0h3))
node _res_hit_msbsLess_T_34 = not(_res_hit_msbsLess_T_33)
node _res_hit_msbsLess_T_35 = shr(_res_hit_msbsLess_T_34, 3)
node res_hit_msbsLess_5 = lt(_res_hit_msbsLess_T_30, _res_hit_msbsLess_T_35)
node _res_hit_msbsEqual_T_35 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_36 = shl(io.pmp[5].addr, 2)
node _res_hit_msbsEqual_T_37 = not(_res_hit_msbsEqual_T_36)
node _res_hit_msbsEqual_T_38 = or(_res_hit_msbsEqual_T_37, UInt<2>(0h3))
node _res_hit_msbsEqual_T_39 = not(_res_hit_msbsEqual_T_38)
node _res_hit_msbsEqual_T_40 = shr(_res_hit_msbsEqual_T_39, 3)
node _res_hit_msbsEqual_T_41 = xor(_res_hit_msbsEqual_T_35, _res_hit_msbsEqual_T_40)
node res_hit_msbsEqual_5 = eq(_res_hit_msbsEqual_T_41, UInt<1>(0h0))
node _res_hit_lsbsLess_T_35 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_36 = or(_res_hit_lsbsLess_T_35, UInt<1>(0h0))
node _res_hit_lsbsLess_T_37 = shl(io.pmp[5].addr, 2)
node _res_hit_lsbsLess_T_38 = not(_res_hit_lsbsLess_T_37)
node _res_hit_lsbsLess_T_39 = or(_res_hit_lsbsLess_T_38, UInt<2>(0h3))
node _res_hit_lsbsLess_T_40 = not(_res_hit_lsbsLess_T_39)
node _res_hit_lsbsLess_T_41 = bits(_res_hit_lsbsLess_T_40, 2, 0)
node res_hit_lsbsLess_5 = lt(_res_hit_lsbsLess_T_36, _res_hit_lsbsLess_T_41)
node _res_hit_T_35 = and(res_hit_msbsEqual_5, res_hit_lsbsLess_5)
node _res_hit_T_36 = or(res_hit_msbsLess_5, _res_hit_T_35)
node _res_hit_T_37 = and(_res_hit_T_34, _res_hit_T_36)
node _res_hit_T_38 = and(_res_hit_T_28, _res_hit_T_37)
node res_hit_2 = mux(_res_hit_T_26, _res_hit_T_27, _res_hit_T_38)
node _res_ignore_T_2 = eq(io.pmp[5].cfg.l, UInt<1>(0h0))
node res_ignore_2 = and(default, _res_ignore_T_2)
node _res_aligned_lsbMask_T_4 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_5 = bits(_res_aligned_lsbMask_T_4, 2, 0)
node res_aligned_lsbMask_2 = not(_res_aligned_lsbMask_T_5)
node _res_aligned_straddlesLowerBound_T_34 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_35 = shl(io.pmp[4].addr, 2)
node _res_aligned_straddlesLowerBound_T_36 = not(_res_aligned_straddlesLowerBound_T_35)
node _res_aligned_straddlesLowerBound_T_37 = or(_res_aligned_straddlesLowerBound_T_36, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_38 = not(_res_aligned_straddlesLowerBound_T_37)
node _res_aligned_straddlesLowerBound_T_39 = shr(_res_aligned_straddlesLowerBound_T_38, 3)
node _res_aligned_straddlesLowerBound_T_40 = xor(_res_aligned_straddlesLowerBound_T_34, _res_aligned_straddlesLowerBound_T_39)
node _res_aligned_straddlesLowerBound_T_41 = eq(_res_aligned_straddlesLowerBound_T_40, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_42 = shl(io.pmp[4].addr, 2)
node _res_aligned_straddlesLowerBound_T_43 = not(_res_aligned_straddlesLowerBound_T_42)
node _res_aligned_straddlesLowerBound_T_44 = or(_res_aligned_straddlesLowerBound_T_43, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_45 = not(_res_aligned_straddlesLowerBound_T_44)
node _res_aligned_straddlesLowerBound_T_46 = bits(_res_aligned_straddlesLowerBound_T_45, 2, 0)
node _res_aligned_straddlesLowerBound_T_47 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_48 = not(_res_aligned_straddlesLowerBound_T_47)
node _res_aligned_straddlesLowerBound_T_49 = and(_res_aligned_straddlesLowerBound_T_46, _res_aligned_straddlesLowerBound_T_48)
node _res_aligned_straddlesLowerBound_T_50 = neq(_res_aligned_straddlesLowerBound_T_49, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_2 = and(_res_aligned_straddlesLowerBound_T_41, _res_aligned_straddlesLowerBound_T_50)
node _res_aligned_straddlesUpperBound_T_34 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_35 = shl(io.pmp[5].addr, 2)
node _res_aligned_straddlesUpperBound_T_36 = not(_res_aligned_straddlesUpperBound_T_35)
node _res_aligned_straddlesUpperBound_T_37 = or(_res_aligned_straddlesUpperBound_T_36, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_38 = not(_res_aligned_straddlesUpperBound_T_37)
node _res_aligned_straddlesUpperBound_T_39 = shr(_res_aligned_straddlesUpperBound_T_38, 3)
node _res_aligned_straddlesUpperBound_T_40 = xor(_res_aligned_straddlesUpperBound_T_34, _res_aligned_straddlesUpperBound_T_39)
node _res_aligned_straddlesUpperBound_T_41 = eq(_res_aligned_straddlesUpperBound_T_40, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_42 = shl(io.pmp[5].addr, 2)
node _res_aligned_straddlesUpperBound_T_43 = not(_res_aligned_straddlesUpperBound_T_42)
node _res_aligned_straddlesUpperBound_T_44 = or(_res_aligned_straddlesUpperBound_T_43, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_45 = not(_res_aligned_straddlesUpperBound_T_44)
node _res_aligned_straddlesUpperBound_T_46 = bits(_res_aligned_straddlesUpperBound_T_45, 2, 0)
node _res_aligned_straddlesUpperBound_T_47 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_48 = or(_res_aligned_straddlesUpperBound_T_47, res_aligned_lsbMask_2)
node _res_aligned_straddlesUpperBound_T_49 = and(_res_aligned_straddlesUpperBound_T_46, _res_aligned_straddlesUpperBound_T_48)
node _res_aligned_straddlesUpperBound_T_50 = neq(_res_aligned_straddlesUpperBound_T_49, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_2 = and(_res_aligned_straddlesUpperBound_T_41, _res_aligned_straddlesUpperBound_T_50)
node _res_aligned_rangeAligned_T_2 = or(res_aligned_straddlesLowerBound_2, res_aligned_straddlesUpperBound_2)
node res_aligned_rangeAligned_2 = eq(_res_aligned_rangeAligned_T_2, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_6 = bits(io.pmp[5].mask, 2, 0)
node _res_aligned_pow2Aligned_T_7 = not(_res_aligned_pow2Aligned_T_6)
node _res_aligned_pow2Aligned_T_8 = and(res_aligned_lsbMask_2, _res_aligned_pow2Aligned_T_7)
node res_aligned_pow2Aligned_2 = eq(_res_aligned_pow2Aligned_T_8, UInt<1>(0h0))
node _res_aligned_T_2 = bits(io.pmp[5].cfg.a, 1, 1)
node res_aligned_2 = mux(_res_aligned_T_2, res_aligned_pow2Aligned_2, res_aligned_rangeAligned_2)
node _res_T_90 = eq(io.pmp[5].cfg.a, UInt<1>(0h0))
node _res_T_91 = eq(io.pmp[5].cfg.a, UInt<1>(0h1))
node _res_T_92 = eq(io.pmp[5].cfg.a, UInt<2>(0h2))
node _res_T_93 = eq(io.pmp[5].cfg.a, UInt<2>(0h3))
node _res_T_94 = eq(io.pmp[5].cfg.l, UInt<1>(0h1))
node res_hi_12 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_95 = cat(res_hi_12, io.pmp[5].cfg.r)
node _res_T_96 = eq(_res_T_95, UInt<1>(0h0))
node res_hi_13 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_97 = cat(res_hi_13, io.pmp[5].cfg.r)
node _res_T_98 = eq(_res_T_97, UInt<1>(0h1))
node res_hi_14 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_99 = cat(res_hi_14, io.pmp[5].cfg.r)
node _res_T_100 = eq(_res_T_99, UInt<2>(0h3))
node res_hi_15 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_101 = cat(res_hi_15, io.pmp[5].cfg.r)
node _res_T_102 = eq(_res_T_101, UInt<3>(0h4))
node res_hi_16 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_103 = cat(res_hi_16, io.pmp[5].cfg.r)
node _res_T_104 = eq(_res_T_103, UInt<3>(0h5))
node res_hi_17 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_105 = cat(res_hi_17, io.pmp[5].cfg.r)
node _res_T_106 = eq(_res_T_105, UInt<3>(0h7))
node _res_T_107 = eq(res_ignore_2, UInt<1>(0h0))
node _res_T_108 = and(_res_T_107, res_hit_2)
node _res_T_109 = and(_res_T_108, res_aligned_2)
node _res_T_110 = eq(io.pmp[5].cfg.a, UInt<1>(0h1))
node _res_T_111 = and(_res_T_109, _res_T_110)
node _res_T_112 = and(io.pmp[5].cfg.l, res_hit_2)
node _res_T_113 = and(_res_T_112, res_aligned_2)
node _res_T_114 = eq(io.pmp[5].cfg.a, UInt<1>(0h1))
node _res_T_115 = and(_res_T_113, _res_T_114)
node _res_T_116 = eq(res_ignore_2, UInt<1>(0h0))
node _res_T_117 = and(_res_T_116, res_hit_2)
node _res_T_118 = and(_res_T_117, res_aligned_2)
node _res_T_119 = eq(io.pmp[5].cfg.a, UInt<2>(0h2))
node _res_T_120 = and(_res_T_118, _res_T_119)
node _res_T_121 = and(io.pmp[5].cfg.l, res_hit_2)
node _res_T_122 = and(_res_T_121, res_aligned_2)
node _res_T_123 = eq(io.pmp[5].cfg.a, UInt<2>(0h2))
node _res_T_124 = and(_res_T_122, _res_T_123)
node _res_T_125 = eq(res_ignore_2, UInt<1>(0h0))
node _res_T_126 = and(_res_T_125, res_hit_2)
node _res_T_127 = and(_res_T_126, res_aligned_2)
node _res_T_128 = eq(io.pmp[5].cfg.a, UInt<2>(0h3))
node _res_T_129 = and(_res_T_127, _res_T_128)
node _res_T_130 = and(io.pmp[5].cfg.l, res_hit_2)
node _res_T_131 = and(_res_T_130, res_aligned_2)
node _res_T_132 = eq(io.pmp[5].cfg.a, UInt<2>(0h3))
node _res_T_133 = and(_res_T_131, _res_T_132)
wire res_cur_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_2, io.pmp[5]
node _res_cur_cfg_r_T_4 = or(io.pmp[5].cfg.r, res_ignore_2)
node _res_cur_cfg_r_T_5 = and(res_aligned_2, _res_cur_cfg_r_T_4)
connect res_cur_2.cfg.r, _res_cur_cfg_r_T_5
node _res_cur_cfg_w_T_4 = or(io.pmp[5].cfg.w, res_ignore_2)
node _res_cur_cfg_w_T_5 = and(res_aligned_2, _res_cur_cfg_w_T_4)
connect res_cur_2.cfg.w, _res_cur_cfg_w_T_5
node _res_cur_cfg_x_T_4 = or(io.pmp[5].cfg.x, res_ignore_2)
node _res_cur_cfg_x_T_5 = and(res_aligned_2, _res_cur_cfg_x_T_4)
connect res_cur_2.cfg.x, _res_cur_cfg_x_T_5
node _res_T_134 = mux(res_hit_2, res_cur_2, _res_T_89)
node _res_hit_T_39 = bits(io.pmp[4].cfg.a, 1, 1)
node _res_hit_lsbMask_T_9 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_10 = bits(_res_hit_lsbMask_T_9, 2, 0)
node _res_hit_lsbMask_T_11 = not(_res_hit_lsbMask_T_10)
node res_hit_lsbMask_3 = or(io.pmp[4].mask, _res_hit_lsbMask_T_11)
node _res_hit_msbMatch_T_30 = shr(io.addr, 3)
node _res_hit_msbMatch_T_31 = shl(io.pmp[4].addr, 2)
node _res_hit_msbMatch_T_32 = not(_res_hit_msbMatch_T_31)
node _res_hit_msbMatch_T_33 = or(_res_hit_msbMatch_T_32, UInt<2>(0h3))
node _res_hit_msbMatch_T_34 = not(_res_hit_msbMatch_T_33)
node _res_hit_msbMatch_T_35 = shr(_res_hit_msbMatch_T_34, 3)
node _res_hit_msbMatch_T_36 = shr(io.pmp[4].mask, 3)
node _res_hit_msbMatch_T_37 = xor(_res_hit_msbMatch_T_30, _res_hit_msbMatch_T_35)
node _res_hit_msbMatch_T_38 = not(_res_hit_msbMatch_T_36)
node _res_hit_msbMatch_T_39 = and(_res_hit_msbMatch_T_37, _res_hit_msbMatch_T_38)
node res_hit_msbMatch_3 = eq(_res_hit_msbMatch_T_39, UInt<1>(0h0))
node _res_hit_lsbMatch_T_30 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_31 = shl(io.pmp[4].addr, 2)
node _res_hit_lsbMatch_T_32 = not(_res_hit_lsbMatch_T_31)
node _res_hit_lsbMatch_T_33 = or(_res_hit_lsbMatch_T_32, UInt<2>(0h3))
node _res_hit_lsbMatch_T_34 = not(_res_hit_lsbMatch_T_33)
node _res_hit_lsbMatch_T_35 = bits(_res_hit_lsbMatch_T_34, 2, 0)
node _res_hit_lsbMatch_T_36 = bits(res_hit_lsbMask_3, 2, 0)
node _res_hit_lsbMatch_T_37 = xor(_res_hit_lsbMatch_T_30, _res_hit_lsbMatch_T_35)
node _res_hit_lsbMatch_T_38 = not(_res_hit_lsbMatch_T_36)
node _res_hit_lsbMatch_T_39 = and(_res_hit_lsbMatch_T_37, _res_hit_lsbMatch_T_38)
node res_hit_lsbMatch_3 = eq(_res_hit_lsbMatch_T_39, UInt<1>(0h0))
node _res_hit_T_40 = and(res_hit_msbMatch_3, res_hit_lsbMatch_3)
node _res_hit_T_41 = bits(io.pmp[4].cfg.a, 0, 0)
node _res_hit_T_42 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_43 = bits(_res_hit_T_42, 2, 0)
node _res_hit_T_44 = not(_res_hit_T_43)
node _res_hit_msbsLess_T_36 = shr(io.addr, 3)
node _res_hit_msbsLess_T_37 = shl(io.pmp[3].addr, 2)
node _res_hit_msbsLess_T_38 = not(_res_hit_msbsLess_T_37)
node _res_hit_msbsLess_T_39 = or(_res_hit_msbsLess_T_38, UInt<2>(0h3))
node _res_hit_msbsLess_T_40 = not(_res_hit_msbsLess_T_39)
node _res_hit_msbsLess_T_41 = shr(_res_hit_msbsLess_T_40, 3)
node res_hit_msbsLess_6 = lt(_res_hit_msbsLess_T_36, _res_hit_msbsLess_T_41)
node _res_hit_msbsEqual_T_42 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_43 = shl(io.pmp[3].addr, 2)
node _res_hit_msbsEqual_T_44 = not(_res_hit_msbsEqual_T_43)
node _res_hit_msbsEqual_T_45 = or(_res_hit_msbsEqual_T_44, UInt<2>(0h3))
node _res_hit_msbsEqual_T_46 = not(_res_hit_msbsEqual_T_45)
node _res_hit_msbsEqual_T_47 = shr(_res_hit_msbsEqual_T_46, 3)
node _res_hit_msbsEqual_T_48 = xor(_res_hit_msbsEqual_T_42, _res_hit_msbsEqual_T_47)
node res_hit_msbsEqual_6 = eq(_res_hit_msbsEqual_T_48, UInt<1>(0h0))
node _res_hit_lsbsLess_T_42 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_43 = or(_res_hit_lsbsLess_T_42, _res_hit_T_44)
node _res_hit_lsbsLess_T_44 = shl(io.pmp[3].addr, 2)
node _res_hit_lsbsLess_T_45 = not(_res_hit_lsbsLess_T_44)
node _res_hit_lsbsLess_T_46 = or(_res_hit_lsbsLess_T_45, UInt<2>(0h3))
node _res_hit_lsbsLess_T_47 = not(_res_hit_lsbsLess_T_46)
node _res_hit_lsbsLess_T_48 = bits(_res_hit_lsbsLess_T_47, 2, 0)
node res_hit_lsbsLess_6 = lt(_res_hit_lsbsLess_T_43, _res_hit_lsbsLess_T_48)
node _res_hit_T_45 = and(res_hit_msbsEqual_6, res_hit_lsbsLess_6)
node _res_hit_T_46 = or(res_hit_msbsLess_6, _res_hit_T_45)
node _res_hit_T_47 = eq(_res_hit_T_46, UInt<1>(0h0))
node _res_hit_msbsLess_T_42 = shr(io.addr, 3)
node _res_hit_msbsLess_T_43 = shl(io.pmp[4].addr, 2)
node _res_hit_msbsLess_T_44 = not(_res_hit_msbsLess_T_43)
node _res_hit_msbsLess_T_45 = or(_res_hit_msbsLess_T_44, UInt<2>(0h3))
node _res_hit_msbsLess_T_46 = not(_res_hit_msbsLess_T_45)
node _res_hit_msbsLess_T_47 = shr(_res_hit_msbsLess_T_46, 3)
node res_hit_msbsLess_7 = lt(_res_hit_msbsLess_T_42, _res_hit_msbsLess_T_47)
node _res_hit_msbsEqual_T_49 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_50 = shl(io.pmp[4].addr, 2)
node _res_hit_msbsEqual_T_51 = not(_res_hit_msbsEqual_T_50)
node _res_hit_msbsEqual_T_52 = or(_res_hit_msbsEqual_T_51, UInt<2>(0h3))
node _res_hit_msbsEqual_T_53 = not(_res_hit_msbsEqual_T_52)
node _res_hit_msbsEqual_T_54 = shr(_res_hit_msbsEqual_T_53, 3)
node _res_hit_msbsEqual_T_55 = xor(_res_hit_msbsEqual_T_49, _res_hit_msbsEqual_T_54)
node res_hit_msbsEqual_7 = eq(_res_hit_msbsEqual_T_55, UInt<1>(0h0))
node _res_hit_lsbsLess_T_49 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_50 = or(_res_hit_lsbsLess_T_49, UInt<1>(0h0))
node _res_hit_lsbsLess_T_51 = shl(io.pmp[4].addr, 2)
node _res_hit_lsbsLess_T_52 = not(_res_hit_lsbsLess_T_51)
node _res_hit_lsbsLess_T_53 = or(_res_hit_lsbsLess_T_52, UInt<2>(0h3))
node _res_hit_lsbsLess_T_54 = not(_res_hit_lsbsLess_T_53)
node _res_hit_lsbsLess_T_55 = bits(_res_hit_lsbsLess_T_54, 2, 0)
node res_hit_lsbsLess_7 = lt(_res_hit_lsbsLess_T_50, _res_hit_lsbsLess_T_55)
node _res_hit_T_48 = and(res_hit_msbsEqual_7, res_hit_lsbsLess_7)
node _res_hit_T_49 = or(res_hit_msbsLess_7, _res_hit_T_48)
node _res_hit_T_50 = and(_res_hit_T_47, _res_hit_T_49)
node _res_hit_T_51 = and(_res_hit_T_41, _res_hit_T_50)
node res_hit_3 = mux(_res_hit_T_39, _res_hit_T_40, _res_hit_T_51)
node _res_ignore_T_3 = eq(io.pmp[4].cfg.l, UInt<1>(0h0))
node res_ignore_3 = and(default, _res_ignore_T_3)
node _res_aligned_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_7 = bits(_res_aligned_lsbMask_T_6, 2, 0)
node res_aligned_lsbMask_3 = not(_res_aligned_lsbMask_T_7)
node _res_aligned_straddlesLowerBound_T_51 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_52 = shl(io.pmp[3].addr, 2)
node _res_aligned_straddlesLowerBound_T_53 = not(_res_aligned_straddlesLowerBound_T_52)
node _res_aligned_straddlesLowerBound_T_54 = or(_res_aligned_straddlesLowerBound_T_53, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_55 = not(_res_aligned_straddlesLowerBound_T_54)
node _res_aligned_straddlesLowerBound_T_56 = shr(_res_aligned_straddlesLowerBound_T_55, 3)
node _res_aligned_straddlesLowerBound_T_57 = xor(_res_aligned_straddlesLowerBound_T_51, _res_aligned_straddlesLowerBound_T_56)
node _res_aligned_straddlesLowerBound_T_58 = eq(_res_aligned_straddlesLowerBound_T_57, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_59 = shl(io.pmp[3].addr, 2)
node _res_aligned_straddlesLowerBound_T_60 = not(_res_aligned_straddlesLowerBound_T_59)
node _res_aligned_straddlesLowerBound_T_61 = or(_res_aligned_straddlesLowerBound_T_60, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_62 = not(_res_aligned_straddlesLowerBound_T_61)
node _res_aligned_straddlesLowerBound_T_63 = bits(_res_aligned_straddlesLowerBound_T_62, 2, 0)
node _res_aligned_straddlesLowerBound_T_64 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_65 = not(_res_aligned_straddlesLowerBound_T_64)
node _res_aligned_straddlesLowerBound_T_66 = and(_res_aligned_straddlesLowerBound_T_63, _res_aligned_straddlesLowerBound_T_65)
node _res_aligned_straddlesLowerBound_T_67 = neq(_res_aligned_straddlesLowerBound_T_66, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_3 = and(_res_aligned_straddlesLowerBound_T_58, _res_aligned_straddlesLowerBound_T_67)
node _res_aligned_straddlesUpperBound_T_51 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_52 = shl(io.pmp[4].addr, 2)
node _res_aligned_straddlesUpperBound_T_53 = not(_res_aligned_straddlesUpperBound_T_52)
node _res_aligned_straddlesUpperBound_T_54 = or(_res_aligned_straddlesUpperBound_T_53, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_55 = not(_res_aligned_straddlesUpperBound_T_54)
node _res_aligned_straddlesUpperBound_T_56 = shr(_res_aligned_straddlesUpperBound_T_55, 3)
node _res_aligned_straddlesUpperBound_T_57 = xor(_res_aligned_straddlesUpperBound_T_51, _res_aligned_straddlesUpperBound_T_56)
node _res_aligned_straddlesUpperBound_T_58 = eq(_res_aligned_straddlesUpperBound_T_57, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_59 = shl(io.pmp[4].addr, 2)
node _res_aligned_straddlesUpperBound_T_60 = not(_res_aligned_straddlesUpperBound_T_59)
node _res_aligned_straddlesUpperBound_T_61 = or(_res_aligned_straddlesUpperBound_T_60, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_62 = not(_res_aligned_straddlesUpperBound_T_61)
node _res_aligned_straddlesUpperBound_T_63 = bits(_res_aligned_straddlesUpperBound_T_62, 2, 0)
node _res_aligned_straddlesUpperBound_T_64 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_65 = or(_res_aligned_straddlesUpperBound_T_64, res_aligned_lsbMask_3)
node _res_aligned_straddlesUpperBound_T_66 = and(_res_aligned_straddlesUpperBound_T_63, _res_aligned_straddlesUpperBound_T_65)
node _res_aligned_straddlesUpperBound_T_67 = neq(_res_aligned_straddlesUpperBound_T_66, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_3 = and(_res_aligned_straddlesUpperBound_T_58, _res_aligned_straddlesUpperBound_T_67)
node _res_aligned_rangeAligned_T_3 = or(res_aligned_straddlesLowerBound_3, res_aligned_straddlesUpperBound_3)
node res_aligned_rangeAligned_3 = eq(_res_aligned_rangeAligned_T_3, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_9 = bits(io.pmp[4].mask, 2, 0)
node _res_aligned_pow2Aligned_T_10 = not(_res_aligned_pow2Aligned_T_9)
node _res_aligned_pow2Aligned_T_11 = and(res_aligned_lsbMask_3, _res_aligned_pow2Aligned_T_10)
node res_aligned_pow2Aligned_3 = eq(_res_aligned_pow2Aligned_T_11, UInt<1>(0h0))
node _res_aligned_T_3 = bits(io.pmp[4].cfg.a, 1, 1)
node res_aligned_3 = mux(_res_aligned_T_3, res_aligned_pow2Aligned_3, res_aligned_rangeAligned_3)
node _res_T_135 = eq(io.pmp[4].cfg.a, UInt<1>(0h0))
node _res_T_136 = eq(io.pmp[4].cfg.a, UInt<1>(0h1))
node _res_T_137 = eq(io.pmp[4].cfg.a, UInt<2>(0h2))
node _res_T_138 = eq(io.pmp[4].cfg.a, UInt<2>(0h3))
node _res_T_139 = eq(io.pmp[4].cfg.l, UInt<1>(0h1))
node res_hi_18 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_140 = cat(res_hi_18, io.pmp[4].cfg.r)
node _res_T_141 = eq(_res_T_140, UInt<1>(0h0))
node res_hi_19 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_142 = cat(res_hi_19, io.pmp[4].cfg.r)
node _res_T_143 = eq(_res_T_142, UInt<1>(0h1))
node res_hi_20 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_144 = cat(res_hi_20, io.pmp[4].cfg.r)
node _res_T_145 = eq(_res_T_144, UInt<2>(0h3))
node res_hi_21 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_146 = cat(res_hi_21, io.pmp[4].cfg.r)
node _res_T_147 = eq(_res_T_146, UInt<3>(0h4))
node res_hi_22 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_148 = cat(res_hi_22, io.pmp[4].cfg.r)
node _res_T_149 = eq(_res_T_148, UInt<3>(0h5))
node res_hi_23 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_150 = cat(res_hi_23, io.pmp[4].cfg.r)
node _res_T_151 = eq(_res_T_150, UInt<3>(0h7))
node _res_T_152 = eq(res_ignore_3, UInt<1>(0h0))
node _res_T_153 = and(_res_T_152, res_hit_3)
node _res_T_154 = and(_res_T_153, res_aligned_3)
node _res_T_155 = eq(io.pmp[4].cfg.a, UInt<1>(0h1))
node _res_T_156 = and(_res_T_154, _res_T_155)
node _res_T_157 = and(io.pmp[4].cfg.l, res_hit_3)
node _res_T_158 = and(_res_T_157, res_aligned_3)
node _res_T_159 = eq(io.pmp[4].cfg.a, UInt<1>(0h1))
node _res_T_160 = and(_res_T_158, _res_T_159)
node _res_T_161 = eq(res_ignore_3, UInt<1>(0h0))
node _res_T_162 = and(_res_T_161, res_hit_3)
node _res_T_163 = and(_res_T_162, res_aligned_3)
node _res_T_164 = eq(io.pmp[4].cfg.a, UInt<2>(0h2))
node _res_T_165 = and(_res_T_163, _res_T_164)
node _res_T_166 = and(io.pmp[4].cfg.l, res_hit_3)
node _res_T_167 = and(_res_T_166, res_aligned_3)
node _res_T_168 = eq(io.pmp[4].cfg.a, UInt<2>(0h2))
node _res_T_169 = and(_res_T_167, _res_T_168)
node _res_T_170 = eq(res_ignore_3, UInt<1>(0h0))
node _res_T_171 = and(_res_T_170, res_hit_3)
node _res_T_172 = and(_res_T_171, res_aligned_3)
node _res_T_173 = eq(io.pmp[4].cfg.a, UInt<2>(0h3))
node _res_T_174 = and(_res_T_172, _res_T_173)
node _res_T_175 = and(io.pmp[4].cfg.l, res_hit_3)
node _res_T_176 = and(_res_T_175, res_aligned_3)
node _res_T_177 = eq(io.pmp[4].cfg.a, UInt<2>(0h3))
node _res_T_178 = and(_res_T_176, _res_T_177)
wire res_cur_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_3, io.pmp[4]
node _res_cur_cfg_r_T_6 = or(io.pmp[4].cfg.r, res_ignore_3)
node _res_cur_cfg_r_T_7 = and(res_aligned_3, _res_cur_cfg_r_T_6)
connect res_cur_3.cfg.r, _res_cur_cfg_r_T_7
node _res_cur_cfg_w_T_6 = or(io.pmp[4].cfg.w, res_ignore_3)
node _res_cur_cfg_w_T_7 = and(res_aligned_3, _res_cur_cfg_w_T_6)
connect res_cur_3.cfg.w, _res_cur_cfg_w_T_7
node _res_cur_cfg_x_T_6 = or(io.pmp[4].cfg.x, res_ignore_3)
node _res_cur_cfg_x_T_7 = and(res_aligned_3, _res_cur_cfg_x_T_6)
connect res_cur_3.cfg.x, _res_cur_cfg_x_T_7
node _res_T_179 = mux(res_hit_3, res_cur_3, _res_T_134)
node _res_hit_T_52 = bits(io.pmp[3].cfg.a, 1, 1)
node _res_hit_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_13 = bits(_res_hit_lsbMask_T_12, 2, 0)
node _res_hit_lsbMask_T_14 = not(_res_hit_lsbMask_T_13)
node res_hit_lsbMask_4 = or(io.pmp[3].mask, _res_hit_lsbMask_T_14)
node _res_hit_msbMatch_T_40 = shr(io.addr, 3)
node _res_hit_msbMatch_T_41 = shl(io.pmp[3].addr, 2)
node _res_hit_msbMatch_T_42 = not(_res_hit_msbMatch_T_41)
node _res_hit_msbMatch_T_43 = or(_res_hit_msbMatch_T_42, UInt<2>(0h3))
node _res_hit_msbMatch_T_44 = not(_res_hit_msbMatch_T_43)
node _res_hit_msbMatch_T_45 = shr(_res_hit_msbMatch_T_44, 3)
node _res_hit_msbMatch_T_46 = shr(io.pmp[3].mask, 3)
node _res_hit_msbMatch_T_47 = xor(_res_hit_msbMatch_T_40, _res_hit_msbMatch_T_45)
node _res_hit_msbMatch_T_48 = not(_res_hit_msbMatch_T_46)
node _res_hit_msbMatch_T_49 = and(_res_hit_msbMatch_T_47, _res_hit_msbMatch_T_48)
node res_hit_msbMatch_4 = eq(_res_hit_msbMatch_T_49, UInt<1>(0h0))
node _res_hit_lsbMatch_T_40 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_41 = shl(io.pmp[3].addr, 2)
node _res_hit_lsbMatch_T_42 = not(_res_hit_lsbMatch_T_41)
node _res_hit_lsbMatch_T_43 = or(_res_hit_lsbMatch_T_42, UInt<2>(0h3))
node _res_hit_lsbMatch_T_44 = not(_res_hit_lsbMatch_T_43)
node _res_hit_lsbMatch_T_45 = bits(_res_hit_lsbMatch_T_44, 2, 0)
node _res_hit_lsbMatch_T_46 = bits(res_hit_lsbMask_4, 2, 0)
node _res_hit_lsbMatch_T_47 = xor(_res_hit_lsbMatch_T_40, _res_hit_lsbMatch_T_45)
node _res_hit_lsbMatch_T_48 = not(_res_hit_lsbMatch_T_46)
node _res_hit_lsbMatch_T_49 = and(_res_hit_lsbMatch_T_47, _res_hit_lsbMatch_T_48)
node res_hit_lsbMatch_4 = eq(_res_hit_lsbMatch_T_49, UInt<1>(0h0))
node _res_hit_T_53 = and(res_hit_msbMatch_4, res_hit_lsbMatch_4)
node _res_hit_T_54 = bits(io.pmp[3].cfg.a, 0, 0)
node _res_hit_T_55 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_56 = bits(_res_hit_T_55, 2, 0)
node _res_hit_T_57 = not(_res_hit_T_56)
node _res_hit_msbsLess_T_48 = shr(io.addr, 3)
node _res_hit_msbsLess_T_49 = shl(io.pmp[2].addr, 2)
node _res_hit_msbsLess_T_50 = not(_res_hit_msbsLess_T_49)
node _res_hit_msbsLess_T_51 = or(_res_hit_msbsLess_T_50, UInt<2>(0h3))
node _res_hit_msbsLess_T_52 = not(_res_hit_msbsLess_T_51)
node _res_hit_msbsLess_T_53 = shr(_res_hit_msbsLess_T_52, 3)
node res_hit_msbsLess_8 = lt(_res_hit_msbsLess_T_48, _res_hit_msbsLess_T_53)
node _res_hit_msbsEqual_T_56 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_57 = shl(io.pmp[2].addr, 2)
node _res_hit_msbsEqual_T_58 = not(_res_hit_msbsEqual_T_57)
node _res_hit_msbsEqual_T_59 = or(_res_hit_msbsEqual_T_58, UInt<2>(0h3))
node _res_hit_msbsEqual_T_60 = not(_res_hit_msbsEqual_T_59)
node _res_hit_msbsEqual_T_61 = shr(_res_hit_msbsEqual_T_60, 3)
node _res_hit_msbsEqual_T_62 = xor(_res_hit_msbsEqual_T_56, _res_hit_msbsEqual_T_61)
node res_hit_msbsEqual_8 = eq(_res_hit_msbsEqual_T_62, UInt<1>(0h0))
node _res_hit_lsbsLess_T_56 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_57 = or(_res_hit_lsbsLess_T_56, _res_hit_T_57)
node _res_hit_lsbsLess_T_58 = shl(io.pmp[2].addr, 2)
node _res_hit_lsbsLess_T_59 = not(_res_hit_lsbsLess_T_58)
node _res_hit_lsbsLess_T_60 = or(_res_hit_lsbsLess_T_59, UInt<2>(0h3))
node _res_hit_lsbsLess_T_61 = not(_res_hit_lsbsLess_T_60)
node _res_hit_lsbsLess_T_62 = bits(_res_hit_lsbsLess_T_61, 2, 0)
node res_hit_lsbsLess_8 = lt(_res_hit_lsbsLess_T_57, _res_hit_lsbsLess_T_62)
node _res_hit_T_58 = and(res_hit_msbsEqual_8, res_hit_lsbsLess_8)
node _res_hit_T_59 = or(res_hit_msbsLess_8, _res_hit_T_58)
node _res_hit_T_60 = eq(_res_hit_T_59, UInt<1>(0h0))
node _res_hit_msbsLess_T_54 = shr(io.addr, 3)
node _res_hit_msbsLess_T_55 = shl(io.pmp[3].addr, 2)
node _res_hit_msbsLess_T_56 = not(_res_hit_msbsLess_T_55)
node _res_hit_msbsLess_T_57 = or(_res_hit_msbsLess_T_56, UInt<2>(0h3))
node _res_hit_msbsLess_T_58 = not(_res_hit_msbsLess_T_57)
node _res_hit_msbsLess_T_59 = shr(_res_hit_msbsLess_T_58, 3)
node res_hit_msbsLess_9 = lt(_res_hit_msbsLess_T_54, _res_hit_msbsLess_T_59)
node _res_hit_msbsEqual_T_63 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_64 = shl(io.pmp[3].addr, 2)
node _res_hit_msbsEqual_T_65 = not(_res_hit_msbsEqual_T_64)
node _res_hit_msbsEqual_T_66 = or(_res_hit_msbsEqual_T_65, UInt<2>(0h3))
node _res_hit_msbsEqual_T_67 = not(_res_hit_msbsEqual_T_66)
node _res_hit_msbsEqual_T_68 = shr(_res_hit_msbsEqual_T_67, 3)
node _res_hit_msbsEqual_T_69 = xor(_res_hit_msbsEqual_T_63, _res_hit_msbsEqual_T_68)
node res_hit_msbsEqual_9 = eq(_res_hit_msbsEqual_T_69, UInt<1>(0h0))
node _res_hit_lsbsLess_T_63 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_64 = or(_res_hit_lsbsLess_T_63, UInt<1>(0h0))
node _res_hit_lsbsLess_T_65 = shl(io.pmp[3].addr, 2)
node _res_hit_lsbsLess_T_66 = not(_res_hit_lsbsLess_T_65)
node _res_hit_lsbsLess_T_67 = or(_res_hit_lsbsLess_T_66, UInt<2>(0h3))
node _res_hit_lsbsLess_T_68 = not(_res_hit_lsbsLess_T_67)
node _res_hit_lsbsLess_T_69 = bits(_res_hit_lsbsLess_T_68, 2, 0)
node res_hit_lsbsLess_9 = lt(_res_hit_lsbsLess_T_64, _res_hit_lsbsLess_T_69)
node _res_hit_T_61 = and(res_hit_msbsEqual_9, res_hit_lsbsLess_9)
node _res_hit_T_62 = or(res_hit_msbsLess_9, _res_hit_T_61)
node _res_hit_T_63 = and(_res_hit_T_60, _res_hit_T_62)
node _res_hit_T_64 = and(_res_hit_T_54, _res_hit_T_63)
node res_hit_4 = mux(_res_hit_T_52, _res_hit_T_53, _res_hit_T_64)
node _res_ignore_T_4 = eq(io.pmp[3].cfg.l, UInt<1>(0h0))
node res_ignore_4 = and(default, _res_ignore_T_4)
node _res_aligned_lsbMask_T_8 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_9 = bits(_res_aligned_lsbMask_T_8, 2, 0)
node res_aligned_lsbMask_4 = not(_res_aligned_lsbMask_T_9)
node _res_aligned_straddlesLowerBound_T_68 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_69 = shl(io.pmp[2].addr, 2)
node _res_aligned_straddlesLowerBound_T_70 = not(_res_aligned_straddlesLowerBound_T_69)
node _res_aligned_straddlesLowerBound_T_71 = or(_res_aligned_straddlesLowerBound_T_70, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_72 = not(_res_aligned_straddlesLowerBound_T_71)
node _res_aligned_straddlesLowerBound_T_73 = shr(_res_aligned_straddlesLowerBound_T_72, 3)
node _res_aligned_straddlesLowerBound_T_74 = xor(_res_aligned_straddlesLowerBound_T_68, _res_aligned_straddlesLowerBound_T_73)
node _res_aligned_straddlesLowerBound_T_75 = eq(_res_aligned_straddlesLowerBound_T_74, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_76 = shl(io.pmp[2].addr, 2)
node _res_aligned_straddlesLowerBound_T_77 = not(_res_aligned_straddlesLowerBound_T_76)
node _res_aligned_straddlesLowerBound_T_78 = or(_res_aligned_straddlesLowerBound_T_77, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_79 = not(_res_aligned_straddlesLowerBound_T_78)
node _res_aligned_straddlesLowerBound_T_80 = bits(_res_aligned_straddlesLowerBound_T_79, 2, 0)
node _res_aligned_straddlesLowerBound_T_81 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_82 = not(_res_aligned_straddlesLowerBound_T_81)
node _res_aligned_straddlesLowerBound_T_83 = and(_res_aligned_straddlesLowerBound_T_80, _res_aligned_straddlesLowerBound_T_82)
node _res_aligned_straddlesLowerBound_T_84 = neq(_res_aligned_straddlesLowerBound_T_83, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_4 = and(_res_aligned_straddlesLowerBound_T_75, _res_aligned_straddlesLowerBound_T_84)
node _res_aligned_straddlesUpperBound_T_68 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_69 = shl(io.pmp[3].addr, 2)
node _res_aligned_straddlesUpperBound_T_70 = not(_res_aligned_straddlesUpperBound_T_69)
node _res_aligned_straddlesUpperBound_T_71 = or(_res_aligned_straddlesUpperBound_T_70, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_72 = not(_res_aligned_straddlesUpperBound_T_71)
node _res_aligned_straddlesUpperBound_T_73 = shr(_res_aligned_straddlesUpperBound_T_72, 3)
node _res_aligned_straddlesUpperBound_T_74 = xor(_res_aligned_straddlesUpperBound_T_68, _res_aligned_straddlesUpperBound_T_73)
node _res_aligned_straddlesUpperBound_T_75 = eq(_res_aligned_straddlesUpperBound_T_74, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_76 = shl(io.pmp[3].addr, 2)
node _res_aligned_straddlesUpperBound_T_77 = not(_res_aligned_straddlesUpperBound_T_76)
node _res_aligned_straddlesUpperBound_T_78 = or(_res_aligned_straddlesUpperBound_T_77, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_79 = not(_res_aligned_straddlesUpperBound_T_78)
node _res_aligned_straddlesUpperBound_T_80 = bits(_res_aligned_straddlesUpperBound_T_79, 2, 0)
node _res_aligned_straddlesUpperBound_T_81 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_82 = or(_res_aligned_straddlesUpperBound_T_81, res_aligned_lsbMask_4)
node _res_aligned_straddlesUpperBound_T_83 = and(_res_aligned_straddlesUpperBound_T_80, _res_aligned_straddlesUpperBound_T_82)
node _res_aligned_straddlesUpperBound_T_84 = neq(_res_aligned_straddlesUpperBound_T_83, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_4 = and(_res_aligned_straddlesUpperBound_T_75, _res_aligned_straddlesUpperBound_T_84)
node _res_aligned_rangeAligned_T_4 = or(res_aligned_straddlesLowerBound_4, res_aligned_straddlesUpperBound_4)
node res_aligned_rangeAligned_4 = eq(_res_aligned_rangeAligned_T_4, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_12 = bits(io.pmp[3].mask, 2, 0)
node _res_aligned_pow2Aligned_T_13 = not(_res_aligned_pow2Aligned_T_12)
node _res_aligned_pow2Aligned_T_14 = and(res_aligned_lsbMask_4, _res_aligned_pow2Aligned_T_13)
node res_aligned_pow2Aligned_4 = eq(_res_aligned_pow2Aligned_T_14, UInt<1>(0h0))
node _res_aligned_T_4 = bits(io.pmp[3].cfg.a, 1, 1)
node res_aligned_4 = mux(_res_aligned_T_4, res_aligned_pow2Aligned_4, res_aligned_rangeAligned_4)
node _res_T_180 = eq(io.pmp[3].cfg.a, UInt<1>(0h0))
node _res_T_181 = eq(io.pmp[3].cfg.a, UInt<1>(0h1))
node _res_T_182 = eq(io.pmp[3].cfg.a, UInt<2>(0h2))
node _res_T_183 = eq(io.pmp[3].cfg.a, UInt<2>(0h3))
node _res_T_184 = eq(io.pmp[3].cfg.l, UInt<1>(0h1))
node res_hi_24 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_185 = cat(res_hi_24, io.pmp[3].cfg.r)
node _res_T_186 = eq(_res_T_185, UInt<1>(0h0))
node res_hi_25 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_187 = cat(res_hi_25, io.pmp[3].cfg.r)
node _res_T_188 = eq(_res_T_187, UInt<1>(0h1))
node res_hi_26 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_189 = cat(res_hi_26, io.pmp[3].cfg.r)
node _res_T_190 = eq(_res_T_189, UInt<2>(0h3))
node res_hi_27 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_191 = cat(res_hi_27, io.pmp[3].cfg.r)
node _res_T_192 = eq(_res_T_191, UInt<3>(0h4))
node res_hi_28 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_193 = cat(res_hi_28, io.pmp[3].cfg.r)
node _res_T_194 = eq(_res_T_193, UInt<3>(0h5))
node res_hi_29 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_195 = cat(res_hi_29, io.pmp[3].cfg.r)
node _res_T_196 = eq(_res_T_195, UInt<3>(0h7))
node _res_T_197 = eq(res_ignore_4, UInt<1>(0h0))
node _res_T_198 = and(_res_T_197, res_hit_4)
node _res_T_199 = and(_res_T_198, res_aligned_4)
node _res_T_200 = eq(io.pmp[3].cfg.a, UInt<1>(0h1))
node _res_T_201 = and(_res_T_199, _res_T_200)
node _res_T_202 = and(io.pmp[3].cfg.l, res_hit_4)
node _res_T_203 = and(_res_T_202, res_aligned_4)
node _res_T_204 = eq(io.pmp[3].cfg.a, UInt<1>(0h1))
node _res_T_205 = and(_res_T_203, _res_T_204)
node _res_T_206 = eq(res_ignore_4, UInt<1>(0h0))
node _res_T_207 = and(_res_T_206, res_hit_4)
node _res_T_208 = and(_res_T_207, res_aligned_4)
node _res_T_209 = eq(io.pmp[3].cfg.a, UInt<2>(0h2))
node _res_T_210 = and(_res_T_208, _res_T_209)
node _res_T_211 = and(io.pmp[3].cfg.l, res_hit_4)
node _res_T_212 = and(_res_T_211, res_aligned_4)
node _res_T_213 = eq(io.pmp[3].cfg.a, UInt<2>(0h2))
node _res_T_214 = and(_res_T_212, _res_T_213)
node _res_T_215 = eq(res_ignore_4, UInt<1>(0h0))
node _res_T_216 = and(_res_T_215, res_hit_4)
node _res_T_217 = and(_res_T_216, res_aligned_4)
node _res_T_218 = eq(io.pmp[3].cfg.a, UInt<2>(0h3))
node _res_T_219 = and(_res_T_217, _res_T_218)
node _res_T_220 = and(io.pmp[3].cfg.l, res_hit_4)
node _res_T_221 = and(_res_T_220, res_aligned_4)
node _res_T_222 = eq(io.pmp[3].cfg.a, UInt<2>(0h3))
node _res_T_223 = and(_res_T_221, _res_T_222)
wire res_cur_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_4, io.pmp[3]
node _res_cur_cfg_r_T_8 = or(io.pmp[3].cfg.r, res_ignore_4)
node _res_cur_cfg_r_T_9 = and(res_aligned_4, _res_cur_cfg_r_T_8)
connect res_cur_4.cfg.r, _res_cur_cfg_r_T_9
node _res_cur_cfg_w_T_8 = or(io.pmp[3].cfg.w, res_ignore_4)
node _res_cur_cfg_w_T_9 = and(res_aligned_4, _res_cur_cfg_w_T_8)
connect res_cur_4.cfg.w, _res_cur_cfg_w_T_9
node _res_cur_cfg_x_T_8 = or(io.pmp[3].cfg.x, res_ignore_4)
node _res_cur_cfg_x_T_9 = and(res_aligned_4, _res_cur_cfg_x_T_8)
connect res_cur_4.cfg.x, _res_cur_cfg_x_T_9
node _res_T_224 = mux(res_hit_4, res_cur_4, _res_T_179)
node _res_hit_T_65 = bits(io.pmp[2].cfg.a, 1, 1)
node _res_hit_lsbMask_T_15 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_16 = bits(_res_hit_lsbMask_T_15, 2, 0)
node _res_hit_lsbMask_T_17 = not(_res_hit_lsbMask_T_16)
node res_hit_lsbMask_5 = or(io.pmp[2].mask, _res_hit_lsbMask_T_17)
node _res_hit_msbMatch_T_50 = shr(io.addr, 3)
node _res_hit_msbMatch_T_51 = shl(io.pmp[2].addr, 2)
node _res_hit_msbMatch_T_52 = not(_res_hit_msbMatch_T_51)
node _res_hit_msbMatch_T_53 = or(_res_hit_msbMatch_T_52, UInt<2>(0h3))
node _res_hit_msbMatch_T_54 = not(_res_hit_msbMatch_T_53)
node _res_hit_msbMatch_T_55 = shr(_res_hit_msbMatch_T_54, 3)
node _res_hit_msbMatch_T_56 = shr(io.pmp[2].mask, 3)
node _res_hit_msbMatch_T_57 = xor(_res_hit_msbMatch_T_50, _res_hit_msbMatch_T_55)
node _res_hit_msbMatch_T_58 = not(_res_hit_msbMatch_T_56)
node _res_hit_msbMatch_T_59 = and(_res_hit_msbMatch_T_57, _res_hit_msbMatch_T_58)
node res_hit_msbMatch_5 = eq(_res_hit_msbMatch_T_59, UInt<1>(0h0))
node _res_hit_lsbMatch_T_50 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_51 = shl(io.pmp[2].addr, 2)
node _res_hit_lsbMatch_T_52 = not(_res_hit_lsbMatch_T_51)
node _res_hit_lsbMatch_T_53 = or(_res_hit_lsbMatch_T_52, UInt<2>(0h3))
node _res_hit_lsbMatch_T_54 = not(_res_hit_lsbMatch_T_53)
node _res_hit_lsbMatch_T_55 = bits(_res_hit_lsbMatch_T_54, 2, 0)
node _res_hit_lsbMatch_T_56 = bits(res_hit_lsbMask_5, 2, 0)
node _res_hit_lsbMatch_T_57 = xor(_res_hit_lsbMatch_T_50, _res_hit_lsbMatch_T_55)
node _res_hit_lsbMatch_T_58 = not(_res_hit_lsbMatch_T_56)
node _res_hit_lsbMatch_T_59 = and(_res_hit_lsbMatch_T_57, _res_hit_lsbMatch_T_58)
node res_hit_lsbMatch_5 = eq(_res_hit_lsbMatch_T_59, UInt<1>(0h0))
node _res_hit_T_66 = and(res_hit_msbMatch_5, res_hit_lsbMatch_5)
node _res_hit_T_67 = bits(io.pmp[2].cfg.a, 0, 0)
node _res_hit_T_68 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_69 = bits(_res_hit_T_68, 2, 0)
node _res_hit_T_70 = not(_res_hit_T_69)
node _res_hit_msbsLess_T_60 = shr(io.addr, 3)
node _res_hit_msbsLess_T_61 = shl(io.pmp[1].addr, 2)
node _res_hit_msbsLess_T_62 = not(_res_hit_msbsLess_T_61)
node _res_hit_msbsLess_T_63 = or(_res_hit_msbsLess_T_62, UInt<2>(0h3))
node _res_hit_msbsLess_T_64 = not(_res_hit_msbsLess_T_63)
node _res_hit_msbsLess_T_65 = shr(_res_hit_msbsLess_T_64, 3)
node res_hit_msbsLess_10 = lt(_res_hit_msbsLess_T_60, _res_hit_msbsLess_T_65)
node _res_hit_msbsEqual_T_70 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_71 = shl(io.pmp[1].addr, 2)
node _res_hit_msbsEqual_T_72 = not(_res_hit_msbsEqual_T_71)
node _res_hit_msbsEqual_T_73 = or(_res_hit_msbsEqual_T_72, UInt<2>(0h3))
node _res_hit_msbsEqual_T_74 = not(_res_hit_msbsEqual_T_73)
node _res_hit_msbsEqual_T_75 = shr(_res_hit_msbsEqual_T_74, 3)
node _res_hit_msbsEqual_T_76 = xor(_res_hit_msbsEqual_T_70, _res_hit_msbsEqual_T_75)
node res_hit_msbsEqual_10 = eq(_res_hit_msbsEqual_T_76, UInt<1>(0h0))
node _res_hit_lsbsLess_T_70 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_71 = or(_res_hit_lsbsLess_T_70, _res_hit_T_70)
node _res_hit_lsbsLess_T_72 = shl(io.pmp[1].addr, 2)
node _res_hit_lsbsLess_T_73 = not(_res_hit_lsbsLess_T_72)
node _res_hit_lsbsLess_T_74 = or(_res_hit_lsbsLess_T_73, UInt<2>(0h3))
node _res_hit_lsbsLess_T_75 = not(_res_hit_lsbsLess_T_74)
node _res_hit_lsbsLess_T_76 = bits(_res_hit_lsbsLess_T_75, 2, 0)
node res_hit_lsbsLess_10 = lt(_res_hit_lsbsLess_T_71, _res_hit_lsbsLess_T_76)
node _res_hit_T_71 = and(res_hit_msbsEqual_10, res_hit_lsbsLess_10)
node _res_hit_T_72 = or(res_hit_msbsLess_10, _res_hit_T_71)
node _res_hit_T_73 = eq(_res_hit_T_72, UInt<1>(0h0))
node _res_hit_msbsLess_T_66 = shr(io.addr, 3)
node _res_hit_msbsLess_T_67 = shl(io.pmp[2].addr, 2)
node _res_hit_msbsLess_T_68 = not(_res_hit_msbsLess_T_67)
node _res_hit_msbsLess_T_69 = or(_res_hit_msbsLess_T_68, UInt<2>(0h3))
node _res_hit_msbsLess_T_70 = not(_res_hit_msbsLess_T_69)
node _res_hit_msbsLess_T_71 = shr(_res_hit_msbsLess_T_70, 3)
node res_hit_msbsLess_11 = lt(_res_hit_msbsLess_T_66, _res_hit_msbsLess_T_71)
node _res_hit_msbsEqual_T_77 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_78 = shl(io.pmp[2].addr, 2)
node _res_hit_msbsEqual_T_79 = not(_res_hit_msbsEqual_T_78)
node _res_hit_msbsEqual_T_80 = or(_res_hit_msbsEqual_T_79, UInt<2>(0h3))
node _res_hit_msbsEqual_T_81 = not(_res_hit_msbsEqual_T_80)
node _res_hit_msbsEqual_T_82 = shr(_res_hit_msbsEqual_T_81, 3)
node _res_hit_msbsEqual_T_83 = xor(_res_hit_msbsEqual_T_77, _res_hit_msbsEqual_T_82)
node res_hit_msbsEqual_11 = eq(_res_hit_msbsEqual_T_83, UInt<1>(0h0))
node _res_hit_lsbsLess_T_77 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_78 = or(_res_hit_lsbsLess_T_77, UInt<1>(0h0))
node _res_hit_lsbsLess_T_79 = shl(io.pmp[2].addr, 2)
node _res_hit_lsbsLess_T_80 = not(_res_hit_lsbsLess_T_79)
node _res_hit_lsbsLess_T_81 = or(_res_hit_lsbsLess_T_80, UInt<2>(0h3))
node _res_hit_lsbsLess_T_82 = not(_res_hit_lsbsLess_T_81)
node _res_hit_lsbsLess_T_83 = bits(_res_hit_lsbsLess_T_82, 2, 0)
node res_hit_lsbsLess_11 = lt(_res_hit_lsbsLess_T_78, _res_hit_lsbsLess_T_83)
node _res_hit_T_74 = and(res_hit_msbsEqual_11, res_hit_lsbsLess_11)
node _res_hit_T_75 = or(res_hit_msbsLess_11, _res_hit_T_74)
node _res_hit_T_76 = and(_res_hit_T_73, _res_hit_T_75)
node _res_hit_T_77 = and(_res_hit_T_67, _res_hit_T_76)
node res_hit_5 = mux(_res_hit_T_65, _res_hit_T_66, _res_hit_T_77)
node _res_ignore_T_5 = eq(io.pmp[2].cfg.l, UInt<1>(0h0))
node res_ignore_5 = and(default, _res_ignore_T_5)
node _res_aligned_lsbMask_T_10 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_11 = bits(_res_aligned_lsbMask_T_10, 2, 0)
node res_aligned_lsbMask_5 = not(_res_aligned_lsbMask_T_11)
node _res_aligned_straddlesLowerBound_T_85 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_86 = shl(io.pmp[1].addr, 2)
node _res_aligned_straddlesLowerBound_T_87 = not(_res_aligned_straddlesLowerBound_T_86)
node _res_aligned_straddlesLowerBound_T_88 = or(_res_aligned_straddlesLowerBound_T_87, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_89 = not(_res_aligned_straddlesLowerBound_T_88)
node _res_aligned_straddlesLowerBound_T_90 = shr(_res_aligned_straddlesLowerBound_T_89, 3)
node _res_aligned_straddlesLowerBound_T_91 = xor(_res_aligned_straddlesLowerBound_T_85, _res_aligned_straddlesLowerBound_T_90)
node _res_aligned_straddlesLowerBound_T_92 = eq(_res_aligned_straddlesLowerBound_T_91, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_93 = shl(io.pmp[1].addr, 2)
node _res_aligned_straddlesLowerBound_T_94 = not(_res_aligned_straddlesLowerBound_T_93)
node _res_aligned_straddlesLowerBound_T_95 = or(_res_aligned_straddlesLowerBound_T_94, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_96 = not(_res_aligned_straddlesLowerBound_T_95)
node _res_aligned_straddlesLowerBound_T_97 = bits(_res_aligned_straddlesLowerBound_T_96, 2, 0)
node _res_aligned_straddlesLowerBound_T_98 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_99 = not(_res_aligned_straddlesLowerBound_T_98)
node _res_aligned_straddlesLowerBound_T_100 = and(_res_aligned_straddlesLowerBound_T_97, _res_aligned_straddlesLowerBound_T_99)
node _res_aligned_straddlesLowerBound_T_101 = neq(_res_aligned_straddlesLowerBound_T_100, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_5 = and(_res_aligned_straddlesLowerBound_T_92, _res_aligned_straddlesLowerBound_T_101)
node _res_aligned_straddlesUpperBound_T_85 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_86 = shl(io.pmp[2].addr, 2)
node _res_aligned_straddlesUpperBound_T_87 = not(_res_aligned_straddlesUpperBound_T_86)
node _res_aligned_straddlesUpperBound_T_88 = or(_res_aligned_straddlesUpperBound_T_87, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_89 = not(_res_aligned_straddlesUpperBound_T_88)
node _res_aligned_straddlesUpperBound_T_90 = shr(_res_aligned_straddlesUpperBound_T_89, 3)
node _res_aligned_straddlesUpperBound_T_91 = xor(_res_aligned_straddlesUpperBound_T_85, _res_aligned_straddlesUpperBound_T_90)
node _res_aligned_straddlesUpperBound_T_92 = eq(_res_aligned_straddlesUpperBound_T_91, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_93 = shl(io.pmp[2].addr, 2)
node _res_aligned_straddlesUpperBound_T_94 = not(_res_aligned_straddlesUpperBound_T_93)
node _res_aligned_straddlesUpperBound_T_95 = or(_res_aligned_straddlesUpperBound_T_94, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_96 = not(_res_aligned_straddlesUpperBound_T_95)
node _res_aligned_straddlesUpperBound_T_97 = bits(_res_aligned_straddlesUpperBound_T_96, 2, 0)
node _res_aligned_straddlesUpperBound_T_98 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_99 = or(_res_aligned_straddlesUpperBound_T_98, res_aligned_lsbMask_5)
node _res_aligned_straddlesUpperBound_T_100 = and(_res_aligned_straddlesUpperBound_T_97, _res_aligned_straddlesUpperBound_T_99)
node _res_aligned_straddlesUpperBound_T_101 = neq(_res_aligned_straddlesUpperBound_T_100, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_5 = and(_res_aligned_straddlesUpperBound_T_92, _res_aligned_straddlesUpperBound_T_101)
node _res_aligned_rangeAligned_T_5 = or(res_aligned_straddlesLowerBound_5, res_aligned_straddlesUpperBound_5)
node res_aligned_rangeAligned_5 = eq(_res_aligned_rangeAligned_T_5, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_15 = bits(io.pmp[2].mask, 2, 0)
node _res_aligned_pow2Aligned_T_16 = not(_res_aligned_pow2Aligned_T_15)
node _res_aligned_pow2Aligned_T_17 = and(res_aligned_lsbMask_5, _res_aligned_pow2Aligned_T_16)
node res_aligned_pow2Aligned_5 = eq(_res_aligned_pow2Aligned_T_17, UInt<1>(0h0))
node _res_aligned_T_5 = bits(io.pmp[2].cfg.a, 1, 1)
node res_aligned_5 = mux(_res_aligned_T_5, res_aligned_pow2Aligned_5, res_aligned_rangeAligned_5)
node _res_T_225 = eq(io.pmp[2].cfg.a, UInt<1>(0h0))
node _res_T_226 = eq(io.pmp[2].cfg.a, UInt<1>(0h1))
node _res_T_227 = eq(io.pmp[2].cfg.a, UInt<2>(0h2))
node _res_T_228 = eq(io.pmp[2].cfg.a, UInt<2>(0h3))
node _res_T_229 = eq(io.pmp[2].cfg.l, UInt<1>(0h1))
node res_hi_30 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_230 = cat(res_hi_30, io.pmp[2].cfg.r)
node _res_T_231 = eq(_res_T_230, UInt<1>(0h0))
node res_hi_31 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_232 = cat(res_hi_31, io.pmp[2].cfg.r)
node _res_T_233 = eq(_res_T_232, UInt<1>(0h1))
node res_hi_32 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_234 = cat(res_hi_32, io.pmp[2].cfg.r)
node _res_T_235 = eq(_res_T_234, UInt<2>(0h3))
node res_hi_33 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_236 = cat(res_hi_33, io.pmp[2].cfg.r)
node _res_T_237 = eq(_res_T_236, UInt<3>(0h4))
node res_hi_34 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_238 = cat(res_hi_34, io.pmp[2].cfg.r)
node _res_T_239 = eq(_res_T_238, UInt<3>(0h5))
node res_hi_35 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_240 = cat(res_hi_35, io.pmp[2].cfg.r)
node _res_T_241 = eq(_res_T_240, UInt<3>(0h7))
node _res_T_242 = eq(res_ignore_5, UInt<1>(0h0))
node _res_T_243 = and(_res_T_242, res_hit_5)
node _res_T_244 = and(_res_T_243, res_aligned_5)
node _res_T_245 = eq(io.pmp[2].cfg.a, UInt<1>(0h1))
node _res_T_246 = and(_res_T_244, _res_T_245)
node _res_T_247 = and(io.pmp[2].cfg.l, res_hit_5)
node _res_T_248 = and(_res_T_247, res_aligned_5)
node _res_T_249 = eq(io.pmp[2].cfg.a, UInt<1>(0h1))
node _res_T_250 = and(_res_T_248, _res_T_249)
node _res_T_251 = eq(res_ignore_5, UInt<1>(0h0))
node _res_T_252 = and(_res_T_251, res_hit_5)
node _res_T_253 = and(_res_T_252, res_aligned_5)
node _res_T_254 = eq(io.pmp[2].cfg.a, UInt<2>(0h2))
node _res_T_255 = and(_res_T_253, _res_T_254)
node _res_T_256 = and(io.pmp[2].cfg.l, res_hit_5)
node _res_T_257 = and(_res_T_256, res_aligned_5)
node _res_T_258 = eq(io.pmp[2].cfg.a, UInt<2>(0h2))
node _res_T_259 = and(_res_T_257, _res_T_258)
node _res_T_260 = eq(res_ignore_5, UInt<1>(0h0))
node _res_T_261 = and(_res_T_260, res_hit_5)
node _res_T_262 = and(_res_T_261, res_aligned_5)
node _res_T_263 = eq(io.pmp[2].cfg.a, UInt<2>(0h3))
node _res_T_264 = and(_res_T_262, _res_T_263)
node _res_T_265 = and(io.pmp[2].cfg.l, res_hit_5)
node _res_T_266 = and(_res_T_265, res_aligned_5)
node _res_T_267 = eq(io.pmp[2].cfg.a, UInt<2>(0h3))
node _res_T_268 = and(_res_T_266, _res_T_267)
wire res_cur_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_5, io.pmp[2]
node _res_cur_cfg_r_T_10 = or(io.pmp[2].cfg.r, res_ignore_5)
node _res_cur_cfg_r_T_11 = and(res_aligned_5, _res_cur_cfg_r_T_10)
connect res_cur_5.cfg.r, _res_cur_cfg_r_T_11
node _res_cur_cfg_w_T_10 = or(io.pmp[2].cfg.w, res_ignore_5)
node _res_cur_cfg_w_T_11 = and(res_aligned_5, _res_cur_cfg_w_T_10)
connect res_cur_5.cfg.w, _res_cur_cfg_w_T_11
node _res_cur_cfg_x_T_10 = or(io.pmp[2].cfg.x, res_ignore_5)
node _res_cur_cfg_x_T_11 = and(res_aligned_5, _res_cur_cfg_x_T_10)
connect res_cur_5.cfg.x, _res_cur_cfg_x_T_11
node _res_T_269 = mux(res_hit_5, res_cur_5, _res_T_224)
node _res_hit_T_78 = bits(io.pmp[1].cfg.a, 1, 1)
node _res_hit_lsbMask_T_18 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_19 = bits(_res_hit_lsbMask_T_18, 2, 0)
node _res_hit_lsbMask_T_20 = not(_res_hit_lsbMask_T_19)
node res_hit_lsbMask_6 = or(io.pmp[1].mask, _res_hit_lsbMask_T_20)
node _res_hit_msbMatch_T_60 = shr(io.addr, 3)
node _res_hit_msbMatch_T_61 = shl(io.pmp[1].addr, 2)
node _res_hit_msbMatch_T_62 = not(_res_hit_msbMatch_T_61)
node _res_hit_msbMatch_T_63 = or(_res_hit_msbMatch_T_62, UInt<2>(0h3))
node _res_hit_msbMatch_T_64 = not(_res_hit_msbMatch_T_63)
node _res_hit_msbMatch_T_65 = shr(_res_hit_msbMatch_T_64, 3)
node _res_hit_msbMatch_T_66 = shr(io.pmp[1].mask, 3)
node _res_hit_msbMatch_T_67 = xor(_res_hit_msbMatch_T_60, _res_hit_msbMatch_T_65)
node _res_hit_msbMatch_T_68 = not(_res_hit_msbMatch_T_66)
node _res_hit_msbMatch_T_69 = and(_res_hit_msbMatch_T_67, _res_hit_msbMatch_T_68)
node res_hit_msbMatch_6 = eq(_res_hit_msbMatch_T_69, UInt<1>(0h0))
node _res_hit_lsbMatch_T_60 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_61 = shl(io.pmp[1].addr, 2)
node _res_hit_lsbMatch_T_62 = not(_res_hit_lsbMatch_T_61)
node _res_hit_lsbMatch_T_63 = or(_res_hit_lsbMatch_T_62, UInt<2>(0h3))
node _res_hit_lsbMatch_T_64 = not(_res_hit_lsbMatch_T_63)
node _res_hit_lsbMatch_T_65 = bits(_res_hit_lsbMatch_T_64, 2, 0)
node _res_hit_lsbMatch_T_66 = bits(res_hit_lsbMask_6, 2, 0)
node _res_hit_lsbMatch_T_67 = xor(_res_hit_lsbMatch_T_60, _res_hit_lsbMatch_T_65)
node _res_hit_lsbMatch_T_68 = not(_res_hit_lsbMatch_T_66)
node _res_hit_lsbMatch_T_69 = and(_res_hit_lsbMatch_T_67, _res_hit_lsbMatch_T_68)
node res_hit_lsbMatch_6 = eq(_res_hit_lsbMatch_T_69, UInt<1>(0h0))
node _res_hit_T_79 = and(res_hit_msbMatch_6, res_hit_lsbMatch_6)
node _res_hit_T_80 = bits(io.pmp[1].cfg.a, 0, 0)
node _res_hit_T_81 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_82 = bits(_res_hit_T_81, 2, 0)
node _res_hit_T_83 = not(_res_hit_T_82)
node _res_hit_msbsLess_T_72 = shr(io.addr, 3)
node _res_hit_msbsLess_T_73 = shl(io.pmp[0].addr, 2)
node _res_hit_msbsLess_T_74 = not(_res_hit_msbsLess_T_73)
node _res_hit_msbsLess_T_75 = or(_res_hit_msbsLess_T_74, UInt<2>(0h3))
node _res_hit_msbsLess_T_76 = not(_res_hit_msbsLess_T_75)
node _res_hit_msbsLess_T_77 = shr(_res_hit_msbsLess_T_76, 3)
node res_hit_msbsLess_12 = lt(_res_hit_msbsLess_T_72, _res_hit_msbsLess_T_77)
node _res_hit_msbsEqual_T_84 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_85 = shl(io.pmp[0].addr, 2)
node _res_hit_msbsEqual_T_86 = not(_res_hit_msbsEqual_T_85)
node _res_hit_msbsEqual_T_87 = or(_res_hit_msbsEqual_T_86, UInt<2>(0h3))
node _res_hit_msbsEqual_T_88 = not(_res_hit_msbsEqual_T_87)
node _res_hit_msbsEqual_T_89 = shr(_res_hit_msbsEqual_T_88, 3)
node _res_hit_msbsEqual_T_90 = xor(_res_hit_msbsEqual_T_84, _res_hit_msbsEqual_T_89)
node res_hit_msbsEqual_12 = eq(_res_hit_msbsEqual_T_90, UInt<1>(0h0))
node _res_hit_lsbsLess_T_84 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_85 = or(_res_hit_lsbsLess_T_84, _res_hit_T_83)
node _res_hit_lsbsLess_T_86 = shl(io.pmp[0].addr, 2)
node _res_hit_lsbsLess_T_87 = not(_res_hit_lsbsLess_T_86)
node _res_hit_lsbsLess_T_88 = or(_res_hit_lsbsLess_T_87, UInt<2>(0h3))
node _res_hit_lsbsLess_T_89 = not(_res_hit_lsbsLess_T_88)
node _res_hit_lsbsLess_T_90 = bits(_res_hit_lsbsLess_T_89, 2, 0)
node res_hit_lsbsLess_12 = lt(_res_hit_lsbsLess_T_85, _res_hit_lsbsLess_T_90)
node _res_hit_T_84 = and(res_hit_msbsEqual_12, res_hit_lsbsLess_12)
node _res_hit_T_85 = or(res_hit_msbsLess_12, _res_hit_T_84)
node _res_hit_T_86 = eq(_res_hit_T_85, UInt<1>(0h0))
node _res_hit_msbsLess_T_78 = shr(io.addr, 3)
node _res_hit_msbsLess_T_79 = shl(io.pmp[1].addr, 2)
node _res_hit_msbsLess_T_80 = not(_res_hit_msbsLess_T_79)
node _res_hit_msbsLess_T_81 = or(_res_hit_msbsLess_T_80, UInt<2>(0h3))
node _res_hit_msbsLess_T_82 = not(_res_hit_msbsLess_T_81)
node _res_hit_msbsLess_T_83 = shr(_res_hit_msbsLess_T_82, 3)
node res_hit_msbsLess_13 = lt(_res_hit_msbsLess_T_78, _res_hit_msbsLess_T_83)
node _res_hit_msbsEqual_T_91 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_92 = shl(io.pmp[1].addr, 2)
node _res_hit_msbsEqual_T_93 = not(_res_hit_msbsEqual_T_92)
node _res_hit_msbsEqual_T_94 = or(_res_hit_msbsEqual_T_93, UInt<2>(0h3))
node _res_hit_msbsEqual_T_95 = not(_res_hit_msbsEqual_T_94)
node _res_hit_msbsEqual_T_96 = shr(_res_hit_msbsEqual_T_95, 3)
node _res_hit_msbsEqual_T_97 = xor(_res_hit_msbsEqual_T_91, _res_hit_msbsEqual_T_96)
node res_hit_msbsEqual_13 = eq(_res_hit_msbsEqual_T_97, UInt<1>(0h0))
node _res_hit_lsbsLess_T_91 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_92 = or(_res_hit_lsbsLess_T_91, UInt<1>(0h0))
node _res_hit_lsbsLess_T_93 = shl(io.pmp[1].addr, 2)
node _res_hit_lsbsLess_T_94 = not(_res_hit_lsbsLess_T_93)
node _res_hit_lsbsLess_T_95 = or(_res_hit_lsbsLess_T_94, UInt<2>(0h3))
node _res_hit_lsbsLess_T_96 = not(_res_hit_lsbsLess_T_95)
node _res_hit_lsbsLess_T_97 = bits(_res_hit_lsbsLess_T_96, 2, 0)
node res_hit_lsbsLess_13 = lt(_res_hit_lsbsLess_T_92, _res_hit_lsbsLess_T_97)
node _res_hit_T_87 = and(res_hit_msbsEqual_13, res_hit_lsbsLess_13)
node _res_hit_T_88 = or(res_hit_msbsLess_13, _res_hit_T_87)
node _res_hit_T_89 = and(_res_hit_T_86, _res_hit_T_88)
node _res_hit_T_90 = and(_res_hit_T_80, _res_hit_T_89)
node res_hit_6 = mux(_res_hit_T_78, _res_hit_T_79, _res_hit_T_90)
node _res_ignore_T_6 = eq(io.pmp[1].cfg.l, UInt<1>(0h0))
node res_ignore_6 = and(default, _res_ignore_T_6)
node _res_aligned_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_13 = bits(_res_aligned_lsbMask_T_12, 2, 0)
node res_aligned_lsbMask_6 = not(_res_aligned_lsbMask_T_13)
node _res_aligned_straddlesLowerBound_T_102 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_103 = shl(io.pmp[0].addr, 2)
node _res_aligned_straddlesLowerBound_T_104 = not(_res_aligned_straddlesLowerBound_T_103)
node _res_aligned_straddlesLowerBound_T_105 = or(_res_aligned_straddlesLowerBound_T_104, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_106 = not(_res_aligned_straddlesLowerBound_T_105)
node _res_aligned_straddlesLowerBound_T_107 = shr(_res_aligned_straddlesLowerBound_T_106, 3)
node _res_aligned_straddlesLowerBound_T_108 = xor(_res_aligned_straddlesLowerBound_T_102, _res_aligned_straddlesLowerBound_T_107)
node _res_aligned_straddlesLowerBound_T_109 = eq(_res_aligned_straddlesLowerBound_T_108, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_110 = shl(io.pmp[0].addr, 2)
node _res_aligned_straddlesLowerBound_T_111 = not(_res_aligned_straddlesLowerBound_T_110)
node _res_aligned_straddlesLowerBound_T_112 = or(_res_aligned_straddlesLowerBound_T_111, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_113 = not(_res_aligned_straddlesLowerBound_T_112)
node _res_aligned_straddlesLowerBound_T_114 = bits(_res_aligned_straddlesLowerBound_T_113, 2, 0)
node _res_aligned_straddlesLowerBound_T_115 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_116 = not(_res_aligned_straddlesLowerBound_T_115)
node _res_aligned_straddlesLowerBound_T_117 = and(_res_aligned_straddlesLowerBound_T_114, _res_aligned_straddlesLowerBound_T_116)
node _res_aligned_straddlesLowerBound_T_118 = neq(_res_aligned_straddlesLowerBound_T_117, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_6 = and(_res_aligned_straddlesLowerBound_T_109, _res_aligned_straddlesLowerBound_T_118)
node _res_aligned_straddlesUpperBound_T_102 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_103 = shl(io.pmp[1].addr, 2)
node _res_aligned_straddlesUpperBound_T_104 = not(_res_aligned_straddlesUpperBound_T_103)
node _res_aligned_straddlesUpperBound_T_105 = or(_res_aligned_straddlesUpperBound_T_104, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_106 = not(_res_aligned_straddlesUpperBound_T_105)
node _res_aligned_straddlesUpperBound_T_107 = shr(_res_aligned_straddlesUpperBound_T_106, 3)
node _res_aligned_straddlesUpperBound_T_108 = xor(_res_aligned_straddlesUpperBound_T_102, _res_aligned_straddlesUpperBound_T_107)
node _res_aligned_straddlesUpperBound_T_109 = eq(_res_aligned_straddlesUpperBound_T_108, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_110 = shl(io.pmp[1].addr, 2)
node _res_aligned_straddlesUpperBound_T_111 = not(_res_aligned_straddlesUpperBound_T_110)
node _res_aligned_straddlesUpperBound_T_112 = or(_res_aligned_straddlesUpperBound_T_111, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_113 = not(_res_aligned_straddlesUpperBound_T_112)
node _res_aligned_straddlesUpperBound_T_114 = bits(_res_aligned_straddlesUpperBound_T_113, 2, 0)
node _res_aligned_straddlesUpperBound_T_115 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_116 = or(_res_aligned_straddlesUpperBound_T_115, res_aligned_lsbMask_6)
node _res_aligned_straddlesUpperBound_T_117 = and(_res_aligned_straddlesUpperBound_T_114, _res_aligned_straddlesUpperBound_T_116)
node _res_aligned_straddlesUpperBound_T_118 = neq(_res_aligned_straddlesUpperBound_T_117, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_6 = and(_res_aligned_straddlesUpperBound_T_109, _res_aligned_straddlesUpperBound_T_118)
node _res_aligned_rangeAligned_T_6 = or(res_aligned_straddlesLowerBound_6, res_aligned_straddlesUpperBound_6)
node res_aligned_rangeAligned_6 = eq(_res_aligned_rangeAligned_T_6, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_18 = bits(io.pmp[1].mask, 2, 0)
node _res_aligned_pow2Aligned_T_19 = not(_res_aligned_pow2Aligned_T_18)
node _res_aligned_pow2Aligned_T_20 = and(res_aligned_lsbMask_6, _res_aligned_pow2Aligned_T_19)
node res_aligned_pow2Aligned_6 = eq(_res_aligned_pow2Aligned_T_20, UInt<1>(0h0))
node _res_aligned_T_6 = bits(io.pmp[1].cfg.a, 1, 1)
node res_aligned_6 = mux(_res_aligned_T_6, res_aligned_pow2Aligned_6, res_aligned_rangeAligned_6)
node _res_T_270 = eq(io.pmp[1].cfg.a, UInt<1>(0h0))
node _res_T_271 = eq(io.pmp[1].cfg.a, UInt<1>(0h1))
node _res_T_272 = eq(io.pmp[1].cfg.a, UInt<2>(0h2))
node _res_T_273 = eq(io.pmp[1].cfg.a, UInt<2>(0h3))
node _res_T_274 = eq(io.pmp[1].cfg.l, UInt<1>(0h1))
node res_hi_36 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_275 = cat(res_hi_36, io.pmp[1].cfg.r)
node _res_T_276 = eq(_res_T_275, UInt<1>(0h0))
node res_hi_37 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_277 = cat(res_hi_37, io.pmp[1].cfg.r)
node _res_T_278 = eq(_res_T_277, UInt<1>(0h1))
node res_hi_38 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_279 = cat(res_hi_38, io.pmp[1].cfg.r)
node _res_T_280 = eq(_res_T_279, UInt<2>(0h3))
node res_hi_39 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_281 = cat(res_hi_39, io.pmp[1].cfg.r)
node _res_T_282 = eq(_res_T_281, UInt<3>(0h4))
node res_hi_40 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_283 = cat(res_hi_40, io.pmp[1].cfg.r)
node _res_T_284 = eq(_res_T_283, UInt<3>(0h5))
node res_hi_41 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_285 = cat(res_hi_41, io.pmp[1].cfg.r)
node _res_T_286 = eq(_res_T_285, UInt<3>(0h7))
node _res_T_287 = eq(res_ignore_6, UInt<1>(0h0))
node _res_T_288 = and(_res_T_287, res_hit_6)
node _res_T_289 = and(_res_T_288, res_aligned_6)
node _res_T_290 = eq(io.pmp[1].cfg.a, UInt<1>(0h1))
node _res_T_291 = and(_res_T_289, _res_T_290)
node _res_T_292 = and(io.pmp[1].cfg.l, res_hit_6)
node _res_T_293 = and(_res_T_292, res_aligned_6)
node _res_T_294 = eq(io.pmp[1].cfg.a, UInt<1>(0h1))
node _res_T_295 = and(_res_T_293, _res_T_294)
node _res_T_296 = eq(res_ignore_6, UInt<1>(0h0))
node _res_T_297 = and(_res_T_296, res_hit_6)
node _res_T_298 = and(_res_T_297, res_aligned_6)
node _res_T_299 = eq(io.pmp[1].cfg.a, UInt<2>(0h2))
node _res_T_300 = and(_res_T_298, _res_T_299)
node _res_T_301 = and(io.pmp[1].cfg.l, res_hit_6)
node _res_T_302 = and(_res_T_301, res_aligned_6)
node _res_T_303 = eq(io.pmp[1].cfg.a, UInt<2>(0h2))
node _res_T_304 = and(_res_T_302, _res_T_303)
node _res_T_305 = eq(res_ignore_6, UInt<1>(0h0))
node _res_T_306 = and(_res_T_305, res_hit_6)
node _res_T_307 = and(_res_T_306, res_aligned_6)
node _res_T_308 = eq(io.pmp[1].cfg.a, UInt<2>(0h3))
node _res_T_309 = and(_res_T_307, _res_T_308)
node _res_T_310 = and(io.pmp[1].cfg.l, res_hit_6)
node _res_T_311 = and(_res_T_310, res_aligned_6)
node _res_T_312 = eq(io.pmp[1].cfg.a, UInt<2>(0h3))
node _res_T_313 = and(_res_T_311, _res_T_312)
wire res_cur_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_6, io.pmp[1]
node _res_cur_cfg_r_T_12 = or(io.pmp[1].cfg.r, res_ignore_6)
node _res_cur_cfg_r_T_13 = and(res_aligned_6, _res_cur_cfg_r_T_12)
connect res_cur_6.cfg.r, _res_cur_cfg_r_T_13
node _res_cur_cfg_w_T_12 = or(io.pmp[1].cfg.w, res_ignore_6)
node _res_cur_cfg_w_T_13 = and(res_aligned_6, _res_cur_cfg_w_T_12)
connect res_cur_6.cfg.w, _res_cur_cfg_w_T_13
node _res_cur_cfg_x_T_12 = or(io.pmp[1].cfg.x, res_ignore_6)
node _res_cur_cfg_x_T_13 = and(res_aligned_6, _res_cur_cfg_x_T_12)
connect res_cur_6.cfg.x, _res_cur_cfg_x_T_13
node _res_T_314 = mux(res_hit_6, res_cur_6, _res_T_269)
node _res_hit_T_91 = bits(io.pmp[0].cfg.a, 1, 1)
node _res_hit_lsbMask_T_21 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_22 = bits(_res_hit_lsbMask_T_21, 2, 0)
node _res_hit_lsbMask_T_23 = not(_res_hit_lsbMask_T_22)
node res_hit_lsbMask_7 = or(io.pmp[0].mask, _res_hit_lsbMask_T_23)
node _res_hit_msbMatch_T_70 = shr(io.addr, 3)
node _res_hit_msbMatch_T_71 = shl(io.pmp[0].addr, 2)
node _res_hit_msbMatch_T_72 = not(_res_hit_msbMatch_T_71)
node _res_hit_msbMatch_T_73 = or(_res_hit_msbMatch_T_72, UInt<2>(0h3))
node _res_hit_msbMatch_T_74 = not(_res_hit_msbMatch_T_73)
node _res_hit_msbMatch_T_75 = shr(_res_hit_msbMatch_T_74, 3)
node _res_hit_msbMatch_T_76 = shr(io.pmp[0].mask, 3)
node _res_hit_msbMatch_T_77 = xor(_res_hit_msbMatch_T_70, _res_hit_msbMatch_T_75)
node _res_hit_msbMatch_T_78 = not(_res_hit_msbMatch_T_76)
node _res_hit_msbMatch_T_79 = and(_res_hit_msbMatch_T_77, _res_hit_msbMatch_T_78)
node res_hit_msbMatch_7 = eq(_res_hit_msbMatch_T_79, UInt<1>(0h0))
node _res_hit_lsbMatch_T_70 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_71 = shl(io.pmp[0].addr, 2)
node _res_hit_lsbMatch_T_72 = not(_res_hit_lsbMatch_T_71)
node _res_hit_lsbMatch_T_73 = or(_res_hit_lsbMatch_T_72, UInt<2>(0h3))
node _res_hit_lsbMatch_T_74 = not(_res_hit_lsbMatch_T_73)
node _res_hit_lsbMatch_T_75 = bits(_res_hit_lsbMatch_T_74, 2, 0)
node _res_hit_lsbMatch_T_76 = bits(res_hit_lsbMask_7, 2, 0)
node _res_hit_lsbMatch_T_77 = xor(_res_hit_lsbMatch_T_70, _res_hit_lsbMatch_T_75)
node _res_hit_lsbMatch_T_78 = not(_res_hit_lsbMatch_T_76)
node _res_hit_lsbMatch_T_79 = and(_res_hit_lsbMatch_T_77, _res_hit_lsbMatch_T_78)
node res_hit_lsbMatch_7 = eq(_res_hit_lsbMatch_T_79, UInt<1>(0h0))
node _res_hit_T_92 = and(res_hit_msbMatch_7, res_hit_lsbMatch_7)
node _res_hit_T_93 = bits(io.pmp[0].cfg.a, 0, 0)
node _res_hit_T_94 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_95 = bits(_res_hit_T_94, 2, 0)
node _res_hit_T_96 = not(_res_hit_T_95)
node _res_hit_msbsLess_T_84 = shr(io.addr, 3)
node _res_hit_msbsLess_T_85 = shl(pmp0.addr, 2)
node _res_hit_msbsLess_T_86 = not(_res_hit_msbsLess_T_85)
node _res_hit_msbsLess_T_87 = or(_res_hit_msbsLess_T_86, UInt<2>(0h3))
node _res_hit_msbsLess_T_88 = not(_res_hit_msbsLess_T_87)
node _res_hit_msbsLess_T_89 = shr(_res_hit_msbsLess_T_88, 3)
node res_hit_msbsLess_14 = lt(_res_hit_msbsLess_T_84, _res_hit_msbsLess_T_89)
node _res_hit_msbsEqual_T_98 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_99 = shl(pmp0.addr, 2)
node _res_hit_msbsEqual_T_100 = not(_res_hit_msbsEqual_T_99)
node _res_hit_msbsEqual_T_101 = or(_res_hit_msbsEqual_T_100, UInt<2>(0h3))
node _res_hit_msbsEqual_T_102 = not(_res_hit_msbsEqual_T_101)
node _res_hit_msbsEqual_T_103 = shr(_res_hit_msbsEqual_T_102, 3)
node _res_hit_msbsEqual_T_104 = xor(_res_hit_msbsEqual_T_98, _res_hit_msbsEqual_T_103)
node res_hit_msbsEqual_14 = eq(_res_hit_msbsEqual_T_104, UInt<1>(0h0))
node _res_hit_lsbsLess_T_98 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_99 = or(_res_hit_lsbsLess_T_98, _res_hit_T_96)
node _res_hit_lsbsLess_T_100 = shl(pmp0.addr, 2)
node _res_hit_lsbsLess_T_101 = not(_res_hit_lsbsLess_T_100)
node _res_hit_lsbsLess_T_102 = or(_res_hit_lsbsLess_T_101, UInt<2>(0h3))
node _res_hit_lsbsLess_T_103 = not(_res_hit_lsbsLess_T_102)
node _res_hit_lsbsLess_T_104 = bits(_res_hit_lsbsLess_T_103, 2, 0)
node res_hit_lsbsLess_14 = lt(_res_hit_lsbsLess_T_99, _res_hit_lsbsLess_T_104)
node _res_hit_T_97 = and(res_hit_msbsEqual_14, res_hit_lsbsLess_14)
node _res_hit_T_98 = or(res_hit_msbsLess_14, _res_hit_T_97)
node _res_hit_T_99 = eq(_res_hit_T_98, UInt<1>(0h0))
node _res_hit_msbsLess_T_90 = shr(io.addr, 3)
node _res_hit_msbsLess_T_91 = shl(io.pmp[0].addr, 2)
node _res_hit_msbsLess_T_92 = not(_res_hit_msbsLess_T_91)
node _res_hit_msbsLess_T_93 = or(_res_hit_msbsLess_T_92, UInt<2>(0h3))
node _res_hit_msbsLess_T_94 = not(_res_hit_msbsLess_T_93)
node _res_hit_msbsLess_T_95 = shr(_res_hit_msbsLess_T_94, 3)
node res_hit_msbsLess_15 = lt(_res_hit_msbsLess_T_90, _res_hit_msbsLess_T_95)
node _res_hit_msbsEqual_T_105 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_106 = shl(io.pmp[0].addr, 2)
node _res_hit_msbsEqual_T_107 = not(_res_hit_msbsEqual_T_106)
node _res_hit_msbsEqual_T_108 = or(_res_hit_msbsEqual_T_107, UInt<2>(0h3))
node _res_hit_msbsEqual_T_109 = not(_res_hit_msbsEqual_T_108)
node _res_hit_msbsEqual_T_110 = shr(_res_hit_msbsEqual_T_109, 3)
node _res_hit_msbsEqual_T_111 = xor(_res_hit_msbsEqual_T_105, _res_hit_msbsEqual_T_110)
node res_hit_msbsEqual_15 = eq(_res_hit_msbsEqual_T_111, UInt<1>(0h0))
node _res_hit_lsbsLess_T_105 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_106 = or(_res_hit_lsbsLess_T_105, UInt<1>(0h0))
node _res_hit_lsbsLess_T_107 = shl(io.pmp[0].addr, 2)
node _res_hit_lsbsLess_T_108 = not(_res_hit_lsbsLess_T_107)
node _res_hit_lsbsLess_T_109 = or(_res_hit_lsbsLess_T_108, UInt<2>(0h3))
node _res_hit_lsbsLess_T_110 = not(_res_hit_lsbsLess_T_109)
node _res_hit_lsbsLess_T_111 = bits(_res_hit_lsbsLess_T_110, 2, 0)
node res_hit_lsbsLess_15 = lt(_res_hit_lsbsLess_T_106, _res_hit_lsbsLess_T_111)
node _res_hit_T_100 = and(res_hit_msbsEqual_15, res_hit_lsbsLess_15)
node _res_hit_T_101 = or(res_hit_msbsLess_15, _res_hit_T_100)
node _res_hit_T_102 = and(_res_hit_T_99, _res_hit_T_101)
node _res_hit_T_103 = and(_res_hit_T_93, _res_hit_T_102)
node res_hit_7 = mux(_res_hit_T_91, _res_hit_T_92, _res_hit_T_103)
node _res_ignore_T_7 = eq(io.pmp[0].cfg.l, UInt<1>(0h0))
node res_ignore_7 = and(default, _res_ignore_T_7)
node _res_aligned_lsbMask_T_14 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_15 = bits(_res_aligned_lsbMask_T_14, 2, 0)
node res_aligned_lsbMask_7 = not(_res_aligned_lsbMask_T_15)
node _res_aligned_straddlesLowerBound_T_119 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_120 = shl(pmp0.addr, 2)
node _res_aligned_straddlesLowerBound_T_121 = not(_res_aligned_straddlesLowerBound_T_120)
node _res_aligned_straddlesLowerBound_T_122 = or(_res_aligned_straddlesLowerBound_T_121, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_123 = not(_res_aligned_straddlesLowerBound_T_122)
node _res_aligned_straddlesLowerBound_T_124 = shr(_res_aligned_straddlesLowerBound_T_123, 3)
node _res_aligned_straddlesLowerBound_T_125 = xor(_res_aligned_straddlesLowerBound_T_119, _res_aligned_straddlesLowerBound_T_124)
node _res_aligned_straddlesLowerBound_T_126 = eq(_res_aligned_straddlesLowerBound_T_125, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_127 = shl(pmp0.addr, 2)
node _res_aligned_straddlesLowerBound_T_128 = not(_res_aligned_straddlesLowerBound_T_127)
node _res_aligned_straddlesLowerBound_T_129 = or(_res_aligned_straddlesLowerBound_T_128, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_130 = not(_res_aligned_straddlesLowerBound_T_129)
node _res_aligned_straddlesLowerBound_T_131 = bits(_res_aligned_straddlesLowerBound_T_130, 2, 0)
node _res_aligned_straddlesLowerBound_T_132 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_133 = not(_res_aligned_straddlesLowerBound_T_132)
node _res_aligned_straddlesLowerBound_T_134 = and(_res_aligned_straddlesLowerBound_T_131, _res_aligned_straddlesLowerBound_T_133)
node _res_aligned_straddlesLowerBound_T_135 = neq(_res_aligned_straddlesLowerBound_T_134, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_7 = and(_res_aligned_straddlesLowerBound_T_126, _res_aligned_straddlesLowerBound_T_135)
node _res_aligned_straddlesUpperBound_T_119 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_120 = shl(io.pmp[0].addr, 2)
node _res_aligned_straddlesUpperBound_T_121 = not(_res_aligned_straddlesUpperBound_T_120)
node _res_aligned_straddlesUpperBound_T_122 = or(_res_aligned_straddlesUpperBound_T_121, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_123 = not(_res_aligned_straddlesUpperBound_T_122)
node _res_aligned_straddlesUpperBound_T_124 = shr(_res_aligned_straddlesUpperBound_T_123, 3)
node _res_aligned_straddlesUpperBound_T_125 = xor(_res_aligned_straddlesUpperBound_T_119, _res_aligned_straddlesUpperBound_T_124)
node _res_aligned_straddlesUpperBound_T_126 = eq(_res_aligned_straddlesUpperBound_T_125, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_127 = shl(io.pmp[0].addr, 2)
node _res_aligned_straddlesUpperBound_T_128 = not(_res_aligned_straddlesUpperBound_T_127)
node _res_aligned_straddlesUpperBound_T_129 = or(_res_aligned_straddlesUpperBound_T_128, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_130 = not(_res_aligned_straddlesUpperBound_T_129)
node _res_aligned_straddlesUpperBound_T_131 = bits(_res_aligned_straddlesUpperBound_T_130, 2, 0)
node _res_aligned_straddlesUpperBound_T_132 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_133 = or(_res_aligned_straddlesUpperBound_T_132, res_aligned_lsbMask_7)
node _res_aligned_straddlesUpperBound_T_134 = and(_res_aligned_straddlesUpperBound_T_131, _res_aligned_straddlesUpperBound_T_133)
node _res_aligned_straddlesUpperBound_T_135 = neq(_res_aligned_straddlesUpperBound_T_134, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_7 = and(_res_aligned_straddlesUpperBound_T_126, _res_aligned_straddlesUpperBound_T_135)
node _res_aligned_rangeAligned_T_7 = or(res_aligned_straddlesLowerBound_7, res_aligned_straddlesUpperBound_7)
node res_aligned_rangeAligned_7 = eq(_res_aligned_rangeAligned_T_7, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_21 = bits(io.pmp[0].mask, 2, 0)
node _res_aligned_pow2Aligned_T_22 = not(_res_aligned_pow2Aligned_T_21)
node _res_aligned_pow2Aligned_T_23 = and(res_aligned_lsbMask_7, _res_aligned_pow2Aligned_T_22)
node res_aligned_pow2Aligned_7 = eq(_res_aligned_pow2Aligned_T_23, UInt<1>(0h0))
node _res_aligned_T_7 = bits(io.pmp[0].cfg.a, 1, 1)
node res_aligned_7 = mux(_res_aligned_T_7, res_aligned_pow2Aligned_7, res_aligned_rangeAligned_7)
node _res_T_315 = eq(io.pmp[0].cfg.a, UInt<1>(0h0))
node _res_T_316 = eq(io.pmp[0].cfg.a, UInt<1>(0h1))
node _res_T_317 = eq(io.pmp[0].cfg.a, UInt<2>(0h2))
node _res_T_318 = eq(io.pmp[0].cfg.a, UInt<2>(0h3))
node _res_T_319 = eq(io.pmp[0].cfg.l, UInt<1>(0h1))
node res_hi_42 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_320 = cat(res_hi_42, io.pmp[0].cfg.r)
node _res_T_321 = eq(_res_T_320, UInt<1>(0h0))
node res_hi_43 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_322 = cat(res_hi_43, io.pmp[0].cfg.r)
node _res_T_323 = eq(_res_T_322, UInt<1>(0h1))
node res_hi_44 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_324 = cat(res_hi_44, io.pmp[0].cfg.r)
node _res_T_325 = eq(_res_T_324, UInt<2>(0h3))
node res_hi_45 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_326 = cat(res_hi_45, io.pmp[0].cfg.r)
node _res_T_327 = eq(_res_T_326, UInt<3>(0h4))
node res_hi_46 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_328 = cat(res_hi_46, io.pmp[0].cfg.r)
node _res_T_329 = eq(_res_T_328, UInt<3>(0h5))
node res_hi_47 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_330 = cat(res_hi_47, io.pmp[0].cfg.r)
node _res_T_331 = eq(_res_T_330, UInt<3>(0h7))
node _res_T_332 = eq(res_ignore_7, UInt<1>(0h0))
node _res_T_333 = and(_res_T_332, res_hit_7)
node _res_T_334 = and(_res_T_333, res_aligned_7)
node _res_T_335 = eq(io.pmp[0].cfg.a, UInt<1>(0h1))
node _res_T_336 = and(_res_T_334, _res_T_335)
node _res_T_337 = and(io.pmp[0].cfg.l, res_hit_7)
node _res_T_338 = and(_res_T_337, res_aligned_7)
node _res_T_339 = eq(io.pmp[0].cfg.a, UInt<1>(0h1))
node _res_T_340 = and(_res_T_338, _res_T_339)
node _res_T_341 = eq(res_ignore_7, UInt<1>(0h0))
node _res_T_342 = and(_res_T_341, res_hit_7)
node _res_T_343 = and(_res_T_342, res_aligned_7)
node _res_T_344 = eq(io.pmp[0].cfg.a, UInt<2>(0h2))
node _res_T_345 = and(_res_T_343, _res_T_344)
node _res_T_346 = and(io.pmp[0].cfg.l, res_hit_7)
node _res_T_347 = and(_res_T_346, res_aligned_7)
node _res_T_348 = eq(io.pmp[0].cfg.a, UInt<2>(0h2))
node _res_T_349 = and(_res_T_347, _res_T_348)
node _res_T_350 = eq(res_ignore_7, UInt<1>(0h0))
node _res_T_351 = and(_res_T_350, res_hit_7)
node _res_T_352 = and(_res_T_351, res_aligned_7)
node _res_T_353 = eq(io.pmp[0].cfg.a, UInt<2>(0h3))
node _res_T_354 = and(_res_T_352, _res_T_353)
node _res_T_355 = and(io.pmp[0].cfg.l, res_hit_7)
node _res_T_356 = and(_res_T_355, res_aligned_7)
node _res_T_357 = eq(io.pmp[0].cfg.a, UInt<2>(0h3))
node _res_T_358 = and(_res_T_356, _res_T_357)
wire res_cur_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_7, io.pmp[0]
node _res_cur_cfg_r_T_14 = or(io.pmp[0].cfg.r, res_ignore_7)
node _res_cur_cfg_r_T_15 = and(res_aligned_7, _res_cur_cfg_r_T_14)
connect res_cur_7.cfg.r, _res_cur_cfg_r_T_15
node _res_cur_cfg_w_T_14 = or(io.pmp[0].cfg.w, res_ignore_7)
node _res_cur_cfg_w_T_15 = and(res_aligned_7, _res_cur_cfg_w_T_14)
connect res_cur_7.cfg.w, _res_cur_cfg_w_T_15
node _res_cur_cfg_x_T_14 = or(io.pmp[0].cfg.x, res_ignore_7)
node _res_cur_cfg_x_T_15 = and(res_aligned_7, _res_cur_cfg_x_T_14)
connect res_cur_7.cfg.x, _res_cur_cfg_x_T_15
node res = mux(res_hit_7, res_cur_7, _res_T_314)
connect io.r, res.cfg.r
connect io.w, res.cfg.w
connect io.x, res.cfg.x | module PMPChecker_s3_11( // @[PMP.scala:143:7]
input clock, // @[PMP.scala:143:7]
input reset, // @[PMP.scala:143:7]
input [1:0] io_prv, // @[PMP.scala:146:14]
input io_pmp_0_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14]
input io_pmp_0_cfg_x, // @[PMP.scala:146:14]
input io_pmp_0_cfg_w, // @[PMP.scala:146:14]
input io_pmp_0_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14]
input io_pmp_1_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14]
input io_pmp_1_cfg_x, // @[PMP.scala:146:14]
input io_pmp_1_cfg_w, // @[PMP.scala:146:14]
input io_pmp_1_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14]
input io_pmp_2_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14]
input io_pmp_2_cfg_x, // @[PMP.scala:146:14]
input io_pmp_2_cfg_w, // @[PMP.scala:146:14]
input io_pmp_2_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14]
input io_pmp_3_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14]
input io_pmp_3_cfg_x, // @[PMP.scala:146:14]
input io_pmp_3_cfg_w, // @[PMP.scala:146:14]
input io_pmp_3_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14]
input io_pmp_4_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14]
input io_pmp_4_cfg_x, // @[PMP.scala:146:14]
input io_pmp_4_cfg_w, // @[PMP.scala:146:14]
input io_pmp_4_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14]
input io_pmp_5_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14]
input io_pmp_5_cfg_x, // @[PMP.scala:146:14]
input io_pmp_5_cfg_w, // @[PMP.scala:146:14]
input io_pmp_5_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14]
input io_pmp_6_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14]
input io_pmp_6_cfg_x, // @[PMP.scala:146:14]
input io_pmp_6_cfg_w, // @[PMP.scala:146:14]
input io_pmp_6_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14]
input io_pmp_7_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14]
input io_pmp_7_cfg_x, // @[PMP.scala:146:14]
input io_pmp_7_cfg_w, // @[PMP.scala:146:14]
input io_pmp_7_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14]
input [31:0] io_addr, // @[PMP.scala:146:14]
input [1:0] io_size, // @[PMP.scala:146:14]
output io_r, // @[PMP.scala:146:14]
output io_w, // @[PMP.scala:146:14]
output io_x // @[PMP.scala:146:14]
);
wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7]
wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7]
wire [1:0] io_size_0 = io_size; // @[PMP.scala:143:7]
wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35]
wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22]
wire _res_hit_T_99 = 1'h1; // @[PMP.scala:88:5]
wire [28:0] _res_hit_msbsLess_T_89 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67]
wire [28:0] _res_hit_msbsEqual_T_103 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_124 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67]
wire [31:0] _res_hit_msbsLess_T_86 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_100 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_102 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_121 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_122 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_128 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_129 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35]
wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22]
wire [31:0] _res_hit_msbsLess_T_85 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_88 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_hit_msbsEqual_T_99 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_102 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_hit_lsbsLess_T_100 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_103 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_aligned_straddlesLowerBound_T_120 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_123 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_aligned_straddlesLowerBound_T_127 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_130 = 32'h0; // @[PMP.scala:60:27]
wire [2:0] _res_hit_lsbsLess_T_104 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}]
wire [2:0] _res_aligned_straddlesLowerBound_T_131 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}]
wire [2:0] _res_aligned_straddlesLowerBound_T_134 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}]
wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35]
wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22]
wire res_hit_msbsLess_14 = 1'h0; // @[PMP.scala:80:39]
wire res_hit_lsbsLess_14 = 1'h0; // @[PMP.scala:82:53]
wire _res_hit_T_97 = 1'h0; // @[PMP.scala:83:30]
wire _res_hit_T_98 = 1'h0; // @[PMP.scala:83:16]
wire _res_aligned_straddlesLowerBound_T_135 = 1'h0; // @[PMP.scala:123:147]
wire res_aligned_straddlesLowerBound_7 = 1'h0; // @[PMP.scala:123:90]
wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35]
wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35]
wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22]
wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22]
wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23]
wire res_cfg_r; // @[PMP.scala:185:8]
wire res_cfg_w; // @[PMP.scala:185:8]
wire res_cfg_x; // @[PMP.scala:185:8]
wire io_r_0; // @[PMP.scala:143:7]
wire io_w_0; // @[PMP.scala:143:7]
wire io_x_0; // @[PMP.scala:143:7]
wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56]
wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22]
wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22]
wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22]
wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [5:0] _GEN = 6'h7 << io_size_0; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T; // @[package.scala:243:71]
assign _res_hit_lsbMask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_3; // @[package.scala:243:71]
assign _res_hit_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_3; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_16; // @[package.scala:243:71]
assign _res_hit_T_16 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_2; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_2 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_6; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_6 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_29; // @[package.scala:243:71]
assign _res_hit_T_29 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_4; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_4 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_9; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_9 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_42; // @[package.scala:243:71]
assign _res_hit_T_42 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_6; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_6 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_12; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_12 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_55; // @[package.scala:243:71]
assign _res_hit_T_55 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_8; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_8 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_15; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_15 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_68; // @[package.scala:243:71]
assign _res_hit_T_68 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_10; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_10 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_18; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_18 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_81; // @[package.scala:243:71]
assign _res_hit_T_81 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_12; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_12 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_21; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_21 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_94; // @[package.scala:243:71]
assign _res_hit_T_94 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_14; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_14 = _GEN; // @[package.scala:243:71]
wire [2:0] _res_hit_lsbMask_T_1 = _res_hit_lsbMask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_2 = ~_res_hit_lsbMask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_6 = io_pmp_7_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T = io_pmp_7_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask = {_res_hit_msbMatch_T_6, _res_aligned_pow2Aligned_T | _res_hit_lsbMask_T_2}; // @[package.scala:243:46]
wire [28:0] _res_hit_msbMatch_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_6 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_7 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_10 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_12 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_14 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_18 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_21 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_20 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_24 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_28 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_35 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_36 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_49 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_40 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_48 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_56 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_54 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_63 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_50 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_66 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_77 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_72 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_78 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_91 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_98 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_90 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_105 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [31:0] _GEN_0 = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbMatch_T_1; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_1; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_7; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_7 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_8; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_8 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_9; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_9 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_1 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_8 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_2 = ~_res_hit_msbMatch_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_3 = {_res_hit_msbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_4 = ~_res_hit_msbMatch_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_5 = _res_hit_msbMatch_T_4[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_7 = _res_hit_msbMatch_T ^ _res_hit_msbMatch_T_5; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_8 = ~_res_hit_msbMatch_T_6; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7 & _res_hit_msbMatch_T_8; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [2:0] _res_hit_lsbMatch_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_7 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_10 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_14 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_21 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_20 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_28 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_35 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_42 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_49 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_40 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_56 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_63 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_50 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_77 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_60 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_84 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_91 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_105 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [31:0] _res_hit_lsbMatch_T_2 = ~_res_hit_lsbMatch_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_3 = {_res_hit_lsbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_4 = ~_res_hit_lsbMatch_T_3; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_5 = _res_hit_lsbMatch_T_4[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_6 = res_hit_lsbMask[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_7 = _res_hit_lsbMatch_T ^ _res_hit_lsbMatch_T_5; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_8 = ~_res_hit_lsbMatch_T_6; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_2 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_4 = _res_hit_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_5 = ~_res_hit_T_4; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_1 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_1; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_1 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_1; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_1 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_2; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_2 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_1 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_8 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_11; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_11; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_19; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_19 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_22; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_22 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_23; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_23 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_18 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_25 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_2 = ~_res_hit_msbsLess_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_3 = {_res_hit_msbsLess_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_4 = ~_res_hit_msbsLess_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_5 = _res_hit_msbsLess_T_4[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess = _res_hit_msbsLess_T < _res_hit_msbsLess_T_5; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_2 = ~_res_hit_msbsEqual_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_3 = {_res_hit_msbsEqual_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_4 = ~_res_hit_msbsEqual_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_5 = _res_hit_msbsEqual_T_4[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_6 = _res_hit_msbsEqual_T ^ _res_hit_msbsEqual_T_5; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_1 = _res_hit_lsbsLess_T | _res_hit_T_5; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_3 = ~_res_hit_lsbsLess_T_2; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_4 = {_res_hit_lsbsLess_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_5 = ~_res_hit_lsbsLess_T_4; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_6 = _res_hit_lsbsLess_T_5[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess = _res_hit_lsbsLess_T_1 < _res_hit_lsbsLess_T_6; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_6 = res_hit_msbsEqual & res_hit_lsbsLess; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_7 = res_hit_msbsLess | _res_hit_T_6; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_8 = ~_res_hit_T_7; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_8 = ~_res_hit_msbsLess_T_7; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_9 = {_res_hit_msbsLess_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_10 = ~_res_hit_msbsLess_T_9; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_11 = _res_hit_msbsLess_T_10[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_1 = _res_hit_msbsLess_T_6 < _res_hit_msbsLess_T_11; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_9 = ~_res_hit_msbsEqual_T_8; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_10 = {_res_hit_msbsEqual_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_11 = ~_res_hit_msbsEqual_T_10; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_12 = _res_hit_msbsEqual_T_11[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_13 = _res_hit_msbsEqual_T_7 ^ _res_hit_msbsEqual_T_12; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_1 = _res_hit_msbsEqual_T_13 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_8 = _res_hit_lsbsLess_T_7; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_10 = ~_res_hit_lsbsLess_T_9; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_11 = {_res_hit_lsbsLess_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_12 = ~_res_hit_lsbsLess_T_11; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_13 = _res_hit_lsbsLess_T_12[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_1 = _res_hit_lsbsLess_T_8 < _res_hit_lsbsLess_T_13; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_9 = res_hit_msbsEqual_1 & res_hit_lsbsLess_1; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_10 = res_hit_msbsLess_1 | _res_hit_T_9; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_11 = _res_hit_T_8 & _res_hit_T_10; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_12 = _res_hit_T_2 & _res_hit_T_11; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit = _res_hit_T ? _res_hit_T_1 : _res_hit_T_12; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_1 = _res_aligned_lsbMask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask = ~_res_aligned_lsbMask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_2 = ~_res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_3 = {_res_aligned_straddlesLowerBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_4 = ~_res_aligned_straddlesLowerBound_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_5 = _res_aligned_straddlesLowerBound_T_4[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_6 = _res_aligned_straddlesLowerBound_T ^ _res_aligned_straddlesLowerBound_T_5; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_7 = _res_aligned_straddlesLowerBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_9 = ~_res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_10 = {_res_aligned_straddlesLowerBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_11 = ~_res_aligned_straddlesLowerBound_T_10; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_12 = _res_aligned_straddlesLowerBound_T_11[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_14 = ~_res_aligned_straddlesLowerBound_T_13; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_15 = _res_aligned_straddlesLowerBound_T_12 & _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_16 = |_res_aligned_straddlesLowerBound_T_15; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound = _res_aligned_straddlesLowerBound_T_7 & _res_aligned_straddlesLowerBound_T_16; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_2 = ~_res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_3 = {_res_aligned_straddlesUpperBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_4 = ~_res_aligned_straddlesUpperBound_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_5 = _res_aligned_straddlesUpperBound_T_4[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_6 = _res_aligned_straddlesUpperBound_T ^ _res_aligned_straddlesUpperBound_T_5; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_7 = _res_aligned_straddlesUpperBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_9 = ~_res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_10 = {_res_aligned_straddlesUpperBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_11 = ~_res_aligned_straddlesUpperBound_T_10; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_12 = _res_aligned_straddlesUpperBound_T_11[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_14 = _res_aligned_straddlesUpperBound_T_13 | res_aligned_lsbMask; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_15 = _res_aligned_straddlesUpperBound_T_12 & _res_aligned_straddlesUpperBound_T_14; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_16 = |_res_aligned_straddlesUpperBound_T_15; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound = _res_aligned_straddlesUpperBound_T_7 & _res_aligned_straddlesUpperBound_T_16; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T = res_aligned_straddlesLowerBound | res_aligned_straddlesUpperBound; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned = ~_res_aligned_rangeAligned_T; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_1 = ~_res_aligned_pow2Aligned_T; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_2 = res_aligned_lsbMask & _res_aligned_pow2Aligned_T_1; // @[package.scala:243:46]
wire res_aligned_pow2Aligned = _res_aligned_pow2Aligned_T_2 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned = _res_aligned_T ? res_aligned_pow2Aligned : res_aligned_rangeAligned; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_1; // @[PMP.scala:168:32]
assign _res_T_1 = _GEN_2; // @[PMP.scala:168:32]
wire _res_T_20; // @[PMP.scala:177:61]
assign _res_T_20 = _GEN_2; // @[PMP.scala:168:32, :177:61]
wire _res_T_24; // @[PMP.scala:178:63]
assign _res_T_24 = _GEN_2; // @[PMP.scala:168:32, :178:63]
wire _GEN_3 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_2; // @[PMP.scala:168:32]
assign _res_T_2 = _GEN_3; // @[PMP.scala:168:32]
wire _res_T_29; // @[PMP.scala:177:61]
assign _res_T_29 = _GEN_3; // @[PMP.scala:168:32, :177:61]
wire _res_T_33; // @[PMP.scala:178:63]
assign _res_T_33 = _GEN_3; // @[PMP.scala:168:32, :178:63]
wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_4 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi; // @[PMP.scala:174:26]
assign res_hi = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_1; // @[PMP.scala:174:26]
assign res_hi_1 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_2; // @[PMP.scala:174:26]
assign res_hi_2 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_3; // @[PMP.scala:174:26]
assign res_hi_3 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_4; // @[PMP.scala:174:26]
assign res_hi_4 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_5; // @[PMP.scala:174:26]
assign res_hi_5 = _GEN_4; // @[PMP.scala:174:26]
wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}]
wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_19 = _res_T_18 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}]
wire _GEN_5 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_22; // @[PMP.scala:178:32]
assign _res_T_22 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_31; // @[PMP.scala:178:32]
assign _res_T_31 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_40; // @[PMP.scala:178:32]
assign _res_T_40 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_23 = _res_T_22 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}]
wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_28 = _res_T_27 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}]
wire _res_T_32 = _res_T_31 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}]
wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_37 = _res_T_36 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}]
wire _res_T_41 = _res_T_40 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26]
wire res_cur_cfg_x; // @[PMP.scala:181:23]
wire res_cur_cfg_w; // @[PMP.scala:181:23]
wire res_cur_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_1 = res_aligned & _res_cur_cfg_r_T; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_1 = res_aligned & _res_cur_cfg_w_T; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_1 = res_aligned & _res_cur_cfg_x_T; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26]
wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_13 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_1 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_4 = _res_hit_lsbMask_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_5 = ~_res_hit_lsbMask_T_4; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_16 = io_pmp_6_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_3 = io_pmp_6_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_1 = {_res_hit_msbMatch_T_16, _res_aligned_pow2Aligned_T_3 | _res_hit_lsbMask_T_5}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_12 = ~_res_hit_msbMatch_T_11; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_13 = {_res_hit_msbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_14 = ~_res_hit_msbMatch_T_13; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_15 = _res_hit_msbMatch_T_14[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_17 = _res_hit_msbMatch_T_10 ^ _res_hit_msbMatch_T_15; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_18 = ~_res_hit_msbMatch_T_16; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_19 = _res_hit_msbMatch_T_17 & _res_hit_msbMatch_T_18; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_12 = ~_res_hit_lsbMatch_T_11; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_13 = {_res_hit_lsbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_14 = ~_res_hit_lsbMatch_T_13; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_15 = _res_hit_lsbMatch_T_14[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_16 = res_hit_lsbMask_1[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_17 = _res_hit_lsbMatch_T_10 ^ _res_hit_lsbMatch_T_15; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_18 = ~_res_hit_lsbMatch_T_16; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_14 = res_hit_msbMatch_1 & res_hit_lsbMatch_1; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_15 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_17 = _res_hit_T_16[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_18 = ~_res_hit_T_17; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_6 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_13; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_13 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_15; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_15 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_16; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_16 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_18 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_25 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_21; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_21; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_31; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_31 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_36; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_36 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_37; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_37 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_35 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_42 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_14 = ~_res_hit_msbsLess_T_13; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_15 = {_res_hit_msbsLess_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_16 = ~_res_hit_msbsLess_T_15; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_17 = _res_hit_msbsLess_T_16[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_2 = _res_hit_msbsLess_T_12 < _res_hit_msbsLess_T_17; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_16 = ~_res_hit_msbsEqual_T_15; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_17 = {_res_hit_msbsEqual_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_18 = ~_res_hit_msbsEqual_T_17; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_19 = _res_hit_msbsEqual_T_18[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_20 = _res_hit_msbsEqual_T_14 ^ _res_hit_msbsEqual_T_19; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_15 = _res_hit_lsbsLess_T_14 | _res_hit_T_18; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_17 = ~_res_hit_lsbsLess_T_16; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_18 = {_res_hit_lsbsLess_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_19 = ~_res_hit_lsbsLess_T_18; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_20 = _res_hit_lsbsLess_T_19[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_2 = _res_hit_lsbsLess_T_15 < _res_hit_lsbsLess_T_20; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_19 = res_hit_msbsEqual_2 & res_hit_lsbsLess_2; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_20 = res_hit_msbsLess_2 | _res_hit_T_19; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_21 = ~_res_hit_T_20; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_20 = ~_res_hit_msbsLess_T_19; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_21 = {_res_hit_msbsLess_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_22 = ~_res_hit_msbsLess_T_21; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_23 = _res_hit_msbsLess_T_22[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_3 = _res_hit_msbsLess_T_18 < _res_hit_msbsLess_T_23; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_23 = ~_res_hit_msbsEqual_T_22; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_24 = {_res_hit_msbsEqual_T_23[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_25 = ~_res_hit_msbsEqual_T_24; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_26 = _res_hit_msbsEqual_T_25[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_27 = _res_hit_msbsEqual_T_21 ^ _res_hit_msbsEqual_T_26; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_3 = _res_hit_msbsEqual_T_27 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_22 = _res_hit_lsbsLess_T_21; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_24 = ~_res_hit_lsbsLess_T_23; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_25 = {_res_hit_lsbsLess_T_24[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_26 = ~_res_hit_lsbsLess_T_25; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_27 = _res_hit_lsbsLess_T_26[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_3 = _res_hit_lsbsLess_T_22 < _res_hit_lsbsLess_T_27; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_22 = res_hit_msbsEqual_3 & res_hit_lsbsLess_3; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_23 = res_hit_msbsLess_3 | _res_hit_T_22; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_24 = _res_hit_T_21 & _res_hit_T_23; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_25 = _res_hit_T_15 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_1 = _res_hit_T_13 ? _res_hit_T_14 : _res_hit_T_25; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_3 = _res_aligned_lsbMask_T_2[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_1 = ~_res_aligned_lsbMask_T_3; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_19 = ~_res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_20 = {_res_aligned_straddlesLowerBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_21 = ~_res_aligned_straddlesLowerBound_T_20; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_22 = _res_aligned_straddlesLowerBound_T_21[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_23 = _res_aligned_straddlesLowerBound_T_17 ^ _res_aligned_straddlesLowerBound_T_22; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_24 = _res_aligned_straddlesLowerBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_26 = ~_res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_27 = {_res_aligned_straddlesLowerBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_28 = ~_res_aligned_straddlesLowerBound_T_27; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_29 = _res_aligned_straddlesLowerBound_T_28[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_31 = ~_res_aligned_straddlesLowerBound_T_30; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_32 = _res_aligned_straddlesLowerBound_T_29 & _res_aligned_straddlesLowerBound_T_31; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_33 = |_res_aligned_straddlesLowerBound_T_32; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_1 = _res_aligned_straddlesLowerBound_T_24 & _res_aligned_straddlesLowerBound_T_33; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_19 = ~_res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_20 = {_res_aligned_straddlesUpperBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_21 = ~_res_aligned_straddlesUpperBound_T_20; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_22 = _res_aligned_straddlesUpperBound_T_21[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_23 = _res_aligned_straddlesUpperBound_T_17 ^ _res_aligned_straddlesUpperBound_T_22; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_24 = _res_aligned_straddlesUpperBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_26 = ~_res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_27 = {_res_aligned_straddlesUpperBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_28 = ~_res_aligned_straddlesUpperBound_T_27; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_29 = _res_aligned_straddlesUpperBound_T_28[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_31 = _res_aligned_straddlesUpperBound_T_30 | res_aligned_lsbMask_1; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_32 = _res_aligned_straddlesUpperBound_T_29 & _res_aligned_straddlesUpperBound_T_31; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_33 = |_res_aligned_straddlesUpperBound_T_32; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_1 = _res_aligned_straddlesUpperBound_T_24 & _res_aligned_straddlesUpperBound_T_33; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_1 = res_aligned_straddlesLowerBound_1 | res_aligned_straddlesUpperBound_1; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_1 = ~_res_aligned_rangeAligned_T_1; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_4 = ~_res_aligned_pow2Aligned_T_3; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_5 = res_aligned_lsbMask_1 & _res_aligned_pow2Aligned_T_4; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_1 = _res_aligned_pow2Aligned_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_1 = _res_aligned_T_1 ? res_aligned_pow2Aligned_1 : res_aligned_rangeAligned_1; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_46; // @[PMP.scala:168:32]
assign _res_T_46 = _GEN_7; // @[PMP.scala:168:32]
wire _res_T_65; // @[PMP.scala:177:61]
assign _res_T_65 = _GEN_7; // @[PMP.scala:168:32, :177:61]
wire _res_T_69; // @[PMP.scala:178:63]
assign _res_T_69 = _GEN_7; // @[PMP.scala:168:32, :178:63]
wire _GEN_8 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_47; // @[PMP.scala:168:32]
assign _res_T_47 = _GEN_8; // @[PMP.scala:168:32]
wire _res_T_74; // @[PMP.scala:177:61]
assign _res_T_74 = _GEN_8; // @[PMP.scala:168:32, :177:61]
wire _res_T_78; // @[PMP.scala:178:63]
assign _res_T_78 = _GEN_8; // @[PMP.scala:168:32, :178:63]
wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_9 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_6; // @[PMP.scala:174:26]
assign res_hi_6 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_7; // @[PMP.scala:174:26]
assign res_hi_7 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_8; // @[PMP.scala:174:26]
assign res_hi_8 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_9; // @[PMP.scala:174:26]
assign res_hi_9 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_10; // @[PMP.scala:174:26]
assign res_hi_10 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_11; // @[PMP.scala:174:26]
assign res_hi_11 = _GEN_9; // @[PMP.scala:174:26]
wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}]
wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_64 = _res_T_63 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}]
wire _GEN_10 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_67; // @[PMP.scala:178:32]
assign _res_T_67 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_76; // @[PMP.scala:178:32]
assign _res_T_76 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_85; // @[PMP.scala:178:32]
assign _res_T_85 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_68 = _res_T_67 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}]
wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_73 = _res_T_72 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}]
wire _res_T_77 = _res_T_76 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}]
wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_82 = _res_T_81 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}]
wire _res_T_86 = _res_T_85 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26]
wire res_cur_1_cfg_x; // @[PMP.scala:181:23]
wire res_cur_1_cfg_w; // @[PMP.scala:181:23]
wire res_cur_1_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_3 = res_aligned_1 & _res_cur_cfg_r_T_2; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_3 = res_aligned_1 & _res_cur_cfg_w_T_2; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_3 = res_aligned_1 & _res_cur_cfg_x_T_2; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26]
wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_26 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_2 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_7 = _res_hit_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_8 = ~_res_hit_lsbMask_T_7; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_26 = io_pmp_5_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_6 = io_pmp_5_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_2 = {_res_hit_msbMatch_T_26, _res_aligned_pow2Aligned_T_6 | _res_hit_lsbMask_T_8}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_22 = ~_res_hit_msbMatch_T_21; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_23 = {_res_hit_msbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_24 = ~_res_hit_msbMatch_T_23; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_25 = _res_hit_msbMatch_T_24[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_27 = _res_hit_msbMatch_T_20 ^ _res_hit_msbMatch_T_25; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_28 = ~_res_hit_msbMatch_T_26; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_29 = _res_hit_msbMatch_T_27 & _res_hit_msbMatch_T_28; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_22 = ~_res_hit_lsbMatch_T_21; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_23 = {_res_hit_lsbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_24 = ~_res_hit_lsbMatch_T_23; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_25 = _res_hit_lsbMatch_T_24[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_26 = res_hit_lsbMask_2[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_27 = _res_hit_lsbMatch_T_20 ^ _res_hit_lsbMatch_T_25; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_28 = ~_res_hit_lsbMatch_T_26; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_27 = res_hit_msbMatch_2 & res_hit_lsbMatch_2; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_28 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_30 = _res_hit_T_29[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_31 = ~_res_hit_T_30; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_11 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_25; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_25 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_29; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_29 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_30; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_30 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_35 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_42 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_31; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_31; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_43; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_43 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_50; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_50 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_51; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_51 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_52 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_59 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_26 = ~_res_hit_msbsLess_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_27 = {_res_hit_msbsLess_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_28 = ~_res_hit_msbsLess_T_27; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_29 = _res_hit_msbsLess_T_28[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_4 = _res_hit_msbsLess_T_24 < _res_hit_msbsLess_T_29; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_30 = ~_res_hit_msbsEqual_T_29; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_31 = {_res_hit_msbsEqual_T_30[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_32 = ~_res_hit_msbsEqual_T_31; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_33 = _res_hit_msbsEqual_T_32[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_34 = _res_hit_msbsEqual_T_28 ^ _res_hit_msbsEqual_T_33; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_29 = _res_hit_lsbsLess_T_28 | _res_hit_T_31; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_31 = ~_res_hit_lsbsLess_T_30; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_32 = {_res_hit_lsbsLess_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_33 = ~_res_hit_lsbsLess_T_32; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_34 = _res_hit_lsbsLess_T_33[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_4 = _res_hit_lsbsLess_T_29 < _res_hit_lsbsLess_T_34; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_32 = res_hit_msbsEqual_4 & res_hit_lsbsLess_4; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_33 = res_hit_msbsLess_4 | _res_hit_T_32; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_34 = ~_res_hit_T_33; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_32 = ~_res_hit_msbsLess_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_33 = {_res_hit_msbsLess_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_34 = ~_res_hit_msbsLess_T_33; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_35 = _res_hit_msbsLess_T_34[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_5 = _res_hit_msbsLess_T_30 < _res_hit_msbsLess_T_35; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_37 = ~_res_hit_msbsEqual_T_36; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_38 = {_res_hit_msbsEqual_T_37[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_39 = ~_res_hit_msbsEqual_T_38; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_40 = _res_hit_msbsEqual_T_39[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_41 = _res_hit_msbsEqual_T_35 ^ _res_hit_msbsEqual_T_40; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_5 = _res_hit_msbsEqual_T_41 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_36 = _res_hit_lsbsLess_T_35; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_38 = ~_res_hit_lsbsLess_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_39 = {_res_hit_lsbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_40 = ~_res_hit_lsbsLess_T_39; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_41 = _res_hit_lsbsLess_T_40[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_5 = _res_hit_lsbsLess_T_36 < _res_hit_lsbsLess_T_41; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_35 = res_hit_msbsEqual_5 & res_hit_lsbsLess_5; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_36 = res_hit_msbsLess_5 | _res_hit_T_35; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_37 = _res_hit_T_34 & _res_hit_T_36; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_38 = _res_hit_T_28 & _res_hit_T_37; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_2 = _res_hit_T_26 ? _res_hit_T_27 : _res_hit_T_38; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_5 = _res_aligned_lsbMask_T_4[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_2 = ~_res_aligned_lsbMask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_36 = ~_res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_37 = {_res_aligned_straddlesLowerBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_38 = ~_res_aligned_straddlesLowerBound_T_37; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_39 = _res_aligned_straddlesLowerBound_T_38[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_40 = _res_aligned_straddlesLowerBound_T_34 ^ _res_aligned_straddlesLowerBound_T_39; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_41 = _res_aligned_straddlesLowerBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_43 = ~_res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_44 = {_res_aligned_straddlesLowerBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_45 = ~_res_aligned_straddlesLowerBound_T_44; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_46 = _res_aligned_straddlesLowerBound_T_45[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_48 = ~_res_aligned_straddlesLowerBound_T_47; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_49 = _res_aligned_straddlesLowerBound_T_46 & _res_aligned_straddlesLowerBound_T_48; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_50 = |_res_aligned_straddlesLowerBound_T_49; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_2 = _res_aligned_straddlesLowerBound_T_41 & _res_aligned_straddlesLowerBound_T_50; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_36 = ~_res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_37 = {_res_aligned_straddlesUpperBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_38 = ~_res_aligned_straddlesUpperBound_T_37; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_39 = _res_aligned_straddlesUpperBound_T_38[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_40 = _res_aligned_straddlesUpperBound_T_34 ^ _res_aligned_straddlesUpperBound_T_39; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_41 = _res_aligned_straddlesUpperBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_43 = ~_res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_44 = {_res_aligned_straddlesUpperBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_45 = ~_res_aligned_straddlesUpperBound_T_44; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_46 = _res_aligned_straddlesUpperBound_T_45[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_48 = _res_aligned_straddlesUpperBound_T_47 | res_aligned_lsbMask_2; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_49 = _res_aligned_straddlesUpperBound_T_46 & _res_aligned_straddlesUpperBound_T_48; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_50 = |_res_aligned_straddlesUpperBound_T_49; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_2 = _res_aligned_straddlesUpperBound_T_41 & _res_aligned_straddlesUpperBound_T_50; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_2 = res_aligned_straddlesLowerBound_2 | res_aligned_straddlesUpperBound_2; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_2 = ~_res_aligned_rangeAligned_T_2; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_7 = ~_res_aligned_pow2Aligned_T_6; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_8 = res_aligned_lsbMask_2 & _res_aligned_pow2Aligned_T_7; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_2 = _res_aligned_pow2Aligned_T_8 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_2 = _res_aligned_T_2 ? res_aligned_pow2Aligned_2 : res_aligned_rangeAligned_2; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_91; // @[PMP.scala:168:32]
assign _res_T_91 = _GEN_12; // @[PMP.scala:168:32]
wire _res_T_110; // @[PMP.scala:177:61]
assign _res_T_110 = _GEN_12; // @[PMP.scala:168:32, :177:61]
wire _res_T_114; // @[PMP.scala:178:63]
assign _res_T_114 = _GEN_12; // @[PMP.scala:168:32, :178:63]
wire _GEN_13 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_92; // @[PMP.scala:168:32]
assign _res_T_92 = _GEN_13; // @[PMP.scala:168:32]
wire _res_T_119; // @[PMP.scala:177:61]
assign _res_T_119 = _GEN_13; // @[PMP.scala:168:32, :177:61]
wire _res_T_123; // @[PMP.scala:178:63]
assign _res_T_123 = _GEN_13; // @[PMP.scala:168:32, :178:63]
wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_14 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_12; // @[PMP.scala:174:26]
assign res_hi_12 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_13; // @[PMP.scala:174:26]
assign res_hi_13 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_14; // @[PMP.scala:174:26]
assign res_hi_14 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_15; // @[PMP.scala:174:26]
assign res_hi_15 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_16; // @[PMP.scala:174:26]
assign res_hi_16 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_17; // @[PMP.scala:174:26]
assign res_hi_17 = _GEN_14; // @[PMP.scala:174:26]
wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}]
wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_109 = _res_T_108 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}]
wire _GEN_15 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_112; // @[PMP.scala:178:32]
assign _res_T_112 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_121; // @[PMP.scala:178:32]
assign _res_T_121 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_130; // @[PMP.scala:178:32]
assign _res_T_130 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_113 = _res_T_112 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}]
wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_118 = _res_T_117 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}]
wire _res_T_122 = _res_T_121 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}]
wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_127 = _res_T_126 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}]
wire _res_T_131 = _res_T_130 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26]
wire res_cur_2_cfg_x; // @[PMP.scala:181:23]
wire res_cur_2_cfg_w; // @[PMP.scala:181:23]
wire res_cur_2_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_5 = res_aligned_2 & _res_cur_cfg_r_T_4; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_5 = res_aligned_2 & _res_cur_cfg_w_T_4; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_5 = res_aligned_2 & _res_cur_cfg_x_T_4; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26]
wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_39 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_3 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_10 = _res_hit_lsbMask_T_9[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_11 = ~_res_hit_lsbMask_T_10; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_36 = io_pmp_4_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_9 = io_pmp_4_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_3 = {_res_hit_msbMatch_T_36, _res_aligned_pow2Aligned_T_9 | _res_hit_lsbMask_T_11}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_32 = ~_res_hit_msbMatch_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_33 = {_res_hit_msbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_34 = ~_res_hit_msbMatch_T_33; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_35 = _res_hit_msbMatch_T_34[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_37 = _res_hit_msbMatch_T_30 ^ _res_hit_msbMatch_T_35; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_38 = ~_res_hit_msbMatch_T_36; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_39 = _res_hit_msbMatch_T_37 & _res_hit_msbMatch_T_38; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_32 = ~_res_hit_lsbMatch_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_33 = {_res_hit_lsbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_34 = ~_res_hit_lsbMatch_T_33; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_35 = _res_hit_lsbMatch_T_34[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_36 = res_hit_lsbMask_3[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_37 = _res_hit_lsbMatch_T_30 ^ _res_hit_lsbMatch_T_35; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_38 = ~_res_hit_lsbMatch_T_36; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_40 = res_hit_msbMatch_3 & res_hit_lsbMatch_3; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_41 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_43 = _res_hit_T_42[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_44 = ~_res_hit_T_43; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_16 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_37; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_37 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_43; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_43 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_44; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_44 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_52 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_59 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_41; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_41; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_55; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_55 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_64; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_64 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_65; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_65 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_69 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_76 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_38 = ~_res_hit_msbsLess_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_39 = {_res_hit_msbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_40 = ~_res_hit_msbsLess_T_39; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_41 = _res_hit_msbsLess_T_40[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_6 = _res_hit_msbsLess_T_36 < _res_hit_msbsLess_T_41; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_44 = ~_res_hit_msbsEqual_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_45 = {_res_hit_msbsEqual_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_46 = ~_res_hit_msbsEqual_T_45; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_47 = _res_hit_msbsEqual_T_46[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_48 = _res_hit_msbsEqual_T_42 ^ _res_hit_msbsEqual_T_47; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_43 = _res_hit_lsbsLess_T_42 | _res_hit_T_44; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_45 = ~_res_hit_lsbsLess_T_44; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_46 = {_res_hit_lsbsLess_T_45[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_47 = ~_res_hit_lsbsLess_T_46; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_48 = _res_hit_lsbsLess_T_47[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_6 = _res_hit_lsbsLess_T_43 < _res_hit_lsbsLess_T_48; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_45 = res_hit_msbsEqual_6 & res_hit_lsbsLess_6; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_46 = res_hit_msbsLess_6 | _res_hit_T_45; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_47 = ~_res_hit_T_46; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_44 = ~_res_hit_msbsLess_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_45 = {_res_hit_msbsLess_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_46 = ~_res_hit_msbsLess_T_45; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_47 = _res_hit_msbsLess_T_46[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_7 = _res_hit_msbsLess_T_42 < _res_hit_msbsLess_T_47; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_51 = ~_res_hit_msbsEqual_T_50; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_52 = {_res_hit_msbsEqual_T_51[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_53 = ~_res_hit_msbsEqual_T_52; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_54 = _res_hit_msbsEqual_T_53[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_55 = _res_hit_msbsEqual_T_49 ^ _res_hit_msbsEqual_T_54; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_7 = _res_hit_msbsEqual_T_55 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_50 = _res_hit_lsbsLess_T_49; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_52 = ~_res_hit_lsbsLess_T_51; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_53 = {_res_hit_lsbsLess_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_54 = ~_res_hit_lsbsLess_T_53; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_55 = _res_hit_lsbsLess_T_54[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_7 = _res_hit_lsbsLess_T_50 < _res_hit_lsbsLess_T_55; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_48 = res_hit_msbsEqual_7 & res_hit_lsbsLess_7; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_49 = res_hit_msbsLess_7 | _res_hit_T_48; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_50 = _res_hit_T_47 & _res_hit_T_49; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_51 = _res_hit_T_41 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_3 = _res_hit_T_39 ? _res_hit_T_40 : _res_hit_T_51; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_7 = _res_aligned_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_3 = ~_res_aligned_lsbMask_T_7; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_53 = ~_res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_54 = {_res_aligned_straddlesLowerBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_55 = ~_res_aligned_straddlesLowerBound_T_54; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_56 = _res_aligned_straddlesLowerBound_T_55[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_57 = _res_aligned_straddlesLowerBound_T_51 ^ _res_aligned_straddlesLowerBound_T_56; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_58 = _res_aligned_straddlesLowerBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_60 = ~_res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_61 = {_res_aligned_straddlesLowerBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_62 = ~_res_aligned_straddlesLowerBound_T_61; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_63 = _res_aligned_straddlesLowerBound_T_62[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_65 = ~_res_aligned_straddlesLowerBound_T_64; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_66 = _res_aligned_straddlesLowerBound_T_63 & _res_aligned_straddlesLowerBound_T_65; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_67 = |_res_aligned_straddlesLowerBound_T_66; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_3 = _res_aligned_straddlesLowerBound_T_58 & _res_aligned_straddlesLowerBound_T_67; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_53 = ~_res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_54 = {_res_aligned_straddlesUpperBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_55 = ~_res_aligned_straddlesUpperBound_T_54; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_56 = _res_aligned_straddlesUpperBound_T_55[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_57 = _res_aligned_straddlesUpperBound_T_51 ^ _res_aligned_straddlesUpperBound_T_56; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_58 = _res_aligned_straddlesUpperBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_60 = ~_res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_61 = {_res_aligned_straddlesUpperBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_62 = ~_res_aligned_straddlesUpperBound_T_61; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_63 = _res_aligned_straddlesUpperBound_T_62[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_65 = _res_aligned_straddlesUpperBound_T_64 | res_aligned_lsbMask_3; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_66 = _res_aligned_straddlesUpperBound_T_63 & _res_aligned_straddlesUpperBound_T_65; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_67 = |_res_aligned_straddlesUpperBound_T_66; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_3 = _res_aligned_straddlesUpperBound_T_58 & _res_aligned_straddlesUpperBound_T_67; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_3 = res_aligned_straddlesLowerBound_3 | res_aligned_straddlesUpperBound_3; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_3 = ~_res_aligned_rangeAligned_T_3; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_10 = ~_res_aligned_pow2Aligned_T_9; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_11 = res_aligned_lsbMask_3 & _res_aligned_pow2Aligned_T_10; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_3 = _res_aligned_pow2Aligned_T_11 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_3 = _res_aligned_T_3 ? res_aligned_pow2Aligned_3 : res_aligned_rangeAligned_3; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_136; // @[PMP.scala:168:32]
assign _res_T_136 = _GEN_17; // @[PMP.scala:168:32]
wire _res_T_155; // @[PMP.scala:177:61]
assign _res_T_155 = _GEN_17; // @[PMP.scala:168:32, :177:61]
wire _res_T_159; // @[PMP.scala:178:63]
assign _res_T_159 = _GEN_17; // @[PMP.scala:168:32, :178:63]
wire _GEN_18 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_137; // @[PMP.scala:168:32]
assign _res_T_137 = _GEN_18; // @[PMP.scala:168:32]
wire _res_T_164; // @[PMP.scala:177:61]
assign _res_T_164 = _GEN_18; // @[PMP.scala:168:32, :177:61]
wire _res_T_168; // @[PMP.scala:178:63]
assign _res_T_168 = _GEN_18; // @[PMP.scala:168:32, :178:63]
wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_19 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_18; // @[PMP.scala:174:26]
assign res_hi_18 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_19; // @[PMP.scala:174:26]
assign res_hi_19 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_20; // @[PMP.scala:174:26]
assign res_hi_20 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_21; // @[PMP.scala:174:26]
assign res_hi_21 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_22; // @[PMP.scala:174:26]
assign res_hi_22 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_23; // @[PMP.scala:174:26]
assign res_hi_23 = _GEN_19; // @[PMP.scala:174:26]
wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}]
wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_154 = _res_T_153 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}]
wire _GEN_20 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_157; // @[PMP.scala:178:32]
assign _res_T_157 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_166; // @[PMP.scala:178:32]
assign _res_T_166 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_175; // @[PMP.scala:178:32]
assign _res_T_175 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_158 = _res_T_157 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}]
wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_163 = _res_T_162 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}]
wire _res_T_167 = _res_T_166 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}]
wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_172 = _res_T_171 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}]
wire _res_T_176 = _res_T_175 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26]
wire res_cur_3_cfg_x; // @[PMP.scala:181:23]
wire res_cur_3_cfg_w; // @[PMP.scala:181:23]
wire res_cur_3_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_7 = res_aligned_3 & _res_cur_cfg_r_T_6; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_7 = res_aligned_3 & _res_cur_cfg_w_T_6; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_7 = res_aligned_3 & _res_cur_cfg_x_T_6; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26]
wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_52 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_4 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_13 = _res_hit_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_14 = ~_res_hit_lsbMask_T_13; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_46 = io_pmp_3_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_12 = io_pmp_3_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_4 = {_res_hit_msbMatch_T_46, _res_aligned_pow2Aligned_T_12 | _res_hit_lsbMask_T_14}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_42 = ~_res_hit_msbMatch_T_41; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_43 = {_res_hit_msbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_44 = ~_res_hit_msbMatch_T_43; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_45 = _res_hit_msbMatch_T_44[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_47 = _res_hit_msbMatch_T_40 ^ _res_hit_msbMatch_T_45; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_48 = ~_res_hit_msbMatch_T_46; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_49 = _res_hit_msbMatch_T_47 & _res_hit_msbMatch_T_48; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_42 = ~_res_hit_lsbMatch_T_41; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_43 = {_res_hit_lsbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_44 = ~_res_hit_lsbMatch_T_43; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_45 = _res_hit_lsbMatch_T_44[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_46 = res_hit_lsbMask_4[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_47 = _res_hit_lsbMatch_T_40 ^ _res_hit_lsbMatch_T_45; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_48 = ~_res_hit_lsbMatch_T_46; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_53 = res_hit_msbMatch_4 & res_hit_lsbMatch_4; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_54 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_56 = _res_hit_T_55[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_57 = ~_res_hit_T_56; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_21 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_49; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_49 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_57; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_57 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_58; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_58 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_69 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_76 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_51; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_51; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_67; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_67 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_78; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_78 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_79; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_79 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_86 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_93 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_50 = ~_res_hit_msbsLess_T_49; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_51 = {_res_hit_msbsLess_T_50[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_52 = ~_res_hit_msbsLess_T_51; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_53 = _res_hit_msbsLess_T_52[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_8 = _res_hit_msbsLess_T_48 < _res_hit_msbsLess_T_53; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_58 = ~_res_hit_msbsEqual_T_57; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_59 = {_res_hit_msbsEqual_T_58[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_60 = ~_res_hit_msbsEqual_T_59; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_61 = _res_hit_msbsEqual_T_60[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_62 = _res_hit_msbsEqual_T_56 ^ _res_hit_msbsEqual_T_61; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_57 = _res_hit_lsbsLess_T_56 | _res_hit_T_57; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_59 = ~_res_hit_lsbsLess_T_58; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_60 = {_res_hit_lsbsLess_T_59[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_61 = ~_res_hit_lsbsLess_T_60; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_62 = _res_hit_lsbsLess_T_61[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_8 = _res_hit_lsbsLess_T_57 < _res_hit_lsbsLess_T_62; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_58 = res_hit_msbsEqual_8 & res_hit_lsbsLess_8; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_59 = res_hit_msbsLess_8 | _res_hit_T_58; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_60 = ~_res_hit_T_59; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_56 = ~_res_hit_msbsLess_T_55; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_57 = {_res_hit_msbsLess_T_56[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_58 = ~_res_hit_msbsLess_T_57; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_59 = _res_hit_msbsLess_T_58[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_9 = _res_hit_msbsLess_T_54 < _res_hit_msbsLess_T_59; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_65 = ~_res_hit_msbsEqual_T_64; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_66 = {_res_hit_msbsEqual_T_65[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_67 = ~_res_hit_msbsEqual_T_66; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_68 = _res_hit_msbsEqual_T_67[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_69 = _res_hit_msbsEqual_T_63 ^ _res_hit_msbsEqual_T_68; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_9 = _res_hit_msbsEqual_T_69 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_64 = _res_hit_lsbsLess_T_63; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_66 = ~_res_hit_lsbsLess_T_65; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_67 = {_res_hit_lsbsLess_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_68 = ~_res_hit_lsbsLess_T_67; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_69 = _res_hit_lsbsLess_T_68[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_9 = _res_hit_lsbsLess_T_64 < _res_hit_lsbsLess_T_69; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_61 = res_hit_msbsEqual_9 & res_hit_lsbsLess_9; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_62 = res_hit_msbsLess_9 | _res_hit_T_61; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_63 = _res_hit_T_60 & _res_hit_T_62; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_64 = _res_hit_T_54 & _res_hit_T_63; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_4 = _res_hit_T_52 ? _res_hit_T_53 : _res_hit_T_64; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_9 = _res_aligned_lsbMask_T_8[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_4 = ~_res_aligned_lsbMask_T_9; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_70 = ~_res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_71 = {_res_aligned_straddlesLowerBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_72 = ~_res_aligned_straddlesLowerBound_T_71; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_73 = _res_aligned_straddlesLowerBound_T_72[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_74 = _res_aligned_straddlesLowerBound_T_68 ^ _res_aligned_straddlesLowerBound_T_73; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_75 = _res_aligned_straddlesLowerBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_77 = ~_res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_78 = {_res_aligned_straddlesLowerBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_79 = ~_res_aligned_straddlesLowerBound_T_78; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_80 = _res_aligned_straddlesLowerBound_T_79[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_82 = ~_res_aligned_straddlesLowerBound_T_81; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_83 = _res_aligned_straddlesLowerBound_T_80 & _res_aligned_straddlesLowerBound_T_82; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_84 = |_res_aligned_straddlesLowerBound_T_83; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_4 = _res_aligned_straddlesLowerBound_T_75 & _res_aligned_straddlesLowerBound_T_84; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_70 = ~_res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_71 = {_res_aligned_straddlesUpperBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_72 = ~_res_aligned_straddlesUpperBound_T_71; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_73 = _res_aligned_straddlesUpperBound_T_72[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_74 = _res_aligned_straddlesUpperBound_T_68 ^ _res_aligned_straddlesUpperBound_T_73; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_75 = _res_aligned_straddlesUpperBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_77 = ~_res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_78 = {_res_aligned_straddlesUpperBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_79 = ~_res_aligned_straddlesUpperBound_T_78; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_80 = _res_aligned_straddlesUpperBound_T_79[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_82 = _res_aligned_straddlesUpperBound_T_81 | res_aligned_lsbMask_4; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_83 = _res_aligned_straddlesUpperBound_T_80 & _res_aligned_straddlesUpperBound_T_82; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_84 = |_res_aligned_straddlesUpperBound_T_83; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_4 = _res_aligned_straddlesUpperBound_T_75 & _res_aligned_straddlesUpperBound_T_84; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_4 = res_aligned_straddlesLowerBound_4 | res_aligned_straddlesUpperBound_4; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_4 = ~_res_aligned_rangeAligned_T_4; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_13 = ~_res_aligned_pow2Aligned_T_12; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_14 = res_aligned_lsbMask_4 & _res_aligned_pow2Aligned_T_13; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_4 = _res_aligned_pow2Aligned_T_14 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_4 = _res_aligned_T_4 ? res_aligned_pow2Aligned_4 : res_aligned_rangeAligned_4; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_181; // @[PMP.scala:168:32]
assign _res_T_181 = _GEN_22; // @[PMP.scala:168:32]
wire _res_T_200; // @[PMP.scala:177:61]
assign _res_T_200 = _GEN_22; // @[PMP.scala:168:32, :177:61]
wire _res_T_204; // @[PMP.scala:178:63]
assign _res_T_204 = _GEN_22; // @[PMP.scala:168:32, :178:63]
wire _GEN_23 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_182; // @[PMP.scala:168:32]
assign _res_T_182 = _GEN_23; // @[PMP.scala:168:32]
wire _res_T_209; // @[PMP.scala:177:61]
assign _res_T_209 = _GEN_23; // @[PMP.scala:168:32, :177:61]
wire _res_T_213; // @[PMP.scala:178:63]
assign _res_T_213 = _GEN_23; // @[PMP.scala:168:32, :178:63]
wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_24 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_24; // @[PMP.scala:174:26]
assign res_hi_24 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_25; // @[PMP.scala:174:26]
assign res_hi_25 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_26; // @[PMP.scala:174:26]
assign res_hi_26 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_27; // @[PMP.scala:174:26]
assign res_hi_27 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_28; // @[PMP.scala:174:26]
assign res_hi_28 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_29; // @[PMP.scala:174:26]
assign res_hi_29 = _GEN_24; // @[PMP.scala:174:26]
wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}]
wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_199 = _res_T_198 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}]
wire _GEN_25 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_202; // @[PMP.scala:178:32]
assign _res_T_202 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_211; // @[PMP.scala:178:32]
assign _res_T_211 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_220; // @[PMP.scala:178:32]
assign _res_T_220 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_203 = _res_T_202 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}]
wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_208 = _res_T_207 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}]
wire _res_T_212 = _res_T_211 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}]
wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_217 = _res_T_216 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}]
wire _res_T_221 = _res_T_220 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26]
wire res_cur_4_cfg_x; // @[PMP.scala:181:23]
wire res_cur_4_cfg_w; // @[PMP.scala:181:23]
wire res_cur_4_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_9 = res_aligned_4 & _res_cur_cfg_r_T_8; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_9 = res_aligned_4 & _res_cur_cfg_w_T_8; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_9 = res_aligned_4 & _res_cur_cfg_x_T_8; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26]
wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_65 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_5 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_16 = _res_hit_lsbMask_T_15[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_17 = ~_res_hit_lsbMask_T_16; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_56 = io_pmp_2_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_15 = io_pmp_2_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_5 = {_res_hit_msbMatch_T_56, _res_aligned_pow2Aligned_T_15 | _res_hit_lsbMask_T_17}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_52 = ~_res_hit_msbMatch_T_51; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_53 = {_res_hit_msbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_54 = ~_res_hit_msbMatch_T_53; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_55 = _res_hit_msbMatch_T_54[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_57 = _res_hit_msbMatch_T_50 ^ _res_hit_msbMatch_T_55; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_58 = ~_res_hit_msbMatch_T_56; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_59 = _res_hit_msbMatch_T_57 & _res_hit_msbMatch_T_58; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_52 = ~_res_hit_lsbMatch_T_51; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_53 = {_res_hit_lsbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_54 = ~_res_hit_lsbMatch_T_53; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_55 = _res_hit_lsbMatch_T_54[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_56 = res_hit_lsbMask_5[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_57 = _res_hit_lsbMatch_T_50 ^ _res_hit_lsbMatch_T_55; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_58 = ~_res_hit_lsbMatch_T_56; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_66 = res_hit_msbMatch_5 & res_hit_lsbMatch_5; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_67 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_69 = _res_hit_T_68[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_70 = ~_res_hit_T_69; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_26 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_61; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_61 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_71; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_71 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_72; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_72 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_86 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_93 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_61; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_61; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_79; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_79 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_92; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_92 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_93; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_93 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_103 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_110 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_62 = ~_res_hit_msbsLess_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_63 = {_res_hit_msbsLess_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_64 = ~_res_hit_msbsLess_T_63; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_65 = _res_hit_msbsLess_T_64[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_10 = _res_hit_msbsLess_T_60 < _res_hit_msbsLess_T_65; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_72 = ~_res_hit_msbsEqual_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_73 = {_res_hit_msbsEqual_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_74 = ~_res_hit_msbsEqual_T_73; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_75 = _res_hit_msbsEqual_T_74[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_76 = _res_hit_msbsEqual_T_70 ^ _res_hit_msbsEqual_T_75; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_71 = _res_hit_lsbsLess_T_70 | _res_hit_T_70; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_73 = ~_res_hit_lsbsLess_T_72; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_74 = {_res_hit_lsbsLess_T_73[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_75 = ~_res_hit_lsbsLess_T_74; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_76 = _res_hit_lsbsLess_T_75[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_10 = _res_hit_lsbsLess_T_71 < _res_hit_lsbsLess_T_76; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_71 = res_hit_msbsEqual_10 & res_hit_lsbsLess_10; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_72 = res_hit_msbsLess_10 | _res_hit_T_71; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_73 = ~_res_hit_T_72; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_68 = ~_res_hit_msbsLess_T_67; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_69 = {_res_hit_msbsLess_T_68[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_70 = ~_res_hit_msbsLess_T_69; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_71 = _res_hit_msbsLess_T_70[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_11 = _res_hit_msbsLess_T_66 < _res_hit_msbsLess_T_71; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_79 = ~_res_hit_msbsEqual_T_78; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_80 = {_res_hit_msbsEqual_T_79[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_81 = ~_res_hit_msbsEqual_T_80; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_82 = _res_hit_msbsEqual_T_81[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_83 = _res_hit_msbsEqual_T_77 ^ _res_hit_msbsEqual_T_82; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_11 = _res_hit_msbsEqual_T_83 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_78 = _res_hit_lsbsLess_T_77; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_80 = ~_res_hit_lsbsLess_T_79; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_81 = {_res_hit_lsbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_82 = ~_res_hit_lsbsLess_T_81; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_83 = _res_hit_lsbsLess_T_82[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_11 = _res_hit_lsbsLess_T_78 < _res_hit_lsbsLess_T_83; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_74 = res_hit_msbsEqual_11 & res_hit_lsbsLess_11; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_75 = res_hit_msbsLess_11 | _res_hit_T_74; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_76 = _res_hit_T_73 & _res_hit_T_75; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_77 = _res_hit_T_67 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_5 = _res_hit_T_65 ? _res_hit_T_66 : _res_hit_T_77; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_11 = _res_aligned_lsbMask_T_10[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_5 = ~_res_aligned_lsbMask_T_11; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_87 = ~_res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_88 = {_res_aligned_straddlesLowerBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_89 = ~_res_aligned_straddlesLowerBound_T_88; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_90 = _res_aligned_straddlesLowerBound_T_89[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_91 = _res_aligned_straddlesLowerBound_T_85 ^ _res_aligned_straddlesLowerBound_T_90; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_92 = _res_aligned_straddlesLowerBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_94 = ~_res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_95 = {_res_aligned_straddlesLowerBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_96 = ~_res_aligned_straddlesLowerBound_T_95; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_97 = _res_aligned_straddlesLowerBound_T_96[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_99 = ~_res_aligned_straddlesLowerBound_T_98; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_100 = _res_aligned_straddlesLowerBound_T_97 & _res_aligned_straddlesLowerBound_T_99; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_101 = |_res_aligned_straddlesLowerBound_T_100; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_5 = _res_aligned_straddlesLowerBound_T_92 & _res_aligned_straddlesLowerBound_T_101; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_87 = ~_res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_88 = {_res_aligned_straddlesUpperBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_89 = ~_res_aligned_straddlesUpperBound_T_88; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_90 = _res_aligned_straddlesUpperBound_T_89[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_91 = _res_aligned_straddlesUpperBound_T_85 ^ _res_aligned_straddlesUpperBound_T_90; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_92 = _res_aligned_straddlesUpperBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_94 = ~_res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_95 = {_res_aligned_straddlesUpperBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_96 = ~_res_aligned_straddlesUpperBound_T_95; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_97 = _res_aligned_straddlesUpperBound_T_96[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_99 = _res_aligned_straddlesUpperBound_T_98 | res_aligned_lsbMask_5; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_100 = _res_aligned_straddlesUpperBound_T_97 & _res_aligned_straddlesUpperBound_T_99; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_101 = |_res_aligned_straddlesUpperBound_T_100; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_5 = _res_aligned_straddlesUpperBound_T_92 & _res_aligned_straddlesUpperBound_T_101; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_5 = res_aligned_straddlesLowerBound_5 | res_aligned_straddlesUpperBound_5; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_5 = ~_res_aligned_rangeAligned_T_5; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_16 = ~_res_aligned_pow2Aligned_T_15; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_17 = res_aligned_lsbMask_5 & _res_aligned_pow2Aligned_T_16; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_5 = _res_aligned_pow2Aligned_T_17 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_5 = _res_aligned_T_5 ? res_aligned_pow2Aligned_5 : res_aligned_rangeAligned_5; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_226; // @[PMP.scala:168:32]
assign _res_T_226 = _GEN_27; // @[PMP.scala:168:32]
wire _res_T_245; // @[PMP.scala:177:61]
assign _res_T_245 = _GEN_27; // @[PMP.scala:168:32, :177:61]
wire _res_T_249; // @[PMP.scala:178:63]
assign _res_T_249 = _GEN_27; // @[PMP.scala:168:32, :178:63]
wire _GEN_28 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_227; // @[PMP.scala:168:32]
assign _res_T_227 = _GEN_28; // @[PMP.scala:168:32]
wire _res_T_254; // @[PMP.scala:177:61]
assign _res_T_254 = _GEN_28; // @[PMP.scala:168:32, :177:61]
wire _res_T_258; // @[PMP.scala:178:63]
assign _res_T_258 = _GEN_28; // @[PMP.scala:168:32, :178:63]
wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_29 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_30; // @[PMP.scala:174:26]
assign res_hi_30 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_31; // @[PMP.scala:174:26]
assign res_hi_31 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_32; // @[PMP.scala:174:26]
assign res_hi_32 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_33; // @[PMP.scala:174:26]
assign res_hi_33 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_34; // @[PMP.scala:174:26]
assign res_hi_34 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_35; // @[PMP.scala:174:26]
assign res_hi_35 = _GEN_29; // @[PMP.scala:174:26]
wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}]
wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_244 = _res_T_243 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}]
wire _GEN_30 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_247; // @[PMP.scala:178:32]
assign _res_T_247 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_256; // @[PMP.scala:178:32]
assign _res_T_256 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_265; // @[PMP.scala:178:32]
assign _res_T_265 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_248 = _res_T_247 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}]
wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_253 = _res_T_252 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}]
wire _res_T_257 = _res_T_256 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}]
wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_262 = _res_T_261 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}]
wire _res_T_266 = _res_T_265 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26]
wire res_cur_5_cfg_x; // @[PMP.scala:181:23]
wire res_cur_5_cfg_w; // @[PMP.scala:181:23]
wire res_cur_5_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_11 = res_aligned_5 & _res_cur_cfg_r_T_10; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_11 = res_aligned_5 & _res_cur_cfg_w_T_10; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_11 = res_aligned_5 & _res_cur_cfg_x_T_10; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26]
wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_78 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_6 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_19 = _res_hit_lsbMask_T_18[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_20 = ~_res_hit_lsbMask_T_19; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_66 = io_pmp_1_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_18 = io_pmp_1_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_6 = {_res_hit_msbMatch_T_66, _res_aligned_pow2Aligned_T_18 | _res_hit_lsbMask_T_20}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_62 = ~_res_hit_msbMatch_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_63 = {_res_hit_msbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_64 = ~_res_hit_msbMatch_T_63; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_65 = _res_hit_msbMatch_T_64[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_67 = _res_hit_msbMatch_T_60 ^ _res_hit_msbMatch_T_65; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_68 = ~_res_hit_msbMatch_T_66; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_69 = _res_hit_msbMatch_T_67 & _res_hit_msbMatch_T_68; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_62 = ~_res_hit_lsbMatch_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_63 = {_res_hit_lsbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_64 = ~_res_hit_lsbMatch_T_63; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_65 = _res_hit_lsbMatch_T_64[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_66 = res_hit_lsbMask_6[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_67 = _res_hit_lsbMatch_T_60 ^ _res_hit_lsbMatch_T_65; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_68 = ~_res_hit_lsbMatch_T_66; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_79 = res_hit_msbMatch_6 & res_hit_lsbMatch_6; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_80 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_82 = _res_hit_T_81[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_83 = ~_res_hit_T_82; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_31 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_73; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_73 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_85; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_85 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_86; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_86 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_103 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_110 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_71; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_71; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_91; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_91 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_106; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_106 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_107; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_107 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_120 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_127 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_74 = ~_res_hit_msbsLess_T_73; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_75 = {_res_hit_msbsLess_T_74[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_76 = ~_res_hit_msbsLess_T_75; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_77 = _res_hit_msbsLess_T_76[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_12 = _res_hit_msbsLess_T_72 < _res_hit_msbsLess_T_77; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_86 = ~_res_hit_msbsEqual_T_85; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_87 = {_res_hit_msbsEqual_T_86[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_88 = ~_res_hit_msbsEqual_T_87; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_89 = _res_hit_msbsEqual_T_88[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_90 = _res_hit_msbsEqual_T_84 ^ _res_hit_msbsEqual_T_89; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_85 = _res_hit_lsbsLess_T_84 | _res_hit_T_83; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_87 = ~_res_hit_lsbsLess_T_86; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_88 = {_res_hit_lsbsLess_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_89 = ~_res_hit_lsbsLess_T_88; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_90 = _res_hit_lsbsLess_T_89[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_12 = _res_hit_lsbsLess_T_85 < _res_hit_lsbsLess_T_90; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_84 = res_hit_msbsEqual_12 & res_hit_lsbsLess_12; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_85 = res_hit_msbsLess_12 | _res_hit_T_84; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_86 = ~_res_hit_T_85; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_80 = ~_res_hit_msbsLess_T_79; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_81 = {_res_hit_msbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_82 = ~_res_hit_msbsLess_T_81; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_83 = _res_hit_msbsLess_T_82[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_13 = _res_hit_msbsLess_T_78 < _res_hit_msbsLess_T_83; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_93 = ~_res_hit_msbsEqual_T_92; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_94 = {_res_hit_msbsEqual_T_93[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_95 = ~_res_hit_msbsEqual_T_94; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_96 = _res_hit_msbsEqual_T_95[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_97 = _res_hit_msbsEqual_T_91 ^ _res_hit_msbsEqual_T_96; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_13 = _res_hit_msbsEqual_T_97 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_92 = _res_hit_lsbsLess_T_91; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_94 = ~_res_hit_lsbsLess_T_93; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_95 = {_res_hit_lsbsLess_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_96 = ~_res_hit_lsbsLess_T_95; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_97 = _res_hit_lsbsLess_T_96[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_13 = _res_hit_lsbsLess_T_92 < _res_hit_lsbsLess_T_97; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_87 = res_hit_msbsEqual_13 & res_hit_lsbsLess_13; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_88 = res_hit_msbsLess_13 | _res_hit_T_87; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_89 = _res_hit_T_86 & _res_hit_T_88; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_90 = _res_hit_T_80 & _res_hit_T_89; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_6 = _res_hit_T_78 ? _res_hit_T_79 : _res_hit_T_90; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_13 = _res_aligned_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_6 = ~_res_aligned_lsbMask_T_13; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_104 = ~_res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_105 = {_res_aligned_straddlesLowerBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_106 = ~_res_aligned_straddlesLowerBound_T_105; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_107 = _res_aligned_straddlesLowerBound_T_106[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_108 = _res_aligned_straddlesLowerBound_T_102 ^ _res_aligned_straddlesLowerBound_T_107; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_109 = _res_aligned_straddlesLowerBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_111 = ~_res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_112 = {_res_aligned_straddlesLowerBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_113 = ~_res_aligned_straddlesLowerBound_T_112; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_114 = _res_aligned_straddlesLowerBound_T_113[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_116 = ~_res_aligned_straddlesLowerBound_T_115; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_117 = _res_aligned_straddlesLowerBound_T_114 & _res_aligned_straddlesLowerBound_T_116; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_118 = |_res_aligned_straddlesLowerBound_T_117; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_6 = _res_aligned_straddlesLowerBound_T_109 & _res_aligned_straddlesLowerBound_T_118; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_104 = ~_res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_105 = {_res_aligned_straddlesUpperBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_106 = ~_res_aligned_straddlesUpperBound_T_105; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_107 = _res_aligned_straddlesUpperBound_T_106[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_108 = _res_aligned_straddlesUpperBound_T_102 ^ _res_aligned_straddlesUpperBound_T_107; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_109 = _res_aligned_straddlesUpperBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_111 = ~_res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_112 = {_res_aligned_straddlesUpperBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_113 = ~_res_aligned_straddlesUpperBound_T_112; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_114 = _res_aligned_straddlesUpperBound_T_113[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_116 = _res_aligned_straddlesUpperBound_T_115 | res_aligned_lsbMask_6; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_117 = _res_aligned_straddlesUpperBound_T_114 & _res_aligned_straddlesUpperBound_T_116; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_118 = |_res_aligned_straddlesUpperBound_T_117; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_6 = _res_aligned_straddlesUpperBound_T_109 & _res_aligned_straddlesUpperBound_T_118; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_6 = res_aligned_straddlesLowerBound_6 | res_aligned_straddlesUpperBound_6; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_6 = ~_res_aligned_rangeAligned_T_6; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_19 = ~_res_aligned_pow2Aligned_T_18; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_20 = res_aligned_lsbMask_6 & _res_aligned_pow2Aligned_T_19; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_6 = _res_aligned_pow2Aligned_T_20 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_6 = _res_aligned_T_6 ? res_aligned_pow2Aligned_6 : res_aligned_rangeAligned_6; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_271; // @[PMP.scala:168:32]
assign _res_T_271 = _GEN_32; // @[PMP.scala:168:32]
wire _res_T_290; // @[PMP.scala:177:61]
assign _res_T_290 = _GEN_32; // @[PMP.scala:168:32, :177:61]
wire _res_T_294; // @[PMP.scala:178:63]
assign _res_T_294 = _GEN_32; // @[PMP.scala:168:32, :178:63]
wire _GEN_33 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_272; // @[PMP.scala:168:32]
assign _res_T_272 = _GEN_33; // @[PMP.scala:168:32]
wire _res_T_299; // @[PMP.scala:177:61]
assign _res_T_299 = _GEN_33; // @[PMP.scala:168:32, :177:61]
wire _res_T_303; // @[PMP.scala:178:63]
assign _res_T_303 = _GEN_33; // @[PMP.scala:168:32, :178:63]
wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_34 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_36; // @[PMP.scala:174:26]
assign res_hi_36 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_37; // @[PMP.scala:174:26]
assign res_hi_37 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_38; // @[PMP.scala:174:26]
assign res_hi_38 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_39; // @[PMP.scala:174:26]
assign res_hi_39 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_40; // @[PMP.scala:174:26]
assign res_hi_40 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_41; // @[PMP.scala:174:26]
assign res_hi_41 = _GEN_34; // @[PMP.scala:174:26]
wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}]
wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_289 = _res_T_288 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}]
wire _GEN_35 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_292; // @[PMP.scala:178:32]
assign _res_T_292 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_301; // @[PMP.scala:178:32]
assign _res_T_301 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_310; // @[PMP.scala:178:32]
assign _res_T_310 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_293 = _res_T_292 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}]
wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_298 = _res_T_297 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}]
wire _res_T_302 = _res_T_301 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}]
wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_307 = _res_T_306 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}]
wire _res_T_311 = _res_T_310 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26]
wire res_cur_6_cfg_x; // @[PMP.scala:181:23]
wire res_cur_6_cfg_w; // @[PMP.scala:181:23]
wire res_cur_6_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_13 = res_aligned_6 & _res_cur_cfg_r_T_12; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_13 = res_aligned_6 & _res_cur_cfg_w_T_12; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_13 = res_aligned_6 & _res_cur_cfg_x_T_12; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26]
wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_91 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_7 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_22 = _res_hit_lsbMask_T_21[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_23 = ~_res_hit_lsbMask_T_22; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_76 = io_pmp_0_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_21 = io_pmp_0_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_7 = {_res_hit_msbMatch_T_76, _res_aligned_pow2Aligned_T_21 | _res_hit_lsbMask_T_23}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_72 = ~_res_hit_msbMatch_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_73 = {_res_hit_msbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_74 = ~_res_hit_msbMatch_T_73; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_75 = _res_hit_msbMatch_T_74[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_77 = _res_hit_msbMatch_T_70 ^ _res_hit_msbMatch_T_75; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_78 = ~_res_hit_msbMatch_T_76; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_79 = _res_hit_msbMatch_T_77 & _res_hit_msbMatch_T_78; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_72 = ~_res_hit_lsbMatch_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_73 = {_res_hit_lsbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_74 = ~_res_hit_lsbMatch_T_73; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_75 = _res_hit_lsbMatch_T_74[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_76 = res_hit_lsbMask_7[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_77 = _res_hit_lsbMatch_T_70 ^ _res_hit_lsbMatch_T_75; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_78 = ~_res_hit_lsbMatch_T_76; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_92 = res_hit_msbMatch_7 & res_hit_lsbMatch_7; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_93 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_95 = _res_hit_T_94[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_96 = ~_res_hit_T_95; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbsEqual_T_104 = _res_hit_msbsEqual_T_98; // @[PMP.scala:81:{27,41}]
wire res_hit_msbsEqual_14 = _res_hit_msbsEqual_T_104 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_99 = _res_hit_lsbsLess_T_98 | _res_hit_T_96; // @[package.scala:243:46]
wire [31:0] _res_hit_msbsLess_T_92 = ~_res_hit_msbsLess_T_91; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_93 = {_res_hit_msbsLess_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_94 = ~_res_hit_msbsLess_T_93; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_95 = _res_hit_msbsLess_T_94[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_15 = _res_hit_msbsLess_T_90 < _res_hit_msbsLess_T_95; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_107 = ~_res_hit_msbsEqual_T_106; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_108 = {_res_hit_msbsEqual_T_107[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_109 = ~_res_hit_msbsEqual_T_108; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_110 = _res_hit_msbsEqual_T_109[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_111 = _res_hit_msbsEqual_T_105 ^ _res_hit_msbsEqual_T_110; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_15 = _res_hit_msbsEqual_T_111 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_106 = _res_hit_lsbsLess_T_105; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_108 = ~_res_hit_lsbsLess_T_107; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_109 = {_res_hit_lsbsLess_T_108[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_110 = ~_res_hit_lsbsLess_T_109; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_111 = _res_hit_lsbsLess_T_110[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_15 = _res_hit_lsbsLess_T_106 < _res_hit_lsbsLess_T_111; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_100 = res_hit_msbsEqual_15 & res_hit_lsbsLess_15; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_101 = res_hit_msbsLess_15 | _res_hit_T_100; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_102 = _res_hit_T_101; // @[PMP.scala:83:16, :94:48]
wire _res_hit_T_103 = _res_hit_T_93 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_7 = _res_hit_T_91 ? _res_hit_T_92 : _res_hit_T_103; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_15 = _res_aligned_lsbMask_T_14[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_7 = ~_res_aligned_lsbMask_T_15; // @[package.scala:243:{46,76}]
wire [28:0] _res_aligned_straddlesLowerBound_T_125 = _res_aligned_straddlesLowerBound_T_119; // @[PMP.scala:123:{35,49}]
wire _res_aligned_straddlesLowerBound_T_126 = _res_aligned_straddlesLowerBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [2:0] _res_aligned_straddlesLowerBound_T_133 = ~_res_aligned_straddlesLowerBound_T_132; // @[PMP.scala:123:{127,129}]
wire [31:0] _res_aligned_straddlesUpperBound_T_121 = ~_res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_122 = {_res_aligned_straddlesUpperBound_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_123 = ~_res_aligned_straddlesUpperBound_T_122; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_124 = _res_aligned_straddlesUpperBound_T_123[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_125 = _res_aligned_straddlesUpperBound_T_119 ^ _res_aligned_straddlesUpperBound_T_124; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_126 = _res_aligned_straddlesUpperBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_128 = ~_res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_129 = {_res_aligned_straddlesUpperBound_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_130 = ~_res_aligned_straddlesUpperBound_T_129; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_131 = _res_aligned_straddlesUpperBound_T_130[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_133 = _res_aligned_straddlesUpperBound_T_132 | res_aligned_lsbMask_7; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_134 = _res_aligned_straddlesUpperBound_T_131 & _res_aligned_straddlesUpperBound_T_133; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_135 = |_res_aligned_straddlesUpperBound_T_134; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_7 = _res_aligned_straddlesUpperBound_T_126 & _res_aligned_straddlesUpperBound_T_135; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_7 = res_aligned_straddlesUpperBound_7; // @[PMP.scala:124:85, :125:46]
wire res_aligned_rangeAligned_7 = ~_res_aligned_rangeAligned_T_7; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_22 = ~_res_aligned_pow2Aligned_T_21; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_23 = res_aligned_lsbMask_7 & _res_aligned_pow2Aligned_T_22; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_7 = _res_aligned_pow2Aligned_T_23 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_7 = _res_aligned_T_7 ? res_aligned_pow2Aligned_7 : res_aligned_rangeAligned_7; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_316; // @[PMP.scala:168:32]
assign _res_T_316 = _GEN_36; // @[PMP.scala:168:32]
wire _res_T_335; // @[PMP.scala:177:61]
assign _res_T_335 = _GEN_36; // @[PMP.scala:168:32, :177:61]
wire _res_T_339; // @[PMP.scala:178:63]
assign _res_T_339 = _GEN_36; // @[PMP.scala:168:32, :178:63]
wire _GEN_37 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_317; // @[PMP.scala:168:32]
assign _res_T_317 = _GEN_37; // @[PMP.scala:168:32]
wire _res_T_344; // @[PMP.scala:177:61]
assign _res_T_344 = _GEN_37; // @[PMP.scala:168:32, :177:61]
wire _res_T_348; // @[PMP.scala:178:63]
assign _res_T_348 = _GEN_37; // @[PMP.scala:168:32, :178:63]
wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_38 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_42; // @[PMP.scala:174:26]
assign res_hi_42 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_43; // @[PMP.scala:174:26]
assign res_hi_43 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_44; // @[PMP.scala:174:26]
assign res_hi_44 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_45; // @[PMP.scala:174:26]
assign res_hi_45 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_46; // @[PMP.scala:174:26]
assign res_hi_46 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_47; // @[PMP.scala:174:26]
assign res_hi_47 = _GEN_38; // @[PMP.scala:174:26]
wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}]
wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_334 = _res_T_333 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}]
wire _GEN_39 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_337; // @[PMP.scala:178:32]
assign _res_T_337 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_346; // @[PMP.scala:178:32]
assign _res_T_346 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_355; // @[PMP.scala:178:32]
assign _res_T_355 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_338 = _res_T_337 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}]
wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_343 = _res_T_342 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}]
wire _res_T_347 = _res_T_346 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}]
wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_352 = _res_T_351 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}]
wire _res_T_356 = _res_T_355 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26]
wire res_cur_7_cfg_x; // @[PMP.scala:181:23]
wire res_cur_7_cfg_w; // @[PMP.scala:181:23]
wire res_cur_7_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_15 = res_aligned_7 & _res_cur_cfg_r_T_14; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_15 = res_aligned_7 & _res_cur_cfg_w_T_14; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_15 = res_aligned_7 & _res_cur_cfg_x_T_14; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26]
wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8]
assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8]
assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8]
assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8]
assign io_r = io_r_0; // @[PMP.scala:143:7]
assign io_w = io_w_0; // @[PMP.scala:143:7]
assign io_x = io_x_0; // @[PMP.scala:143:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_36 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, in_vc : UInt<0>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}, flip out_credit_available : { `1` : UInt<1>[1], `0` : UInt<1>[4]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}}
inst route_buffer of Queue2_Flit_72
connect route_buffer.clock, clock
connect route_buffer.reset, reset
inst route_q of Queue2_RouteComputerResp_36
connect route_q.clock, clock
connect route_q.reset, reset
node _T = eq(UInt<4>(0h8), io.in.bits.egress_id)
node _T_1 = eq(UInt<3>(0h7), io.in.bits.egress_id)
node _T_2 = eq(UInt<2>(0h2), io.in.bits.egress_id)
node _T_3 = eq(UInt<1>(0h1), io.in.bits.egress_id)
node _T_4 = eq(UInt<3>(0h6), io.in.bits.egress_id)
node _T_5 = eq(UInt<2>(0h3), io.in.bits.egress_id)
node _T_6 = eq(UInt<3>(0h5), io.in.bits.egress_id)
node _T_7 = eq(UInt<3>(0h4), io.in.bits.egress_id)
node _T_8 = or(_T, _T_1)
node _T_9 = or(_T_8, _T_2)
node _T_10 = or(_T_9, _T_3)
node _T_11 = or(_T_10, _T_4)
node _T_12 = or(_T_11, _T_5)
node _T_13 = or(_T_12, _T_6)
node _T_14 = or(_T_13, _T_7)
node _T_15 = eq(_T_14, UInt<1>(0h0))
node _T_16 = and(io.in.valid, _T_15)
node _T_17 = eq(_T_16, UInt<1>(0h0))
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
node _T_20 = eq(_T_17, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf
assert(clock, _T_17, UInt<1>(0h1), "") : assert
connect route_buffer.io.enq.bits.head, io.in.bits.head
connect route_buffer.io.enq.bits.tail, io.in.bits.tail
connect route_buffer.io.enq.bits.flow.ingress_node, UInt<4>(0hc)
connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0)
connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h1)
node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<4>(0h8), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<3>(0h7), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<2>(0h2), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<1>(0h1), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_4 = eq(UInt<3>(0h6), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_5 = eq(UInt<2>(0h3), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_6 = eq(UInt<3>(0h5), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_7 = eq(UInt<3>(0h4), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<3>(0h7), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h6), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_10 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<1>(0h1), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_11 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_12 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_4, UInt<3>(0h5), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_13 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_5, UInt<2>(0h2), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_14 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_6, UInt<3>(0h4), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_15 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_7, UInt<2>(0h3), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_16 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_9)
node _route_buffer_io_enq_bits_flow_egress_node_T_17 = or(_route_buffer_io_enq_bits_flow_egress_node_T_16, _route_buffer_io_enq_bits_flow_egress_node_T_10)
node _route_buffer_io_enq_bits_flow_egress_node_T_18 = or(_route_buffer_io_enq_bits_flow_egress_node_T_17, _route_buffer_io_enq_bits_flow_egress_node_T_11)
node _route_buffer_io_enq_bits_flow_egress_node_T_19 = or(_route_buffer_io_enq_bits_flow_egress_node_T_18, _route_buffer_io_enq_bits_flow_egress_node_T_12)
node _route_buffer_io_enq_bits_flow_egress_node_T_20 = or(_route_buffer_io_enq_bits_flow_egress_node_T_19, _route_buffer_io_enq_bits_flow_egress_node_T_13)
node _route_buffer_io_enq_bits_flow_egress_node_T_21 = or(_route_buffer_io_enq_bits_flow_egress_node_T_20, _route_buffer_io_enq_bits_flow_egress_node_T_14)
node _route_buffer_io_enq_bits_flow_egress_node_T_22 = or(_route_buffer_io_enq_bits_flow_egress_node_T_21, _route_buffer_io_enq_bits_flow_egress_node_T_15)
wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<3>
connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_22
connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE
node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<4>(0h8), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<3>(0h7), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<2>(0h2), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<1>(0h1), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = eq(UInt<3>(0h6), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = eq(UInt<2>(0h3), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = eq(UInt<3>(0h5), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = eq(UInt<3>(0h4), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_5, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_14 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_6, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_15 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_7, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_16 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_9)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_17 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_16, _route_buffer_io_enq_bits_flow_egress_node_id_T_10)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_18 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_17, _route_buffer_io_enq_bits_flow_egress_node_id_T_11)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_19 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_18, _route_buffer_io_enq_bits_flow_egress_node_id_T_12)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_20 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_19, _route_buffer_io_enq_bits_flow_egress_node_id_T_13)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_21 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_20, _route_buffer_io_enq_bits_flow_egress_node_id_T_14)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_22 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_21, _route_buffer_io_enq_bits_flow_egress_node_id_T_15)
wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1>
connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_22
connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE
connect route_buffer.io.enq.bits.payload, io.in.bits.payload
invalidate route_buffer.io.enq.bits.virt_channel_id
connect io.router_req.bits.src_virt_id, UInt<1>(0h0)
connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id
connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node
connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id
connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node
connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id
node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<4>(0hc))
node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0))
node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T)
node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest)
node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2)
connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3
node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready)
node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head)
node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0))
node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2)
connect io.router_req.valid, _io_router_req_valid_T_3
node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0))
node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T)
node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest)
node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2)
connect io.in.ready, _io_in_ready_T_3
node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid)
connect route_q.io.enq.valid, _route_q_io_enq_valid_T
connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0]
connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1]
connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2]
connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3]
connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0]
node _T_21 = and(io.in.ready, io.in.valid)
node _T_22 = and(_T_21, io.in.bits.head)
node _T_23 = and(_T_22, at_dest)
when _T_23 :
connect route_q.io.enq.valid, UInt<1>(0h1)
connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0)
node _T_24 = eq(UInt<4>(0hd), io.in.bits.egress_id)
when _T_24 :
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1)
node _T_25 = eq(route_q.io.enq.ready, UInt<1>(0h0))
node _T_26 = and(route_q.io.enq.valid, _T_25)
node _T_27 = eq(_T_26, UInt<1>(0h0))
node _T_28 = asUInt(reset)
node _T_29 = eq(_T_28, UInt<1>(0h0))
when _T_29 :
node _T_30 = eq(_T_27, UInt<1>(0h0))
when _T_30 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1
assert(clock, _T_27, UInt<1>(0h1), "") : assert_1
inst vcalloc_buffer of Queue2_Flit_73
connect vcalloc_buffer.clock, clock
connect vcalloc_buffer.reset, reset
inst vcalloc_q of Queue1_VCAllocResp_36
connect vcalloc_q.clock, clock
connect vcalloc_q.reset, reset
connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node
connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id
connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node
connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id
connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload
connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail
connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head
connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0`
connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1`
connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow
connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0)
node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T)
node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1)
node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3)
node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4)
connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5
node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid)
node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head)
node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready)
node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready)
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3
node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T)
node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1)
node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3)
node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4)
node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6)
node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7)
connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8
node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid)
node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail)
connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1
node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T
connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3]
connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0]
node _T_31 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0))
node _T_32 = and(vcalloc_q.io.enq.valid, _T_31)
node _T_33 = eq(_T_32, UInt<1>(0h0))
node _T_34 = asUInt(reset)
node _T_35 = eq(_T_34, UInt<1>(0h0))
when _T_35 :
node _T_36 = eq(_T_33, UInt<1>(0h0))
when _T_36 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2
assert(clock, _T_33, UInt<1>(0h1), "") : assert_2
connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0`
connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1`
connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail
node c_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node c_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _c_T = cat(c_hi, c_lo)
node _c_T_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T)
node c_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node c_hi_1 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node _c_T_2 = cat(c_hi_1, c_lo_1)
node _c_T_3 = cat(io.out_credit_available.`1`[0], _c_T_2)
node _c_T_4 = and(_c_T_1, _c_T_3)
node c = neq(_c_T_4, UInt<1>(0h0))
node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid)
node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c)
node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0))
node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2)
connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3
node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid)
node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c)
node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0))
node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2)
connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3
node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T)
connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1
reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}, clock
connect io.out[0], out_bundle
node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
connect out_bundle.valid, _out_bundle_valid_T
connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits
connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0)
node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1])
node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node out_channel_oh_0 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node out_bundle_bits_out_virt_channel_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node out_bundle_bits_out_virt_channel_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo)
node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 2)
node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 1, 0)
node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1)
node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1)
node _out_bundle_bits_out_virt_channel_T_3 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 1)
node _out_bundle_bits_out_virt_channel_T_4 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_3)
node _out_bundle_bits_out_virt_channel_T_5 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_4, UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_6 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_7 = or(_out_bundle_bits_out_virt_channel_T_5, _out_bundle_bits_out_virt_channel_T_6)
wire _out_bundle_bits_out_virt_channel_WIRE : UInt<2>
connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_7
connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE
node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0))
node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T)
connect io.debug.va_stall, _io_debug_va_stall_T_1
node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T)
connect io.debug.sa_stall, _io_debug_sa_stall_T_1 | module IngressUnit_36( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [36:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [36:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [3:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire [36:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [36:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 4'h8; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 4'h7; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 4'h2; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 4'h6; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 4'h3; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 4'h5; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = io_in_bits_egress_id == 4'h4; // @[IngressUnit.scala:30:72]
wire [2:0] _route_buffer_io_enq_bits_flow_egress_node_T_16 = {3{_route_buffer_io_enq_bits_flow_egress_node_id_T}} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 3'h6 : 3'h0); // @[Mux.scala:30:73]
wire [2:0] _route_buffer_io_enq_bits_flow_egress_node_T_19 = {_route_buffer_io_enq_bits_flow_egress_node_T_16[2:1], _route_buffer_io_enq_bits_flow_egress_node_T_16[0] | _route_buffer_io_enq_bits_flow_egress_node_id_T_2} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h5 : 3'h0); // @[Mux.scala:30:73]
wire [3:0] route_buffer_io_enq_bits_flow_egress_node = {1'h0, _route_buffer_io_enq_bits_flow_egress_node_T_19[2] | _route_buffer_io_enq_bits_flow_egress_node_id_T_6, _route_buffer_io_enq_bits_flow_egress_node_T_19[1:0] | {_route_buffer_io_enq_bits_flow_egress_node_id_T_5, 1'h0} | {2{_route_buffer_io_enq_bits_flow_egress_node_id_T_7}}}; // @[Mux.scala:30:73]
wire _io_router_req_valid_T_1 = io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head; // @[IngressUnit.scala:26:28, :58:{38,67}]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to this FIRRTL code module FullyPortedRF :
input clock : Clock
input reset : Reset
output io : { flip arb_read_reqs : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<6>}[3], rrd_read_resps : UInt<65>[3], flip write_ports : { valid : UInt<1>, bits : { addr : UInt<7>, data : UInt<65>}}[2]}
node _T = eq(io.write_ports[0].valid, UInt<1>(0h0))
node _T_1 = eq(io.write_ports[1].valid, UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = neq(io.write_ports[0].bits.addr, io.write_ports[1].bits.addr)
node _T_4 = or(_T_2, _T_3)
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid ||\n") : printf
assert(clock, _T_4, UInt<1>(0h1), "") : assert
connect io.arb_read_reqs[0].ready, UInt<1>(0h1)
connect io.arb_read_reqs[1].ready, UInt<1>(0h1)
connect io.arb_read_reqs[2].ready, UInt<1>(0h1)
cmem regfile : UInt<65> [64]
reg io_rrd_read_resps_0_REG : UInt, clock
connect io_rrd_read_resps_0_REG, io.arb_read_reqs[0].bits
node _io_rrd_read_resps_0_T = or(io_rrd_read_resps_0_REG, UInt<6>(0h0))
node _io_rrd_read_resps_0_T_1 = bits(_io_rrd_read_resps_0_T, 5, 0)
infer mport io_rrd_read_resps_0_MPORT = regfile[_io_rrd_read_resps_0_T_1], clock
connect io.rrd_read_resps[0], io_rrd_read_resps_0_MPORT
reg io_rrd_read_resps_1_REG : UInt, clock
connect io_rrd_read_resps_1_REG, io.arb_read_reqs[1].bits
node _io_rrd_read_resps_1_T = or(io_rrd_read_resps_1_REG, UInt<6>(0h0))
node _io_rrd_read_resps_1_T_1 = bits(_io_rrd_read_resps_1_T, 5, 0)
infer mport io_rrd_read_resps_1_MPORT = regfile[_io_rrd_read_resps_1_T_1], clock
connect io.rrd_read_resps[1], io_rrd_read_resps_1_MPORT
reg io_rrd_read_resps_2_REG : UInt, clock
connect io_rrd_read_resps_2_REG, io.arb_read_reqs[2].bits
node _io_rrd_read_resps_2_T = or(io_rrd_read_resps_2_REG, UInt<6>(0h0))
node _io_rrd_read_resps_2_T_1 = bits(_io_rrd_read_resps_2_T, 5, 0)
infer mport io_rrd_read_resps_2_MPORT = regfile[_io_rrd_read_resps_2_T_1], clock
connect io.rrd_read_resps[2], io_rrd_read_resps_2_MPORT
when io.write_ports[0].valid :
node _T_8 = bits(io.write_ports[0].bits.addr, 5, 0)
infer mport MPORT = regfile[_T_8], clock
connect MPORT, io.write_ports[0].bits.data
when io.write_ports[1].valid :
node _T_9 = bits(io.write_ports[1].bits.addr, 5, 0)
infer mport MPORT_1 = regfile[_T_9], clock
connect MPORT_1, io.write_ports[1].bits.data | module FullyPortedRF( // @[regfile.scala:186:7]
input clock, // @[regfile.scala:186:7]
input reset, // @[regfile.scala:186:7]
input io_arb_read_reqs_0_valid, // @[regfile.scala:31:14]
input [5:0] io_arb_read_reqs_0_bits, // @[regfile.scala:31:14]
input io_arb_read_reqs_1_valid, // @[regfile.scala:31:14]
input [5:0] io_arb_read_reqs_1_bits, // @[regfile.scala:31:14]
input io_arb_read_reqs_2_valid, // @[regfile.scala:31:14]
input [5:0] io_arb_read_reqs_2_bits, // @[regfile.scala:31:14]
output [64:0] io_rrd_read_resps_0, // @[regfile.scala:31:14]
output [64:0] io_rrd_read_resps_1, // @[regfile.scala:31:14]
output [64:0] io_rrd_read_resps_2, // @[regfile.scala:31:14]
input io_write_ports_0_valid, // @[regfile.scala:31:14]
input [6:0] io_write_ports_0_bits_addr, // @[regfile.scala:31:14]
input [64:0] io_write_ports_0_bits_data, // @[regfile.scala:31:14]
input io_write_ports_1_valid, // @[regfile.scala:31:14]
input [6:0] io_write_ports_1_bits_addr, // @[regfile.scala:31:14]
input [64:0] io_write_ports_1_bits_data // @[regfile.scala:31:14]
);
wire io_arb_read_reqs_0_valid_0 = io_arb_read_reqs_0_valid; // @[regfile.scala:186:7]
wire [5:0] io_arb_read_reqs_0_bits_0 = io_arb_read_reqs_0_bits; // @[regfile.scala:186:7]
wire io_arb_read_reqs_1_valid_0 = io_arb_read_reqs_1_valid; // @[regfile.scala:186:7]
wire [5:0] io_arb_read_reqs_1_bits_0 = io_arb_read_reqs_1_bits; // @[regfile.scala:186:7]
wire io_arb_read_reqs_2_valid_0 = io_arb_read_reqs_2_valid; // @[regfile.scala:186:7]
wire [5:0] io_arb_read_reqs_2_bits_0 = io_arb_read_reqs_2_bits; // @[regfile.scala:186:7]
wire io_write_ports_0_valid_0 = io_write_ports_0_valid; // @[regfile.scala:186:7]
wire [6:0] io_write_ports_0_bits_addr_0 = io_write_ports_0_bits_addr; // @[regfile.scala:186:7]
wire [64:0] io_write_ports_0_bits_data_0 = io_write_ports_0_bits_data; // @[regfile.scala:186:7]
wire io_write_ports_1_valid_0 = io_write_ports_1_valid; // @[regfile.scala:186:7]
wire [6:0] io_write_ports_1_bits_addr_0 = io_write_ports_1_bits_addr; // @[regfile.scala:186:7]
wire [64:0] io_write_ports_1_bits_data_0 = io_write_ports_1_bits_data; // @[regfile.scala:186:7]
wire io_arb_read_reqs_0_ready = 1'h1; // @[regfile.scala:186:7]
wire io_arb_read_reqs_1_ready = 1'h1; // @[regfile.scala:186:7]
wire io_arb_read_reqs_2_ready = 1'h1; // @[regfile.scala:186:7]
wire [64:0] io_rrd_read_resps_0_0; // @[regfile.scala:186:7]
wire [64:0] io_rrd_read_resps_1_0; // @[regfile.scala:186:7]
wire [64:0] io_rrd_read_resps_2_0; // @[regfile.scala:186:7] |
Generate the Verilog code corresponding to this FIRRTL code module ITLB_2 :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip kill : UInt<1>}
invalidate io.ptw.customCSRs.csrs[0].sdata
invalidate io.ptw.customCSRs.csrs[0].set
invalidate io.ptw.customCSRs.csrs[0].stall
invalidate io.ptw.customCSRs.csrs[0].value
invalidate io.ptw.customCSRs.csrs[0].wdata
invalidate io.ptw.customCSRs.csrs[0].wen
invalidate io.ptw.customCSRs.csrs[0].ren
invalidate io.ptw.customCSRs.csrs[1].sdata
invalidate io.ptw.customCSRs.csrs[1].set
invalidate io.ptw.customCSRs.csrs[1].stall
invalidate io.ptw.customCSRs.csrs[1].value
invalidate io.ptw.customCSRs.csrs[1].wdata
invalidate io.ptw.customCSRs.csrs[1].wen
invalidate io.ptw.customCSRs.csrs[1].ren
invalidate io.ptw.customCSRs.csrs[2].sdata
invalidate io.ptw.customCSRs.csrs[2].set
invalidate io.ptw.customCSRs.csrs[2].stall
invalidate io.ptw.customCSRs.csrs[2].value
invalidate io.ptw.customCSRs.csrs[2].wdata
invalidate io.ptw.customCSRs.csrs[2].wen
invalidate io.ptw.customCSRs.csrs[2].ren
invalidate io.ptw.customCSRs.csrs[3].sdata
invalidate io.ptw.customCSRs.csrs[3].set
invalidate io.ptw.customCSRs.csrs[3].stall
invalidate io.ptw.customCSRs.csrs[3].value
invalidate io.ptw.customCSRs.csrs[3].wdata
invalidate io.ptw.customCSRs.csrs[3].wen
invalidate io.ptw.customCSRs.csrs[3].ren
node vpn = bits(io.req.bits.vaddr, 38, 12)
reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[4], valid : UInt<1>[4]}[8][1], clock
reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4], clock
reg special_entry : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock
regreset state : UInt<2>, clock, reset, UInt<2>(0h0)
reg r_refill_tag : UInt<27>, clock
reg r_superpage_repl_addr : UInt<2>, clock
reg r_sectored_repl_addr : UInt<3>, clock
reg r_sectored_hit : { valid : UInt<1>, bits : UInt<3>}, clock
reg r_superpage_hit : { valid : UInt<1>, bits : UInt<2>}, clock
reg r_vstage1_en : UInt<1>, clock
reg r_stage2_en : UInt<1>, clock
reg r_need_gpa : UInt<1>, clock
reg r_gpa_valid : UInt<1>, clock
reg r_gpa : UInt<39>, clock
reg r_gpa_vpn : UInt<27>, clock
reg r_gpa_is_pte : UInt<1>, clock
node priv_v = and(UInt<1>(0h0), io.req.bits.v)
node priv_s = bits(io.req.bits.prv, 0, 0)
node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1))
node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr)
node _stage1_en_T = bits(satp.mode, 3, 3)
node stage1_en = and(UInt<1>(0h1), _stage1_en_T)
node _vstage1_en_T = and(UInt<1>(0h0), priv_v)
node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3)
node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1)
node _stage2_en_T = and(UInt<1>(0h0), priv_v)
node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3)
node stage2_en = and(_stage2_en_T, _stage2_en_T_1)
node _vm_enabled_T = or(stage1_en, stage2_en)
node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm)
node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0))
node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2)
regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1)
node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T)
node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0))
node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2)
node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0)
node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid)
node _invalidate_refill_T = eq(state, UInt<2>(0h1))
node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3))
node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1)
node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid)
node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1))
wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _mpu_ppn_WIRE_1 : UInt<42>
connect _mpu_ppn_WIRE_1, special_entry.data[0]
node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0)
connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1
node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1)
connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2
node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2)
connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3
node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3)
connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4
node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4)
connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5
node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5)
connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6
node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6)
connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7
node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7)
connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8
node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8)
connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9
node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9)
connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10
node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10)
connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11
node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11)
connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12
node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12)
connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13
node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13)
connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14
node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14)
connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15
node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15)
connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16
node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16)
connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17
node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17)
connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18
node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18)
connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19
node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19)
connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20
node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20)
connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21
node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21)
connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22
node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22)
connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23
inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_112
connect mpu_ppn_barrier.clock, clock
connect mpu_ppn_barrier.reset, reset
connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage
connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c
connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff
connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa
connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal
connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp
connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr
connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px
connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw
connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr
connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx
connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw
connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr
connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx
connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw
connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf
connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf
connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2
connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final
connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw
connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g
connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u
connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn
node mpu_ppn_res = shr(mpu_ppn_barrier.io.y.ppn, 18)
node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1))
node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0))
node _mpu_ppn_T_24 = mux(mpu_ppn_ignore, vpn, UInt<1>(0h0))
node _mpu_ppn_T_25 = or(_mpu_ppn_T_24, mpu_ppn_barrier.io.y.ppn)
node _mpu_ppn_T_26 = bits(_mpu_ppn_T_25, 17, 9)
node _mpu_ppn_T_27 = cat(mpu_ppn_res, _mpu_ppn_T_26)
node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2))
node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0))
node _mpu_ppn_T_28 = mux(mpu_ppn_ignore_1, vpn, UInt<1>(0h0))
node _mpu_ppn_T_29 = or(_mpu_ppn_T_28, mpu_ppn_barrier.io.y.ppn)
node _mpu_ppn_T_30 = bits(_mpu_ppn_T_29, 8, 0)
node _mpu_ppn_T_31 = cat(_mpu_ppn_T_27, _mpu_ppn_T_30)
node _mpu_ppn_T_32 = shr(io.req.bits.vaddr, 12)
node _mpu_ppn_T_33 = mux(_mpu_ppn_T, _mpu_ppn_T_31, _mpu_ppn_T_32)
node mpu_ppn = mux(do_refill, refill_ppn, _mpu_ppn_T_33)
node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0)
node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T)
node _mpu_priv_T = or(do_refill, io.req.bits.passthrough)
node _mpu_priv_T_1 = and(UInt<1>(0h1), _mpu_priv_T)
node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv)
node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2)
inst pmp of PMPChecker_s2_2
connect pmp.clock, clock
connect pmp.reset, reset
connect pmp.io.addr, mpu_physaddr
connect pmp.io.size, io.req.bits.size
connect pmp.io.pmp[0].mask, io.ptw.pmp[0].mask
connect pmp.io.pmp[0].addr, io.ptw.pmp[0].addr
connect pmp.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r
connect pmp.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w
connect pmp.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x
connect pmp.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a
connect pmp.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res
connect pmp.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l
connect pmp.io.pmp[1].mask, io.ptw.pmp[1].mask
connect pmp.io.pmp[1].addr, io.ptw.pmp[1].addr
connect pmp.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r
connect pmp.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w
connect pmp.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x
connect pmp.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a
connect pmp.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res
connect pmp.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l
connect pmp.io.pmp[2].mask, io.ptw.pmp[2].mask
connect pmp.io.pmp[2].addr, io.ptw.pmp[2].addr
connect pmp.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r
connect pmp.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w
connect pmp.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x
connect pmp.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a
connect pmp.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res
connect pmp.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l
connect pmp.io.pmp[3].mask, io.ptw.pmp[3].mask
connect pmp.io.pmp[3].addr, io.ptw.pmp[3].addr
connect pmp.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r
connect pmp.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w
connect pmp.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x
connect pmp.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a
connect pmp.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res
connect pmp.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l
connect pmp.io.pmp[4].mask, io.ptw.pmp[4].mask
connect pmp.io.pmp[4].addr, io.ptw.pmp[4].addr
connect pmp.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r
connect pmp.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w
connect pmp.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x
connect pmp.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a
connect pmp.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res
connect pmp.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l
connect pmp.io.pmp[5].mask, io.ptw.pmp[5].mask
connect pmp.io.pmp[5].addr, io.ptw.pmp[5].addr
connect pmp.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r
connect pmp.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w
connect pmp.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x
connect pmp.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a
connect pmp.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res
connect pmp.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l
connect pmp.io.pmp[6].mask, io.ptw.pmp[6].mask
connect pmp.io.pmp[6].addr, io.ptw.pmp[6].addr
connect pmp.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r
connect pmp.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w
connect pmp.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x
connect pmp.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a
connect pmp.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res
connect pmp.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l
connect pmp.io.pmp[7].mask, io.ptw.pmp[7].mask
connect pmp.io.pmp[7].addr, io.ptw.pmp[7].addr
connect pmp.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r
connect pmp.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w
connect pmp.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x
connect pmp.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a
connect pmp.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res
connect pmp.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l
connect pmp.io.prv, mpu_priv
inst pma of PMAChecker_8
connect pma.clock, clock
connect pma.reset, reset
connect pma.io.paddr, mpu_physaddr
node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1))
node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0))
node _homogeneous_T_1 = cvt(_homogeneous_T)
node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000)))
node _homogeneous_T_3 = asSInt(_homogeneous_T_2)
node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0)))
node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000))
node _homogeneous_T_6 = cvt(_homogeneous_T_5)
node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000)))
node _homogeneous_T_8 = asSInt(_homogeneous_T_7)
node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0)))
node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_11 = cvt(_homogeneous_T_10)
node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000)))
node _homogeneous_T_13 = asSInt(_homogeneous_T_12)
node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0)))
node _homogeneous_T_15 = xor(mpu_physaddr, UInt<21>(0h100000))
node _homogeneous_T_16 = cvt(_homogeneous_T_15)
node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<18>(0h2f000)))
node _homogeneous_T_18 = asSInt(_homogeneous_T_17)
node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0)))
node _homogeneous_T_20 = xor(mpu_physaddr, UInt<26>(0h2000000))
node _homogeneous_T_21 = cvt(_homogeneous_T_20)
node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<17>(0h10000)))
node _homogeneous_T_23 = asSInt(_homogeneous_T_22)
node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0)))
node _homogeneous_T_25 = xor(mpu_physaddr, UInt<26>(0h2010000))
node _homogeneous_T_26 = cvt(_homogeneous_T_25)
node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<13>(0h1000)))
node _homogeneous_T_28 = asSInt(_homogeneous_T_27)
node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0)))
node _homogeneous_T_30 = xor(mpu_physaddr, UInt<28>(0h8000000))
node _homogeneous_T_31 = cvt(_homogeneous_T_30)
node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000)))
node _homogeneous_T_33 = asSInt(_homogeneous_T_32)
node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0)))
node _homogeneous_T_35 = xor(mpu_physaddr, UInt<28>(0hc000000))
node _homogeneous_T_36 = cvt(_homogeneous_T_35)
node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<27>(0h4000000)))
node _homogeneous_T_38 = asSInt(_homogeneous_T_37)
node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0)))
node _homogeneous_T_40 = xor(mpu_physaddr, UInt<29>(0h10020000))
node _homogeneous_T_41 = cvt(_homogeneous_T_40)
node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<13>(0h1000)))
node _homogeneous_T_43 = asSInt(_homogeneous_T_42)
node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0)))
node _homogeneous_T_45 = xor(mpu_physaddr, UInt<32>(0h80000000))
node _homogeneous_T_46 = cvt(_homogeneous_T_45)
node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<29>(0h10000000)))
node _homogeneous_T_48 = asSInt(_homogeneous_T_47)
node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0)))
node _homogeneous_T_50 = or(UInt<1>(0h0), _homogeneous_T_4)
node _homogeneous_T_51 = or(_homogeneous_T_50, _homogeneous_T_9)
node _homogeneous_T_52 = or(_homogeneous_T_51, _homogeneous_T_14)
node _homogeneous_T_53 = or(_homogeneous_T_52, _homogeneous_T_19)
node _homogeneous_T_54 = or(_homogeneous_T_53, _homogeneous_T_24)
node _homogeneous_T_55 = or(_homogeneous_T_54, _homogeneous_T_29)
node _homogeneous_T_56 = or(_homogeneous_T_55, _homogeneous_T_34)
node _homogeneous_T_57 = or(_homogeneous_T_56, _homogeneous_T_39)
node _homogeneous_T_58 = or(_homogeneous_T_57, _homogeneous_T_44)
node homogeneous = or(_homogeneous_T_58, _homogeneous_T_49)
node _homogeneous_T_59 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _homogeneous_T_60 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_61 = cvt(_homogeneous_T_60)
node _homogeneous_T_62 = and(_homogeneous_T_61, asSInt(UInt<33>(0h8a110000)))
node _homogeneous_T_63 = asSInt(_homogeneous_T_62)
node _homogeneous_T_64 = eq(_homogeneous_T_63, asSInt(UInt<1>(0h0)))
node _homogeneous_T_65 = or(UInt<1>(0h0), _homogeneous_T_64)
node _homogeneous_T_66 = eq(_homogeneous_T_65, UInt<1>(0h0))
node _homogeneous_T_67 = xor(mpu_physaddr, UInt<1>(0h0))
node _homogeneous_T_68 = cvt(_homogeneous_T_67)
node _homogeneous_T_69 = and(_homogeneous_T_68, asSInt(UInt<33>(0h9e113000)))
node _homogeneous_T_70 = asSInt(_homogeneous_T_69)
node _homogeneous_T_71 = eq(_homogeneous_T_70, asSInt(UInt<1>(0h0)))
node _homogeneous_T_72 = xor(mpu_physaddr, UInt<14>(0h3000))
node _homogeneous_T_73 = cvt(_homogeneous_T_72)
node _homogeneous_T_74 = and(_homogeneous_T_73, asSInt(UInt<33>(0h9e113000)))
node _homogeneous_T_75 = asSInt(_homogeneous_T_74)
node _homogeneous_T_76 = eq(_homogeneous_T_75, asSInt(UInt<1>(0h0)))
node _homogeneous_T_77 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_78 = cvt(_homogeneous_T_77)
node _homogeneous_T_79 = and(_homogeneous_T_78, asSInt(UInt<33>(0h9e110000)))
node _homogeneous_T_80 = asSInt(_homogeneous_T_79)
node _homogeneous_T_81 = eq(_homogeneous_T_80, asSInt(UInt<1>(0h0)))
node _homogeneous_T_82 = xor(mpu_physaddr, UInt<28>(0h8000000))
node _homogeneous_T_83 = cvt(_homogeneous_T_82)
node _homogeneous_T_84 = and(_homogeneous_T_83, asSInt(UInt<33>(0h9e110000)))
node _homogeneous_T_85 = asSInt(_homogeneous_T_84)
node _homogeneous_T_86 = eq(_homogeneous_T_85, asSInt(UInt<1>(0h0)))
node _homogeneous_T_87 = xor(mpu_physaddr, UInt<32>(0h80000000))
node _homogeneous_T_88 = cvt(_homogeneous_T_87)
node _homogeneous_T_89 = and(_homogeneous_T_88, asSInt(UInt<33>(0h90000000)))
node _homogeneous_T_90 = asSInt(_homogeneous_T_89)
node _homogeneous_T_91 = eq(_homogeneous_T_90, asSInt(UInt<1>(0h0)))
node _homogeneous_T_92 = or(UInt<1>(0h0), _homogeneous_T_71)
node _homogeneous_T_93 = or(_homogeneous_T_92, _homogeneous_T_76)
node _homogeneous_T_94 = or(_homogeneous_T_93, _homogeneous_T_81)
node _homogeneous_T_95 = or(_homogeneous_T_94, _homogeneous_T_86)
node _homogeneous_T_96 = or(_homogeneous_T_95, _homogeneous_T_91)
node _homogeneous_T_97 = xor(mpu_physaddr, UInt<28>(0h8000000))
node _homogeneous_T_98 = cvt(_homogeneous_T_97)
node _homogeneous_T_99 = and(_homogeneous_T_98, asSInt(UInt<33>(0h8e000000)))
node _homogeneous_T_100 = asSInt(_homogeneous_T_99)
node _homogeneous_T_101 = eq(_homogeneous_T_100, asSInt(UInt<1>(0h0)))
node _homogeneous_T_102 = xor(mpu_physaddr, UInt<32>(0h80000000))
node _homogeneous_T_103 = cvt(_homogeneous_T_102)
node _homogeneous_T_104 = and(_homogeneous_T_103, asSInt(UInt<33>(0h80000000)))
node _homogeneous_T_105 = asSInt(_homogeneous_T_104)
node _homogeneous_T_106 = eq(_homogeneous_T_105, asSInt(UInt<1>(0h0)))
node _homogeneous_T_107 = or(UInt<1>(0h0), _homogeneous_T_101)
node _homogeneous_T_108 = or(_homogeneous_T_107, _homogeneous_T_106)
node _homogeneous_T_109 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_110 = cvt(_homogeneous_T_109)
node _homogeneous_T_111 = and(_homogeneous_T_110, asSInt(UInt<33>(0h8a110000)))
node _homogeneous_T_112 = asSInt(_homogeneous_T_111)
node _homogeneous_T_113 = eq(_homogeneous_T_112, asSInt(UInt<1>(0h0)))
node _homogeneous_T_114 = or(UInt<1>(0h0), _homogeneous_T_113)
node _homogeneous_T_115 = eq(_homogeneous_T_114, UInt<1>(0h0))
node _homogeneous_T_116 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_117 = cvt(_homogeneous_T_116)
node _homogeneous_T_118 = and(_homogeneous_T_117, asSInt(UInt<33>(0h8a110000)))
node _homogeneous_T_119 = asSInt(_homogeneous_T_118)
node _homogeneous_T_120 = eq(_homogeneous_T_119, asSInt(UInt<1>(0h0)))
node _homogeneous_T_121 = or(UInt<1>(0h0), _homogeneous_T_120)
node _homogeneous_T_122 = eq(_homogeneous_T_121, UInt<1>(0h0))
node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3))
node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0))
node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1)
node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000)))
node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3)
node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0)))
node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5)
node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0))
node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T)
node prot_r = and(_prot_r_T_1, pmp.io.r)
node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0))
node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T)
node prot_w = and(_prot_w_T_1, pmp.io.w)
node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0))
node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T)
node prot_x = and(_prot_x_T_1, pmp.io.x)
node _sector_hits_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1])
node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0][0].valid[2])
node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0][0].valid[3])
node _sector_hits_T_3 = xor(sectored_entries[0][0].tag_vpn, vpn)
node _sector_hits_T_4 = shr(_sector_hits_T_3, 2)
node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0))
node _sector_hits_T_6 = eq(sectored_entries[0][0].tag_v, priv_v)
node _sector_hits_T_7 = and(_sector_hits_T_5, _sector_hits_T_6)
node sector_hits_0 = and(_sector_hits_T_2, _sector_hits_T_7)
node _sector_hits_T_8 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1])
node _sector_hits_T_9 = or(_sector_hits_T_8, sectored_entries[0][1].valid[2])
node _sector_hits_T_10 = or(_sector_hits_T_9, sectored_entries[0][1].valid[3])
node _sector_hits_T_11 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _sector_hits_T_12 = shr(_sector_hits_T_11, 2)
node _sector_hits_T_13 = eq(_sector_hits_T_12, UInt<1>(0h0))
node _sector_hits_T_14 = eq(sectored_entries[0][1].tag_v, priv_v)
node _sector_hits_T_15 = and(_sector_hits_T_13, _sector_hits_T_14)
node sector_hits_1 = and(_sector_hits_T_10, _sector_hits_T_15)
node _sector_hits_T_16 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1])
node _sector_hits_T_17 = or(_sector_hits_T_16, sectored_entries[0][2].valid[2])
node _sector_hits_T_18 = or(_sector_hits_T_17, sectored_entries[0][2].valid[3])
node _sector_hits_T_19 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _sector_hits_T_20 = shr(_sector_hits_T_19, 2)
node _sector_hits_T_21 = eq(_sector_hits_T_20, UInt<1>(0h0))
node _sector_hits_T_22 = eq(sectored_entries[0][2].tag_v, priv_v)
node _sector_hits_T_23 = and(_sector_hits_T_21, _sector_hits_T_22)
node sector_hits_2 = and(_sector_hits_T_18, _sector_hits_T_23)
node _sector_hits_T_24 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1])
node _sector_hits_T_25 = or(_sector_hits_T_24, sectored_entries[0][3].valid[2])
node _sector_hits_T_26 = or(_sector_hits_T_25, sectored_entries[0][3].valid[3])
node _sector_hits_T_27 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _sector_hits_T_28 = shr(_sector_hits_T_27, 2)
node _sector_hits_T_29 = eq(_sector_hits_T_28, UInt<1>(0h0))
node _sector_hits_T_30 = eq(sectored_entries[0][3].tag_v, priv_v)
node _sector_hits_T_31 = and(_sector_hits_T_29, _sector_hits_T_30)
node sector_hits_3 = and(_sector_hits_T_26, _sector_hits_T_31)
node _sector_hits_T_32 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1])
node _sector_hits_T_33 = or(_sector_hits_T_32, sectored_entries[0][4].valid[2])
node _sector_hits_T_34 = or(_sector_hits_T_33, sectored_entries[0][4].valid[3])
node _sector_hits_T_35 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _sector_hits_T_36 = shr(_sector_hits_T_35, 2)
node _sector_hits_T_37 = eq(_sector_hits_T_36, UInt<1>(0h0))
node _sector_hits_T_38 = eq(sectored_entries[0][4].tag_v, priv_v)
node _sector_hits_T_39 = and(_sector_hits_T_37, _sector_hits_T_38)
node sector_hits_4 = and(_sector_hits_T_34, _sector_hits_T_39)
node _sector_hits_T_40 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1])
node _sector_hits_T_41 = or(_sector_hits_T_40, sectored_entries[0][5].valid[2])
node _sector_hits_T_42 = or(_sector_hits_T_41, sectored_entries[0][5].valid[3])
node _sector_hits_T_43 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _sector_hits_T_44 = shr(_sector_hits_T_43, 2)
node _sector_hits_T_45 = eq(_sector_hits_T_44, UInt<1>(0h0))
node _sector_hits_T_46 = eq(sectored_entries[0][5].tag_v, priv_v)
node _sector_hits_T_47 = and(_sector_hits_T_45, _sector_hits_T_46)
node sector_hits_5 = and(_sector_hits_T_42, _sector_hits_T_47)
node _sector_hits_T_48 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1])
node _sector_hits_T_49 = or(_sector_hits_T_48, sectored_entries[0][6].valid[2])
node _sector_hits_T_50 = or(_sector_hits_T_49, sectored_entries[0][6].valid[3])
node _sector_hits_T_51 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _sector_hits_T_52 = shr(_sector_hits_T_51, 2)
node _sector_hits_T_53 = eq(_sector_hits_T_52, UInt<1>(0h0))
node _sector_hits_T_54 = eq(sectored_entries[0][6].tag_v, priv_v)
node _sector_hits_T_55 = and(_sector_hits_T_53, _sector_hits_T_54)
node sector_hits_6 = and(_sector_hits_T_50, _sector_hits_T_55)
node _sector_hits_T_56 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1])
node _sector_hits_T_57 = or(_sector_hits_T_56, sectored_entries[0][7].valid[2])
node _sector_hits_T_58 = or(_sector_hits_T_57, sectored_entries[0][7].valid[3])
node _sector_hits_T_59 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _sector_hits_T_60 = shr(_sector_hits_T_59, 2)
node _sector_hits_T_61 = eq(_sector_hits_T_60, UInt<1>(0h0))
node _sector_hits_T_62 = eq(sectored_entries[0][7].tag_v, priv_v)
node _sector_hits_T_63 = and(_sector_hits_T_61, _sector_hits_T_62)
node sector_hits_7 = and(_sector_hits_T_58, _sector_hits_T_63)
node _superpage_hits_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v)
node superpage_hits_tagMatch = and(superpage_entries[0].valid[0], _superpage_hits_tagMatch_T)
node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0))
node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0))
node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn)
node _superpage_hits_T_1 = bits(_superpage_hits_T, 26, 18)
node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0))
node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2)
node _superpage_hits_T_4 = and(superpage_hits_tagMatch, _superpage_hits_T_3)
node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1))
node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0))
node _superpage_hits_T_5 = xor(superpage_entries[0].tag_vpn, vpn)
node _superpage_hits_T_6 = bits(_superpage_hits_T_5, 17, 9)
node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0))
node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7)
node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8)
node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2))
node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1))
node _superpage_hits_T_10 = xor(superpage_entries[0].tag_vpn, vpn)
node _superpage_hits_T_11 = bits(_superpage_hits_T_10, 8, 0)
node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0))
node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12)
node superpage_hits_0 = and(_superpage_hits_T_9, _superpage_hits_T_13)
node _superpage_hits_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v)
node superpage_hits_tagMatch_1 = and(superpage_entries[1].valid[0], _superpage_hits_tagMatch_T_1)
node _superpage_hits_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0))
node superpage_hits_ignore_3 = or(_superpage_hits_ignore_T_3, UInt<1>(0h0))
node _superpage_hits_T_14 = xor(superpage_entries[1].tag_vpn, vpn)
node _superpage_hits_T_15 = bits(_superpage_hits_T_14, 26, 18)
node _superpage_hits_T_16 = eq(_superpage_hits_T_15, UInt<1>(0h0))
node _superpage_hits_T_17 = or(superpage_hits_ignore_3, _superpage_hits_T_16)
node _superpage_hits_T_18 = and(superpage_hits_tagMatch_1, _superpage_hits_T_17)
node _superpage_hits_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1))
node superpage_hits_ignore_4 = or(_superpage_hits_ignore_T_4, UInt<1>(0h0))
node _superpage_hits_T_19 = xor(superpage_entries[1].tag_vpn, vpn)
node _superpage_hits_T_20 = bits(_superpage_hits_T_19, 17, 9)
node _superpage_hits_T_21 = eq(_superpage_hits_T_20, UInt<1>(0h0))
node _superpage_hits_T_22 = or(superpage_hits_ignore_4, _superpage_hits_T_21)
node _superpage_hits_T_23 = and(_superpage_hits_T_18, _superpage_hits_T_22)
node _superpage_hits_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2))
node superpage_hits_ignore_5 = or(_superpage_hits_ignore_T_5, UInt<1>(0h1))
node _superpage_hits_T_24 = xor(superpage_entries[1].tag_vpn, vpn)
node _superpage_hits_T_25 = bits(_superpage_hits_T_24, 8, 0)
node _superpage_hits_T_26 = eq(_superpage_hits_T_25, UInt<1>(0h0))
node _superpage_hits_T_27 = or(superpage_hits_ignore_5, _superpage_hits_T_26)
node superpage_hits_1 = and(_superpage_hits_T_23, _superpage_hits_T_27)
node _superpage_hits_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v)
node superpage_hits_tagMatch_2 = and(superpage_entries[2].valid[0], _superpage_hits_tagMatch_T_2)
node _superpage_hits_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0))
node superpage_hits_ignore_6 = or(_superpage_hits_ignore_T_6, UInt<1>(0h0))
node _superpage_hits_T_28 = xor(superpage_entries[2].tag_vpn, vpn)
node _superpage_hits_T_29 = bits(_superpage_hits_T_28, 26, 18)
node _superpage_hits_T_30 = eq(_superpage_hits_T_29, UInt<1>(0h0))
node _superpage_hits_T_31 = or(superpage_hits_ignore_6, _superpage_hits_T_30)
node _superpage_hits_T_32 = and(superpage_hits_tagMatch_2, _superpage_hits_T_31)
node _superpage_hits_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1))
node superpage_hits_ignore_7 = or(_superpage_hits_ignore_T_7, UInt<1>(0h0))
node _superpage_hits_T_33 = xor(superpage_entries[2].tag_vpn, vpn)
node _superpage_hits_T_34 = bits(_superpage_hits_T_33, 17, 9)
node _superpage_hits_T_35 = eq(_superpage_hits_T_34, UInt<1>(0h0))
node _superpage_hits_T_36 = or(superpage_hits_ignore_7, _superpage_hits_T_35)
node _superpage_hits_T_37 = and(_superpage_hits_T_32, _superpage_hits_T_36)
node _superpage_hits_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2))
node superpage_hits_ignore_8 = or(_superpage_hits_ignore_T_8, UInt<1>(0h1))
node _superpage_hits_T_38 = xor(superpage_entries[2].tag_vpn, vpn)
node _superpage_hits_T_39 = bits(_superpage_hits_T_38, 8, 0)
node _superpage_hits_T_40 = eq(_superpage_hits_T_39, UInt<1>(0h0))
node _superpage_hits_T_41 = or(superpage_hits_ignore_8, _superpage_hits_T_40)
node superpage_hits_2 = and(_superpage_hits_T_37, _superpage_hits_T_41)
node _superpage_hits_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v)
node superpage_hits_tagMatch_3 = and(superpage_entries[3].valid[0], _superpage_hits_tagMatch_T_3)
node _superpage_hits_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0))
node superpage_hits_ignore_9 = or(_superpage_hits_ignore_T_9, UInt<1>(0h0))
node _superpage_hits_T_42 = xor(superpage_entries[3].tag_vpn, vpn)
node _superpage_hits_T_43 = bits(_superpage_hits_T_42, 26, 18)
node _superpage_hits_T_44 = eq(_superpage_hits_T_43, UInt<1>(0h0))
node _superpage_hits_T_45 = or(superpage_hits_ignore_9, _superpage_hits_T_44)
node _superpage_hits_T_46 = and(superpage_hits_tagMatch_3, _superpage_hits_T_45)
node _superpage_hits_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1))
node superpage_hits_ignore_10 = or(_superpage_hits_ignore_T_10, UInt<1>(0h0))
node _superpage_hits_T_47 = xor(superpage_entries[3].tag_vpn, vpn)
node _superpage_hits_T_48 = bits(_superpage_hits_T_47, 17, 9)
node _superpage_hits_T_49 = eq(_superpage_hits_T_48, UInt<1>(0h0))
node _superpage_hits_T_50 = or(superpage_hits_ignore_10, _superpage_hits_T_49)
node _superpage_hits_T_51 = and(_superpage_hits_T_46, _superpage_hits_T_50)
node _superpage_hits_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2))
node superpage_hits_ignore_11 = or(_superpage_hits_ignore_T_11, UInt<1>(0h1))
node _superpage_hits_T_52 = xor(superpage_entries[3].tag_vpn, vpn)
node _superpage_hits_T_53 = bits(_superpage_hits_T_52, 8, 0)
node _superpage_hits_T_54 = eq(_superpage_hits_T_53, UInt<1>(0h0))
node _superpage_hits_T_55 = or(superpage_hits_ignore_11, _superpage_hits_T_54)
node superpage_hits_3 = and(_superpage_hits_T_51, _superpage_hits_T_55)
node hitsVec_idx = bits(vpn, 1, 0)
node _hitsVec_T = xor(sectored_entries[0][0].tag_vpn, vpn)
node _hitsVec_T_1 = shr(_hitsVec_T, 2)
node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0))
node _hitsVec_T_3 = eq(sectored_entries[0][0].tag_v, priv_v)
node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3)
node _hitsVec_T_5 = and(sectored_entries[0][0].valid[hitsVec_idx], _hitsVec_T_4)
node hitsVec_0 = and(vm_enabled, _hitsVec_T_5)
node hitsVec_idx_1 = bits(vpn, 1, 0)
node _hitsVec_T_6 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _hitsVec_T_7 = shr(_hitsVec_T_6, 2)
node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0))
node _hitsVec_T_9 = eq(sectored_entries[0][1].tag_v, priv_v)
node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9)
node _hitsVec_T_11 = and(sectored_entries[0][1].valid[hitsVec_idx_1], _hitsVec_T_10)
node hitsVec_1 = and(vm_enabled, _hitsVec_T_11)
node hitsVec_idx_2 = bits(vpn, 1, 0)
node _hitsVec_T_12 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _hitsVec_T_13 = shr(_hitsVec_T_12, 2)
node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0))
node _hitsVec_T_15 = eq(sectored_entries[0][2].tag_v, priv_v)
node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15)
node _hitsVec_T_17 = and(sectored_entries[0][2].valid[hitsVec_idx_2], _hitsVec_T_16)
node hitsVec_2 = and(vm_enabled, _hitsVec_T_17)
node hitsVec_idx_3 = bits(vpn, 1, 0)
node _hitsVec_T_18 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _hitsVec_T_19 = shr(_hitsVec_T_18, 2)
node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0))
node _hitsVec_T_21 = eq(sectored_entries[0][3].tag_v, priv_v)
node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21)
node _hitsVec_T_23 = and(sectored_entries[0][3].valid[hitsVec_idx_3], _hitsVec_T_22)
node hitsVec_3 = and(vm_enabled, _hitsVec_T_23)
node hitsVec_idx_4 = bits(vpn, 1, 0)
node _hitsVec_T_24 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _hitsVec_T_25 = shr(_hitsVec_T_24, 2)
node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0))
node _hitsVec_T_27 = eq(sectored_entries[0][4].tag_v, priv_v)
node _hitsVec_T_28 = and(_hitsVec_T_26, _hitsVec_T_27)
node _hitsVec_T_29 = and(sectored_entries[0][4].valid[hitsVec_idx_4], _hitsVec_T_28)
node hitsVec_4 = and(vm_enabled, _hitsVec_T_29)
node hitsVec_idx_5 = bits(vpn, 1, 0)
node _hitsVec_T_30 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _hitsVec_T_31 = shr(_hitsVec_T_30, 2)
node _hitsVec_T_32 = eq(_hitsVec_T_31, UInt<1>(0h0))
node _hitsVec_T_33 = eq(sectored_entries[0][5].tag_v, priv_v)
node _hitsVec_T_34 = and(_hitsVec_T_32, _hitsVec_T_33)
node _hitsVec_T_35 = and(sectored_entries[0][5].valid[hitsVec_idx_5], _hitsVec_T_34)
node hitsVec_5 = and(vm_enabled, _hitsVec_T_35)
node hitsVec_idx_6 = bits(vpn, 1, 0)
node _hitsVec_T_36 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _hitsVec_T_37 = shr(_hitsVec_T_36, 2)
node _hitsVec_T_38 = eq(_hitsVec_T_37, UInt<1>(0h0))
node _hitsVec_T_39 = eq(sectored_entries[0][6].tag_v, priv_v)
node _hitsVec_T_40 = and(_hitsVec_T_38, _hitsVec_T_39)
node _hitsVec_T_41 = and(sectored_entries[0][6].valid[hitsVec_idx_6], _hitsVec_T_40)
node hitsVec_6 = and(vm_enabled, _hitsVec_T_41)
node hitsVec_idx_7 = bits(vpn, 1, 0)
node _hitsVec_T_42 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _hitsVec_T_43 = shr(_hitsVec_T_42, 2)
node _hitsVec_T_44 = eq(_hitsVec_T_43, UInt<1>(0h0))
node _hitsVec_T_45 = eq(sectored_entries[0][7].tag_v, priv_v)
node _hitsVec_T_46 = and(_hitsVec_T_44, _hitsVec_T_45)
node _hitsVec_T_47 = and(sectored_entries[0][7].valid[hitsVec_idx_7], _hitsVec_T_46)
node hitsVec_7 = and(vm_enabled, _hitsVec_T_47)
node _hitsVec_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v)
node hitsVec_tagMatch = and(superpage_entries[0].valid[0], _hitsVec_tagMatch_T)
node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0))
node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0))
node _hitsVec_T_48 = xor(superpage_entries[0].tag_vpn, vpn)
node _hitsVec_T_49 = bits(_hitsVec_T_48, 26, 18)
node _hitsVec_T_50 = eq(_hitsVec_T_49, UInt<1>(0h0))
node _hitsVec_T_51 = or(hitsVec_ignore, _hitsVec_T_50)
node _hitsVec_T_52 = and(hitsVec_tagMatch, _hitsVec_T_51)
node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1))
node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0))
node _hitsVec_T_53 = xor(superpage_entries[0].tag_vpn, vpn)
node _hitsVec_T_54 = bits(_hitsVec_T_53, 17, 9)
node _hitsVec_T_55 = eq(_hitsVec_T_54, UInt<1>(0h0))
node _hitsVec_T_56 = or(hitsVec_ignore_1, _hitsVec_T_55)
node _hitsVec_T_57 = and(_hitsVec_T_52, _hitsVec_T_56)
node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2))
node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1))
node _hitsVec_T_58 = xor(superpage_entries[0].tag_vpn, vpn)
node _hitsVec_T_59 = bits(_hitsVec_T_58, 8, 0)
node _hitsVec_T_60 = eq(_hitsVec_T_59, UInt<1>(0h0))
node _hitsVec_T_61 = or(hitsVec_ignore_2, _hitsVec_T_60)
node _hitsVec_T_62 = and(_hitsVec_T_57, _hitsVec_T_61)
node hitsVec_8 = and(vm_enabled, _hitsVec_T_62)
node _hitsVec_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v)
node hitsVec_tagMatch_1 = and(superpage_entries[1].valid[0], _hitsVec_tagMatch_T_1)
node _hitsVec_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0))
node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0))
node _hitsVec_T_63 = xor(superpage_entries[1].tag_vpn, vpn)
node _hitsVec_T_64 = bits(_hitsVec_T_63, 26, 18)
node _hitsVec_T_65 = eq(_hitsVec_T_64, UInt<1>(0h0))
node _hitsVec_T_66 = or(hitsVec_ignore_3, _hitsVec_T_65)
node _hitsVec_T_67 = and(hitsVec_tagMatch_1, _hitsVec_T_66)
node _hitsVec_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1))
node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0))
node _hitsVec_T_68 = xor(superpage_entries[1].tag_vpn, vpn)
node _hitsVec_T_69 = bits(_hitsVec_T_68, 17, 9)
node _hitsVec_T_70 = eq(_hitsVec_T_69, UInt<1>(0h0))
node _hitsVec_T_71 = or(hitsVec_ignore_4, _hitsVec_T_70)
node _hitsVec_T_72 = and(_hitsVec_T_67, _hitsVec_T_71)
node _hitsVec_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2))
node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h1))
node _hitsVec_T_73 = xor(superpage_entries[1].tag_vpn, vpn)
node _hitsVec_T_74 = bits(_hitsVec_T_73, 8, 0)
node _hitsVec_T_75 = eq(_hitsVec_T_74, UInt<1>(0h0))
node _hitsVec_T_76 = or(hitsVec_ignore_5, _hitsVec_T_75)
node _hitsVec_T_77 = and(_hitsVec_T_72, _hitsVec_T_76)
node hitsVec_9 = and(vm_enabled, _hitsVec_T_77)
node _hitsVec_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v)
node hitsVec_tagMatch_2 = and(superpage_entries[2].valid[0], _hitsVec_tagMatch_T_2)
node _hitsVec_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0))
node hitsVec_ignore_6 = or(_hitsVec_ignore_T_6, UInt<1>(0h0))
node _hitsVec_T_78 = xor(superpage_entries[2].tag_vpn, vpn)
node _hitsVec_T_79 = bits(_hitsVec_T_78, 26, 18)
node _hitsVec_T_80 = eq(_hitsVec_T_79, UInt<1>(0h0))
node _hitsVec_T_81 = or(hitsVec_ignore_6, _hitsVec_T_80)
node _hitsVec_T_82 = and(hitsVec_tagMatch_2, _hitsVec_T_81)
node _hitsVec_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1))
node hitsVec_ignore_7 = or(_hitsVec_ignore_T_7, UInt<1>(0h0))
node _hitsVec_T_83 = xor(superpage_entries[2].tag_vpn, vpn)
node _hitsVec_T_84 = bits(_hitsVec_T_83, 17, 9)
node _hitsVec_T_85 = eq(_hitsVec_T_84, UInt<1>(0h0))
node _hitsVec_T_86 = or(hitsVec_ignore_7, _hitsVec_T_85)
node _hitsVec_T_87 = and(_hitsVec_T_82, _hitsVec_T_86)
node _hitsVec_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2))
node hitsVec_ignore_8 = or(_hitsVec_ignore_T_8, UInt<1>(0h1))
node _hitsVec_T_88 = xor(superpage_entries[2].tag_vpn, vpn)
node _hitsVec_T_89 = bits(_hitsVec_T_88, 8, 0)
node _hitsVec_T_90 = eq(_hitsVec_T_89, UInt<1>(0h0))
node _hitsVec_T_91 = or(hitsVec_ignore_8, _hitsVec_T_90)
node _hitsVec_T_92 = and(_hitsVec_T_87, _hitsVec_T_91)
node hitsVec_10 = and(vm_enabled, _hitsVec_T_92)
node _hitsVec_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v)
node hitsVec_tagMatch_3 = and(superpage_entries[3].valid[0], _hitsVec_tagMatch_T_3)
node _hitsVec_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0))
node hitsVec_ignore_9 = or(_hitsVec_ignore_T_9, UInt<1>(0h0))
node _hitsVec_T_93 = xor(superpage_entries[3].tag_vpn, vpn)
node _hitsVec_T_94 = bits(_hitsVec_T_93, 26, 18)
node _hitsVec_T_95 = eq(_hitsVec_T_94, UInt<1>(0h0))
node _hitsVec_T_96 = or(hitsVec_ignore_9, _hitsVec_T_95)
node _hitsVec_T_97 = and(hitsVec_tagMatch_3, _hitsVec_T_96)
node _hitsVec_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1))
node hitsVec_ignore_10 = or(_hitsVec_ignore_T_10, UInt<1>(0h0))
node _hitsVec_T_98 = xor(superpage_entries[3].tag_vpn, vpn)
node _hitsVec_T_99 = bits(_hitsVec_T_98, 17, 9)
node _hitsVec_T_100 = eq(_hitsVec_T_99, UInt<1>(0h0))
node _hitsVec_T_101 = or(hitsVec_ignore_10, _hitsVec_T_100)
node _hitsVec_T_102 = and(_hitsVec_T_97, _hitsVec_T_101)
node _hitsVec_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2))
node hitsVec_ignore_11 = or(_hitsVec_ignore_T_11, UInt<1>(0h1))
node _hitsVec_T_103 = xor(superpage_entries[3].tag_vpn, vpn)
node _hitsVec_T_104 = bits(_hitsVec_T_103, 8, 0)
node _hitsVec_T_105 = eq(_hitsVec_T_104, UInt<1>(0h0))
node _hitsVec_T_106 = or(hitsVec_ignore_11, _hitsVec_T_105)
node _hitsVec_T_107 = and(_hitsVec_T_102, _hitsVec_T_106)
node hitsVec_11 = and(vm_enabled, _hitsVec_T_107)
node _hitsVec_tagMatch_T_4 = eq(special_entry.tag_v, priv_v)
node hitsVec_tagMatch_4 = and(special_entry.valid[0], _hitsVec_tagMatch_T_4)
node _hitsVec_ignore_T_12 = lt(special_entry.level, UInt<1>(0h0))
node hitsVec_ignore_12 = or(_hitsVec_ignore_T_12, UInt<1>(0h0))
node _hitsVec_T_108 = xor(special_entry.tag_vpn, vpn)
node _hitsVec_T_109 = bits(_hitsVec_T_108, 26, 18)
node _hitsVec_T_110 = eq(_hitsVec_T_109, UInt<1>(0h0))
node _hitsVec_T_111 = or(hitsVec_ignore_12, _hitsVec_T_110)
node _hitsVec_T_112 = and(hitsVec_tagMatch_4, _hitsVec_T_111)
node _hitsVec_ignore_T_13 = lt(special_entry.level, UInt<1>(0h1))
node hitsVec_ignore_13 = or(_hitsVec_ignore_T_13, UInt<1>(0h0))
node _hitsVec_T_113 = xor(special_entry.tag_vpn, vpn)
node _hitsVec_T_114 = bits(_hitsVec_T_113, 17, 9)
node _hitsVec_T_115 = eq(_hitsVec_T_114, UInt<1>(0h0))
node _hitsVec_T_116 = or(hitsVec_ignore_13, _hitsVec_T_115)
node _hitsVec_T_117 = and(_hitsVec_T_112, _hitsVec_T_116)
node _hitsVec_ignore_T_14 = lt(special_entry.level, UInt<2>(0h2))
node hitsVec_ignore_14 = or(_hitsVec_ignore_T_14, UInt<1>(0h0))
node _hitsVec_T_118 = xor(special_entry.tag_vpn, vpn)
node _hitsVec_T_119 = bits(_hitsVec_T_118, 8, 0)
node _hitsVec_T_120 = eq(_hitsVec_T_119, UInt<1>(0h0))
node _hitsVec_T_121 = or(hitsVec_ignore_14, _hitsVec_T_120)
node _hitsVec_T_122 = and(_hitsVec_T_117, _hitsVec_T_121)
node hitsVec_12 = and(vm_enabled, _hitsVec_T_122)
node real_hits_lo_lo_hi = cat(hitsVec_2, hitsVec_1)
node real_hits_lo_lo = cat(real_hits_lo_lo_hi, hitsVec_0)
node real_hits_lo_hi_hi = cat(hitsVec_5, hitsVec_4)
node real_hits_lo_hi = cat(real_hits_lo_hi_hi, hitsVec_3)
node real_hits_lo = cat(real_hits_lo_hi, real_hits_lo_lo)
node real_hits_hi_lo_hi = cat(hitsVec_8, hitsVec_7)
node real_hits_hi_lo = cat(real_hits_hi_lo_hi, hitsVec_6)
node real_hits_hi_hi_lo = cat(hitsVec_10, hitsVec_9)
node real_hits_hi_hi_hi = cat(hitsVec_12, hitsVec_11)
node real_hits_hi_hi = cat(real_hits_hi_hi_hi, real_hits_hi_hi_lo)
node real_hits_hi = cat(real_hits_hi_hi, real_hits_hi_lo)
node real_hits = cat(real_hits_hi, real_hits_lo)
node _hits_T = eq(vm_enabled, UInt<1>(0h0))
node hits = cat(_hits_T, real_hits)
when do_refill :
node refill_v = or(r_vstage1_en, r_stage2_en)
wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
connect newEntry.ppn, io.ptw.resp.bits.pte.ppn
connect newEntry.c, cacheable
connect newEntry.u, io.ptw.resp.bits.pte.u
node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v)
connect newEntry.g, _newEntry_g_T
connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw
connect newEntry.ae_final, io.ptw.resp.bits.ae_final
node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte)
node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en)
connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1
connect newEntry.pf, io.ptw.resp.bits.pf
connect newEntry.gf, io.ptw.resp.bits.gf
connect newEntry.hr, io.ptw.resp.bits.hr
connect newEntry.hw, io.ptw.resp.bits.hw
connect newEntry.hx, io.ptw.resp.bits.hx
node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0))
node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T)
node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1)
node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2)
node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a)
node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r)
connect newEntry.sr, _newEntry_sr_T_5
node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0))
node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T)
node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1)
node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2)
node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a)
node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w)
node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d)
connect newEntry.sw, _newEntry_sw_T_6
node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0))
node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T)
node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1)
node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2)
node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a)
node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x)
connect newEntry.sx, _newEntry_sx_T_5
connect newEntry.pr, prot_r
connect newEntry.pw, prot_w
connect newEntry.px, prot_x
connect newEntry.ppp, pma.io.resp.pp
connect newEntry.pal, pma.io.resp.al
connect newEntry.paa, pma.io.resp.aa
connect newEntry.eff, pma.io.resp.eff
connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage
node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
when _T_1 :
connect special_entry.tag_vpn, r_refill_tag
connect special_entry.tag_v, refill_v
node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0)
connect special_entry.level, _special_entry_level_T
connect special_entry.valid[0], UInt<1>(0h1)
node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff)
node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo)
node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp)
node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw)
node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo)
node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo)
node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw)
node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw)
node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo)
node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g)
node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo)
node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo)
node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo)
connect special_entry.data[0], _special_entry_data_0_T
else :
node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2))
when _T_2 :
node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0))
node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr)
node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0))
when _T_3 :
connect superpage_entries[0].tag_vpn, r_refill_tag
connect superpage_entries[0].tag_v, refill_v
node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[0].level, _superpage_entries_0_level_T
connect superpage_entries[0].valid[0], UInt<1>(0h1)
node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo)
node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo)
node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo)
node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo)
node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo)
node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo)
node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo)
connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T
when invalidate_refill :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1))
when _T_4 :
connect superpage_entries[1].tag_vpn, r_refill_tag
connect superpage_entries[1].tag_v, refill_v
node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[1].level, _superpage_entries_1_level_T
connect superpage_entries[1].valid[0], UInt<1>(0h1)
node superpage_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_1_data_0_lo_lo_hi = cat(superpage_entries_1_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo)
node superpage_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_1_data_0_lo_hi_lo = cat(superpage_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_1_data_0_lo_hi_hi = cat(superpage_entries_1_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo)
node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo)
node superpage_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_1_data_0_hi_lo_lo = cat(superpage_entries_1_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_1_data_0_hi_lo_hi = cat(superpage_entries_1_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo)
node superpage_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_1_data_0_hi_hi_lo = cat(superpage_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_1_data_0_hi_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo)
node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo)
node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo)
connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T
when invalidate_refill :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2))
when _T_5 :
connect superpage_entries[2].tag_vpn, r_refill_tag
connect superpage_entries[2].tag_v, refill_v
node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[2].level, _superpage_entries_2_level_T
connect superpage_entries[2].valid[0], UInt<1>(0h1)
node superpage_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_2_data_0_lo_lo_hi = cat(superpage_entries_2_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo)
node superpage_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_2_data_0_lo_hi_lo = cat(superpage_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_2_data_0_lo_hi_hi = cat(superpage_entries_2_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo)
node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo)
node superpage_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_2_data_0_hi_lo_lo = cat(superpage_entries_2_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_2_data_0_hi_lo_hi = cat(superpage_entries_2_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo)
node superpage_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_2_data_0_hi_hi_lo = cat(superpage_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_2_data_0_hi_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo)
node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo)
node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo)
connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T
when invalidate_refill :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3))
when _T_6 :
connect superpage_entries[3].tag_vpn, r_refill_tag
connect superpage_entries[3].tag_v, refill_v
node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[3].level, _superpage_entries_3_level_T
connect superpage_entries[3].valid[0], UInt<1>(0h1)
node superpage_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_3_data_0_lo_lo_hi = cat(superpage_entries_3_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo)
node superpage_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_3_data_0_lo_hi_lo = cat(superpage_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_3_data_0_lo_hi_hi = cat(superpage_entries_3_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo)
node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo)
node superpage_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_3_data_0_hi_lo_lo = cat(superpage_entries_3_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_3_data_0_hi_lo_hi = cat(superpage_entries_3_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo)
node superpage_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_3_data_0_hi_hi_lo = cat(superpage_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_3_data_0_hi_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo)
node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo)
node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo)
connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T
when invalidate_refill :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
else :
node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr)
node _T_7 = eq(waddr_1, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_8 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
connect sectored_entries[0][0].tag_vpn, r_refill_tag
connect sectored_entries[0][0].tag_v, refill_v
connect sectored_entries[0][0].level, UInt<2>(0h0)
node idx = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][0].valid[idx], UInt<1>(0h1)
node sectored_entries_0_0_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_0_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_0_data_lo_lo_hi = cat(sectored_entries_0_0_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_0_data_lo_lo = cat(sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo)
node sectored_entries_0_0_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_0_data_lo_hi_lo = cat(sectored_entries_0_0_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_0_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_0_data_lo_hi_hi = cat(sectored_entries_0_0_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_0_data_lo_hi = cat(sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo)
node sectored_entries_0_0_data_lo = cat(sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo)
node sectored_entries_0_0_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_0_data_hi_lo_lo = cat(sectored_entries_0_0_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_0_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_0_data_hi_lo_hi = cat(sectored_entries_0_0_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_0_data_hi_lo = cat(sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo)
node sectored_entries_0_0_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_0_data_hi_hi_lo = cat(sectored_entries_0_0_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_0_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_0_data_hi_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_0_data_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo)
node sectored_entries_0_0_data_hi = cat(sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo)
node _sectored_entries_0_0_data_T = cat(sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo)
connect sectored_entries[0][0].data[idx], _sectored_entries_0_0_data_T
when invalidate_refill :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
node _T_9 = eq(waddr_1, UInt<1>(0h1))
when _T_9 :
node _T_10 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_10 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
connect sectored_entries[0][1].tag_vpn, r_refill_tag
connect sectored_entries[0][1].tag_v, refill_v
connect sectored_entries[0][1].level, UInt<2>(0h0)
node idx_1 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][1].valid[idx_1], UInt<1>(0h1)
node sectored_entries_0_1_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_1_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_1_data_lo_lo_hi = cat(sectored_entries_0_1_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_1_data_lo_lo = cat(sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo)
node sectored_entries_0_1_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_1_data_lo_hi_lo = cat(sectored_entries_0_1_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_1_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_1_data_lo_hi_hi = cat(sectored_entries_0_1_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_1_data_lo_hi = cat(sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo)
node sectored_entries_0_1_data_lo = cat(sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo)
node sectored_entries_0_1_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_1_data_hi_lo_lo = cat(sectored_entries_0_1_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_1_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_1_data_hi_lo_hi = cat(sectored_entries_0_1_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_1_data_hi_lo = cat(sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo)
node sectored_entries_0_1_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_1_data_hi_hi_lo = cat(sectored_entries_0_1_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_1_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_1_data_hi_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_1_data_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo)
node sectored_entries_0_1_data_hi = cat(sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo)
node _sectored_entries_0_1_data_T = cat(sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo)
connect sectored_entries[0][1].data[idx_1], _sectored_entries_0_1_data_T
when invalidate_refill :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
node _T_11 = eq(waddr_1, UInt<2>(0h2))
when _T_11 :
node _T_12 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_12 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
connect sectored_entries[0][2].tag_vpn, r_refill_tag
connect sectored_entries[0][2].tag_v, refill_v
connect sectored_entries[0][2].level, UInt<2>(0h0)
node idx_2 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][2].valid[idx_2], UInt<1>(0h1)
node sectored_entries_0_2_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_2_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_2_data_lo_lo_hi = cat(sectored_entries_0_2_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_2_data_lo_lo = cat(sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo)
node sectored_entries_0_2_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_2_data_lo_hi_lo = cat(sectored_entries_0_2_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_2_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_2_data_lo_hi_hi = cat(sectored_entries_0_2_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_2_data_lo_hi = cat(sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo)
node sectored_entries_0_2_data_lo = cat(sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo)
node sectored_entries_0_2_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_2_data_hi_lo_lo = cat(sectored_entries_0_2_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_2_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_2_data_hi_lo_hi = cat(sectored_entries_0_2_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_2_data_hi_lo = cat(sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo)
node sectored_entries_0_2_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_2_data_hi_hi_lo = cat(sectored_entries_0_2_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_2_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_2_data_hi_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_2_data_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo)
node sectored_entries_0_2_data_hi = cat(sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo)
node _sectored_entries_0_2_data_T = cat(sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo)
connect sectored_entries[0][2].data[idx_2], _sectored_entries_0_2_data_T
when invalidate_refill :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
node _T_13 = eq(waddr_1, UInt<2>(0h3))
when _T_13 :
node _T_14 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_14 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
connect sectored_entries[0][3].tag_vpn, r_refill_tag
connect sectored_entries[0][3].tag_v, refill_v
connect sectored_entries[0][3].level, UInt<2>(0h0)
node idx_3 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][3].valid[idx_3], UInt<1>(0h1)
node sectored_entries_0_3_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_3_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_3_data_lo_lo_hi = cat(sectored_entries_0_3_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_3_data_lo_lo = cat(sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo)
node sectored_entries_0_3_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_3_data_lo_hi_lo = cat(sectored_entries_0_3_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_3_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_3_data_lo_hi_hi = cat(sectored_entries_0_3_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_3_data_lo_hi = cat(sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo)
node sectored_entries_0_3_data_lo = cat(sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo)
node sectored_entries_0_3_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_3_data_hi_lo_lo = cat(sectored_entries_0_3_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_3_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_3_data_hi_lo_hi = cat(sectored_entries_0_3_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_3_data_hi_lo = cat(sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo)
node sectored_entries_0_3_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_3_data_hi_hi_lo = cat(sectored_entries_0_3_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_3_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_3_data_hi_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_3_data_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo)
node sectored_entries_0_3_data_hi = cat(sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo)
node _sectored_entries_0_3_data_T = cat(sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo)
connect sectored_entries[0][3].data[idx_3], _sectored_entries_0_3_data_T
when invalidate_refill :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
node _T_15 = eq(waddr_1, UInt<3>(0h4))
when _T_15 :
node _T_16 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_16 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
connect sectored_entries[0][4].tag_vpn, r_refill_tag
connect sectored_entries[0][4].tag_v, refill_v
connect sectored_entries[0][4].level, UInt<2>(0h0)
node idx_4 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][4].valid[idx_4], UInt<1>(0h1)
node sectored_entries_0_4_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_4_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_4_data_lo_lo_hi = cat(sectored_entries_0_4_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_4_data_lo_lo = cat(sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo)
node sectored_entries_0_4_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_4_data_lo_hi_lo = cat(sectored_entries_0_4_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_4_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_4_data_lo_hi_hi = cat(sectored_entries_0_4_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_4_data_lo_hi = cat(sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo)
node sectored_entries_0_4_data_lo = cat(sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo)
node sectored_entries_0_4_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_4_data_hi_lo_lo = cat(sectored_entries_0_4_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_4_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_4_data_hi_lo_hi = cat(sectored_entries_0_4_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_4_data_hi_lo = cat(sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo)
node sectored_entries_0_4_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_4_data_hi_hi_lo = cat(sectored_entries_0_4_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_4_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_4_data_hi_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_4_data_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo)
node sectored_entries_0_4_data_hi = cat(sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo)
node _sectored_entries_0_4_data_T = cat(sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo)
connect sectored_entries[0][4].data[idx_4], _sectored_entries_0_4_data_T
when invalidate_refill :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
node _T_17 = eq(waddr_1, UInt<3>(0h5))
when _T_17 :
node _T_18 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_18 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
connect sectored_entries[0][5].tag_vpn, r_refill_tag
connect sectored_entries[0][5].tag_v, refill_v
connect sectored_entries[0][5].level, UInt<2>(0h0)
node idx_5 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][5].valid[idx_5], UInt<1>(0h1)
node sectored_entries_0_5_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_5_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_5_data_lo_lo_hi = cat(sectored_entries_0_5_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_5_data_lo_lo = cat(sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo)
node sectored_entries_0_5_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_5_data_lo_hi_lo = cat(sectored_entries_0_5_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_5_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_5_data_lo_hi_hi = cat(sectored_entries_0_5_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_5_data_lo_hi = cat(sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo)
node sectored_entries_0_5_data_lo = cat(sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo)
node sectored_entries_0_5_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_5_data_hi_lo_lo = cat(sectored_entries_0_5_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_5_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_5_data_hi_lo_hi = cat(sectored_entries_0_5_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_5_data_hi_lo = cat(sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo)
node sectored_entries_0_5_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_5_data_hi_hi_lo = cat(sectored_entries_0_5_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_5_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_5_data_hi_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_5_data_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo)
node sectored_entries_0_5_data_hi = cat(sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo)
node _sectored_entries_0_5_data_T = cat(sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo)
connect sectored_entries[0][5].data[idx_5], _sectored_entries_0_5_data_T
when invalidate_refill :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
node _T_19 = eq(waddr_1, UInt<3>(0h6))
when _T_19 :
node _T_20 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_20 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
connect sectored_entries[0][6].tag_vpn, r_refill_tag
connect sectored_entries[0][6].tag_v, refill_v
connect sectored_entries[0][6].level, UInt<2>(0h0)
node idx_6 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][6].valid[idx_6], UInt<1>(0h1)
node sectored_entries_0_6_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_6_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_6_data_lo_lo_hi = cat(sectored_entries_0_6_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_6_data_lo_lo = cat(sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo)
node sectored_entries_0_6_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_6_data_lo_hi_lo = cat(sectored_entries_0_6_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_6_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_6_data_lo_hi_hi = cat(sectored_entries_0_6_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_6_data_lo_hi = cat(sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo)
node sectored_entries_0_6_data_lo = cat(sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo)
node sectored_entries_0_6_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_6_data_hi_lo_lo = cat(sectored_entries_0_6_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_6_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_6_data_hi_lo_hi = cat(sectored_entries_0_6_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_6_data_hi_lo = cat(sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo)
node sectored_entries_0_6_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_6_data_hi_hi_lo = cat(sectored_entries_0_6_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_6_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_6_data_hi_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_6_data_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo)
node sectored_entries_0_6_data_hi = cat(sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo)
node _sectored_entries_0_6_data_T = cat(sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo)
connect sectored_entries[0][6].data[idx_6], _sectored_entries_0_6_data_T
when invalidate_refill :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
node _T_21 = eq(waddr_1, UInt<3>(0h7))
when _T_21 :
node _T_22 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_22 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
connect sectored_entries[0][7].tag_vpn, r_refill_tag
connect sectored_entries[0][7].tag_v, refill_v
connect sectored_entries[0][7].level, UInt<2>(0h0)
node idx_7 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][7].valid[idx_7], UInt<1>(0h1)
node sectored_entries_0_7_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_7_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_7_data_lo_lo_hi = cat(sectored_entries_0_7_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_7_data_lo_lo = cat(sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo)
node sectored_entries_0_7_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_7_data_lo_hi_lo = cat(sectored_entries_0_7_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_7_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_7_data_lo_hi_hi = cat(sectored_entries_0_7_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_7_data_lo_hi = cat(sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo)
node sectored_entries_0_7_data_lo = cat(sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo)
node sectored_entries_0_7_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_7_data_hi_lo_lo = cat(sectored_entries_0_7_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_7_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_7_data_hi_lo_hi = cat(sectored_entries_0_7_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_7_data_hi_lo = cat(sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo)
node sectored_entries_0_7_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_7_data_hi_hi_lo = cat(sectored_entries_0_7_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_7_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_7_data_hi_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_7_data_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo)
node sectored_entries_0_7_data_hi = cat(sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo)
node _sectored_entries_0_7_data_T = cat(sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo)
connect sectored_entries[0][7].data[idx_7], _sectored_entries_0_7_data_T
when invalidate_refill :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
connect r_gpa_valid, io.ptw.resp.bits.gpa.valid
connect r_gpa, io.ptw.resp.bits.gpa.bits
connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte
node _entries_T = bits(vpn, 1, 0)
wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_1 : UInt<42>
connect _entries_WIRE_1, sectored_entries[0][0].data[_entries_T]
node _entries_T_1 = bits(_entries_WIRE_1, 0, 0)
connect _entries_WIRE.fragmented_superpage, _entries_T_1
node _entries_T_2 = bits(_entries_WIRE_1, 1, 1)
connect _entries_WIRE.c, _entries_T_2
node _entries_T_3 = bits(_entries_WIRE_1, 2, 2)
connect _entries_WIRE.eff, _entries_T_3
node _entries_T_4 = bits(_entries_WIRE_1, 3, 3)
connect _entries_WIRE.paa, _entries_T_4
node _entries_T_5 = bits(_entries_WIRE_1, 4, 4)
connect _entries_WIRE.pal, _entries_T_5
node _entries_T_6 = bits(_entries_WIRE_1, 5, 5)
connect _entries_WIRE.ppp, _entries_T_6
node _entries_T_7 = bits(_entries_WIRE_1, 6, 6)
connect _entries_WIRE.pr, _entries_T_7
node _entries_T_8 = bits(_entries_WIRE_1, 7, 7)
connect _entries_WIRE.px, _entries_T_8
node _entries_T_9 = bits(_entries_WIRE_1, 8, 8)
connect _entries_WIRE.pw, _entries_T_9
node _entries_T_10 = bits(_entries_WIRE_1, 9, 9)
connect _entries_WIRE.hr, _entries_T_10
node _entries_T_11 = bits(_entries_WIRE_1, 10, 10)
connect _entries_WIRE.hx, _entries_T_11
node _entries_T_12 = bits(_entries_WIRE_1, 11, 11)
connect _entries_WIRE.hw, _entries_T_12
node _entries_T_13 = bits(_entries_WIRE_1, 12, 12)
connect _entries_WIRE.sr, _entries_T_13
node _entries_T_14 = bits(_entries_WIRE_1, 13, 13)
connect _entries_WIRE.sx, _entries_T_14
node _entries_T_15 = bits(_entries_WIRE_1, 14, 14)
connect _entries_WIRE.sw, _entries_T_15
node _entries_T_16 = bits(_entries_WIRE_1, 15, 15)
connect _entries_WIRE.gf, _entries_T_16
node _entries_T_17 = bits(_entries_WIRE_1, 16, 16)
connect _entries_WIRE.pf, _entries_T_17
node _entries_T_18 = bits(_entries_WIRE_1, 17, 17)
connect _entries_WIRE.ae_stage2, _entries_T_18
node _entries_T_19 = bits(_entries_WIRE_1, 18, 18)
connect _entries_WIRE.ae_final, _entries_T_19
node _entries_T_20 = bits(_entries_WIRE_1, 19, 19)
connect _entries_WIRE.ae_ptw, _entries_T_20
node _entries_T_21 = bits(_entries_WIRE_1, 20, 20)
connect _entries_WIRE.g, _entries_T_21
node _entries_T_22 = bits(_entries_WIRE_1, 21, 21)
connect _entries_WIRE.u, _entries_T_22
node _entries_T_23 = bits(_entries_WIRE_1, 41, 22)
connect _entries_WIRE.ppn, _entries_T_23
inst entries_barrier of OptimizationBarrier_TLBEntryData_113
connect entries_barrier.clock, clock
connect entries_barrier.reset, reset
connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage
connect entries_barrier.io.x.c, _entries_WIRE.c
connect entries_barrier.io.x.eff, _entries_WIRE.eff
connect entries_barrier.io.x.paa, _entries_WIRE.paa
connect entries_barrier.io.x.pal, _entries_WIRE.pal
connect entries_barrier.io.x.ppp, _entries_WIRE.ppp
connect entries_barrier.io.x.pr, _entries_WIRE.pr
connect entries_barrier.io.x.px, _entries_WIRE.px
connect entries_barrier.io.x.pw, _entries_WIRE.pw
connect entries_barrier.io.x.hr, _entries_WIRE.hr
connect entries_barrier.io.x.hx, _entries_WIRE.hx
connect entries_barrier.io.x.hw, _entries_WIRE.hw
connect entries_barrier.io.x.sr, _entries_WIRE.sr
connect entries_barrier.io.x.sx, _entries_WIRE.sx
connect entries_barrier.io.x.sw, _entries_WIRE.sw
connect entries_barrier.io.x.gf, _entries_WIRE.gf
connect entries_barrier.io.x.pf, _entries_WIRE.pf
connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2
connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final
connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw
connect entries_barrier.io.x.g, _entries_WIRE.g
connect entries_barrier.io.x.u, _entries_WIRE.u
connect entries_barrier.io.x.ppn, _entries_WIRE.ppn
node _entries_T_24 = bits(vpn, 1, 0)
wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_3 : UInt<42>
connect _entries_WIRE_3, sectored_entries[0][1].data[_entries_T_24]
node _entries_T_25 = bits(_entries_WIRE_3, 0, 0)
connect _entries_WIRE_2.fragmented_superpage, _entries_T_25
node _entries_T_26 = bits(_entries_WIRE_3, 1, 1)
connect _entries_WIRE_2.c, _entries_T_26
node _entries_T_27 = bits(_entries_WIRE_3, 2, 2)
connect _entries_WIRE_2.eff, _entries_T_27
node _entries_T_28 = bits(_entries_WIRE_3, 3, 3)
connect _entries_WIRE_2.paa, _entries_T_28
node _entries_T_29 = bits(_entries_WIRE_3, 4, 4)
connect _entries_WIRE_2.pal, _entries_T_29
node _entries_T_30 = bits(_entries_WIRE_3, 5, 5)
connect _entries_WIRE_2.ppp, _entries_T_30
node _entries_T_31 = bits(_entries_WIRE_3, 6, 6)
connect _entries_WIRE_2.pr, _entries_T_31
node _entries_T_32 = bits(_entries_WIRE_3, 7, 7)
connect _entries_WIRE_2.px, _entries_T_32
node _entries_T_33 = bits(_entries_WIRE_3, 8, 8)
connect _entries_WIRE_2.pw, _entries_T_33
node _entries_T_34 = bits(_entries_WIRE_3, 9, 9)
connect _entries_WIRE_2.hr, _entries_T_34
node _entries_T_35 = bits(_entries_WIRE_3, 10, 10)
connect _entries_WIRE_2.hx, _entries_T_35
node _entries_T_36 = bits(_entries_WIRE_3, 11, 11)
connect _entries_WIRE_2.hw, _entries_T_36
node _entries_T_37 = bits(_entries_WIRE_3, 12, 12)
connect _entries_WIRE_2.sr, _entries_T_37
node _entries_T_38 = bits(_entries_WIRE_3, 13, 13)
connect _entries_WIRE_2.sx, _entries_T_38
node _entries_T_39 = bits(_entries_WIRE_3, 14, 14)
connect _entries_WIRE_2.sw, _entries_T_39
node _entries_T_40 = bits(_entries_WIRE_3, 15, 15)
connect _entries_WIRE_2.gf, _entries_T_40
node _entries_T_41 = bits(_entries_WIRE_3, 16, 16)
connect _entries_WIRE_2.pf, _entries_T_41
node _entries_T_42 = bits(_entries_WIRE_3, 17, 17)
connect _entries_WIRE_2.ae_stage2, _entries_T_42
node _entries_T_43 = bits(_entries_WIRE_3, 18, 18)
connect _entries_WIRE_2.ae_final, _entries_T_43
node _entries_T_44 = bits(_entries_WIRE_3, 19, 19)
connect _entries_WIRE_2.ae_ptw, _entries_T_44
node _entries_T_45 = bits(_entries_WIRE_3, 20, 20)
connect _entries_WIRE_2.g, _entries_T_45
node _entries_T_46 = bits(_entries_WIRE_3, 21, 21)
connect _entries_WIRE_2.u, _entries_T_46
node _entries_T_47 = bits(_entries_WIRE_3, 41, 22)
connect _entries_WIRE_2.ppn, _entries_T_47
inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_114
connect entries_barrier_1.clock, clock
connect entries_barrier_1.reset, reset
connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage
connect entries_barrier_1.io.x.c, _entries_WIRE_2.c
connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff
connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa
connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal
connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp
connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr
connect entries_barrier_1.io.x.px, _entries_WIRE_2.px
connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw
connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr
connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx
connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw
connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr
connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx
connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw
connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf
connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf
connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2
connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final
connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw
connect entries_barrier_1.io.x.g, _entries_WIRE_2.g
connect entries_barrier_1.io.x.u, _entries_WIRE_2.u
connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn
node _entries_T_48 = bits(vpn, 1, 0)
wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_5 : UInt<42>
connect _entries_WIRE_5, sectored_entries[0][2].data[_entries_T_48]
node _entries_T_49 = bits(_entries_WIRE_5, 0, 0)
connect _entries_WIRE_4.fragmented_superpage, _entries_T_49
node _entries_T_50 = bits(_entries_WIRE_5, 1, 1)
connect _entries_WIRE_4.c, _entries_T_50
node _entries_T_51 = bits(_entries_WIRE_5, 2, 2)
connect _entries_WIRE_4.eff, _entries_T_51
node _entries_T_52 = bits(_entries_WIRE_5, 3, 3)
connect _entries_WIRE_4.paa, _entries_T_52
node _entries_T_53 = bits(_entries_WIRE_5, 4, 4)
connect _entries_WIRE_4.pal, _entries_T_53
node _entries_T_54 = bits(_entries_WIRE_5, 5, 5)
connect _entries_WIRE_4.ppp, _entries_T_54
node _entries_T_55 = bits(_entries_WIRE_5, 6, 6)
connect _entries_WIRE_4.pr, _entries_T_55
node _entries_T_56 = bits(_entries_WIRE_5, 7, 7)
connect _entries_WIRE_4.px, _entries_T_56
node _entries_T_57 = bits(_entries_WIRE_5, 8, 8)
connect _entries_WIRE_4.pw, _entries_T_57
node _entries_T_58 = bits(_entries_WIRE_5, 9, 9)
connect _entries_WIRE_4.hr, _entries_T_58
node _entries_T_59 = bits(_entries_WIRE_5, 10, 10)
connect _entries_WIRE_4.hx, _entries_T_59
node _entries_T_60 = bits(_entries_WIRE_5, 11, 11)
connect _entries_WIRE_4.hw, _entries_T_60
node _entries_T_61 = bits(_entries_WIRE_5, 12, 12)
connect _entries_WIRE_4.sr, _entries_T_61
node _entries_T_62 = bits(_entries_WIRE_5, 13, 13)
connect _entries_WIRE_4.sx, _entries_T_62
node _entries_T_63 = bits(_entries_WIRE_5, 14, 14)
connect _entries_WIRE_4.sw, _entries_T_63
node _entries_T_64 = bits(_entries_WIRE_5, 15, 15)
connect _entries_WIRE_4.gf, _entries_T_64
node _entries_T_65 = bits(_entries_WIRE_5, 16, 16)
connect _entries_WIRE_4.pf, _entries_T_65
node _entries_T_66 = bits(_entries_WIRE_5, 17, 17)
connect _entries_WIRE_4.ae_stage2, _entries_T_66
node _entries_T_67 = bits(_entries_WIRE_5, 18, 18)
connect _entries_WIRE_4.ae_final, _entries_T_67
node _entries_T_68 = bits(_entries_WIRE_5, 19, 19)
connect _entries_WIRE_4.ae_ptw, _entries_T_68
node _entries_T_69 = bits(_entries_WIRE_5, 20, 20)
connect _entries_WIRE_4.g, _entries_T_69
node _entries_T_70 = bits(_entries_WIRE_5, 21, 21)
connect _entries_WIRE_4.u, _entries_T_70
node _entries_T_71 = bits(_entries_WIRE_5, 41, 22)
connect _entries_WIRE_4.ppn, _entries_T_71
inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_115
connect entries_barrier_2.clock, clock
connect entries_barrier_2.reset, reset
connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage
connect entries_barrier_2.io.x.c, _entries_WIRE_4.c
connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff
connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa
connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal
connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp
connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr
connect entries_barrier_2.io.x.px, _entries_WIRE_4.px
connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw
connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr
connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx
connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw
connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr
connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx
connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw
connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf
connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf
connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2
connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final
connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw
connect entries_barrier_2.io.x.g, _entries_WIRE_4.g
connect entries_barrier_2.io.x.u, _entries_WIRE_4.u
connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn
node _entries_T_72 = bits(vpn, 1, 0)
wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_7 : UInt<42>
connect _entries_WIRE_7, sectored_entries[0][3].data[_entries_T_72]
node _entries_T_73 = bits(_entries_WIRE_7, 0, 0)
connect _entries_WIRE_6.fragmented_superpage, _entries_T_73
node _entries_T_74 = bits(_entries_WIRE_7, 1, 1)
connect _entries_WIRE_6.c, _entries_T_74
node _entries_T_75 = bits(_entries_WIRE_7, 2, 2)
connect _entries_WIRE_6.eff, _entries_T_75
node _entries_T_76 = bits(_entries_WIRE_7, 3, 3)
connect _entries_WIRE_6.paa, _entries_T_76
node _entries_T_77 = bits(_entries_WIRE_7, 4, 4)
connect _entries_WIRE_6.pal, _entries_T_77
node _entries_T_78 = bits(_entries_WIRE_7, 5, 5)
connect _entries_WIRE_6.ppp, _entries_T_78
node _entries_T_79 = bits(_entries_WIRE_7, 6, 6)
connect _entries_WIRE_6.pr, _entries_T_79
node _entries_T_80 = bits(_entries_WIRE_7, 7, 7)
connect _entries_WIRE_6.px, _entries_T_80
node _entries_T_81 = bits(_entries_WIRE_7, 8, 8)
connect _entries_WIRE_6.pw, _entries_T_81
node _entries_T_82 = bits(_entries_WIRE_7, 9, 9)
connect _entries_WIRE_6.hr, _entries_T_82
node _entries_T_83 = bits(_entries_WIRE_7, 10, 10)
connect _entries_WIRE_6.hx, _entries_T_83
node _entries_T_84 = bits(_entries_WIRE_7, 11, 11)
connect _entries_WIRE_6.hw, _entries_T_84
node _entries_T_85 = bits(_entries_WIRE_7, 12, 12)
connect _entries_WIRE_6.sr, _entries_T_85
node _entries_T_86 = bits(_entries_WIRE_7, 13, 13)
connect _entries_WIRE_6.sx, _entries_T_86
node _entries_T_87 = bits(_entries_WIRE_7, 14, 14)
connect _entries_WIRE_6.sw, _entries_T_87
node _entries_T_88 = bits(_entries_WIRE_7, 15, 15)
connect _entries_WIRE_6.gf, _entries_T_88
node _entries_T_89 = bits(_entries_WIRE_7, 16, 16)
connect _entries_WIRE_6.pf, _entries_T_89
node _entries_T_90 = bits(_entries_WIRE_7, 17, 17)
connect _entries_WIRE_6.ae_stage2, _entries_T_90
node _entries_T_91 = bits(_entries_WIRE_7, 18, 18)
connect _entries_WIRE_6.ae_final, _entries_T_91
node _entries_T_92 = bits(_entries_WIRE_7, 19, 19)
connect _entries_WIRE_6.ae_ptw, _entries_T_92
node _entries_T_93 = bits(_entries_WIRE_7, 20, 20)
connect _entries_WIRE_6.g, _entries_T_93
node _entries_T_94 = bits(_entries_WIRE_7, 21, 21)
connect _entries_WIRE_6.u, _entries_T_94
node _entries_T_95 = bits(_entries_WIRE_7, 41, 22)
connect _entries_WIRE_6.ppn, _entries_T_95
inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_116
connect entries_barrier_3.clock, clock
connect entries_barrier_3.reset, reset
connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage
connect entries_barrier_3.io.x.c, _entries_WIRE_6.c
connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff
connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa
connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal
connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp
connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr
connect entries_barrier_3.io.x.px, _entries_WIRE_6.px
connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw
connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr
connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx
connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw
connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr
connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx
connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw
connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf
connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf
connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2
connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final
connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw
connect entries_barrier_3.io.x.g, _entries_WIRE_6.g
connect entries_barrier_3.io.x.u, _entries_WIRE_6.u
connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn
node _entries_T_96 = bits(vpn, 1, 0)
wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_9 : UInt<42>
connect _entries_WIRE_9, sectored_entries[0][4].data[_entries_T_96]
node _entries_T_97 = bits(_entries_WIRE_9, 0, 0)
connect _entries_WIRE_8.fragmented_superpage, _entries_T_97
node _entries_T_98 = bits(_entries_WIRE_9, 1, 1)
connect _entries_WIRE_8.c, _entries_T_98
node _entries_T_99 = bits(_entries_WIRE_9, 2, 2)
connect _entries_WIRE_8.eff, _entries_T_99
node _entries_T_100 = bits(_entries_WIRE_9, 3, 3)
connect _entries_WIRE_8.paa, _entries_T_100
node _entries_T_101 = bits(_entries_WIRE_9, 4, 4)
connect _entries_WIRE_8.pal, _entries_T_101
node _entries_T_102 = bits(_entries_WIRE_9, 5, 5)
connect _entries_WIRE_8.ppp, _entries_T_102
node _entries_T_103 = bits(_entries_WIRE_9, 6, 6)
connect _entries_WIRE_8.pr, _entries_T_103
node _entries_T_104 = bits(_entries_WIRE_9, 7, 7)
connect _entries_WIRE_8.px, _entries_T_104
node _entries_T_105 = bits(_entries_WIRE_9, 8, 8)
connect _entries_WIRE_8.pw, _entries_T_105
node _entries_T_106 = bits(_entries_WIRE_9, 9, 9)
connect _entries_WIRE_8.hr, _entries_T_106
node _entries_T_107 = bits(_entries_WIRE_9, 10, 10)
connect _entries_WIRE_8.hx, _entries_T_107
node _entries_T_108 = bits(_entries_WIRE_9, 11, 11)
connect _entries_WIRE_8.hw, _entries_T_108
node _entries_T_109 = bits(_entries_WIRE_9, 12, 12)
connect _entries_WIRE_8.sr, _entries_T_109
node _entries_T_110 = bits(_entries_WIRE_9, 13, 13)
connect _entries_WIRE_8.sx, _entries_T_110
node _entries_T_111 = bits(_entries_WIRE_9, 14, 14)
connect _entries_WIRE_8.sw, _entries_T_111
node _entries_T_112 = bits(_entries_WIRE_9, 15, 15)
connect _entries_WIRE_8.gf, _entries_T_112
node _entries_T_113 = bits(_entries_WIRE_9, 16, 16)
connect _entries_WIRE_8.pf, _entries_T_113
node _entries_T_114 = bits(_entries_WIRE_9, 17, 17)
connect _entries_WIRE_8.ae_stage2, _entries_T_114
node _entries_T_115 = bits(_entries_WIRE_9, 18, 18)
connect _entries_WIRE_8.ae_final, _entries_T_115
node _entries_T_116 = bits(_entries_WIRE_9, 19, 19)
connect _entries_WIRE_8.ae_ptw, _entries_T_116
node _entries_T_117 = bits(_entries_WIRE_9, 20, 20)
connect _entries_WIRE_8.g, _entries_T_117
node _entries_T_118 = bits(_entries_WIRE_9, 21, 21)
connect _entries_WIRE_8.u, _entries_T_118
node _entries_T_119 = bits(_entries_WIRE_9, 41, 22)
connect _entries_WIRE_8.ppn, _entries_T_119
inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_117
connect entries_barrier_4.clock, clock
connect entries_barrier_4.reset, reset
connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage
connect entries_barrier_4.io.x.c, _entries_WIRE_8.c
connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff
connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa
connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal
connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp
connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr
connect entries_barrier_4.io.x.px, _entries_WIRE_8.px
connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw
connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr
connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx
connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw
connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr
connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx
connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw
connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf
connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf
connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2
connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final
connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw
connect entries_barrier_4.io.x.g, _entries_WIRE_8.g
connect entries_barrier_4.io.x.u, _entries_WIRE_8.u
connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn
node _entries_T_120 = bits(vpn, 1, 0)
wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_11 : UInt<42>
connect _entries_WIRE_11, sectored_entries[0][5].data[_entries_T_120]
node _entries_T_121 = bits(_entries_WIRE_11, 0, 0)
connect _entries_WIRE_10.fragmented_superpage, _entries_T_121
node _entries_T_122 = bits(_entries_WIRE_11, 1, 1)
connect _entries_WIRE_10.c, _entries_T_122
node _entries_T_123 = bits(_entries_WIRE_11, 2, 2)
connect _entries_WIRE_10.eff, _entries_T_123
node _entries_T_124 = bits(_entries_WIRE_11, 3, 3)
connect _entries_WIRE_10.paa, _entries_T_124
node _entries_T_125 = bits(_entries_WIRE_11, 4, 4)
connect _entries_WIRE_10.pal, _entries_T_125
node _entries_T_126 = bits(_entries_WIRE_11, 5, 5)
connect _entries_WIRE_10.ppp, _entries_T_126
node _entries_T_127 = bits(_entries_WIRE_11, 6, 6)
connect _entries_WIRE_10.pr, _entries_T_127
node _entries_T_128 = bits(_entries_WIRE_11, 7, 7)
connect _entries_WIRE_10.px, _entries_T_128
node _entries_T_129 = bits(_entries_WIRE_11, 8, 8)
connect _entries_WIRE_10.pw, _entries_T_129
node _entries_T_130 = bits(_entries_WIRE_11, 9, 9)
connect _entries_WIRE_10.hr, _entries_T_130
node _entries_T_131 = bits(_entries_WIRE_11, 10, 10)
connect _entries_WIRE_10.hx, _entries_T_131
node _entries_T_132 = bits(_entries_WIRE_11, 11, 11)
connect _entries_WIRE_10.hw, _entries_T_132
node _entries_T_133 = bits(_entries_WIRE_11, 12, 12)
connect _entries_WIRE_10.sr, _entries_T_133
node _entries_T_134 = bits(_entries_WIRE_11, 13, 13)
connect _entries_WIRE_10.sx, _entries_T_134
node _entries_T_135 = bits(_entries_WIRE_11, 14, 14)
connect _entries_WIRE_10.sw, _entries_T_135
node _entries_T_136 = bits(_entries_WIRE_11, 15, 15)
connect _entries_WIRE_10.gf, _entries_T_136
node _entries_T_137 = bits(_entries_WIRE_11, 16, 16)
connect _entries_WIRE_10.pf, _entries_T_137
node _entries_T_138 = bits(_entries_WIRE_11, 17, 17)
connect _entries_WIRE_10.ae_stage2, _entries_T_138
node _entries_T_139 = bits(_entries_WIRE_11, 18, 18)
connect _entries_WIRE_10.ae_final, _entries_T_139
node _entries_T_140 = bits(_entries_WIRE_11, 19, 19)
connect _entries_WIRE_10.ae_ptw, _entries_T_140
node _entries_T_141 = bits(_entries_WIRE_11, 20, 20)
connect _entries_WIRE_10.g, _entries_T_141
node _entries_T_142 = bits(_entries_WIRE_11, 21, 21)
connect _entries_WIRE_10.u, _entries_T_142
node _entries_T_143 = bits(_entries_WIRE_11, 41, 22)
connect _entries_WIRE_10.ppn, _entries_T_143
inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_118
connect entries_barrier_5.clock, clock
connect entries_barrier_5.reset, reset
connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage
connect entries_barrier_5.io.x.c, _entries_WIRE_10.c
connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff
connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa
connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal
connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp
connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr
connect entries_barrier_5.io.x.px, _entries_WIRE_10.px
connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw
connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr
connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx
connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw
connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr
connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx
connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw
connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf
connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf
connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2
connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final
connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw
connect entries_barrier_5.io.x.g, _entries_WIRE_10.g
connect entries_barrier_5.io.x.u, _entries_WIRE_10.u
connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn
node _entries_T_144 = bits(vpn, 1, 0)
wire _entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_13 : UInt<42>
connect _entries_WIRE_13, sectored_entries[0][6].data[_entries_T_144]
node _entries_T_145 = bits(_entries_WIRE_13, 0, 0)
connect _entries_WIRE_12.fragmented_superpage, _entries_T_145
node _entries_T_146 = bits(_entries_WIRE_13, 1, 1)
connect _entries_WIRE_12.c, _entries_T_146
node _entries_T_147 = bits(_entries_WIRE_13, 2, 2)
connect _entries_WIRE_12.eff, _entries_T_147
node _entries_T_148 = bits(_entries_WIRE_13, 3, 3)
connect _entries_WIRE_12.paa, _entries_T_148
node _entries_T_149 = bits(_entries_WIRE_13, 4, 4)
connect _entries_WIRE_12.pal, _entries_T_149
node _entries_T_150 = bits(_entries_WIRE_13, 5, 5)
connect _entries_WIRE_12.ppp, _entries_T_150
node _entries_T_151 = bits(_entries_WIRE_13, 6, 6)
connect _entries_WIRE_12.pr, _entries_T_151
node _entries_T_152 = bits(_entries_WIRE_13, 7, 7)
connect _entries_WIRE_12.px, _entries_T_152
node _entries_T_153 = bits(_entries_WIRE_13, 8, 8)
connect _entries_WIRE_12.pw, _entries_T_153
node _entries_T_154 = bits(_entries_WIRE_13, 9, 9)
connect _entries_WIRE_12.hr, _entries_T_154
node _entries_T_155 = bits(_entries_WIRE_13, 10, 10)
connect _entries_WIRE_12.hx, _entries_T_155
node _entries_T_156 = bits(_entries_WIRE_13, 11, 11)
connect _entries_WIRE_12.hw, _entries_T_156
node _entries_T_157 = bits(_entries_WIRE_13, 12, 12)
connect _entries_WIRE_12.sr, _entries_T_157
node _entries_T_158 = bits(_entries_WIRE_13, 13, 13)
connect _entries_WIRE_12.sx, _entries_T_158
node _entries_T_159 = bits(_entries_WIRE_13, 14, 14)
connect _entries_WIRE_12.sw, _entries_T_159
node _entries_T_160 = bits(_entries_WIRE_13, 15, 15)
connect _entries_WIRE_12.gf, _entries_T_160
node _entries_T_161 = bits(_entries_WIRE_13, 16, 16)
connect _entries_WIRE_12.pf, _entries_T_161
node _entries_T_162 = bits(_entries_WIRE_13, 17, 17)
connect _entries_WIRE_12.ae_stage2, _entries_T_162
node _entries_T_163 = bits(_entries_WIRE_13, 18, 18)
connect _entries_WIRE_12.ae_final, _entries_T_163
node _entries_T_164 = bits(_entries_WIRE_13, 19, 19)
connect _entries_WIRE_12.ae_ptw, _entries_T_164
node _entries_T_165 = bits(_entries_WIRE_13, 20, 20)
connect _entries_WIRE_12.g, _entries_T_165
node _entries_T_166 = bits(_entries_WIRE_13, 21, 21)
connect _entries_WIRE_12.u, _entries_T_166
node _entries_T_167 = bits(_entries_WIRE_13, 41, 22)
connect _entries_WIRE_12.ppn, _entries_T_167
inst entries_barrier_6 of OptimizationBarrier_TLBEntryData_119
connect entries_barrier_6.clock, clock
connect entries_barrier_6.reset, reset
connect entries_barrier_6.io.x.fragmented_superpage, _entries_WIRE_12.fragmented_superpage
connect entries_barrier_6.io.x.c, _entries_WIRE_12.c
connect entries_barrier_6.io.x.eff, _entries_WIRE_12.eff
connect entries_barrier_6.io.x.paa, _entries_WIRE_12.paa
connect entries_barrier_6.io.x.pal, _entries_WIRE_12.pal
connect entries_barrier_6.io.x.ppp, _entries_WIRE_12.ppp
connect entries_barrier_6.io.x.pr, _entries_WIRE_12.pr
connect entries_barrier_6.io.x.px, _entries_WIRE_12.px
connect entries_barrier_6.io.x.pw, _entries_WIRE_12.pw
connect entries_barrier_6.io.x.hr, _entries_WIRE_12.hr
connect entries_barrier_6.io.x.hx, _entries_WIRE_12.hx
connect entries_barrier_6.io.x.hw, _entries_WIRE_12.hw
connect entries_barrier_6.io.x.sr, _entries_WIRE_12.sr
connect entries_barrier_6.io.x.sx, _entries_WIRE_12.sx
connect entries_barrier_6.io.x.sw, _entries_WIRE_12.sw
connect entries_barrier_6.io.x.gf, _entries_WIRE_12.gf
connect entries_barrier_6.io.x.pf, _entries_WIRE_12.pf
connect entries_barrier_6.io.x.ae_stage2, _entries_WIRE_12.ae_stage2
connect entries_barrier_6.io.x.ae_final, _entries_WIRE_12.ae_final
connect entries_barrier_6.io.x.ae_ptw, _entries_WIRE_12.ae_ptw
connect entries_barrier_6.io.x.g, _entries_WIRE_12.g
connect entries_barrier_6.io.x.u, _entries_WIRE_12.u
connect entries_barrier_6.io.x.ppn, _entries_WIRE_12.ppn
node _entries_T_168 = bits(vpn, 1, 0)
wire _entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_15 : UInt<42>
connect _entries_WIRE_15, sectored_entries[0][7].data[_entries_T_168]
node _entries_T_169 = bits(_entries_WIRE_15, 0, 0)
connect _entries_WIRE_14.fragmented_superpage, _entries_T_169
node _entries_T_170 = bits(_entries_WIRE_15, 1, 1)
connect _entries_WIRE_14.c, _entries_T_170
node _entries_T_171 = bits(_entries_WIRE_15, 2, 2)
connect _entries_WIRE_14.eff, _entries_T_171
node _entries_T_172 = bits(_entries_WIRE_15, 3, 3)
connect _entries_WIRE_14.paa, _entries_T_172
node _entries_T_173 = bits(_entries_WIRE_15, 4, 4)
connect _entries_WIRE_14.pal, _entries_T_173
node _entries_T_174 = bits(_entries_WIRE_15, 5, 5)
connect _entries_WIRE_14.ppp, _entries_T_174
node _entries_T_175 = bits(_entries_WIRE_15, 6, 6)
connect _entries_WIRE_14.pr, _entries_T_175
node _entries_T_176 = bits(_entries_WIRE_15, 7, 7)
connect _entries_WIRE_14.px, _entries_T_176
node _entries_T_177 = bits(_entries_WIRE_15, 8, 8)
connect _entries_WIRE_14.pw, _entries_T_177
node _entries_T_178 = bits(_entries_WIRE_15, 9, 9)
connect _entries_WIRE_14.hr, _entries_T_178
node _entries_T_179 = bits(_entries_WIRE_15, 10, 10)
connect _entries_WIRE_14.hx, _entries_T_179
node _entries_T_180 = bits(_entries_WIRE_15, 11, 11)
connect _entries_WIRE_14.hw, _entries_T_180
node _entries_T_181 = bits(_entries_WIRE_15, 12, 12)
connect _entries_WIRE_14.sr, _entries_T_181
node _entries_T_182 = bits(_entries_WIRE_15, 13, 13)
connect _entries_WIRE_14.sx, _entries_T_182
node _entries_T_183 = bits(_entries_WIRE_15, 14, 14)
connect _entries_WIRE_14.sw, _entries_T_183
node _entries_T_184 = bits(_entries_WIRE_15, 15, 15)
connect _entries_WIRE_14.gf, _entries_T_184
node _entries_T_185 = bits(_entries_WIRE_15, 16, 16)
connect _entries_WIRE_14.pf, _entries_T_185
node _entries_T_186 = bits(_entries_WIRE_15, 17, 17)
connect _entries_WIRE_14.ae_stage2, _entries_T_186
node _entries_T_187 = bits(_entries_WIRE_15, 18, 18)
connect _entries_WIRE_14.ae_final, _entries_T_187
node _entries_T_188 = bits(_entries_WIRE_15, 19, 19)
connect _entries_WIRE_14.ae_ptw, _entries_T_188
node _entries_T_189 = bits(_entries_WIRE_15, 20, 20)
connect _entries_WIRE_14.g, _entries_T_189
node _entries_T_190 = bits(_entries_WIRE_15, 21, 21)
connect _entries_WIRE_14.u, _entries_T_190
node _entries_T_191 = bits(_entries_WIRE_15, 41, 22)
connect _entries_WIRE_14.ppn, _entries_T_191
inst entries_barrier_7 of OptimizationBarrier_TLBEntryData_120
connect entries_barrier_7.clock, clock
connect entries_barrier_7.reset, reset
connect entries_barrier_7.io.x.fragmented_superpage, _entries_WIRE_14.fragmented_superpage
connect entries_barrier_7.io.x.c, _entries_WIRE_14.c
connect entries_barrier_7.io.x.eff, _entries_WIRE_14.eff
connect entries_barrier_7.io.x.paa, _entries_WIRE_14.paa
connect entries_barrier_7.io.x.pal, _entries_WIRE_14.pal
connect entries_barrier_7.io.x.ppp, _entries_WIRE_14.ppp
connect entries_barrier_7.io.x.pr, _entries_WIRE_14.pr
connect entries_barrier_7.io.x.px, _entries_WIRE_14.px
connect entries_barrier_7.io.x.pw, _entries_WIRE_14.pw
connect entries_barrier_7.io.x.hr, _entries_WIRE_14.hr
connect entries_barrier_7.io.x.hx, _entries_WIRE_14.hx
connect entries_barrier_7.io.x.hw, _entries_WIRE_14.hw
connect entries_barrier_7.io.x.sr, _entries_WIRE_14.sr
connect entries_barrier_7.io.x.sx, _entries_WIRE_14.sx
connect entries_barrier_7.io.x.sw, _entries_WIRE_14.sw
connect entries_barrier_7.io.x.gf, _entries_WIRE_14.gf
connect entries_barrier_7.io.x.pf, _entries_WIRE_14.pf
connect entries_barrier_7.io.x.ae_stage2, _entries_WIRE_14.ae_stage2
connect entries_barrier_7.io.x.ae_final, _entries_WIRE_14.ae_final
connect entries_barrier_7.io.x.ae_ptw, _entries_WIRE_14.ae_ptw
connect entries_barrier_7.io.x.g, _entries_WIRE_14.g
connect entries_barrier_7.io.x.u, _entries_WIRE_14.u
connect entries_barrier_7.io.x.ppn, _entries_WIRE_14.ppn
wire _entries_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_17 : UInt<42>
connect _entries_WIRE_17, superpage_entries[0].data[0]
node _entries_T_192 = bits(_entries_WIRE_17, 0, 0)
connect _entries_WIRE_16.fragmented_superpage, _entries_T_192
node _entries_T_193 = bits(_entries_WIRE_17, 1, 1)
connect _entries_WIRE_16.c, _entries_T_193
node _entries_T_194 = bits(_entries_WIRE_17, 2, 2)
connect _entries_WIRE_16.eff, _entries_T_194
node _entries_T_195 = bits(_entries_WIRE_17, 3, 3)
connect _entries_WIRE_16.paa, _entries_T_195
node _entries_T_196 = bits(_entries_WIRE_17, 4, 4)
connect _entries_WIRE_16.pal, _entries_T_196
node _entries_T_197 = bits(_entries_WIRE_17, 5, 5)
connect _entries_WIRE_16.ppp, _entries_T_197
node _entries_T_198 = bits(_entries_WIRE_17, 6, 6)
connect _entries_WIRE_16.pr, _entries_T_198
node _entries_T_199 = bits(_entries_WIRE_17, 7, 7)
connect _entries_WIRE_16.px, _entries_T_199
node _entries_T_200 = bits(_entries_WIRE_17, 8, 8)
connect _entries_WIRE_16.pw, _entries_T_200
node _entries_T_201 = bits(_entries_WIRE_17, 9, 9)
connect _entries_WIRE_16.hr, _entries_T_201
node _entries_T_202 = bits(_entries_WIRE_17, 10, 10)
connect _entries_WIRE_16.hx, _entries_T_202
node _entries_T_203 = bits(_entries_WIRE_17, 11, 11)
connect _entries_WIRE_16.hw, _entries_T_203
node _entries_T_204 = bits(_entries_WIRE_17, 12, 12)
connect _entries_WIRE_16.sr, _entries_T_204
node _entries_T_205 = bits(_entries_WIRE_17, 13, 13)
connect _entries_WIRE_16.sx, _entries_T_205
node _entries_T_206 = bits(_entries_WIRE_17, 14, 14)
connect _entries_WIRE_16.sw, _entries_T_206
node _entries_T_207 = bits(_entries_WIRE_17, 15, 15)
connect _entries_WIRE_16.gf, _entries_T_207
node _entries_T_208 = bits(_entries_WIRE_17, 16, 16)
connect _entries_WIRE_16.pf, _entries_T_208
node _entries_T_209 = bits(_entries_WIRE_17, 17, 17)
connect _entries_WIRE_16.ae_stage2, _entries_T_209
node _entries_T_210 = bits(_entries_WIRE_17, 18, 18)
connect _entries_WIRE_16.ae_final, _entries_T_210
node _entries_T_211 = bits(_entries_WIRE_17, 19, 19)
connect _entries_WIRE_16.ae_ptw, _entries_T_211
node _entries_T_212 = bits(_entries_WIRE_17, 20, 20)
connect _entries_WIRE_16.g, _entries_T_212
node _entries_T_213 = bits(_entries_WIRE_17, 21, 21)
connect _entries_WIRE_16.u, _entries_T_213
node _entries_T_214 = bits(_entries_WIRE_17, 41, 22)
connect _entries_WIRE_16.ppn, _entries_T_214
inst entries_barrier_8 of OptimizationBarrier_TLBEntryData_121
connect entries_barrier_8.clock, clock
connect entries_barrier_8.reset, reset
connect entries_barrier_8.io.x.fragmented_superpage, _entries_WIRE_16.fragmented_superpage
connect entries_barrier_8.io.x.c, _entries_WIRE_16.c
connect entries_barrier_8.io.x.eff, _entries_WIRE_16.eff
connect entries_barrier_8.io.x.paa, _entries_WIRE_16.paa
connect entries_barrier_8.io.x.pal, _entries_WIRE_16.pal
connect entries_barrier_8.io.x.ppp, _entries_WIRE_16.ppp
connect entries_barrier_8.io.x.pr, _entries_WIRE_16.pr
connect entries_barrier_8.io.x.px, _entries_WIRE_16.px
connect entries_barrier_8.io.x.pw, _entries_WIRE_16.pw
connect entries_barrier_8.io.x.hr, _entries_WIRE_16.hr
connect entries_barrier_8.io.x.hx, _entries_WIRE_16.hx
connect entries_barrier_8.io.x.hw, _entries_WIRE_16.hw
connect entries_barrier_8.io.x.sr, _entries_WIRE_16.sr
connect entries_barrier_8.io.x.sx, _entries_WIRE_16.sx
connect entries_barrier_8.io.x.sw, _entries_WIRE_16.sw
connect entries_barrier_8.io.x.gf, _entries_WIRE_16.gf
connect entries_barrier_8.io.x.pf, _entries_WIRE_16.pf
connect entries_barrier_8.io.x.ae_stage2, _entries_WIRE_16.ae_stage2
connect entries_barrier_8.io.x.ae_final, _entries_WIRE_16.ae_final
connect entries_barrier_8.io.x.ae_ptw, _entries_WIRE_16.ae_ptw
connect entries_barrier_8.io.x.g, _entries_WIRE_16.g
connect entries_barrier_8.io.x.u, _entries_WIRE_16.u
connect entries_barrier_8.io.x.ppn, _entries_WIRE_16.ppn
wire _entries_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_19 : UInt<42>
connect _entries_WIRE_19, superpage_entries[1].data[0]
node _entries_T_215 = bits(_entries_WIRE_19, 0, 0)
connect _entries_WIRE_18.fragmented_superpage, _entries_T_215
node _entries_T_216 = bits(_entries_WIRE_19, 1, 1)
connect _entries_WIRE_18.c, _entries_T_216
node _entries_T_217 = bits(_entries_WIRE_19, 2, 2)
connect _entries_WIRE_18.eff, _entries_T_217
node _entries_T_218 = bits(_entries_WIRE_19, 3, 3)
connect _entries_WIRE_18.paa, _entries_T_218
node _entries_T_219 = bits(_entries_WIRE_19, 4, 4)
connect _entries_WIRE_18.pal, _entries_T_219
node _entries_T_220 = bits(_entries_WIRE_19, 5, 5)
connect _entries_WIRE_18.ppp, _entries_T_220
node _entries_T_221 = bits(_entries_WIRE_19, 6, 6)
connect _entries_WIRE_18.pr, _entries_T_221
node _entries_T_222 = bits(_entries_WIRE_19, 7, 7)
connect _entries_WIRE_18.px, _entries_T_222
node _entries_T_223 = bits(_entries_WIRE_19, 8, 8)
connect _entries_WIRE_18.pw, _entries_T_223
node _entries_T_224 = bits(_entries_WIRE_19, 9, 9)
connect _entries_WIRE_18.hr, _entries_T_224
node _entries_T_225 = bits(_entries_WIRE_19, 10, 10)
connect _entries_WIRE_18.hx, _entries_T_225
node _entries_T_226 = bits(_entries_WIRE_19, 11, 11)
connect _entries_WIRE_18.hw, _entries_T_226
node _entries_T_227 = bits(_entries_WIRE_19, 12, 12)
connect _entries_WIRE_18.sr, _entries_T_227
node _entries_T_228 = bits(_entries_WIRE_19, 13, 13)
connect _entries_WIRE_18.sx, _entries_T_228
node _entries_T_229 = bits(_entries_WIRE_19, 14, 14)
connect _entries_WIRE_18.sw, _entries_T_229
node _entries_T_230 = bits(_entries_WIRE_19, 15, 15)
connect _entries_WIRE_18.gf, _entries_T_230
node _entries_T_231 = bits(_entries_WIRE_19, 16, 16)
connect _entries_WIRE_18.pf, _entries_T_231
node _entries_T_232 = bits(_entries_WIRE_19, 17, 17)
connect _entries_WIRE_18.ae_stage2, _entries_T_232
node _entries_T_233 = bits(_entries_WIRE_19, 18, 18)
connect _entries_WIRE_18.ae_final, _entries_T_233
node _entries_T_234 = bits(_entries_WIRE_19, 19, 19)
connect _entries_WIRE_18.ae_ptw, _entries_T_234
node _entries_T_235 = bits(_entries_WIRE_19, 20, 20)
connect _entries_WIRE_18.g, _entries_T_235
node _entries_T_236 = bits(_entries_WIRE_19, 21, 21)
connect _entries_WIRE_18.u, _entries_T_236
node _entries_T_237 = bits(_entries_WIRE_19, 41, 22)
connect _entries_WIRE_18.ppn, _entries_T_237
inst entries_barrier_9 of OptimizationBarrier_TLBEntryData_122
connect entries_barrier_9.clock, clock
connect entries_barrier_9.reset, reset
connect entries_barrier_9.io.x.fragmented_superpage, _entries_WIRE_18.fragmented_superpage
connect entries_barrier_9.io.x.c, _entries_WIRE_18.c
connect entries_barrier_9.io.x.eff, _entries_WIRE_18.eff
connect entries_barrier_9.io.x.paa, _entries_WIRE_18.paa
connect entries_barrier_9.io.x.pal, _entries_WIRE_18.pal
connect entries_barrier_9.io.x.ppp, _entries_WIRE_18.ppp
connect entries_barrier_9.io.x.pr, _entries_WIRE_18.pr
connect entries_barrier_9.io.x.px, _entries_WIRE_18.px
connect entries_barrier_9.io.x.pw, _entries_WIRE_18.pw
connect entries_barrier_9.io.x.hr, _entries_WIRE_18.hr
connect entries_barrier_9.io.x.hx, _entries_WIRE_18.hx
connect entries_barrier_9.io.x.hw, _entries_WIRE_18.hw
connect entries_barrier_9.io.x.sr, _entries_WIRE_18.sr
connect entries_barrier_9.io.x.sx, _entries_WIRE_18.sx
connect entries_barrier_9.io.x.sw, _entries_WIRE_18.sw
connect entries_barrier_9.io.x.gf, _entries_WIRE_18.gf
connect entries_barrier_9.io.x.pf, _entries_WIRE_18.pf
connect entries_barrier_9.io.x.ae_stage2, _entries_WIRE_18.ae_stage2
connect entries_barrier_9.io.x.ae_final, _entries_WIRE_18.ae_final
connect entries_barrier_9.io.x.ae_ptw, _entries_WIRE_18.ae_ptw
connect entries_barrier_9.io.x.g, _entries_WIRE_18.g
connect entries_barrier_9.io.x.u, _entries_WIRE_18.u
connect entries_barrier_9.io.x.ppn, _entries_WIRE_18.ppn
wire _entries_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_21 : UInt<42>
connect _entries_WIRE_21, superpage_entries[2].data[0]
node _entries_T_238 = bits(_entries_WIRE_21, 0, 0)
connect _entries_WIRE_20.fragmented_superpage, _entries_T_238
node _entries_T_239 = bits(_entries_WIRE_21, 1, 1)
connect _entries_WIRE_20.c, _entries_T_239
node _entries_T_240 = bits(_entries_WIRE_21, 2, 2)
connect _entries_WIRE_20.eff, _entries_T_240
node _entries_T_241 = bits(_entries_WIRE_21, 3, 3)
connect _entries_WIRE_20.paa, _entries_T_241
node _entries_T_242 = bits(_entries_WIRE_21, 4, 4)
connect _entries_WIRE_20.pal, _entries_T_242
node _entries_T_243 = bits(_entries_WIRE_21, 5, 5)
connect _entries_WIRE_20.ppp, _entries_T_243
node _entries_T_244 = bits(_entries_WIRE_21, 6, 6)
connect _entries_WIRE_20.pr, _entries_T_244
node _entries_T_245 = bits(_entries_WIRE_21, 7, 7)
connect _entries_WIRE_20.px, _entries_T_245
node _entries_T_246 = bits(_entries_WIRE_21, 8, 8)
connect _entries_WIRE_20.pw, _entries_T_246
node _entries_T_247 = bits(_entries_WIRE_21, 9, 9)
connect _entries_WIRE_20.hr, _entries_T_247
node _entries_T_248 = bits(_entries_WIRE_21, 10, 10)
connect _entries_WIRE_20.hx, _entries_T_248
node _entries_T_249 = bits(_entries_WIRE_21, 11, 11)
connect _entries_WIRE_20.hw, _entries_T_249
node _entries_T_250 = bits(_entries_WIRE_21, 12, 12)
connect _entries_WIRE_20.sr, _entries_T_250
node _entries_T_251 = bits(_entries_WIRE_21, 13, 13)
connect _entries_WIRE_20.sx, _entries_T_251
node _entries_T_252 = bits(_entries_WIRE_21, 14, 14)
connect _entries_WIRE_20.sw, _entries_T_252
node _entries_T_253 = bits(_entries_WIRE_21, 15, 15)
connect _entries_WIRE_20.gf, _entries_T_253
node _entries_T_254 = bits(_entries_WIRE_21, 16, 16)
connect _entries_WIRE_20.pf, _entries_T_254
node _entries_T_255 = bits(_entries_WIRE_21, 17, 17)
connect _entries_WIRE_20.ae_stage2, _entries_T_255
node _entries_T_256 = bits(_entries_WIRE_21, 18, 18)
connect _entries_WIRE_20.ae_final, _entries_T_256
node _entries_T_257 = bits(_entries_WIRE_21, 19, 19)
connect _entries_WIRE_20.ae_ptw, _entries_T_257
node _entries_T_258 = bits(_entries_WIRE_21, 20, 20)
connect _entries_WIRE_20.g, _entries_T_258
node _entries_T_259 = bits(_entries_WIRE_21, 21, 21)
connect _entries_WIRE_20.u, _entries_T_259
node _entries_T_260 = bits(_entries_WIRE_21, 41, 22)
connect _entries_WIRE_20.ppn, _entries_T_260
inst entries_barrier_10 of OptimizationBarrier_TLBEntryData_123
connect entries_barrier_10.clock, clock
connect entries_barrier_10.reset, reset
connect entries_barrier_10.io.x.fragmented_superpage, _entries_WIRE_20.fragmented_superpage
connect entries_barrier_10.io.x.c, _entries_WIRE_20.c
connect entries_barrier_10.io.x.eff, _entries_WIRE_20.eff
connect entries_barrier_10.io.x.paa, _entries_WIRE_20.paa
connect entries_barrier_10.io.x.pal, _entries_WIRE_20.pal
connect entries_barrier_10.io.x.ppp, _entries_WIRE_20.ppp
connect entries_barrier_10.io.x.pr, _entries_WIRE_20.pr
connect entries_barrier_10.io.x.px, _entries_WIRE_20.px
connect entries_barrier_10.io.x.pw, _entries_WIRE_20.pw
connect entries_barrier_10.io.x.hr, _entries_WIRE_20.hr
connect entries_barrier_10.io.x.hx, _entries_WIRE_20.hx
connect entries_barrier_10.io.x.hw, _entries_WIRE_20.hw
connect entries_barrier_10.io.x.sr, _entries_WIRE_20.sr
connect entries_barrier_10.io.x.sx, _entries_WIRE_20.sx
connect entries_barrier_10.io.x.sw, _entries_WIRE_20.sw
connect entries_barrier_10.io.x.gf, _entries_WIRE_20.gf
connect entries_barrier_10.io.x.pf, _entries_WIRE_20.pf
connect entries_barrier_10.io.x.ae_stage2, _entries_WIRE_20.ae_stage2
connect entries_barrier_10.io.x.ae_final, _entries_WIRE_20.ae_final
connect entries_barrier_10.io.x.ae_ptw, _entries_WIRE_20.ae_ptw
connect entries_barrier_10.io.x.g, _entries_WIRE_20.g
connect entries_barrier_10.io.x.u, _entries_WIRE_20.u
connect entries_barrier_10.io.x.ppn, _entries_WIRE_20.ppn
wire _entries_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_23 : UInt<42>
connect _entries_WIRE_23, superpage_entries[3].data[0]
node _entries_T_261 = bits(_entries_WIRE_23, 0, 0)
connect _entries_WIRE_22.fragmented_superpage, _entries_T_261
node _entries_T_262 = bits(_entries_WIRE_23, 1, 1)
connect _entries_WIRE_22.c, _entries_T_262
node _entries_T_263 = bits(_entries_WIRE_23, 2, 2)
connect _entries_WIRE_22.eff, _entries_T_263
node _entries_T_264 = bits(_entries_WIRE_23, 3, 3)
connect _entries_WIRE_22.paa, _entries_T_264
node _entries_T_265 = bits(_entries_WIRE_23, 4, 4)
connect _entries_WIRE_22.pal, _entries_T_265
node _entries_T_266 = bits(_entries_WIRE_23, 5, 5)
connect _entries_WIRE_22.ppp, _entries_T_266
node _entries_T_267 = bits(_entries_WIRE_23, 6, 6)
connect _entries_WIRE_22.pr, _entries_T_267
node _entries_T_268 = bits(_entries_WIRE_23, 7, 7)
connect _entries_WIRE_22.px, _entries_T_268
node _entries_T_269 = bits(_entries_WIRE_23, 8, 8)
connect _entries_WIRE_22.pw, _entries_T_269
node _entries_T_270 = bits(_entries_WIRE_23, 9, 9)
connect _entries_WIRE_22.hr, _entries_T_270
node _entries_T_271 = bits(_entries_WIRE_23, 10, 10)
connect _entries_WIRE_22.hx, _entries_T_271
node _entries_T_272 = bits(_entries_WIRE_23, 11, 11)
connect _entries_WIRE_22.hw, _entries_T_272
node _entries_T_273 = bits(_entries_WIRE_23, 12, 12)
connect _entries_WIRE_22.sr, _entries_T_273
node _entries_T_274 = bits(_entries_WIRE_23, 13, 13)
connect _entries_WIRE_22.sx, _entries_T_274
node _entries_T_275 = bits(_entries_WIRE_23, 14, 14)
connect _entries_WIRE_22.sw, _entries_T_275
node _entries_T_276 = bits(_entries_WIRE_23, 15, 15)
connect _entries_WIRE_22.gf, _entries_T_276
node _entries_T_277 = bits(_entries_WIRE_23, 16, 16)
connect _entries_WIRE_22.pf, _entries_T_277
node _entries_T_278 = bits(_entries_WIRE_23, 17, 17)
connect _entries_WIRE_22.ae_stage2, _entries_T_278
node _entries_T_279 = bits(_entries_WIRE_23, 18, 18)
connect _entries_WIRE_22.ae_final, _entries_T_279
node _entries_T_280 = bits(_entries_WIRE_23, 19, 19)
connect _entries_WIRE_22.ae_ptw, _entries_T_280
node _entries_T_281 = bits(_entries_WIRE_23, 20, 20)
connect _entries_WIRE_22.g, _entries_T_281
node _entries_T_282 = bits(_entries_WIRE_23, 21, 21)
connect _entries_WIRE_22.u, _entries_T_282
node _entries_T_283 = bits(_entries_WIRE_23, 41, 22)
connect _entries_WIRE_22.ppn, _entries_T_283
inst entries_barrier_11 of OptimizationBarrier_TLBEntryData_124
connect entries_barrier_11.clock, clock
connect entries_barrier_11.reset, reset
connect entries_barrier_11.io.x.fragmented_superpage, _entries_WIRE_22.fragmented_superpage
connect entries_barrier_11.io.x.c, _entries_WIRE_22.c
connect entries_barrier_11.io.x.eff, _entries_WIRE_22.eff
connect entries_barrier_11.io.x.paa, _entries_WIRE_22.paa
connect entries_barrier_11.io.x.pal, _entries_WIRE_22.pal
connect entries_barrier_11.io.x.ppp, _entries_WIRE_22.ppp
connect entries_barrier_11.io.x.pr, _entries_WIRE_22.pr
connect entries_barrier_11.io.x.px, _entries_WIRE_22.px
connect entries_barrier_11.io.x.pw, _entries_WIRE_22.pw
connect entries_barrier_11.io.x.hr, _entries_WIRE_22.hr
connect entries_barrier_11.io.x.hx, _entries_WIRE_22.hx
connect entries_barrier_11.io.x.hw, _entries_WIRE_22.hw
connect entries_barrier_11.io.x.sr, _entries_WIRE_22.sr
connect entries_barrier_11.io.x.sx, _entries_WIRE_22.sx
connect entries_barrier_11.io.x.sw, _entries_WIRE_22.sw
connect entries_barrier_11.io.x.gf, _entries_WIRE_22.gf
connect entries_barrier_11.io.x.pf, _entries_WIRE_22.pf
connect entries_barrier_11.io.x.ae_stage2, _entries_WIRE_22.ae_stage2
connect entries_barrier_11.io.x.ae_final, _entries_WIRE_22.ae_final
connect entries_barrier_11.io.x.ae_ptw, _entries_WIRE_22.ae_ptw
connect entries_barrier_11.io.x.g, _entries_WIRE_22.g
connect entries_barrier_11.io.x.u, _entries_WIRE_22.u
connect entries_barrier_11.io.x.ppn, _entries_WIRE_22.ppn
wire _entries_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_25 : UInt<42>
connect _entries_WIRE_25, special_entry.data[0]
node _entries_T_284 = bits(_entries_WIRE_25, 0, 0)
connect _entries_WIRE_24.fragmented_superpage, _entries_T_284
node _entries_T_285 = bits(_entries_WIRE_25, 1, 1)
connect _entries_WIRE_24.c, _entries_T_285
node _entries_T_286 = bits(_entries_WIRE_25, 2, 2)
connect _entries_WIRE_24.eff, _entries_T_286
node _entries_T_287 = bits(_entries_WIRE_25, 3, 3)
connect _entries_WIRE_24.paa, _entries_T_287
node _entries_T_288 = bits(_entries_WIRE_25, 4, 4)
connect _entries_WIRE_24.pal, _entries_T_288
node _entries_T_289 = bits(_entries_WIRE_25, 5, 5)
connect _entries_WIRE_24.ppp, _entries_T_289
node _entries_T_290 = bits(_entries_WIRE_25, 6, 6)
connect _entries_WIRE_24.pr, _entries_T_290
node _entries_T_291 = bits(_entries_WIRE_25, 7, 7)
connect _entries_WIRE_24.px, _entries_T_291
node _entries_T_292 = bits(_entries_WIRE_25, 8, 8)
connect _entries_WIRE_24.pw, _entries_T_292
node _entries_T_293 = bits(_entries_WIRE_25, 9, 9)
connect _entries_WIRE_24.hr, _entries_T_293
node _entries_T_294 = bits(_entries_WIRE_25, 10, 10)
connect _entries_WIRE_24.hx, _entries_T_294
node _entries_T_295 = bits(_entries_WIRE_25, 11, 11)
connect _entries_WIRE_24.hw, _entries_T_295
node _entries_T_296 = bits(_entries_WIRE_25, 12, 12)
connect _entries_WIRE_24.sr, _entries_T_296
node _entries_T_297 = bits(_entries_WIRE_25, 13, 13)
connect _entries_WIRE_24.sx, _entries_T_297
node _entries_T_298 = bits(_entries_WIRE_25, 14, 14)
connect _entries_WIRE_24.sw, _entries_T_298
node _entries_T_299 = bits(_entries_WIRE_25, 15, 15)
connect _entries_WIRE_24.gf, _entries_T_299
node _entries_T_300 = bits(_entries_WIRE_25, 16, 16)
connect _entries_WIRE_24.pf, _entries_T_300
node _entries_T_301 = bits(_entries_WIRE_25, 17, 17)
connect _entries_WIRE_24.ae_stage2, _entries_T_301
node _entries_T_302 = bits(_entries_WIRE_25, 18, 18)
connect _entries_WIRE_24.ae_final, _entries_T_302
node _entries_T_303 = bits(_entries_WIRE_25, 19, 19)
connect _entries_WIRE_24.ae_ptw, _entries_T_303
node _entries_T_304 = bits(_entries_WIRE_25, 20, 20)
connect _entries_WIRE_24.g, _entries_T_304
node _entries_T_305 = bits(_entries_WIRE_25, 21, 21)
connect _entries_WIRE_24.u, _entries_T_305
node _entries_T_306 = bits(_entries_WIRE_25, 41, 22)
connect _entries_WIRE_24.ppn, _entries_T_306
inst entries_barrier_12 of OptimizationBarrier_TLBEntryData_125
connect entries_barrier_12.clock, clock
connect entries_barrier_12.reset, reset
connect entries_barrier_12.io.x.fragmented_superpage, _entries_WIRE_24.fragmented_superpage
connect entries_barrier_12.io.x.c, _entries_WIRE_24.c
connect entries_barrier_12.io.x.eff, _entries_WIRE_24.eff
connect entries_barrier_12.io.x.paa, _entries_WIRE_24.paa
connect entries_barrier_12.io.x.pal, _entries_WIRE_24.pal
connect entries_barrier_12.io.x.ppp, _entries_WIRE_24.ppp
connect entries_barrier_12.io.x.pr, _entries_WIRE_24.pr
connect entries_barrier_12.io.x.px, _entries_WIRE_24.px
connect entries_barrier_12.io.x.pw, _entries_WIRE_24.pw
connect entries_barrier_12.io.x.hr, _entries_WIRE_24.hr
connect entries_barrier_12.io.x.hx, _entries_WIRE_24.hx
connect entries_barrier_12.io.x.hw, _entries_WIRE_24.hw
connect entries_barrier_12.io.x.sr, _entries_WIRE_24.sr
connect entries_barrier_12.io.x.sx, _entries_WIRE_24.sx
connect entries_barrier_12.io.x.sw, _entries_WIRE_24.sw
connect entries_barrier_12.io.x.gf, _entries_WIRE_24.gf
connect entries_barrier_12.io.x.pf, _entries_WIRE_24.pf
connect entries_barrier_12.io.x.ae_stage2, _entries_WIRE_24.ae_stage2
connect entries_barrier_12.io.x.ae_final, _entries_WIRE_24.ae_final
connect entries_barrier_12.io.x.ae_ptw, _entries_WIRE_24.ae_ptw
connect entries_barrier_12.io.x.g, _entries_WIRE_24.g
connect entries_barrier_12.io.x.u, _entries_WIRE_24.u
connect entries_barrier_12.io.x.ppn, _entries_WIRE_24.ppn
node _ppn_T = eq(vm_enabled, UInt<1>(0h0))
node ppn_res = shr(entries_barrier_8.io.y.ppn, 18)
node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1))
node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0))
node _ppn_T_1 = mux(ppn_ignore, vpn, UInt<1>(0h0))
node _ppn_T_2 = or(_ppn_T_1, entries_barrier_8.io.y.ppn)
node _ppn_T_3 = bits(_ppn_T_2, 17, 9)
node _ppn_T_4 = cat(ppn_res, _ppn_T_3)
node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2))
node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1))
node _ppn_T_5 = mux(ppn_ignore_1, vpn, UInt<1>(0h0))
node _ppn_T_6 = or(_ppn_T_5, entries_barrier_8.io.y.ppn)
node _ppn_T_7 = bits(_ppn_T_6, 8, 0)
node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7)
node ppn_res_1 = shr(entries_barrier_9.io.y.ppn, 18)
node _ppn_ignore_T_2 = lt(superpage_entries[1].level, UInt<1>(0h1))
node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0))
node _ppn_T_9 = mux(ppn_ignore_2, vpn, UInt<1>(0h0))
node _ppn_T_10 = or(_ppn_T_9, entries_barrier_9.io.y.ppn)
node _ppn_T_11 = bits(_ppn_T_10, 17, 9)
node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11)
node _ppn_ignore_T_3 = lt(superpage_entries[1].level, UInt<2>(0h2))
node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h1))
node _ppn_T_13 = mux(ppn_ignore_3, vpn, UInt<1>(0h0))
node _ppn_T_14 = or(_ppn_T_13, entries_barrier_9.io.y.ppn)
node _ppn_T_15 = bits(_ppn_T_14, 8, 0)
node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15)
node ppn_res_2 = shr(entries_barrier_10.io.y.ppn, 18)
node _ppn_ignore_T_4 = lt(superpage_entries[2].level, UInt<1>(0h1))
node ppn_ignore_4 = or(_ppn_ignore_T_4, UInt<1>(0h0))
node _ppn_T_17 = mux(ppn_ignore_4, vpn, UInt<1>(0h0))
node _ppn_T_18 = or(_ppn_T_17, entries_barrier_10.io.y.ppn)
node _ppn_T_19 = bits(_ppn_T_18, 17, 9)
node _ppn_T_20 = cat(ppn_res_2, _ppn_T_19)
node _ppn_ignore_T_5 = lt(superpage_entries[2].level, UInt<2>(0h2))
node ppn_ignore_5 = or(_ppn_ignore_T_5, UInt<1>(0h1))
node _ppn_T_21 = mux(ppn_ignore_5, vpn, UInt<1>(0h0))
node _ppn_T_22 = or(_ppn_T_21, entries_barrier_10.io.y.ppn)
node _ppn_T_23 = bits(_ppn_T_22, 8, 0)
node _ppn_T_24 = cat(_ppn_T_20, _ppn_T_23)
node ppn_res_3 = shr(entries_barrier_11.io.y.ppn, 18)
node _ppn_ignore_T_6 = lt(superpage_entries[3].level, UInt<1>(0h1))
node ppn_ignore_6 = or(_ppn_ignore_T_6, UInt<1>(0h0))
node _ppn_T_25 = mux(ppn_ignore_6, vpn, UInt<1>(0h0))
node _ppn_T_26 = or(_ppn_T_25, entries_barrier_11.io.y.ppn)
node _ppn_T_27 = bits(_ppn_T_26, 17, 9)
node _ppn_T_28 = cat(ppn_res_3, _ppn_T_27)
node _ppn_ignore_T_7 = lt(superpage_entries[3].level, UInt<2>(0h2))
node ppn_ignore_7 = or(_ppn_ignore_T_7, UInt<1>(0h1))
node _ppn_T_29 = mux(ppn_ignore_7, vpn, UInt<1>(0h0))
node _ppn_T_30 = or(_ppn_T_29, entries_barrier_11.io.y.ppn)
node _ppn_T_31 = bits(_ppn_T_30, 8, 0)
node _ppn_T_32 = cat(_ppn_T_28, _ppn_T_31)
node ppn_res_4 = shr(entries_barrier_12.io.y.ppn, 18)
node _ppn_ignore_T_8 = lt(special_entry.level, UInt<1>(0h1))
node ppn_ignore_8 = or(_ppn_ignore_T_8, UInt<1>(0h0))
node _ppn_T_33 = mux(ppn_ignore_8, vpn, UInt<1>(0h0))
node _ppn_T_34 = or(_ppn_T_33, entries_barrier_12.io.y.ppn)
node _ppn_T_35 = bits(_ppn_T_34, 17, 9)
node _ppn_T_36 = cat(ppn_res_4, _ppn_T_35)
node _ppn_ignore_T_9 = lt(special_entry.level, UInt<2>(0h2))
node ppn_ignore_9 = or(_ppn_ignore_T_9, UInt<1>(0h0))
node _ppn_T_37 = mux(ppn_ignore_9, vpn, UInt<1>(0h0))
node _ppn_T_38 = or(_ppn_T_37, entries_barrier_12.io.y.ppn)
node _ppn_T_39 = bits(_ppn_T_38, 8, 0)
node _ppn_T_40 = cat(_ppn_T_36, _ppn_T_39)
node _ppn_T_41 = bits(vpn, 19, 0)
node _ppn_T_42 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0))
node _ppn_T_43 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0))
node _ppn_T_44 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0))
node _ppn_T_45 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0))
node _ppn_T_46 = mux(hitsVec_4, entries_barrier_4.io.y.ppn, UInt<1>(0h0))
node _ppn_T_47 = mux(hitsVec_5, entries_barrier_5.io.y.ppn, UInt<1>(0h0))
node _ppn_T_48 = mux(hitsVec_6, entries_barrier_6.io.y.ppn, UInt<1>(0h0))
node _ppn_T_49 = mux(hitsVec_7, entries_barrier_7.io.y.ppn, UInt<1>(0h0))
node _ppn_T_50 = mux(hitsVec_8, _ppn_T_8, UInt<1>(0h0))
node _ppn_T_51 = mux(hitsVec_9, _ppn_T_16, UInt<1>(0h0))
node _ppn_T_52 = mux(hitsVec_10, _ppn_T_24, UInt<1>(0h0))
node _ppn_T_53 = mux(hitsVec_11, _ppn_T_32, UInt<1>(0h0))
node _ppn_T_54 = mux(hitsVec_12, _ppn_T_40, UInt<1>(0h0))
node _ppn_T_55 = mux(_ppn_T, _ppn_T_41, UInt<1>(0h0))
node _ppn_T_56 = or(_ppn_T_42, _ppn_T_43)
node _ppn_T_57 = or(_ppn_T_56, _ppn_T_44)
node _ppn_T_58 = or(_ppn_T_57, _ppn_T_45)
node _ppn_T_59 = or(_ppn_T_58, _ppn_T_46)
node _ppn_T_60 = or(_ppn_T_59, _ppn_T_47)
node _ppn_T_61 = or(_ppn_T_60, _ppn_T_48)
node _ppn_T_62 = or(_ppn_T_61, _ppn_T_49)
node _ppn_T_63 = or(_ppn_T_62, _ppn_T_50)
node _ppn_T_64 = or(_ppn_T_63, _ppn_T_51)
node _ppn_T_65 = or(_ppn_T_64, _ppn_T_52)
node _ppn_T_66 = or(_ppn_T_65, _ppn_T_53)
node _ppn_T_67 = or(_ppn_T_66, _ppn_T_54)
node _ppn_T_68 = or(_ppn_T_67, _ppn_T_55)
wire ppn : UInt<20>
connect ppn, _ppn_T_68
node ptw_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw)
node ptw_ae_array_lo_lo = cat(ptw_ae_array_lo_lo_hi, entries_barrier.io.y.ae_ptw)
node ptw_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw)
node ptw_ae_array_lo_hi = cat(ptw_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_ptw)
node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, ptw_ae_array_lo_lo)
node ptw_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_ptw, entries_barrier_7.io.y.ae_ptw)
node ptw_ae_array_hi_lo = cat(ptw_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_ptw)
node ptw_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_ptw, entries_barrier_9.io.y.ae_ptw)
node ptw_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_ptw, entries_barrier_11.io.y.ae_ptw)
node ptw_ae_array_hi_hi = cat(ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo)
node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, ptw_ae_array_hi_lo)
node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo)
node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T)
node final_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final)
node final_ae_array_lo_lo = cat(final_ae_array_lo_lo_hi, entries_barrier.io.y.ae_final)
node final_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final)
node final_ae_array_lo_hi = cat(final_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_final)
node final_ae_array_lo = cat(final_ae_array_lo_hi, final_ae_array_lo_lo)
node final_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_final, entries_barrier_7.io.y.ae_final)
node final_ae_array_hi_lo = cat(final_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_final)
node final_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_final, entries_barrier_9.io.y.ae_final)
node final_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_final, entries_barrier_11.io.y.ae_final)
node final_ae_array_hi_hi = cat(final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo)
node final_ae_array_hi = cat(final_ae_array_hi_hi, final_ae_array_hi_lo)
node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo)
node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T)
node ptw_pf_array_lo_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf)
node ptw_pf_array_lo_lo = cat(ptw_pf_array_lo_lo_hi, entries_barrier.io.y.pf)
node ptw_pf_array_lo_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf)
node ptw_pf_array_lo_hi = cat(ptw_pf_array_lo_hi_hi, entries_barrier_3.io.y.pf)
node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, ptw_pf_array_lo_lo)
node ptw_pf_array_hi_lo_hi = cat(entries_barrier_8.io.y.pf, entries_barrier_7.io.y.pf)
node ptw_pf_array_hi_lo = cat(ptw_pf_array_hi_lo_hi, entries_barrier_6.io.y.pf)
node ptw_pf_array_hi_hi_lo = cat(entries_barrier_10.io.y.pf, entries_barrier_9.io.y.pf)
node ptw_pf_array_hi_hi_hi = cat(entries_barrier_12.io.y.pf, entries_barrier_11.io.y.pf)
node ptw_pf_array_hi_hi = cat(ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo)
node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, ptw_pf_array_hi_lo)
node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo)
node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T)
node ptw_gf_array_lo_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf)
node ptw_gf_array_lo_lo = cat(ptw_gf_array_lo_lo_hi, entries_barrier.io.y.gf)
node ptw_gf_array_lo_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf)
node ptw_gf_array_lo_hi = cat(ptw_gf_array_lo_hi_hi, entries_barrier_3.io.y.gf)
node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, ptw_gf_array_lo_lo)
node ptw_gf_array_hi_lo_hi = cat(entries_barrier_8.io.y.gf, entries_barrier_7.io.y.gf)
node ptw_gf_array_hi_lo = cat(ptw_gf_array_hi_lo_hi, entries_barrier_6.io.y.gf)
node ptw_gf_array_hi_hi_lo = cat(entries_barrier_10.io.y.gf, entries_barrier_9.io.y.gf)
node ptw_gf_array_hi_hi_hi = cat(entries_barrier_12.io.y.gf, entries_barrier_11.io.y.gf)
node ptw_gf_array_hi_hi = cat(ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo)
node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, ptw_gf_array_hi_lo)
node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo)
node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T)
node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum)
node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0))
node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum)
node priv_rw_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_rw_ok_lo_lo = cat(priv_rw_ok_lo_lo_hi, entries_barrier.io.y.u)
node priv_rw_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_rw_ok_lo_hi = cat(priv_rw_ok_lo_hi_hi, entries_barrier_3.io.y.u)
node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, priv_rw_ok_lo_lo)
node priv_rw_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_rw_ok_hi_lo = cat(priv_rw_ok_hi_lo_hi, entries_barrier_6.io.y.u)
node priv_rw_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_rw_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_rw_ok_hi_hi = cat(priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo)
node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, priv_rw_ok_hi_lo)
node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo)
node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0))
node priv_rw_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_rw_ok_lo_lo_1 = cat(priv_rw_ok_lo_lo_hi_1, entries_barrier.io.y.u)
node priv_rw_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_rw_ok_lo_hi_1 = cat(priv_rw_ok_lo_hi_hi_1, entries_barrier_3.io.y.u)
node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1)
node priv_rw_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_rw_ok_hi_lo_1 = cat(priv_rw_ok_hi_lo_hi_1, entries_barrier_6.io.y.u)
node priv_rw_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_rw_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_rw_ok_hi_hi_1 = cat(priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1)
node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1)
node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1)
node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4)
node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0))
node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6)
node priv_x_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_x_ok_lo_lo = cat(priv_x_ok_lo_lo_hi, entries_barrier.io.y.u)
node priv_x_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_x_ok_lo_hi = cat(priv_x_ok_lo_hi_hi, entries_barrier_3.io.y.u)
node priv_x_ok_lo = cat(priv_x_ok_lo_hi, priv_x_ok_lo_lo)
node priv_x_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_x_ok_hi_lo = cat(priv_x_ok_hi_lo_hi, entries_barrier_6.io.y.u)
node priv_x_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_x_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_x_ok_hi_hi = cat(priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo)
node priv_x_ok_hi = cat(priv_x_ok_hi_hi, priv_x_ok_hi_lo)
node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo)
node _priv_x_ok_T_1 = not(_priv_x_ok_T)
node priv_x_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_x_ok_lo_lo_1 = cat(priv_x_ok_lo_lo_hi_1, entries_barrier.io.y.u)
node priv_x_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_x_ok_lo_hi_1 = cat(priv_x_ok_lo_hi_hi_1, entries_barrier_3.io.y.u)
node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1)
node priv_x_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_x_ok_hi_lo_1 = cat(priv_x_ok_hi_lo_hi_1, entries_barrier_6.io.y.u)
node priv_x_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_x_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_x_ok_hi_hi_1 = cat(priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1)
node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1)
node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1)
node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2)
node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<13>(0h1fff), UInt<13>(0h0))
node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0))
node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<13>(0h1fff), UInt<13>(0h0))
node stage1_bypass_lo_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2)
node stage1_bypass_lo_lo = cat(stage1_bypass_lo_lo_hi, entries_barrier.io.y.ae_stage2)
node stage1_bypass_lo_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2)
node stage1_bypass_lo_hi = cat(stage1_bypass_lo_hi_hi, entries_barrier_3.io.y.ae_stage2)
node stage1_bypass_lo = cat(stage1_bypass_lo_hi, stage1_bypass_lo_lo)
node stage1_bypass_hi_lo_hi = cat(entries_barrier_8.io.y.ae_stage2, entries_barrier_7.io.y.ae_stage2)
node stage1_bypass_hi_lo = cat(stage1_bypass_hi_lo_hi, entries_barrier_6.io.y.ae_stage2)
node stage1_bypass_hi_hi_lo = cat(entries_barrier_10.io.y.ae_stage2, entries_barrier_9.io.y.ae_stage2)
node stage1_bypass_hi_hi_hi = cat(entries_barrier_12.io.y.ae_stage2, entries_barrier_11.io.y.ae_stage2)
node stage1_bypass_hi_hi = cat(stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo)
node stage1_bypass_hi = cat(stage1_bypass_hi_hi, stage1_bypass_hi_lo)
node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo)
node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3)
node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4)
node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0))
node mxr = or(io.ptw.status.mxr, _mxr_T)
node r_array_lo_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr)
node r_array_lo_lo = cat(r_array_lo_lo_hi, entries_barrier.io.y.sr)
node r_array_lo_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr)
node r_array_lo_hi = cat(r_array_lo_hi_hi, entries_barrier_3.io.y.sr)
node r_array_lo = cat(r_array_lo_hi, r_array_lo_lo)
node r_array_hi_lo_hi = cat(entries_barrier_8.io.y.sr, entries_barrier_7.io.y.sr)
node r_array_hi_lo = cat(r_array_hi_lo_hi, entries_barrier_6.io.y.sr)
node r_array_hi_hi_lo = cat(entries_barrier_10.io.y.sr, entries_barrier_9.io.y.sr)
node r_array_hi_hi_hi = cat(entries_barrier_12.io.y.sr, entries_barrier_11.io.y.sr)
node r_array_hi_hi = cat(r_array_hi_hi_hi, r_array_hi_hi_lo)
node r_array_hi = cat(r_array_hi_hi, r_array_hi_lo)
node _r_array_T = cat(r_array_hi, r_array_lo)
node r_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx)
node r_array_lo_lo_1 = cat(r_array_lo_lo_hi_1, entries_barrier.io.y.sx)
node r_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx)
node r_array_lo_hi_1 = cat(r_array_lo_hi_hi_1, entries_barrier_3.io.y.sx)
node r_array_lo_1 = cat(r_array_lo_hi_1, r_array_lo_lo_1)
node r_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx)
node r_array_hi_lo_1 = cat(r_array_hi_lo_hi_1, entries_barrier_6.io.y.sx)
node r_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx)
node r_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx)
node r_array_hi_hi_1 = cat(r_array_hi_hi_hi_1, r_array_hi_hi_lo_1)
node r_array_hi_1 = cat(r_array_hi_hi_1, r_array_hi_lo_1)
node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1)
node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0))
node _r_array_T_3 = or(_r_array_T, _r_array_T_2)
node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3)
node _r_array_T_5 = or(_r_array_T_4, stage1_bypass)
node r_array = cat(UInt<1>(0h1), _r_array_T_5)
node w_array_lo_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw)
node w_array_lo_lo = cat(w_array_lo_lo_hi, entries_barrier.io.y.sw)
node w_array_lo_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw)
node w_array_lo_hi = cat(w_array_lo_hi_hi, entries_barrier_3.io.y.sw)
node w_array_lo = cat(w_array_lo_hi, w_array_lo_lo)
node w_array_hi_lo_hi = cat(entries_barrier_8.io.y.sw, entries_barrier_7.io.y.sw)
node w_array_hi_lo = cat(w_array_hi_lo_hi, entries_barrier_6.io.y.sw)
node w_array_hi_hi_lo = cat(entries_barrier_10.io.y.sw, entries_barrier_9.io.y.sw)
node w_array_hi_hi_hi = cat(entries_barrier_12.io.y.sw, entries_barrier_11.io.y.sw)
node w_array_hi_hi = cat(w_array_hi_hi_hi, w_array_hi_hi_lo)
node w_array_hi = cat(w_array_hi_hi, w_array_hi_lo)
node _w_array_T = cat(w_array_hi, w_array_lo)
node _w_array_T_1 = and(priv_rw_ok, _w_array_T)
node _w_array_T_2 = or(_w_array_T_1, stage1_bypass)
node w_array = cat(UInt<1>(0h1), _w_array_T_2)
node x_array_lo_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx)
node x_array_lo_lo = cat(x_array_lo_lo_hi, entries_barrier.io.y.sx)
node x_array_lo_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx)
node x_array_lo_hi = cat(x_array_lo_hi_hi, entries_barrier_3.io.y.sx)
node x_array_lo = cat(x_array_lo_hi, x_array_lo_lo)
node x_array_hi_lo_hi = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx)
node x_array_hi_lo = cat(x_array_hi_lo_hi, entries_barrier_6.io.y.sx)
node x_array_hi_hi_lo = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx)
node x_array_hi_hi_hi = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx)
node x_array_hi_hi = cat(x_array_hi_hi_hi, x_array_hi_hi_lo)
node x_array_hi = cat(x_array_hi_hi, x_array_hi_lo)
node _x_array_T = cat(x_array_hi, x_array_lo)
node _x_array_T_1 = and(priv_x_ok, _x_array_T)
node _x_array_T_2 = or(_x_array_T_1, stage1_bypass)
node x_array = cat(UInt<1>(0h1), _x_array_T_2)
node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0))
node stage2_bypass = mux(_stage2_bypass_T, UInt<13>(0h1fff), UInt<13>(0h0))
node hr_array_lo_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr)
node hr_array_lo_lo = cat(hr_array_lo_lo_hi, entries_barrier.io.y.hr)
node hr_array_lo_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr)
node hr_array_lo_hi = cat(hr_array_lo_hi_hi, entries_barrier_3.io.y.hr)
node hr_array_lo = cat(hr_array_lo_hi, hr_array_lo_lo)
node hr_array_hi_lo_hi = cat(entries_barrier_8.io.y.hr, entries_barrier_7.io.y.hr)
node hr_array_hi_lo = cat(hr_array_hi_lo_hi, entries_barrier_6.io.y.hr)
node hr_array_hi_hi_lo = cat(entries_barrier_10.io.y.hr, entries_barrier_9.io.y.hr)
node hr_array_hi_hi_hi = cat(entries_barrier_12.io.y.hr, entries_barrier_11.io.y.hr)
node hr_array_hi_hi = cat(hr_array_hi_hi_hi, hr_array_hi_hi_lo)
node hr_array_hi = cat(hr_array_hi_hi, hr_array_hi_lo)
node _hr_array_T = cat(hr_array_hi, hr_array_lo)
node hr_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx)
node hr_array_lo_lo_1 = cat(hr_array_lo_lo_hi_1, entries_barrier.io.y.hx)
node hr_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx)
node hr_array_lo_hi_1 = cat(hr_array_lo_hi_hi_1, entries_barrier_3.io.y.hx)
node hr_array_lo_1 = cat(hr_array_lo_hi_1, hr_array_lo_lo_1)
node hr_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx)
node hr_array_hi_lo_1 = cat(hr_array_hi_lo_hi_1, entries_barrier_6.io.y.hx)
node hr_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx)
node hr_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx)
node hr_array_hi_hi_1 = cat(hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1)
node hr_array_hi_1 = cat(hr_array_hi_hi_1, hr_array_hi_lo_1)
node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1)
node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0))
node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2)
node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass)
node hr_array = cat(UInt<1>(0h1), _hr_array_T_4)
node hw_array_lo_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw)
node hw_array_lo_lo = cat(hw_array_lo_lo_hi, entries_barrier.io.y.hw)
node hw_array_lo_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw)
node hw_array_lo_hi = cat(hw_array_lo_hi_hi, entries_barrier_3.io.y.hw)
node hw_array_lo = cat(hw_array_lo_hi, hw_array_lo_lo)
node hw_array_hi_lo_hi = cat(entries_barrier_8.io.y.hw, entries_barrier_7.io.y.hw)
node hw_array_hi_lo = cat(hw_array_hi_lo_hi, entries_barrier_6.io.y.hw)
node hw_array_hi_hi_lo = cat(entries_barrier_10.io.y.hw, entries_barrier_9.io.y.hw)
node hw_array_hi_hi_hi = cat(entries_barrier_12.io.y.hw, entries_barrier_11.io.y.hw)
node hw_array_hi_hi = cat(hw_array_hi_hi_hi, hw_array_hi_hi_lo)
node hw_array_hi = cat(hw_array_hi_hi, hw_array_hi_lo)
node _hw_array_T = cat(hw_array_hi, hw_array_lo)
node _hw_array_T_1 = or(_hw_array_T, stage2_bypass)
node hw_array = cat(UInt<1>(0h1), _hw_array_T_1)
node hx_array_lo_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx)
node hx_array_lo_lo = cat(hx_array_lo_lo_hi, entries_barrier.io.y.hx)
node hx_array_lo_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx)
node hx_array_lo_hi = cat(hx_array_lo_hi_hi, entries_barrier_3.io.y.hx)
node hx_array_lo = cat(hx_array_lo_hi, hx_array_lo_lo)
node hx_array_hi_lo_hi = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx)
node hx_array_hi_lo = cat(hx_array_hi_lo_hi, entries_barrier_6.io.y.hx)
node hx_array_hi_hi_lo = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx)
node hx_array_hi_hi_hi = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx)
node hx_array_hi_hi = cat(hx_array_hi_hi_hi, hx_array_hi_hi_lo)
node hx_array_hi = cat(hx_array_hi_hi, hx_array_hi_lo)
node _hx_array_T = cat(hx_array_hi, hx_array_lo)
node _hx_array_T_1 = or(_hx_array_T, stage2_bypass)
node hx_array = cat(UInt<1>(0h1), _hx_array_T_1)
node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0))
node pr_array_lo_lo_hi = cat(entries_barrier_2.io.y.pr, entries_barrier_1.io.y.pr)
node pr_array_lo_lo = cat(pr_array_lo_lo_hi, entries_barrier.io.y.pr)
node pr_array_lo_hi_hi = cat(entries_barrier_5.io.y.pr, entries_barrier_4.io.y.pr)
node pr_array_lo_hi = cat(pr_array_lo_hi_hi, entries_barrier_3.io.y.pr)
node pr_array_lo = cat(pr_array_lo_hi, pr_array_lo_lo)
node pr_array_hi_lo_hi = cat(entries_barrier_8.io.y.pr, entries_barrier_7.io.y.pr)
node pr_array_hi_lo = cat(pr_array_hi_lo_hi, entries_barrier_6.io.y.pr)
node pr_array_hi_hi_hi = cat(entries_barrier_11.io.y.pr, entries_barrier_10.io.y.pr)
node pr_array_hi_hi = cat(pr_array_hi_hi_hi, entries_barrier_9.io.y.pr)
node pr_array_hi = cat(pr_array_hi_hi, pr_array_hi_lo)
node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo)
node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1)
node _pr_array_T_3 = or(ptw_ae_array, final_ae_array)
node _pr_array_T_4 = not(_pr_array_T_3)
node pr_array = and(_pr_array_T_2, _pr_array_T_4)
node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0))
node pw_array_lo_lo_hi = cat(entries_barrier_2.io.y.pw, entries_barrier_1.io.y.pw)
node pw_array_lo_lo = cat(pw_array_lo_lo_hi, entries_barrier.io.y.pw)
node pw_array_lo_hi_hi = cat(entries_barrier_5.io.y.pw, entries_barrier_4.io.y.pw)
node pw_array_lo_hi = cat(pw_array_lo_hi_hi, entries_barrier_3.io.y.pw)
node pw_array_lo = cat(pw_array_lo_hi, pw_array_lo_lo)
node pw_array_hi_lo_hi = cat(entries_barrier_8.io.y.pw, entries_barrier_7.io.y.pw)
node pw_array_hi_lo = cat(pw_array_hi_lo_hi, entries_barrier_6.io.y.pw)
node pw_array_hi_hi_hi = cat(entries_barrier_11.io.y.pw, entries_barrier_10.io.y.pw)
node pw_array_hi_hi = cat(pw_array_hi_hi_hi, entries_barrier_9.io.y.pw)
node pw_array_hi = cat(pw_array_hi_hi, pw_array_hi_lo)
node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo)
node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1)
node _pw_array_T_3 = or(ptw_ae_array, final_ae_array)
node _pw_array_T_4 = not(_pw_array_T_3)
node pw_array = and(_pw_array_T_2, _pw_array_T_4)
node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0))
node px_array_lo_lo_hi = cat(entries_barrier_2.io.y.px, entries_barrier_1.io.y.px)
node px_array_lo_lo = cat(px_array_lo_lo_hi, entries_barrier.io.y.px)
node px_array_lo_hi_hi = cat(entries_barrier_5.io.y.px, entries_barrier_4.io.y.px)
node px_array_lo_hi = cat(px_array_lo_hi_hi, entries_barrier_3.io.y.px)
node px_array_lo = cat(px_array_lo_hi, px_array_lo_lo)
node px_array_hi_lo_hi = cat(entries_barrier_8.io.y.px, entries_barrier_7.io.y.px)
node px_array_hi_lo = cat(px_array_hi_lo_hi, entries_barrier_6.io.y.px)
node px_array_hi_hi_hi = cat(entries_barrier_11.io.y.px, entries_barrier_10.io.y.px)
node px_array_hi_hi = cat(px_array_hi_hi_hi, entries_barrier_9.io.y.px)
node px_array_hi = cat(px_array_hi_hi, px_array_hi_lo)
node _px_array_T_1 = cat(px_array_hi, px_array_lo)
node _px_array_T_2 = cat(_px_array_T, _px_array_T_1)
node _px_array_T_3 = or(ptw_ae_array, final_ae_array)
node _px_array_T_4 = not(_px_array_T_3)
node px_array = and(_px_array_T_2, _px_array_T_4)
node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0))
node eff_array_lo_lo_hi = cat(entries_barrier_2.io.y.eff, entries_barrier_1.io.y.eff)
node eff_array_lo_lo = cat(eff_array_lo_lo_hi, entries_barrier.io.y.eff)
node eff_array_lo_hi_hi = cat(entries_barrier_5.io.y.eff, entries_barrier_4.io.y.eff)
node eff_array_lo_hi = cat(eff_array_lo_hi_hi, entries_barrier_3.io.y.eff)
node eff_array_lo = cat(eff_array_lo_hi, eff_array_lo_lo)
node eff_array_hi_lo_hi = cat(entries_barrier_8.io.y.eff, entries_barrier_7.io.y.eff)
node eff_array_hi_lo = cat(eff_array_hi_lo_hi, entries_barrier_6.io.y.eff)
node eff_array_hi_hi_hi = cat(entries_barrier_11.io.y.eff, entries_barrier_10.io.y.eff)
node eff_array_hi_hi = cat(eff_array_hi_hi_hi, entries_barrier_9.io.y.eff)
node eff_array_hi = cat(eff_array_hi_hi, eff_array_hi_lo)
node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo)
node eff_array = cat(_eff_array_T, _eff_array_T_1)
node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0))
node c_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c)
node c_array_lo_lo = cat(c_array_lo_lo_hi, entries_barrier.io.y.c)
node c_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c)
node c_array_lo_hi = cat(c_array_lo_hi_hi, entries_barrier_3.io.y.c)
node c_array_lo = cat(c_array_lo_hi, c_array_lo_lo)
node c_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c)
node c_array_hi_lo = cat(c_array_hi_lo_hi, entries_barrier_6.io.y.c)
node c_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c)
node c_array_hi_hi = cat(c_array_hi_hi_hi, entries_barrier_9.io.y.c)
node c_array_hi = cat(c_array_hi_hi, c_array_hi_lo)
node _c_array_T_1 = cat(c_array_hi, c_array_lo)
node c_array = cat(_c_array_T, _c_array_T_1)
node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0))
node ppp_array_lo_lo_hi = cat(entries_barrier_2.io.y.ppp, entries_barrier_1.io.y.ppp)
node ppp_array_lo_lo = cat(ppp_array_lo_lo_hi, entries_barrier.io.y.ppp)
node ppp_array_lo_hi_hi = cat(entries_barrier_5.io.y.ppp, entries_barrier_4.io.y.ppp)
node ppp_array_lo_hi = cat(ppp_array_lo_hi_hi, entries_barrier_3.io.y.ppp)
node ppp_array_lo = cat(ppp_array_lo_hi, ppp_array_lo_lo)
node ppp_array_hi_lo_hi = cat(entries_barrier_8.io.y.ppp, entries_barrier_7.io.y.ppp)
node ppp_array_hi_lo = cat(ppp_array_hi_lo_hi, entries_barrier_6.io.y.ppp)
node ppp_array_hi_hi_hi = cat(entries_barrier_11.io.y.ppp, entries_barrier_10.io.y.ppp)
node ppp_array_hi_hi = cat(ppp_array_hi_hi_hi, entries_barrier_9.io.y.ppp)
node ppp_array_hi = cat(ppp_array_hi_hi, ppp_array_hi_lo)
node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo)
node ppp_array = cat(_ppp_array_T, _ppp_array_T_1)
node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0))
node paa_array_lo_lo_hi = cat(entries_barrier_2.io.y.paa, entries_barrier_1.io.y.paa)
node paa_array_lo_lo = cat(paa_array_lo_lo_hi, entries_barrier.io.y.paa)
node paa_array_lo_hi_hi = cat(entries_barrier_5.io.y.paa, entries_barrier_4.io.y.paa)
node paa_array_lo_hi = cat(paa_array_lo_hi_hi, entries_barrier_3.io.y.paa)
node paa_array_lo = cat(paa_array_lo_hi, paa_array_lo_lo)
node paa_array_hi_lo_hi = cat(entries_barrier_8.io.y.paa, entries_barrier_7.io.y.paa)
node paa_array_hi_lo = cat(paa_array_hi_lo_hi, entries_barrier_6.io.y.paa)
node paa_array_hi_hi_hi = cat(entries_barrier_11.io.y.paa, entries_barrier_10.io.y.paa)
node paa_array_hi_hi = cat(paa_array_hi_hi_hi, entries_barrier_9.io.y.paa)
node paa_array_hi = cat(paa_array_hi_hi, paa_array_hi_lo)
node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo)
node paa_array = cat(_paa_array_T, _paa_array_T_1)
node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0))
node pal_array_lo_lo_hi = cat(entries_barrier_2.io.y.pal, entries_barrier_1.io.y.pal)
node pal_array_lo_lo = cat(pal_array_lo_lo_hi, entries_barrier.io.y.pal)
node pal_array_lo_hi_hi = cat(entries_barrier_5.io.y.pal, entries_barrier_4.io.y.pal)
node pal_array_lo_hi = cat(pal_array_lo_hi_hi, entries_barrier_3.io.y.pal)
node pal_array_lo = cat(pal_array_lo_hi, pal_array_lo_lo)
node pal_array_hi_lo_hi = cat(entries_barrier_8.io.y.pal, entries_barrier_7.io.y.pal)
node pal_array_hi_lo = cat(pal_array_hi_lo_hi, entries_barrier_6.io.y.pal)
node pal_array_hi_hi_hi = cat(entries_barrier_11.io.y.pal, entries_barrier_10.io.y.pal)
node pal_array_hi_hi = cat(pal_array_hi_hi_hi, entries_barrier_9.io.y.pal)
node pal_array_hi = cat(pal_array_hi_hi, pal_array_hi_lo)
node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo)
node pal_array = cat(_pal_array_T, _pal_array_T_1)
node ppp_array_if_cached = or(ppp_array, c_array)
node paa_array_if_cached = or(paa_array, c_array)
node pal_array_if_cached = or(pal_array, c_array)
node _prefetchable_array_T = and(cacheable, homogeneous)
node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1)
node prefetchable_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c)
node prefetchable_array_lo_lo = cat(prefetchable_array_lo_lo_hi, entries_barrier.io.y.c)
node prefetchable_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c)
node prefetchable_array_lo_hi = cat(prefetchable_array_lo_hi_hi, entries_barrier_3.io.y.c)
node prefetchable_array_lo = cat(prefetchable_array_lo_hi, prefetchable_array_lo_lo)
node prefetchable_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c)
node prefetchable_array_hi_lo = cat(prefetchable_array_hi_lo_hi, entries_barrier_6.io.y.c)
node prefetchable_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c)
node prefetchable_array_hi_hi = cat(prefetchable_array_hi_hi_hi, entries_barrier_9.io.y.c)
node prefetchable_array_hi = cat(prefetchable_array_hi_hi, prefetchable_array_hi_lo)
node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo)
node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2)
node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size)
node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1))
node _misaligned_T_2 = tail(_misaligned_T_1, 1)
node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2)
node misaligned = orr(_misaligned_T_3)
node _bad_va_T = and(vm_enabled, stage1_en)
node bad_va_maskedVAddr = and(io.req.bits.vaddr, UInt<40>(0hc000000000))
node _bad_va_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<1>(0h0))
node _bad_va_T_3 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000))
node _bad_va_T_4 = and(UInt<1>(0h1), _bad_va_T_3)
node _bad_va_T_5 = or(_bad_va_T_2, _bad_va_T_4)
node _bad_va_T_6 = eq(_bad_va_T_5, UInt<1>(0h0))
node _bad_va_T_7 = and(_bad_va_T_1, _bad_va_T_6)
node bad_va = and(_bad_va_T, _bad_va_T_7)
node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6))
node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7))
node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1)
node cmd_lrsc = and(UInt<1>(0h1), _cmd_lrsc_T_2)
node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4))
node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9))
node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha))
node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb))
node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1)
node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2)
node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3)
node cmd_amo_logical = and(UInt<1>(0h1), _cmd_amo_logical_T_6)
node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8))
node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc))
node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd))
node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he))
node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf))
node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1)
node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2)
node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3)
node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4)
node cmd_amo_arithmetic = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8)
node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11))
node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0))
node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10))
node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6))
node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7))
node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1)
node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2)
node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3)
node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4))
node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9))
node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha))
node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb))
node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8)
node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9)
node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10)
node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8))
node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc))
node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd))
node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he))
node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf))
node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15)
node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16)
node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17)
node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18)
node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22)
node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23)
node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10))
node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T)
node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1))
node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11))
node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1)
node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7))
node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3)
node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4))
node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9))
node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha))
node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb))
node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6)
node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7)
node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8)
node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8))
node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc))
node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd))
node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he))
node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf))
node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13)
node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14)
node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15)
node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16)
node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20)
node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21)
node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5))
node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17))
node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1)
node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2)
node lrscAllowed = mux(UInt<1>(0h0), UInt<1>(0h0), c_array)
node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0))
node _ae_array_T_1 = not(lrscAllowed)
node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0))
node ae_array = or(_ae_array_T, _ae_array_T_2)
node _ae_ld_array_T = not(pr_array)
node _ae_ld_array_T_1 = or(ae_array, _ae_ld_array_T)
node ae_ld_array = mux(cmd_read, _ae_ld_array_T_1, UInt<1>(0h0))
node _ae_st_array_T = not(pw_array)
node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T)
node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0))
node _ae_st_array_T_3 = not(ppp_array_if_cached)
node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0))
node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4)
node _ae_st_array_T_6 = not(pal_array_if_cached)
node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0))
node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7)
node _ae_st_array_T_9 = not(paa_array_if_cached)
node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0))
node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10)
node _must_alloc_array_T = not(ppp_array)
node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0))
node _must_alloc_array_T_2 = not(pal_array)
node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0))
node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3)
node _must_alloc_array_T_5 = not(paa_array)
node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0))
node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6)
node _must_alloc_array_T_8 = not(UInt<14>(0h0))
node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0))
node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9)
node _pf_ld_array_T = mux(cmd_readx, x_array, r_array)
node _pf_ld_array_T_1 = not(_pf_ld_array_T)
node _pf_ld_array_T_2 = not(ptw_ae_array)
node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2)
node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array)
node _pf_ld_array_T_5 = not(ptw_gf_array)
node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5)
node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0))
node _pf_st_array_T = not(w_array)
node _pf_st_array_T_1 = not(ptw_ae_array)
node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1)
node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array)
node _pf_st_array_T_4 = not(ptw_gf_array)
node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4)
node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0))
node _pf_inst_array_T = not(x_array)
node _pf_inst_array_T_1 = not(ptw_ae_array)
node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1)
node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array)
node _pf_inst_array_T_4 = not(ptw_gf_array)
node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4)
node _gf_ld_array_T = and(priv_v, cmd_read)
node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array)
node _gf_ld_array_T_2 = not(_gf_ld_array_T_1)
node _gf_ld_array_T_3 = or(_gf_ld_array_T_2, ptw_gf_array)
node _gf_ld_array_T_4 = not(ptw_ae_array)
node _gf_ld_array_T_5 = and(_gf_ld_array_T_3, _gf_ld_array_T_4)
node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0))
node _gf_st_array_T = and(priv_v, cmd_write_perms)
node _gf_st_array_T_1 = not(hw_array)
node _gf_st_array_T_2 = or(_gf_st_array_T_1, ptw_gf_array)
node _gf_st_array_T_3 = not(ptw_ae_array)
node _gf_st_array_T_4 = and(_gf_st_array_T_2, _gf_st_array_T_3)
node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0))
node _gf_inst_array_T = not(hx_array)
node _gf_inst_array_T_1 = or(_gf_inst_array_T, ptw_gf_array)
node _gf_inst_array_T_2 = not(ptw_ae_array)
node _gf_inst_array_T_3 = and(_gf_inst_array_T_1, _gf_inst_array_T_2)
node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0))
node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn)
node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T)
node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<12>(0hfff), UInt<12>(0h0))
node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0))
node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<13>(0h1fff), UInt<13>(0h0))
node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4)
node _gpa_hits_T = bits(gf_inst_array, 12, 0)
node _gpa_hits_T_1 = not(_gpa_hits_T)
node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1)
node tlb_hit_if_not_gpa_miss = orr(real_hits)
node _tlb_hit_T = and(real_hits, gpa_hits)
node tlb_hit = orr(_tlb_hit_T)
node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0))
node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T)
node _tlb_miss_T_2 = eq(bad_va, UInt<1>(0h0))
node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2)
node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0))
node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4)
regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0)
wire _state_vec_WIRE : UInt<7>[1]
connect _state_vec_WIRE[0], UInt<7>(0h0)
regreset state_vec : UInt<7>[1], clock, reset, _state_vec_WIRE
regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _T_23 = and(io.req.valid, vm_enabled)
when _T_23 :
node _T_24 = or(sector_hits_0, sector_hits_1)
node _T_25 = or(_T_24, sector_hits_2)
node _T_26 = or(_T_25, sector_hits_3)
node _T_27 = or(_T_26, sector_hits_4)
node _T_28 = or(_T_27, sector_hits_5)
node _T_29 = or(_T_28, sector_hits_6)
node _T_30 = or(_T_29, sector_hits_7)
when _T_30 :
node lo_lo = cat(sector_hits_1, sector_hits_0)
node lo_hi = cat(sector_hits_3, sector_hits_2)
node lo = cat(lo_hi, lo_lo)
node hi_lo = cat(sector_hits_5, sector_hits_4)
node hi_hi = cat(sector_hits_7, sector_hits_6)
node hi = cat(hi_hi, hi_lo)
node _T_31 = cat(hi, lo)
node hi_1 = bits(_T_31, 7, 4)
node lo_1 = bits(_T_31, 3, 0)
node _T_32 = orr(hi_1)
node _T_33 = or(hi_1, lo_1)
node hi_2 = bits(_T_33, 3, 2)
node lo_2 = bits(_T_33, 1, 0)
node _T_34 = orr(hi_2)
node _T_35 = or(hi_2, lo_2)
node _T_36 = bits(_T_35, 1, 1)
node _T_37 = cat(_T_34, _T_36)
node _T_38 = cat(_T_32, _T_37)
node state_vec_0_touch_way_sized = bits(_T_38, 2, 0)
node _state_vec_0_set_left_older_T = bits(state_vec_0_touch_way_sized, 2, 2)
node state_vec_0_set_left_older = eq(_state_vec_0_set_left_older_T, UInt<1>(0h0))
node state_vec_0_left_subtree_state = bits(state_vec[0], 5, 3)
node state_vec_0_right_subtree_state = bits(state_vec[0], 2, 0)
node _state_vec_0_T = bits(state_vec_0_touch_way_sized, 1, 0)
node _state_vec_0_set_left_older_T_1 = bits(_state_vec_0_T, 1, 1)
node state_vec_0_set_left_older_1 = eq(_state_vec_0_set_left_older_T_1, UInt<1>(0h0))
node state_vec_0_left_subtree_state_1 = bits(state_vec_0_left_subtree_state, 1, 1)
node state_vec_0_right_subtree_state_1 = bits(state_vec_0_left_subtree_state, 0, 0)
node _state_vec_0_T_1 = bits(_state_vec_0_T, 0, 0)
node _state_vec_0_T_2 = bits(_state_vec_0_T_1, 0, 0)
node _state_vec_0_T_3 = eq(_state_vec_0_T_2, UInt<1>(0h0))
node _state_vec_0_T_4 = mux(state_vec_0_set_left_older_1, state_vec_0_left_subtree_state_1, _state_vec_0_T_3)
node _state_vec_0_T_5 = bits(_state_vec_0_T, 0, 0)
node _state_vec_0_T_6 = bits(_state_vec_0_T_5, 0, 0)
node _state_vec_0_T_7 = eq(_state_vec_0_T_6, UInt<1>(0h0))
node _state_vec_0_T_8 = mux(state_vec_0_set_left_older_1, _state_vec_0_T_7, state_vec_0_right_subtree_state_1)
node state_vec_0_hi = cat(state_vec_0_set_left_older_1, _state_vec_0_T_4)
node _state_vec_0_T_9 = cat(state_vec_0_hi, _state_vec_0_T_8)
node _state_vec_0_T_10 = mux(state_vec_0_set_left_older, state_vec_0_left_subtree_state, _state_vec_0_T_9)
node _state_vec_0_T_11 = bits(state_vec_0_touch_way_sized, 1, 0)
node _state_vec_0_set_left_older_T_2 = bits(_state_vec_0_T_11, 1, 1)
node state_vec_0_set_left_older_2 = eq(_state_vec_0_set_left_older_T_2, UInt<1>(0h0))
node state_vec_0_left_subtree_state_2 = bits(state_vec_0_right_subtree_state, 1, 1)
node state_vec_0_right_subtree_state_2 = bits(state_vec_0_right_subtree_state, 0, 0)
node _state_vec_0_T_12 = bits(_state_vec_0_T_11, 0, 0)
node _state_vec_0_T_13 = bits(_state_vec_0_T_12, 0, 0)
node _state_vec_0_T_14 = eq(_state_vec_0_T_13, UInt<1>(0h0))
node _state_vec_0_T_15 = mux(state_vec_0_set_left_older_2, state_vec_0_left_subtree_state_2, _state_vec_0_T_14)
node _state_vec_0_T_16 = bits(_state_vec_0_T_11, 0, 0)
node _state_vec_0_T_17 = bits(_state_vec_0_T_16, 0, 0)
node _state_vec_0_T_18 = eq(_state_vec_0_T_17, UInt<1>(0h0))
node _state_vec_0_T_19 = mux(state_vec_0_set_left_older_2, _state_vec_0_T_18, state_vec_0_right_subtree_state_2)
node state_vec_0_hi_1 = cat(state_vec_0_set_left_older_2, _state_vec_0_T_15)
node _state_vec_0_T_20 = cat(state_vec_0_hi_1, _state_vec_0_T_19)
node _state_vec_0_T_21 = mux(state_vec_0_set_left_older, _state_vec_0_T_20, state_vec_0_right_subtree_state)
node state_vec_0_hi_2 = cat(state_vec_0_set_left_older, _state_vec_0_T_10)
node _state_vec_0_T_22 = cat(state_vec_0_hi_2, _state_vec_0_T_21)
connect state_vec[0], _state_vec_0_T_22
node _T_39 = or(superpage_hits_0, superpage_hits_1)
node _T_40 = or(_T_39, superpage_hits_2)
node _T_41 = or(_T_40, superpage_hits_3)
when _T_41 :
node lo_3 = cat(superpage_hits_1, superpage_hits_0)
node hi_3 = cat(superpage_hits_3, superpage_hits_2)
node _T_42 = cat(hi_3, lo_3)
node hi_4 = bits(_T_42, 3, 2)
node lo_4 = bits(_T_42, 1, 0)
node _T_43 = orr(hi_4)
node _T_44 = or(hi_4, lo_4)
node _T_45 = bits(_T_44, 1, 1)
node _T_46 = cat(_T_43, _T_45)
node state_reg_touch_way_sized = bits(_T_46, 1, 0)
node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 1, 1)
node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0))
node state_reg_left_subtree_state = bits(state_reg_1, 1, 1)
node state_reg_right_subtree_state = bits(state_reg_1, 0, 0)
node _state_reg_T = bits(state_reg_touch_way_sized, 0, 0)
node _state_reg_T_1 = bits(_state_reg_T, 0, 0)
node _state_reg_T_2 = eq(_state_reg_T_1, UInt<1>(0h0))
node _state_reg_T_3 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_2)
node _state_reg_T_4 = bits(state_reg_touch_way_sized, 0, 0)
node _state_reg_T_5 = bits(_state_reg_T_4, 0, 0)
node _state_reg_T_6 = eq(_state_reg_T_5, UInt<1>(0h0))
node _state_reg_T_7 = mux(state_reg_set_left_older, _state_reg_T_6, state_reg_right_subtree_state)
node state_reg_hi = cat(state_reg_set_left_older, _state_reg_T_3)
node _state_reg_T_8 = cat(state_reg_hi, _state_reg_T_7)
connect state_reg_1, _state_reg_T_8
node _multipleHits_T = bits(real_hits, 5, 0)
node _multipleHits_T_1 = bits(_multipleHits_T, 2, 0)
node _multipleHits_T_2 = bits(_multipleHits_T_1, 0, 0)
node multipleHits_leftOne = bits(_multipleHits_T_2, 0, 0)
node _multipleHits_T_3 = bits(_multipleHits_T_1, 2, 1)
node _multipleHits_T_4 = bits(_multipleHits_T_3, 0, 0)
node multipleHits_leftOne_1 = bits(_multipleHits_T_4, 0, 0)
node _multipleHits_T_5 = bits(_multipleHits_T_3, 1, 1)
node multipleHits_rightOne = bits(_multipleHits_T_5, 0, 0)
node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne)
node _multipleHits_T_6 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_7 = and(multipleHits_leftOne_1, multipleHits_rightOne)
node multipleHits_rightTwo = or(_multipleHits_T_6, _multipleHits_T_7)
node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1)
node _multipleHits_T_8 = or(UInt<1>(0h0), multipleHits_rightTwo)
node _multipleHits_T_9 = and(multipleHits_leftOne, multipleHits_rightOne_1)
node multipleHits_leftTwo = or(_multipleHits_T_8, _multipleHits_T_9)
node _multipleHits_T_10 = bits(_multipleHits_T, 5, 3)
node _multipleHits_T_11 = bits(_multipleHits_T_10, 0, 0)
node multipleHits_leftOne_3 = bits(_multipleHits_T_11, 0, 0)
node _multipleHits_T_12 = bits(_multipleHits_T_10, 2, 1)
node _multipleHits_T_13 = bits(_multipleHits_T_12, 0, 0)
node multipleHits_leftOne_4 = bits(_multipleHits_T_13, 0, 0)
node _multipleHits_T_14 = bits(_multipleHits_T_12, 1, 1)
node multipleHits_rightOne_2 = bits(_multipleHits_T_14, 0, 0)
node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2)
node _multipleHits_T_15 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_16 = and(multipleHits_leftOne_4, multipleHits_rightOne_2)
node multipleHits_rightTwo_1 = or(_multipleHits_T_15, _multipleHits_T_16)
node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3)
node _multipleHits_T_17 = or(UInt<1>(0h0), multipleHits_rightTwo_1)
node _multipleHits_T_18 = and(multipleHits_leftOne_3, multipleHits_rightOne_3)
node multipleHits_rightTwo_2 = or(_multipleHits_T_17, _multipleHits_T_18)
node multipleHits_leftOne_5 = or(multipleHits_leftOne_2, multipleHits_rightOne_4)
node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2)
node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4)
node multipleHits_leftTwo_1 = or(_multipleHits_T_19, _multipleHits_T_20)
node _multipleHits_T_21 = bits(real_hits, 12, 6)
node _multipleHits_T_22 = bits(_multipleHits_T_21, 2, 0)
node _multipleHits_T_23 = bits(_multipleHits_T_22, 0, 0)
node multipleHits_leftOne_6 = bits(_multipleHits_T_23, 0, 0)
node _multipleHits_T_24 = bits(_multipleHits_T_22, 2, 1)
node _multipleHits_T_25 = bits(_multipleHits_T_24, 0, 0)
node multipleHits_leftOne_7 = bits(_multipleHits_T_25, 0, 0)
node _multipleHits_T_26 = bits(_multipleHits_T_24, 1, 1)
node multipleHits_rightOne_5 = bits(_multipleHits_T_26, 0, 0)
node multipleHits_rightOne_6 = or(multipleHits_leftOne_7, multipleHits_rightOne_5)
node _multipleHits_T_27 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_28 = and(multipleHits_leftOne_7, multipleHits_rightOne_5)
node multipleHits_rightTwo_3 = or(_multipleHits_T_27, _multipleHits_T_28)
node multipleHits_leftOne_8 = or(multipleHits_leftOne_6, multipleHits_rightOne_6)
node _multipleHits_T_29 = or(UInt<1>(0h0), multipleHits_rightTwo_3)
node _multipleHits_T_30 = and(multipleHits_leftOne_6, multipleHits_rightOne_6)
node multipleHits_leftTwo_2 = or(_multipleHits_T_29, _multipleHits_T_30)
node _multipleHits_T_31 = bits(_multipleHits_T_21, 6, 3)
node _multipleHits_T_32 = bits(_multipleHits_T_31, 1, 0)
node _multipleHits_T_33 = bits(_multipleHits_T_32, 0, 0)
node multipleHits_leftOne_9 = bits(_multipleHits_T_33, 0, 0)
node _multipleHits_T_34 = bits(_multipleHits_T_32, 1, 1)
node multipleHits_rightOne_7 = bits(_multipleHits_T_34, 0, 0)
node multipleHits_leftOne_10 = or(multipleHits_leftOne_9, multipleHits_rightOne_7)
node _multipleHits_T_35 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_36 = and(multipleHits_leftOne_9, multipleHits_rightOne_7)
node multipleHits_leftTwo_3 = or(_multipleHits_T_35, _multipleHits_T_36)
node _multipleHits_T_37 = bits(_multipleHits_T_31, 3, 2)
node _multipleHits_T_38 = bits(_multipleHits_T_37, 0, 0)
node multipleHits_leftOne_11 = bits(_multipleHits_T_38, 0, 0)
node _multipleHits_T_39 = bits(_multipleHits_T_37, 1, 1)
node multipleHits_rightOne_8 = bits(_multipleHits_T_39, 0, 0)
node multipleHits_rightOne_9 = or(multipleHits_leftOne_11, multipleHits_rightOne_8)
node _multipleHits_T_40 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_41 = and(multipleHits_leftOne_11, multipleHits_rightOne_8)
node multipleHits_rightTwo_4 = or(_multipleHits_T_40, _multipleHits_T_41)
node multipleHits_rightOne_10 = or(multipleHits_leftOne_10, multipleHits_rightOne_9)
node _multipleHits_T_42 = or(multipleHits_leftTwo_3, multipleHits_rightTwo_4)
node _multipleHits_T_43 = and(multipleHits_leftOne_10, multipleHits_rightOne_9)
node multipleHits_rightTwo_5 = or(_multipleHits_T_42, _multipleHits_T_43)
node multipleHits_rightOne_11 = or(multipleHits_leftOne_8, multipleHits_rightOne_10)
node _multipleHits_T_44 = or(multipleHits_leftTwo_2, multipleHits_rightTwo_5)
node _multipleHits_T_45 = and(multipleHits_leftOne_8, multipleHits_rightOne_10)
node multipleHits_rightTwo_6 = or(_multipleHits_T_44, _multipleHits_T_45)
node _multipleHits_T_46 = or(multipleHits_leftOne_5, multipleHits_rightOne_11)
node _multipleHits_T_47 = or(multipleHits_leftTwo_1, multipleHits_rightTwo_6)
node _multipleHits_T_48 = and(multipleHits_leftOne_5, multipleHits_rightOne_11)
node multipleHits = or(_multipleHits_T_47, _multipleHits_T_48)
node _io_req_ready_T = eq(state, UInt<2>(0h0))
connect io.req.ready, _io_req_ready_T
node _io_resp_pf_ld_T = and(bad_va, cmd_read)
node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits)
node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1)
node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2)
connect io.resp.pf.ld, _io_resp_pf_ld_T_3
node _io_resp_pf_st_T = and(bad_va, cmd_write_perms)
node _io_resp_pf_st_T_1 = and(pf_st_array, hits)
node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1)
node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2)
connect io.resp.pf.st, _io_resp_pf_st_T_3
node _io_resp_pf_inst_T = and(pf_inst_array, hits)
node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T)
node _io_resp_pf_inst_T_2 = or(bad_va, _io_resp_pf_inst_T_1)
connect io.resp.pf.inst, _io_resp_pf_inst_T_2
node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read)
node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits)
node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1)
node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2)
connect io.resp.gf.ld, _io_resp_gf_ld_T_3
node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms)
node _io_resp_gf_st_T_1 = and(gf_st_array, hits)
node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1)
node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2)
connect io.resp.gf.st, _io_resp_gf_st_T_3
node _io_resp_gf_inst_T = and(gf_inst_array, hits)
node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T)
node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1)
connect io.resp.gf.inst, _io_resp_gf_inst_T_2
node _io_resp_ae_ld_T = and(ae_ld_array, hits)
node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T)
connect io.resp.ae.ld, _io_resp_ae_ld_T_1
node _io_resp_ae_st_T = and(ae_st_array, hits)
node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T)
connect io.resp.ae.st, _io_resp_ae_st_T_1
node _io_resp_ae_inst_T = not(px_array)
node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits)
node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1)
connect io.resp.ae.inst, _io_resp_ae_inst_T_2
node _io_resp_ma_ld_T = and(misaligned, cmd_read)
connect io.resp.ma.ld, _io_resp_ma_ld_T
node _io_resp_ma_st_T = and(misaligned, cmd_write)
connect io.resp.ma.st, _io_resp_ma_st_T
connect io.resp.ma.inst, UInt<1>(0h0)
node _io_resp_cacheable_T = and(c_array, hits)
node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T)
connect io.resp.cacheable, _io_resp_cacheable_T_1
node _io_resp_must_alloc_T = and(must_alloc_array, hits)
node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T)
connect io.resp.must_alloc, _io_resp_must_alloc_T_1
node _io_resp_prefetchable_T = and(prefetchable_array, hits)
node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T)
node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1))
connect io.resp.prefetchable, _io_resp_prefetchable_T_2
node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch)
node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss)
node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits)
connect io.resp.miss, _io_resp_miss_T_2
node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0)
node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T)
connect io.resp.paddr, _io_resp_paddr_T_1
connect io.resp.size, io.req.bits.size
connect io.resp.cmd, io.req.bits.cmd
node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte)
connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T
node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0))
node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn)
node _io_resp_gpa_page_T_2 = shr(r_gpa, 12)
node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2)
node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0)
node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0)
node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1)
node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset)
connect io.resp.gpa, _io_resp_gpa_T
node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1))
connect io.ptw.req.valid, _io_ptw_req_valid_T
node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0))
connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T
connect io.ptw.req.bits.bits.addr, r_refill_tag
connect io.ptw.req.bits.bits.vstage1, r_vstage1_en
connect io.ptw.req.bits.bits.stage2, r_stage2_en
connect io.ptw.req.bits.bits.need_gpa, r_need_gpa
node _T_47 = and(io.ptw.req.ready, io.ptw.req.valid)
node _T_48 = and(_T_47, io.ptw.req.bits.valid)
when _T_48 :
connect r_gpa_valid, UInt<1>(0h0)
connect r_gpa_vpn, r_refill_tag
node _T_49 = and(io.req.ready, io.req.valid)
node _T_50 = and(_T_49, tlb_miss)
when _T_50 :
connect state, UInt<2>(0h1)
connect r_refill_tag, vpn
connect r_need_gpa, tlb_hit_if_not_gpa_miss
connect r_vstage1_en, vstage1_en
connect r_stage2_en, stage2_en
node r_superpage_repl_addr_left_subtree_older = bits(state_reg_1, 2, 2)
node r_superpage_repl_addr_left_subtree_state = bits(state_reg_1, 1, 1)
node r_superpage_repl_addr_right_subtree_state = bits(state_reg_1, 0, 0)
node _r_superpage_repl_addr_T = bits(r_superpage_repl_addr_left_subtree_state, 0, 0)
node _r_superpage_repl_addr_T_1 = bits(r_superpage_repl_addr_right_subtree_state, 0, 0)
node _r_superpage_repl_addr_T_2 = mux(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T, _r_superpage_repl_addr_T_1)
node _r_superpage_repl_addr_T_3 = cat(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2)
node r_superpage_repl_addr_valids_lo = cat(superpage_entries[1].valid[0], superpage_entries[0].valid[0])
node r_superpage_repl_addr_valids_hi = cat(superpage_entries[3].valid[0], superpage_entries[2].valid[0])
node r_superpage_repl_addr_valids = cat(r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo)
node _r_superpage_repl_addr_T_4 = andr(r_superpage_repl_addr_valids)
node _r_superpage_repl_addr_T_5 = not(r_superpage_repl_addr_valids)
node _r_superpage_repl_addr_T_6 = bits(_r_superpage_repl_addr_T_5, 0, 0)
node _r_superpage_repl_addr_T_7 = bits(_r_superpage_repl_addr_T_5, 1, 1)
node _r_superpage_repl_addr_T_8 = bits(_r_superpage_repl_addr_T_5, 2, 2)
node _r_superpage_repl_addr_T_9 = bits(_r_superpage_repl_addr_T_5, 3, 3)
node _r_superpage_repl_addr_T_10 = mux(_r_superpage_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _r_superpage_repl_addr_T_11 = mux(_r_superpage_repl_addr_T_7, UInt<1>(0h1), _r_superpage_repl_addr_T_10)
node _r_superpage_repl_addr_T_12 = mux(_r_superpage_repl_addr_T_6, UInt<1>(0h0), _r_superpage_repl_addr_T_11)
node _r_superpage_repl_addr_T_13 = mux(_r_superpage_repl_addr_T_4, _r_superpage_repl_addr_T_3, _r_superpage_repl_addr_T_12)
connect r_superpage_repl_addr, _r_superpage_repl_addr_T_13
node r_sectored_repl_addr_left_subtree_older = bits(state_vec[0], 6, 6)
node r_sectored_repl_addr_left_subtree_state = bits(state_vec[0], 5, 3)
node r_sectored_repl_addr_right_subtree_state = bits(state_vec[0], 2, 0)
node r_sectored_repl_addr_left_subtree_older_1 = bits(r_sectored_repl_addr_left_subtree_state, 2, 2)
node r_sectored_repl_addr_left_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 1, 1)
node r_sectored_repl_addr_right_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 0, 0)
node _r_sectored_repl_addr_T = bits(r_sectored_repl_addr_left_subtree_state_1, 0, 0)
node _r_sectored_repl_addr_T_1 = bits(r_sectored_repl_addr_right_subtree_state_1, 0, 0)
node _r_sectored_repl_addr_T_2 = mux(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T, _r_sectored_repl_addr_T_1)
node _r_sectored_repl_addr_T_3 = cat(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2)
node r_sectored_repl_addr_left_subtree_older_2 = bits(r_sectored_repl_addr_right_subtree_state, 2, 2)
node r_sectored_repl_addr_left_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 1, 1)
node r_sectored_repl_addr_right_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 0, 0)
node _r_sectored_repl_addr_T_4 = bits(r_sectored_repl_addr_left_subtree_state_2, 0, 0)
node _r_sectored_repl_addr_T_5 = bits(r_sectored_repl_addr_right_subtree_state_2, 0, 0)
node _r_sectored_repl_addr_T_6 = mux(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_4, _r_sectored_repl_addr_T_5)
node _r_sectored_repl_addr_T_7 = cat(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6)
node _r_sectored_repl_addr_T_8 = mux(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_3, _r_sectored_repl_addr_T_7)
node _r_sectored_repl_addr_T_9 = cat(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8)
node _r_sectored_repl_addr_valids_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1])
node _r_sectored_repl_addr_valids_T_1 = or(_r_sectored_repl_addr_valids_T, sectored_entries[0][0].valid[2])
node _r_sectored_repl_addr_valids_T_2 = or(_r_sectored_repl_addr_valids_T_1, sectored_entries[0][0].valid[3])
node _r_sectored_repl_addr_valids_T_3 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1])
node _r_sectored_repl_addr_valids_T_4 = or(_r_sectored_repl_addr_valids_T_3, sectored_entries[0][1].valid[2])
node _r_sectored_repl_addr_valids_T_5 = or(_r_sectored_repl_addr_valids_T_4, sectored_entries[0][1].valid[3])
node _r_sectored_repl_addr_valids_T_6 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1])
node _r_sectored_repl_addr_valids_T_7 = or(_r_sectored_repl_addr_valids_T_6, sectored_entries[0][2].valid[2])
node _r_sectored_repl_addr_valids_T_8 = or(_r_sectored_repl_addr_valids_T_7, sectored_entries[0][2].valid[3])
node _r_sectored_repl_addr_valids_T_9 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1])
node _r_sectored_repl_addr_valids_T_10 = or(_r_sectored_repl_addr_valids_T_9, sectored_entries[0][3].valid[2])
node _r_sectored_repl_addr_valids_T_11 = or(_r_sectored_repl_addr_valids_T_10, sectored_entries[0][3].valid[3])
node _r_sectored_repl_addr_valids_T_12 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1])
node _r_sectored_repl_addr_valids_T_13 = or(_r_sectored_repl_addr_valids_T_12, sectored_entries[0][4].valid[2])
node _r_sectored_repl_addr_valids_T_14 = or(_r_sectored_repl_addr_valids_T_13, sectored_entries[0][4].valid[3])
node _r_sectored_repl_addr_valids_T_15 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1])
node _r_sectored_repl_addr_valids_T_16 = or(_r_sectored_repl_addr_valids_T_15, sectored_entries[0][5].valid[2])
node _r_sectored_repl_addr_valids_T_17 = or(_r_sectored_repl_addr_valids_T_16, sectored_entries[0][5].valid[3])
node _r_sectored_repl_addr_valids_T_18 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1])
node _r_sectored_repl_addr_valids_T_19 = or(_r_sectored_repl_addr_valids_T_18, sectored_entries[0][6].valid[2])
node _r_sectored_repl_addr_valids_T_20 = or(_r_sectored_repl_addr_valids_T_19, sectored_entries[0][6].valid[3])
node _r_sectored_repl_addr_valids_T_21 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1])
node _r_sectored_repl_addr_valids_T_22 = or(_r_sectored_repl_addr_valids_T_21, sectored_entries[0][7].valid[2])
node _r_sectored_repl_addr_valids_T_23 = or(_r_sectored_repl_addr_valids_T_22, sectored_entries[0][7].valid[3])
node r_sectored_repl_addr_valids_lo_lo = cat(_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2)
node r_sectored_repl_addr_valids_lo_hi = cat(_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8)
node r_sectored_repl_addr_valids_lo = cat(r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo)
node r_sectored_repl_addr_valids_hi_lo = cat(_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14)
node r_sectored_repl_addr_valids_hi_hi = cat(_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20)
node r_sectored_repl_addr_valids_hi = cat(r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo)
node r_sectored_repl_addr_valids = cat(r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo)
node _r_sectored_repl_addr_T_10 = andr(r_sectored_repl_addr_valids)
node _r_sectored_repl_addr_T_11 = not(r_sectored_repl_addr_valids)
node _r_sectored_repl_addr_T_12 = bits(_r_sectored_repl_addr_T_11, 0, 0)
node _r_sectored_repl_addr_T_13 = bits(_r_sectored_repl_addr_T_11, 1, 1)
node _r_sectored_repl_addr_T_14 = bits(_r_sectored_repl_addr_T_11, 2, 2)
node _r_sectored_repl_addr_T_15 = bits(_r_sectored_repl_addr_T_11, 3, 3)
node _r_sectored_repl_addr_T_16 = bits(_r_sectored_repl_addr_T_11, 4, 4)
node _r_sectored_repl_addr_T_17 = bits(_r_sectored_repl_addr_T_11, 5, 5)
node _r_sectored_repl_addr_T_18 = bits(_r_sectored_repl_addr_T_11, 6, 6)
node _r_sectored_repl_addr_T_19 = bits(_r_sectored_repl_addr_T_11, 7, 7)
node _r_sectored_repl_addr_T_20 = mux(_r_sectored_repl_addr_T_18, UInt<3>(0h6), UInt<3>(0h7))
node _r_sectored_repl_addr_T_21 = mux(_r_sectored_repl_addr_T_17, UInt<3>(0h5), _r_sectored_repl_addr_T_20)
node _r_sectored_repl_addr_T_22 = mux(_r_sectored_repl_addr_T_16, UInt<3>(0h4), _r_sectored_repl_addr_T_21)
node _r_sectored_repl_addr_T_23 = mux(_r_sectored_repl_addr_T_15, UInt<2>(0h3), _r_sectored_repl_addr_T_22)
node _r_sectored_repl_addr_T_24 = mux(_r_sectored_repl_addr_T_14, UInt<2>(0h2), _r_sectored_repl_addr_T_23)
node _r_sectored_repl_addr_T_25 = mux(_r_sectored_repl_addr_T_13, UInt<1>(0h1), _r_sectored_repl_addr_T_24)
node _r_sectored_repl_addr_T_26 = mux(_r_sectored_repl_addr_T_12, UInt<1>(0h0), _r_sectored_repl_addr_T_25)
node _r_sectored_repl_addr_T_27 = mux(_r_sectored_repl_addr_T_10, _r_sectored_repl_addr_T_9, _r_sectored_repl_addr_T_26)
connect r_sectored_repl_addr, _r_sectored_repl_addr_T_27
node _r_sectored_hit_valid_T = or(sector_hits_0, sector_hits_1)
node _r_sectored_hit_valid_T_1 = or(_r_sectored_hit_valid_T, sector_hits_2)
node _r_sectored_hit_valid_T_2 = or(_r_sectored_hit_valid_T_1, sector_hits_3)
node _r_sectored_hit_valid_T_3 = or(_r_sectored_hit_valid_T_2, sector_hits_4)
node _r_sectored_hit_valid_T_4 = or(_r_sectored_hit_valid_T_3, sector_hits_5)
node _r_sectored_hit_valid_T_5 = or(_r_sectored_hit_valid_T_4, sector_hits_6)
node _r_sectored_hit_valid_T_6 = or(_r_sectored_hit_valid_T_5, sector_hits_7)
connect r_sectored_hit.valid, _r_sectored_hit_valid_T_6
node r_sectored_hit_bits_lo_lo = cat(sector_hits_1, sector_hits_0)
node r_sectored_hit_bits_lo_hi = cat(sector_hits_3, sector_hits_2)
node r_sectored_hit_bits_lo = cat(r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo)
node r_sectored_hit_bits_hi_lo = cat(sector_hits_5, sector_hits_4)
node r_sectored_hit_bits_hi_hi = cat(sector_hits_7, sector_hits_6)
node r_sectored_hit_bits_hi = cat(r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo)
node _r_sectored_hit_bits_T = cat(r_sectored_hit_bits_hi, r_sectored_hit_bits_lo)
node r_sectored_hit_bits_hi_1 = bits(_r_sectored_hit_bits_T, 7, 4)
node r_sectored_hit_bits_lo_1 = bits(_r_sectored_hit_bits_T, 3, 0)
node _r_sectored_hit_bits_T_1 = orr(r_sectored_hit_bits_hi_1)
node _r_sectored_hit_bits_T_2 = or(r_sectored_hit_bits_hi_1, r_sectored_hit_bits_lo_1)
node r_sectored_hit_bits_hi_2 = bits(_r_sectored_hit_bits_T_2, 3, 2)
node r_sectored_hit_bits_lo_2 = bits(_r_sectored_hit_bits_T_2, 1, 0)
node _r_sectored_hit_bits_T_3 = orr(r_sectored_hit_bits_hi_2)
node _r_sectored_hit_bits_T_4 = or(r_sectored_hit_bits_hi_2, r_sectored_hit_bits_lo_2)
node _r_sectored_hit_bits_T_5 = bits(_r_sectored_hit_bits_T_4, 1, 1)
node _r_sectored_hit_bits_T_6 = cat(_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5)
node _r_sectored_hit_bits_T_7 = cat(_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6)
connect r_sectored_hit.bits, _r_sectored_hit_bits_T_7
node _r_superpage_hit_valid_T = or(superpage_hits_0, superpage_hits_1)
node _r_superpage_hit_valid_T_1 = or(_r_superpage_hit_valid_T, superpage_hits_2)
node _r_superpage_hit_valid_T_2 = or(_r_superpage_hit_valid_T_1, superpage_hits_3)
connect r_superpage_hit.valid, _r_superpage_hit_valid_T_2
node r_superpage_hit_bits_lo = cat(superpage_hits_1, superpage_hits_0)
node r_superpage_hit_bits_hi = cat(superpage_hits_3, superpage_hits_2)
node _r_superpage_hit_bits_T = cat(r_superpage_hit_bits_hi, r_superpage_hit_bits_lo)
node r_superpage_hit_bits_hi_1 = bits(_r_superpage_hit_bits_T, 3, 2)
node r_superpage_hit_bits_lo_1 = bits(_r_superpage_hit_bits_T, 1, 0)
node _r_superpage_hit_bits_T_1 = orr(r_superpage_hit_bits_hi_1)
node _r_superpage_hit_bits_T_2 = or(r_superpage_hit_bits_hi_1, r_superpage_hit_bits_lo_1)
node _r_superpage_hit_bits_T_3 = bits(_r_superpage_hit_bits_T_2, 1, 1)
node _r_superpage_hit_bits_T_4 = cat(_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3)
connect r_superpage_hit.bits, _r_superpage_hit_bits_T_4
node _T_51 = eq(state, UInt<2>(0h1))
when _T_51 :
when io.sfence.valid :
connect state, UInt<2>(0h0)
when io.ptw.req.ready :
node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2))
connect state, _state_T
when io.kill :
connect state, UInt<2>(0h0)
node _T_52 = eq(state, UInt<2>(0h2))
node _T_53 = and(_T_52, io.sfence.valid)
when _T_53 :
connect state, UInt<2>(0h3)
when io.ptw.resp.valid :
connect state, UInt<2>(0h0)
when io.sfence.valid :
node _T_54 = eq(io.sfence.bits.rs1, UInt<1>(0h0))
node _T_55 = shr(io.sfence.bits.addr, 12)
node _T_56 = eq(_T_55, vpn)
node _T_57 = or(_T_54, _T_56)
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_T_57, UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at TLB.scala:719 assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn)\n") : printf
assert(clock, _T_57, UInt<1>(0h1), "") : assert
node hv = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_61 = eq(hg, UInt<1>(0h0))
node _T_62 = and(_T_61, io.sfence.bits.rs1)
when _T_62 :
node _T_63 = xor(sectored_entries[0][0].tag_vpn, vpn)
node _T_64 = shr(_T_63, 2)
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = eq(sectored_entries[0][0].tag_v, hv)
node _T_67 = and(_T_65, _T_66)
when _T_67 :
wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_1 : UInt<42>
connect _WIRE_1, sectored_entries[0][0].data[0]
node _T_68 = bits(_WIRE_1, 0, 0)
connect _WIRE.fragmented_superpage, _T_68
node _T_69 = bits(_WIRE_1, 1, 1)
connect _WIRE.c, _T_69
node _T_70 = bits(_WIRE_1, 2, 2)
connect _WIRE.eff, _T_70
node _T_71 = bits(_WIRE_1, 3, 3)
connect _WIRE.paa, _T_71
node _T_72 = bits(_WIRE_1, 4, 4)
connect _WIRE.pal, _T_72
node _T_73 = bits(_WIRE_1, 5, 5)
connect _WIRE.ppp, _T_73
node _T_74 = bits(_WIRE_1, 6, 6)
connect _WIRE.pr, _T_74
node _T_75 = bits(_WIRE_1, 7, 7)
connect _WIRE.px, _T_75
node _T_76 = bits(_WIRE_1, 8, 8)
connect _WIRE.pw, _T_76
node _T_77 = bits(_WIRE_1, 9, 9)
connect _WIRE.hr, _T_77
node _T_78 = bits(_WIRE_1, 10, 10)
connect _WIRE.hx, _T_78
node _T_79 = bits(_WIRE_1, 11, 11)
connect _WIRE.hw, _T_79
node _T_80 = bits(_WIRE_1, 12, 12)
connect _WIRE.sr, _T_80
node _T_81 = bits(_WIRE_1, 13, 13)
connect _WIRE.sx, _T_81
node _T_82 = bits(_WIRE_1, 14, 14)
connect _WIRE.sw, _T_82
node _T_83 = bits(_WIRE_1, 15, 15)
connect _WIRE.gf, _T_83
node _T_84 = bits(_WIRE_1, 16, 16)
connect _WIRE.pf, _T_84
node _T_85 = bits(_WIRE_1, 17, 17)
connect _WIRE.ae_stage2, _T_85
node _T_86 = bits(_WIRE_1, 18, 18)
connect _WIRE.ae_final, _T_86
node _T_87 = bits(_WIRE_1, 19, 19)
connect _WIRE.ae_ptw, _T_87
node _T_88 = bits(_WIRE_1, 20, 20)
connect _WIRE.g, _T_88
node _T_89 = bits(_WIRE_1, 21, 21)
connect _WIRE.u, _T_89
node _T_90 = bits(_WIRE_1, 41, 22)
connect _WIRE.ppn, _T_90
wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_3 : UInt<42>
connect _WIRE_3, sectored_entries[0][0].data[1]
node _T_91 = bits(_WIRE_3, 0, 0)
connect _WIRE_2.fragmented_superpage, _T_91
node _T_92 = bits(_WIRE_3, 1, 1)
connect _WIRE_2.c, _T_92
node _T_93 = bits(_WIRE_3, 2, 2)
connect _WIRE_2.eff, _T_93
node _T_94 = bits(_WIRE_3, 3, 3)
connect _WIRE_2.paa, _T_94
node _T_95 = bits(_WIRE_3, 4, 4)
connect _WIRE_2.pal, _T_95
node _T_96 = bits(_WIRE_3, 5, 5)
connect _WIRE_2.ppp, _T_96
node _T_97 = bits(_WIRE_3, 6, 6)
connect _WIRE_2.pr, _T_97
node _T_98 = bits(_WIRE_3, 7, 7)
connect _WIRE_2.px, _T_98
node _T_99 = bits(_WIRE_3, 8, 8)
connect _WIRE_2.pw, _T_99
node _T_100 = bits(_WIRE_3, 9, 9)
connect _WIRE_2.hr, _T_100
node _T_101 = bits(_WIRE_3, 10, 10)
connect _WIRE_2.hx, _T_101
node _T_102 = bits(_WIRE_3, 11, 11)
connect _WIRE_2.hw, _T_102
node _T_103 = bits(_WIRE_3, 12, 12)
connect _WIRE_2.sr, _T_103
node _T_104 = bits(_WIRE_3, 13, 13)
connect _WIRE_2.sx, _T_104
node _T_105 = bits(_WIRE_3, 14, 14)
connect _WIRE_2.sw, _T_105
node _T_106 = bits(_WIRE_3, 15, 15)
connect _WIRE_2.gf, _T_106
node _T_107 = bits(_WIRE_3, 16, 16)
connect _WIRE_2.pf, _T_107
node _T_108 = bits(_WIRE_3, 17, 17)
connect _WIRE_2.ae_stage2, _T_108
node _T_109 = bits(_WIRE_3, 18, 18)
connect _WIRE_2.ae_final, _T_109
node _T_110 = bits(_WIRE_3, 19, 19)
connect _WIRE_2.ae_ptw, _T_110
node _T_111 = bits(_WIRE_3, 20, 20)
connect _WIRE_2.g, _T_111
node _T_112 = bits(_WIRE_3, 21, 21)
connect _WIRE_2.u, _T_112
node _T_113 = bits(_WIRE_3, 41, 22)
connect _WIRE_2.ppn, _T_113
wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_5 : UInt<42>
connect _WIRE_5, sectored_entries[0][0].data[2]
node _T_114 = bits(_WIRE_5, 0, 0)
connect _WIRE_4.fragmented_superpage, _T_114
node _T_115 = bits(_WIRE_5, 1, 1)
connect _WIRE_4.c, _T_115
node _T_116 = bits(_WIRE_5, 2, 2)
connect _WIRE_4.eff, _T_116
node _T_117 = bits(_WIRE_5, 3, 3)
connect _WIRE_4.paa, _T_117
node _T_118 = bits(_WIRE_5, 4, 4)
connect _WIRE_4.pal, _T_118
node _T_119 = bits(_WIRE_5, 5, 5)
connect _WIRE_4.ppp, _T_119
node _T_120 = bits(_WIRE_5, 6, 6)
connect _WIRE_4.pr, _T_120
node _T_121 = bits(_WIRE_5, 7, 7)
connect _WIRE_4.px, _T_121
node _T_122 = bits(_WIRE_5, 8, 8)
connect _WIRE_4.pw, _T_122
node _T_123 = bits(_WIRE_5, 9, 9)
connect _WIRE_4.hr, _T_123
node _T_124 = bits(_WIRE_5, 10, 10)
connect _WIRE_4.hx, _T_124
node _T_125 = bits(_WIRE_5, 11, 11)
connect _WIRE_4.hw, _T_125
node _T_126 = bits(_WIRE_5, 12, 12)
connect _WIRE_4.sr, _T_126
node _T_127 = bits(_WIRE_5, 13, 13)
connect _WIRE_4.sx, _T_127
node _T_128 = bits(_WIRE_5, 14, 14)
connect _WIRE_4.sw, _T_128
node _T_129 = bits(_WIRE_5, 15, 15)
connect _WIRE_4.gf, _T_129
node _T_130 = bits(_WIRE_5, 16, 16)
connect _WIRE_4.pf, _T_130
node _T_131 = bits(_WIRE_5, 17, 17)
connect _WIRE_4.ae_stage2, _T_131
node _T_132 = bits(_WIRE_5, 18, 18)
connect _WIRE_4.ae_final, _T_132
node _T_133 = bits(_WIRE_5, 19, 19)
connect _WIRE_4.ae_ptw, _T_133
node _T_134 = bits(_WIRE_5, 20, 20)
connect _WIRE_4.g, _T_134
node _T_135 = bits(_WIRE_5, 21, 21)
connect _WIRE_4.u, _T_135
node _T_136 = bits(_WIRE_5, 41, 22)
connect _WIRE_4.ppn, _T_136
wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_7 : UInt<42>
connect _WIRE_7, sectored_entries[0][0].data[3]
node _T_137 = bits(_WIRE_7, 0, 0)
connect _WIRE_6.fragmented_superpage, _T_137
node _T_138 = bits(_WIRE_7, 1, 1)
connect _WIRE_6.c, _T_138
node _T_139 = bits(_WIRE_7, 2, 2)
connect _WIRE_6.eff, _T_139
node _T_140 = bits(_WIRE_7, 3, 3)
connect _WIRE_6.paa, _T_140
node _T_141 = bits(_WIRE_7, 4, 4)
connect _WIRE_6.pal, _T_141
node _T_142 = bits(_WIRE_7, 5, 5)
connect _WIRE_6.ppp, _T_142
node _T_143 = bits(_WIRE_7, 6, 6)
connect _WIRE_6.pr, _T_143
node _T_144 = bits(_WIRE_7, 7, 7)
connect _WIRE_6.px, _T_144
node _T_145 = bits(_WIRE_7, 8, 8)
connect _WIRE_6.pw, _T_145
node _T_146 = bits(_WIRE_7, 9, 9)
connect _WIRE_6.hr, _T_146
node _T_147 = bits(_WIRE_7, 10, 10)
connect _WIRE_6.hx, _T_147
node _T_148 = bits(_WIRE_7, 11, 11)
connect _WIRE_6.hw, _T_148
node _T_149 = bits(_WIRE_7, 12, 12)
connect _WIRE_6.sr, _T_149
node _T_150 = bits(_WIRE_7, 13, 13)
connect _WIRE_6.sx, _T_150
node _T_151 = bits(_WIRE_7, 14, 14)
connect _WIRE_6.sw, _T_151
node _T_152 = bits(_WIRE_7, 15, 15)
connect _WIRE_6.gf, _T_152
node _T_153 = bits(_WIRE_7, 16, 16)
connect _WIRE_6.pf, _T_153
node _T_154 = bits(_WIRE_7, 17, 17)
connect _WIRE_6.ae_stage2, _T_154
node _T_155 = bits(_WIRE_7, 18, 18)
connect _WIRE_6.ae_final, _T_155
node _T_156 = bits(_WIRE_7, 19, 19)
connect _WIRE_6.ae_ptw, _T_156
node _T_157 = bits(_WIRE_7, 20, 20)
connect _WIRE_6.g, _T_157
node _T_158 = bits(_WIRE_7, 21, 21)
connect _WIRE_6.u, _T_158
node _T_159 = bits(_WIRE_7, 41, 22)
connect _WIRE_6.ppn, _T_159
node _T_160 = eq(sectored_entries[0][0].tag_v, hv)
node _T_161 = bits(vpn, 1, 0)
node _T_162 = eq(UInt<1>(0h0), _T_161)
node _T_163 = and(_T_160, _T_162)
when _T_163 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_164 = eq(sectored_entries[0][0].tag_v, hv)
node _T_165 = bits(vpn, 1, 0)
node _T_166 = eq(UInt<1>(0h1), _T_165)
node _T_167 = and(_T_164, _T_166)
when _T_167 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_168 = eq(sectored_entries[0][0].tag_v, hv)
node _T_169 = bits(vpn, 1, 0)
node _T_170 = eq(UInt<2>(0h2), _T_169)
node _T_171 = and(_T_168, _T_170)
when _T_171 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_172 = eq(sectored_entries[0][0].tag_v, hv)
node _T_173 = bits(vpn, 1, 0)
node _T_174 = eq(UInt<2>(0h3), _T_173)
node _T_175 = and(_T_172, _T_174)
when _T_175 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
node _T_176 = xor(sectored_entries[0][0].tag_vpn, vpn)
node _T_177 = shr(_T_176, 18)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_9 : UInt<42>
connect _WIRE_9, sectored_entries[0][0].data[0]
node _T_179 = bits(_WIRE_9, 0, 0)
connect _WIRE_8.fragmented_superpage, _T_179
node _T_180 = bits(_WIRE_9, 1, 1)
connect _WIRE_8.c, _T_180
node _T_181 = bits(_WIRE_9, 2, 2)
connect _WIRE_8.eff, _T_181
node _T_182 = bits(_WIRE_9, 3, 3)
connect _WIRE_8.paa, _T_182
node _T_183 = bits(_WIRE_9, 4, 4)
connect _WIRE_8.pal, _T_183
node _T_184 = bits(_WIRE_9, 5, 5)
connect _WIRE_8.ppp, _T_184
node _T_185 = bits(_WIRE_9, 6, 6)
connect _WIRE_8.pr, _T_185
node _T_186 = bits(_WIRE_9, 7, 7)
connect _WIRE_8.px, _T_186
node _T_187 = bits(_WIRE_9, 8, 8)
connect _WIRE_8.pw, _T_187
node _T_188 = bits(_WIRE_9, 9, 9)
connect _WIRE_8.hr, _T_188
node _T_189 = bits(_WIRE_9, 10, 10)
connect _WIRE_8.hx, _T_189
node _T_190 = bits(_WIRE_9, 11, 11)
connect _WIRE_8.hw, _T_190
node _T_191 = bits(_WIRE_9, 12, 12)
connect _WIRE_8.sr, _T_191
node _T_192 = bits(_WIRE_9, 13, 13)
connect _WIRE_8.sx, _T_192
node _T_193 = bits(_WIRE_9, 14, 14)
connect _WIRE_8.sw, _T_193
node _T_194 = bits(_WIRE_9, 15, 15)
connect _WIRE_8.gf, _T_194
node _T_195 = bits(_WIRE_9, 16, 16)
connect _WIRE_8.pf, _T_195
node _T_196 = bits(_WIRE_9, 17, 17)
connect _WIRE_8.ae_stage2, _T_196
node _T_197 = bits(_WIRE_9, 18, 18)
connect _WIRE_8.ae_final, _T_197
node _T_198 = bits(_WIRE_9, 19, 19)
connect _WIRE_8.ae_ptw, _T_198
node _T_199 = bits(_WIRE_9, 20, 20)
connect _WIRE_8.g, _T_199
node _T_200 = bits(_WIRE_9, 21, 21)
connect _WIRE_8.u, _T_200
node _T_201 = bits(_WIRE_9, 41, 22)
connect _WIRE_8.ppn, _T_201
wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_11 : UInt<42>
connect _WIRE_11, sectored_entries[0][0].data[1]
node _T_202 = bits(_WIRE_11, 0, 0)
connect _WIRE_10.fragmented_superpage, _T_202
node _T_203 = bits(_WIRE_11, 1, 1)
connect _WIRE_10.c, _T_203
node _T_204 = bits(_WIRE_11, 2, 2)
connect _WIRE_10.eff, _T_204
node _T_205 = bits(_WIRE_11, 3, 3)
connect _WIRE_10.paa, _T_205
node _T_206 = bits(_WIRE_11, 4, 4)
connect _WIRE_10.pal, _T_206
node _T_207 = bits(_WIRE_11, 5, 5)
connect _WIRE_10.ppp, _T_207
node _T_208 = bits(_WIRE_11, 6, 6)
connect _WIRE_10.pr, _T_208
node _T_209 = bits(_WIRE_11, 7, 7)
connect _WIRE_10.px, _T_209
node _T_210 = bits(_WIRE_11, 8, 8)
connect _WIRE_10.pw, _T_210
node _T_211 = bits(_WIRE_11, 9, 9)
connect _WIRE_10.hr, _T_211
node _T_212 = bits(_WIRE_11, 10, 10)
connect _WIRE_10.hx, _T_212
node _T_213 = bits(_WIRE_11, 11, 11)
connect _WIRE_10.hw, _T_213
node _T_214 = bits(_WIRE_11, 12, 12)
connect _WIRE_10.sr, _T_214
node _T_215 = bits(_WIRE_11, 13, 13)
connect _WIRE_10.sx, _T_215
node _T_216 = bits(_WIRE_11, 14, 14)
connect _WIRE_10.sw, _T_216
node _T_217 = bits(_WIRE_11, 15, 15)
connect _WIRE_10.gf, _T_217
node _T_218 = bits(_WIRE_11, 16, 16)
connect _WIRE_10.pf, _T_218
node _T_219 = bits(_WIRE_11, 17, 17)
connect _WIRE_10.ae_stage2, _T_219
node _T_220 = bits(_WIRE_11, 18, 18)
connect _WIRE_10.ae_final, _T_220
node _T_221 = bits(_WIRE_11, 19, 19)
connect _WIRE_10.ae_ptw, _T_221
node _T_222 = bits(_WIRE_11, 20, 20)
connect _WIRE_10.g, _T_222
node _T_223 = bits(_WIRE_11, 21, 21)
connect _WIRE_10.u, _T_223
node _T_224 = bits(_WIRE_11, 41, 22)
connect _WIRE_10.ppn, _T_224
wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_13 : UInt<42>
connect _WIRE_13, sectored_entries[0][0].data[2]
node _T_225 = bits(_WIRE_13, 0, 0)
connect _WIRE_12.fragmented_superpage, _T_225
node _T_226 = bits(_WIRE_13, 1, 1)
connect _WIRE_12.c, _T_226
node _T_227 = bits(_WIRE_13, 2, 2)
connect _WIRE_12.eff, _T_227
node _T_228 = bits(_WIRE_13, 3, 3)
connect _WIRE_12.paa, _T_228
node _T_229 = bits(_WIRE_13, 4, 4)
connect _WIRE_12.pal, _T_229
node _T_230 = bits(_WIRE_13, 5, 5)
connect _WIRE_12.ppp, _T_230
node _T_231 = bits(_WIRE_13, 6, 6)
connect _WIRE_12.pr, _T_231
node _T_232 = bits(_WIRE_13, 7, 7)
connect _WIRE_12.px, _T_232
node _T_233 = bits(_WIRE_13, 8, 8)
connect _WIRE_12.pw, _T_233
node _T_234 = bits(_WIRE_13, 9, 9)
connect _WIRE_12.hr, _T_234
node _T_235 = bits(_WIRE_13, 10, 10)
connect _WIRE_12.hx, _T_235
node _T_236 = bits(_WIRE_13, 11, 11)
connect _WIRE_12.hw, _T_236
node _T_237 = bits(_WIRE_13, 12, 12)
connect _WIRE_12.sr, _T_237
node _T_238 = bits(_WIRE_13, 13, 13)
connect _WIRE_12.sx, _T_238
node _T_239 = bits(_WIRE_13, 14, 14)
connect _WIRE_12.sw, _T_239
node _T_240 = bits(_WIRE_13, 15, 15)
connect _WIRE_12.gf, _T_240
node _T_241 = bits(_WIRE_13, 16, 16)
connect _WIRE_12.pf, _T_241
node _T_242 = bits(_WIRE_13, 17, 17)
connect _WIRE_12.ae_stage2, _T_242
node _T_243 = bits(_WIRE_13, 18, 18)
connect _WIRE_12.ae_final, _T_243
node _T_244 = bits(_WIRE_13, 19, 19)
connect _WIRE_12.ae_ptw, _T_244
node _T_245 = bits(_WIRE_13, 20, 20)
connect _WIRE_12.g, _T_245
node _T_246 = bits(_WIRE_13, 21, 21)
connect _WIRE_12.u, _T_246
node _T_247 = bits(_WIRE_13, 41, 22)
connect _WIRE_12.ppn, _T_247
wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_15 : UInt<42>
connect _WIRE_15, sectored_entries[0][0].data[3]
node _T_248 = bits(_WIRE_15, 0, 0)
connect _WIRE_14.fragmented_superpage, _T_248
node _T_249 = bits(_WIRE_15, 1, 1)
connect _WIRE_14.c, _T_249
node _T_250 = bits(_WIRE_15, 2, 2)
connect _WIRE_14.eff, _T_250
node _T_251 = bits(_WIRE_15, 3, 3)
connect _WIRE_14.paa, _T_251
node _T_252 = bits(_WIRE_15, 4, 4)
connect _WIRE_14.pal, _T_252
node _T_253 = bits(_WIRE_15, 5, 5)
connect _WIRE_14.ppp, _T_253
node _T_254 = bits(_WIRE_15, 6, 6)
connect _WIRE_14.pr, _T_254
node _T_255 = bits(_WIRE_15, 7, 7)
connect _WIRE_14.px, _T_255
node _T_256 = bits(_WIRE_15, 8, 8)
connect _WIRE_14.pw, _T_256
node _T_257 = bits(_WIRE_15, 9, 9)
connect _WIRE_14.hr, _T_257
node _T_258 = bits(_WIRE_15, 10, 10)
connect _WIRE_14.hx, _T_258
node _T_259 = bits(_WIRE_15, 11, 11)
connect _WIRE_14.hw, _T_259
node _T_260 = bits(_WIRE_15, 12, 12)
connect _WIRE_14.sr, _T_260
node _T_261 = bits(_WIRE_15, 13, 13)
connect _WIRE_14.sx, _T_261
node _T_262 = bits(_WIRE_15, 14, 14)
connect _WIRE_14.sw, _T_262
node _T_263 = bits(_WIRE_15, 15, 15)
connect _WIRE_14.gf, _T_263
node _T_264 = bits(_WIRE_15, 16, 16)
connect _WIRE_14.pf, _T_264
node _T_265 = bits(_WIRE_15, 17, 17)
connect _WIRE_14.ae_stage2, _T_265
node _T_266 = bits(_WIRE_15, 18, 18)
connect _WIRE_14.ae_final, _T_266
node _T_267 = bits(_WIRE_15, 19, 19)
connect _WIRE_14.ae_ptw, _T_267
node _T_268 = bits(_WIRE_15, 20, 20)
connect _WIRE_14.g, _T_268
node _T_269 = bits(_WIRE_15, 21, 21)
connect _WIRE_14.u, _T_269
node _T_270 = bits(_WIRE_15, 41, 22)
connect _WIRE_14.ppn, _T_270
node _T_271 = eq(sectored_entries[0][0].tag_v, hv)
node _T_272 = and(_T_271, _WIRE_8.fragmented_superpage)
when _T_272 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_273 = eq(sectored_entries[0][0].tag_v, hv)
node _T_274 = and(_T_273, _WIRE_10.fragmented_superpage)
when _T_274 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_275 = eq(sectored_entries[0][0].tag_v, hv)
node _T_276 = and(_T_275, _WIRE_12.fragmented_superpage)
when _T_276 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_277 = eq(sectored_entries[0][0].tag_v, hv)
node _T_278 = and(_T_277, _WIRE_14.fragmented_superpage)
when _T_278 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
else :
node _T_279 = eq(hg, UInt<1>(0h0))
node _T_280 = and(_T_279, io.sfence.bits.rs2)
when _T_280 :
wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_17 : UInt<42>
connect _WIRE_17, sectored_entries[0][0].data[0]
node _T_281 = bits(_WIRE_17, 0, 0)
connect _WIRE_16.fragmented_superpage, _T_281
node _T_282 = bits(_WIRE_17, 1, 1)
connect _WIRE_16.c, _T_282
node _T_283 = bits(_WIRE_17, 2, 2)
connect _WIRE_16.eff, _T_283
node _T_284 = bits(_WIRE_17, 3, 3)
connect _WIRE_16.paa, _T_284
node _T_285 = bits(_WIRE_17, 4, 4)
connect _WIRE_16.pal, _T_285
node _T_286 = bits(_WIRE_17, 5, 5)
connect _WIRE_16.ppp, _T_286
node _T_287 = bits(_WIRE_17, 6, 6)
connect _WIRE_16.pr, _T_287
node _T_288 = bits(_WIRE_17, 7, 7)
connect _WIRE_16.px, _T_288
node _T_289 = bits(_WIRE_17, 8, 8)
connect _WIRE_16.pw, _T_289
node _T_290 = bits(_WIRE_17, 9, 9)
connect _WIRE_16.hr, _T_290
node _T_291 = bits(_WIRE_17, 10, 10)
connect _WIRE_16.hx, _T_291
node _T_292 = bits(_WIRE_17, 11, 11)
connect _WIRE_16.hw, _T_292
node _T_293 = bits(_WIRE_17, 12, 12)
connect _WIRE_16.sr, _T_293
node _T_294 = bits(_WIRE_17, 13, 13)
connect _WIRE_16.sx, _T_294
node _T_295 = bits(_WIRE_17, 14, 14)
connect _WIRE_16.sw, _T_295
node _T_296 = bits(_WIRE_17, 15, 15)
connect _WIRE_16.gf, _T_296
node _T_297 = bits(_WIRE_17, 16, 16)
connect _WIRE_16.pf, _T_297
node _T_298 = bits(_WIRE_17, 17, 17)
connect _WIRE_16.ae_stage2, _T_298
node _T_299 = bits(_WIRE_17, 18, 18)
connect _WIRE_16.ae_final, _T_299
node _T_300 = bits(_WIRE_17, 19, 19)
connect _WIRE_16.ae_ptw, _T_300
node _T_301 = bits(_WIRE_17, 20, 20)
connect _WIRE_16.g, _T_301
node _T_302 = bits(_WIRE_17, 21, 21)
connect _WIRE_16.u, _T_302
node _T_303 = bits(_WIRE_17, 41, 22)
connect _WIRE_16.ppn, _T_303
wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_19 : UInt<42>
connect _WIRE_19, sectored_entries[0][0].data[1]
node _T_304 = bits(_WIRE_19, 0, 0)
connect _WIRE_18.fragmented_superpage, _T_304
node _T_305 = bits(_WIRE_19, 1, 1)
connect _WIRE_18.c, _T_305
node _T_306 = bits(_WIRE_19, 2, 2)
connect _WIRE_18.eff, _T_306
node _T_307 = bits(_WIRE_19, 3, 3)
connect _WIRE_18.paa, _T_307
node _T_308 = bits(_WIRE_19, 4, 4)
connect _WIRE_18.pal, _T_308
node _T_309 = bits(_WIRE_19, 5, 5)
connect _WIRE_18.ppp, _T_309
node _T_310 = bits(_WIRE_19, 6, 6)
connect _WIRE_18.pr, _T_310
node _T_311 = bits(_WIRE_19, 7, 7)
connect _WIRE_18.px, _T_311
node _T_312 = bits(_WIRE_19, 8, 8)
connect _WIRE_18.pw, _T_312
node _T_313 = bits(_WIRE_19, 9, 9)
connect _WIRE_18.hr, _T_313
node _T_314 = bits(_WIRE_19, 10, 10)
connect _WIRE_18.hx, _T_314
node _T_315 = bits(_WIRE_19, 11, 11)
connect _WIRE_18.hw, _T_315
node _T_316 = bits(_WIRE_19, 12, 12)
connect _WIRE_18.sr, _T_316
node _T_317 = bits(_WIRE_19, 13, 13)
connect _WIRE_18.sx, _T_317
node _T_318 = bits(_WIRE_19, 14, 14)
connect _WIRE_18.sw, _T_318
node _T_319 = bits(_WIRE_19, 15, 15)
connect _WIRE_18.gf, _T_319
node _T_320 = bits(_WIRE_19, 16, 16)
connect _WIRE_18.pf, _T_320
node _T_321 = bits(_WIRE_19, 17, 17)
connect _WIRE_18.ae_stage2, _T_321
node _T_322 = bits(_WIRE_19, 18, 18)
connect _WIRE_18.ae_final, _T_322
node _T_323 = bits(_WIRE_19, 19, 19)
connect _WIRE_18.ae_ptw, _T_323
node _T_324 = bits(_WIRE_19, 20, 20)
connect _WIRE_18.g, _T_324
node _T_325 = bits(_WIRE_19, 21, 21)
connect _WIRE_18.u, _T_325
node _T_326 = bits(_WIRE_19, 41, 22)
connect _WIRE_18.ppn, _T_326
wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_21 : UInt<42>
connect _WIRE_21, sectored_entries[0][0].data[2]
node _T_327 = bits(_WIRE_21, 0, 0)
connect _WIRE_20.fragmented_superpage, _T_327
node _T_328 = bits(_WIRE_21, 1, 1)
connect _WIRE_20.c, _T_328
node _T_329 = bits(_WIRE_21, 2, 2)
connect _WIRE_20.eff, _T_329
node _T_330 = bits(_WIRE_21, 3, 3)
connect _WIRE_20.paa, _T_330
node _T_331 = bits(_WIRE_21, 4, 4)
connect _WIRE_20.pal, _T_331
node _T_332 = bits(_WIRE_21, 5, 5)
connect _WIRE_20.ppp, _T_332
node _T_333 = bits(_WIRE_21, 6, 6)
connect _WIRE_20.pr, _T_333
node _T_334 = bits(_WIRE_21, 7, 7)
connect _WIRE_20.px, _T_334
node _T_335 = bits(_WIRE_21, 8, 8)
connect _WIRE_20.pw, _T_335
node _T_336 = bits(_WIRE_21, 9, 9)
connect _WIRE_20.hr, _T_336
node _T_337 = bits(_WIRE_21, 10, 10)
connect _WIRE_20.hx, _T_337
node _T_338 = bits(_WIRE_21, 11, 11)
connect _WIRE_20.hw, _T_338
node _T_339 = bits(_WIRE_21, 12, 12)
connect _WIRE_20.sr, _T_339
node _T_340 = bits(_WIRE_21, 13, 13)
connect _WIRE_20.sx, _T_340
node _T_341 = bits(_WIRE_21, 14, 14)
connect _WIRE_20.sw, _T_341
node _T_342 = bits(_WIRE_21, 15, 15)
connect _WIRE_20.gf, _T_342
node _T_343 = bits(_WIRE_21, 16, 16)
connect _WIRE_20.pf, _T_343
node _T_344 = bits(_WIRE_21, 17, 17)
connect _WIRE_20.ae_stage2, _T_344
node _T_345 = bits(_WIRE_21, 18, 18)
connect _WIRE_20.ae_final, _T_345
node _T_346 = bits(_WIRE_21, 19, 19)
connect _WIRE_20.ae_ptw, _T_346
node _T_347 = bits(_WIRE_21, 20, 20)
connect _WIRE_20.g, _T_347
node _T_348 = bits(_WIRE_21, 21, 21)
connect _WIRE_20.u, _T_348
node _T_349 = bits(_WIRE_21, 41, 22)
connect _WIRE_20.ppn, _T_349
wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_23 : UInt<42>
connect _WIRE_23, sectored_entries[0][0].data[3]
node _T_350 = bits(_WIRE_23, 0, 0)
connect _WIRE_22.fragmented_superpage, _T_350
node _T_351 = bits(_WIRE_23, 1, 1)
connect _WIRE_22.c, _T_351
node _T_352 = bits(_WIRE_23, 2, 2)
connect _WIRE_22.eff, _T_352
node _T_353 = bits(_WIRE_23, 3, 3)
connect _WIRE_22.paa, _T_353
node _T_354 = bits(_WIRE_23, 4, 4)
connect _WIRE_22.pal, _T_354
node _T_355 = bits(_WIRE_23, 5, 5)
connect _WIRE_22.ppp, _T_355
node _T_356 = bits(_WIRE_23, 6, 6)
connect _WIRE_22.pr, _T_356
node _T_357 = bits(_WIRE_23, 7, 7)
connect _WIRE_22.px, _T_357
node _T_358 = bits(_WIRE_23, 8, 8)
connect _WIRE_22.pw, _T_358
node _T_359 = bits(_WIRE_23, 9, 9)
connect _WIRE_22.hr, _T_359
node _T_360 = bits(_WIRE_23, 10, 10)
connect _WIRE_22.hx, _T_360
node _T_361 = bits(_WIRE_23, 11, 11)
connect _WIRE_22.hw, _T_361
node _T_362 = bits(_WIRE_23, 12, 12)
connect _WIRE_22.sr, _T_362
node _T_363 = bits(_WIRE_23, 13, 13)
connect _WIRE_22.sx, _T_363
node _T_364 = bits(_WIRE_23, 14, 14)
connect _WIRE_22.sw, _T_364
node _T_365 = bits(_WIRE_23, 15, 15)
connect _WIRE_22.gf, _T_365
node _T_366 = bits(_WIRE_23, 16, 16)
connect _WIRE_22.pf, _T_366
node _T_367 = bits(_WIRE_23, 17, 17)
connect _WIRE_22.ae_stage2, _T_367
node _T_368 = bits(_WIRE_23, 18, 18)
connect _WIRE_22.ae_final, _T_368
node _T_369 = bits(_WIRE_23, 19, 19)
connect _WIRE_22.ae_ptw, _T_369
node _T_370 = bits(_WIRE_23, 20, 20)
connect _WIRE_22.g, _T_370
node _T_371 = bits(_WIRE_23, 21, 21)
connect _WIRE_22.u, _T_371
node _T_372 = bits(_WIRE_23, 41, 22)
connect _WIRE_22.ppn, _T_372
node _T_373 = eq(sectored_entries[0][0].tag_v, hv)
node _T_374 = eq(_WIRE_16.g, UInt<1>(0h0))
node _T_375 = and(_T_373, _T_374)
when _T_375 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_376 = eq(sectored_entries[0][0].tag_v, hv)
node _T_377 = eq(_WIRE_18.g, UInt<1>(0h0))
node _T_378 = and(_T_376, _T_377)
when _T_378 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_379 = eq(sectored_entries[0][0].tag_v, hv)
node _T_380 = eq(_WIRE_20.g, UInt<1>(0h0))
node _T_381 = and(_T_379, _T_380)
when _T_381 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_382 = eq(sectored_entries[0][0].tag_v, hv)
node _T_383 = eq(_WIRE_22.g, UInt<1>(0h0))
node _T_384 = and(_T_382, _T_383)
when _T_384 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
else :
node _T_385 = or(hv, hg)
wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_25 : UInt<42>
connect _WIRE_25, sectored_entries[0][0].data[0]
node _T_386 = bits(_WIRE_25, 0, 0)
connect _WIRE_24.fragmented_superpage, _T_386
node _T_387 = bits(_WIRE_25, 1, 1)
connect _WIRE_24.c, _T_387
node _T_388 = bits(_WIRE_25, 2, 2)
connect _WIRE_24.eff, _T_388
node _T_389 = bits(_WIRE_25, 3, 3)
connect _WIRE_24.paa, _T_389
node _T_390 = bits(_WIRE_25, 4, 4)
connect _WIRE_24.pal, _T_390
node _T_391 = bits(_WIRE_25, 5, 5)
connect _WIRE_24.ppp, _T_391
node _T_392 = bits(_WIRE_25, 6, 6)
connect _WIRE_24.pr, _T_392
node _T_393 = bits(_WIRE_25, 7, 7)
connect _WIRE_24.px, _T_393
node _T_394 = bits(_WIRE_25, 8, 8)
connect _WIRE_24.pw, _T_394
node _T_395 = bits(_WIRE_25, 9, 9)
connect _WIRE_24.hr, _T_395
node _T_396 = bits(_WIRE_25, 10, 10)
connect _WIRE_24.hx, _T_396
node _T_397 = bits(_WIRE_25, 11, 11)
connect _WIRE_24.hw, _T_397
node _T_398 = bits(_WIRE_25, 12, 12)
connect _WIRE_24.sr, _T_398
node _T_399 = bits(_WIRE_25, 13, 13)
connect _WIRE_24.sx, _T_399
node _T_400 = bits(_WIRE_25, 14, 14)
connect _WIRE_24.sw, _T_400
node _T_401 = bits(_WIRE_25, 15, 15)
connect _WIRE_24.gf, _T_401
node _T_402 = bits(_WIRE_25, 16, 16)
connect _WIRE_24.pf, _T_402
node _T_403 = bits(_WIRE_25, 17, 17)
connect _WIRE_24.ae_stage2, _T_403
node _T_404 = bits(_WIRE_25, 18, 18)
connect _WIRE_24.ae_final, _T_404
node _T_405 = bits(_WIRE_25, 19, 19)
connect _WIRE_24.ae_ptw, _T_405
node _T_406 = bits(_WIRE_25, 20, 20)
connect _WIRE_24.g, _T_406
node _T_407 = bits(_WIRE_25, 21, 21)
connect _WIRE_24.u, _T_407
node _T_408 = bits(_WIRE_25, 41, 22)
connect _WIRE_24.ppn, _T_408
wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_27 : UInt<42>
connect _WIRE_27, sectored_entries[0][0].data[1]
node _T_409 = bits(_WIRE_27, 0, 0)
connect _WIRE_26.fragmented_superpage, _T_409
node _T_410 = bits(_WIRE_27, 1, 1)
connect _WIRE_26.c, _T_410
node _T_411 = bits(_WIRE_27, 2, 2)
connect _WIRE_26.eff, _T_411
node _T_412 = bits(_WIRE_27, 3, 3)
connect _WIRE_26.paa, _T_412
node _T_413 = bits(_WIRE_27, 4, 4)
connect _WIRE_26.pal, _T_413
node _T_414 = bits(_WIRE_27, 5, 5)
connect _WIRE_26.ppp, _T_414
node _T_415 = bits(_WIRE_27, 6, 6)
connect _WIRE_26.pr, _T_415
node _T_416 = bits(_WIRE_27, 7, 7)
connect _WIRE_26.px, _T_416
node _T_417 = bits(_WIRE_27, 8, 8)
connect _WIRE_26.pw, _T_417
node _T_418 = bits(_WIRE_27, 9, 9)
connect _WIRE_26.hr, _T_418
node _T_419 = bits(_WIRE_27, 10, 10)
connect _WIRE_26.hx, _T_419
node _T_420 = bits(_WIRE_27, 11, 11)
connect _WIRE_26.hw, _T_420
node _T_421 = bits(_WIRE_27, 12, 12)
connect _WIRE_26.sr, _T_421
node _T_422 = bits(_WIRE_27, 13, 13)
connect _WIRE_26.sx, _T_422
node _T_423 = bits(_WIRE_27, 14, 14)
connect _WIRE_26.sw, _T_423
node _T_424 = bits(_WIRE_27, 15, 15)
connect _WIRE_26.gf, _T_424
node _T_425 = bits(_WIRE_27, 16, 16)
connect _WIRE_26.pf, _T_425
node _T_426 = bits(_WIRE_27, 17, 17)
connect _WIRE_26.ae_stage2, _T_426
node _T_427 = bits(_WIRE_27, 18, 18)
connect _WIRE_26.ae_final, _T_427
node _T_428 = bits(_WIRE_27, 19, 19)
connect _WIRE_26.ae_ptw, _T_428
node _T_429 = bits(_WIRE_27, 20, 20)
connect _WIRE_26.g, _T_429
node _T_430 = bits(_WIRE_27, 21, 21)
connect _WIRE_26.u, _T_430
node _T_431 = bits(_WIRE_27, 41, 22)
connect _WIRE_26.ppn, _T_431
wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_29 : UInt<42>
connect _WIRE_29, sectored_entries[0][0].data[2]
node _T_432 = bits(_WIRE_29, 0, 0)
connect _WIRE_28.fragmented_superpage, _T_432
node _T_433 = bits(_WIRE_29, 1, 1)
connect _WIRE_28.c, _T_433
node _T_434 = bits(_WIRE_29, 2, 2)
connect _WIRE_28.eff, _T_434
node _T_435 = bits(_WIRE_29, 3, 3)
connect _WIRE_28.paa, _T_435
node _T_436 = bits(_WIRE_29, 4, 4)
connect _WIRE_28.pal, _T_436
node _T_437 = bits(_WIRE_29, 5, 5)
connect _WIRE_28.ppp, _T_437
node _T_438 = bits(_WIRE_29, 6, 6)
connect _WIRE_28.pr, _T_438
node _T_439 = bits(_WIRE_29, 7, 7)
connect _WIRE_28.px, _T_439
node _T_440 = bits(_WIRE_29, 8, 8)
connect _WIRE_28.pw, _T_440
node _T_441 = bits(_WIRE_29, 9, 9)
connect _WIRE_28.hr, _T_441
node _T_442 = bits(_WIRE_29, 10, 10)
connect _WIRE_28.hx, _T_442
node _T_443 = bits(_WIRE_29, 11, 11)
connect _WIRE_28.hw, _T_443
node _T_444 = bits(_WIRE_29, 12, 12)
connect _WIRE_28.sr, _T_444
node _T_445 = bits(_WIRE_29, 13, 13)
connect _WIRE_28.sx, _T_445
node _T_446 = bits(_WIRE_29, 14, 14)
connect _WIRE_28.sw, _T_446
node _T_447 = bits(_WIRE_29, 15, 15)
connect _WIRE_28.gf, _T_447
node _T_448 = bits(_WIRE_29, 16, 16)
connect _WIRE_28.pf, _T_448
node _T_449 = bits(_WIRE_29, 17, 17)
connect _WIRE_28.ae_stage2, _T_449
node _T_450 = bits(_WIRE_29, 18, 18)
connect _WIRE_28.ae_final, _T_450
node _T_451 = bits(_WIRE_29, 19, 19)
connect _WIRE_28.ae_ptw, _T_451
node _T_452 = bits(_WIRE_29, 20, 20)
connect _WIRE_28.g, _T_452
node _T_453 = bits(_WIRE_29, 21, 21)
connect _WIRE_28.u, _T_453
node _T_454 = bits(_WIRE_29, 41, 22)
connect _WIRE_28.ppn, _T_454
wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_31 : UInt<42>
connect _WIRE_31, sectored_entries[0][0].data[3]
node _T_455 = bits(_WIRE_31, 0, 0)
connect _WIRE_30.fragmented_superpage, _T_455
node _T_456 = bits(_WIRE_31, 1, 1)
connect _WIRE_30.c, _T_456
node _T_457 = bits(_WIRE_31, 2, 2)
connect _WIRE_30.eff, _T_457
node _T_458 = bits(_WIRE_31, 3, 3)
connect _WIRE_30.paa, _T_458
node _T_459 = bits(_WIRE_31, 4, 4)
connect _WIRE_30.pal, _T_459
node _T_460 = bits(_WIRE_31, 5, 5)
connect _WIRE_30.ppp, _T_460
node _T_461 = bits(_WIRE_31, 6, 6)
connect _WIRE_30.pr, _T_461
node _T_462 = bits(_WIRE_31, 7, 7)
connect _WIRE_30.px, _T_462
node _T_463 = bits(_WIRE_31, 8, 8)
connect _WIRE_30.pw, _T_463
node _T_464 = bits(_WIRE_31, 9, 9)
connect _WIRE_30.hr, _T_464
node _T_465 = bits(_WIRE_31, 10, 10)
connect _WIRE_30.hx, _T_465
node _T_466 = bits(_WIRE_31, 11, 11)
connect _WIRE_30.hw, _T_466
node _T_467 = bits(_WIRE_31, 12, 12)
connect _WIRE_30.sr, _T_467
node _T_468 = bits(_WIRE_31, 13, 13)
connect _WIRE_30.sx, _T_468
node _T_469 = bits(_WIRE_31, 14, 14)
connect _WIRE_30.sw, _T_469
node _T_470 = bits(_WIRE_31, 15, 15)
connect _WIRE_30.gf, _T_470
node _T_471 = bits(_WIRE_31, 16, 16)
connect _WIRE_30.pf, _T_471
node _T_472 = bits(_WIRE_31, 17, 17)
connect _WIRE_30.ae_stage2, _T_472
node _T_473 = bits(_WIRE_31, 18, 18)
connect _WIRE_30.ae_final, _T_473
node _T_474 = bits(_WIRE_31, 19, 19)
connect _WIRE_30.ae_ptw, _T_474
node _T_475 = bits(_WIRE_31, 20, 20)
connect _WIRE_30.g, _T_475
node _T_476 = bits(_WIRE_31, 21, 21)
connect _WIRE_30.u, _T_476
node _T_477 = bits(_WIRE_31, 41, 22)
connect _WIRE_30.ppn, _T_477
node _T_478 = eq(sectored_entries[0][0].tag_v, _T_385)
when _T_478 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_479 = eq(sectored_entries[0][0].tag_v, _T_385)
when _T_479 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_480 = eq(sectored_entries[0][0].tag_v, _T_385)
when _T_480 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_481 = eq(sectored_entries[0][0].tag_v, _T_385)
when _T_481 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
node hv_1 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_1 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_482 = eq(hg_1, UInt<1>(0h0))
node _T_483 = and(_T_482, io.sfence.bits.rs1)
when _T_483 :
node _T_484 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _T_485 = shr(_T_484, 2)
node _T_486 = eq(_T_485, UInt<1>(0h0))
node _T_487 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_488 = and(_T_486, _T_487)
when _T_488 :
wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_33 : UInt<42>
connect _WIRE_33, sectored_entries[0][1].data[0]
node _T_489 = bits(_WIRE_33, 0, 0)
connect _WIRE_32.fragmented_superpage, _T_489
node _T_490 = bits(_WIRE_33, 1, 1)
connect _WIRE_32.c, _T_490
node _T_491 = bits(_WIRE_33, 2, 2)
connect _WIRE_32.eff, _T_491
node _T_492 = bits(_WIRE_33, 3, 3)
connect _WIRE_32.paa, _T_492
node _T_493 = bits(_WIRE_33, 4, 4)
connect _WIRE_32.pal, _T_493
node _T_494 = bits(_WIRE_33, 5, 5)
connect _WIRE_32.ppp, _T_494
node _T_495 = bits(_WIRE_33, 6, 6)
connect _WIRE_32.pr, _T_495
node _T_496 = bits(_WIRE_33, 7, 7)
connect _WIRE_32.px, _T_496
node _T_497 = bits(_WIRE_33, 8, 8)
connect _WIRE_32.pw, _T_497
node _T_498 = bits(_WIRE_33, 9, 9)
connect _WIRE_32.hr, _T_498
node _T_499 = bits(_WIRE_33, 10, 10)
connect _WIRE_32.hx, _T_499
node _T_500 = bits(_WIRE_33, 11, 11)
connect _WIRE_32.hw, _T_500
node _T_501 = bits(_WIRE_33, 12, 12)
connect _WIRE_32.sr, _T_501
node _T_502 = bits(_WIRE_33, 13, 13)
connect _WIRE_32.sx, _T_502
node _T_503 = bits(_WIRE_33, 14, 14)
connect _WIRE_32.sw, _T_503
node _T_504 = bits(_WIRE_33, 15, 15)
connect _WIRE_32.gf, _T_504
node _T_505 = bits(_WIRE_33, 16, 16)
connect _WIRE_32.pf, _T_505
node _T_506 = bits(_WIRE_33, 17, 17)
connect _WIRE_32.ae_stage2, _T_506
node _T_507 = bits(_WIRE_33, 18, 18)
connect _WIRE_32.ae_final, _T_507
node _T_508 = bits(_WIRE_33, 19, 19)
connect _WIRE_32.ae_ptw, _T_508
node _T_509 = bits(_WIRE_33, 20, 20)
connect _WIRE_32.g, _T_509
node _T_510 = bits(_WIRE_33, 21, 21)
connect _WIRE_32.u, _T_510
node _T_511 = bits(_WIRE_33, 41, 22)
connect _WIRE_32.ppn, _T_511
wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_35 : UInt<42>
connect _WIRE_35, sectored_entries[0][1].data[1]
node _T_512 = bits(_WIRE_35, 0, 0)
connect _WIRE_34.fragmented_superpage, _T_512
node _T_513 = bits(_WIRE_35, 1, 1)
connect _WIRE_34.c, _T_513
node _T_514 = bits(_WIRE_35, 2, 2)
connect _WIRE_34.eff, _T_514
node _T_515 = bits(_WIRE_35, 3, 3)
connect _WIRE_34.paa, _T_515
node _T_516 = bits(_WIRE_35, 4, 4)
connect _WIRE_34.pal, _T_516
node _T_517 = bits(_WIRE_35, 5, 5)
connect _WIRE_34.ppp, _T_517
node _T_518 = bits(_WIRE_35, 6, 6)
connect _WIRE_34.pr, _T_518
node _T_519 = bits(_WIRE_35, 7, 7)
connect _WIRE_34.px, _T_519
node _T_520 = bits(_WIRE_35, 8, 8)
connect _WIRE_34.pw, _T_520
node _T_521 = bits(_WIRE_35, 9, 9)
connect _WIRE_34.hr, _T_521
node _T_522 = bits(_WIRE_35, 10, 10)
connect _WIRE_34.hx, _T_522
node _T_523 = bits(_WIRE_35, 11, 11)
connect _WIRE_34.hw, _T_523
node _T_524 = bits(_WIRE_35, 12, 12)
connect _WIRE_34.sr, _T_524
node _T_525 = bits(_WIRE_35, 13, 13)
connect _WIRE_34.sx, _T_525
node _T_526 = bits(_WIRE_35, 14, 14)
connect _WIRE_34.sw, _T_526
node _T_527 = bits(_WIRE_35, 15, 15)
connect _WIRE_34.gf, _T_527
node _T_528 = bits(_WIRE_35, 16, 16)
connect _WIRE_34.pf, _T_528
node _T_529 = bits(_WIRE_35, 17, 17)
connect _WIRE_34.ae_stage2, _T_529
node _T_530 = bits(_WIRE_35, 18, 18)
connect _WIRE_34.ae_final, _T_530
node _T_531 = bits(_WIRE_35, 19, 19)
connect _WIRE_34.ae_ptw, _T_531
node _T_532 = bits(_WIRE_35, 20, 20)
connect _WIRE_34.g, _T_532
node _T_533 = bits(_WIRE_35, 21, 21)
connect _WIRE_34.u, _T_533
node _T_534 = bits(_WIRE_35, 41, 22)
connect _WIRE_34.ppn, _T_534
wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_37 : UInt<42>
connect _WIRE_37, sectored_entries[0][1].data[2]
node _T_535 = bits(_WIRE_37, 0, 0)
connect _WIRE_36.fragmented_superpage, _T_535
node _T_536 = bits(_WIRE_37, 1, 1)
connect _WIRE_36.c, _T_536
node _T_537 = bits(_WIRE_37, 2, 2)
connect _WIRE_36.eff, _T_537
node _T_538 = bits(_WIRE_37, 3, 3)
connect _WIRE_36.paa, _T_538
node _T_539 = bits(_WIRE_37, 4, 4)
connect _WIRE_36.pal, _T_539
node _T_540 = bits(_WIRE_37, 5, 5)
connect _WIRE_36.ppp, _T_540
node _T_541 = bits(_WIRE_37, 6, 6)
connect _WIRE_36.pr, _T_541
node _T_542 = bits(_WIRE_37, 7, 7)
connect _WIRE_36.px, _T_542
node _T_543 = bits(_WIRE_37, 8, 8)
connect _WIRE_36.pw, _T_543
node _T_544 = bits(_WIRE_37, 9, 9)
connect _WIRE_36.hr, _T_544
node _T_545 = bits(_WIRE_37, 10, 10)
connect _WIRE_36.hx, _T_545
node _T_546 = bits(_WIRE_37, 11, 11)
connect _WIRE_36.hw, _T_546
node _T_547 = bits(_WIRE_37, 12, 12)
connect _WIRE_36.sr, _T_547
node _T_548 = bits(_WIRE_37, 13, 13)
connect _WIRE_36.sx, _T_548
node _T_549 = bits(_WIRE_37, 14, 14)
connect _WIRE_36.sw, _T_549
node _T_550 = bits(_WIRE_37, 15, 15)
connect _WIRE_36.gf, _T_550
node _T_551 = bits(_WIRE_37, 16, 16)
connect _WIRE_36.pf, _T_551
node _T_552 = bits(_WIRE_37, 17, 17)
connect _WIRE_36.ae_stage2, _T_552
node _T_553 = bits(_WIRE_37, 18, 18)
connect _WIRE_36.ae_final, _T_553
node _T_554 = bits(_WIRE_37, 19, 19)
connect _WIRE_36.ae_ptw, _T_554
node _T_555 = bits(_WIRE_37, 20, 20)
connect _WIRE_36.g, _T_555
node _T_556 = bits(_WIRE_37, 21, 21)
connect _WIRE_36.u, _T_556
node _T_557 = bits(_WIRE_37, 41, 22)
connect _WIRE_36.ppn, _T_557
wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_39 : UInt<42>
connect _WIRE_39, sectored_entries[0][1].data[3]
node _T_558 = bits(_WIRE_39, 0, 0)
connect _WIRE_38.fragmented_superpage, _T_558
node _T_559 = bits(_WIRE_39, 1, 1)
connect _WIRE_38.c, _T_559
node _T_560 = bits(_WIRE_39, 2, 2)
connect _WIRE_38.eff, _T_560
node _T_561 = bits(_WIRE_39, 3, 3)
connect _WIRE_38.paa, _T_561
node _T_562 = bits(_WIRE_39, 4, 4)
connect _WIRE_38.pal, _T_562
node _T_563 = bits(_WIRE_39, 5, 5)
connect _WIRE_38.ppp, _T_563
node _T_564 = bits(_WIRE_39, 6, 6)
connect _WIRE_38.pr, _T_564
node _T_565 = bits(_WIRE_39, 7, 7)
connect _WIRE_38.px, _T_565
node _T_566 = bits(_WIRE_39, 8, 8)
connect _WIRE_38.pw, _T_566
node _T_567 = bits(_WIRE_39, 9, 9)
connect _WIRE_38.hr, _T_567
node _T_568 = bits(_WIRE_39, 10, 10)
connect _WIRE_38.hx, _T_568
node _T_569 = bits(_WIRE_39, 11, 11)
connect _WIRE_38.hw, _T_569
node _T_570 = bits(_WIRE_39, 12, 12)
connect _WIRE_38.sr, _T_570
node _T_571 = bits(_WIRE_39, 13, 13)
connect _WIRE_38.sx, _T_571
node _T_572 = bits(_WIRE_39, 14, 14)
connect _WIRE_38.sw, _T_572
node _T_573 = bits(_WIRE_39, 15, 15)
connect _WIRE_38.gf, _T_573
node _T_574 = bits(_WIRE_39, 16, 16)
connect _WIRE_38.pf, _T_574
node _T_575 = bits(_WIRE_39, 17, 17)
connect _WIRE_38.ae_stage2, _T_575
node _T_576 = bits(_WIRE_39, 18, 18)
connect _WIRE_38.ae_final, _T_576
node _T_577 = bits(_WIRE_39, 19, 19)
connect _WIRE_38.ae_ptw, _T_577
node _T_578 = bits(_WIRE_39, 20, 20)
connect _WIRE_38.g, _T_578
node _T_579 = bits(_WIRE_39, 21, 21)
connect _WIRE_38.u, _T_579
node _T_580 = bits(_WIRE_39, 41, 22)
connect _WIRE_38.ppn, _T_580
node _T_581 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_582 = bits(vpn, 1, 0)
node _T_583 = eq(UInt<1>(0h0), _T_582)
node _T_584 = and(_T_581, _T_583)
when _T_584 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_585 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_586 = bits(vpn, 1, 0)
node _T_587 = eq(UInt<1>(0h1), _T_586)
node _T_588 = and(_T_585, _T_587)
when _T_588 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_589 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_590 = bits(vpn, 1, 0)
node _T_591 = eq(UInt<2>(0h2), _T_590)
node _T_592 = and(_T_589, _T_591)
when _T_592 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_593 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_594 = bits(vpn, 1, 0)
node _T_595 = eq(UInt<2>(0h3), _T_594)
node _T_596 = and(_T_593, _T_595)
when _T_596 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
node _T_597 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _T_598 = shr(_T_597, 18)
node _T_599 = eq(_T_598, UInt<1>(0h0))
when _T_599 :
wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_41 : UInt<42>
connect _WIRE_41, sectored_entries[0][1].data[0]
node _T_600 = bits(_WIRE_41, 0, 0)
connect _WIRE_40.fragmented_superpage, _T_600
node _T_601 = bits(_WIRE_41, 1, 1)
connect _WIRE_40.c, _T_601
node _T_602 = bits(_WIRE_41, 2, 2)
connect _WIRE_40.eff, _T_602
node _T_603 = bits(_WIRE_41, 3, 3)
connect _WIRE_40.paa, _T_603
node _T_604 = bits(_WIRE_41, 4, 4)
connect _WIRE_40.pal, _T_604
node _T_605 = bits(_WIRE_41, 5, 5)
connect _WIRE_40.ppp, _T_605
node _T_606 = bits(_WIRE_41, 6, 6)
connect _WIRE_40.pr, _T_606
node _T_607 = bits(_WIRE_41, 7, 7)
connect _WIRE_40.px, _T_607
node _T_608 = bits(_WIRE_41, 8, 8)
connect _WIRE_40.pw, _T_608
node _T_609 = bits(_WIRE_41, 9, 9)
connect _WIRE_40.hr, _T_609
node _T_610 = bits(_WIRE_41, 10, 10)
connect _WIRE_40.hx, _T_610
node _T_611 = bits(_WIRE_41, 11, 11)
connect _WIRE_40.hw, _T_611
node _T_612 = bits(_WIRE_41, 12, 12)
connect _WIRE_40.sr, _T_612
node _T_613 = bits(_WIRE_41, 13, 13)
connect _WIRE_40.sx, _T_613
node _T_614 = bits(_WIRE_41, 14, 14)
connect _WIRE_40.sw, _T_614
node _T_615 = bits(_WIRE_41, 15, 15)
connect _WIRE_40.gf, _T_615
node _T_616 = bits(_WIRE_41, 16, 16)
connect _WIRE_40.pf, _T_616
node _T_617 = bits(_WIRE_41, 17, 17)
connect _WIRE_40.ae_stage2, _T_617
node _T_618 = bits(_WIRE_41, 18, 18)
connect _WIRE_40.ae_final, _T_618
node _T_619 = bits(_WIRE_41, 19, 19)
connect _WIRE_40.ae_ptw, _T_619
node _T_620 = bits(_WIRE_41, 20, 20)
connect _WIRE_40.g, _T_620
node _T_621 = bits(_WIRE_41, 21, 21)
connect _WIRE_40.u, _T_621
node _T_622 = bits(_WIRE_41, 41, 22)
connect _WIRE_40.ppn, _T_622
wire _WIRE_42 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_43 : UInt<42>
connect _WIRE_43, sectored_entries[0][1].data[1]
node _T_623 = bits(_WIRE_43, 0, 0)
connect _WIRE_42.fragmented_superpage, _T_623
node _T_624 = bits(_WIRE_43, 1, 1)
connect _WIRE_42.c, _T_624
node _T_625 = bits(_WIRE_43, 2, 2)
connect _WIRE_42.eff, _T_625
node _T_626 = bits(_WIRE_43, 3, 3)
connect _WIRE_42.paa, _T_626
node _T_627 = bits(_WIRE_43, 4, 4)
connect _WIRE_42.pal, _T_627
node _T_628 = bits(_WIRE_43, 5, 5)
connect _WIRE_42.ppp, _T_628
node _T_629 = bits(_WIRE_43, 6, 6)
connect _WIRE_42.pr, _T_629
node _T_630 = bits(_WIRE_43, 7, 7)
connect _WIRE_42.px, _T_630
node _T_631 = bits(_WIRE_43, 8, 8)
connect _WIRE_42.pw, _T_631
node _T_632 = bits(_WIRE_43, 9, 9)
connect _WIRE_42.hr, _T_632
node _T_633 = bits(_WIRE_43, 10, 10)
connect _WIRE_42.hx, _T_633
node _T_634 = bits(_WIRE_43, 11, 11)
connect _WIRE_42.hw, _T_634
node _T_635 = bits(_WIRE_43, 12, 12)
connect _WIRE_42.sr, _T_635
node _T_636 = bits(_WIRE_43, 13, 13)
connect _WIRE_42.sx, _T_636
node _T_637 = bits(_WIRE_43, 14, 14)
connect _WIRE_42.sw, _T_637
node _T_638 = bits(_WIRE_43, 15, 15)
connect _WIRE_42.gf, _T_638
node _T_639 = bits(_WIRE_43, 16, 16)
connect _WIRE_42.pf, _T_639
node _T_640 = bits(_WIRE_43, 17, 17)
connect _WIRE_42.ae_stage2, _T_640
node _T_641 = bits(_WIRE_43, 18, 18)
connect _WIRE_42.ae_final, _T_641
node _T_642 = bits(_WIRE_43, 19, 19)
connect _WIRE_42.ae_ptw, _T_642
node _T_643 = bits(_WIRE_43, 20, 20)
connect _WIRE_42.g, _T_643
node _T_644 = bits(_WIRE_43, 21, 21)
connect _WIRE_42.u, _T_644
node _T_645 = bits(_WIRE_43, 41, 22)
connect _WIRE_42.ppn, _T_645
wire _WIRE_44 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_45 : UInt<42>
connect _WIRE_45, sectored_entries[0][1].data[2]
node _T_646 = bits(_WIRE_45, 0, 0)
connect _WIRE_44.fragmented_superpage, _T_646
node _T_647 = bits(_WIRE_45, 1, 1)
connect _WIRE_44.c, _T_647
node _T_648 = bits(_WIRE_45, 2, 2)
connect _WIRE_44.eff, _T_648
node _T_649 = bits(_WIRE_45, 3, 3)
connect _WIRE_44.paa, _T_649
node _T_650 = bits(_WIRE_45, 4, 4)
connect _WIRE_44.pal, _T_650
node _T_651 = bits(_WIRE_45, 5, 5)
connect _WIRE_44.ppp, _T_651
node _T_652 = bits(_WIRE_45, 6, 6)
connect _WIRE_44.pr, _T_652
node _T_653 = bits(_WIRE_45, 7, 7)
connect _WIRE_44.px, _T_653
node _T_654 = bits(_WIRE_45, 8, 8)
connect _WIRE_44.pw, _T_654
node _T_655 = bits(_WIRE_45, 9, 9)
connect _WIRE_44.hr, _T_655
node _T_656 = bits(_WIRE_45, 10, 10)
connect _WIRE_44.hx, _T_656
node _T_657 = bits(_WIRE_45, 11, 11)
connect _WIRE_44.hw, _T_657
node _T_658 = bits(_WIRE_45, 12, 12)
connect _WIRE_44.sr, _T_658
node _T_659 = bits(_WIRE_45, 13, 13)
connect _WIRE_44.sx, _T_659
node _T_660 = bits(_WIRE_45, 14, 14)
connect _WIRE_44.sw, _T_660
node _T_661 = bits(_WIRE_45, 15, 15)
connect _WIRE_44.gf, _T_661
node _T_662 = bits(_WIRE_45, 16, 16)
connect _WIRE_44.pf, _T_662
node _T_663 = bits(_WIRE_45, 17, 17)
connect _WIRE_44.ae_stage2, _T_663
node _T_664 = bits(_WIRE_45, 18, 18)
connect _WIRE_44.ae_final, _T_664
node _T_665 = bits(_WIRE_45, 19, 19)
connect _WIRE_44.ae_ptw, _T_665
node _T_666 = bits(_WIRE_45, 20, 20)
connect _WIRE_44.g, _T_666
node _T_667 = bits(_WIRE_45, 21, 21)
connect _WIRE_44.u, _T_667
node _T_668 = bits(_WIRE_45, 41, 22)
connect _WIRE_44.ppn, _T_668
wire _WIRE_46 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_47 : UInt<42>
connect _WIRE_47, sectored_entries[0][1].data[3]
node _T_669 = bits(_WIRE_47, 0, 0)
connect _WIRE_46.fragmented_superpage, _T_669
node _T_670 = bits(_WIRE_47, 1, 1)
connect _WIRE_46.c, _T_670
node _T_671 = bits(_WIRE_47, 2, 2)
connect _WIRE_46.eff, _T_671
node _T_672 = bits(_WIRE_47, 3, 3)
connect _WIRE_46.paa, _T_672
node _T_673 = bits(_WIRE_47, 4, 4)
connect _WIRE_46.pal, _T_673
node _T_674 = bits(_WIRE_47, 5, 5)
connect _WIRE_46.ppp, _T_674
node _T_675 = bits(_WIRE_47, 6, 6)
connect _WIRE_46.pr, _T_675
node _T_676 = bits(_WIRE_47, 7, 7)
connect _WIRE_46.px, _T_676
node _T_677 = bits(_WIRE_47, 8, 8)
connect _WIRE_46.pw, _T_677
node _T_678 = bits(_WIRE_47, 9, 9)
connect _WIRE_46.hr, _T_678
node _T_679 = bits(_WIRE_47, 10, 10)
connect _WIRE_46.hx, _T_679
node _T_680 = bits(_WIRE_47, 11, 11)
connect _WIRE_46.hw, _T_680
node _T_681 = bits(_WIRE_47, 12, 12)
connect _WIRE_46.sr, _T_681
node _T_682 = bits(_WIRE_47, 13, 13)
connect _WIRE_46.sx, _T_682
node _T_683 = bits(_WIRE_47, 14, 14)
connect _WIRE_46.sw, _T_683
node _T_684 = bits(_WIRE_47, 15, 15)
connect _WIRE_46.gf, _T_684
node _T_685 = bits(_WIRE_47, 16, 16)
connect _WIRE_46.pf, _T_685
node _T_686 = bits(_WIRE_47, 17, 17)
connect _WIRE_46.ae_stage2, _T_686
node _T_687 = bits(_WIRE_47, 18, 18)
connect _WIRE_46.ae_final, _T_687
node _T_688 = bits(_WIRE_47, 19, 19)
connect _WIRE_46.ae_ptw, _T_688
node _T_689 = bits(_WIRE_47, 20, 20)
connect _WIRE_46.g, _T_689
node _T_690 = bits(_WIRE_47, 21, 21)
connect _WIRE_46.u, _T_690
node _T_691 = bits(_WIRE_47, 41, 22)
connect _WIRE_46.ppn, _T_691
node _T_692 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_693 = and(_T_692, _WIRE_40.fragmented_superpage)
when _T_693 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_694 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_695 = and(_T_694, _WIRE_42.fragmented_superpage)
when _T_695 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_696 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_697 = and(_T_696, _WIRE_44.fragmented_superpage)
when _T_697 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_698 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_699 = and(_T_698, _WIRE_46.fragmented_superpage)
when _T_699 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
else :
node _T_700 = eq(hg_1, UInt<1>(0h0))
node _T_701 = and(_T_700, io.sfence.bits.rs2)
when _T_701 :
wire _WIRE_48 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_49 : UInt<42>
connect _WIRE_49, sectored_entries[0][1].data[0]
node _T_702 = bits(_WIRE_49, 0, 0)
connect _WIRE_48.fragmented_superpage, _T_702
node _T_703 = bits(_WIRE_49, 1, 1)
connect _WIRE_48.c, _T_703
node _T_704 = bits(_WIRE_49, 2, 2)
connect _WIRE_48.eff, _T_704
node _T_705 = bits(_WIRE_49, 3, 3)
connect _WIRE_48.paa, _T_705
node _T_706 = bits(_WIRE_49, 4, 4)
connect _WIRE_48.pal, _T_706
node _T_707 = bits(_WIRE_49, 5, 5)
connect _WIRE_48.ppp, _T_707
node _T_708 = bits(_WIRE_49, 6, 6)
connect _WIRE_48.pr, _T_708
node _T_709 = bits(_WIRE_49, 7, 7)
connect _WIRE_48.px, _T_709
node _T_710 = bits(_WIRE_49, 8, 8)
connect _WIRE_48.pw, _T_710
node _T_711 = bits(_WIRE_49, 9, 9)
connect _WIRE_48.hr, _T_711
node _T_712 = bits(_WIRE_49, 10, 10)
connect _WIRE_48.hx, _T_712
node _T_713 = bits(_WIRE_49, 11, 11)
connect _WIRE_48.hw, _T_713
node _T_714 = bits(_WIRE_49, 12, 12)
connect _WIRE_48.sr, _T_714
node _T_715 = bits(_WIRE_49, 13, 13)
connect _WIRE_48.sx, _T_715
node _T_716 = bits(_WIRE_49, 14, 14)
connect _WIRE_48.sw, _T_716
node _T_717 = bits(_WIRE_49, 15, 15)
connect _WIRE_48.gf, _T_717
node _T_718 = bits(_WIRE_49, 16, 16)
connect _WIRE_48.pf, _T_718
node _T_719 = bits(_WIRE_49, 17, 17)
connect _WIRE_48.ae_stage2, _T_719
node _T_720 = bits(_WIRE_49, 18, 18)
connect _WIRE_48.ae_final, _T_720
node _T_721 = bits(_WIRE_49, 19, 19)
connect _WIRE_48.ae_ptw, _T_721
node _T_722 = bits(_WIRE_49, 20, 20)
connect _WIRE_48.g, _T_722
node _T_723 = bits(_WIRE_49, 21, 21)
connect _WIRE_48.u, _T_723
node _T_724 = bits(_WIRE_49, 41, 22)
connect _WIRE_48.ppn, _T_724
wire _WIRE_50 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_51 : UInt<42>
connect _WIRE_51, sectored_entries[0][1].data[1]
node _T_725 = bits(_WIRE_51, 0, 0)
connect _WIRE_50.fragmented_superpage, _T_725
node _T_726 = bits(_WIRE_51, 1, 1)
connect _WIRE_50.c, _T_726
node _T_727 = bits(_WIRE_51, 2, 2)
connect _WIRE_50.eff, _T_727
node _T_728 = bits(_WIRE_51, 3, 3)
connect _WIRE_50.paa, _T_728
node _T_729 = bits(_WIRE_51, 4, 4)
connect _WIRE_50.pal, _T_729
node _T_730 = bits(_WIRE_51, 5, 5)
connect _WIRE_50.ppp, _T_730
node _T_731 = bits(_WIRE_51, 6, 6)
connect _WIRE_50.pr, _T_731
node _T_732 = bits(_WIRE_51, 7, 7)
connect _WIRE_50.px, _T_732
node _T_733 = bits(_WIRE_51, 8, 8)
connect _WIRE_50.pw, _T_733
node _T_734 = bits(_WIRE_51, 9, 9)
connect _WIRE_50.hr, _T_734
node _T_735 = bits(_WIRE_51, 10, 10)
connect _WIRE_50.hx, _T_735
node _T_736 = bits(_WIRE_51, 11, 11)
connect _WIRE_50.hw, _T_736
node _T_737 = bits(_WIRE_51, 12, 12)
connect _WIRE_50.sr, _T_737
node _T_738 = bits(_WIRE_51, 13, 13)
connect _WIRE_50.sx, _T_738
node _T_739 = bits(_WIRE_51, 14, 14)
connect _WIRE_50.sw, _T_739
node _T_740 = bits(_WIRE_51, 15, 15)
connect _WIRE_50.gf, _T_740
node _T_741 = bits(_WIRE_51, 16, 16)
connect _WIRE_50.pf, _T_741
node _T_742 = bits(_WIRE_51, 17, 17)
connect _WIRE_50.ae_stage2, _T_742
node _T_743 = bits(_WIRE_51, 18, 18)
connect _WIRE_50.ae_final, _T_743
node _T_744 = bits(_WIRE_51, 19, 19)
connect _WIRE_50.ae_ptw, _T_744
node _T_745 = bits(_WIRE_51, 20, 20)
connect _WIRE_50.g, _T_745
node _T_746 = bits(_WIRE_51, 21, 21)
connect _WIRE_50.u, _T_746
node _T_747 = bits(_WIRE_51, 41, 22)
connect _WIRE_50.ppn, _T_747
wire _WIRE_52 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_53 : UInt<42>
connect _WIRE_53, sectored_entries[0][1].data[2]
node _T_748 = bits(_WIRE_53, 0, 0)
connect _WIRE_52.fragmented_superpage, _T_748
node _T_749 = bits(_WIRE_53, 1, 1)
connect _WIRE_52.c, _T_749
node _T_750 = bits(_WIRE_53, 2, 2)
connect _WIRE_52.eff, _T_750
node _T_751 = bits(_WIRE_53, 3, 3)
connect _WIRE_52.paa, _T_751
node _T_752 = bits(_WIRE_53, 4, 4)
connect _WIRE_52.pal, _T_752
node _T_753 = bits(_WIRE_53, 5, 5)
connect _WIRE_52.ppp, _T_753
node _T_754 = bits(_WIRE_53, 6, 6)
connect _WIRE_52.pr, _T_754
node _T_755 = bits(_WIRE_53, 7, 7)
connect _WIRE_52.px, _T_755
node _T_756 = bits(_WIRE_53, 8, 8)
connect _WIRE_52.pw, _T_756
node _T_757 = bits(_WIRE_53, 9, 9)
connect _WIRE_52.hr, _T_757
node _T_758 = bits(_WIRE_53, 10, 10)
connect _WIRE_52.hx, _T_758
node _T_759 = bits(_WIRE_53, 11, 11)
connect _WIRE_52.hw, _T_759
node _T_760 = bits(_WIRE_53, 12, 12)
connect _WIRE_52.sr, _T_760
node _T_761 = bits(_WIRE_53, 13, 13)
connect _WIRE_52.sx, _T_761
node _T_762 = bits(_WIRE_53, 14, 14)
connect _WIRE_52.sw, _T_762
node _T_763 = bits(_WIRE_53, 15, 15)
connect _WIRE_52.gf, _T_763
node _T_764 = bits(_WIRE_53, 16, 16)
connect _WIRE_52.pf, _T_764
node _T_765 = bits(_WIRE_53, 17, 17)
connect _WIRE_52.ae_stage2, _T_765
node _T_766 = bits(_WIRE_53, 18, 18)
connect _WIRE_52.ae_final, _T_766
node _T_767 = bits(_WIRE_53, 19, 19)
connect _WIRE_52.ae_ptw, _T_767
node _T_768 = bits(_WIRE_53, 20, 20)
connect _WIRE_52.g, _T_768
node _T_769 = bits(_WIRE_53, 21, 21)
connect _WIRE_52.u, _T_769
node _T_770 = bits(_WIRE_53, 41, 22)
connect _WIRE_52.ppn, _T_770
wire _WIRE_54 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_55 : UInt<42>
connect _WIRE_55, sectored_entries[0][1].data[3]
node _T_771 = bits(_WIRE_55, 0, 0)
connect _WIRE_54.fragmented_superpage, _T_771
node _T_772 = bits(_WIRE_55, 1, 1)
connect _WIRE_54.c, _T_772
node _T_773 = bits(_WIRE_55, 2, 2)
connect _WIRE_54.eff, _T_773
node _T_774 = bits(_WIRE_55, 3, 3)
connect _WIRE_54.paa, _T_774
node _T_775 = bits(_WIRE_55, 4, 4)
connect _WIRE_54.pal, _T_775
node _T_776 = bits(_WIRE_55, 5, 5)
connect _WIRE_54.ppp, _T_776
node _T_777 = bits(_WIRE_55, 6, 6)
connect _WIRE_54.pr, _T_777
node _T_778 = bits(_WIRE_55, 7, 7)
connect _WIRE_54.px, _T_778
node _T_779 = bits(_WIRE_55, 8, 8)
connect _WIRE_54.pw, _T_779
node _T_780 = bits(_WIRE_55, 9, 9)
connect _WIRE_54.hr, _T_780
node _T_781 = bits(_WIRE_55, 10, 10)
connect _WIRE_54.hx, _T_781
node _T_782 = bits(_WIRE_55, 11, 11)
connect _WIRE_54.hw, _T_782
node _T_783 = bits(_WIRE_55, 12, 12)
connect _WIRE_54.sr, _T_783
node _T_784 = bits(_WIRE_55, 13, 13)
connect _WIRE_54.sx, _T_784
node _T_785 = bits(_WIRE_55, 14, 14)
connect _WIRE_54.sw, _T_785
node _T_786 = bits(_WIRE_55, 15, 15)
connect _WIRE_54.gf, _T_786
node _T_787 = bits(_WIRE_55, 16, 16)
connect _WIRE_54.pf, _T_787
node _T_788 = bits(_WIRE_55, 17, 17)
connect _WIRE_54.ae_stage2, _T_788
node _T_789 = bits(_WIRE_55, 18, 18)
connect _WIRE_54.ae_final, _T_789
node _T_790 = bits(_WIRE_55, 19, 19)
connect _WIRE_54.ae_ptw, _T_790
node _T_791 = bits(_WIRE_55, 20, 20)
connect _WIRE_54.g, _T_791
node _T_792 = bits(_WIRE_55, 21, 21)
connect _WIRE_54.u, _T_792
node _T_793 = bits(_WIRE_55, 41, 22)
connect _WIRE_54.ppn, _T_793
node _T_794 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_795 = eq(_WIRE_48.g, UInt<1>(0h0))
node _T_796 = and(_T_794, _T_795)
when _T_796 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_797 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_798 = eq(_WIRE_50.g, UInt<1>(0h0))
node _T_799 = and(_T_797, _T_798)
when _T_799 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_800 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_801 = eq(_WIRE_52.g, UInt<1>(0h0))
node _T_802 = and(_T_800, _T_801)
when _T_802 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_803 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_804 = eq(_WIRE_54.g, UInt<1>(0h0))
node _T_805 = and(_T_803, _T_804)
when _T_805 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
else :
node _T_806 = or(hv_1, hg_1)
wire _WIRE_56 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_57 : UInt<42>
connect _WIRE_57, sectored_entries[0][1].data[0]
node _T_807 = bits(_WIRE_57, 0, 0)
connect _WIRE_56.fragmented_superpage, _T_807
node _T_808 = bits(_WIRE_57, 1, 1)
connect _WIRE_56.c, _T_808
node _T_809 = bits(_WIRE_57, 2, 2)
connect _WIRE_56.eff, _T_809
node _T_810 = bits(_WIRE_57, 3, 3)
connect _WIRE_56.paa, _T_810
node _T_811 = bits(_WIRE_57, 4, 4)
connect _WIRE_56.pal, _T_811
node _T_812 = bits(_WIRE_57, 5, 5)
connect _WIRE_56.ppp, _T_812
node _T_813 = bits(_WIRE_57, 6, 6)
connect _WIRE_56.pr, _T_813
node _T_814 = bits(_WIRE_57, 7, 7)
connect _WIRE_56.px, _T_814
node _T_815 = bits(_WIRE_57, 8, 8)
connect _WIRE_56.pw, _T_815
node _T_816 = bits(_WIRE_57, 9, 9)
connect _WIRE_56.hr, _T_816
node _T_817 = bits(_WIRE_57, 10, 10)
connect _WIRE_56.hx, _T_817
node _T_818 = bits(_WIRE_57, 11, 11)
connect _WIRE_56.hw, _T_818
node _T_819 = bits(_WIRE_57, 12, 12)
connect _WIRE_56.sr, _T_819
node _T_820 = bits(_WIRE_57, 13, 13)
connect _WIRE_56.sx, _T_820
node _T_821 = bits(_WIRE_57, 14, 14)
connect _WIRE_56.sw, _T_821
node _T_822 = bits(_WIRE_57, 15, 15)
connect _WIRE_56.gf, _T_822
node _T_823 = bits(_WIRE_57, 16, 16)
connect _WIRE_56.pf, _T_823
node _T_824 = bits(_WIRE_57, 17, 17)
connect _WIRE_56.ae_stage2, _T_824
node _T_825 = bits(_WIRE_57, 18, 18)
connect _WIRE_56.ae_final, _T_825
node _T_826 = bits(_WIRE_57, 19, 19)
connect _WIRE_56.ae_ptw, _T_826
node _T_827 = bits(_WIRE_57, 20, 20)
connect _WIRE_56.g, _T_827
node _T_828 = bits(_WIRE_57, 21, 21)
connect _WIRE_56.u, _T_828
node _T_829 = bits(_WIRE_57, 41, 22)
connect _WIRE_56.ppn, _T_829
wire _WIRE_58 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_59 : UInt<42>
connect _WIRE_59, sectored_entries[0][1].data[1]
node _T_830 = bits(_WIRE_59, 0, 0)
connect _WIRE_58.fragmented_superpage, _T_830
node _T_831 = bits(_WIRE_59, 1, 1)
connect _WIRE_58.c, _T_831
node _T_832 = bits(_WIRE_59, 2, 2)
connect _WIRE_58.eff, _T_832
node _T_833 = bits(_WIRE_59, 3, 3)
connect _WIRE_58.paa, _T_833
node _T_834 = bits(_WIRE_59, 4, 4)
connect _WIRE_58.pal, _T_834
node _T_835 = bits(_WIRE_59, 5, 5)
connect _WIRE_58.ppp, _T_835
node _T_836 = bits(_WIRE_59, 6, 6)
connect _WIRE_58.pr, _T_836
node _T_837 = bits(_WIRE_59, 7, 7)
connect _WIRE_58.px, _T_837
node _T_838 = bits(_WIRE_59, 8, 8)
connect _WIRE_58.pw, _T_838
node _T_839 = bits(_WIRE_59, 9, 9)
connect _WIRE_58.hr, _T_839
node _T_840 = bits(_WIRE_59, 10, 10)
connect _WIRE_58.hx, _T_840
node _T_841 = bits(_WIRE_59, 11, 11)
connect _WIRE_58.hw, _T_841
node _T_842 = bits(_WIRE_59, 12, 12)
connect _WIRE_58.sr, _T_842
node _T_843 = bits(_WIRE_59, 13, 13)
connect _WIRE_58.sx, _T_843
node _T_844 = bits(_WIRE_59, 14, 14)
connect _WIRE_58.sw, _T_844
node _T_845 = bits(_WIRE_59, 15, 15)
connect _WIRE_58.gf, _T_845
node _T_846 = bits(_WIRE_59, 16, 16)
connect _WIRE_58.pf, _T_846
node _T_847 = bits(_WIRE_59, 17, 17)
connect _WIRE_58.ae_stage2, _T_847
node _T_848 = bits(_WIRE_59, 18, 18)
connect _WIRE_58.ae_final, _T_848
node _T_849 = bits(_WIRE_59, 19, 19)
connect _WIRE_58.ae_ptw, _T_849
node _T_850 = bits(_WIRE_59, 20, 20)
connect _WIRE_58.g, _T_850
node _T_851 = bits(_WIRE_59, 21, 21)
connect _WIRE_58.u, _T_851
node _T_852 = bits(_WIRE_59, 41, 22)
connect _WIRE_58.ppn, _T_852
wire _WIRE_60 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_61 : UInt<42>
connect _WIRE_61, sectored_entries[0][1].data[2]
node _T_853 = bits(_WIRE_61, 0, 0)
connect _WIRE_60.fragmented_superpage, _T_853
node _T_854 = bits(_WIRE_61, 1, 1)
connect _WIRE_60.c, _T_854
node _T_855 = bits(_WIRE_61, 2, 2)
connect _WIRE_60.eff, _T_855
node _T_856 = bits(_WIRE_61, 3, 3)
connect _WIRE_60.paa, _T_856
node _T_857 = bits(_WIRE_61, 4, 4)
connect _WIRE_60.pal, _T_857
node _T_858 = bits(_WIRE_61, 5, 5)
connect _WIRE_60.ppp, _T_858
node _T_859 = bits(_WIRE_61, 6, 6)
connect _WIRE_60.pr, _T_859
node _T_860 = bits(_WIRE_61, 7, 7)
connect _WIRE_60.px, _T_860
node _T_861 = bits(_WIRE_61, 8, 8)
connect _WIRE_60.pw, _T_861
node _T_862 = bits(_WIRE_61, 9, 9)
connect _WIRE_60.hr, _T_862
node _T_863 = bits(_WIRE_61, 10, 10)
connect _WIRE_60.hx, _T_863
node _T_864 = bits(_WIRE_61, 11, 11)
connect _WIRE_60.hw, _T_864
node _T_865 = bits(_WIRE_61, 12, 12)
connect _WIRE_60.sr, _T_865
node _T_866 = bits(_WIRE_61, 13, 13)
connect _WIRE_60.sx, _T_866
node _T_867 = bits(_WIRE_61, 14, 14)
connect _WIRE_60.sw, _T_867
node _T_868 = bits(_WIRE_61, 15, 15)
connect _WIRE_60.gf, _T_868
node _T_869 = bits(_WIRE_61, 16, 16)
connect _WIRE_60.pf, _T_869
node _T_870 = bits(_WIRE_61, 17, 17)
connect _WIRE_60.ae_stage2, _T_870
node _T_871 = bits(_WIRE_61, 18, 18)
connect _WIRE_60.ae_final, _T_871
node _T_872 = bits(_WIRE_61, 19, 19)
connect _WIRE_60.ae_ptw, _T_872
node _T_873 = bits(_WIRE_61, 20, 20)
connect _WIRE_60.g, _T_873
node _T_874 = bits(_WIRE_61, 21, 21)
connect _WIRE_60.u, _T_874
node _T_875 = bits(_WIRE_61, 41, 22)
connect _WIRE_60.ppn, _T_875
wire _WIRE_62 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_63 : UInt<42>
connect _WIRE_63, sectored_entries[0][1].data[3]
node _T_876 = bits(_WIRE_63, 0, 0)
connect _WIRE_62.fragmented_superpage, _T_876
node _T_877 = bits(_WIRE_63, 1, 1)
connect _WIRE_62.c, _T_877
node _T_878 = bits(_WIRE_63, 2, 2)
connect _WIRE_62.eff, _T_878
node _T_879 = bits(_WIRE_63, 3, 3)
connect _WIRE_62.paa, _T_879
node _T_880 = bits(_WIRE_63, 4, 4)
connect _WIRE_62.pal, _T_880
node _T_881 = bits(_WIRE_63, 5, 5)
connect _WIRE_62.ppp, _T_881
node _T_882 = bits(_WIRE_63, 6, 6)
connect _WIRE_62.pr, _T_882
node _T_883 = bits(_WIRE_63, 7, 7)
connect _WIRE_62.px, _T_883
node _T_884 = bits(_WIRE_63, 8, 8)
connect _WIRE_62.pw, _T_884
node _T_885 = bits(_WIRE_63, 9, 9)
connect _WIRE_62.hr, _T_885
node _T_886 = bits(_WIRE_63, 10, 10)
connect _WIRE_62.hx, _T_886
node _T_887 = bits(_WIRE_63, 11, 11)
connect _WIRE_62.hw, _T_887
node _T_888 = bits(_WIRE_63, 12, 12)
connect _WIRE_62.sr, _T_888
node _T_889 = bits(_WIRE_63, 13, 13)
connect _WIRE_62.sx, _T_889
node _T_890 = bits(_WIRE_63, 14, 14)
connect _WIRE_62.sw, _T_890
node _T_891 = bits(_WIRE_63, 15, 15)
connect _WIRE_62.gf, _T_891
node _T_892 = bits(_WIRE_63, 16, 16)
connect _WIRE_62.pf, _T_892
node _T_893 = bits(_WIRE_63, 17, 17)
connect _WIRE_62.ae_stage2, _T_893
node _T_894 = bits(_WIRE_63, 18, 18)
connect _WIRE_62.ae_final, _T_894
node _T_895 = bits(_WIRE_63, 19, 19)
connect _WIRE_62.ae_ptw, _T_895
node _T_896 = bits(_WIRE_63, 20, 20)
connect _WIRE_62.g, _T_896
node _T_897 = bits(_WIRE_63, 21, 21)
connect _WIRE_62.u, _T_897
node _T_898 = bits(_WIRE_63, 41, 22)
connect _WIRE_62.ppn, _T_898
node _T_899 = eq(sectored_entries[0][1].tag_v, _T_806)
when _T_899 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_900 = eq(sectored_entries[0][1].tag_v, _T_806)
when _T_900 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_901 = eq(sectored_entries[0][1].tag_v, _T_806)
when _T_901 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_902 = eq(sectored_entries[0][1].tag_v, _T_806)
when _T_902 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
node hv_2 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_2 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_903 = eq(hg_2, UInt<1>(0h0))
node _T_904 = and(_T_903, io.sfence.bits.rs1)
when _T_904 :
node _T_905 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _T_906 = shr(_T_905, 2)
node _T_907 = eq(_T_906, UInt<1>(0h0))
node _T_908 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_909 = and(_T_907, _T_908)
when _T_909 :
wire _WIRE_64 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_65 : UInt<42>
connect _WIRE_65, sectored_entries[0][2].data[0]
node _T_910 = bits(_WIRE_65, 0, 0)
connect _WIRE_64.fragmented_superpage, _T_910
node _T_911 = bits(_WIRE_65, 1, 1)
connect _WIRE_64.c, _T_911
node _T_912 = bits(_WIRE_65, 2, 2)
connect _WIRE_64.eff, _T_912
node _T_913 = bits(_WIRE_65, 3, 3)
connect _WIRE_64.paa, _T_913
node _T_914 = bits(_WIRE_65, 4, 4)
connect _WIRE_64.pal, _T_914
node _T_915 = bits(_WIRE_65, 5, 5)
connect _WIRE_64.ppp, _T_915
node _T_916 = bits(_WIRE_65, 6, 6)
connect _WIRE_64.pr, _T_916
node _T_917 = bits(_WIRE_65, 7, 7)
connect _WIRE_64.px, _T_917
node _T_918 = bits(_WIRE_65, 8, 8)
connect _WIRE_64.pw, _T_918
node _T_919 = bits(_WIRE_65, 9, 9)
connect _WIRE_64.hr, _T_919
node _T_920 = bits(_WIRE_65, 10, 10)
connect _WIRE_64.hx, _T_920
node _T_921 = bits(_WIRE_65, 11, 11)
connect _WIRE_64.hw, _T_921
node _T_922 = bits(_WIRE_65, 12, 12)
connect _WIRE_64.sr, _T_922
node _T_923 = bits(_WIRE_65, 13, 13)
connect _WIRE_64.sx, _T_923
node _T_924 = bits(_WIRE_65, 14, 14)
connect _WIRE_64.sw, _T_924
node _T_925 = bits(_WIRE_65, 15, 15)
connect _WIRE_64.gf, _T_925
node _T_926 = bits(_WIRE_65, 16, 16)
connect _WIRE_64.pf, _T_926
node _T_927 = bits(_WIRE_65, 17, 17)
connect _WIRE_64.ae_stage2, _T_927
node _T_928 = bits(_WIRE_65, 18, 18)
connect _WIRE_64.ae_final, _T_928
node _T_929 = bits(_WIRE_65, 19, 19)
connect _WIRE_64.ae_ptw, _T_929
node _T_930 = bits(_WIRE_65, 20, 20)
connect _WIRE_64.g, _T_930
node _T_931 = bits(_WIRE_65, 21, 21)
connect _WIRE_64.u, _T_931
node _T_932 = bits(_WIRE_65, 41, 22)
connect _WIRE_64.ppn, _T_932
wire _WIRE_66 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_67 : UInt<42>
connect _WIRE_67, sectored_entries[0][2].data[1]
node _T_933 = bits(_WIRE_67, 0, 0)
connect _WIRE_66.fragmented_superpage, _T_933
node _T_934 = bits(_WIRE_67, 1, 1)
connect _WIRE_66.c, _T_934
node _T_935 = bits(_WIRE_67, 2, 2)
connect _WIRE_66.eff, _T_935
node _T_936 = bits(_WIRE_67, 3, 3)
connect _WIRE_66.paa, _T_936
node _T_937 = bits(_WIRE_67, 4, 4)
connect _WIRE_66.pal, _T_937
node _T_938 = bits(_WIRE_67, 5, 5)
connect _WIRE_66.ppp, _T_938
node _T_939 = bits(_WIRE_67, 6, 6)
connect _WIRE_66.pr, _T_939
node _T_940 = bits(_WIRE_67, 7, 7)
connect _WIRE_66.px, _T_940
node _T_941 = bits(_WIRE_67, 8, 8)
connect _WIRE_66.pw, _T_941
node _T_942 = bits(_WIRE_67, 9, 9)
connect _WIRE_66.hr, _T_942
node _T_943 = bits(_WIRE_67, 10, 10)
connect _WIRE_66.hx, _T_943
node _T_944 = bits(_WIRE_67, 11, 11)
connect _WIRE_66.hw, _T_944
node _T_945 = bits(_WIRE_67, 12, 12)
connect _WIRE_66.sr, _T_945
node _T_946 = bits(_WIRE_67, 13, 13)
connect _WIRE_66.sx, _T_946
node _T_947 = bits(_WIRE_67, 14, 14)
connect _WIRE_66.sw, _T_947
node _T_948 = bits(_WIRE_67, 15, 15)
connect _WIRE_66.gf, _T_948
node _T_949 = bits(_WIRE_67, 16, 16)
connect _WIRE_66.pf, _T_949
node _T_950 = bits(_WIRE_67, 17, 17)
connect _WIRE_66.ae_stage2, _T_950
node _T_951 = bits(_WIRE_67, 18, 18)
connect _WIRE_66.ae_final, _T_951
node _T_952 = bits(_WIRE_67, 19, 19)
connect _WIRE_66.ae_ptw, _T_952
node _T_953 = bits(_WIRE_67, 20, 20)
connect _WIRE_66.g, _T_953
node _T_954 = bits(_WIRE_67, 21, 21)
connect _WIRE_66.u, _T_954
node _T_955 = bits(_WIRE_67, 41, 22)
connect _WIRE_66.ppn, _T_955
wire _WIRE_68 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_69 : UInt<42>
connect _WIRE_69, sectored_entries[0][2].data[2]
node _T_956 = bits(_WIRE_69, 0, 0)
connect _WIRE_68.fragmented_superpage, _T_956
node _T_957 = bits(_WIRE_69, 1, 1)
connect _WIRE_68.c, _T_957
node _T_958 = bits(_WIRE_69, 2, 2)
connect _WIRE_68.eff, _T_958
node _T_959 = bits(_WIRE_69, 3, 3)
connect _WIRE_68.paa, _T_959
node _T_960 = bits(_WIRE_69, 4, 4)
connect _WIRE_68.pal, _T_960
node _T_961 = bits(_WIRE_69, 5, 5)
connect _WIRE_68.ppp, _T_961
node _T_962 = bits(_WIRE_69, 6, 6)
connect _WIRE_68.pr, _T_962
node _T_963 = bits(_WIRE_69, 7, 7)
connect _WIRE_68.px, _T_963
node _T_964 = bits(_WIRE_69, 8, 8)
connect _WIRE_68.pw, _T_964
node _T_965 = bits(_WIRE_69, 9, 9)
connect _WIRE_68.hr, _T_965
node _T_966 = bits(_WIRE_69, 10, 10)
connect _WIRE_68.hx, _T_966
node _T_967 = bits(_WIRE_69, 11, 11)
connect _WIRE_68.hw, _T_967
node _T_968 = bits(_WIRE_69, 12, 12)
connect _WIRE_68.sr, _T_968
node _T_969 = bits(_WIRE_69, 13, 13)
connect _WIRE_68.sx, _T_969
node _T_970 = bits(_WIRE_69, 14, 14)
connect _WIRE_68.sw, _T_970
node _T_971 = bits(_WIRE_69, 15, 15)
connect _WIRE_68.gf, _T_971
node _T_972 = bits(_WIRE_69, 16, 16)
connect _WIRE_68.pf, _T_972
node _T_973 = bits(_WIRE_69, 17, 17)
connect _WIRE_68.ae_stage2, _T_973
node _T_974 = bits(_WIRE_69, 18, 18)
connect _WIRE_68.ae_final, _T_974
node _T_975 = bits(_WIRE_69, 19, 19)
connect _WIRE_68.ae_ptw, _T_975
node _T_976 = bits(_WIRE_69, 20, 20)
connect _WIRE_68.g, _T_976
node _T_977 = bits(_WIRE_69, 21, 21)
connect _WIRE_68.u, _T_977
node _T_978 = bits(_WIRE_69, 41, 22)
connect _WIRE_68.ppn, _T_978
wire _WIRE_70 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_71 : UInt<42>
connect _WIRE_71, sectored_entries[0][2].data[3]
node _T_979 = bits(_WIRE_71, 0, 0)
connect _WIRE_70.fragmented_superpage, _T_979
node _T_980 = bits(_WIRE_71, 1, 1)
connect _WIRE_70.c, _T_980
node _T_981 = bits(_WIRE_71, 2, 2)
connect _WIRE_70.eff, _T_981
node _T_982 = bits(_WIRE_71, 3, 3)
connect _WIRE_70.paa, _T_982
node _T_983 = bits(_WIRE_71, 4, 4)
connect _WIRE_70.pal, _T_983
node _T_984 = bits(_WIRE_71, 5, 5)
connect _WIRE_70.ppp, _T_984
node _T_985 = bits(_WIRE_71, 6, 6)
connect _WIRE_70.pr, _T_985
node _T_986 = bits(_WIRE_71, 7, 7)
connect _WIRE_70.px, _T_986
node _T_987 = bits(_WIRE_71, 8, 8)
connect _WIRE_70.pw, _T_987
node _T_988 = bits(_WIRE_71, 9, 9)
connect _WIRE_70.hr, _T_988
node _T_989 = bits(_WIRE_71, 10, 10)
connect _WIRE_70.hx, _T_989
node _T_990 = bits(_WIRE_71, 11, 11)
connect _WIRE_70.hw, _T_990
node _T_991 = bits(_WIRE_71, 12, 12)
connect _WIRE_70.sr, _T_991
node _T_992 = bits(_WIRE_71, 13, 13)
connect _WIRE_70.sx, _T_992
node _T_993 = bits(_WIRE_71, 14, 14)
connect _WIRE_70.sw, _T_993
node _T_994 = bits(_WIRE_71, 15, 15)
connect _WIRE_70.gf, _T_994
node _T_995 = bits(_WIRE_71, 16, 16)
connect _WIRE_70.pf, _T_995
node _T_996 = bits(_WIRE_71, 17, 17)
connect _WIRE_70.ae_stage2, _T_996
node _T_997 = bits(_WIRE_71, 18, 18)
connect _WIRE_70.ae_final, _T_997
node _T_998 = bits(_WIRE_71, 19, 19)
connect _WIRE_70.ae_ptw, _T_998
node _T_999 = bits(_WIRE_71, 20, 20)
connect _WIRE_70.g, _T_999
node _T_1000 = bits(_WIRE_71, 21, 21)
connect _WIRE_70.u, _T_1000
node _T_1001 = bits(_WIRE_71, 41, 22)
connect _WIRE_70.ppn, _T_1001
node _T_1002 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1003 = bits(vpn, 1, 0)
node _T_1004 = eq(UInt<1>(0h0), _T_1003)
node _T_1005 = and(_T_1002, _T_1004)
when _T_1005 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_1006 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1007 = bits(vpn, 1, 0)
node _T_1008 = eq(UInt<1>(0h1), _T_1007)
node _T_1009 = and(_T_1006, _T_1008)
when _T_1009 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_1010 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1011 = bits(vpn, 1, 0)
node _T_1012 = eq(UInt<2>(0h2), _T_1011)
node _T_1013 = and(_T_1010, _T_1012)
when _T_1013 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_1014 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1015 = bits(vpn, 1, 0)
node _T_1016 = eq(UInt<2>(0h3), _T_1015)
node _T_1017 = and(_T_1014, _T_1016)
when _T_1017 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
node _T_1018 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _T_1019 = shr(_T_1018, 18)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
wire _WIRE_72 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_73 : UInt<42>
connect _WIRE_73, sectored_entries[0][2].data[0]
node _T_1021 = bits(_WIRE_73, 0, 0)
connect _WIRE_72.fragmented_superpage, _T_1021
node _T_1022 = bits(_WIRE_73, 1, 1)
connect _WIRE_72.c, _T_1022
node _T_1023 = bits(_WIRE_73, 2, 2)
connect _WIRE_72.eff, _T_1023
node _T_1024 = bits(_WIRE_73, 3, 3)
connect _WIRE_72.paa, _T_1024
node _T_1025 = bits(_WIRE_73, 4, 4)
connect _WIRE_72.pal, _T_1025
node _T_1026 = bits(_WIRE_73, 5, 5)
connect _WIRE_72.ppp, _T_1026
node _T_1027 = bits(_WIRE_73, 6, 6)
connect _WIRE_72.pr, _T_1027
node _T_1028 = bits(_WIRE_73, 7, 7)
connect _WIRE_72.px, _T_1028
node _T_1029 = bits(_WIRE_73, 8, 8)
connect _WIRE_72.pw, _T_1029
node _T_1030 = bits(_WIRE_73, 9, 9)
connect _WIRE_72.hr, _T_1030
node _T_1031 = bits(_WIRE_73, 10, 10)
connect _WIRE_72.hx, _T_1031
node _T_1032 = bits(_WIRE_73, 11, 11)
connect _WIRE_72.hw, _T_1032
node _T_1033 = bits(_WIRE_73, 12, 12)
connect _WIRE_72.sr, _T_1033
node _T_1034 = bits(_WIRE_73, 13, 13)
connect _WIRE_72.sx, _T_1034
node _T_1035 = bits(_WIRE_73, 14, 14)
connect _WIRE_72.sw, _T_1035
node _T_1036 = bits(_WIRE_73, 15, 15)
connect _WIRE_72.gf, _T_1036
node _T_1037 = bits(_WIRE_73, 16, 16)
connect _WIRE_72.pf, _T_1037
node _T_1038 = bits(_WIRE_73, 17, 17)
connect _WIRE_72.ae_stage2, _T_1038
node _T_1039 = bits(_WIRE_73, 18, 18)
connect _WIRE_72.ae_final, _T_1039
node _T_1040 = bits(_WIRE_73, 19, 19)
connect _WIRE_72.ae_ptw, _T_1040
node _T_1041 = bits(_WIRE_73, 20, 20)
connect _WIRE_72.g, _T_1041
node _T_1042 = bits(_WIRE_73, 21, 21)
connect _WIRE_72.u, _T_1042
node _T_1043 = bits(_WIRE_73, 41, 22)
connect _WIRE_72.ppn, _T_1043
wire _WIRE_74 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_75 : UInt<42>
connect _WIRE_75, sectored_entries[0][2].data[1]
node _T_1044 = bits(_WIRE_75, 0, 0)
connect _WIRE_74.fragmented_superpage, _T_1044
node _T_1045 = bits(_WIRE_75, 1, 1)
connect _WIRE_74.c, _T_1045
node _T_1046 = bits(_WIRE_75, 2, 2)
connect _WIRE_74.eff, _T_1046
node _T_1047 = bits(_WIRE_75, 3, 3)
connect _WIRE_74.paa, _T_1047
node _T_1048 = bits(_WIRE_75, 4, 4)
connect _WIRE_74.pal, _T_1048
node _T_1049 = bits(_WIRE_75, 5, 5)
connect _WIRE_74.ppp, _T_1049
node _T_1050 = bits(_WIRE_75, 6, 6)
connect _WIRE_74.pr, _T_1050
node _T_1051 = bits(_WIRE_75, 7, 7)
connect _WIRE_74.px, _T_1051
node _T_1052 = bits(_WIRE_75, 8, 8)
connect _WIRE_74.pw, _T_1052
node _T_1053 = bits(_WIRE_75, 9, 9)
connect _WIRE_74.hr, _T_1053
node _T_1054 = bits(_WIRE_75, 10, 10)
connect _WIRE_74.hx, _T_1054
node _T_1055 = bits(_WIRE_75, 11, 11)
connect _WIRE_74.hw, _T_1055
node _T_1056 = bits(_WIRE_75, 12, 12)
connect _WIRE_74.sr, _T_1056
node _T_1057 = bits(_WIRE_75, 13, 13)
connect _WIRE_74.sx, _T_1057
node _T_1058 = bits(_WIRE_75, 14, 14)
connect _WIRE_74.sw, _T_1058
node _T_1059 = bits(_WIRE_75, 15, 15)
connect _WIRE_74.gf, _T_1059
node _T_1060 = bits(_WIRE_75, 16, 16)
connect _WIRE_74.pf, _T_1060
node _T_1061 = bits(_WIRE_75, 17, 17)
connect _WIRE_74.ae_stage2, _T_1061
node _T_1062 = bits(_WIRE_75, 18, 18)
connect _WIRE_74.ae_final, _T_1062
node _T_1063 = bits(_WIRE_75, 19, 19)
connect _WIRE_74.ae_ptw, _T_1063
node _T_1064 = bits(_WIRE_75, 20, 20)
connect _WIRE_74.g, _T_1064
node _T_1065 = bits(_WIRE_75, 21, 21)
connect _WIRE_74.u, _T_1065
node _T_1066 = bits(_WIRE_75, 41, 22)
connect _WIRE_74.ppn, _T_1066
wire _WIRE_76 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_77 : UInt<42>
connect _WIRE_77, sectored_entries[0][2].data[2]
node _T_1067 = bits(_WIRE_77, 0, 0)
connect _WIRE_76.fragmented_superpage, _T_1067
node _T_1068 = bits(_WIRE_77, 1, 1)
connect _WIRE_76.c, _T_1068
node _T_1069 = bits(_WIRE_77, 2, 2)
connect _WIRE_76.eff, _T_1069
node _T_1070 = bits(_WIRE_77, 3, 3)
connect _WIRE_76.paa, _T_1070
node _T_1071 = bits(_WIRE_77, 4, 4)
connect _WIRE_76.pal, _T_1071
node _T_1072 = bits(_WIRE_77, 5, 5)
connect _WIRE_76.ppp, _T_1072
node _T_1073 = bits(_WIRE_77, 6, 6)
connect _WIRE_76.pr, _T_1073
node _T_1074 = bits(_WIRE_77, 7, 7)
connect _WIRE_76.px, _T_1074
node _T_1075 = bits(_WIRE_77, 8, 8)
connect _WIRE_76.pw, _T_1075
node _T_1076 = bits(_WIRE_77, 9, 9)
connect _WIRE_76.hr, _T_1076
node _T_1077 = bits(_WIRE_77, 10, 10)
connect _WIRE_76.hx, _T_1077
node _T_1078 = bits(_WIRE_77, 11, 11)
connect _WIRE_76.hw, _T_1078
node _T_1079 = bits(_WIRE_77, 12, 12)
connect _WIRE_76.sr, _T_1079
node _T_1080 = bits(_WIRE_77, 13, 13)
connect _WIRE_76.sx, _T_1080
node _T_1081 = bits(_WIRE_77, 14, 14)
connect _WIRE_76.sw, _T_1081
node _T_1082 = bits(_WIRE_77, 15, 15)
connect _WIRE_76.gf, _T_1082
node _T_1083 = bits(_WIRE_77, 16, 16)
connect _WIRE_76.pf, _T_1083
node _T_1084 = bits(_WIRE_77, 17, 17)
connect _WIRE_76.ae_stage2, _T_1084
node _T_1085 = bits(_WIRE_77, 18, 18)
connect _WIRE_76.ae_final, _T_1085
node _T_1086 = bits(_WIRE_77, 19, 19)
connect _WIRE_76.ae_ptw, _T_1086
node _T_1087 = bits(_WIRE_77, 20, 20)
connect _WIRE_76.g, _T_1087
node _T_1088 = bits(_WIRE_77, 21, 21)
connect _WIRE_76.u, _T_1088
node _T_1089 = bits(_WIRE_77, 41, 22)
connect _WIRE_76.ppn, _T_1089
wire _WIRE_78 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_79 : UInt<42>
connect _WIRE_79, sectored_entries[0][2].data[3]
node _T_1090 = bits(_WIRE_79, 0, 0)
connect _WIRE_78.fragmented_superpage, _T_1090
node _T_1091 = bits(_WIRE_79, 1, 1)
connect _WIRE_78.c, _T_1091
node _T_1092 = bits(_WIRE_79, 2, 2)
connect _WIRE_78.eff, _T_1092
node _T_1093 = bits(_WIRE_79, 3, 3)
connect _WIRE_78.paa, _T_1093
node _T_1094 = bits(_WIRE_79, 4, 4)
connect _WIRE_78.pal, _T_1094
node _T_1095 = bits(_WIRE_79, 5, 5)
connect _WIRE_78.ppp, _T_1095
node _T_1096 = bits(_WIRE_79, 6, 6)
connect _WIRE_78.pr, _T_1096
node _T_1097 = bits(_WIRE_79, 7, 7)
connect _WIRE_78.px, _T_1097
node _T_1098 = bits(_WIRE_79, 8, 8)
connect _WIRE_78.pw, _T_1098
node _T_1099 = bits(_WIRE_79, 9, 9)
connect _WIRE_78.hr, _T_1099
node _T_1100 = bits(_WIRE_79, 10, 10)
connect _WIRE_78.hx, _T_1100
node _T_1101 = bits(_WIRE_79, 11, 11)
connect _WIRE_78.hw, _T_1101
node _T_1102 = bits(_WIRE_79, 12, 12)
connect _WIRE_78.sr, _T_1102
node _T_1103 = bits(_WIRE_79, 13, 13)
connect _WIRE_78.sx, _T_1103
node _T_1104 = bits(_WIRE_79, 14, 14)
connect _WIRE_78.sw, _T_1104
node _T_1105 = bits(_WIRE_79, 15, 15)
connect _WIRE_78.gf, _T_1105
node _T_1106 = bits(_WIRE_79, 16, 16)
connect _WIRE_78.pf, _T_1106
node _T_1107 = bits(_WIRE_79, 17, 17)
connect _WIRE_78.ae_stage2, _T_1107
node _T_1108 = bits(_WIRE_79, 18, 18)
connect _WIRE_78.ae_final, _T_1108
node _T_1109 = bits(_WIRE_79, 19, 19)
connect _WIRE_78.ae_ptw, _T_1109
node _T_1110 = bits(_WIRE_79, 20, 20)
connect _WIRE_78.g, _T_1110
node _T_1111 = bits(_WIRE_79, 21, 21)
connect _WIRE_78.u, _T_1111
node _T_1112 = bits(_WIRE_79, 41, 22)
connect _WIRE_78.ppn, _T_1112
node _T_1113 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1114 = and(_T_1113, _WIRE_72.fragmented_superpage)
when _T_1114 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_1115 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1116 = and(_T_1115, _WIRE_74.fragmented_superpage)
when _T_1116 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_1117 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1118 = and(_T_1117, _WIRE_76.fragmented_superpage)
when _T_1118 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_1119 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1120 = and(_T_1119, _WIRE_78.fragmented_superpage)
when _T_1120 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
else :
node _T_1121 = eq(hg_2, UInt<1>(0h0))
node _T_1122 = and(_T_1121, io.sfence.bits.rs2)
when _T_1122 :
wire _WIRE_80 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_81 : UInt<42>
connect _WIRE_81, sectored_entries[0][2].data[0]
node _T_1123 = bits(_WIRE_81, 0, 0)
connect _WIRE_80.fragmented_superpage, _T_1123
node _T_1124 = bits(_WIRE_81, 1, 1)
connect _WIRE_80.c, _T_1124
node _T_1125 = bits(_WIRE_81, 2, 2)
connect _WIRE_80.eff, _T_1125
node _T_1126 = bits(_WIRE_81, 3, 3)
connect _WIRE_80.paa, _T_1126
node _T_1127 = bits(_WIRE_81, 4, 4)
connect _WIRE_80.pal, _T_1127
node _T_1128 = bits(_WIRE_81, 5, 5)
connect _WIRE_80.ppp, _T_1128
node _T_1129 = bits(_WIRE_81, 6, 6)
connect _WIRE_80.pr, _T_1129
node _T_1130 = bits(_WIRE_81, 7, 7)
connect _WIRE_80.px, _T_1130
node _T_1131 = bits(_WIRE_81, 8, 8)
connect _WIRE_80.pw, _T_1131
node _T_1132 = bits(_WIRE_81, 9, 9)
connect _WIRE_80.hr, _T_1132
node _T_1133 = bits(_WIRE_81, 10, 10)
connect _WIRE_80.hx, _T_1133
node _T_1134 = bits(_WIRE_81, 11, 11)
connect _WIRE_80.hw, _T_1134
node _T_1135 = bits(_WIRE_81, 12, 12)
connect _WIRE_80.sr, _T_1135
node _T_1136 = bits(_WIRE_81, 13, 13)
connect _WIRE_80.sx, _T_1136
node _T_1137 = bits(_WIRE_81, 14, 14)
connect _WIRE_80.sw, _T_1137
node _T_1138 = bits(_WIRE_81, 15, 15)
connect _WIRE_80.gf, _T_1138
node _T_1139 = bits(_WIRE_81, 16, 16)
connect _WIRE_80.pf, _T_1139
node _T_1140 = bits(_WIRE_81, 17, 17)
connect _WIRE_80.ae_stage2, _T_1140
node _T_1141 = bits(_WIRE_81, 18, 18)
connect _WIRE_80.ae_final, _T_1141
node _T_1142 = bits(_WIRE_81, 19, 19)
connect _WIRE_80.ae_ptw, _T_1142
node _T_1143 = bits(_WIRE_81, 20, 20)
connect _WIRE_80.g, _T_1143
node _T_1144 = bits(_WIRE_81, 21, 21)
connect _WIRE_80.u, _T_1144
node _T_1145 = bits(_WIRE_81, 41, 22)
connect _WIRE_80.ppn, _T_1145
wire _WIRE_82 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_83 : UInt<42>
connect _WIRE_83, sectored_entries[0][2].data[1]
node _T_1146 = bits(_WIRE_83, 0, 0)
connect _WIRE_82.fragmented_superpage, _T_1146
node _T_1147 = bits(_WIRE_83, 1, 1)
connect _WIRE_82.c, _T_1147
node _T_1148 = bits(_WIRE_83, 2, 2)
connect _WIRE_82.eff, _T_1148
node _T_1149 = bits(_WIRE_83, 3, 3)
connect _WIRE_82.paa, _T_1149
node _T_1150 = bits(_WIRE_83, 4, 4)
connect _WIRE_82.pal, _T_1150
node _T_1151 = bits(_WIRE_83, 5, 5)
connect _WIRE_82.ppp, _T_1151
node _T_1152 = bits(_WIRE_83, 6, 6)
connect _WIRE_82.pr, _T_1152
node _T_1153 = bits(_WIRE_83, 7, 7)
connect _WIRE_82.px, _T_1153
node _T_1154 = bits(_WIRE_83, 8, 8)
connect _WIRE_82.pw, _T_1154
node _T_1155 = bits(_WIRE_83, 9, 9)
connect _WIRE_82.hr, _T_1155
node _T_1156 = bits(_WIRE_83, 10, 10)
connect _WIRE_82.hx, _T_1156
node _T_1157 = bits(_WIRE_83, 11, 11)
connect _WIRE_82.hw, _T_1157
node _T_1158 = bits(_WIRE_83, 12, 12)
connect _WIRE_82.sr, _T_1158
node _T_1159 = bits(_WIRE_83, 13, 13)
connect _WIRE_82.sx, _T_1159
node _T_1160 = bits(_WIRE_83, 14, 14)
connect _WIRE_82.sw, _T_1160
node _T_1161 = bits(_WIRE_83, 15, 15)
connect _WIRE_82.gf, _T_1161
node _T_1162 = bits(_WIRE_83, 16, 16)
connect _WIRE_82.pf, _T_1162
node _T_1163 = bits(_WIRE_83, 17, 17)
connect _WIRE_82.ae_stage2, _T_1163
node _T_1164 = bits(_WIRE_83, 18, 18)
connect _WIRE_82.ae_final, _T_1164
node _T_1165 = bits(_WIRE_83, 19, 19)
connect _WIRE_82.ae_ptw, _T_1165
node _T_1166 = bits(_WIRE_83, 20, 20)
connect _WIRE_82.g, _T_1166
node _T_1167 = bits(_WIRE_83, 21, 21)
connect _WIRE_82.u, _T_1167
node _T_1168 = bits(_WIRE_83, 41, 22)
connect _WIRE_82.ppn, _T_1168
wire _WIRE_84 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_85 : UInt<42>
connect _WIRE_85, sectored_entries[0][2].data[2]
node _T_1169 = bits(_WIRE_85, 0, 0)
connect _WIRE_84.fragmented_superpage, _T_1169
node _T_1170 = bits(_WIRE_85, 1, 1)
connect _WIRE_84.c, _T_1170
node _T_1171 = bits(_WIRE_85, 2, 2)
connect _WIRE_84.eff, _T_1171
node _T_1172 = bits(_WIRE_85, 3, 3)
connect _WIRE_84.paa, _T_1172
node _T_1173 = bits(_WIRE_85, 4, 4)
connect _WIRE_84.pal, _T_1173
node _T_1174 = bits(_WIRE_85, 5, 5)
connect _WIRE_84.ppp, _T_1174
node _T_1175 = bits(_WIRE_85, 6, 6)
connect _WIRE_84.pr, _T_1175
node _T_1176 = bits(_WIRE_85, 7, 7)
connect _WIRE_84.px, _T_1176
node _T_1177 = bits(_WIRE_85, 8, 8)
connect _WIRE_84.pw, _T_1177
node _T_1178 = bits(_WIRE_85, 9, 9)
connect _WIRE_84.hr, _T_1178
node _T_1179 = bits(_WIRE_85, 10, 10)
connect _WIRE_84.hx, _T_1179
node _T_1180 = bits(_WIRE_85, 11, 11)
connect _WIRE_84.hw, _T_1180
node _T_1181 = bits(_WIRE_85, 12, 12)
connect _WIRE_84.sr, _T_1181
node _T_1182 = bits(_WIRE_85, 13, 13)
connect _WIRE_84.sx, _T_1182
node _T_1183 = bits(_WIRE_85, 14, 14)
connect _WIRE_84.sw, _T_1183
node _T_1184 = bits(_WIRE_85, 15, 15)
connect _WIRE_84.gf, _T_1184
node _T_1185 = bits(_WIRE_85, 16, 16)
connect _WIRE_84.pf, _T_1185
node _T_1186 = bits(_WIRE_85, 17, 17)
connect _WIRE_84.ae_stage2, _T_1186
node _T_1187 = bits(_WIRE_85, 18, 18)
connect _WIRE_84.ae_final, _T_1187
node _T_1188 = bits(_WIRE_85, 19, 19)
connect _WIRE_84.ae_ptw, _T_1188
node _T_1189 = bits(_WIRE_85, 20, 20)
connect _WIRE_84.g, _T_1189
node _T_1190 = bits(_WIRE_85, 21, 21)
connect _WIRE_84.u, _T_1190
node _T_1191 = bits(_WIRE_85, 41, 22)
connect _WIRE_84.ppn, _T_1191
wire _WIRE_86 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_87 : UInt<42>
connect _WIRE_87, sectored_entries[0][2].data[3]
node _T_1192 = bits(_WIRE_87, 0, 0)
connect _WIRE_86.fragmented_superpage, _T_1192
node _T_1193 = bits(_WIRE_87, 1, 1)
connect _WIRE_86.c, _T_1193
node _T_1194 = bits(_WIRE_87, 2, 2)
connect _WIRE_86.eff, _T_1194
node _T_1195 = bits(_WIRE_87, 3, 3)
connect _WIRE_86.paa, _T_1195
node _T_1196 = bits(_WIRE_87, 4, 4)
connect _WIRE_86.pal, _T_1196
node _T_1197 = bits(_WIRE_87, 5, 5)
connect _WIRE_86.ppp, _T_1197
node _T_1198 = bits(_WIRE_87, 6, 6)
connect _WIRE_86.pr, _T_1198
node _T_1199 = bits(_WIRE_87, 7, 7)
connect _WIRE_86.px, _T_1199
node _T_1200 = bits(_WIRE_87, 8, 8)
connect _WIRE_86.pw, _T_1200
node _T_1201 = bits(_WIRE_87, 9, 9)
connect _WIRE_86.hr, _T_1201
node _T_1202 = bits(_WIRE_87, 10, 10)
connect _WIRE_86.hx, _T_1202
node _T_1203 = bits(_WIRE_87, 11, 11)
connect _WIRE_86.hw, _T_1203
node _T_1204 = bits(_WIRE_87, 12, 12)
connect _WIRE_86.sr, _T_1204
node _T_1205 = bits(_WIRE_87, 13, 13)
connect _WIRE_86.sx, _T_1205
node _T_1206 = bits(_WIRE_87, 14, 14)
connect _WIRE_86.sw, _T_1206
node _T_1207 = bits(_WIRE_87, 15, 15)
connect _WIRE_86.gf, _T_1207
node _T_1208 = bits(_WIRE_87, 16, 16)
connect _WIRE_86.pf, _T_1208
node _T_1209 = bits(_WIRE_87, 17, 17)
connect _WIRE_86.ae_stage2, _T_1209
node _T_1210 = bits(_WIRE_87, 18, 18)
connect _WIRE_86.ae_final, _T_1210
node _T_1211 = bits(_WIRE_87, 19, 19)
connect _WIRE_86.ae_ptw, _T_1211
node _T_1212 = bits(_WIRE_87, 20, 20)
connect _WIRE_86.g, _T_1212
node _T_1213 = bits(_WIRE_87, 21, 21)
connect _WIRE_86.u, _T_1213
node _T_1214 = bits(_WIRE_87, 41, 22)
connect _WIRE_86.ppn, _T_1214
node _T_1215 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1216 = eq(_WIRE_80.g, UInt<1>(0h0))
node _T_1217 = and(_T_1215, _T_1216)
when _T_1217 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_1218 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1219 = eq(_WIRE_82.g, UInt<1>(0h0))
node _T_1220 = and(_T_1218, _T_1219)
when _T_1220 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_1221 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1222 = eq(_WIRE_84.g, UInt<1>(0h0))
node _T_1223 = and(_T_1221, _T_1222)
when _T_1223 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_1224 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1225 = eq(_WIRE_86.g, UInt<1>(0h0))
node _T_1226 = and(_T_1224, _T_1225)
when _T_1226 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
else :
node _T_1227 = or(hv_2, hg_2)
wire _WIRE_88 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_89 : UInt<42>
connect _WIRE_89, sectored_entries[0][2].data[0]
node _T_1228 = bits(_WIRE_89, 0, 0)
connect _WIRE_88.fragmented_superpage, _T_1228
node _T_1229 = bits(_WIRE_89, 1, 1)
connect _WIRE_88.c, _T_1229
node _T_1230 = bits(_WIRE_89, 2, 2)
connect _WIRE_88.eff, _T_1230
node _T_1231 = bits(_WIRE_89, 3, 3)
connect _WIRE_88.paa, _T_1231
node _T_1232 = bits(_WIRE_89, 4, 4)
connect _WIRE_88.pal, _T_1232
node _T_1233 = bits(_WIRE_89, 5, 5)
connect _WIRE_88.ppp, _T_1233
node _T_1234 = bits(_WIRE_89, 6, 6)
connect _WIRE_88.pr, _T_1234
node _T_1235 = bits(_WIRE_89, 7, 7)
connect _WIRE_88.px, _T_1235
node _T_1236 = bits(_WIRE_89, 8, 8)
connect _WIRE_88.pw, _T_1236
node _T_1237 = bits(_WIRE_89, 9, 9)
connect _WIRE_88.hr, _T_1237
node _T_1238 = bits(_WIRE_89, 10, 10)
connect _WIRE_88.hx, _T_1238
node _T_1239 = bits(_WIRE_89, 11, 11)
connect _WIRE_88.hw, _T_1239
node _T_1240 = bits(_WIRE_89, 12, 12)
connect _WIRE_88.sr, _T_1240
node _T_1241 = bits(_WIRE_89, 13, 13)
connect _WIRE_88.sx, _T_1241
node _T_1242 = bits(_WIRE_89, 14, 14)
connect _WIRE_88.sw, _T_1242
node _T_1243 = bits(_WIRE_89, 15, 15)
connect _WIRE_88.gf, _T_1243
node _T_1244 = bits(_WIRE_89, 16, 16)
connect _WIRE_88.pf, _T_1244
node _T_1245 = bits(_WIRE_89, 17, 17)
connect _WIRE_88.ae_stage2, _T_1245
node _T_1246 = bits(_WIRE_89, 18, 18)
connect _WIRE_88.ae_final, _T_1246
node _T_1247 = bits(_WIRE_89, 19, 19)
connect _WIRE_88.ae_ptw, _T_1247
node _T_1248 = bits(_WIRE_89, 20, 20)
connect _WIRE_88.g, _T_1248
node _T_1249 = bits(_WIRE_89, 21, 21)
connect _WIRE_88.u, _T_1249
node _T_1250 = bits(_WIRE_89, 41, 22)
connect _WIRE_88.ppn, _T_1250
wire _WIRE_90 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_91 : UInt<42>
connect _WIRE_91, sectored_entries[0][2].data[1]
node _T_1251 = bits(_WIRE_91, 0, 0)
connect _WIRE_90.fragmented_superpage, _T_1251
node _T_1252 = bits(_WIRE_91, 1, 1)
connect _WIRE_90.c, _T_1252
node _T_1253 = bits(_WIRE_91, 2, 2)
connect _WIRE_90.eff, _T_1253
node _T_1254 = bits(_WIRE_91, 3, 3)
connect _WIRE_90.paa, _T_1254
node _T_1255 = bits(_WIRE_91, 4, 4)
connect _WIRE_90.pal, _T_1255
node _T_1256 = bits(_WIRE_91, 5, 5)
connect _WIRE_90.ppp, _T_1256
node _T_1257 = bits(_WIRE_91, 6, 6)
connect _WIRE_90.pr, _T_1257
node _T_1258 = bits(_WIRE_91, 7, 7)
connect _WIRE_90.px, _T_1258
node _T_1259 = bits(_WIRE_91, 8, 8)
connect _WIRE_90.pw, _T_1259
node _T_1260 = bits(_WIRE_91, 9, 9)
connect _WIRE_90.hr, _T_1260
node _T_1261 = bits(_WIRE_91, 10, 10)
connect _WIRE_90.hx, _T_1261
node _T_1262 = bits(_WIRE_91, 11, 11)
connect _WIRE_90.hw, _T_1262
node _T_1263 = bits(_WIRE_91, 12, 12)
connect _WIRE_90.sr, _T_1263
node _T_1264 = bits(_WIRE_91, 13, 13)
connect _WIRE_90.sx, _T_1264
node _T_1265 = bits(_WIRE_91, 14, 14)
connect _WIRE_90.sw, _T_1265
node _T_1266 = bits(_WIRE_91, 15, 15)
connect _WIRE_90.gf, _T_1266
node _T_1267 = bits(_WIRE_91, 16, 16)
connect _WIRE_90.pf, _T_1267
node _T_1268 = bits(_WIRE_91, 17, 17)
connect _WIRE_90.ae_stage2, _T_1268
node _T_1269 = bits(_WIRE_91, 18, 18)
connect _WIRE_90.ae_final, _T_1269
node _T_1270 = bits(_WIRE_91, 19, 19)
connect _WIRE_90.ae_ptw, _T_1270
node _T_1271 = bits(_WIRE_91, 20, 20)
connect _WIRE_90.g, _T_1271
node _T_1272 = bits(_WIRE_91, 21, 21)
connect _WIRE_90.u, _T_1272
node _T_1273 = bits(_WIRE_91, 41, 22)
connect _WIRE_90.ppn, _T_1273
wire _WIRE_92 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_93 : UInt<42>
connect _WIRE_93, sectored_entries[0][2].data[2]
node _T_1274 = bits(_WIRE_93, 0, 0)
connect _WIRE_92.fragmented_superpage, _T_1274
node _T_1275 = bits(_WIRE_93, 1, 1)
connect _WIRE_92.c, _T_1275
node _T_1276 = bits(_WIRE_93, 2, 2)
connect _WIRE_92.eff, _T_1276
node _T_1277 = bits(_WIRE_93, 3, 3)
connect _WIRE_92.paa, _T_1277
node _T_1278 = bits(_WIRE_93, 4, 4)
connect _WIRE_92.pal, _T_1278
node _T_1279 = bits(_WIRE_93, 5, 5)
connect _WIRE_92.ppp, _T_1279
node _T_1280 = bits(_WIRE_93, 6, 6)
connect _WIRE_92.pr, _T_1280
node _T_1281 = bits(_WIRE_93, 7, 7)
connect _WIRE_92.px, _T_1281
node _T_1282 = bits(_WIRE_93, 8, 8)
connect _WIRE_92.pw, _T_1282
node _T_1283 = bits(_WIRE_93, 9, 9)
connect _WIRE_92.hr, _T_1283
node _T_1284 = bits(_WIRE_93, 10, 10)
connect _WIRE_92.hx, _T_1284
node _T_1285 = bits(_WIRE_93, 11, 11)
connect _WIRE_92.hw, _T_1285
node _T_1286 = bits(_WIRE_93, 12, 12)
connect _WIRE_92.sr, _T_1286
node _T_1287 = bits(_WIRE_93, 13, 13)
connect _WIRE_92.sx, _T_1287
node _T_1288 = bits(_WIRE_93, 14, 14)
connect _WIRE_92.sw, _T_1288
node _T_1289 = bits(_WIRE_93, 15, 15)
connect _WIRE_92.gf, _T_1289
node _T_1290 = bits(_WIRE_93, 16, 16)
connect _WIRE_92.pf, _T_1290
node _T_1291 = bits(_WIRE_93, 17, 17)
connect _WIRE_92.ae_stage2, _T_1291
node _T_1292 = bits(_WIRE_93, 18, 18)
connect _WIRE_92.ae_final, _T_1292
node _T_1293 = bits(_WIRE_93, 19, 19)
connect _WIRE_92.ae_ptw, _T_1293
node _T_1294 = bits(_WIRE_93, 20, 20)
connect _WIRE_92.g, _T_1294
node _T_1295 = bits(_WIRE_93, 21, 21)
connect _WIRE_92.u, _T_1295
node _T_1296 = bits(_WIRE_93, 41, 22)
connect _WIRE_92.ppn, _T_1296
wire _WIRE_94 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_95 : UInt<42>
connect _WIRE_95, sectored_entries[0][2].data[3]
node _T_1297 = bits(_WIRE_95, 0, 0)
connect _WIRE_94.fragmented_superpage, _T_1297
node _T_1298 = bits(_WIRE_95, 1, 1)
connect _WIRE_94.c, _T_1298
node _T_1299 = bits(_WIRE_95, 2, 2)
connect _WIRE_94.eff, _T_1299
node _T_1300 = bits(_WIRE_95, 3, 3)
connect _WIRE_94.paa, _T_1300
node _T_1301 = bits(_WIRE_95, 4, 4)
connect _WIRE_94.pal, _T_1301
node _T_1302 = bits(_WIRE_95, 5, 5)
connect _WIRE_94.ppp, _T_1302
node _T_1303 = bits(_WIRE_95, 6, 6)
connect _WIRE_94.pr, _T_1303
node _T_1304 = bits(_WIRE_95, 7, 7)
connect _WIRE_94.px, _T_1304
node _T_1305 = bits(_WIRE_95, 8, 8)
connect _WIRE_94.pw, _T_1305
node _T_1306 = bits(_WIRE_95, 9, 9)
connect _WIRE_94.hr, _T_1306
node _T_1307 = bits(_WIRE_95, 10, 10)
connect _WIRE_94.hx, _T_1307
node _T_1308 = bits(_WIRE_95, 11, 11)
connect _WIRE_94.hw, _T_1308
node _T_1309 = bits(_WIRE_95, 12, 12)
connect _WIRE_94.sr, _T_1309
node _T_1310 = bits(_WIRE_95, 13, 13)
connect _WIRE_94.sx, _T_1310
node _T_1311 = bits(_WIRE_95, 14, 14)
connect _WIRE_94.sw, _T_1311
node _T_1312 = bits(_WIRE_95, 15, 15)
connect _WIRE_94.gf, _T_1312
node _T_1313 = bits(_WIRE_95, 16, 16)
connect _WIRE_94.pf, _T_1313
node _T_1314 = bits(_WIRE_95, 17, 17)
connect _WIRE_94.ae_stage2, _T_1314
node _T_1315 = bits(_WIRE_95, 18, 18)
connect _WIRE_94.ae_final, _T_1315
node _T_1316 = bits(_WIRE_95, 19, 19)
connect _WIRE_94.ae_ptw, _T_1316
node _T_1317 = bits(_WIRE_95, 20, 20)
connect _WIRE_94.g, _T_1317
node _T_1318 = bits(_WIRE_95, 21, 21)
connect _WIRE_94.u, _T_1318
node _T_1319 = bits(_WIRE_95, 41, 22)
connect _WIRE_94.ppn, _T_1319
node _T_1320 = eq(sectored_entries[0][2].tag_v, _T_1227)
when _T_1320 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_1321 = eq(sectored_entries[0][2].tag_v, _T_1227)
when _T_1321 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_1322 = eq(sectored_entries[0][2].tag_v, _T_1227)
when _T_1322 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_1323 = eq(sectored_entries[0][2].tag_v, _T_1227)
when _T_1323 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
node hv_3 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_3 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_1324 = eq(hg_3, UInt<1>(0h0))
node _T_1325 = and(_T_1324, io.sfence.bits.rs1)
when _T_1325 :
node _T_1326 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _T_1327 = shr(_T_1326, 2)
node _T_1328 = eq(_T_1327, UInt<1>(0h0))
node _T_1329 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1330 = and(_T_1328, _T_1329)
when _T_1330 :
wire _WIRE_96 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_97 : UInt<42>
connect _WIRE_97, sectored_entries[0][3].data[0]
node _T_1331 = bits(_WIRE_97, 0, 0)
connect _WIRE_96.fragmented_superpage, _T_1331
node _T_1332 = bits(_WIRE_97, 1, 1)
connect _WIRE_96.c, _T_1332
node _T_1333 = bits(_WIRE_97, 2, 2)
connect _WIRE_96.eff, _T_1333
node _T_1334 = bits(_WIRE_97, 3, 3)
connect _WIRE_96.paa, _T_1334
node _T_1335 = bits(_WIRE_97, 4, 4)
connect _WIRE_96.pal, _T_1335
node _T_1336 = bits(_WIRE_97, 5, 5)
connect _WIRE_96.ppp, _T_1336
node _T_1337 = bits(_WIRE_97, 6, 6)
connect _WIRE_96.pr, _T_1337
node _T_1338 = bits(_WIRE_97, 7, 7)
connect _WIRE_96.px, _T_1338
node _T_1339 = bits(_WIRE_97, 8, 8)
connect _WIRE_96.pw, _T_1339
node _T_1340 = bits(_WIRE_97, 9, 9)
connect _WIRE_96.hr, _T_1340
node _T_1341 = bits(_WIRE_97, 10, 10)
connect _WIRE_96.hx, _T_1341
node _T_1342 = bits(_WIRE_97, 11, 11)
connect _WIRE_96.hw, _T_1342
node _T_1343 = bits(_WIRE_97, 12, 12)
connect _WIRE_96.sr, _T_1343
node _T_1344 = bits(_WIRE_97, 13, 13)
connect _WIRE_96.sx, _T_1344
node _T_1345 = bits(_WIRE_97, 14, 14)
connect _WIRE_96.sw, _T_1345
node _T_1346 = bits(_WIRE_97, 15, 15)
connect _WIRE_96.gf, _T_1346
node _T_1347 = bits(_WIRE_97, 16, 16)
connect _WIRE_96.pf, _T_1347
node _T_1348 = bits(_WIRE_97, 17, 17)
connect _WIRE_96.ae_stage2, _T_1348
node _T_1349 = bits(_WIRE_97, 18, 18)
connect _WIRE_96.ae_final, _T_1349
node _T_1350 = bits(_WIRE_97, 19, 19)
connect _WIRE_96.ae_ptw, _T_1350
node _T_1351 = bits(_WIRE_97, 20, 20)
connect _WIRE_96.g, _T_1351
node _T_1352 = bits(_WIRE_97, 21, 21)
connect _WIRE_96.u, _T_1352
node _T_1353 = bits(_WIRE_97, 41, 22)
connect _WIRE_96.ppn, _T_1353
wire _WIRE_98 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_99 : UInt<42>
connect _WIRE_99, sectored_entries[0][3].data[1]
node _T_1354 = bits(_WIRE_99, 0, 0)
connect _WIRE_98.fragmented_superpage, _T_1354
node _T_1355 = bits(_WIRE_99, 1, 1)
connect _WIRE_98.c, _T_1355
node _T_1356 = bits(_WIRE_99, 2, 2)
connect _WIRE_98.eff, _T_1356
node _T_1357 = bits(_WIRE_99, 3, 3)
connect _WIRE_98.paa, _T_1357
node _T_1358 = bits(_WIRE_99, 4, 4)
connect _WIRE_98.pal, _T_1358
node _T_1359 = bits(_WIRE_99, 5, 5)
connect _WIRE_98.ppp, _T_1359
node _T_1360 = bits(_WIRE_99, 6, 6)
connect _WIRE_98.pr, _T_1360
node _T_1361 = bits(_WIRE_99, 7, 7)
connect _WIRE_98.px, _T_1361
node _T_1362 = bits(_WIRE_99, 8, 8)
connect _WIRE_98.pw, _T_1362
node _T_1363 = bits(_WIRE_99, 9, 9)
connect _WIRE_98.hr, _T_1363
node _T_1364 = bits(_WIRE_99, 10, 10)
connect _WIRE_98.hx, _T_1364
node _T_1365 = bits(_WIRE_99, 11, 11)
connect _WIRE_98.hw, _T_1365
node _T_1366 = bits(_WIRE_99, 12, 12)
connect _WIRE_98.sr, _T_1366
node _T_1367 = bits(_WIRE_99, 13, 13)
connect _WIRE_98.sx, _T_1367
node _T_1368 = bits(_WIRE_99, 14, 14)
connect _WIRE_98.sw, _T_1368
node _T_1369 = bits(_WIRE_99, 15, 15)
connect _WIRE_98.gf, _T_1369
node _T_1370 = bits(_WIRE_99, 16, 16)
connect _WIRE_98.pf, _T_1370
node _T_1371 = bits(_WIRE_99, 17, 17)
connect _WIRE_98.ae_stage2, _T_1371
node _T_1372 = bits(_WIRE_99, 18, 18)
connect _WIRE_98.ae_final, _T_1372
node _T_1373 = bits(_WIRE_99, 19, 19)
connect _WIRE_98.ae_ptw, _T_1373
node _T_1374 = bits(_WIRE_99, 20, 20)
connect _WIRE_98.g, _T_1374
node _T_1375 = bits(_WIRE_99, 21, 21)
connect _WIRE_98.u, _T_1375
node _T_1376 = bits(_WIRE_99, 41, 22)
connect _WIRE_98.ppn, _T_1376
wire _WIRE_100 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_101 : UInt<42>
connect _WIRE_101, sectored_entries[0][3].data[2]
node _T_1377 = bits(_WIRE_101, 0, 0)
connect _WIRE_100.fragmented_superpage, _T_1377
node _T_1378 = bits(_WIRE_101, 1, 1)
connect _WIRE_100.c, _T_1378
node _T_1379 = bits(_WIRE_101, 2, 2)
connect _WIRE_100.eff, _T_1379
node _T_1380 = bits(_WIRE_101, 3, 3)
connect _WIRE_100.paa, _T_1380
node _T_1381 = bits(_WIRE_101, 4, 4)
connect _WIRE_100.pal, _T_1381
node _T_1382 = bits(_WIRE_101, 5, 5)
connect _WIRE_100.ppp, _T_1382
node _T_1383 = bits(_WIRE_101, 6, 6)
connect _WIRE_100.pr, _T_1383
node _T_1384 = bits(_WIRE_101, 7, 7)
connect _WIRE_100.px, _T_1384
node _T_1385 = bits(_WIRE_101, 8, 8)
connect _WIRE_100.pw, _T_1385
node _T_1386 = bits(_WIRE_101, 9, 9)
connect _WIRE_100.hr, _T_1386
node _T_1387 = bits(_WIRE_101, 10, 10)
connect _WIRE_100.hx, _T_1387
node _T_1388 = bits(_WIRE_101, 11, 11)
connect _WIRE_100.hw, _T_1388
node _T_1389 = bits(_WIRE_101, 12, 12)
connect _WIRE_100.sr, _T_1389
node _T_1390 = bits(_WIRE_101, 13, 13)
connect _WIRE_100.sx, _T_1390
node _T_1391 = bits(_WIRE_101, 14, 14)
connect _WIRE_100.sw, _T_1391
node _T_1392 = bits(_WIRE_101, 15, 15)
connect _WIRE_100.gf, _T_1392
node _T_1393 = bits(_WIRE_101, 16, 16)
connect _WIRE_100.pf, _T_1393
node _T_1394 = bits(_WIRE_101, 17, 17)
connect _WIRE_100.ae_stage2, _T_1394
node _T_1395 = bits(_WIRE_101, 18, 18)
connect _WIRE_100.ae_final, _T_1395
node _T_1396 = bits(_WIRE_101, 19, 19)
connect _WIRE_100.ae_ptw, _T_1396
node _T_1397 = bits(_WIRE_101, 20, 20)
connect _WIRE_100.g, _T_1397
node _T_1398 = bits(_WIRE_101, 21, 21)
connect _WIRE_100.u, _T_1398
node _T_1399 = bits(_WIRE_101, 41, 22)
connect _WIRE_100.ppn, _T_1399
wire _WIRE_102 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_103 : UInt<42>
connect _WIRE_103, sectored_entries[0][3].data[3]
node _T_1400 = bits(_WIRE_103, 0, 0)
connect _WIRE_102.fragmented_superpage, _T_1400
node _T_1401 = bits(_WIRE_103, 1, 1)
connect _WIRE_102.c, _T_1401
node _T_1402 = bits(_WIRE_103, 2, 2)
connect _WIRE_102.eff, _T_1402
node _T_1403 = bits(_WIRE_103, 3, 3)
connect _WIRE_102.paa, _T_1403
node _T_1404 = bits(_WIRE_103, 4, 4)
connect _WIRE_102.pal, _T_1404
node _T_1405 = bits(_WIRE_103, 5, 5)
connect _WIRE_102.ppp, _T_1405
node _T_1406 = bits(_WIRE_103, 6, 6)
connect _WIRE_102.pr, _T_1406
node _T_1407 = bits(_WIRE_103, 7, 7)
connect _WIRE_102.px, _T_1407
node _T_1408 = bits(_WIRE_103, 8, 8)
connect _WIRE_102.pw, _T_1408
node _T_1409 = bits(_WIRE_103, 9, 9)
connect _WIRE_102.hr, _T_1409
node _T_1410 = bits(_WIRE_103, 10, 10)
connect _WIRE_102.hx, _T_1410
node _T_1411 = bits(_WIRE_103, 11, 11)
connect _WIRE_102.hw, _T_1411
node _T_1412 = bits(_WIRE_103, 12, 12)
connect _WIRE_102.sr, _T_1412
node _T_1413 = bits(_WIRE_103, 13, 13)
connect _WIRE_102.sx, _T_1413
node _T_1414 = bits(_WIRE_103, 14, 14)
connect _WIRE_102.sw, _T_1414
node _T_1415 = bits(_WIRE_103, 15, 15)
connect _WIRE_102.gf, _T_1415
node _T_1416 = bits(_WIRE_103, 16, 16)
connect _WIRE_102.pf, _T_1416
node _T_1417 = bits(_WIRE_103, 17, 17)
connect _WIRE_102.ae_stage2, _T_1417
node _T_1418 = bits(_WIRE_103, 18, 18)
connect _WIRE_102.ae_final, _T_1418
node _T_1419 = bits(_WIRE_103, 19, 19)
connect _WIRE_102.ae_ptw, _T_1419
node _T_1420 = bits(_WIRE_103, 20, 20)
connect _WIRE_102.g, _T_1420
node _T_1421 = bits(_WIRE_103, 21, 21)
connect _WIRE_102.u, _T_1421
node _T_1422 = bits(_WIRE_103, 41, 22)
connect _WIRE_102.ppn, _T_1422
node _T_1423 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1424 = bits(vpn, 1, 0)
node _T_1425 = eq(UInt<1>(0h0), _T_1424)
node _T_1426 = and(_T_1423, _T_1425)
when _T_1426 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_1427 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1428 = bits(vpn, 1, 0)
node _T_1429 = eq(UInt<1>(0h1), _T_1428)
node _T_1430 = and(_T_1427, _T_1429)
when _T_1430 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_1431 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1432 = bits(vpn, 1, 0)
node _T_1433 = eq(UInt<2>(0h2), _T_1432)
node _T_1434 = and(_T_1431, _T_1433)
when _T_1434 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_1435 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1436 = bits(vpn, 1, 0)
node _T_1437 = eq(UInt<2>(0h3), _T_1436)
node _T_1438 = and(_T_1435, _T_1437)
when _T_1438 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
node _T_1439 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _T_1440 = shr(_T_1439, 18)
node _T_1441 = eq(_T_1440, UInt<1>(0h0))
when _T_1441 :
wire _WIRE_104 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_105 : UInt<42>
connect _WIRE_105, sectored_entries[0][3].data[0]
node _T_1442 = bits(_WIRE_105, 0, 0)
connect _WIRE_104.fragmented_superpage, _T_1442
node _T_1443 = bits(_WIRE_105, 1, 1)
connect _WIRE_104.c, _T_1443
node _T_1444 = bits(_WIRE_105, 2, 2)
connect _WIRE_104.eff, _T_1444
node _T_1445 = bits(_WIRE_105, 3, 3)
connect _WIRE_104.paa, _T_1445
node _T_1446 = bits(_WIRE_105, 4, 4)
connect _WIRE_104.pal, _T_1446
node _T_1447 = bits(_WIRE_105, 5, 5)
connect _WIRE_104.ppp, _T_1447
node _T_1448 = bits(_WIRE_105, 6, 6)
connect _WIRE_104.pr, _T_1448
node _T_1449 = bits(_WIRE_105, 7, 7)
connect _WIRE_104.px, _T_1449
node _T_1450 = bits(_WIRE_105, 8, 8)
connect _WIRE_104.pw, _T_1450
node _T_1451 = bits(_WIRE_105, 9, 9)
connect _WIRE_104.hr, _T_1451
node _T_1452 = bits(_WIRE_105, 10, 10)
connect _WIRE_104.hx, _T_1452
node _T_1453 = bits(_WIRE_105, 11, 11)
connect _WIRE_104.hw, _T_1453
node _T_1454 = bits(_WIRE_105, 12, 12)
connect _WIRE_104.sr, _T_1454
node _T_1455 = bits(_WIRE_105, 13, 13)
connect _WIRE_104.sx, _T_1455
node _T_1456 = bits(_WIRE_105, 14, 14)
connect _WIRE_104.sw, _T_1456
node _T_1457 = bits(_WIRE_105, 15, 15)
connect _WIRE_104.gf, _T_1457
node _T_1458 = bits(_WIRE_105, 16, 16)
connect _WIRE_104.pf, _T_1458
node _T_1459 = bits(_WIRE_105, 17, 17)
connect _WIRE_104.ae_stage2, _T_1459
node _T_1460 = bits(_WIRE_105, 18, 18)
connect _WIRE_104.ae_final, _T_1460
node _T_1461 = bits(_WIRE_105, 19, 19)
connect _WIRE_104.ae_ptw, _T_1461
node _T_1462 = bits(_WIRE_105, 20, 20)
connect _WIRE_104.g, _T_1462
node _T_1463 = bits(_WIRE_105, 21, 21)
connect _WIRE_104.u, _T_1463
node _T_1464 = bits(_WIRE_105, 41, 22)
connect _WIRE_104.ppn, _T_1464
wire _WIRE_106 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_107 : UInt<42>
connect _WIRE_107, sectored_entries[0][3].data[1]
node _T_1465 = bits(_WIRE_107, 0, 0)
connect _WIRE_106.fragmented_superpage, _T_1465
node _T_1466 = bits(_WIRE_107, 1, 1)
connect _WIRE_106.c, _T_1466
node _T_1467 = bits(_WIRE_107, 2, 2)
connect _WIRE_106.eff, _T_1467
node _T_1468 = bits(_WIRE_107, 3, 3)
connect _WIRE_106.paa, _T_1468
node _T_1469 = bits(_WIRE_107, 4, 4)
connect _WIRE_106.pal, _T_1469
node _T_1470 = bits(_WIRE_107, 5, 5)
connect _WIRE_106.ppp, _T_1470
node _T_1471 = bits(_WIRE_107, 6, 6)
connect _WIRE_106.pr, _T_1471
node _T_1472 = bits(_WIRE_107, 7, 7)
connect _WIRE_106.px, _T_1472
node _T_1473 = bits(_WIRE_107, 8, 8)
connect _WIRE_106.pw, _T_1473
node _T_1474 = bits(_WIRE_107, 9, 9)
connect _WIRE_106.hr, _T_1474
node _T_1475 = bits(_WIRE_107, 10, 10)
connect _WIRE_106.hx, _T_1475
node _T_1476 = bits(_WIRE_107, 11, 11)
connect _WIRE_106.hw, _T_1476
node _T_1477 = bits(_WIRE_107, 12, 12)
connect _WIRE_106.sr, _T_1477
node _T_1478 = bits(_WIRE_107, 13, 13)
connect _WIRE_106.sx, _T_1478
node _T_1479 = bits(_WIRE_107, 14, 14)
connect _WIRE_106.sw, _T_1479
node _T_1480 = bits(_WIRE_107, 15, 15)
connect _WIRE_106.gf, _T_1480
node _T_1481 = bits(_WIRE_107, 16, 16)
connect _WIRE_106.pf, _T_1481
node _T_1482 = bits(_WIRE_107, 17, 17)
connect _WIRE_106.ae_stage2, _T_1482
node _T_1483 = bits(_WIRE_107, 18, 18)
connect _WIRE_106.ae_final, _T_1483
node _T_1484 = bits(_WIRE_107, 19, 19)
connect _WIRE_106.ae_ptw, _T_1484
node _T_1485 = bits(_WIRE_107, 20, 20)
connect _WIRE_106.g, _T_1485
node _T_1486 = bits(_WIRE_107, 21, 21)
connect _WIRE_106.u, _T_1486
node _T_1487 = bits(_WIRE_107, 41, 22)
connect _WIRE_106.ppn, _T_1487
wire _WIRE_108 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_109 : UInt<42>
connect _WIRE_109, sectored_entries[0][3].data[2]
node _T_1488 = bits(_WIRE_109, 0, 0)
connect _WIRE_108.fragmented_superpage, _T_1488
node _T_1489 = bits(_WIRE_109, 1, 1)
connect _WIRE_108.c, _T_1489
node _T_1490 = bits(_WIRE_109, 2, 2)
connect _WIRE_108.eff, _T_1490
node _T_1491 = bits(_WIRE_109, 3, 3)
connect _WIRE_108.paa, _T_1491
node _T_1492 = bits(_WIRE_109, 4, 4)
connect _WIRE_108.pal, _T_1492
node _T_1493 = bits(_WIRE_109, 5, 5)
connect _WIRE_108.ppp, _T_1493
node _T_1494 = bits(_WIRE_109, 6, 6)
connect _WIRE_108.pr, _T_1494
node _T_1495 = bits(_WIRE_109, 7, 7)
connect _WIRE_108.px, _T_1495
node _T_1496 = bits(_WIRE_109, 8, 8)
connect _WIRE_108.pw, _T_1496
node _T_1497 = bits(_WIRE_109, 9, 9)
connect _WIRE_108.hr, _T_1497
node _T_1498 = bits(_WIRE_109, 10, 10)
connect _WIRE_108.hx, _T_1498
node _T_1499 = bits(_WIRE_109, 11, 11)
connect _WIRE_108.hw, _T_1499
node _T_1500 = bits(_WIRE_109, 12, 12)
connect _WIRE_108.sr, _T_1500
node _T_1501 = bits(_WIRE_109, 13, 13)
connect _WIRE_108.sx, _T_1501
node _T_1502 = bits(_WIRE_109, 14, 14)
connect _WIRE_108.sw, _T_1502
node _T_1503 = bits(_WIRE_109, 15, 15)
connect _WIRE_108.gf, _T_1503
node _T_1504 = bits(_WIRE_109, 16, 16)
connect _WIRE_108.pf, _T_1504
node _T_1505 = bits(_WIRE_109, 17, 17)
connect _WIRE_108.ae_stage2, _T_1505
node _T_1506 = bits(_WIRE_109, 18, 18)
connect _WIRE_108.ae_final, _T_1506
node _T_1507 = bits(_WIRE_109, 19, 19)
connect _WIRE_108.ae_ptw, _T_1507
node _T_1508 = bits(_WIRE_109, 20, 20)
connect _WIRE_108.g, _T_1508
node _T_1509 = bits(_WIRE_109, 21, 21)
connect _WIRE_108.u, _T_1509
node _T_1510 = bits(_WIRE_109, 41, 22)
connect _WIRE_108.ppn, _T_1510
wire _WIRE_110 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_111 : UInt<42>
connect _WIRE_111, sectored_entries[0][3].data[3]
node _T_1511 = bits(_WIRE_111, 0, 0)
connect _WIRE_110.fragmented_superpage, _T_1511
node _T_1512 = bits(_WIRE_111, 1, 1)
connect _WIRE_110.c, _T_1512
node _T_1513 = bits(_WIRE_111, 2, 2)
connect _WIRE_110.eff, _T_1513
node _T_1514 = bits(_WIRE_111, 3, 3)
connect _WIRE_110.paa, _T_1514
node _T_1515 = bits(_WIRE_111, 4, 4)
connect _WIRE_110.pal, _T_1515
node _T_1516 = bits(_WIRE_111, 5, 5)
connect _WIRE_110.ppp, _T_1516
node _T_1517 = bits(_WIRE_111, 6, 6)
connect _WIRE_110.pr, _T_1517
node _T_1518 = bits(_WIRE_111, 7, 7)
connect _WIRE_110.px, _T_1518
node _T_1519 = bits(_WIRE_111, 8, 8)
connect _WIRE_110.pw, _T_1519
node _T_1520 = bits(_WIRE_111, 9, 9)
connect _WIRE_110.hr, _T_1520
node _T_1521 = bits(_WIRE_111, 10, 10)
connect _WIRE_110.hx, _T_1521
node _T_1522 = bits(_WIRE_111, 11, 11)
connect _WIRE_110.hw, _T_1522
node _T_1523 = bits(_WIRE_111, 12, 12)
connect _WIRE_110.sr, _T_1523
node _T_1524 = bits(_WIRE_111, 13, 13)
connect _WIRE_110.sx, _T_1524
node _T_1525 = bits(_WIRE_111, 14, 14)
connect _WIRE_110.sw, _T_1525
node _T_1526 = bits(_WIRE_111, 15, 15)
connect _WIRE_110.gf, _T_1526
node _T_1527 = bits(_WIRE_111, 16, 16)
connect _WIRE_110.pf, _T_1527
node _T_1528 = bits(_WIRE_111, 17, 17)
connect _WIRE_110.ae_stage2, _T_1528
node _T_1529 = bits(_WIRE_111, 18, 18)
connect _WIRE_110.ae_final, _T_1529
node _T_1530 = bits(_WIRE_111, 19, 19)
connect _WIRE_110.ae_ptw, _T_1530
node _T_1531 = bits(_WIRE_111, 20, 20)
connect _WIRE_110.g, _T_1531
node _T_1532 = bits(_WIRE_111, 21, 21)
connect _WIRE_110.u, _T_1532
node _T_1533 = bits(_WIRE_111, 41, 22)
connect _WIRE_110.ppn, _T_1533
node _T_1534 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1535 = and(_T_1534, _WIRE_104.fragmented_superpage)
when _T_1535 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_1536 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1537 = and(_T_1536, _WIRE_106.fragmented_superpage)
when _T_1537 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_1538 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1539 = and(_T_1538, _WIRE_108.fragmented_superpage)
when _T_1539 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_1540 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1541 = and(_T_1540, _WIRE_110.fragmented_superpage)
when _T_1541 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
else :
node _T_1542 = eq(hg_3, UInt<1>(0h0))
node _T_1543 = and(_T_1542, io.sfence.bits.rs2)
when _T_1543 :
wire _WIRE_112 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_113 : UInt<42>
connect _WIRE_113, sectored_entries[0][3].data[0]
node _T_1544 = bits(_WIRE_113, 0, 0)
connect _WIRE_112.fragmented_superpage, _T_1544
node _T_1545 = bits(_WIRE_113, 1, 1)
connect _WIRE_112.c, _T_1545
node _T_1546 = bits(_WIRE_113, 2, 2)
connect _WIRE_112.eff, _T_1546
node _T_1547 = bits(_WIRE_113, 3, 3)
connect _WIRE_112.paa, _T_1547
node _T_1548 = bits(_WIRE_113, 4, 4)
connect _WIRE_112.pal, _T_1548
node _T_1549 = bits(_WIRE_113, 5, 5)
connect _WIRE_112.ppp, _T_1549
node _T_1550 = bits(_WIRE_113, 6, 6)
connect _WIRE_112.pr, _T_1550
node _T_1551 = bits(_WIRE_113, 7, 7)
connect _WIRE_112.px, _T_1551
node _T_1552 = bits(_WIRE_113, 8, 8)
connect _WIRE_112.pw, _T_1552
node _T_1553 = bits(_WIRE_113, 9, 9)
connect _WIRE_112.hr, _T_1553
node _T_1554 = bits(_WIRE_113, 10, 10)
connect _WIRE_112.hx, _T_1554
node _T_1555 = bits(_WIRE_113, 11, 11)
connect _WIRE_112.hw, _T_1555
node _T_1556 = bits(_WIRE_113, 12, 12)
connect _WIRE_112.sr, _T_1556
node _T_1557 = bits(_WIRE_113, 13, 13)
connect _WIRE_112.sx, _T_1557
node _T_1558 = bits(_WIRE_113, 14, 14)
connect _WIRE_112.sw, _T_1558
node _T_1559 = bits(_WIRE_113, 15, 15)
connect _WIRE_112.gf, _T_1559
node _T_1560 = bits(_WIRE_113, 16, 16)
connect _WIRE_112.pf, _T_1560
node _T_1561 = bits(_WIRE_113, 17, 17)
connect _WIRE_112.ae_stage2, _T_1561
node _T_1562 = bits(_WIRE_113, 18, 18)
connect _WIRE_112.ae_final, _T_1562
node _T_1563 = bits(_WIRE_113, 19, 19)
connect _WIRE_112.ae_ptw, _T_1563
node _T_1564 = bits(_WIRE_113, 20, 20)
connect _WIRE_112.g, _T_1564
node _T_1565 = bits(_WIRE_113, 21, 21)
connect _WIRE_112.u, _T_1565
node _T_1566 = bits(_WIRE_113, 41, 22)
connect _WIRE_112.ppn, _T_1566
wire _WIRE_114 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_115 : UInt<42>
connect _WIRE_115, sectored_entries[0][3].data[1]
node _T_1567 = bits(_WIRE_115, 0, 0)
connect _WIRE_114.fragmented_superpage, _T_1567
node _T_1568 = bits(_WIRE_115, 1, 1)
connect _WIRE_114.c, _T_1568
node _T_1569 = bits(_WIRE_115, 2, 2)
connect _WIRE_114.eff, _T_1569
node _T_1570 = bits(_WIRE_115, 3, 3)
connect _WIRE_114.paa, _T_1570
node _T_1571 = bits(_WIRE_115, 4, 4)
connect _WIRE_114.pal, _T_1571
node _T_1572 = bits(_WIRE_115, 5, 5)
connect _WIRE_114.ppp, _T_1572
node _T_1573 = bits(_WIRE_115, 6, 6)
connect _WIRE_114.pr, _T_1573
node _T_1574 = bits(_WIRE_115, 7, 7)
connect _WIRE_114.px, _T_1574
node _T_1575 = bits(_WIRE_115, 8, 8)
connect _WIRE_114.pw, _T_1575
node _T_1576 = bits(_WIRE_115, 9, 9)
connect _WIRE_114.hr, _T_1576
node _T_1577 = bits(_WIRE_115, 10, 10)
connect _WIRE_114.hx, _T_1577
node _T_1578 = bits(_WIRE_115, 11, 11)
connect _WIRE_114.hw, _T_1578
node _T_1579 = bits(_WIRE_115, 12, 12)
connect _WIRE_114.sr, _T_1579
node _T_1580 = bits(_WIRE_115, 13, 13)
connect _WIRE_114.sx, _T_1580
node _T_1581 = bits(_WIRE_115, 14, 14)
connect _WIRE_114.sw, _T_1581
node _T_1582 = bits(_WIRE_115, 15, 15)
connect _WIRE_114.gf, _T_1582
node _T_1583 = bits(_WIRE_115, 16, 16)
connect _WIRE_114.pf, _T_1583
node _T_1584 = bits(_WIRE_115, 17, 17)
connect _WIRE_114.ae_stage2, _T_1584
node _T_1585 = bits(_WIRE_115, 18, 18)
connect _WIRE_114.ae_final, _T_1585
node _T_1586 = bits(_WIRE_115, 19, 19)
connect _WIRE_114.ae_ptw, _T_1586
node _T_1587 = bits(_WIRE_115, 20, 20)
connect _WIRE_114.g, _T_1587
node _T_1588 = bits(_WIRE_115, 21, 21)
connect _WIRE_114.u, _T_1588
node _T_1589 = bits(_WIRE_115, 41, 22)
connect _WIRE_114.ppn, _T_1589
wire _WIRE_116 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_117 : UInt<42>
connect _WIRE_117, sectored_entries[0][3].data[2]
node _T_1590 = bits(_WIRE_117, 0, 0)
connect _WIRE_116.fragmented_superpage, _T_1590
node _T_1591 = bits(_WIRE_117, 1, 1)
connect _WIRE_116.c, _T_1591
node _T_1592 = bits(_WIRE_117, 2, 2)
connect _WIRE_116.eff, _T_1592
node _T_1593 = bits(_WIRE_117, 3, 3)
connect _WIRE_116.paa, _T_1593
node _T_1594 = bits(_WIRE_117, 4, 4)
connect _WIRE_116.pal, _T_1594
node _T_1595 = bits(_WIRE_117, 5, 5)
connect _WIRE_116.ppp, _T_1595
node _T_1596 = bits(_WIRE_117, 6, 6)
connect _WIRE_116.pr, _T_1596
node _T_1597 = bits(_WIRE_117, 7, 7)
connect _WIRE_116.px, _T_1597
node _T_1598 = bits(_WIRE_117, 8, 8)
connect _WIRE_116.pw, _T_1598
node _T_1599 = bits(_WIRE_117, 9, 9)
connect _WIRE_116.hr, _T_1599
node _T_1600 = bits(_WIRE_117, 10, 10)
connect _WIRE_116.hx, _T_1600
node _T_1601 = bits(_WIRE_117, 11, 11)
connect _WIRE_116.hw, _T_1601
node _T_1602 = bits(_WIRE_117, 12, 12)
connect _WIRE_116.sr, _T_1602
node _T_1603 = bits(_WIRE_117, 13, 13)
connect _WIRE_116.sx, _T_1603
node _T_1604 = bits(_WIRE_117, 14, 14)
connect _WIRE_116.sw, _T_1604
node _T_1605 = bits(_WIRE_117, 15, 15)
connect _WIRE_116.gf, _T_1605
node _T_1606 = bits(_WIRE_117, 16, 16)
connect _WIRE_116.pf, _T_1606
node _T_1607 = bits(_WIRE_117, 17, 17)
connect _WIRE_116.ae_stage2, _T_1607
node _T_1608 = bits(_WIRE_117, 18, 18)
connect _WIRE_116.ae_final, _T_1608
node _T_1609 = bits(_WIRE_117, 19, 19)
connect _WIRE_116.ae_ptw, _T_1609
node _T_1610 = bits(_WIRE_117, 20, 20)
connect _WIRE_116.g, _T_1610
node _T_1611 = bits(_WIRE_117, 21, 21)
connect _WIRE_116.u, _T_1611
node _T_1612 = bits(_WIRE_117, 41, 22)
connect _WIRE_116.ppn, _T_1612
wire _WIRE_118 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_119 : UInt<42>
connect _WIRE_119, sectored_entries[0][3].data[3]
node _T_1613 = bits(_WIRE_119, 0, 0)
connect _WIRE_118.fragmented_superpage, _T_1613
node _T_1614 = bits(_WIRE_119, 1, 1)
connect _WIRE_118.c, _T_1614
node _T_1615 = bits(_WIRE_119, 2, 2)
connect _WIRE_118.eff, _T_1615
node _T_1616 = bits(_WIRE_119, 3, 3)
connect _WIRE_118.paa, _T_1616
node _T_1617 = bits(_WIRE_119, 4, 4)
connect _WIRE_118.pal, _T_1617
node _T_1618 = bits(_WIRE_119, 5, 5)
connect _WIRE_118.ppp, _T_1618
node _T_1619 = bits(_WIRE_119, 6, 6)
connect _WIRE_118.pr, _T_1619
node _T_1620 = bits(_WIRE_119, 7, 7)
connect _WIRE_118.px, _T_1620
node _T_1621 = bits(_WIRE_119, 8, 8)
connect _WIRE_118.pw, _T_1621
node _T_1622 = bits(_WIRE_119, 9, 9)
connect _WIRE_118.hr, _T_1622
node _T_1623 = bits(_WIRE_119, 10, 10)
connect _WIRE_118.hx, _T_1623
node _T_1624 = bits(_WIRE_119, 11, 11)
connect _WIRE_118.hw, _T_1624
node _T_1625 = bits(_WIRE_119, 12, 12)
connect _WIRE_118.sr, _T_1625
node _T_1626 = bits(_WIRE_119, 13, 13)
connect _WIRE_118.sx, _T_1626
node _T_1627 = bits(_WIRE_119, 14, 14)
connect _WIRE_118.sw, _T_1627
node _T_1628 = bits(_WIRE_119, 15, 15)
connect _WIRE_118.gf, _T_1628
node _T_1629 = bits(_WIRE_119, 16, 16)
connect _WIRE_118.pf, _T_1629
node _T_1630 = bits(_WIRE_119, 17, 17)
connect _WIRE_118.ae_stage2, _T_1630
node _T_1631 = bits(_WIRE_119, 18, 18)
connect _WIRE_118.ae_final, _T_1631
node _T_1632 = bits(_WIRE_119, 19, 19)
connect _WIRE_118.ae_ptw, _T_1632
node _T_1633 = bits(_WIRE_119, 20, 20)
connect _WIRE_118.g, _T_1633
node _T_1634 = bits(_WIRE_119, 21, 21)
connect _WIRE_118.u, _T_1634
node _T_1635 = bits(_WIRE_119, 41, 22)
connect _WIRE_118.ppn, _T_1635
node _T_1636 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1637 = eq(_WIRE_112.g, UInt<1>(0h0))
node _T_1638 = and(_T_1636, _T_1637)
when _T_1638 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_1639 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1640 = eq(_WIRE_114.g, UInt<1>(0h0))
node _T_1641 = and(_T_1639, _T_1640)
when _T_1641 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_1642 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1643 = eq(_WIRE_116.g, UInt<1>(0h0))
node _T_1644 = and(_T_1642, _T_1643)
when _T_1644 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_1645 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1646 = eq(_WIRE_118.g, UInt<1>(0h0))
node _T_1647 = and(_T_1645, _T_1646)
when _T_1647 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
else :
node _T_1648 = or(hv_3, hg_3)
wire _WIRE_120 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_121 : UInt<42>
connect _WIRE_121, sectored_entries[0][3].data[0]
node _T_1649 = bits(_WIRE_121, 0, 0)
connect _WIRE_120.fragmented_superpage, _T_1649
node _T_1650 = bits(_WIRE_121, 1, 1)
connect _WIRE_120.c, _T_1650
node _T_1651 = bits(_WIRE_121, 2, 2)
connect _WIRE_120.eff, _T_1651
node _T_1652 = bits(_WIRE_121, 3, 3)
connect _WIRE_120.paa, _T_1652
node _T_1653 = bits(_WIRE_121, 4, 4)
connect _WIRE_120.pal, _T_1653
node _T_1654 = bits(_WIRE_121, 5, 5)
connect _WIRE_120.ppp, _T_1654
node _T_1655 = bits(_WIRE_121, 6, 6)
connect _WIRE_120.pr, _T_1655
node _T_1656 = bits(_WIRE_121, 7, 7)
connect _WIRE_120.px, _T_1656
node _T_1657 = bits(_WIRE_121, 8, 8)
connect _WIRE_120.pw, _T_1657
node _T_1658 = bits(_WIRE_121, 9, 9)
connect _WIRE_120.hr, _T_1658
node _T_1659 = bits(_WIRE_121, 10, 10)
connect _WIRE_120.hx, _T_1659
node _T_1660 = bits(_WIRE_121, 11, 11)
connect _WIRE_120.hw, _T_1660
node _T_1661 = bits(_WIRE_121, 12, 12)
connect _WIRE_120.sr, _T_1661
node _T_1662 = bits(_WIRE_121, 13, 13)
connect _WIRE_120.sx, _T_1662
node _T_1663 = bits(_WIRE_121, 14, 14)
connect _WIRE_120.sw, _T_1663
node _T_1664 = bits(_WIRE_121, 15, 15)
connect _WIRE_120.gf, _T_1664
node _T_1665 = bits(_WIRE_121, 16, 16)
connect _WIRE_120.pf, _T_1665
node _T_1666 = bits(_WIRE_121, 17, 17)
connect _WIRE_120.ae_stage2, _T_1666
node _T_1667 = bits(_WIRE_121, 18, 18)
connect _WIRE_120.ae_final, _T_1667
node _T_1668 = bits(_WIRE_121, 19, 19)
connect _WIRE_120.ae_ptw, _T_1668
node _T_1669 = bits(_WIRE_121, 20, 20)
connect _WIRE_120.g, _T_1669
node _T_1670 = bits(_WIRE_121, 21, 21)
connect _WIRE_120.u, _T_1670
node _T_1671 = bits(_WIRE_121, 41, 22)
connect _WIRE_120.ppn, _T_1671
wire _WIRE_122 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_123 : UInt<42>
connect _WIRE_123, sectored_entries[0][3].data[1]
node _T_1672 = bits(_WIRE_123, 0, 0)
connect _WIRE_122.fragmented_superpage, _T_1672
node _T_1673 = bits(_WIRE_123, 1, 1)
connect _WIRE_122.c, _T_1673
node _T_1674 = bits(_WIRE_123, 2, 2)
connect _WIRE_122.eff, _T_1674
node _T_1675 = bits(_WIRE_123, 3, 3)
connect _WIRE_122.paa, _T_1675
node _T_1676 = bits(_WIRE_123, 4, 4)
connect _WIRE_122.pal, _T_1676
node _T_1677 = bits(_WIRE_123, 5, 5)
connect _WIRE_122.ppp, _T_1677
node _T_1678 = bits(_WIRE_123, 6, 6)
connect _WIRE_122.pr, _T_1678
node _T_1679 = bits(_WIRE_123, 7, 7)
connect _WIRE_122.px, _T_1679
node _T_1680 = bits(_WIRE_123, 8, 8)
connect _WIRE_122.pw, _T_1680
node _T_1681 = bits(_WIRE_123, 9, 9)
connect _WIRE_122.hr, _T_1681
node _T_1682 = bits(_WIRE_123, 10, 10)
connect _WIRE_122.hx, _T_1682
node _T_1683 = bits(_WIRE_123, 11, 11)
connect _WIRE_122.hw, _T_1683
node _T_1684 = bits(_WIRE_123, 12, 12)
connect _WIRE_122.sr, _T_1684
node _T_1685 = bits(_WIRE_123, 13, 13)
connect _WIRE_122.sx, _T_1685
node _T_1686 = bits(_WIRE_123, 14, 14)
connect _WIRE_122.sw, _T_1686
node _T_1687 = bits(_WIRE_123, 15, 15)
connect _WIRE_122.gf, _T_1687
node _T_1688 = bits(_WIRE_123, 16, 16)
connect _WIRE_122.pf, _T_1688
node _T_1689 = bits(_WIRE_123, 17, 17)
connect _WIRE_122.ae_stage2, _T_1689
node _T_1690 = bits(_WIRE_123, 18, 18)
connect _WIRE_122.ae_final, _T_1690
node _T_1691 = bits(_WIRE_123, 19, 19)
connect _WIRE_122.ae_ptw, _T_1691
node _T_1692 = bits(_WIRE_123, 20, 20)
connect _WIRE_122.g, _T_1692
node _T_1693 = bits(_WIRE_123, 21, 21)
connect _WIRE_122.u, _T_1693
node _T_1694 = bits(_WIRE_123, 41, 22)
connect _WIRE_122.ppn, _T_1694
wire _WIRE_124 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_125 : UInt<42>
connect _WIRE_125, sectored_entries[0][3].data[2]
node _T_1695 = bits(_WIRE_125, 0, 0)
connect _WIRE_124.fragmented_superpage, _T_1695
node _T_1696 = bits(_WIRE_125, 1, 1)
connect _WIRE_124.c, _T_1696
node _T_1697 = bits(_WIRE_125, 2, 2)
connect _WIRE_124.eff, _T_1697
node _T_1698 = bits(_WIRE_125, 3, 3)
connect _WIRE_124.paa, _T_1698
node _T_1699 = bits(_WIRE_125, 4, 4)
connect _WIRE_124.pal, _T_1699
node _T_1700 = bits(_WIRE_125, 5, 5)
connect _WIRE_124.ppp, _T_1700
node _T_1701 = bits(_WIRE_125, 6, 6)
connect _WIRE_124.pr, _T_1701
node _T_1702 = bits(_WIRE_125, 7, 7)
connect _WIRE_124.px, _T_1702
node _T_1703 = bits(_WIRE_125, 8, 8)
connect _WIRE_124.pw, _T_1703
node _T_1704 = bits(_WIRE_125, 9, 9)
connect _WIRE_124.hr, _T_1704
node _T_1705 = bits(_WIRE_125, 10, 10)
connect _WIRE_124.hx, _T_1705
node _T_1706 = bits(_WIRE_125, 11, 11)
connect _WIRE_124.hw, _T_1706
node _T_1707 = bits(_WIRE_125, 12, 12)
connect _WIRE_124.sr, _T_1707
node _T_1708 = bits(_WIRE_125, 13, 13)
connect _WIRE_124.sx, _T_1708
node _T_1709 = bits(_WIRE_125, 14, 14)
connect _WIRE_124.sw, _T_1709
node _T_1710 = bits(_WIRE_125, 15, 15)
connect _WIRE_124.gf, _T_1710
node _T_1711 = bits(_WIRE_125, 16, 16)
connect _WIRE_124.pf, _T_1711
node _T_1712 = bits(_WIRE_125, 17, 17)
connect _WIRE_124.ae_stage2, _T_1712
node _T_1713 = bits(_WIRE_125, 18, 18)
connect _WIRE_124.ae_final, _T_1713
node _T_1714 = bits(_WIRE_125, 19, 19)
connect _WIRE_124.ae_ptw, _T_1714
node _T_1715 = bits(_WIRE_125, 20, 20)
connect _WIRE_124.g, _T_1715
node _T_1716 = bits(_WIRE_125, 21, 21)
connect _WIRE_124.u, _T_1716
node _T_1717 = bits(_WIRE_125, 41, 22)
connect _WIRE_124.ppn, _T_1717
wire _WIRE_126 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_127 : UInt<42>
connect _WIRE_127, sectored_entries[0][3].data[3]
node _T_1718 = bits(_WIRE_127, 0, 0)
connect _WIRE_126.fragmented_superpage, _T_1718
node _T_1719 = bits(_WIRE_127, 1, 1)
connect _WIRE_126.c, _T_1719
node _T_1720 = bits(_WIRE_127, 2, 2)
connect _WIRE_126.eff, _T_1720
node _T_1721 = bits(_WIRE_127, 3, 3)
connect _WIRE_126.paa, _T_1721
node _T_1722 = bits(_WIRE_127, 4, 4)
connect _WIRE_126.pal, _T_1722
node _T_1723 = bits(_WIRE_127, 5, 5)
connect _WIRE_126.ppp, _T_1723
node _T_1724 = bits(_WIRE_127, 6, 6)
connect _WIRE_126.pr, _T_1724
node _T_1725 = bits(_WIRE_127, 7, 7)
connect _WIRE_126.px, _T_1725
node _T_1726 = bits(_WIRE_127, 8, 8)
connect _WIRE_126.pw, _T_1726
node _T_1727 = bits(_WIRE_127, 9, 9)
connect _WIRE_126.hr, _T_1727
node _T_1728 = bits(_WIRE_127, 10, 10)
connect _WIRE_126.hx, _T_1728
node _T_1729 = bits(_WIRE_127, 11, 11)
connect _WIRE_126.hw, _T_1729
node _T_1730 = bits(_WIRE_127, 12, 12)
connect _WIRE_126.sr, _T_1730
node _T_1731 = bits(_WIRE_127, 13, 13)
connect _WIRE_126.sx, _T_1731
node _T_1732 = bits(_WIRE_127, 14, 14)
connect _WIRE_126.sw, _T_1732
node _T_1733 = bits(_WIRE_127, 15, 15)
connect _WIRE_126.gf, _T_1733
node _T_1734 = bits(_WIRE_127, 16, 16)
connect _WIRE_126.pf, _T_1734
node _T_1735 = bits(_WIRE_127, 17, 17)
connect _WIRE_126.ae_stage2, _T_1735
node _T_1736 = bits(_WIRE_127, 18, 18)
connect _WIRE_126.ae_final, _T_1736
node _T_1737 = bits(_WIRE_127, 19, 19)
connect _WIRE_126.ae_ptw, _T_1737
node _T_1738 = bits(_WIRE_127, 20, 20)
connect _WIRE_126.g, _T_1738
node _T_1739 = bits(_WIRE_127, 21, 21)
connect _WIRE_126.u, _T_1739
node _T_1740 = bits(_WIRE_127, 41, 22)
connect _WIRE_126.ppn, _T_1740
node _T_1741 = eq(sectored_entries[0][3].tag_v, _T_1648)
when _T_1741 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_1742 = eq(sectored_entries[0][3].tag_v, _T_1648)
when _T_1742 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_1743 = eq(sectored_entries[0][3].tag_v, _T_1648)
when _T_1743 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_1744 = eq(sectored_entries[0][3].tag_v, _T_1648)
when _T_1744 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
node hv_4 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_4 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_1745 = eq(hg_4, UInt<1>(0h0))
node _T_1746 = and(_T_1745, io.sfence.bits.rs1)
when _T_1746 :
node _T_1747 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _T_1748 = shr(_T_1747, 2)
node _T_1749 = eq(_T_1748, UInt<1>(0h0))
node _T_1750 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1751 = and(_T_1749, _T_1750)
when _T_1751 :
wire _WIRE_128 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_129 : UInt<42>
connect _WIRE_129, sectored_entries[0][4].data[0]
node _T_1752 = bits(_WIRE_129, 0, 0)
connect _WIRE_128.fragmented_superpage, _T_1752
node _T_1753 = bits(_WIRE_129, 1, 1)
connect _WIRE_128.c, _T_1753
node _T_1754 = bits(_WIRE_129, 2, 2)
connect _WIRE_128.eff, _T_1754
node _T_1755 = bits(_WIRE_129, 3, 3)
connect _WIRE_128.paa, _T_1755
node _T_1756 = bits(_WIRE_129, 4, 4)
connect _WIRE_128.pal, _T_1756
node _T_1757 = bits(_WIRE_129, 5, 5)
connect _WIRE_128.ppp, _T_1757
node _T_1758 = bits(_WIRE_129, 6, 6)
connect _WIRE_128.pr, _T_1758
node _T_1759 = bits(_WIRE_129, 7, 7)
connect _WIRE_128.px, _T_1759
node _T_1760 = bits(_WIRE_129, 8, 8)
connect _WIRE_128.pw, _T_1760
node _T_1761 = bits(_WIRE_129, 9, 9)
connect _WIRE_128.hr, _T_1761
node _T_1762 = bits(_WIRE_129, 10, 10)
connect _WIRE_128.hx, _T_1762
node _T_1763 = bits(_WIRE_129, 11, 11)
connect _WIRE_128.hw, _T_1763
node _T_1764 = bits(_WIRE_129, 12, 12)
connect _WIRE_128.sr, _T_1764
node _T_1765 = bits(_WIRE_129, 13, 13)
connect _WIRE_128.sx, _T_1765
node _T_1766 = bits(_WIRE_129, 14, 14)
connect _WIRE_128.sw, _T_1766
node _T_1767 = bits(_WIRE_129, 15, 15)
connect _WIRE_128.gf, _T_1767
node _T_1768 = bits(_WIRE_129, 16, 16)
connect _WIRE_128.pf, _T_1768
node _T_1769 = bits(_WIRE_129, 17, 17)
connect _WIRE_128.ae_stage2, _T_1769
node _T_1770 = bits(_WIRE_129, 18, 18)
connect _WIRE_128.ae_final, _T_1770
node _T_1771 = bits(_WIRE_129, 19, 19)
connect _WIRE_128.ae_ptw, _T_1771
node _T_1772 = bits(_WIRE_129, 20, 20)
connect _WIRE_128.g, _T_1772
node _T_1773 = bits(_WIRE_129, 21, 21)
connect _WIRE_128.u, _T_1773
node _T_1774 = bits(_WIRE_129, 41, 22)
connect _WIRE_128.ppn, _T_1774
wire _WIRE_130 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_131 : UInt<42>
connect _WIRE_131, sectored_entries[0][4].data[1]
node _T_1775 = bits(_WIRE_131, 0, 0)
connect _WIRE_130.fragmented_superpage, _T_1775
node _T_1776 = bits(_WIRE_131, 1, 1)
connect _WIRE_130.c, _T_1776
node _T_1777 = bits(_WIRE_131, 2, 2)
connect _WIRE_130.eff, _T_1777
node _T_1778 = bits(_WIRE_131, 3, 3)
connect _WIRE_130.paa, _T_1778
node _T_1779 = bits(_WIRE_131, 4, 4)
connect _WIRE_130.pal, _T_1779
node _T_1780 = bits(_WIRE_131, 5, 5)
connect _WIRE_130.ppp, _T_1780
node _T_1781 = bits(_WIRE_131, 6, 6)
connect _WIRE_130.pr, _T_1781
node _T_1782 = bits(_WIRE_131, 7, 7)
connect _WIRE_130.px, _T_1782
node _T_1783 = bits(_WIRE_131, 8, 8)
connect _WIRE_130.pw, _T_1783
node _T_1784 = bits(_WIRE_131, 9, 9)
connect _WIRE_130.hr, _T_1784
node _T_1785 = bits(_WIRE_131, 10, 10)
connect _WIRE_130.hx, _T_1785
node _T_1786 = bits(_WIRE_131, 11, 11)
connect _WIRE_130.hw, _T_1786
node _T_1787 = bits(_WIRE_131, 12, 12)
connect _WIRE_130.sr, _T_1787
node _T_1788 = bits(_WIRE_131, 13, 13)
connect _WIRE_130.sx, _T_1788
node _T_1789 = bits(_WIRE_131, 14, 14)
connect _WIRE_130.sw, _T_1789
node _T_1790 = bits(_WIRE_131, 15, 15)
connect _WIRE_130.gf, _T_1790
node _T_1791 = bits(_WIRE_131, 16, 16)
connect _WIRE_130.pf, _T_1791
node _T_1792 = bits(_WIRE_131, 17, 17)
connect _WIRE_130.ae_stage2, _T_1792
node _T_1793 = bits(_WIRE_131, 18, 18)
connect _WIRE_130.ae_final, _T_1793
node _T_1794 = bits(_WIRE_131, 19, 19)
connect _WIRE_130.ae_ptw, _T_1794
node _T_1795 = bits(_WIRE_131, 20, 20)
connect _WIRE_130.g, _T_1795
node _T_1796 = bits(_WIRE_131, 21, 21)
connect _WIRE_130.u, _T_1796
node _T_1797 = bits(_WIRE_131, 41, 22)
connect _WIRE_130.ppn, _T_1797
wire _WIRE_132 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_133 : UInt<42>
connect _WIRE_133, sectored_entries[0][4].data[2]
node _T_1798 = bits(_WIRE_133, 0, 0)
connect _WIRE_132.fragmented_superpage, _T_1798
node _T_1799 = bits(_WIRE_133, 1, 1)
connect _WIRE_132.c, _T_1799
node _T_1800 = bits(_WIRE_133, 2, 2)
connect _WIRE_132.eff, _T_1800
node _T_1801 = bits(_WIRE_133, 3, 3)
connect _WIRE_132.paa, _T_1801
node _T_1802 = bits(_WIRE_133, 4, 4)
connect _WIRE_132.pal, _T_1802
node _T_1803 = bits(_WIRE_133, 5, 5)
connect _WIRE_132.ppp, _T_1803
node _T_1804 = bits(_WIRE_133, 6, 6)
connect _WIRE_132.pr, _T_1804
node _T_1805 = bits(_WIRE_133, 7, 7)
connect _WIRE_132.px, _T_1805
node _T_1806 = bits(_WIRE_133, 8, 8)
connect _WIRE_132.pw, _T_1806
node _T_1807 = bits(_WIRE_133, 9, 9)
connect _WIRE_132.hr, _T_1807
node _T_1808 = bits(_WIRE_133, 10, 10)
connect _WIRE_132.hx, _T_1808
node _T_1809 = bits(_WIRE_133, 11, 11)
connect _WIRE_132.hw, _T_1809
node _T_1810 = bits(_WIRE_133, 12, 12)
connect _WIRE_132.sr, _T_1810
node _T_1811 = bits(_WIRE_133, 13, 13)
connect _WIRE_132.sx, _T_1811
node _T_1812 = bits(_WIRE_133, 14, 14)
connect _WIRE_132.sw, _T_1812
node _T_1813 = bits(_WIRE_133, 15, 15)
connect _WIRE_132.gf, _T_1813
node _T_1814 = bits(_WIRE_133, 16, 16)
connect _WIRE_132.pf, _T_1814
node _T_1815 = bits(_WIRE_133, 17, 17)
connect _WIRE_132.ae_stage2, _T_1815
node _T_1816 = bits(_WIRE_133, 18, 18)
connect _WIRE_132.ae_final, _T_1816
node _T_1817 = bits(_WIRE_133, 19, 19)
connect _WIRE_132.ae_ptw, _T_1817
node _T_1818 = bits(_WIRE_133, 20, 20)
connect _WIRE_132.g, _T_1818
node _T_1819 = bits(_WIRE_133, 21, 21)
connect _WIRE_132.u, _T_1819
node _T_1820 = bits(_WIRE_133, 41, 22)
connect _WIRE_132.ppn, _T_1820
wire _WIRE_134 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_135 : UInt<42>
connect _WIRE_135, sectored_entries[0][4].data[3]
node _T_1821 = bits(_WIRE_135, 0, 0)
connect _WIRE_134.fragmented_superpage, _T_1821
node _T_1822 = bits(_WIRE_135, 1, 1)
connect _WIRE_134.c, _T_1822
node _T_1823 = bits(_WIRE_135, 2, 2)
connect _WIRE_134.eff, _T_1823
node _T_1824 = bits(_WIRE_135, 3, 3)
connect _WIRE_134.paa, _T_1824
node _T_1825 = bits(_WIRE_135, 4, 4)
connect _WIRE_134.pal, _T_1825
node _T_1826 = bits(_WIRE_135, 5, 5)
connect _WIRE_134.ppp, _T_1826
node _T_1827 = bits(_WIRE_135, 6, 6)
connect _WIRE_134.pr, _T_1827
node _T_1828 = bits(_WIRE_135, 7, 7)
connect _WIRE_134.px, _T_1828
node _T_1829 = bits(_WIRE_135, 8, 8)
connect _WIRE_134.pw, _T_1829
node _T_1830 = bits(_WIRE_135, 9, 9)
connect _WIRE_134.hr, _T_1830
node _T_1831 = bits(_WIRE_135, 10, 10)
connect _WIRE_134.hx, _T_1831
node _T_1832 = bits(_WIRE_135, 11, 11)
connect _WIRE_134.hw, _T_1832
node _T_1833 = bits(_WIRE_135, 12, 12)
connect _WIRE_134.sr, _T_1833
node _T_1834 = bits(_WIRE_135, 13, 13)
connect _WIRE_134.sx, _T_1834
node _T_1835 = bits(_WIRE_135, 14, 14)
connect _WIRE_134.sw, _T_1835
node _T_1836 = bits(_WIRE_135, 15, 15)
connect _WIRE_134.gf, _T_1836
node _T_1837 = bits(_WIRE_135, 16, 16)
connect _WIRE_134.pf, _T_1837
node _T_1838 = bits(_WIRE_135, 17, 17)
connect _WIRE_134.ae_stage2, _T_1838
node _T_1839 = bits(_WIRE_135, 18, 18)
connect _WIRE_134.ae_final, _T_1839
node _T_1840 = bits(_WIRE_135, 19, 19)
connect _WIRE_134.ae_ptw, _T_1840
node _T_1841 = bits(_WIRE_135, 20, 20)
connect _WIRE_134.g, _T_1841
node _T_1842 = bits(_WIRE_135, 21, 21)
connect _WIRE_134.u, _T_1842
node _T_1843 = bits(_WIRE_135, 41, 22)
connect _WIRE_134.ppn, _T_1843
node _T_1844 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1845 = bits(vpn, 1, 0)
node _T_1846 = eq(UInt<1>(0h0), _T_1845)
node _T_1847 = and(_T_1844, _T_1846)
when _T_1847 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_1848 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1849 = bits(vpn, 1, 0)
node _T_1850 = eq(UInt<1>(0h1), _T_1849)
node _T_1851 = and(_T_1848, _T_1850)
when _T_1851 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_1852 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1853 = bits(vpn, 1, 0)
node _T_1854 = eq(UInt<2>(0h2), _T_1853)
node _T_1855 = and(_T_1852, _T_1854)
when _T_1855 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_1856 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1857 = bits(vpn, 1, 0)
node _T_1858 = eq(UInt<2>(0h3), _T_1857)
node _T_1859 = and(_T_1856, _T_1858)
when _T_1859 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
node _T_1860 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _T_1861 = shr(_T_1860, 18)
node _T_1862 = eq(_T_1861, UInt<1>(0h0))
when _T_1862 :
wire _WIRE_136 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_137 : UInt<42>
connect _WIRE_137, sectored_entries[0][4].data[0]
node _T_1863 = bits(_WIRE_137, 0, 0)
connect _WIRE_136.fragmented_superpage, _T_1863
node _T_1864 = bits(_WIRE_137, 1, 1)
connect _WIRE_136.c, _T_1864
node _T_1865 = bits(_WIRE_137, 2, 2)
connect _WIRE_136.eff, _T_1865
node _T_1866 = bits(_WIRE_137, 3, 3)
connect _WIRE_136.paa, _T_1866
node _T_1867 = bits(_WIRE_137, 4, 4)
connect _WIRE_136.pal, _T_1867
node _T_1868 = bits(_WIRE_137, 5, 5)
connect _WIRE_136.ppp, _T_1868
node _T_1869 = bits(_WIRE_137, 6, 6)
connect _WIRE_136.pr, _T_1869
node _T_1870 = bits(_WIRE_137, 7, 7)
connect _WIRE_136.px, _T_1870
node _T_1871 = bits(_WIRE_137, 8, 8)
connect _WIRE_136.pw, _T_1871
node _T_1872 = bits(_WIRE_137, 9, 9)
connect _WIRE_136.hr, _T_1872
node _T_1873 = bits(_WIRE_137, 10, 10)
connect _WIRE_136.hx, _T_1873
node _T_1874 = bits(_WIRE_137, 11, 11)
connect _WIRE_136.hw, _T_1874
node _T_1875 = bits(_WIRE_137, 12, 12)
connect _WIRE_136.sr, _T_1875
node _T_1876 = bits(_WIRE_137, 13, 13)
connect _WIRE_136.sx, _T_1876
node _T_1877 = bits(_WIRE_137, 14, 14)
connect _WIRE_136.sw, _T_1877
node _T_1878 = bits(_WIRE_137, 15, 15)
connect _WIRE_136.gf, _T_1878
node _T_1879 = bits(_WIRE_137, 16, 16)
connect _WIRE_136.pf, _T_1879
node _T_1880 = bits(_WIRE_137, 17, 17)
connect _WIRE_136.ae_stage2, _T_1880
node _T_1881 = bits(_WIRE_137, 18, 18)
connect _WIRE_136.ae_final, _T_1881
node _T_1882 = bits(_WIRE_137, 19, 19)
connect _WIRE_136.ae_ptw, _T_1882
node _T_1883 = bits(_WIRE_137, 20, 20)
connect _WIRE_136.g, _T_1883
node _T_1884 = bits(_WIRE_137, 21, 21)
connect _WIRE_136.u, _T_1884
node _T_1885 = bits(_WIRE_137, 41, 22)
connect _WIRE_136.ppn, _T_1885
wire _WIRE_138 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_139 : UInt<42>
connect _WIRE_139, sectored_entries[0][4].data[1]
node _T_1886 = bits(_WIRE_139, 0, 0)
connect _WIRE_138.fragmented_superpage, _T_1886
node _T_1887 = bits(_WIRE_139, 1, 1)
connect _WIRE_138.c, _T_1887
node _T_1888 = bits(_WIRE_139, 2, 2)
connect _WIRE_138.eff, _T_1888
node _T_1889 = bits(_WIRE_139, 3, 3)
connect _WIRE_138.paa, _T_1889
node _T_1890 = bits(_WIRE_139, 4, 4)
connect _WIRE_138.pal, _T_1890
node _T_1891 = bits(_WIRE_139, 5, 5)
connect _WIRE_138.ppp, _T_1891
node _T_1892 = bits(_WIRE_139, 6, 6)
connect _WIRE_138.pr, _T_1892
node _T_1893 = bits(_WIRE_139, 7, 7)
connect _WIRE_138.px, _T_1893
node _T_1894 = bits(_WIRE_139, 8, 8)
connect _WIRE_138.pw, _T_1894
node _T_1895 = bits(_WIRE_139, 9, 9)
connect _WIRE_138.hr, _T_1895
node _T_1896 = bits(_WIRE_139, 10, 10)
connect _WIRE_138.hx, _T_1896
node _T_1897 = bits(_WIRE_139, 11, 11)
connect _WIRE_138.hw, _T_1897
node _T_1898 = bits(_WIRE_139, 12, 12)
connect _WIRE_138.sr, _T_1898
node _T_1899 = bits(_WIRE_139, 13, 13)
connect _WIRE_138.sx, _T_1899
node _T_1900 = bits(_WIRE_139, 14, 14)
connect _WIRE_138.sw, _T_1900
node _T_1901 = bits(_WIRE_139, 15, 15)
connect _WIRE_138.gf, _T_1901
node _T_1902 = bits(_WIRE_139, 16, 16)
connect _WIRE_138.pf, _T_1902
node _T_1903 = bits(_WIRE_139, 17, 17)
connect _WIRE_138.ae_stage2, _T_1903
node _T_1904 = bits(_WIRE_139, 18, 18)
connect _WIRE_138.ae_final, _T_1904
node _T_1905 = bits(_WIRE_139, 19, 19)
connect _WIRE_138.ae_ptw, _T_1905
node _T_1906 = bits(_WIRE_139, 20, 20)
connect _WIRE_138.g, _T_1906
node _T_1907 = bits(_WIRE_139, 21, 21)
connect _WIRE_138.u, _T_1907
node _T_1908 = bits(_WIRE_139, 41, 22)
connect _WIRE_138.ppn, _T_1908
wire _WIRE_140 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_141 : UInt<42>
connect _WIRE_141, sectored_entries[0][4].data[2]
node _T_1909 = bits(_WIRE_141, 0, 0)
connect _WIRE_140.fragmented_superpage, _T_1909
node _T_1910 = bits(_WIRE_141, 1, 1)
connect _WIRE_140.c, _T_1910
node _T_1911 = bits(_WIRE_141, 2, 2)
connect _WIRE_140.eff, _T_1911
node _T_1912 = bits(_WIRE_141, 3, 3)
connect _WIRE_140.paa, _T_1912
node _T_1913 = bits(_WIRE_141, 4, 4)
connect _WIRE_140.pal, _T_1913
node _T_1914 = bits(_WIRE_141, 5, 5)
connect _WIRE_140.ppp, _T_1914
node _T_1915 = bits(_WIRE_141, 6, 6)
connect _WIRE_140.pr, _T_1915
node _T_1916 = bits(_WIRE_141, 7, 7)
connect _WIRE_140.px, _T_1916
node _T_1917 = bits(_WIRE_141, 8, 8)
connect _WIRE_140.pw, _T_1917
node _T_1918 = bits(_WIRE_141, 9, 9)
connect _WIRE_140.hr, _T_1918
node _T_1919 = bits(_WIRE_141, 10, 10)
connect _WIRE_140.hx, _T_1919
node _T_1920 = bits(_WIRE_141, 11, 11)
connect _WIRE_140.hw, _T_1920
node _T_1921 = bits(_WIRE_141, 12, 12)
connect _WIRE_140.sr, _T_1921
node _T_1922 = bits(_WIRE_141, 13, 13)
connect _WIRE_140.sx, _T_1922
node _T_1923 = bits(_WIRE_141, 14, 14)
connect _WIRE_140.sw, _T_1923
node _T_1924 = bits(_WIRE_141, 15, 15)
connect _WIRE_140.gf, _T_1924
node _T_1925 = bits(_WIRE_141, 16, 16)
connect _WIRE_140.pf, _T_1925
node _T_1926 = bits(_WIRE_141, 17, 17)
connect _WIRE_140.ae_stage2, _T_1926
node _T_1927 = bits(_WIRE_141, 18, 18)
connect _WIRE_140.ae_final, _T_1927
node _T_1928 = bits(_WIRE_141, 19, 19)
connect _WIRE_140.ae_ptw, _T_1928
node _T_1929 = bits(_WIRE_141, 20, 20)
connect _WIRE_140.g, _T_1929
node _T_1930 = bits(_WIRE_141, 21, 21)
connect _WIRE_140.u, _T_1930
node _T_1931 = bits(_WIRE_141, 41, 22)
connect _WIRE_140.ppn, _T_1931
wire _WIRE_142 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_143 : UInt<42>
connect _WIRE_143, sectored_entries[0][4].data[3]
node _T_1932 = bits(_WIRE_143, 0, 0)
connect _WIRE_142.fragmented_superpage, _T_1932
node _T_1933 = bits(_WIRE_143, 1, 1)
connect _WIRE_142.c, _T_1933
node _T_1934 = bits(_WIRE_143, 2, 2)
connect _WIRE_142.eff, _T_1934
node _T_1935 = bits(_WIRE_143, 3, 3)
connect _WIRE_142.paa, _T_1935
node _T_1936 = bits(_WIRE_143, 4, 4)
connect _WIRE_142.pal, _T_1936
node _T_1937 = bits(_WIRE_143, 5, 5)
connect _WIRE_142.ppp, _T_1937
node _T_1938 = bits(_WIRE_143, 6, 6)
connect _WIRE_142.pr, _T_1938
node _T_1939 = bits(_WIRE_143, 7, 7)
connect _WIRE_142.px, _T_1939
node _T_1940 = bits(_WIRE_143, 8, 8)
connect _WIRE_142.pw, _T_1940
node _T_1941 = bits(_WIRE_143, 9, 9)
connect _WIRE_142.hr, _T_1941
node _T_1942 = bits(_WIRE_143, 10, 10)
connect _WIRE_142.hx, _T_1942
node _T_1943 = bits(_WIRE_143, 11, 11)
connect _WIRE_142.hw, _T_1943
node _T_1944 = bits(_WIRE_143, 12, 12)
connect _WIRE_142.sr, _T_1944
node _T_1945 = bits(_WIRE_143, 13, 13)
connect _WIRE_142.sx, _T_1945
node _T_1946 = bits(_WIRE_143, 14, 14)
connect _WIRE_142.sw, _T_1946
node _T_1947 = bits(_WIRE_143, 15, 15)
connect _WIRE_142.gf, _T_1947
node _T_1948 = bits(_WIRE_143, 16, 16)
connect _WIRE_142.pf, _T_1948
node _T_1949 = bits(_WIRE_143, 17, 17)
connect _WIRE_142.ae_stage2, _T_1949
node _T_1950 = bits(_WIRE_143, 18, 18)
connect _WIRE_142.ae_final, _T_1950
node _T_1951 = bits(_WIRE_143, 19, 19)
connect _WIRE_142.ae_ptw, _T_1951
node _T_1952 = bits(_WIRE_143, 20, 20)
connect _WIRE_142.g, _T_1952
node _T_1953 = bits(_WIRE_143, 21, 21)
connect _WIRE_142.u, _T_1953
node _T_1954 = bits(_WIRE_143, 41, 22)
connect _WIRE_142.ppn, _T_1954
node _T_1955 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1956 = and(_T_1955, _WIRE_136.fragmented_superpage)
when _T_1956 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_1957 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1958 = and(_T_1957, _WIRE_138.fragmented_superpage)
when _T_1958 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_1959 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1960 = and(_T_1959, _WIRE_140.fragmented_superpage)
when _T_1960 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_1961 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1962 = and(_T_1961, _WIRE_142.fragmented_superpage)
when _T_1962 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
else :
node _T_1963 = eq(hg_4, UInt<1>(0h0))
node _T_1964 = and(_T_1963, io.sfence.bits.rs2)
when _T_1964 :
wire _WIRE_144 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_145 : UInt<42>
connect _WIRE_145, sectored_entries[0][4].data[0]
node _T_1965 = bits(_WIRE_145, 0, 0)
connect _WIRE_144.fragmented_superpage, _T_1965
node _T_1966 = bits(_WIRE_145, 1, 1)
connect _WIRE_144.c, _T_1966
node _T_1967 = bits(_WIRE_145, 2, 2)
connect _WIRE_144.eff, _T_1967
node _T_1968 = bits(_WIRE_145, 3, 3)
connect _WIRE_144.paa, _T_1968
node _T_1969 = bits(_WIRE_145, 4, 4)
connect _WIRE_144.pal, _T_1969
node _T_1970 = bits(_WIRE_145, 5, 5)
connect _WIRE_144.ppp, _T_1970
node _T_1971 = bits(_WIRE_145, 6, 6)
connect _WIRE_144.pr, _T_1971
node _T_1972 = bits(_WIRE_145, 7, 7)
connect _WIRE_144.px, _T_1972
node _T_1973 = bits(_WIRE_145, 8, 8)
connect _WIRE_144.pw, _T_1973
node _T_1974 = bits(_WIRE_145, 9, 9)
connect _WIRE_144.hr, _T_1974
node _T_1975 = bits(_WIRE_145, 10, 10)
connect _WIRE_144.hx, _T_1975
node _T_1976 = bits(_WIRE_145, 11, 11)
connect _WIRE_144.hw, _T_1976
node _T_1977 = bits(_WIRE_145, 12, 12)
connect _WIRE_144.sr, _T_1977
node _T_1978 = bits(_WIRE_145, 13, 13)
connect _WIRE_144.sx, _T_1978
node _T_1979 = bits(_WIRE_145, 14, 14)
connect _WIRE_144.sw, _T_1979
node _T_1980 = bits(_WIRE_145, 15, 15)
connect _WIRE_144.gf, _T_1980
node _T_1981 = bits(_WIRE_145, 16, 16)
connect _WIRE_144.pf, _T_1981
node _T_1982 = bits(_WIRE_145, 17, 17)
connect _WIRE_144.ae_stage2, _T_1982
node _T_1983 = bits(_WIRE_145, 18, 18)
connect _WIRE_144.ae_final, _T_1983
node _T_1984 = bits(_WIRE_145, 19, 19)
connect _WIRE_144.ae_ptw, _T_1984
node _T_1985 = bits(_WIRE_145, 20, 20)
connect _WIRE_144.g, _T_1985
node _T_1986 = bits(_WIRE_145, 21, 21)
connect _WIRE_144.u, _T_1986
node _T_1987 = bits(_WIRE_145, 41, 22)
connect _WIRE_144.ppn, _T_1987
wire _WIRE_146 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_147 : UInt<42>
connect _WIRE_147, sectored_entries[0][4].data[1]
node _T_1988 = bits(_WIRE_147, 0, 0)
connect _WIRE_146.fragmented_superpage, _T_1988
node _T_1989 = bits(_WIRE_147, 1, 1)
connect _WIRE_146.c, _T_1989
node _T_1990 = bits(_WIRE_147, 2, 2)
connect _WIRE_146.eff, _T_1990
node _T_1991 = bits(_WIRE_147, 3, 3)
connect _WIRE_146.paa, _T_1991
node _T_1992 = bits(_WIRE_147, 4, 4)
connect _WIRE_146.pal, _T_1992
node _T_1993 = bits(_WIRE_147, 5, 5)
connect _WIRE_146.ppp, _T_1993
node _T_1994 = bits(_WIRE_147, 6, 6)
connect _WIRE_146.pr, _T_1994
node _T_1995 = bits(_WIRE_147, 7, 7)
connect _WIRE_146.px, _T_1995
node _T_1996 = bits(_WIRE_147, 8, 8)
connect _WIRE_146.pw, _T_1996
node _T_1997 = bits(_WIRE_147, 9, 9)
connect _WIRE_146.hr, _T_1997
node _T_1998 = bits(_WIRE_147, 10, 10)
connect _WIRE_146.hx, _T_1998
node _T_1999 = bits(_WIRE_147, 11, 11)
connect _WIRE_146.hw, _T_1999
node _T_2000 = bits(_WIRE_147, 12, 12)
connect _WIRE_146.sr, _T_2000
node _T_2001 = bits(_WIRE_147, 13, 13)
connect _WIRE_146.sx, _T_2001
node _T_2002 = bits(_WIRE_147, 14, 14)
connect _WIRE_146.sw, _T_2002
node _T_2003 = bits(_WIRE_147, 15, 15)
connect _WIRE_146.gf, _T_2003
node _T_2004 = bits(_WIRE_147, 16, 16)
connect _WIRE_146.pf, _T_2004
node _T_2005 = bits(_WIRE_147, 17, 17)
connect _WIRE_146.ae_stage2, _T_2005
node _T_2006 = bits(_WIRE_147, 18, 18)
connect _WIRE_146.ae_final, _T_2006
node _T_2007 = bits(_WIRE_147, 19, 19)
connect _WIRE_146.ae_ptw, _T_2007
node _T_2008 = bits(_WIRE_147, 20, 20)
connect _WIRE_146.g, _T_2008
node _T_2009 = bits(_WIRE_147, 21, 21)
connect _WIRE_146.u, _T_2009
node _T_2010 = bits(_WIRE_147, 41, 22)
connect _WIRE_146.ppn, _T_2010
wire _WIRE_148 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_149 : UInt<42>
connect _WIRE_149, sectored_entries[0][4].data[2]
node _T_2011 = bits(_WIRE_149, 0, 0)
connect _WIRE_148.fragmented_superpage, _T_2011
node _T_2012 = bits(_WIRE_149, 1, 1)
connect _WIRE_148.c, _T_2012
node _T_2013 = bits(_WIRE_149, 2, 2)
connect _WIRE_148.eff, _T_2013
node _T_2014 = bits(_WIRE_149, 3, 3)
connect _WIRE_148.paa, _T_2014
node _T_2015 = bits(_WIRE_149, 4, 4)
connect _WIRE_148.pal, _T_2015
node _T_2016 = bits(_WIRE_149, 5, 5)
connect _WIRE_148.ppp, _T_2016
node _T_2017 = bits(_WIRE_149, 6, 6)
connect _WIRE_148.pr, _T_2017
node _T_2018 = bits(_WIRE_149, 7, 7)
connect _WIRE_148.px, _T_2018
node _T_2019 = bits(_WIRE_149, 8, 8)
connect _WIRE_148.pw, _T_2019
node _T_2020 = bits(_WIRE_149, 9, 9)
connect _WIRE_148.hr, _T_2020
node _T_2021 = bits(_WIRE_149, 10, 10)
connect _WIRE_148.hx, _T_2021
node _T_2022 = bits(_WIRE_149, 11, 11)
connect _WIRE_148.hw, _T_2022
node _T_2023 = bits(_WIRE_149, 12, 12)
connect _WIRE_148.sr, _T_2023
node _T_2024 = bits(_WIRE_149, 13, 13)
connect _WIRE_148.sx, _T_2024
node _T_2025 = bits(_WIRE_149, 14, 14)
connect _WIRE_148.sw, _T_2025
node _T_2026 = bits(_WIRE_149, 15, 15)
connect _WIRE_148.gf, _T_2026
node _T_2027 = bits(_WIRE_149, 16, 16)
connect _WIRE_148.pf, _T_2027
node _T_2028 = bits(_WIRE_149, 17, 17)
connect _WIRE_148.ae_stage2, _T_2028
node _T_2029 = bits(_WIRE_149, 18, 18)
connect _WIRE_148.ae_final, _T_2029
node _T_2030 = bits(_WIRE_149, 19, 19)
connect _WIRE_148.ae_ptw, _T_2030
node _T_2031 = bits(_WIRE_149, 20, 20)
connect _WIRE_148.g, _T_2031
node _T_2032 = bits(_WIRE_149, 21, 21)
connect _WIRE_148.u, _T_2032
node _T_2033 = bits(_WIRE_149, 41, 22)
connect _WIRE_148.ppn, _T_2033
wire _WIRE_150 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_151 : UInt<42>
connect _WIRE_151, sectored_entries[0][4].data[3]
node _T_2034 = bits(_WIRE_151, 0, 0)
connect _WIRE_150.fragmented_superpage, _T_2034
node _T_2035 = bits(_WIRE_151, 1, 1)
connect _WIRE_150.c, _T_2035
node _T_2036 = bits(_WIRE_151, 2, 2)
connect _WIRE_150.eff, _T_2036
node _T_2037 = bits(_WIRE_151, 3, 3)
connect _WIRE_150.paa, _T_2037
node _T_2038 = bits(_WIRE_151, 4, 4)
connect _WIRE_150.pal, _T_2038
node _T_2039 = bits(_WIRE_151, 5, 5)
connect _WIRE_150.ppp, _T_2039
node _T_2040 = bits(_WIRE_151, 6, 6)
connect _WIRE_150.pr, _T_2040
node _T_2041 = bits(_WIRE_151, 7, 7)
connect _WIRE_150.px, _T_2041
node _T_2042 = bits(_WIRE_151, 8, 8)
connect _WIRE_150.pw, _T_2042
node _T_2043 = bits(_WIRE_151, 9, 9)
connect _WIRE_150.hr, _T_2043
node _T_2044 = bits(_WIRE_151, 10, 10)
connect _WIRE_150.hx, _T_2044
node _T_2045 = bits(_WIRE_151, 11, 11)
connect _WIRE_150.hw, _T_2045
node _T_2046 = bits(_WIRE_151, 12, 12)
connect _WIRE_150.sr, _T_2046
node _T_2047 = bits(_WIRE_151, 13, 13)
connect _WIRE_150.sx, _T_2047
node _T_2048 = bits(_WIRE_151, 14, 14)
connect _WIRE_150.sw, _T_2048
node _T_2049 = bits(_WIRE_151, 15, 15)
connect _WIRE_150.gf, _T_2049
node _T_2050 = bits(_WIRE_151, 16, 16)
connect _WIRE_150.pf, _T_2050
node _T_2051 = bits(_WIRE_151, 17, 17)
connect _WIRE_150.ae_stage2, _T_2051
node _T_2052 = bits(_WIRE_151, 18, 18)
connect _WIRE_150.ae_final, _T_2052
node _T_2053 = bits(_WIRE_151, 19, 19)
connect _WIRE_150.ae_ptw, _T_2053
node _T_2054 = bits(_WIRE_151, 20, 20)
connect _WIRE_150.g, _T_2054
node _T_2055 = bits(_WIRE_151, 21, 21)
connect _WIRE_150.u, _T_2055
node _T_2056 = bits(_WIRE_151, 41, 22)
connect _WIRE_150.ppn, _T_2056
node _T_2057 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_2058 = eq(_WIRE_144.g, UInt<1>(0h0))
node _T_2059 = and(_T_2057, _T_2058)
when _T_2059 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_2060 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_2061 = eq(_WIRE_146.g, UInt<1>(0h0))
node _T_2062 = and(_T_2060, _T_2061)
when _T_2062 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_2063 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_2064 = eq(_WIRE_148.g, UInt<1>(0h0))
node _T_2065 = and(_T_2063, _T_2064)
when _T_2065 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_2066 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_2067 = eq(_WIRE_150.g, UInt<1>(0h0))
node _T_2068 = and(_T_2066, _T_2067)
when _T_2068 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
else :
node _T_2069 = or(hv_4, hg_4)
wire _WIRE_152 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_153 : UInt<42>
connect _WIRE_153, sectored_entries[0][4].data[0]
node _T_2070 = bits(_WIRE_153, 0, 0)
connect _WIRE_152.fragmented_superpage, _T_2070
node _T_2071 = bits(_WIRE_153, 1, 1)
connect _WIRE_152.c, _T_2071
node _T_2072 = bits(_WIRE_153, 2, 2)
connect _WIRE_152.eff, _T_2072
node _T_2073 = bits(_WIRE_153, 3, 3)
connect _WIRE_152.paa, _T_2073
node _T_2074 = bits(_WIRE_153, 4, 4)
connect _WIRE_152.pal, _T_2074
node _T_2075 = bits(_WIRE_153, 5, 5)
connect _WIRE_152.ppp, _T_2075
node _T_2076 = bits(_WIRE_153, 6, 6)
connect _WIRE_152.pr, _T_2076
node _T_2077 = bits(_WIRE_153, 7, 7)
connect _WIRE_152.px, _T_2077
node _T_2078 = bits(_WIRE_153, 8, 8)
connect _WIRE_152.pw, _T_2078
node _T_2079 = bits(_WIRE_153, 9, 9)
connect _WIRE_152.hr, _T_2079
node _T_2080 = bits(_WIRE_153, 10, 10)
connect _WIRE_152.hx, _T_2080
node _T_2081 = bits(_WIRE_153, 11, 11)
connect _WIRE_152.hw, _T_2081
node _T_2082 = bits(_WIRE_153, 12, 12)
connect _WIRE_152.sr, _T_2082
node _T_2083 = bits(_WIRE_153, 13, 13)
connect _WIRE_152.sx, _T_2083
node _T_2084 = bits(_WIRE_153, 14, 14)
connect _WIRE_152.sw, _T_2084
node _T_2085 = bits(_WIRE_153, 15, 15)
connect _WIRE_152.gf, _T_2085
node _T_2086 = bits(_WIRE_153, 16, 16)
connect _WIRE_152.pf, _T_2086
node _T_2087 = bits(_WIRE_153, 17, 17)
connect _WIRE_152.ae_stage2, _T_2087
node _T_2088 = bits(_WIRE_153, 18, 18)
connect _WIRE_152.ae_final, _T_2088
node _T_2089 = bits(_WIRE_153, 19, 19)
connect _WIRE_152.ae_ptw, _T_2089
node _T_2090 = bits(_WIRE_153, 20, 20)
connect _WIRE_152.g, _T_2090
node _T_2091 = bits(_WIRE_153, 21, 21)
connect _WIRE_152.u, _T_2091
node _T_2092 = bits(_WIRE_153, 41, 22)
connect _WIRE_152.ppn, _T_2092
wire _WIRE_154 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_155 : UInt<42>
connect _WIRE_155, sectored_entries[0][4].data[1]
node _T_2093 = bits(_WIRE_155, 0, 0)
connect _WIRE_154.fragmented_superpage, _T_2093
node _T_2094 = bits(_WIRE_155, 1, 1)
connect _WIRE_154.c, _T_2094
node _T_2095 = bits(_WIRE_155, 2, 2)
connect _WIRE_154.eff, _T_2095
node _T_2096 = bits(_WIRE_155, 3, 3)
connect _WIRE_154.paa, _T_2096
node _T_2097 = bits(_WIRE_155, 4, 4)
connect _WIRE_154.pal, _T_2097
node _T_2098 = bits(_WIRE_155, 5, 5)
connect _WIRE_154.ppp, _T_2098
node _T_2099 = bits(_WIRE_155, 6, 6)
connect _WIRE_154.pr, _T_2099
node _T_2100 = bits(_WIRE_155, 7, 7)
connect _WIRE_154.px, _T_2100
node _T_2101 = bits(_WIRE_155, 8, 8)
connect _WIRE_154.pw, _T_2101
node _T_2102 = bits(_WIRE_155, 9, 9)
connect _WIRE_154.hr, _T_2102
node _T_2103 = bits(_WIRE_155, 10, 10)
connect _WIRE_154.hx, _T_2103
node _T_2104 = bits(_WIRE_155, 11, 11)
connect _WIRE_154.hw, _T_2104
node _T_2105 = bits(_WIRE_155, 12, 12)
connect _WIRE_154.sr, _T_2105
node _T_2106 = bits(_WIRE_155, 13, 13)
connect _WIRE_154.sx, _T_2106
node _T_2107 = bits(_WIRE_155, 14, 14)
connect _WIRE_154.sw, _T_2107
node _T_2108 = bits(_WIRE_155, 15, 15)
connect _WIRE_154.gf, _T_2108
node _T_2109 = bits(_WIRE_155, 16, 16)
connect _WIRE_154.pf, _T_2109
node _T_2110 = bits(_WIRE_155, 17, 17)
connect _WIRE_154.ae_stage2, _T_2110
node _T_2111 = bits(_WIRE_155, 18, 18)
connect _WIRE_154.ae_final, _T_2111
node _T_2112 = bits(_WIRE_155, 19, 19)
connect _WIRE_154.ae_ptw, _T_2112
node _T_2113 = bits(_WIRE_155, 20, 20)
connect _WIRE_154.g, _T_2113
node _T_2114 = bits(_WIRE_155, 21, 21)
connect _WIRE_154.u, _T_2114
node _T_2115 = bits(_WIRE_155, 41, 22)
connect _WIRE_154.ppn, _T_2115
wire _WIRE_156 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_157 : UInt<42>
connect _WIRE_157, sectored_entries[0][4].data[2]
node _T_2116 = bits(_WIRE_157, 0, 0)
connect _WIRE_156.fragmented_superpage, _T_2116
node _T_2117 = bits(_WIRE_157, 1, 1)
connect _WIRE_156.c, _T_2117
node _T_2118 = bits(_WIRE_157, 2, 2)
connect _WIRE_156.eff, _T_2118
node _T_2119 = bits(_WIRE_157, 3, 3)
connect _WIRE_156.paa, _T_2119
node _T_2120 = bits(_WIRE_157, 4, 4)
connect _WIRE_156.pal, _T_2120
node _T_2121 = bits(_WIRE_157, 5, 5)
connect _WIRE_156.ppp, _T_2121
node _T_2122 = bits(_WIRE_157, 6, 6)
connect _WIRE_156.pr, _T_2122
node _T_2123 = bits(_WIRE_157, 7, 7)
connect _WIRE_156.px, _T_2123
node _T_2124 = bits(_WIRE_157, 8, 8)
connect _WIRE_156.pw, _T_2124
node _T_2125 = bits(_WIRE_157, 9, 9)
connect _WIRE_156.hr, _T_2125
node _T_2126 = bits(_WIRE_157, 10, 10)
connect _WIRE_156.hx, _T_2126
node _T_2127 = bits(_WIRE_157, 11, 11)
connect _WIRE_156.hw, _T_2127
node _T_2128 = bits(_WIRE_157, 12, 12)
connect _WIRE_156.sr, _T_2128
node _T_2129 = bits(_WIRE_157, 13, 13)
connect _WIRE_156.sx, _T_2129
node _T_2130 = bits(_WIRE_157, 14, 14)
connect _WIRE_156.sw, _T_2130
node _T_2131 = bits(_WIRE_157, 15, 15)
connect _WIRE_156.gf, _T_2131
node _T_2132 = bits(_WIRE_157, 16, 16)
connect _WIRE_156.pf, _T_2132
node _T_2133 = bits(_WIRE_157, 17, 17)
connect _WIRE_156.ae_stage2, _T_2133
node _T_2134 = bits(_WIRE_157, 18, 18)
connect _WIRE_156.ae_final, _T_2134
node _T_2135 = bits(_WIRE_157, 19, 19)
connect _WIRE_156.ae_ptw, _T_2135
node _T_2136 = bits(_WIRE_157, 20, 20)
connect _WIRE_156.g, _T_2136
node _T_2137 = bits(_WIRE_157, 21, 21)
connect _WIRE_156.u, _T_2137
node _T_2138 = bits(_WIRE_157, 41, 22)
connect _WIRE_156.ppn, _T_2138
wire _WIRE_158 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_159 : UInt<42>
connect _WIRE_159, sectored_entries[0][4].data[3]
node _T_2139 = bits(_WIRE_159, 0, 0)
connect _WIRE_158.fragmented_superpage, _T_2139
node _T_2140 = bits(_WIRE_159, 1, 1)
connect _WIRE_158.c, _T_2140
node _T_2141 = bits(_WIRE_159, 2, 2)
connect _WIRE_158.eff, _T_2141
node _T_2142 = bits(_WIRE_159, 3, 3)
connect _WIRE_158.paa, _T_2142
node _T_2143 = bits(_WIRE_159, 4, 4)
connect _WIRE_158.pal, _T_2143
node _T_2144 = bits(_WIRE_159, 5, 5)
connect _WIRE_158.ppp, _T_2144
node _T_2145 = bits(_WIRE_159, 6, 6)
connect _WIRE_158.pr, _T_2145
node _T_2146 = bits(_WIRE_159, 7, 7)
connect _WIRE_158.px, _T_2146
node _T_2147 = bits(_WIRE_159, 8, 8)
connect _WIRE_158.pw, _T_2147
node _T_2148 = bits(_WIRE_159, 9, 9)
connect _WIRE_158.hr, _T_2148
node _T_2149 = bits(_WIRE_159, 10, 10)
connect _WIRE_158.hx, _T_2149
node _T_2150 = bits(_WIRE_159, 11, 11)
connect _WIRE_158.hw, _T_2150
node _T_2151 = bits(_WIRE_159, 12, 12)
connect _WIRE_158.sr, _T_2151
node _T_2152 = bits(_WIRE_159, 13, 13)
connect _WIRE_158.sx, _T_2152
node _T_2153 = bits(_WIRE_159, 14, 14)
connect _WIRE_158.sw, _T_2153
node _T_2154 = bits(_WIRE_159, 15, 15)
connect _WIRE_158.gf, _T_2154
node _T_2155 = bits(_WIRE_159, 16, 16)
connect _WIRE_158.pf, _T_2155
node _T_2156 = bits(_WIRE_159, 17, 17)
connect _WIRE_158.ae_stage2, _T_2156
node _T_2157 = bits(_WIRE_159, 18, 18)
connect _WIRE_158.ae_final, _T_2157
node _T_2158 = bits(_WIRE_159, 19, 19)
connect _WIRE_158.ae_ptw, _T_2158
node _T_2159 = bits(_WIRE_159, 20, 20)
connect _WIRE_158.g, _T_2159
node _T_2160 = bits(_WIRE_159, 21, 21)
connect _WIRE_158.u, _T_2160
node _T_2161 = bits(_WIRE_159, 41, 22)
connect _WIRE_158.ppn, _T_2161
node _T_2162 = eq(sectored_entries[0][4].tag_v, _T_2069)
when _T_2162 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_2163 = eq(sectored_entries[0][4].tag_v, _T_2069)
when _T_2163 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_2164 = eq(sectored_entries[0][4].tag_v, _T_2069)
when _T_2164 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_2165 = eq(sectored_entries[0][4].tag_v, _T_2069)
when _T_2165 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
node hv_5 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_5 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_2166 = eq(hg_5, UInt<1>(0h0))
node _T_2167 = and(_T_2166, io.sfence.bits.rs1)
when _T_2167 :
node _T_2168 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _T_2169 = shr(_T_2168, 2)
node _T_2170 = eq(_T_2169, UInt<1>(0h0))
node _T_2171 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2172 = and(_T_2170, _T_2171)
when _T_2172 :
wire _WIRE_160 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_161 : UInt<42>
connect _WIRE_161, sectored_entries[0][5].data[0]
node _T_2173 = bits(_WIRE_161, 0, 0)
connect _WIRE_160.fragmented_superpage, _T_2173
node _T_2174 = bits(_WIRE_161, 1, 1)
connect _WIRE_160.c, _T_2174
node _T_2175 = bits(_WIRE_161, 2, 2)
connect _WIRE_160.eff, _T_2175
node _T_2176 = bits(_WIRE_161, 3, 3)
connect _WIRE_160.paa, _T_2176
node _T_2177 = bits(_WIRE_161, 4, 4)
connect _WIRE_160.pal, _T_2177
node _T_2178 = bits(_WIRE_161, 5, 5)
connect _WIRE_160.ppp, _T_2178
node _T_2179 = bits(_WIRE_161, 6, 6)
connect _WIRE_160.pr, _T_2179
node _T_2180 = bits(_WIRE_161, 7, 7)
connect _WIRE_160.px, _T_2180
node _T_2181 = bits(_WIRE_161, 8, 8)
connect _WIRE_160.pw, _T_2181
node _T_2182 = bits(_WIRE_161, 9, 9)
connect _WIRE_160.hr, _T_2182
node _T_2183 = bits(_WIRE_161, 10, 10)
connect _WIRE_160.hx, _T_2183
node _T_2184 = bits(_WIRE_161, 11, 11)
connect _WIRE_160.hw, _T_2184
node _T_2185 = bits(_WIRE_161, 12, 12)
connect _WIRE_160.sr, _T_2185
node _T_2186 = bits(_WIRE_161, 13, 13)
connect _WIRE_160.sx, _T_2186
node _T_2187 = bits(_WIRE_161, 14, 14)
connect _WIRE_160.sw, _T_2187
node _T_2188 = bits(_WIRE_161, 15, 15)
connect _WIRE_160.gf, _T_2188
node _T_2189 = bits(_WIRE_161, 16, 16)
connect _WIRE_160.pf, _T_2189
node _T_2190 = bits(_WIRE_161, 17, 17)
connect _WIRE_160.ae_stage2, _T_2190
node _T_2191 = bits(_WIRE_161, 18, 18)
connect _WIRE_160.ae_final, _T_2191
node _T_2192 = bits(_WIRE_161, 19, 19)
connect _WIRE_160.ae_ptw, _T_2192
node _T_2193 = bits(_WIRE_161, 20, 20)
connect _WIRE_160.g, _T_2193
node _T_2194 = bits(_WIRE_161, 21, 21)
connect _WIRE_160.u, _T_2194
node _T_2195 = bits(_WIRE_161, 41, 22)
connect _WIRE_160.ppn, _T_2195
wire _WIRE_162 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_163 : UInt<42>
connect _WIRE_163, sectored_entries[0][5].data[1]
node _T_2196 = bits(_WIRE_163, 0, 0)
connect _WIRE_162.fragmented_superpage, _T_2196
node _T_2197 = bits(_WIRE_163, 1, 1)
connect _WIRE_162.c, _T_2197
node _T_2198 = bits(_WIRE_163, 2, 2)
connect _WIRE_162.eff, _T_2198
node _T_2199 = bits(_WIRE_163, 3, 3)
connect _WIRE_162.paa, _T_2199
node _T_2200 = bits(_WIRE_163, 4, 4)
connect _WIRE_162.pal, _T_2200
node _T_2201 = bits(_WIRE_163, 5, 5)
connect _WIRE_162.ppp, _T_2201
node _T_2202 = bits(_WIRE_163, 6, 6)
connect _WIRE_162.pr, _T_2202
node _T_2203 = bits(_WIRE_163, 7, 7)
connect _WIRE_162.px, _T_2203
node _T_2204 = bits(_WIRE_163, 8, 8)
connect _WIRE_162.pw, _T_2204
node _T_2205 = bits(_WIRE_163, 9, 9)
connect _WIRE_162.hr, _T_2205
node _T_2206 = bits(_WIRE_163, 10, 10)
connect _WIRE_162.hx, _T_2206
node _T_2207 = bits(_WIRE_163, 11, 11)
connect _WIRE_162.hw, _T_2207
node _T_2208 = bits(_WIRE_163, 12, 12)
connect _WIRE_162.sr, _T_2208
node _T_2209 = bits(_WIRE_163, 13, 13)
connect _WIRE_162.sx, _T_2209
node _T_2210 = bits(_WIRE_163, 14, 14)
connect _WIRE_162.sw, _T_2210
node _T_2211 = bits(_WIRE_163, 15, 15)
connect _WIRE_162.gf, _T_2211
node _T_2212 = bits(_WIRE_163, 16, 16)
connect _WIRE_162.pf, _T_2212
node _T_2213 = bits(_WIRE_163, 17, 17)
connect _WIRE_162.ae_stage2, _T_2213
node _T_2214 = bits(_WIRE_163, 18, 18)
connect _WIRE_162.ae_final, _T_2214
node _T_2215 = bits(_WIRE_163, 19, 19)
connect _WIRE_162.ae_ptw, _T_2215
node _T_2216 = bits(_WIRE_163, 20, 20)
connect _WIRE_162.g, _T_2216
node _T_2217 = bits(_WIRE_163, 21, 21)
connect _WIRE_162.u, _T_2217
node _T_2218 = bits(_WIRE_163, 41, 22)
connect _WIRE_162.ppn, _T_2218
wire _WIRE_164 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_165 : UInt<42>
connect _WIRE_165, sectored_entries[0][5].data[2]
node _T_2219 = bits(_WIRE_165, 0, 0)
connect _WIRE_164.fragmented_superpage, _T_2219
node _T_2220 = bits(_WIRE_165, 1, 1)
connect _WIRE_164.c, _T_2220
node _T_2221 = bits(_WIRE_165, 2, 2)
connect _WIRE_164.eff, _T_2221
node _T_2222 = bits(_WIRE_165, 3, 3)
connect _WIRE_164.paa, _T_2222
node _T_2223 = bits(_WIRE_165, 4, 4)
connect _WIRE_164.pal, _T_2223
node _T_2224 = bits(_WIRE_165, 5, 5)
connect _WIRE_164.ppp, _T_2224
node _T_2225 = bits(_WIRE_165, 6, 6)
connect _WIRE_164.pr, _T_2225
node _T_2226 = bits(_WIRE_165, 7, 7)
connect _WIRE_164.px, _T_2226
node _T_2227 = bits(_WIRE_165, 8, 8)
connect _WIRE_164.pw, _T_2227
node _T_2228 = bits(_WIRE_165, 9, 9)
connect _WIRE_164.hr, _T_2228
node _T_2229 = bits(_WIRE_165, 10, 10)
connect _WIRE_164.hx, _T_2229
node _T_2230 = bits(_WIRE_165, 11, 11)
connect _WIRE_164.hw, _T_2230
node _T_2231 = bits(_WIRE_165, 12, 12)
connect _WIRE_164.sr, _T_2231
node _T_2232 = bits(_WIRE_165, 13, 13)
connect _WIRE_164.sx, _T_2232
node _T_2233 = bits(_WIRE_165, 14, 14)
connect _WIRE_164.sw, _T_2233
node _T_2234 = bits(_WIRE_165, 15, 15)
connect _WIRE_164.gf, _T_2234
node _T_2235 = bits(_WIRE_165, 16, 16)
connect _WIRE_164.pf, _T_2235
node _T_2236 = bits(_WIRE_165, 17, 17)
connect _WIRE_164.ae_stage2, _T_2236
node _T_2237 = bits(_WIRE_165, 18, 18)
connect _WIRE_164.ae_final, _T_2237
node _T_2238 = bits(_WIRE_165, 19, 19)
connect _WIRE_164.ae_ptw, _T_2238
node _T_2239 = bits(_WIRE_165, 20, 20)
connect _WIRE_164.g, _T_2239
node _T_2240 = bits(_WIRE_165, 21, 21)
connect _WIRE_164.u, _T_2240
node _T_2241 = bits(_WIRE_165, 41, 22)
connect _WIRE_164.ppn, _T_2241
wire _WIRE_166 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_167 : UInt<42>
connect _WIRE_167, sectored_entries[0][5].data[3]
node _T_2242 = bits(_WIRE_167, 0, 0)
connect _WIRE_166.fragmented_superpage, _T_2242
node _T_2243 = bits(_WIRE_167, 1, 1)
connect _WIRE_166.c, _T_2243
node _T_2244 = bits(_WIRE_167, 2, 2)
connect _WIRE_166.eff, _T_2244
node _T_2245 = bits(_WIRE_167, 3, 3)
connect _WIRE_166.paa, _T_2245
node _T_2246 = bits(_WIRE_167, 4, 4)
connect _WIRE_166.pal, _T_2246
node _T_2247 = bits(_WIRE_167, 5, 5)
connect _WIRE_166.ppp, _T_2247
node _T_2248 = bits(_WIRE_167, 6, 6)
connect _WIRE_166.pr, _T_2248
node _T_2249 = bits(_WIRE_167, 7, 7)
connect _WIRE_166.px, _T_2249
node _T_2250 = bits(_WIRE_167, 8, 8)
connect _WIRE_166.pw, _T_2250
node _T_2251 = bits(_WIRE_167, 9, 9)
connect _WIRE_166.hr, _T_2251
node _T_2252 = bits(_WIRE_167, 10, 10)
connect _WIRE_166.hx, _T_2252
node _T_2253 = bits(_WIRE_167, 11, 11)
connect _WIRE_166.hw, _T_2253
node _T_2254 = bits(_WIRE_167, 12, 12)
connect _WIRE_166.sr, _T_2254
node _T_2255 = bits(_WIRE_167, 13, 13)
connect _WIRE_166.sx, _T_2255
node _T_2256 = bits(_WIRE_167, 14, 14)
connect _WIRE_166.sw, _T_2256
node _T_2257 = bits(_WIRE_167, 15, 15)
connect _WIRE_166.gf, _T_2257
node _T_2258 = bits(_WIRE_167, 16, 16)
connect _WIRE_166.pf, _T_2258
node _T_2259 = bits(_WIRE_167, 17, 17)
connect _WIRE_166.ae_stage2, _T_2259
node _T_2260 = bits(_WIRE_167, 18, 18)
connect _WIRE_166.ae_final, _T_2260
node _T_2261 = bits(_WIRE_167, 19, 19)
connect _WIRE_166.ae_ptw, _T_2261
node _T_2262 = bits(_WIRE_167, 20, 20)
connect _WIRE_166.g, _T_2262
node _T_2263 = bits(_WIRE_167, 21, 21)
connect _WIRE_166.u, _T_2263
node _T_2264 = bits(_WIRE_167, 41, 22)
connect _WIRE_166.ppn, _T_2264
node _T_2265 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2266 = bits(vpn, 1, 0)
node _T_2267 = eq(UInt<1>(0h0), _T_2266)
node _T_2268 = and(_T_2265, _T_2267)
when _T_2268 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_2269 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2270 = bits(vpn, 1, 0)
node _T_2271 = eq(UInt<1>(0h1), _T_2270)
node _T_2272 = and(_T_2269, _T_2271)
when _T_2272 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_2273 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2274 = bits(vpn, 1, 0)
node _T_2275 = eq(UInt<2>(0h2), _T_2274)
node _T_2276 = and(_T_2273, _T_2275)
when _T_2276 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_2277 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2278 = bits(vpn, 1, 0)
node _T_2279 = eq(UInt<2>(0h3), _T_2278)
node _T_2280 = and(_T_2277, _T_2279)
when _T_2280 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
node _T_2281 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _T_2282 = shr(_T_2281, 18)
node _T_2283 = eq(_T_2282, UInt<1>(0h0))
when _T_2283 :
wire _WIRE_168 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_169 : UInt<42>
connect _WIRE_169, sectored_entries[0][5].data[0]
node _T_2284 = bits(_WIRE_169, 0, 0)
connect _WIRE_168.fragmented_superpage, _T_2284
node _T_2285 = bits(_WIRE_169, 1, 1)
connect _WIRE_168.c, _T_2285
node _T_2286 = bits(_WIRE_169, 2, 2)
connect _WIRE_168.eff, _T_2286
node _T_2287 = bits(_WIRE_169, 3, 3)
connect _WIRE_168.paa, _T_2287
node _T_2288 = bits(_WIRE_169, 4, 4)
connect _WIRE_168.pal, _T_2288
node _T_2289 = bits(_WIRE_169, 5, 5)
connect _WIRE_168.ppp, _T_2289
node _T_2290 = bits(_WIRE_169, 6, 6)
connect _WIRE_168.pr, _T_2290
node _T_2291 = bits(_WIRE_169, 7, 7)
connect _WIRE_168.px, _T_2291
node _T_2292 = bits(_WIRE_169, 8, 8)
connect _WIRE_168.pw, _T_2292
node _T_2293 = bits(_WIRE_169, 9, 9)
connect _WIRE_168.hr, _T_2293
node _T_2294 = bits(_WIRE_169, 10, 10)
connect _WIRE_168.hx, _T_2294
node _T_2295 = bits(_WIRE_169, 11, 11)
connect _WIRE_168.hw, _T_2295
node _T_2296 = bits(_WIRE_169, 12, 12)
connect _WIRE_168.sr, _T_2296
node _T_2297 = bits(_WIRE_169, 13, 13)
connect _WIRE_168.sx, _T_2297
node _T_2298 = bits(_WIRE_169, 14, 14)
connect _WIRE_168.sw, _T_2298
node _T_2299 = bits(_WIRE_169, 15, 15)
connect _WIRE_168.gf, _T_2299
node _T_2300 = bits(_WIRE_169, 16, 16)
connect _WIRE_168.pf, _T_2300
node _T_2301 = bits(_WIRE_169, 17, 17)
connect _WIRE_168.ae_stage2, _T_2301
node _T_2302 = bits(_WIRE_169, 18, 18)
connect _WIRE_168.ae_final, _T_2302
node _T_2303 = bits(_WIRE_169, 19, 19)
connect _WIRE_168.ae_ptw, _T_2303
node _T_2304 = bits(_WIRE_169, 20, 20)
connect _WIRE_168.g, _T_2304
node _T_2305 = bits(_WIRE_169, 21, 21)
connect _WIRE_168.u, _T_2305
node _T_2306 = bits(_WIRE_169, 41, 22)
connect _WIRE_168.ppn, _T_2306
wire _WIRE_170 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_171 : UInt<42>
connect _WIRE_171, sectored_entries[0][5].data[1]
node _T_2307 = bits(_WIRE_171, 0, 0)
connect _WIRE_170.fragmented_superpage, _T_2307
node _T_2308 = bits(_WIRE_171, 1, 1)
connect _WIRE_170.c, _T_2308
node _T_2309 = bits(_WIRE_171, 2, 2)
connect _WIRE_170.eff, _T_2309
node _T_2310 = bits(_WIRE_171, 3, 3)
connect _WIRE_170.paa, _T_2310
node _T_2311 = bits(_WIRE_171, 4, 4)
connect _WIRE_170.pal, _T_2311
node _T_2312 = bits(_WIRE_171, 5, 5)
connect _WIRE_170.ppp, _T_2312
node _T_2313 = bits(_WIRE_171, 6, 6)
connect _WIRE_170.pr, _T_2313
node _T_2314 = bits(_WIRE_171, 7, 7)
connect _WIRE_170.px, _T_2314
node _T_2315 = bits(_WIRE_171, 8, 8)
connect _WIRE_170.pw, _T_2315
node _T_2316 = bits(_WIRE_171, 9, 9)
connect _WIRE_170.hr, _T_2316
node _T_2317 = bits(_WIRE_171, 10, 10)
connect _WIRE_170.hx, _T_2317
node _T_2318 = bits(_WIRE_171, 11, 11)
connect _WIRE_170.hw, _T_2318
node _T_2319 = bits(_WIRE_171, 12, 12)
connect _WIRE_170.sr, _T_2319
node _T_2320 = bits(_WIRE_171, 13, 13)
connect _WIRE_170.sx, _T_2320
node _T_2321 = bits(_WIRE_171, 14, 14)
connect _WIRE_170.sw, _T_2321
node _T_2322 = bits(_WIRE_171, 15, 15)
connect _WIRE_170.gf, _T_2322
node _T_2323 = bits(_WIRE_171, 16, 16)
connect _WIRE_170.pf, _T_2323
node _T_2324 = bits(_WIRE_171, 17, 17)
connect _WIRE_170.ae_stage2, _T_2324
node _T_2325 = bits(_WIRE_171, 18, 18)
connect _WIRE_170.ae_final, _T_2325
node _T_2326 = bits(_WIRE_171, 19, 19)
connect _WIRE_170.ae_ptw, _T_2326
node _T_2327 = bits(_WIRE_171, 20, 20)
connect _WIRE_170.g, _T_2327
node _T_2328 = bits(_WIRE_171, 21, 21)
connect _WIRE_170.u, _T_2328
node _T_2329 = bits(_WIRE_171, 41, 22)
connect _WIRE_170.ppn, _T_2329
wire _WIRE_172 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_173 : UInt<42>
connect _WIRE_173, sectored_entries[0][5].data[2]
node _T_2330 = bits(_WIRE_173, 0, 0)
connect _WIRE_172.fragmented_superpage, _T_2330
node _T_2331 = bits(_WIRE_173, 1, 1)
connect _WIRE_172.c, _T_2331
node _T_2332 = bits(_WIRE_173, 2, 2)
connect _WIRE_172.eff, _T_2332
node _T_2333 = bits(_WIRE_173, 3, 3)
connect _WIRE_172.paa, _T_2333
node _T_2334 = bits(_WIRE_173, 4, 4)
connect _WIRE_172.pal, _T_2334
node _T_2335 = bits(_WIRE_173, 5, 5)
connect _WIRE_172.ppp, _T_2335
node _T_2336 = bits(_WIRE_173, 6, 6)
connect _WIRE_172.pr, _T_2336
node _T_2337 = bits(_WIRE_173, 7, 7)
connect _WIRE_172.px, _T_2337
node _T_2338 = bits(_WIRE_173, 8, 8)
connect _WIRE_172.pw, _T_2338
node _T_2339 = bits(_WIRE_173, 9, 9)
connect _WIRE_172.hr, _T_2339
node _T_2340 = bits(_WIRE_173, 10, 10)
connect _WIRE_172.hx, _T_2340
node _T_2341 = bits(_WIRE_173, 11, 11)
connect _WIRE_172.hw, _T_2341
node _T_2342 = bits(_WIRE_173, 12, 12)
connect _WIRE_172.sr, _T_2342
node _T_2343 = bits(_WIRE_173, 13, 13)
connect _WIRE_172.sx, _T_2343
node _T_2344 = bits(_WIRE_173, 14, 14)
connect _WIRE_172.sw, _T_2344
node _T_2345 = bits(_WIRE_173, 15, 15)
connect _WIRE_172.gf, _T_2345
node _T_2346 = bits(_WIRE_173, 16, 16)
connect _WIRE_172.pf, _T_2346
node _T_2347 = bits(_WIRE_173, 17, 17)
connect _WIRE_172.ae_stage2, _T_2347
node _T_2348 = bits(_WIRE_173, 18, 18)
connect _WIRE_172.ae_final, _T_2348
node _T_2349 = bits(_WIRE_173, 19, 19)
connect _WIRE_172.ae_ptw, _T_2349
node _T_2350 = bits(_WIRE_173, 20, 20)
connect _WIRE_172.g, _T_2350
node _T_2351 = bits(_WIRE_173, 21, 21)
connect _WIRE_172.u, _T_2351
node _T_2352 = bits(_WIRE_173, 41, 22)
connect _WIRE_172.ppn, _T_2352
wire _WIRE_174 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_175 : UInt<42>
connect _WIRE_175, sectored_entries[0][5].data[3]
node _T_2353 = bits(_WIRE_175, 0, 0)
connect _WIRE_174.fragmented_superpage, _T_2353
node _T_2354 = bits(_WIRE_175, 1, 1)
connect _WIRE_174.c, _T_2354
node _T_2355 = bits(_WIRE_175, 2, 2)
connect _WIRE_174.eff, _T_2355
node _T_2356 = bits(_WIRE_175, 3, 3)
connect _WIRE_174.paa, _T_2356
node _T_2357 = bits(_WIRE_175, 4, 4)
connect _WIRE_174.pal, _T_2357
node _T_2358 = bits(_WIRE_175, 5, 5)
connect _WIRE_174.ppp, _T_2358
node _T_2359 = bits(_WIRE_175, 6, 6)
connect _WIRE_174.pr, _T_2359
node _T_2360 = bits(_WIRE_175, 7, 7)
connect _WIRE_174.px, _T_2360
node _T_2361 = bits(_WIRE_175, 8, 8)
connect _WIRE_174.pw, _T_2361
node _T_2362 = bits(_WIRE_175, 9, 9)
connect _WIRE_174.hr, _T_2362
node _T_2363 = bits(_WIRE_175, 10, 10)
connect _WIRE_174.hx, _T_2363
node _T_2364 = bits(_WIRE_175, 11, 11)
connect _WIRE_174.hw, _T_2364
node _T_2365 = bits(_WIRE_175, 12, 12)
connect _WIRE_174.sr, _T_2365
node _T_2366 = bits(_WIRE_175, 13, 13)
connect _WIRE_174.sx, _T_2366
node _T_2367 = bits(_WIRE_175, 14, 14)
connect _WIRE_174.sw, _T_2367
node _T_2368 = bits(_WIRE_175, 15, 15)
connect _WIRE_174.gf, _T_2368
node _T_2369 = bits(_WIRE_175, 16, 16)
connect _WIRE_174.pf, _T_2369
node _T_2370 = bits(_WIRE_175, 17, 17)
connect _WIRE_174.ae_stage2, _T_2370
node _T_2371 = bits(_WIRE_175, 18, 18)
connect _WIRE_174.ae_final, _T_2371
node _T_2372 = bits(_WIRE_175, 19, 19)
connect _WIRE_174.ae_ptw, _T_2372
node _T_2373 = bits(_WIRE_175, 20, 20)
connect _WIRE_174.g, _T_2373
node _T_2374 = bits(_WIRE_175, 21, 21)
connect _WIRE_174.u, _T_2374
node _T_2375 = bits(_WIRE_175, 41, 22)
connect _WIRE_174.ppn, _T_2375
node _T_2376 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2377 = and(_T_2376, _WIRE_168.fragmented_superpage)
when _T_2377 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_2378 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2379 = and(_T_2378, _WIRE_170.fragmented_superpage)
when _T_2379 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_2380 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2381 = and(_T_2380, _WIRE_172.fragmented_superpage)
when _T_2381 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_2382 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2383 = and(_T_2382, _WIRE_174.fragmented_superpage)
when _T_2383 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
else :
node _T_2384 = eq(hg_5, UInt<1>(0h0))
node _T_2385 = and(_T_2384, io.sfence.bits.rs2)
when _T_2385 :
wire _WIRE_176 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_177 : UInt<42>
connect _WIRE_177, sectored_entries[0][5].data[0]
node _T_2386 = bits(_WIRE_177, 0, 0)
connect _WIRE_176.fragmented_superpage, _T_2386
node _T_2387 = bits(_WIRE_177, 1, 1)
connect _WIRE_176.c, _T_2387
node _T_2388 = bits(_WIRE_177, 2, 2)
connect _WIRE_176.eff, _T_2388
node _T_2389 = bits(_WIRE_177, 3, 3)
connect _WIRE_176.paa, _T_2389
node _T_2390 = bits(_WIRE_177, 4, 4)
connect _WIRE_176.pal, _T_2390
node _T_2391 = bits(_WIRE_177, 5, 5)
connect _WIRE_176.ppp, _T_2391
node _T_2392 = bits(_WIRE_177, 6, 6)
connect _WIRE_176.pr, _T_2392
node _T_2393 = bits(_WIRE_177, 7, 7)
connect _WIRE_176.px, _T_2393
node _T_2394 = bits(_WIRE_177, 8, 8)
connect _WIRE_176.pw, _T_2394
node _T_2395 = bits(_WIRE_177, 9, 9)
connect _WIRE_176.hr, _T_2395
node _T_2396 = bits(_WIRE_177, 10, 10)
connect _WIRE_176.hx, _T_2396
node _T_2397 = bits(_WIRE_177, 11, 11)
connect _WIRE_176.hw, _T_2397
node _T_2398 = bits(_WIRE_177, 12, 12)
connect _WIRE_176.sr, _T_2398
node _T_2399 = bits(_WIRE_177, 13, 13)
connect _WIRE_176.sx, _T_2399
node _T_2400 = bits(_WIRE_177, 14, 14)
connect _WIRE_176.sw, _T_2400
node _T_2401 = bits(_WIRE_177, 15, 15)
connect _WIRE_176.gf, _T_2401
node _T_2402 = bits(_WIRE_177, 16, 16)
connect _WIRE_176.pf, _T_2402
node _T_2403 = bits(_WIRE_177, 17, 17)
connect _WIRE_176.ae_stage2, _T_2403
node _T_2404 = bits(_WIRE_177, 18, 18)
connect _WIRE_176.ae_final, _T_2404
node _T_2405 = bits(_WIRE_177, 19, 19)
connect _WIRE_176.ae_ptw, _T_2405
node _T_2406 = bits(_WIRE_177, 20, 20)
connect _WIRE_176.g, _T_2406
node _T_2407 = bits(_WIRE_177, 21, 21)
connect _WIRE_176.u, _T_2407
node _T_2408 = bits(_WIRE_177, 41, 22)
connect _WIRE_176.ppn, _T_2408
wire _WIRE_178 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_179 : UInt<42>
connect _WIRE_179, sectored_entries[0][5].data[1]
node _T_2409 = bits(_WIRE_179, 0, 0)
connect _WIRE_178.fragmented_superpage, _T_2409
node _T_2410 = bits(_WIRE_179, 1, 1)
connect _WIRE_178.c, _T_2410
node _T_2411 = bits(_WIRE_179, 2, 2)
connect _WIRE_178.eff, _T_2411
node _T_2412 = bits(_WIRE_179, 3, 3)
connect _WIRE_178.paa, _T_2412
node _T_2413 = bits(_WIRE_179, 4, 4)
connect _WIRE_178.pal, _T_2413
node _T_2414 = bits(_WIRE_179, 5, 5)
connect _WIRE_178.ppp, _T_2414
node _T_2415 = bits(_WIRE_179, 6, 6)
connect _WIRE_178.pr, _T_2415
node _T_2416 = bits(_WIRE_179, 7, 7)
connect _WIRE_178.px, _T_2416
node _T_2417 = bits(_WIRE_179, 8, 8)
connect _WIRE_178.pw, _T_2417
node _T_2418 = bits(_WIRE_179, 9, 9)
connect _WIRE_178.hr, _T_2418
node _T_2419 = bits(_WIRE_179, 10, 10)
connect _WIRE_178.hx, _T_2419
node _T_2420 = bits(_WIRE_179, 11, 11)
connect _WIRE_178.hw, _T_2420
node _T_2421 = bits(_WIRE_179, 12, 12)
connect _WIRE_178.sr, _T_2421
node _T_2422 = bits(_WIRE_179, 13, 13)
connect _WIRE_178.sx, _T_2422
node _T_2423 = bits(_WIRE_179, 14, 14)
connect _WIRE_178.sw, _T_2423
node _T_2424 = bits(_WIRE_179, 15, 15)
connect _WIRE_178.gf, _T_2424
node _T_2425 = bits(_WIRE_179, 16, 16)
connect _WIRE_178.pf, _T_2425
node _T_2426 = bits(_WIRE_179, 17, 17)
connect _WIRE_178.ae_stage2, _T_2426
node _T_2427 = bits(_WIRE_179, 18, 18)
connect _WIRE_178.ae_final, _T_2427
node _T_2428 = bits(_WIRE_179, 19, 19)
connect _WIRE_178.ae_ptw, _T_2428
node _T_2429 = bits(_WIRE_179, 20, 20)
connect _WIRE_178.g, _T_2429
node _T_2430 = bits(_WIRE_179, 21, 21)
connect _WIRE_178.u, _T_2430
node _T_2431 = bits(_WIRE_179, 41, 22)
connect _WIRE_178.ppn, _T_2431
wire _WIRE_180 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_181 : UInt<42>
connect _WIRE_181, sectored_entries[0][5].data[2]
node _T_2432 = bits(_WIRE_181, 0, 0)
connect _WIRE_180.fragmented_superpage, _T_2432
node _T_2433 = bits(_WIRE_181, 1, 1)
connect _WIRE_180.c, _T_2433
node _T_2434 = bits(_WIRE_181, 2, 2)
connect _WIRE_180.eff, _T_2434
node _T_2435 = bits(_WIRE_181, 3, 3)
connect _WIRE_180.paa, _T_2435
node _T_2436 = bits(_WIRE_181, 4, 4)
connect _WIRE_180.pal, _T_2436
node _T_2437 = bits(_WIRE_181, 5, 5)
connect _WIRE_180.ppp, _T_2437
node _T_2438 = bits(_WIRE_181, 6, 6)
connect _WIRE_180.pr, _T_2438
node _T_2439 = bits(_WIRE_181, 7, 7)
connect _WIRE_180.px, _T_2439
node _T_2440 = bits(_WIRE_181, 8, 8)
connect _WIRE_180.pw, _T_2440
node _T_2441 = bits(_WIRE_181, 9, 9)
connect _WIRE_180.hr, _T_2441
node _T_2442 = bits(_WIRE_181, 10, 10)
connect _WIRE_180.hx, _T_2442
node _T_2443 = bits(_WIRE_181, 11, 11)
connect _WIRE_180.hw, _T_2443
node _T_2444 = bits(_WIRE_181, 12, 12)
connect _WIRE_180.sr, _T_2444
node _T_2445 = bits(_WIRE_181, 13, 13)
connect _WIRE_180.sx, _T_2445
node _T_2446 = bits(_WIRE_181, 14, 14)
connect _WIRE_180.sw, _T_2446
node _T_2447 = bits(_WIRE_181, 15, 15)
connect _WIRE_180.gf, _T_2447
node _T_2448 = bits(_WIRE_181, 16, 16)
connect _WIRE_180.pf, _T_2448
node _T_2449 = bits(_WIRE_181, 17, 17)
connect _WIRE_180.ae_stage2, _T_2449
node _T_2450 = bits(_WIRE_181, 18, 18)
connect _WIRE_180.ae_final, _T_2450
node _T_2451 = bits(_WIRE_181, 19, 19)
connect _WIRE_180.ae_ptw, _T_2451
node _T_2452 = bits(_WIRE_181, 20, 20)
connect _WIRE_180.g, _T_2452
node _T_2453 = bits(_WIRE_181, 21, 21)
connect _WIRE_180.u, _T_2453
node _T_2454 = bits(_WIRE_181, 41, 22)
connect _WIRE_180.ppn, _T_2454
wire _WIRE_182 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_183 : UInt<42>
connect _WIRE_183, sectored_entries[0][5].data[3]
node _T_2455 = bits(_WIRE_183, 0, 0)
connect _WIRE_182.fragmented_superpage, _T_2455
node _T_2456 = bits(_WIRE_183, 1, 1)
connect _WIRE_182.c, _T_2456
node _T_2457 = bits(_WIRE_183, 2, 2)
connect _WIRE_182.eff, _T_2457
node _T_2458 = bits(_WIRE_183, 3, 3)
connect _WIRE_182.paa, _T_2458
node _T_2459 = bits(_WIRE_183, 4, 4)
connect _WIRE_182.pal, _T_2459
node _T_2460 = bits(_WIRE_183, 5, 5)
connect _WIRE_182.ppp, _T_2460
node _T_2461 = bits(_WIRE_183, 6, 6)
connect _WIRE_182.pr, _T_2461
node _T_2462 = bits(_WIRE_183, 7, 7)
connect _WIRE_182.px, _T_2462
node _T_2463 = bits(_WIRE_183, 8, 8)
connect _WIRE_182.pw, _T_2463
node _T_2464 = bits(_WIRE_183, 9, 9)
connect _WIRE_182.hr, _T_2464
node _T_2465 = bits(_WIRE_183, 10, 10)
connect _WIRE_182.hx, _T_2465
node _T_2466 = bits(_WIRE_183, 11, 11)
connect _WIRE_182.hw, _T_2466
node _T_2467 = bits(_WIRE_183, 12, 12)
connect _WIRE_182.sr, _T_2467
node _T_2468 = bits(_WIRE_183, 13, 13)
connect _WIRE_182.sx, _T_2468
node _T_2469 = bits(_WIRE_183, 14, 14)
connect _WIRE_182.sw, _T_2469
node _T_2470 = bits(_WIRE_183, 15, 15)
connect _WIRE_182.gf, _T_2470
node _T_2471 = bits(_WIRE_183, 16, 16)
connect _WIRE_182.pf, _T_2471
node _T_2472 = bits(_WIRE_183, 17, 17)
connect _WIRE_182.ae_stage2, _T_2472
node _T_2473 = bits(_WIRE_183, 18, 18)
connect _WIRE_182.ae_final, _T_2473
node _T_2474 = bits(_WIRE_183, 19, 19)
connect _WIRE_182.ae_ptw, _T_2474
node _T_2475 = bits(_WIRE_183, 20, 20)
connect _WIRE_182.g, _T_2475
node _T_2476 = bits(_WIRE_183, 21, 21)
connect _WIRE_182.u, _T_2476
node _T_2477 = bits(_WIRE_183, 41, 22)
connect _WIRE_182.ppn, _T_2477
node _T_2478 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2479 = eq(_WIRE_176.g, UInt<1>(0h0))
node _T_2480 = and(_T_2478, _T_2479)
when _T_2480 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_2481 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2482 = eq(_WIRE_178.g, UInt<1>(0h0))
node _T_2483 = and(_T_2481, _T_2482)
when _T_2483 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_2484 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2485 = eq(_WIRE_180.g, UInt<1>(0h0))
node _T_2486 = and(_T_2484, _T_2485)
when _T_2486 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_2487 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2488 = eq(_WIRE_182.g, UInt<1>(0h0))
node _T_2489 = and(_T_2487, _T_2488)
when _T_2489 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
else :
node _T_2490 = or(hv_5, hg_5)
wire _WIRE_184 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_185 : UInt<42>
connect _WIRE_185, sectored_entries[0][5].data[0]
node _T_2491 = bits(_WIRE_185, 0, 0)
connect _WIRE_184.fragmented_superpage, _T_2491
node _T_2492 = bits(_WIRE_185, 1, 1)
connect _WIRE_184.c, _T_2492
node _T_2493 = bits(_WIRE_185, 2, 2)
connect _WIRE_184.eff, _T_2493
node _T_2494 = bits(_WIRE_185, 3, 3)
connect _WIRE_184.paa, _T_2494
node _T_2495 = bits(_WIRE_185, 4, 4)
connect _WIRE_184.pal, _T_2495
node _T_2496 = bits(_WIRE_185, 5, 5)
connect _WIRE_184.ppp, _T_2496
node _T_2497 = bits(_WIRE_185, 6, 6)
connect _WIRE_184.pr, _T_2497
node _T_2498 = bits(_WIRE_185, 7, 7)
connect _WIRE_184.px, _T_2498
node _T_2499 = bits(_WIRE_185, 8, 8)
connect _WIRE_184.pw, _T_2499
node _T_2500 = bits(_WIRE_185, 9, 9)
connect _WIRE_184.hr, _T_2500
node _T_2501 = bits(_WIRE_185, 10, 10)
connect _WIRE_184.hx, _T_2501
node _T_2502 = bits(_WIRE_185, 11, 11)
connect _WIRE_184.hw, _T_2502
node _T_2503 = bits(_WIRE_185, 12, 12)
connect _WIRE_184.sr, _T_2503
node _T_2504 = bits(_WIRE_185, 13, 13)
connect _WIRE_184.sx, _T_2504
node _T_2505 = bits(_WIRE_185, 14, 14)
connect _WIRE_184.sw, _T_2505
node _T_2506 = bits(_WIRE_185, 15, 15)
connect _WIRE_184.gf, _T_2506
node _T_2507 = bits(_WIRE_185, 16, 16)
connect _WIRE_184.pf, _T_2507
node _T_2508 = bits(_WIRE_185, 17, 17)
connect _WIRE_184.ae_stage2, _T_2508
node _T_2509 = bits(_WIRE_185, 18, 18)
connect _WIRE_184.ae_final, _T_2509
node _T_2510 = bits(_WIRE_185, 19, 19)
connect _WIRE_184.ae_ptw, _T_2510
node _T_2511 = bits(_WIRE_185, 20, 20)
connect _WIRE_184.g, _T_2511
node _T_2512 = bits(_WIRE_185, 21, 21)
connect _WIRE_184.u, _T_2512
node _T_2513 = bits(_WIRE_185, 41, 22)
connect _WIRE_184.ppn, _T_2513
wire _WIRE_186 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_187 : UInt<42>
connect _WIRE_187, sectored_entries[0][5].data[1]
node _T_2514 = bits(_WIRE_187, 0, 0)
connect _WIRE_186.fragmented_superpage, _T_2514
node _T_2515 = bits(_WIRE_187, 1, 1)
connect _WIRE_186.c, _T_2515
node _T_2516 = bits(_WIRE_187, 2, 2)
connect _WIRE_186.eff, _T_2516
node _T_2517 = bits(_WIRE_187, 3, 3)
connect _WIRE_186.paa, _T_2517
node _T_2518 = bits(_WIRE_187, 4, 4)
connect _WIRE_186.pal, _T_2518
node _T_2519 = bits(_WIRE_187, 5, 5)
connect _WIRE_186.ppp, _T_2519
node _T_2520 = bits(_WIRE_187, 6, 6)
connect _WIRE_186.pr, _T_2520
node _T_2521 = bits(_WIRE_187, 7, 7)
connect _WIRE_186.px, _T_2521
node _T_2522 = bits(_WIRE_187, 8, 8)
connect _WIRE_186.pw, _T_2522
node _T_2523 = bits(_WIRE_187, 9, 9)
connect _WIRE_186.hr, _T_2523
node _T_2524 = bits(_WIRE_187, 10, 10)
connect _WIRE_186.hx, _T_2524
node _T_2525 = bits(_WIRE_187, 11, 11)
connect _WIRE_186.hw, _T_2525
node _T_2526 = bits(_WIRE_187, 12, 12)
connect _WIRE_186.sr, _T_2526
node _T_2527 = bits(_WIRE_187, 13, 13)
connect _WIRE_186.sx, _T_2527
node _T_2528 = bits(_WIRE_187, 14, 14)
connect _WIRE_186.sw, _T_2528
node _T_2529 = bits(_WIRE_187, 15, 15)
connect _WIRE_186.gf, _T_2529
node _T_2530 = bits(_WIRE_187, 16, 16)
connect _WIRE_186.pf, _T_2530
node _T_2531 = bits(_WIRE_187, 17, 17)
connect _WIRE_186.ae_stage2, _T_2531
node _T_2532 = bits(_WIRE_187, 18, 18)
connect _WIRE_186.ae_final, _T_2532
node _T_2533 = bits(_WIRE_187, 19, 19)
connect _WIRE_186.ae_ptw, _T_2533
node _T_2534 = bits(_WIRE_187, 20, 20)
connect _WIRE_186.g, _T_2534
node _T_2535 = bits(_WIRE_187, 21, 21)
connect _WIRE_186.u, _T_2535
node _T_2536 = bits(_WIRE_187, 41, 22)
connect _WIRE_186.ppn, _T_2536
wire _WIRE_188 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_189 : UInt<42>
connect _WIRE_189, sectored_entries[0][5].data[2]
node _T_2537 = bits(_WIRE_189, 0, 0)
connect _WIRE_188.fragmented_superpage, _T_2537
node _T_2538 = bits(_WIRE_189, 1, 1)
connect _WIRE_188.c, _T_2538
node _T_2539 = bits(_WIRE_189, 2, 2)
connect _WIRE_188.eff, _T_2539
node _T_2540 = bits(_WIRE_189, 3, 3)
connect _WIRE_188.paa, _T_2540
node _T_2541 = bits(_WIRE_189, 4, 4)
connect _WIRE_188.pal, _T_2541
node _T_2542 = bits(_WIRE_189, 5, 5)
connect _WIRE_188.ppp, _T_2542
node _T_2543 = bits(_WIRE_189, 6, 6)
connect _WIRE_188.pr, _T_2543
node _T_2544 = bits(_WIRE_189, 7, 7)
connect _WIRE_188.px, _T_2544
node _T_2545 = bits(_WIRE_189, 8, 8)
connect _WIRE_188.pw, _T_2545
node _T_2546 = bits(_WIRE_189, 9, 9)
connect _WIRE_188.hr, _T_2546
node _T_2547 = bits(_WIRE_189, 10, 10)
connect _WIRE_188.hx, _T_2547
node _T_2548 = bits(_WIRE_189, 11, 11)
connect _WIRE_188.hw, _T_2548
node _T_2549 = bits(_WIRE_189, 12, 12)
connect _WIRE_188.sr, _T_2549
node _T_2550 = bits(_WIRE_189, 13, 13)
connect _WIRE_188.sx, _T_2550
node _T_2551 = bits(_WIRE_189, 14, 14)
connect _WIRE_188.sw, _T_2551
node _T_2552 = bits(_WIRE_189, 15, 15)
connect _WIRE_188.gf, _T_2552
node _T_2553 = bits(_WIRE_189, 16, 16)
connect _WIRE_188.pf, _T_2553
node _T_2554 = bits(_WIRE_189, 17, 17)
connect _WIRE_188.ae_stage2, _T_2554
node _T_2555 = bits(_WIRE_189, 18, 18)
connect _WIRE_188.ae_final, _T_2555
node _T_2556 = bits(_WIRE_189, 19, 19)
connect _WIRE_188.ae_ptw, _T_2556
node _T_2557 = bits(_WIRE_189, 20, 20)
connect _WIRE_188.g, _T_2557
node _T_2558 = bits(_WIRE_189, 21, 21)
connect _WIRE_188.u, _T_2558
node _T_2559 = bits(_WIRE_189, 41, 22)
connect _WIRE_188.ppn, _T_2559
wire _WIRE_190 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_191 : UInt<42>
connect _WIRE_191, sectored_entries[0][5].data[3]
node _T_2560 = bits(_WIRE_191, 0, 0)
connect _WIRE_190.fragmented_superpage, _T_2560
node _T_2561 = bits(_WIRE_191, 1, 1)
connect _WIRE_190.c, _T_2561
node _T_2562 = bits(_WIRE_191, 2, 2)
connect _WIRE_190.eff, _T_2562
node _T_2563 = bits(_WIRE_191, 3, 3)
connect _WIRE_190.paa, _T_2563
node _T_2564 = bits(_WIRE_191, 4, 4)
connect _WIRE_190.pal, _T_2564
node _T_2565 = bits(_WIRE_191, 5, 5)
connect _WIRE_190.ppp, _T_2565
node _T_2566 = bits(_WIRE_191, 6, 6)
connect _WIRE_190.pr, _T_2566
node _T_2567 = bits(_WIRE_191, 7, 7)
connect _WIRE_190.px, _T_2567
node _T_2568 = bits(_WIRE_191, 8, 8)
connect _WIRE_190.pw, _T_2568
node _T_2569 = bits(_WIRE_191, 9, 9)
connect _WIRE_190.hr, _T_2569
node _T_2570 = bits(_WIRE_191, 10, 10)
connect _WIRE_190.hx, _T_2570
node _T_2571 = bits(_WIRE_191, 11, 11)
connect _WIRE_190.hw, _T_2571
node _T_2572 = bits(_WIRE_191, 12, 12)
connect _WIRE_190.sr, _T_2572
node _T_2573 = bits(_WIRE_191, 13, 13)
connect _WIRE_190.sx, _T_2573
node _T_2574 = bits(_WIRE_191, 14, 14)
connect _WIRE_190.sw, _T_2574
node _T_2575 = bits(_WIRE_191, 15, 15)
connect _WIRE_190.gf, _T_2575
node _T_2576 = bits(_WIRE_191, 16, 16)
connect _WIRE_190.pf, _T_2576
node _T_2577 = bits(_WIRE_191, 17, 17)
connect _WIRE_190.ae_stage2, _T_2577
node _T_2578 = bits(_WIRE_191, 18, 18)
connect _WIRE_190.ae_final, _T_2578
node _T_2579 = bits(_WIRE_191, 19, 19)
connect _WIRE_190.ae_ptw, _T_2579
node _T_2580 = bits(_WIRE_191, 20, 20)
connect _WIRE_190.g, _T_2580
node _T_2581 = bits(_WIRE_191, 21, 21)
connect _WIRE_190.u, _T_2581
node _T_2582 = bits(_WIRE_191, 41, 22)
connect _WIRE_190.ppn, _T_2582
node _T_2583 = eq(sectored_entries[0][5].tag_v, _T_2490)
when _T_2583 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_2584 = eq(sectored_entries[0][5].tag_v, _T_2490)
when _T_2584 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_2585 = eq(sectored_entries[0][5].tag_v, _T_2490)
when _T_2585 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_2586 = eq(sectored_entries[0][5].tag_v, _T_2490)
when _T_2586 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
node hv_6 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_6 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_2587 = eq(hg_6, UInt<1>(0h0))
node _T_2588 = and(_T_2587, io.sfence.bits.rs1)
when _T_2588 :
node _T_2589 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _T_2590 = shr(_T_2589, 2)
node _T_2591 = eq(_T_2590, UInt<1>(0h0))
node _T_2592 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2593 = and(_T_2591, _T_2592)
when _T_2593 :
wire _WIRE_192 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_193 : UInt<42>
connect _WIRE_193, sectored_entries[0][6].data[0]
node _T_2594 = bits(_WIRE_193, 0, 0)
connect _WIRE_192.fragmented_superpage, _T_2594
node _T_2595 = bits(_WIRE_193, 1, 1)
connect _WIRE_192.c, _T_2595
node _T_2596 = bits(_WIRE_193, 2, 2)
connect _WIRE_192.eff, _T_2596
node _T_2597 = bits(_WIRE_193, 3, 3)
connect _WIRE_192.paa, _T_2597
node _T_2598 = bits(_WIRE_193, 4, 4)
connect _WIRE_192.pal, _T_2598
node _T_2599 = bits(_WIRE_193, 5, 5)
connect _WIRE_192.ppp, _T_2599
node _T_2600 = bits(_WIRE_193, 6, 6)
connect _WIRE_192.pr, _T_2600
node _T_2601 = bits(_WIRE_193, 7, 7)
connect _WIRE_192.px, _T_2601
node _T_2602 = bits(_WIRE_193, 8, 8)
connect _WIRE_192.pw, _T_2602
node _T_2603 = bits(_WIRE_193, 9, 9)
connect _WIRE_192.hr, _T_2603
node _T_2604 = bits(_WIRE_193, 10, 10)
connect _WIRE_192.hx, _T_2604
node _T_2605 = bits(_WIRE_193, 11, 11)
connect _WIRE_192.hw, _T_2605
node _T_2606 = bits(_WIRE_193, 12, 12)
connect _WIRE_192.sr, _T_2606
node _T_2607 = bits(_WIRE_193, 13, 13)
connect _WIRE_192.sx, _T_2607
node _T_2608 = bits(_WIRE_193, 14, 14)
connect _WIRE_192.sw, _T_2608
node _T_2609 = bits(_WIRE_193, 15, 15)
connect _WIRE_192.gf, _T_2609
node _T_2610 = bits(_WIRE_193, 16, 16)
connect _WIRE_192.pf, _T_2610
node _T_2611 = bits(_WIRE_193, 17, 17)
connect _WIRE_192.ae_stage2, _T_2611
node _T_2612 = bits(_WIRE_193, 18, 18)
connect _WIRE_192.ae_final, _T_2612
node _T_2613 = bits(_WIRE_193, 19, 19)
connect _WIRE_192.ae_ptw, _T_2613
node _T_2614 = bits(_WIRE_193, 20, 20)
connect _WIRE_192.g, _T_2614
node _T_2615 = bits(_WIRE_193, 21, 21)
connect _WIRE_192.u, _T_2615
node _T_2616 = bits(_WIRE_193, 41, 22)
connect _WIRE_192.ppn, _T_2616
wire _WIRE_194 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_195 : UInt<42>
connect _WIRE_195, sectored_entries[0][6].data[1]
node _T_2617 = bits(_WIRE_195, 0, 0)
connect _WIRE_194.fragmented_superpage, _T_2617
node _T_2618 = bits(_WIRE_195, 1, 1)
connect _WIRE_194.c, _T_2618
node _T_2619 = bits(_WIRE_195, 2, 2)
connect _WIRE_194.eff, _T_2619
node _T_2620 = bits(_WIRE_195, 3, 3)
connect _WIRE_194.paa, _T_2620
node _T_2621 = bits(_WIRE_195, 4, 4)
connect _WIRE_194.pal, _T_2621
node _T_2622 = bits(_WIRE_195, 5, 5)
connect _WIRE_194.ppp, _T_2622
node _T_2623 = bits(_WIRE_195, 6, 6)
connect _WIRE_194.pr, _T_2623
node _T_2624 = bits(_WIRE_195, 7, 7)
connect _WIRE_194.px, _T_2624
node _T_2625 = bits(_WIRE_195, 8, 8)
connect _WIRE_194.pw, _T_2625
node _T_2626 = bits(_WIRE_195, 9, 9)
connect _WIRE_194.hr, _T_2626
node _T_2627 = bits(_WIRE_195, 10, 10)
connect _WIRE_194.hx, _T_2627
node _T_2628 = bits(_WIRE_195, 11, 11)
connect _WIRE_194.hw, _T_2628
node _T_2629 = bits(_WIRE_195, 12, 12)
connect _WIRE_194.sr, _T_2629
node _T_2630 = bits(_WIRE_195, 13, 13)
connect _WIRE_194.sx, _T_2630
node _T_2631 = bits(_WIRE_195, 14, 14)
connect _WIRE_194.sw, _T_2631
node _T_2632 = bits(_WIRE_195, 15, 15)
connect _WIRE_194.gf, _T_2632
node _T_2633 = bits(_WIRE_195, 16, 16)
connect _WIRE_194.pf, _T_2633
node _T_2634 = bits(_WIRE_195, 17, 17)
connect _WIRE_194.ae_stage2, _T_2634
node _T_2635 = bits(_WIRE_195, 18, 18)
connect _WIRE_194.ae_final, _T_2635
node _T_2636 = bits(_WIRE_195, 19, 19)
connect _WIRE_194.ae_ptw, _T_2636
node _T_2637 = bits(_WIRE_195, 20, 20)
connect _WIRE_194.g, _T_2637
node _T_2638 = bits(_WIRE_195, 21, 21)
connect _WIRE_194.u, _T_2638
node _T_2639 = bits(_WIRE_195, 41, 22)
connect _WIRE_194.ppn, _T_2639
wire _WIRE_196 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_197 : UInt<42>
connect _WIRE_197, sectored_entries[0][6].data[2]
node _T_2640 = bits(_WIRE_197, 0, 0)
connect _WIRE_196.fragmented_superpage, _T_2640
node _T_2641 = bits(_WIRE_197, 1, 1)
connect _WIRE_196.c, _T_2641
node _T_2642 = bits(_WIRE_197, 2, 2)
connect _WIRE_196.eff, _T_2642
node _T_2643 = bits(_WIRE_197, 3, 3)
connect _WIRE_196.paa, _T_2643
node _T_2644 = bits(_WIRE_197, 4, 4)
connect _WIRE_196.pal, _T_2644
node _T_2645 = bits(_WIRE_197, 5, 5)
connect _WIRE_196.ppp, _T_2645
node _T_2646 = bits(_WIRE_197, 6, 6)
connect _WIRE_196.pr, _T_2646
node _T_2647 = bits(_WIRE_197, 7, 7)
connect _WIRE_196.px, _T_2647
node _T_2648 = bits(_WIRE_197, 8, 8)
connect _WIRE_196.pw, _T_2648
node _T_2649 = bits(_WIRE_197, 9, 9)
connect _WIRE_196.hr, _T_2649
node _T_2650 = bits(_WIRE_197, 10, 10)
connect _WIRE_196.hx, _T_2650
node _T_2651 = bits(_WIRE_197, 11, 11)
connect _WIRE_196.hw, _T_2651
node _T_2652 = bits(_WIRE_197, 12, 12)
connect _WIRE_196.sr, _T_2652
node _T_2653 = bits(_WIRE_197, 13, 13)
connect _WIRE_196.sx, _T_2653
node _T_2654 = bits(_WIRE_197, 14, 14)
connect _WIRE_196.sw, _T_2654
node _T_2655 = bits(_WIRE_197, 15, 15)
connect _WIRE_196.gf, _T_2655
node _T_2656 = bits(_WIRE_197, 16, 16)
connect _WIRE_196.pf, _T_2656
node _T_2657 = bits(_WIRE_197, 17, 17)
connect _WIRE_196.ae_stage2, _T_2657
node _T_2658 = bits(_WIRE_197, 18, 18)
connect _WIRE_196.ae_final, _T_2658
node _T_2659 = bits(_WIRE_197, 19, 19)
connect _WIRE_196.ae_ptw, _T_2659
node _T_2660 = bits(_WIRE_197, 20, 20)
connect _WIRE_196.g, _T_2660
node _T_2661 = bits(_WIRE_197, 21, 21)
connect _WIRE_196.u, _T_2661
node _T_2662 = bits(_WIRE_197, 41, 22)
connect _WIRE_196.ppn, _T_2662
wire _WIRE_198 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_199 : UInt<42>
connect _WIRE_199, sectored_entries[0][6].data[3]
node _T_2663 = bits(_WIRE_199, 0, 0)
connect _WIRE_198.fragmented_superpage, _T_2663
node _T_2664 = bits(_WIRE_199, 1, 1)
connect _WIRE_198.c, _T_2664
node _T_2665 = bits(_WIRE_199, 2, 2)
connect _WIRE_198.eff, _T_2665
node _T_2666 = bits(_WIRE_199, 3, 3)
connect _WIRE_198.paa, _T_2666
node _T_2667 = bits(_WIRE_199, 4, 4)
connect _WIRE_198.pal, _T_2667
node _T_2668 = bits(_WIRE_199, 5, 5)
connect _WIRE_198.ppp, _T_2668
node _T_2669 = bits(_WIRE_199, 6, 6)
connect _WIRE_198.pr, _T_2669
node _T_2670 = bits(_WIRE_199, 7, 7)
connect _WIRE_198.px, _T_2670
node _T_2671 = bits(_WIRE_199, 8, 8)
connect _WIRE_198.pw, _T_2671
node _T_2672 = bits(_WIRE_199, 9, 9)
connect _WIRE_198.hr, _T_2672
node _T_2673 = bits(_WIRE_199, 10, 10)
connect _WIRE_198.hx, _T_2673
node _T_2674 = bits(_WIRE_199, 11, 11)
connect _WIRE_198.hw, _T_2674
node _T_2675 = bits(_WIRE_199, 12, 12)
connect _WIRE_198.sr, _T_2675
node _T_2676 = bits(_WIRE_199, 13, 13)
connect _WIRE_198.sx, _T_2676
node _T_2677 = bits(_WIRE_199, 14, 14)
connect _WIRE_198.sw, _T_2677
node _T_2678 = bits(_WIRE_199, 15, 15)
connect _WIRE_198.gf, _T_2678
node _T_2679 = bits(_WIRE_199, 16, 16)
connect _WIRE_198.pf, _T_2679
node _T_2680 = bits(_WIRE_199, 17, 17)
connect _WIRE_198.ae_stage2, _T_2680
node _T_2681 = bits(_WIRE_199, 18, 18)
connect _WIRE_198.ae_final, _T_2681
node _T_2682 = bits(_WIRE_199, 19, 19)
connect _WIRE_198.ae_ptw, _T_2682
node _T_2683 = bits(_WIRE_199, 20, 20)
connect _WIRE_198.g, _T_2683
node _T_2684 = bits(_WIRE_199, 21, 21)
connect _WIRE_198.u, _T_2684
node _T_2685 = bits(_WIRE_199, 41, 22)
connect _WIRE_198.ppn, _T_2685
node _T_2686 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2687 = bits(vpn, 1, 0)
node _T_2688 = eq(UInt<1>(0h0), _T_2687)
node _T_2689 = and(_T_2686, _T_2688)
when _T_2689 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_2690 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2691 = bits(vpn, 1, 0)
node _T_2692 = eq(UInt<1>(0h1), _T_2691)
node _T_2693 = and(_T_2690, _T_2692)
when _T_2693 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_2694 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2695 = bits(vpn, 1, 0)
node _T_2696 = eq(UInt<2>(0h2), _T_2695)
node _T_2697 = and(_T_2694, _T_2696)
when _T_2697 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_2698 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2699 = bits(vpn, 1, 0)
node _T_2700 = eq(UInt<2>(0h3), _T_2699)
node _T_2701 = and(_T_2698, _T_2700)
when _T_2701 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
node _T_2702 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _T_2703 = shr(_T_2702, 18)
node _T_2704 = eq(_T_2703, UInt<1>(0h0))
when _T_2704 :
wire _WIRE_200 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_201 : UInt<42>
connect _WIRE_201, sectored_entries[0][6].data[0]
node _T_2705 = bits(_WIRE_201, 0, 0)
connect _WIRE_200.fragmented_superpage, _T_2705
node _T_2706 = bits(_WIRE_201, 1, 1)
connect _WIRE_200.c, _T_2706
node _T_2707 = bits(_WIRE_201, 2, 2)
connect _WIRE_200.eff, _T_2707
node _T_2708 = bits(_WIRE_201, 3, 3)
connect _WIRE_200.paa, _T_2708
node _T_2709 = bits(_WIRE_201, 4, 4)
connect _WIRE_200.pal, _T_2709
node _T_2710 = bits(_WIRE_201, 5, 5)
connect _WIRE_200.ppp, _T_2710
node _T_2711 = bits(_WIRE_201, 6, 6)
connect _WIRE_200.pr, _T_2711
node _T_2712 = bits(_WIRE_201, 7, 7)
connect _WIRE_200.px, _T_2712
node _T_2713 = bits(_WIRE_201, 8, 8)
connect _WIRE_200.pw, _T_2713
node _T_2714 = bits(_WIRE_201, 9, 9)
connect _WIRE_200.hr, _T_2714
node _T_2715 = bits(_WIRE_201, 10, 10)
connect _WIRE_200.hx, _T_2715
node _T_2716 = bits(_WIRE_201, 11, 11)
connect _WIRE_200.hw, _T_2716
node _T_2717 = bits(_WIRE_201, 12, 12)
connect _WIRE_200.sr, _T_2717
node _T_2718 = bits(_WIRE_201, 13, 13)
connect _WIRE_200.sx, _T_2718
node _T_2719 = bits(_WIRE_201, 14, 14)
connect _WIRE_200.sw, _T_2719
node _T_2720 = bits(_WIRE_201, 15, 15)
connect _WIRE_200.gf, _T_2720
node _T_2721 = bits(_WIRE_201, 16, 16)
connect _WIRE_200.pf, _T_2721
node _T_2722 = bits(_WIRE_201, 17, 17)
connect _WIRE_200.ae_stage2, _T_2722
node _T_2723 = bits(_WIRE_201, 18, 18)
connect _WIRE_200.ae_final, _T_2723
node _T_2724 = bits(_WIRE_201, 19, 19)
connect _WIRE_200.ae_ptw, _T_2724
node _T_2725 = bits(_WIRE_201, 20, 20)
connect _WIRE_200.g, _T_2725
node _T_2726 = bits(_WIRE_201, 21, 21)
connect _WIRE_200.u, _T_2726
node _T_2727 = bits(_WIRE_201, 41, 22)
connect _WIRE_200.ppn, _T_2727
wire _WIRE_202 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_203 : UInt<42>
connect _WIRE_203, sectored_entries[0][6].data[1]
node _T_2728 = bits(_WIRE_203, 0, 0)
connect _WIRE_202.fragmented_superpage, _T_2728
node _T_2729 = bits(_WIRE_203, 1, 1)
connect _WIRE_202.c, _T_2729
node _T_2730 = bits(_WIRE_203, 2, 2)
connect _WIRE_202.eff, _T_2730
node _T_2731 = bits(_WIRE_203, 3, 3)
connect _WIRE_202.paa, _T_2731
node _T_2732 = bits(_WIRE_203, 4, 4)
connect _WIRE_202.pal, _T_2732
node _T_2733 = bits(_WIRE_203, 5, 5)
connect _WIRE_202.ppp, _T_2733
node _T_2734 = bits(_WIRE_203, 6, 6)
connect _WIRE_202.pr, _T_2734
node _T_2735 = bits(_WIRE_203, 7, 7)
connect _WIRE_202.px, _T_2735
node _T_2736 = bits(_WIRE_203, 8, 8)
connect _WIRE_202.pw, _T_2736
node _T_2737 = bits(_WIRE_203, 9, 9)
connect _WIRE_202.hr, _T_2737
node _T_2738 = bits(_WIRE_203, 10, 10)
connect _WIRE_202.hx, _T_2738
node _T_2739 = bits(_WIRE_203, 11, 11)
connect _WIRE_202.hw, _T_2739
node _T_2740 = bits(_WIRE_203, 12, 12)
connect _WIRE_202.sr, _T_2740
node _T_2741 = bits(_WIRE_203, 13, 13)
connect _WIRE_202.sx, _T_2741
node _T_2742 = bits(_WIRE_203, 14, 14)
connect _WIRE_202.sw, _T_2742
node _T_2743 = bits(_WIRE_203, 15, 15)
connect _WIRE_202.gf, _T_2743
node _T_2744 = bits(_WIRE_203, 16, 16)
connect _WIRE_202.pf, _T_2744
node _T_2745 = bits(_WIRE_203, 17, 17)
connect _WIRE_202.ae_stage2, _T_2745
node _T_2746 = bits(_WIRE_203, 18, 18)
connect _WIRE_202.ae_final, _T_2746
node _T_2747 = bits(_WIRE_203, 19, 19)
connect _WIRE_202.ae_ptw, _T_2747
node _T_2748 = bits(_WIRE_203, 20, 20)
connect _WIRE_202.g, _T_2748
node _T_2749 = bits(_WIRE_203, 21, 21)
connect _WIRE_202.u, _T_2749
node _T_2750 = bits(_WIRE_203, 41, 22)
connect _WIRE_202.ppn, _T_2750
wire _WIRE_204 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_205 : UInt<42>
connect _WIRE_205, sectored_entries[0][6].data[2]
node _T_2751 = bits(_WIRE_205, 0, 0)
connect _WIRE_204.fragmented_superpage, _T_2751
node _T_2752 = bits(_WIRE_205, 1, 1)
connect _WIRE_204.c, _T_2752
node _T_2753 = bits(_WIRE_205, 2, 2)
connect _WIRE_204.eff, _T_2753
node _T_2754 = bits(_WIRE_205, 3, 3)
connect _WIRE_204.paa, _T_2754
node _T_2755 = bits(_WIRE_205, 4, 4)
connect _WIRE_204.pal, _T_2755
node _T_2756 = bits(_WIRE_205, 5, 5)
connect _WIRE_204.ppp, _T_2756
node _T_2757 = bits(_WIRE_205, 6, 6)
connect _WIRE_204.pr, _T_2757
node _T_2758 = bits(_WIRE_205, 7, 7)
connect _WIRE_204.px, _T_2758
node _T_2759 = bits(_WIRE_205, 8, 8)
connect _WIRE_204.pw, _T_2759
node _T_2760 = bits(_WIRE_205, 9, 9)
connect _WIRE_204.hr, _T_2760
node _T_2761 = bits(_WIRE_205, 10, 10)
connect _WIRE_204.hx, _T_2761
node _T_2762 = bits(_WIRE_205, 11, 11)
connect _WIRE_204.hw, _T_2762
node _T_2763 = bits(_WIRE_205, 12, 12)
connect _WIRE_204.sr, _T_2763
node _T_2764 = bits(_WIRE_205, 13, 13)
connect _WIRE_204.sx, _T_2764
node _T_2765 = bits(_WIRE_205, 14, 14)
connect _WIRE_204.sw, _T_2765
node _T_2766 = bits(_WIRE_205, 15, 15)
connect _WIRE_204.gf, _T_2766
node _T_2767 = bits(_WIRE_205, 16, 16)
connect _WIRE_204.pf, _T_2767
node _T_2768 = bits(_WIRE_205, 17, 17)
connect _WIRE_204.ae_stage2, _T_2768
node _T_2769 = bits(_WIRE_205, 18, 18)
connect _WIRE_204.ae_final, _T_2769
node _T_2770 = bits(_WIRE_205, 19, 19)
connect _WIRE_204.ae_ptw, _T_2770
node _T_2771 = bits(_WIRE_205, 20, 20)
connect _WIRE_204.g, _T_2771
node _T_2772 = bits(_WIRE_205, 21, 21)
connect _WIRE_204.u, _T_2772
node _T_2773 = bits(_WIRE_205, 41, 22)
connect _WIRE_204.ppn, _T_2773
wire _WIRE_206 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_207 : UInt<42>
connect _WIRE_207, sectored_entries[0][6].data[3]
node _T_2774 = bits(_WIRE_207, 0, 0)
connect _WIRE_206.fragmented_superpage, _T_2774
node _T_2775 = bits(_WIRE_207, 1, 1)
connect _WIRE_206.c, _T_2775
node _T_2776 = bits(_WIRE_207, 2, 2)
connect _WIRE_206.eff, _T_2776
node _T_2777 = bits(_WIRE_207, 3, 3)
connect _WIRE_206.paa, _T_2777
node _T_2778 = bits(_WIRE_207, 4, 4)
connect _WIRE_206.pal, _T_2778
node _T_2779 = bits(_WIRE_207, 5, 5)
connect _WIRE_206.ppp, _T_2779
node _T_2780 = bits(_WIRE_207, 6, 6)
connect _WIRE_206.pr, _T_2780
node _T_2781 = bits(_WIRE_207, 7, 7)
connect _WIRE_206.px, _T_2781
node _T_2782 = bits(_WIRE_207, 8, 8)
connect _WIRE_206.pw, _T_2782
node _T_2783 = bits(_WIRE_207, 9, 9)
connect _WIRE_206.hr, _T_2783
node _T_2784 = bits(_WIRE_207, 10, 10)
connect _WIRE_206.hx, _T_2784
node _T_2785 = bits(_WIRE_207, 11, 11)
connect _WIRE_206.hw, _T_2785
node _T_2786 = bits(_WIRE_207, 12, 12)
connect _WIRE_206.sr, _T_2786
node _T_2787 = bits(_WIRE_207, 13, 13)
connect _WIRE_206.sx, _T_2787
node _T_2788 = bits(_WIRE_207, 14, 14)
connect _WIRE_206.sw, _T_2788
node _T_2789 = bits(_WIRE_207, 15, 15)
connect _WIRE_206.gf, _T_2789
node _T_2790 = bits(_WIRE_207, 16, 16)
connect _WIRE_206.pf, _T_2790
node _T_2791 = bits(_WIRE_207, 17, 17)
connect _WIRE_206.ae_stage2, _T_2791
node _T_2792 = bits(_WIRE_207, 18, 18)
connect _WIRE_206.ae_final, _T_2792
node _T_2793 = bits(_WIRE_207, 19, 19)
connect _WIRE_206.ae_ptw, _T_2793
node _T_2794 = bits(_WIRE_207, 20, 20)
connect _WIRE_206.g, _T_2794
node _T_2795 = bits(_WIRE_207, 21, 21)
connect _WIRE_206.u, _T_2795
node _T_2796 = bits(_WIRE_207, 41, 22)
connect _WIRE_206.ppn, _T_2796
node _T_2797 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2798 = and(_T_2797, _WIRE_200.fragmented_superpage)
when _T_2798 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_2799 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2800 = and(_T_2799, _WIRE_202.fragmented_superpage)
when _T_2800 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_2801 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2802 = and(_T_2801, _WIRE_204.fragmented_superpage)
when _T_2802 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_2803 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2804 = and(_T_2803, _WIRE_206.fragmented_superpage)
when _T_2804 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
else :
node _T_2805 = eq(hg_6, UInt<1>(0h0))
node _T_2806 = and(_T_2805, io.sfence.bits.rs2)
when _T_2806 :
wire _WIRE_208 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_209 : UInt<42>
connect _WIRE_209, sectored_entries[0][6].data[0]
node _T_2807 = bits(_WIRE_209, 0, 0)
connect _WIRE_208.fragmented_superpage, _T_2807
node _T_2808 = bits(_WIRE_209, 1, 1)
connect _WIRE_208.c, _T_2808
node _T_2809 = bits(_WIRE_209, 2, 2)
connect _WIRE_208.eff, _T_2809
node _T_2810 = bits(_WIRE_209, 3, 3)
connect _WIRE_208.paa, _T_2810
node _T_2811 = bits(_WIRE_209, 4, 4)
connect _WIRE_208.pal, _T_2811
node _T_2812 = bits(_WIRE_209, 5, 5)
connect _WIRE_208.ppp, _T_2812
node _T_2813 = bits(_WIRE_209, 6, 6)
connect _WIRE_208.pr, _T_2813
node _T_2814 = bits(_WIRE_209, 7, 7)
connect _WIRE_208.px, _T_2814
node _T_2815 = bits(_WIRE_209, 8, 8)
connect _WIRE_208.pw, _T_2815
node _T_2816 = bits(_WIRE_209, 9, 9)
connect _WIRE_208.hr, _T_2816
node _T_2817 = bits(_WIRE_209, 10, 10)
connect _WIRE_208.hx, _T_2817
node _T_2818 = bits(_WIRE_209, 11, 11)
connect _WIRE_208.hw, _T_2818
node _T_2819 = bits(_WIRE_209, 12, 12)
connect _WIRE_208.sr, _T_2819
node _T_2820 = bits(_WIRE_209, 13, 13)
connect _WIRE_208.sx, _T_2820
node _T_2821 = bits(_WIRE_209, 14, 14)
connect _WIRE_208.sw, _T_2821
node _T_2822 = bits(_WIRE_209, 15, 15)
connect _WIRE_208.gf, _T_2822
node _T_2823 = bits(_WIRE_209, 16, 16)
connect _WIRE_208.pf, _T_2823
node _T_2824 = bits(_WIRE_209, 17, 17)
connect _WIRE_208.ae_stage2, _T_2824
node _T_2825 = bits(_WIRE_209, 18, 18)
connect _WIRE_208.ae_final, _T_2825
node _T_2826 = bits(_WIRE_209, 19, 19)
connect _WIRE_208.ae_ptw, _T_2826
node _T_2827 = bits(_WIRE_209, 20, 20)
connect _WIRE_208.g, _T_2827
node _T_2828 = bits(_WIRE_209, 21, 21)
connect _WIRE_208.u, _T_2828
node _T_2829 = bits(_WIRE_209, 41, 22)
connect _WIRE_208.ppn, _T_2829
wire _WIRE_210 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_211 : UInt<42>
connect _WIRE_211, sectored_entries[0][6].data[1]
node _T_2830 = bits(_WIRE_211, 0, 0)
connect _WIRE_210.fragmented_superpage, _T_2830
node _T_2831 = bits(_WIRE_211, 1, 1)
connect _WIRE_210.c, _T_2831
node _T_2832 = bits(_WIRE_211, 2, 2)
connect _WIRE_210.eff, _T_2832
node _T_2833 = bits(_WIRE_211, 3, 3)
connect _WIRE_210.paa, _T_2833
node _T_2834 = bits(_WIRE_211, 4, 4)
connect _WIRE_210.pal, _T_2834
node _T_2835 = bits(_WIRE_211, 5, 5)
connect _WIRE_210.ppp, _T_2835
node _T_2836 = bits(_WIRE_211, 6, 6)
connect _WIRE_210.pr, _T_2836
node _T_2837 = bits(_WIRE_211, 7, 7)
connect _WIRE_210.px, _T_2837
node _T_2838 = bits(_WIRE_211, 8, 8)
connect _WIRE_210.pw, _T_2838
node _T_2839 = bits(_WIRE_211, 9, 9)
connect _WIRE_210.hr, _T_2839
node _T_2840 = bits(_WIRE_211, 10, 10)
connect _WIRE_210.hx, _T_2840
node _T_2841 = bits(_WIRE_211, 11, 11)
connect _WIRE_210.hw, _T_2841
node _T_2842 = bits(_WIRE_211, 12, 12)
connect _WIRE_210.sr, _T_2842
node _T_2843 = bits(_WIRE_211, 13, 13)
connect _WIRE_210.sx, _T_2843
node _T_2844 = bits(_WIRE_211, 14, 14)
connect _WIRE_210.sw, _T_2844
node _T_2845 = bits(_WIRE_211, 15, 15)
connect _WIRE_210.gf, _T_2845
node _T_2846 = bits(_WIRE_211, 16, 16)
connect _WIRE_210.pf, _T_2846
node _T_2847 = bits(_WIRE_211, 17, 17)
connect _WIRE_210.ae_stage2, _T_2847
node _T_2848 = bits(_WIRE_211, 18, 18)
connect _WIRE_210.ae_final, _T_2848
node _T_2849 = bits(_WIRE_211, 19, 19)
connect _WIRE_210.ae_ptw, _T_2849
node _T_2850 = bits(_WIRE_211, 20, 20)
connect _WIRE_210.g, _T_2850
node _T_2851 = bits(_WIRE_211, 21, 21)
connect _WIRE_210.u, _T_2851
node _T_2852 = bits(_WIRE_211, 41, 22)
connect _WIRE_210.ppn, _T_2852
wire _WIRE_212 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_213 : UInt<42>
connect _WIRE_213, sectored_entries[0][6].data[2]
node _T_2853 = bits(_WIRE_213, 0, 0)
connect _WIRE_212.fragmented_superpage, _T_2853
node _T_2854 = bits(_WIRE_213, 1, 1)
connect _WIRE_212.c, _T_2854
node _T_2855 = bits(_WIRE_213, 2, 2)
connect _WIRE_212.eff, _T_2855
node _T_2856 = bits(_WIRE_213, 3, 3)
connect _WIRE_212.paa, _T_2856
node _T_2857 = bits(_WIRE_213, 4, 4)
connect _WIRE_212.pal, _T_2857
node _T_2858 = bits(_WIRE_213, 5, 5)
connect _WIRE_212.ppp, _T_2858
node _T_2859 = bits(_WIRE_213, 6, 6)
connect _WIRE_212.pr, _T_2859
node _T_2860 = bits(_WIRE_213, 7, 7)
connect _WIRE_212.px, _T_2860
node _T_2861 = bits(_WIRE_213, 8, 8)
connect _WIRE_212.pw, _T_2861
node _T_2862 = bits(_WIRE_213, 9, 9)
connect _WIRE_212.hr, _T_2862
node _T_2863 = bits(_WIRE_213, 10, 10)
connect _WIRE_212.hx, _T_2863
node _T_2864 = bits(_WIRE_213, 11, 11)
connect _WIRE_212.hw, _T_2864
node _T_2865 = bits(_WIRE_213, 12, 12)
connect _WIRE_212.sr, _T_2865
node _T_2866 = bits(_WIRE_213, 13, 13)
connect _WIRE_212.sx, _T_2866
node _T_2867 = bits(_WIRE_213, 14, 14)
connect _WIRE_212.sw, _T_2867
node _T_2868 = bits(_WIRE_213, 15, 15)
connect _WIRE_212.gf, _T_2868
node _T_2869 = bits(_WIRE_213, 16, 16)
connect _WIRE_212.pf, _T_2869
node _T_2870 = bits(_WIRE_213, 17, 17)
connect _WIRE_212.ae_stage2, _T_2870
node _T_2871 = bits(_WIRE_213, 18, 18)
connect _WIRE_212.ae_final, _T_2871
node _T_2872 = bits(_WIRE_213, 19, 19)
connect _WIRE_212.ae_ptw, _T_2872
node _T_2873 = bits(_WIRE_213, 20, 20)
connect _WIRE_212.g, _T_2873
node _T_2874 = bits(_WIRE_213, 21, 21)
connect _WIRE_212.u, _T_2874
node _T_2875 = bits(_WIRE_213, 41, 22)
connect _WIRE_212.ppn, _T_2875
wire _WIRE_214 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_215 : UInt<42>
connect _WIRE_215, sectored_entries[0][6].data[3]
node _T_2876 = bits(_WIRE_215, 0, 0)
connect _WIRE_214.fragmented_superpage, _T_2876
node _T_2877 = bits(_WIRE_215, 1, 1)
connect _WIRE_214.c, _T_2877
node _T_2878 = bits(_WIRE_215, 2, 2)
connect _WIRE_214.eff, _T_2878
node _T_2879 = bits(_WIRE_215, 3, 3)
connect _WIRE_214.paa, _T_2879
node _T_2880 = bits(_WIRE_215, 4, 4)
connect _WIRE_214.pal, _T_2880
node _T_2881 = bits(_WIRE_215, 5, 5)
connect _WIRE_214.ppp, _T_2881
node _T_2882 = bits(_WIRE_215, 6, 6)
connect _WIRE_214.pr, _T_2882
node _T_2883 = bits(_WIRE_215, 7, 7)
connect _WIRE_214.px, _T_2883
node _T_2884 = bits(_WIRE_215, 8, 8)
connect _WIRE_214.pw, _T_2884
node _T_2885 = bits(_WIRE_215, 9, 9)
connect _WIRE_214.hr, _T_2885
node _T_2886 = bits(_WIRE_215, 10, 10)
connect _WIRE_214.hx, _T_2886
node _T_2887 = bits(_WIRE_215, 11, 11)
connect _WIRE_214.hw, _T_2887
node _T_2888 = bits(_WIRE_215, 12, 12)
connect _WIRE_214.sr, _T_2888
node _T_2889 = bits(_WIRE_215, 13, 13)
connect _WIRE_214.sx, _T_2889
node _T_2890 = bits(_WIRE_215, 14, 14)
connect _WIRE_214.sw, _T_2890
node _T_2891 = bits(_WIRE_215, 15, 15)
connect _WIRE_214.gf, _T_2891
node _T_2892 = bits(_WIRE_215, 16, 16)
connect _WIRE_214.pf, _T_2892
node _T_2893 = bits(_WIRE_215, 17, 17)
connect _WIRE_214.ae_stage2, _T_2893
node _T_2894 = bits(_WIRE_215, 18, 18)
connect _WIRE_214.ae_final, _T_2894
node _T_2895 = bits(_WIRE_215, 19, 19)
connect _WIRE_214.ae_ptw, _T_2895
node _T_2896 = bits(_WIRE_215, 20, 20)
connect _WIRE_214.g, _T_2896
node _T_2897 = bits(_WIRE_215, 21, 21)
connect _WIRE_214.u, _T_2897
node _T_2898 = bits(_WIRE_215, 41, 22)
connect _WIRE_214.ppn, _T_2898
node _T_2899 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2900 = eq(_WIRE_208.g, UInt<1>(0h0))
node _T_2901 = and(_T_2899, _T_2900)
when _T_2901 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_2902 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2903 = eq(_WIRE_210.g, UInt<1>(0h0))
node _T_2904 = and(_T_2902, _T_2903)
when _T_2904 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_2905 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2906 = eq(_WIRE_212.g, UInt<1>(0h0))
node _T_2907 = and(_T_2905, _T_2906)
when _T_2907 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_2908 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2909 = eq(_WIRE_214.g, UInt<1>(0h0))
node _T_2910 = and(_T_2908, _T_2909)
when _T_2910 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
else :
node _T_2911 = or(hv_6, hg_6)
wire _WIRE_216 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_217 : UInt<42>
connect _WIRE_217, sectored_entries[0][6].data[0]
node _T_2912 = bits(_WIRE_217, 0, 0)
connect _WIRE_216.fragmented_superpage, _T_2912
node _T_2913 = bits(_WIRE_217, 1, 1)
connect _WIRE_216.c, _T_2913
node _T_2914 = bits(_WIRE_217, 2, 2)
connect _WIRE_216.eff, _T_2914
node _T_2915 = bits(_WIRE_217, 3, 3)
connect _WIRE_216.paa, _T_2915
node _T_2916 = bits(_WIRE_217, 4, 4)
connect _WIRE_216.pal, _T_2916
node _T_2917 = bits(_WIRE_217, 5, 5)
connect _WIRE_216.ppp, _T_2917
node _T_2918 = bits(_WIRE_217, 6, 6)
connect _WIRE_216.pr, _T_2918
node _T_2919 = bits(_WIRE_217, 7, 7)
connect _WIRE_216.px, _T_2919
node _T_2920 = bits(_WIRE_217, 8, 8)
connect _WIRE_216.pw, _T_2920
node _T_2921 = bits(_WIRE_217, 9, 9)
connect _WIRE_216.hr, _T_2921
node _T_2922 = bits(_WIRE_217, 10, 10)
connect _WIRE_216.hx, _T_2922
node _T_2923 = bits(_WIRE_217, 11, 11)
connect _WIRE_216.hw, _T_2923
node _T_2924 = bits(_WIRE_217, 12, 12)
connect _WIRE_216.sr, _T_2924
node _T_2925 = bits(_WIRE_217, 13, 13)
connect _WIRE_216.sx, _T_2925
node _T_2926 = bits(_WIRE_217, 14, 14)
connect _WIRE_216.sw, _T_2926
node _T_2927 = bits(_WIRE_217, 15, 15)
connect _WIRE_216.gf, _T_2927
node _T_2928 = bits(_WIRE_217, 16, 16)
connect _WIRE_216.pf, _T_2928
node _T_2929 = bits(_WIRE_217, 17, 17)
connect _WIRE_216.ae_stage2, _T_2929
node _T_2930 = bits(_WIRE_217, 18, 18)
connect _WIRE_216.ae_final, _T_2930
node _T_2931 = bits(_WIRE_217, 19, 19)
connect _WIRE_216.ae_ptw, _T_2931
node _T_2932 = bits(_WIRE_217, 20, 20)
connect _WIRE_216.g, _T_2932
node _T_2933 = bits(_WIRE_217, 21, 21)
connect _WIRE_216.u, _T_2933
node _T_2934 = bits(_WIRE_217, 41, 22)
connect _WIRE_216.ppn, _T_2934
wire _WIRE_218 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_219 : UInt<42>
connect _WIRE_219, sectored_entries[0][6].data[1]
node _T_2935 = bits(_WIRE_219, 0, 0)
connect _WIRE_218.fragmented_superpage, _T_2935
node _T_2936 = bits(_WIRE_219, 1, 1)
connect _WIRE_218.c, _T_2936
node _T_2937 = bits(_WIRE_219, 2, 2)
connect _WIRE_218.eff, _T_2937
node _T_2938 = bits(_WIRE_219, 3, 3)
connect _WIRE_218.paa, _T_2938
node _T_2939 = bits(_WIRE_219, 4, 4)
connect _WIRE_218.pal, _T_2939
node _T_2940 = bits(_WIRE_219, 5, 5)
connect _WIRE_218.ppp, _T_2940
node _T_2941 = bits(_WIRE_219, 6, 6)
connect _WIRE_218.pr, _T_2941
node _T_2942 = bits(_WIRE_219, 7, 7)
connect _WIRE_218.px, _T_2942
node _T_2943 = bits(_WIRE_219, 8, 8)
connect _WIRE_218.pw, _T_2943
node _T_2944 = bits(_WIRE_219, 9, 9)
connect _WIRE_218.hr, _T_2944
node _T_2945 = bits(_WIRE_219, 10, 10)
connect _WIRE_218.hx, _T_2945
node _T_2946 = bits(_WIRE_219, 11, 11)
connect _WIRE_218.hw, _T_2946
node _T_2947 = bits(_WIRE_219, 12, 12)
connect _WIRE_218.sr, _T_2947
node _T_2948 = bits(_WIRE_219, 13, 13)
connect _WIRE_218.sx, _T_2948
node _T_2949 = bits(_WIRE_219, 14, 14)
connect _WIRE_218.sw, _T_2949
node _T_2950 = bits(_WIRE_219, 15, 15)
connect _WIRE_218.gf, _T_2950
node _T_2951 = bits(_WIRE_219, 16, 16)
connect _WIRE_218.pf, _T_2951
node _T_2952 = bits(_WIRE_219, 17, 17)
connect _WIRE_218.ae_stage2, _T_2952
node _T_2953 = bits(_WIRE_219, 18, 18)
connect _WIRE_218.ae_final, _T_2953
node _T_2954 = bits(_WIRE_219, 19, 19)
connect _WIRE_218.ae_ptw, _T_2954
node _T_2955 = bits(_WIRE_219, 20, 20)
connect _WIRE_218.g, _T_2955
node _T_2956 = bits(_WIRE_219, 21, 21)
connect _WIRE_218.u, _T_2956
node _T_2957 = bits(_WIRE_219, 41, 22)
connect _WIRE_218.ppn, _T_2957
wire _WIRE_220 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_221 : UInt<42>
connect _WIRE_221, sectored_entries[0][6].data[2]
node _T_2958 = bits(_WIRE_221, 0, 0)
connect _WIRE_220.fragmented_superpage, _T_2958
node _T_2959 = bits(_WIRE_221, 1, 1)
connect _WIRE_220.c, _T_2959
node _T_2960 = bits(_WIRE_221, 2, 2)
connect _WIRE_220.eff, _T_2960
node _T_2961 = bits(_WIRE_221, 3, 3)
connect _WIRE_220.paa, _T_2961
node _T_2962 = bits(_WIRE_221, 4, 4)
connect _WIRE_220.pal, _T_2962
node _T_2963 = bits(_WIRE_221, 5, 5)
connect _WIRE_220.ppp, _T_2963
node _T_2964 = bits(_WIRE_221, 6, 6)
connect _WIRE_220.pr, _T_2964
node _T_2965 = bits(_WIRE_221, 7, 7)
connect _WIRE_220.px, _T_2965
node _T_2966 = bits(_WIRE_221, 8, 8)
connect _WIRE_220.pw, _T_2966
node _T_2967 = bits(_WIRE_221, 9, 9)
connect _WIRE_220.hr, _T_2967
node _T_2968 = bits(_WIRE_221, 10, 10)
connect _WIRE_220.hx, _T_2968
node _T_2969 = bits(_WIRE_221, 11, 11)
connect _WIRE_220.hw, _T_2969
node _T_2970 = bits(_WIRE_221, 12, 12)
connect _WIRE_220.sr, _T_2970
node _T_2971 = bits(_WIRE_221, 13, 13)
connect _WIRE_220.sx, _T_2971
node _T_2972 = bits(_WIRE_221, 14, 14)
connect _WIRE_220.sw, _T_2972
node _T_2973 = bits(_WIRE_221, 15, 15)
connect _WIRE_220.gf, _T_2973
node _T_2974 = bits(_WIRE_221, 16, 16)
connect _WIRE_220.pf, _T_2974
node _T_2975 = bits(_WIRE_221, 17, 17)
connect _WIRE_220.ae_stage2, _T_2975
node _T_2976 = bits(_WIRE_221, 18, 18)
connect _WIRE_220.ae_final, _T_2976
node _T_2977 = bits(_WIRE_221, 19, 19)
connect _WIRE_220.ae_ptw, _T_2977
node _T_2978 = bits(_WIRE_221, 20, 20)
connect _WIRE_220.g, _T_2978
node _T_2979 = bits(_WIRE_221, 21, 21)
connect _WIRE_220.u, _T_2979
node _T_2980 = bits(_WIRE_221, 41, 22)
connect _WIRE_220.ppn, _T_2980
wire _WIRE_222 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_223 : UInt<42>
connect _WIRE_223, sectored_entries[0][6].data[3]
node _T_2981 = bits(_WIRE_223, 0, 0)
connect _WIRE_222.fragmented_superpage, _T_2981
node _T_2982 = bits(_WIRE_223, 1, 1)
connect _WIRE_222.c, _T_2982
node _T_2983 = bits(_WIRE_223, 2, 2)
connect _WIRE_222.eff, _T_2983
node _T_2984 = bits(_WIRE_223, 3, 3)
connect _WIRE_222.paa, _T_2984
node _T_2985 = bits(_WIRE_223, 4, 4)
connect _WIRE_222.pal, _T_2985
node _T_2986 = bits(_WIRE_223, 5, 5)
connect _WIRE_222.ppp, _T_2986
node _T_2987 = bits(_WIRE_223, 6, 6)
connect _WIRE_222.pr, _T_2987
node _T_2988 = bits(_WIRE_223, 7, 7)
connect _WIRE_222.px, _T_2988
node _T_2989 = bits(_WIRE_223, 8, 8)
connect _WIRE_222.pw, _T_2989
node _T_2990 = bits(_WIRE_223, 9, 9)
connect _WIRE_222.hr, _T_2990
node _T_2991 = bits(_WIRE_223, 10, 10)
connect _WIRE_222.hx, _T_2991
node _T_2992 = bits(_WIRE_223, 11, 11)
connect _WIRE_222.hw, _T_2992
node _T_2993 = bits(_WIRE_223, 12, 12)
connect _WIRE_222.sr, _T_2993
node _T_2994 = bits(_WIRE_223, 13, 13)
connect _WIRE_222.sx, _T_2994
node _T_2995 = bits(_WIRE_223, 14, 14)
connect _WIRE_222.sw, _T_2995
node _T_2996 = bits(_WIRE_223, 15, 15)
connect _WIRE_222.gf, _T_2996
node _T_2997 = bits(_WIRE_223, 16, 16)
connect _WIRE_222.pf, _T_2997
node _T_2998 = bits(_WIRE_223, 17, 17)
connect _WIRE_222.ae_stage2, _T_2998
node _T_2999 = bits(_WIRE_223, 18, 18)
connect _WIRE_222.ae_final, _T_2999
node _T_3000 = bits(_WIRE_223, 19, 19)
connect _WIRE_222.ae_ptw, _T_3000
node _T_3001 = bits(_WIRE_223, 20, 20)
connect _WIRE_222.g, _T_3001
node _T_3002 = bits(_WIRE_223, 21, 21)
connect _WIRE_222.u, _T_3002
node _T_3003 = bits(_WIRE_223, 41, 22)
connect _WIRE_222.ppn, _T_3003
node _T_3004 = eq(sectored_entries[0][6].tag_v, _T_2911)
when _T_3004 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_3005 = eq(sectored_entries[0][6].tag_v, _T_2911)
when _T_3005 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_3006 = eq(sectored_entries[0][6].tag_v, _T_2911)
when _T_3006 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_3007 = eq(sectored_entries[0][6].tag_v, _T_2911)
when _T_3007 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
node hv_7 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_7 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3008 = eq(hg_7, UInt<1>(0h0))
node _T_3009 = and(_T_3008, io.sfence.bits.rs1)
when _T_3009 :
node _T_3010 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _T_3011 = shr(_T_3010, 2)
node _T_3012 = eq(_T_3011, UInt<1>(0h0))
node _T_3013 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3014 = and(_T_3012, _T_3013)
when _T_3014 :
wire _WIRE_224 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_225 : UInt<42>
connect _WIRE_225, sectored_entries[0][7].data[0]
node _T_3015 = bits(_WIRE_225, 0, 0)
connect _WIRE_224.fragmented_superpage, _T_3015
node _T_3016 = bits(_WIRE_225, 1, 1)
connect _WIRE_224.c, _T_3016
node _T_3017 = bits(_WIRE_225, 2, 2)
connect _WIRE_224.eff, _T_3017
node _T_3018 = bits(_WIRE_225, 3, 3)
connect _WIRE_224.paa, _T_3018
node _T_3019 = bits(_WIRE_225, 4, 4)
connect _WIRE_224.pal, _T_3019
node _T_3020 = bits(_WIRE_225, 5, 5)
connect _WIRE_224.ppp, _T_3020
node _T_3021 = bits(_WIRE_225, 6, 6)
connect _WIRE_224.pr, _T_3021
node _T_3022 = bits(_WIRE_225, 7, 7)
connect _WIRE_224.px, _T_3022
node _T_3023 = bits(_WIRE_225, 8, 8)
connect _WIRE_224.pw, _T_3023
node _T_3024 = bits(_WIRE_225, 9, 9)
connect _WIRE_224.hr, _T_3024
node _T_3025 = bits(_WIRE_225, 10, 10)
connect _WIRE_224.hx, _T_3025
node _T_3026 = bits(_WIRE_225, 11, 11)
connect _WIRE_224.hw, _T_3026
node _T_3027 = bits(_WIRE_225, 12, 12)
connect _WIRE_224.sr, _T_3027
node _T_3028 = bits(_WIRE_225, 13, 13)
connect _WIRE_224.sx, _T_3028
node _T_3029 = bits(_WIRE_225, 14, 14)
connect _WIRE_224.sw, _T_3029
node _T_3030 = bits(_WIRE_225, 15, 15)
connect _WIRE_224.gf, _T_3030
node _T_3031 = bits(_WIRE_225, 16, 16)
connect _WIRE_224.pf, _T_3031
node _T_3032 = bits(_WIRE_225, 17, 17)
connect _WIRE_224.ae_stage2, _T_3032
node _T_3033 = bits(_WIRE_225, 18, 18)
connect _WIRE_224.ae_final, _T_3033
node _T_3034 = bits(_WIRE_225, 19, 19)
connect _WIRE_224.ae_ptw, _T_3034
node _T_3035 = bits(_WIRE_225, 20, 20)
connect _WIRE_224.g, _T_3035
node _T_3036 = bits(_WIRE_225, 21, 21)
connect _WIRE_224.u, _T_3036
node _T_3037 = bits(_WIRE_225, 41, 22)
connect _WIRE_224.ppn, _T_3037
wire _WIRE_226 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_227 : UInt<42>
connect _WIRE_227, sectored_entries[0][7].data[1]
node _T_3038 = bits(_WIRE_227, 0, 0)
connect _WIRE_226.fragmented_superpage, _T_3038
node _T_3039 = bits(_WIRE_227, 1, 1)
connect _WIRE_226.c, _T_3039
node _T_3040 = bits(_WIRE_227, 2, 2)
connect _WIRE_226.eff, _T_3040
node _T_3041 = bits(_WIRE_227, 3, 3)
connect _WIRE_226.paa, _T_3041
node _T_3042 = bits(_WIRE_227, 4, 4)
connect _WIRE_226.pal, _T_3042
node _T_3043 = bits(_WIRE_227, 5, 5)
connect _WIRE_226.ppp, _T_3043
node _T_3044 = bits(_WIRE_227, 6, 6)
connect _WIRE_226.pr, _T_3044
node _T_3045 = bits(_WIRE_227, 7, 7)
connect _WIRE_226.px, _T_3045
node _T_3046 = bits(_WIRE_227, 8, 8)
connect _WIRE_226.pw, _T_3046
node _T_3047 = bits(_WIRE_227, 9, 9)
connect _WIRE_226.hr, _T_3047
node _T_3048 = bits(_WIRE_227, 10, 10)
connect _WIRE_226.hx, _T_3048
node _T_3049 = bits(_WIRE_227, 11, 11)
connect _WIRE_226.hw, _T_3049
node _T_3050 = bits(_WIRE_227, 12, 12)
connect _WIRE_226.sr, _T_3050
node _T_3051 = bits(_WIRE_227, 13, 13)
connect _WIRE_226.sx, _T_3051
node _T_3052 = bits(_WIRE_227, 14, 14)
connect _WIRE_226.sw, _T_3052
node _T_3053 = bits(_WIRE_227, 15, 15)
connect _WIRE_226.gf, _T_3053
node _T_3054 = bits(_WIRE_227, 16, 16)
connect _WIRE_226.pf, _T_3054
node _T_3055 = bits(_WIRE_227, 17, 17)
connect _WIRE_226.ae_stage2, _T_3055
node _T_3056 = bits(_WIRE_227, 18, 18)
connect _WIRE_226.ae_final, _T_3056
node _T_3057 = bits(_WIRE_227, 19, 19)
connect _WIRE_226.ae_ptw, _T_3057
node _T_3058 = bits(_WIRE_227, 20, 20)
connect _WIRE_226.g, _T_3058
node _T_3059 = bits(_WIRE_227, 21, 21)
connect _WIRE_226.u, _T_3059
node _T_3060 = bits(_WIRE_227, 41, 22)
connect _WIRE_226.ppn, _T_3060
wire _WIRE_228 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_229 : UInt<42>
connect _WIRE_229, sectored_entries[0][7].data[2]
node _T_3061 = bits(_WIRE_229, 0, 0)
connect _WIRE_228.fragmented_superpage, _T_3061
node _T_3062 = bits(_WIRE_229, 1, 1)
connect _WIRE_228.c, _T_3062
node _T_3063 = bits(_WIRE_229, 2, 2)
connect _WIRE_228.eff, _T_3063
node _T_3064 = bits(_WIRE_229, 3, 3)
connect _WIRE_228.paa, _T_3064
node _T_3065 = bits(_WIRE_229, 4, 4)
connect _WIRE_228.pal, _T_3065
node _T_3066 = bits(_WIRE_229, 5, 5)
connect _WIRE_228.ppp, _T_3066
node _T_3067 = bits(_WIRE_229, 6, 6)
connect _WIRE_228.pr, _T_3067
node _T_3068 = bits(_WIRE_229, 7, 7)
connect _WIRE_228.px, _T_3068
node _T_3069 = bits(_WIRE_229, 8, 8)
connect _WIRE_228.pw, _T_3069
node _T_3070 = bits(_WIRE_229, 9, 9)
connect _WIRE_228.hr, _T_3070
node _T_3071 = bits(_WIRE_229, 10, 10)
connect _WIRE_228.hx, _T_3071
node _T_3072 = bits(_WIRE_229, 11, 11)
connect _WIRE_228.hw, _T_3072
node _T_3073 = bits(_WIRE_229, 12, 12)
connect _WIRE_228.sr, _T_3073
node _T_3074 = bits(_WIRE_229, 13, 13)
connect _WIRE_228.sx, _T_3074
node _T_3075 = bits(_WIRE_229, 14, 14)
connect _WIRE_228.sw, _T_3075
node _T_3076 = bits(_WIRE_229, 15, 15)
connect _WIRE_228.gf, _T_3076
node _T_3077 = bits(_WIRE_229, 16, 16)
connect _WIRE_228.pf, _T_3077
node _T_3078 = bits(_WIRE_229, 17, 17)
connect _WIRE_228.ae_stage2, _T_3078
node _T_3079 = bits(_WIRE_229, 18, 18)
connect _WIRE_228.ae_final, _T_3079
node _T_3080 = bits(_WIRE_229, 19, 19)
connect _WIRE_228.ae_ptw, _T_3080
node _T_3081 = bits(_WIRE_229, 20, 20)
connect _WIRE_228.g, _T_3081
node _T_3082 = bits(_WIRE_229, 21, 21)
connect _WIRE_228.u, _T_3082
node _T_3083 = bits(_WIRE_229, 41, 22)
connect _WIRE_228.ppn, _T_3083
wire _WIRE_230 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_231 : UInt<42>
connect _WIRE_231, sectored_entries[0][7].data[3]
node _T_3084 = bits(_WIRE_231, 0, 0)
connect _WIRE_230.fragmented_superpage, _T_3084
node _T_3085 = bits(_WIRE_231, 1, 1)
connect _WIRE_230.c, _T_3085
node _T_3086 = bits(_WIRE_231, 2, 2)
connect _WIRE_230.eff, _T_3086
node _T_3087 = bits(_WIRE_231, 3, 3)
connect _WIRE_230.paa, _T_3087
node _T_3088 = bits(_WIRE_231, 4, 4)
connect _WIRE_230.pal, _T_3088
node _T_3089 = bits(_WIRE_231, 5, 5)
connect _WIRE_230.ppp, _T_3089
node _T_3090 = bits(_WIRE_231, 6, 6)
connect _WIRE_230.pr, _T_3090
node _T_3091 = bits(_WIRE_231, 7, 7)
connect _WIRE_230.px, _T_3091
node _T_3092 = bits(_WIRE_231, 8, 8)
connect _WIRE_230.pw, _T_3092
node _T_3093 = bits(_WIRE_231, 9, 9)
connect _WIRE_230.hr, _T_3093
node _T_3094 = bits(_WIRE_231, 10, 10)
connect _WIRE_230.hx, _T_3094
node _T_3095 = bits(_WIRE_231, 11, 11)
connect _WIRE_230.hw, _T_3095
node _T_3096 = bits(_WIRE_231, 12, 12)
connect _WIRE_230.sr, _T_3096
node _T_3097 = bits(_WIRE_231, 13, 13)
connect _WIRE_230.sx, _T_3097
node _T_3098 = bits(_WIRE_231, 14, 14)
connect _WIRE_230.sw, _T_3098
node _T_3099 = bits(_WIRE_231, 15, 15)
connect _WIRE_230.gf, _T_3099
node _T_3100 = bits(_WIRE_231, 16, 16)
connect _WIRE_230.pf, _T_3100
node _T_3101 = bits(_WIRE_231, 17, 17)
connect _WIRE_230.ae_stage2, _T_3101
node _T_3102 = bits(_WIRE_231, 18, 18)
connect _WIRE_230.ae_final, _T_3102
node _T_3103 = bits(_WIRE_231, 19, 19)
connect _WIRE_230.ae_ptw, _T_3103
node _T_3104 = bits(_WIRE_231, 20, 20)
connect _WIRE_230.g, _T_3104
node _T_3105 = bits(_WIRE_231, 21, 21)
connect _WIRE_230.u, _T_3105
node _T_3106 = bits(_WIRE_231, 41, 22)
connect _WIRE_230.ppn, _T_3106
node _T_3107 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3108 = bits(vpn, 1, 0)
node _T_3109 = eq(UInt<1>(0h0), _T_3108)
node _T_3110 = and(_T_3107, _T_3109)
when _T_3110 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_3111 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3112 = bits(vpn, 1, 0)
node _T_3113 = eq(UInt<1>(0h1), _T_3112)
node _T_3114 = and(_T_3111, _T_3113)
when _T_3114 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_3115 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3116 = bits(vpn, 1, 0)
node _T_3117 = eq(UInt<2>(0h2), _T_3116)
node _T_3118 = and(_T_3115, _T_3117)
when _T_3118 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_3119 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3120 = bits(vpn, 1, 0)
node _T_3121 = eq(UInt<2>(0h3), _T_3120)
node _T_3122 = and(_T_3119, _T_3121)
when _T_3122 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
node _T_3123 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _T_3124 = shr(_T_3123, 18)
node _T_3125 = eq(_T_3124, UInt<1>(0h0))
when _T_3125 :
wire _WIRE_232 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_233 : UInt<42>
connect _WIRE_233, sectored_entries[0][7].data[0]
node _T_3126 = bits(_WIRE_233, 0, 0)
connect _WIRE_232.fragmented_superpage, _T_3126
node _T_3127 = bits(_WIRE_233, 1, 1)
connect _WIRE_232.c, _T_3127
node _T_3128 = bits(_WIRE_233, 2, 2)
connect _WIRE_232.eff, _T_3128
node _T_3129 = bits(_WIRE_233, 3, 3)
connect _WIRE_232.paa, _T_3129
node _T_3130 = bits(_WIRE_233, 4, 4)
connect _WIRE_232.pal, _T_3130
node _T_3131 = bits(_WIRE_233, 5, 5)
connect _WIRE_232.ppp, _T_3131
node _T_3132 = bits(_WIRE_233, 6, 6)
connect _WIRE_232.pr, _T_3132
node _T_3133 = bits(_WIRE_233, 7, 7)
connect _WIRE_232.px, _T_3133
node _T_3134 = bits(_WIRE_233, 8, 8)
connect _WIRE_232.pw, _T_3134
node _T_3135 = bits(_WIRE_233, 9, 9)
connect _WIRE_232.hr, _T_3135
node _T_3136 = bits(_WIRE_233, 10, 10)
connect _WIRE_232.hx, _T_3136
node _T_3137 = bits(_WIRE_233, 11, 11)
connect _WIRE_232.hw, _T_3137
node _T_3138 = bits(_WIRE_233, 12, 12)
connect _WIRE_232.sr, _T_3138
node _T_3139 = bits(_WIRE_233, 13, 13)
connect _WIRE_232.sx, _T_3139
node _T_3140 = bits(_WIRE_233, 14, 14)
connect _WIRE_232.sw, _T_3140
node _T_3141 = bits(_WIRE_233, 15, 15)
connect _WIRE_232.gf, _T_3141
node _T_3142 = bits(_WIRE_233, 16, 16)
connect _WIRE_232.pf, _T_3142
node _T_3143 = bits(_WIRE_233, 17, 17)
connect _WIRE_232.ae_stage2, _T_3143
node _T_3144 = bits(_WIRE_233, 18, 18)
connect _WIRE_232.ae_final, _T_3144
node _T_3145 = bits(_WIRE_233, 19, 19)
connect _WIRE_232.ae_ptw, _T_3145
node _T_3146 = bits(_WIRE_233, 20, 20)
connect _WIRE_232.g, _T_3146
node _T_3147 = bits(_WIRE_233, 21, 21)
connect _WIRE_232.u, _T_3147
node _T_3148 = bits(_WIRE_233, 41, 22)
connect _WIRE_232.ppn, _T_3148
wire _WIRE_234 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_235 : UInt<42>
connect _WIRE_235, sectored_entries[0][7].data[1]
node _T_3149 = bits(_WIRE_235, 0, 0)
connect _WIRE_234.fragmented_superpage, _T_3149
node _T_3150 = bits(_WIRE_235, 1, 1)
connect _WIRE_234.c, _T_3150
node _T_3151 = bits(_WIRE_235, 2, 2)
connect _WIRE_234.eff, _T_3151
node _T_3152 = bits(_WIRE_235, 3, 3)
connect _WIRE_234.paa, _T_3152
node _T_3153 = bits(_WIRE_235, 4, 4)
connect _WIRE_234.pal, _T_3153
node _T_3154 = bits(_WIRE_235, 5, 5)
connect _WIRE_234.ppp, _T_3154
node _T_3155 = bits(_WIRE_235, 6, 6)
connect _WIRE_234.pr, _T_3155
node _T_3156 = bits(_WIRE_235, 7, 7)
connect _WIRE_234.px, _T_3156
node _T_3157 = bits(_WIRE_235, 8, 8)
connect _WIRE_234.pw, _T_3157
node _T_3158 = bits(_WIRE_235, 9, 9)
connect _WIRE_234.hr, _T_3158
node _T_3159 = bits(_WIRE_235, 10, 10)
connect _WIRE_234.hx, _T_3159
node _T_3160 = bits(_WIRE_235, 11, 11)
connect _WIRE_234.hw, _T_3160
node _T_3161 = bits(_WIRE_235, 12, 12)
connect _WIRE_234.sr, _T_3161
node _T_3162 = bits(_WIRE_235, 13, 13)
connect _WIRE_234.sx, _T_3162
node _T_3163 = bits(_WIRE_235, 14, 14)
connect _WIRE_234.sw, _T_3163
node _T_3164 = bits(_WIRE_235, 15, 15)
connect _WIRE_234.gf, _T_3164
node _T_3165 = bits(_WIRE_235, 16, 16)
connect _WIRE_234.pf, _T_3165
node _T_3166 = bits(_WIRE_235, 17, 17)
connect _WIRE_234.ae_stage2, _T_3166
node _T_3167 = bits(_WIRE_235, 18, 18)
connect _WIRE_234.ae_final, _T_3167
node _T_3168 = bits(_WIRE_235, 19, 19)
connect _WIRE_234.ae_ptw, _T_3168
node _T_3169 = bits(_WIRE_235, 20, 20)
connect _WIRE_234.g, _T_3169
node _T_3170 = bits(_WIRE_235, 21, 21)
connect _WIRE_234.u, _T_3170
node _T_3171 = bits(_WIRE_235, 41, 22)
connect _WIRE_234.ppn, _T_3171
wire _WIRE_236 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_237 : UInt<42>
connect _WIRE_237, sectored_entries[0][7].data[2]
node _T_3172 = bits(_WIRE_237, 0, 0)
connect _WIRE_236.fragmented_superpage, _T_3172
node _T_3173 = bits(_WIRE_237, 1, 1)
connect _WIRE_236.c, _T_3173
node _T_3174 = bits(_WIRE_237, 2, 2)
connect _WIRE_236.eff, _T_3174
node _T_3175 = bits(_WIRE_237, 3, 3)
connect _WIRE_236.paa, _T_3175
node _T_3176 = bits(_WIRE_237, 4, 4)
connect _WIRE_236.pal, _T_3176
node _T_3177 = bits(_WIRE_237, 5, 5)
connect _WIRE_236.ppp, _T_3177
node _T_3178 = bits(_WIRE_237, 6, 6)
connect _WIRE_236.pr, _T_3178
node _T_3179 = bits(_WIRE_237, 7, 7)
connect _WIRE_236.px, _T_3179
node _T_3180 = bits(_WIRE_237, 8, 8)
connect _WIRE_236.pw, _T_3180
node _T_3181 = bits(_WIRE_237, 9, 9)
connect _WIRE_236.hr, _T_3181
node _T_3182 = bits(_WIRE_237, 10, 10)
connect _WIRE_236.hx, _T_3182
node _T_3183 = bits(_WIRE_237, 11, 11)
connect _WIRE_236.hw, _T_3183
node _T_3184 = bits(_WIRE_237, 12, 12)
connect _WIRE_236.sr, _T_3184
node _T_3185 = bits(_WIRE_237, 13, 13)
connect _WIRE_236.sx, _T_3185
node _T_3186 = bits(_WIRE_237, 14, 14)
connect _WIRE_236.sw, _T_3186
node _T_3187 = bits(_WIRE_237, 15, 15)
connect _WIRE_236.gf, _T_3187
node _T_3188 = bits(_WIRE_237, 16, 16)
connect _WIRE_236.pf, _T_3188
node _T_3189 = bits(_WIRE_237, 17, 17)
connect _WIRE_236.ae_stage2, _T_3189
node _T_3190 = bits(_WIRE_237, 18, 18)
connect _WIRE_236.ae_final, _T_3190
node _T_3191 = bits(_WIRE_237, 19, 19)
connect _WIRE_236.ae_ptw, _T_3191
node _T_3192 = bits(_WIRE_237, 20, 20)
connect _WIRE_236.g, _T_3192
node _T_3193 = bits(_WIRE_237, 21, 21)
connect _WIRE_236.u, _T_3193
node _T_3194 = bits(_WIRE_237, 41, 22)
connect _WIRE_236.ppn, _T_3194
wire _WIRE_238 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_239 : UInt<42>
connect _WIRE_239, sectored_entries[0][7].data[3]
node _T_3195 = bits(_WIRE_239, 0, 0)
connect _WIRE_238.fragmented_superpage, _T_3195
node _T_3196 = bits(_WIRE_239, 1, 1)
connect _WIRE_238.c, _T_3196
node _T_3197 = bits(_WIRE_239, 2, 2)
connect _WIRE_238.eff, _T_3197
node _T_3198 = bits(_WIRE_239, 3, 3)
connect _WIRE_238.paa, _T_3198
node _T_3199 = bits(_WIRE_239, 4, 4)
connect _WIRE_238.pal, _T_3199
node _T_3200 = bits(_WIRE_239, 5, 5)
connect _WIRE_238.ppp, _T_3200
node _T_3201 = bits(_WIRE_239, 6, 6)
connect _WIRE_238.pr, _T_3201
node _T_3202 = bits(_WIRE_239, 7, 7)
connect _WIRE_238.px, _T_3202
node _T_3203 = bits(_WIRE_239, 8, 8)
connect _WIRE_238.pw, _T_3203
node _T_3204 = bits(_WIRE_239, 9, 9)
connect _WIRE_238.hr, _T_3204
node _T_3205 = bits(_WIRE_239, 10, 10)
connect _WIRE_238.hx, _T_3205
node _T_3206 = bits(_WIRE_239, 11, 11)
connect _WIRE_238.hw, _T_3206
node _T_3207 = bits(_WIRE_239, 12, 12)
connect _WIRE_238.sr, _T_3207
node _T_3208 = bits(_WIRE_239, 13, 13)
connect _WIRE_238.sx, _T_3208
node _T_3209 = bits(_WIRE_239, 14, 14)
connect _WIRE_238.sw, _T_3209
node _T_3210 = bits(_WIRE_239, 15, 15)
connect _WIRE_238.gf, _T_3210
node _T_3211 = bits(_WIRE_239, 16, 16)
connect _WIRE_238.pf, _T_3211
node _T_3212 = bits(_WIRE_239, 17, 17)
connect _WIRE_238.ae_stage2, _T_3212
node _T_3213 = bits(_WIRE_239, 18, 18)
connect _WIRE_238.ae_final, _T_3213
node _T_3214 = bits(_WIRE_239, 19, 19)
connect _WIRE_238.ae_ptw, _T_3214
node _T_3215 = bits(_WIRE_239, 20, 20)
connect _WIRE_238.g, _T_3215
node _T_3216 = bits(_WIRE_239, 21, 21)
connect _WIRE_238.u, _T_3216
node _T_3217 = bits(_WIRE_239, 41, 22)
connect _WIRE_238.ppn, _T_3217
node _T_3218 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3219 = and(_T_3218, _WIRE_232.fragmented_superpage)
when _T_3219 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_3220 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3221 = and(_T_3220, _WIRE_234.fragmented_superpage)
when _T_3221 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_3222 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3223 = and(_T_3222, _WIRE_236.fragmented_superpage)
when _T_3223 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_3224 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3225 = and(_T_3224, _WIRE_238.fragmented_superpage)
when _T_3225 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
else :
node _T_3226 = eq(hg_7, UInt<1>(0h0))
node _T_3227 = and(_T_3226, io.sfence.bits.rs2)
when _T_3227 :
wire _WIRE_240 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_241 : UInt<42>
connect _WIRE_241, sectored_entries[0][7].data[0]
node _T_3228 = bits(_WIRE_241, 0, 0)
connect _WIRE_240.fragmented_superpage, _T_3228
node _T_3229 = bits(_WIRE_241, 1, 1)
connect _WIRE_240.c, _T_3229
node _T_3230 = bits(_WIRE_241, 2, 2)
connect _WIRE_240.eff, _T_3230
node _T_3231 = bits(_WIRE_241, 3, 3)
connect _WIRE_240.paa, _T_3231
node _T_3232 = bits(_WIRE_241, 4, 4)
connect _WIRE_240.pal, _T_3232
node _T_3233 = bits(_WIRE_241, 5, 5)
connect _WIRE_240.ppp, _T_3233
node _T_3234 = bits(_WIRE_241, 6, 6)
connect _WIRE_240.pr, _T_3234
node _T_3235 = bits(_WIRE_241, 7, 7)
connect _WIRE_240.px, _T_3235
node _T_3236 = bits(_WIRE_241, 8, 8)
connect _WIRE_240.pw, _T_3236
node _T_3237 = bits(_WIRE_241, 9, 9)
connect _WIRE_240.hr, _T_3237
node _T_3238 = bits(_WIRE_241, 10, 10)
connect _WIRE_240.hx, _T_3238
node _T_3239 = bits(_WIRE_241, 11, 11)
connect _WIRE_240.hw, _T_3239
node _T_3240 = bits(_WIRE_241, 12, 12)
connect _WIRE_240.sr, _T_3240
node _T_3241 = bits(_WIRE_241, 13, 13)
connect _WIRE_240.sx, _T_3241
node _T_3242 = bits(_WIRE_241, 14, 14)
connect _WIRE_240.sw, _T_3242
node _T_3243 = bits(_WIRE_241, 15, 15)
connect _WIRE_240.gf, _T_3243
node _T_3244 = bits(_WIRE_241, 16, 16)
connect _WIRE_240.pf, _T_3244
node _T_3245 = bits(_WIRE_241, 17, 17)
connect _WIRE_240.ae_stage2, _T_3245
node _T_3246 = bits(_WIRE_241, 18, 18)
connect _WIRE_240.ae_final, _T_3246
node _T_3247 = bits(_WIRE_241, 19, 19)
connect _WIRE_240.ae_ptw, _T_3247
node _T_3248 = bits(_WIRE_241, 20, 20)
connect _WIRE_240.g, _T_3248
node _T_3249 = bits(_WIRE_241, 21, 21)
connect _WIRE_240.u, _T_3249
node _T_3250 = bits(_WIRE_241, 41, 22)
connect _WIRE_240.ppn, _T_3250
wire _WIRE_242 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_243 : UInt<42>
connect _WIRE_243, sectored_entries[0][7].data[1]
node _T_3251 = bits(_WIRE_243, 0, 0)
connect _WIRE_242.fragmented_superpage, _T_3251
node _T_3252 = bits(_WIRE_243, 1, 1)
connect _WIRE_242.c, _T_3252
node _T_3253 = bits(_WIRE_243, 2, 2)
connect _WIRE_242.eff, _T_3253
node _T_3254 = bits(_WIRE_243, 3, 3)
connect _WIRE_242.paa, _T_3254
node _T_3255 = bits(_WIRE_243, 4, 4)
connect _WIRE_242.pal, _T_3255
node _T_3256 = bits(_WIRE_243, 5, 5)
connect _WIRE_242.ppp, _T_3256
node _T_3257 = bits(_WIRE_243, 6, 6)
connect _WIRE_242.pr, _T_3257
node _T_3258 = bits(_WIRE_243, 7, 7)
connect _WIRE_242.px, _T_3258
node _T_3259 = bits(_WIRE_243, 8, 8)
connect _WIRE_242.pw, _T_3259
node _T_3260 = bits(_WIRE_243, 9, 9)
connect _WIRE_242.hr, _T_3260
node _T_3261 = bits(_WIRE_243, 10, 10)
connect _WIRE_242.hx, _T_3261
node _T_3262 = bits(_WIRE_243, 11, 11)
connect _WIRE_242.hw, _T_3262
node _T_3263 = bits(_WIRE_243, 12, 12)
connect _WIRE_242.sr, _T_3263
node _T_3264 = bits(_WIRE_243, 13, 13)
connect _WIRE_242.sx, _T_3264
node _T_3265 = bits(_WIRE_243, 14, 14)
connect _WIRE_242.sw, _T_3265
node _T_3266 = bits(_WIRE_243, 15, 15)
connect _WIRE_242.gf, _T_3266
node _T_3267 = bits(_WIRE_243, 16, 16)
connect _WIRE_242.pf, _T_3267
node _T_3268 = bits(_WIRE_243, 17, 17)
connect _WIRE_242.ae_stage2, _T_3268
node _T_3269 = bits(_WIRE_243, 18, 18)
connect _WIRE_242.ae_final, _T_3269
node _T_3270 = bits(_WIRE_243, 19, 19)
connect _WIRE_242.ae_ptw, _T_3270
node _T_3271 = bits(_WIRE_243, 20, 20)
connect _WIRE_242.g, _T_3271
node _T_3272 = bits(_WIRE_243, 21, 21)
connect _WIRE_242.u, _T_3272
node _T_3273 = bits(_WIRE_243, 41, 22)
connect _WIRE_242.ppn, _T_3273
wire _WIRE_244 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_245 : UInt<42>
connect _WIRE_245, sectored_entries[0][7].data[2]
node _T_3274 = bits(_WIRE_245, 0, 0)
connect _WIRE_244.fragmented_superpage, _T_3274
node _T_3275 = bits(_WIRE_245, 1, 1)
connect _WIRE_244.c, _T_3275
node _T_3276 = bits(_WIRE_245, 2, 2)
connect _WIRE_244.eff, _T_3276
node _T_3277 = bits(_WIRE_245, 3, 3)
connect _WIRE_244.paa, _T_3277
node _T_3278 = bits(_WIRE_245, 4, 4)
connect _WIRE_244.pal, _T_3278
node _T_3279 = bits(_WIRE_245, 5, 5)
connect _WIRE_244.ppp, _T_3279
node _T_3280 = bits(_WIRE_245, 6, 6)
connect _WIRE_244.pr, _T_3280
node _T_3281 = bits(_WIRE_245, 7, 7)
connect _WIRE_244.px, _T_3281
node _T_3282 = bits(_WIRE_245, 8, 8)
connect _WIRE_244.pw, _T_3282
node _T_3283 = bits(_WIRE_245, 9, 9)
connect _WIRE_244.hr, _T_3283
node _T_3284 = bits(_WIRE_245, 10, 10)
connect _WIRE_244.hx, _T_3284
node _T_3285 = bits(_WIRE_245, 11, 11)
connect _WIRE_244.hw, _T_3285
node _T_3286 = bits(_WIRE_245, 12, 12)
connect _WIRE_244.sr, _T_3286
node _T_3287 = bits(_WIRE_245, 13, 13)
connect _WIRE_244.sx, _T_3287
node _T_3288 = bits(_WIRE_245, 14, 14)
connect _WIRE_244.sw, _T_3288
node _T_3289 = bits(_WIRE_245, 15, 15)
connect _WIRE_244.gf, _T_3289
node _T_3290 = bits(_WIRE_245, 16, 16)
connect _WIRE_244.pf, _T_3290
node _T_3291 = bits(_WIRE_245, 17, 17)
connect _WIRE_244.ae_stage2, _T_3291
node _T_3292 = bits(_WIRE_245, 18, 18)
connect _WIRE_244.ae_final, _T_3292
node _T_3293 = bits(_WIRE_245, 19, 19)
connect _WIRE_244.ae_ptw, _T_3293
node _T_3294 = bits(_WIRE_245, 20, 20)
connect _WIRE_244.g, _T_3294
node _T_3295 = bits(_WIRE_245, 21, 21)
connect _WIRE_244.u, _T_3295
node _T_3296 = bits(_WIRE_245, 41, 22)
connect _WIRE_244.ppn, _T_3296
wire _WIRE_246 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_247 : UInt<42>
connect _WIRE_247, sectored_entries[0][7].data[3]
node _T_3297 = bits(_WIRE_247, 0, 0)
connect _WIRE_246.fragmented_superpage, _T_3297
node _T_3298 = bits(_WIRE_247, 1, 1)
connect _WIRE_246.c, _T_3298
node _T_3299 = bits(_WIRE_247, 2, 2)
connect _WIRE_246.eff, _T_3299
node _T_3300 = bits(_WIRE_247, 3, 3)
connect _WIRE_246.paa, _T_3300
node _T_3301 = bits(_WIRE_247, 4, 4)
connect _WIRE_246.pal, _T_3301
node _T_3302 = bits(_WIRE_247, 5, 5)
connect _WIRE_246.ppp, _T_3302
node _T_3303 = bits(_WIRE_247, 6, 6)
connect _WIRE_246.pr, _T_3303
node _T_3304 = bits(_WIRE_247, 7, 7)
connect _WIRE_246.px, _T_3304
node _T_3305 = bits(_WIRE_247, 8, 8)
connect _WIRE_246.pw, _T_3305
node _T_3306 = bits(_WIRE_247, 9, 9)
connect _WIRE_246.hr, _T_3306
node _T_3307 = bits(_WIRE_247, 10, 10)
connect _WIRE_246.hx, _T_3307
node _T_3308 = bits(_WIRE_247, 11, 11)
connect _WIRE_246.hw, _T_3308
node _T_3309 = bits(_WIRE_247, 12, 12)
connect _WIRE_246.sr, _T_3309
node _T_3310 = bits(_WIRE_247, 13, 13)
connect _WIRE_246.sx, _T_3310
node _T_3311 = bits(_WIRE_247, 14, 14)
connect _WIRE_246.sw, _T_3311
node _T_3312 = bits(_WIRE_247, 15, 15)
connect _WIRE_246.gf, _T_3312
node _T_3313 = bits(_WIRE_247, 16, 16)
connect _WIRE_246.pf, _T_3313
node _T_3314 = bits(_WIRE_247, 17, 17)
connect _WIRE_246.ae_stage2, _T_3314
node _T_3315 = bits(_WIRE_247, 18, 18)
connect _WIRE_246.ae_final, _T_3315
node _T_3316 = bits(_WIRE_247, 19, 19)
connect _WIRE_246.ae_ptw, _T_3316
node _T_3317 = bits(_WIRE_247, 20, 20)
connect _WIRE_246.g, _T_3317
node _T_3318 = bits(_WIRE_247, 21, 21)
connect _WIRE_246.u, _T_3318
node _T_3319 = bits(_WIRE_247, 41, 22)
connect _WIRE_246.ppn, _T_3319
node _T_3320 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3321 = eq(_WIRE_240.g, UInt<1>(0h0))
node _T_3322 = and(_T_3320, _T_3321)
when _T_3322 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_3323 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3324 = eq(_WIRE_242.g, UInt<1>(0h0))
node _T_3325 = and(_T_3323, _T_3324)
when _T_3325 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_3326 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3327 = eq(_WIRE_244.g, UInt<1>(0h0))
node _T_3328 = and(_T_3326, _T_3327)
when _T_3328 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_3329 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3330 = eq(_WIRE_246.g, UInt<1>(0h0))
node _T_3331 = and(_T_3329, _T_3330)
when _T_3331 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
else :
node _T_3332 = or(hv_7, hg_7)
wire _WIRE_248 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_249 : UInt<42>
connect _WIRE_249, sectored_entries[0][7].data[0]
node _T_3333 = bits(_WIRE_249, 0, 0)
connect _WIRE_248.fragmented_superpage, _T_3333
node _T_3334 = bits(_WIRE_249, 1, 1)
connect _WIRE_248.c, _T_3334
node _T_3335 = bits(_WIRE_249, 2, 2)
connect _WIRE_248.eff, _T_3335
node _T_3336 = bits(_WIRE_249, 3, 3)
connect _WIRE_248.paa, _T_3336
node _T_3337 = bits(_WIRE_249, 4, 4)
connect _WIRE_248.pal, _T_3337
node _T_3338 = bits(_WIRE_249, 5, 5)
connect _WIRE_248.ppp, _T_3338
node _T_3339 = bits(_WIRE_249, 6, 6)
connect _WIRE_248.pr, _T_3339
node _T_3340 = bits(_WIRE_249, 7, 7)
connect _WIRE_248.px, _T_3340
node _T_3341 = bits(_WIRE_249, 8, 8)
connect _WIRE_248.pw, _T_3341
node _T_3342 = bits(_WIRE_249, 9, 9)
connect _WIRE_248.hr, _T_3342
node _T_3343 = bits(_WIRE_249, 10, 10)
connect _WIRE_248.hx, _T_3343
node _T_3344 = bits(_WIRE_249, 11, 11)
connect _WIRE_248.hw, _T_3344
node _T_3345 = bits(_WIRE_249, 12, 12)
connect _WIRE_248.sr, _T_3345
node _T_3346 = bits(_WIRE_249, 13, 13)
connect _WIRE_248.sx, _T_3346
node _T_3347 = bits(_WIRE_249, 14, 14)
connect _WIRE_248.sw, _T_3347
node _T_3348 = bits(_WIRE_249, 15, 15)
connect _WIRE_248.gf, _T_3348
node _T_3349 = bits(_WIRE_249, 16, 16)
connect _WIRE_248.pf, _T_3349
node _T_3350 = bits(_WIRE_249, 17, 17)
connect _WIRE_248.ae_stage2, _T_3350
node _T_3351 = bits(_WIRE_249, 18, 18)
connect _WIRE_248.ae_final, _T_3351
node _T_3352 = bits(_WIRE_249, 19, 19)
connect _WIRE_248.ae_ptw, _T_3352
node _T_3353 = bits(_WIRE_249, 20, 20)
connect _WIRE_248.g, _T_3353
node _T_3354 = bits(_WIRE_249, 21, 21)
connect _WIRE_248.u, _T_3354
node _T_3355 = bits(_WIRE_249, 41, 22)
connect _WIRE_248.ppn, _T_3355
wire _WIRE_250 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_251 : UInt<42>
connect _WIRE_251, sectored_entries[0][7].data[1]
node _T_3356 = bits(_WIRE_251, 0, 0)
connect _WIRE_250.fragmented_superpage, _T_3356
node _T_3357 = bits(_WIRE_251, 1, 1)
connect _WIRE_250.c, _T_3357
node _T_3358 = bits(_WIRE_251, 2, 2)
connect _WIRE_250.eff, _T_3358
node _T_3359 = bits(_WIRE_251, 3, 3)
connect _WIRE_250.paa, _T_3359
node _T_3360 = bits(_WIRE_251, 4, 4)
connect _WIRE_250.pal, _T_3360
node _T_3361 = bits(_WIRE_251, 5, 5)
connect _WIRE_250.ppp, _T_3361
node _T_3362 = bits(_WIRE_251, 6, 6)
connect _WIRE_250.pr, _T_3362
node _T_3363 = bits(_WIRE_251, 7, 7)
connect _WIRE_250.px, _T_3363
node _T_3364 = bits(_WIRE_251, 8, 8)
connect _WIRE_250.pw, _T_3364
node _T_3365 = bits(_WIRE_251, 9, 9)
connect _WIRE_250.hr, _T_3365
node _T_3366 = bits(_WIRE_251, 10, 10)
connect _WIRE_250.hx, _T_3366
node _T_3367 = bits(_WIRE_251, 11, 11)
connect _WIRE_250.hw, _T_3367
node _T_3368 = bits(_WIRE_251, 12, 12)
connect _WIRE_250.sr, _T_3368
node _T_3369 = bits(_WIRE_251, 13, 13)
connect _WIRE_250.sx, _T_3369
node _T_3370 = bits(_WIRE_251, 14, 14)
connect _WIRE_250.sw, _T_3370
node _T_3371 = bits(_WIRE_251, 15, 15)
connect _WIRE_250.gf, _T_3371
node _T_3372 = bits(_WIRE_251, 16, 16)
connect _WIRE_250.pf, _T_3372
node _T_3373 = bits(_WIRE_251, 17, 17)
connect _WIRE_250.ae_stage2, _T_3373
node _T_3374 = bits(_WIRE_251, 18, 18)
connect _WIRE_250.ae_final, _T_3374
node _T_3375 = bits(_WIRE_251, 19, 19)
connect _WIRE_250.ae_ptw, _T_3375
node _T_3376 = bits(_WIRE_251, 20, 20)
connect _WIRE_250.g, _T_3376
node _T_3377 = bits(_WIRE_251, 21, 21)
connect _WIRE_250.u, _T_3377
node _T_3378 = bits(_WIRE_251, 41, 22)
connect _WIRE_250.ppn, _T_3378
wire _WIRE_252 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_253 : UInt<42>
connect _WIRE_253, sectored_entries[0][7].data[2]
node _T_3379 = bits(_WIRE_253, 0, 0)
connect _WIRE_252.fragmented_superpage, _T_3379
node _T_3380 = bits(_WIRE_253, 1, 1)
connect _WIRE_252.c, _T_3380
node _T_3381 = bits(_WIRE_253, 2, 2)
connect _WIRE_252.eff, _T_3381
node _T_3382 = bits(_WIRE_253, 3, 3)
connect _WIRE_252.paa, _T_3382
node _T_3383 = bits(_WIRE_253, 4, 4)
connect _WIRE_252.pal, _T_3383
node _T_3384 = bits(_WIRE_253, 5, 5)
connect _WIRE_252.ppp, _T_3384
node _T_3385 = bits(_WIRE_253, 6, 6)
connect _WIRE_252.pr, _T_3385
node _T_3386 = bits(_WIRE_253, 7, 7)
connect _WIRE_252.px, _T_3386
node _T_3387 = bits(_WIRE_253, 8, 8)
connect _WIRE_252.pw, _T_3387
node _T_3388 = bits(_WIRE_253, 9, 9)
connect _WIRE_252.hr, _T_3388
node _T_3389 = bits(_WIRE_253, 10, 10)
connect _WIRE_252.hx, _T_3389
node _T_3390 = bits(_WIRE_253, 11, 11)
connect _WIRE_252.hw, _T_3390
node _T_3391 = bits(_WIRE_253, 12, 12)
connect _WIRE_252.sr, _T_3391
node _T_3392 = bits(_WIRE_253, 13, 13)
connect _WIRE_252.sx, _T_3392
node _T_3393 = bits(_WIRE_253, 14, 14)
connect _WIRE_252.sw, _T_3393
node _T_3394 = bits(_WIRE_253, 15, 15)
connect _WIRE_252.gf, _T_3394
node _T_3395 = bits(_WIRE_253, 16, 16)
connect _WIRE_252.pf, _T_3395
node _T_3396 = bits(_WIRE_253, 17, 17)
connect _WIRE_252.ae_stage2, _T_3396
node _T_3397 = bits(_WIRE_253, 18, 18)
connect _WIRE_252.ae_final, _T_3397
node _T_3398 = bits(_WIRE_253, 19, 19)
connect _WIRE_252.ae_ptw, _T_3398
node _T_3399 = bits(_WIRE_253, 20, 20)
connect _WIRE_252.g, _T_3399
node _T_3400 = bits(_WIRE_253, 21, 21)
connect _WIRE_252.u, _T_3400
node _T_3401 = bits(_WIRE_253, 41, 22)
connect _WIRE_252.ppn, _T_3401
wire _WIRE_254 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_255 : UInt<42>
connect _WIRE_255, sectored_entries[0][7].data[3]
node _T_3402 = bits(_WIRE_255, 0, 0)
connect _WIRE_254.fragmented_superpage, _T_3402
node _T_3403 = bits(_WIRE_255, 1, 1)
connect _WIRE_254.c, _T_3403
node _T_3404 = bits(_WIRE_255, 2, 2)
connect _WIRE_254.eff, _T_3404
node _T_3405 = bits(_WIRE_255, 3, 3)
connect _WIRE_254.paa, _T_3405
node _T_3406 = bits(_WIRE_255, 4, 4)
connect _WIRE_254.pal, _T_3406
node _T_3407 = bits(_WIRE_255, 5, 5)
connect _WIRE_254.ppp, _T_3407
node _T_3408 = bits(_WIRE_255, 6, 6)
connect _WIRE_254.pr, _T_3408
node _T_3409 = bits(_WIRE_255, 7, 7)
connect _WIRE_254.px, _T_3409
node _T_3410 = bits(_WIRE_255, 8, 8)
connect _WIRE_254.pw, _T_3410
node _T_3411 = bits(_WIRE_255, 9, 9)
connect _WIRE_254.hr, _T_3411
node _T_3412 = bits(_WIRE_255, 10, 10)
connect _WIRE_254.hx, _T_3412
node _T_3413 = bits(_WIRE_255, 11, 11)
connect _WIRE_254.hw, _T_3413
node _T_3414 = bits(_WIRE_255, 12, 12)
connect _WIRE_254.sr, _T_3414
node _T_3415 = bits(_WIRE_255, 13, 13)
connect _WIRE_254.sx, _T_3415
node _T_3416 = bits(_WIRE_255, 14, 14)
connect _WIRE_254.sw, _T_3416
node _T_3417 = bits(_WIRE_255, 15, 15)
connect _WIRE_254.gf, _T_3417
node _T_3418 = bits(_WIRE_255, 16, 16)
connect _WIRE_254.pf, _T_3418
node _T_3419 = bits(_WIRE_255, 17, 17)
connect _WIRE_254.ae_stage2, _T_3419
node _T_3420 = bits(_WIRE_255, 18, 18)
connect _WIRE_254.ae_final, _T_3420
node _T_3421 = bits(_WIRE_255, 19, 19)
connect _WIRE_254.ae_ptw, _T_3421
node _T_3422 = bits(_WIRE_255, 20, 20)
connect _WIRE_254.g, _T_3422
node _T_3423 = bits(_WIRE_255, 21, 21)
connect _WIRE_254.u, _T_3423
node _T_3424 = bits(_WIRE_255, 41, 22)
connect _WIRE_254.ppn, _T_3424
node _T_3425 = eq(sectored_entries[0][7].tag_v, _T_3332)
when _T_3425 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_3426 = eq(sectored_entries[0][7].tag_v, _T_3332)
when _T_3426 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_3427 = eq(sectored_entries[0][7].tag_v, _T_3332)
when _T_3427 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_3428 = eq(sectored_entries[0][7].tag_v, _T_3332)
when _T_3428 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
node hv_8 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_8 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3429 = eq(hg_8, UInt<1>(0h0))
node _T_3430 = and(_T_3429, io.sfence.bits.rs1)
when _T_3430 :
node _tagMatch_T = eq(superpage_entries[0].tag_v, hv_8)
node tagMatch = and(superpage_entries[0].valid[0], _tagMatch_T)
node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0))
node ignore = or(_ignore_T, UInt<1>(0h0))
node _T_3431 = xor(superpage_entries[0].tag_vpn, vpn)
node _T_3432 = bits(_T_3431, 26, 18)
node _T_3433 = eq(_T_3432, UInt<1>(0h0))
node _T_3434 = or(ignore, _T_3433)
node _T_3435 = and(tagMatch, _T_3434)
node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1))
node ignore_1 = or(_ignore_T_1, UInt<1>(0h0))
node _T_3436 = xor(superpage_entries[0].tag_vpn, vpn)
node _T_3437 = bits(_T_3436, 17, 9)
node _T_3438 = eq(_T_3437, UInt<1>(0h0))
node _T_3439 = or(ignore_1, _T_3438)
node _T_3440 = and(_T_3435, _T_3439)
node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2))
node ignore_2 = or(_ignore_T_2, UInt<1>(0h1))
node _T_3441 = xor(superpage_entries[0].tag_vpn, vpn)
node _T_3442 = bits(_T_3441, 8, 0)
node _T_3443 = eq(_T_3442, UInt<1>(0h0))
node _T_3444 = or(ignore_2, _T_3443)
node _T_3445 = and(_T_3440, _T_3444)
when _T_3445 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
node _T_3446 = xor(superpage_entries[0].tag_vpn, vpn)
node _T_3447 = shr(_T_3446, 18)
node _T_3448 = eq(_T_3447, UInt<1>(0h0))
when _T_3448 :
wire _WIRE_256 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_257 : UInt<42>
connect _WIRE_257, superpage_entries[0].data[0]
node _T_3449 = bits(_WIRE_257, 0, 0)
connect _WIRE_256.fragmented_superpage, _T_3449
node _T_3450 = bits(_WIRE_257, 1, 1)
connect _WIRE_256.c, _T_3450
node _T_3451 = bits(_WIRE_257, 2, 2)
connect _WIRE_256.eff, _T_3451
node _T_3452 = bits(_WIRE_257, 3, 3)
connect _WIRE_256.paa, _T_3452
node _T_3453 = bits(_WIRE_257, 4, 4)
connect _WIRE_256.pal, _T_3453
node _T_3454 = bits(_WIRE_257, 5, 5)
connect _WIRE_256.ppp, _T_3454
node _T_3455 = bits(_WIRE_257, 6, 6)
connect _WIRE_256.pr, _T_3455
node _T_3456 = bits(_WIRE_257, 7, 7)
connect _WIRE_256.px, _T_3456
node _T_3457 = bits(_WIRE_257, 8, 8)
connect _WIRE_256.pw, _T_3457
node _T_3458 = bits(_WIRE_257, 9, 9)
connect _WIRE_256.hr, _T_3458
node _T_3459 = bits(_WIRE_257, 10, 10)
connect _WIRE_256.hx, _T_3459
node _T_3460 = bits(_WIRE_257, 11, 11)
connect _WIRE_256.hw, _T_3460
node _T_3461 = bits(_WIRE_257, 12, 12)
connect _WIRE_256.sr, _T_3461
node _T_3462 = bits(_WIRE_257, 13, 13)
connect _WIRE_256.sx, _T_3462
node _T_3463 = bits(_WIRE_257, 14, 14)
connect _WIRE_256.sw, _T_3463
node _T_3464 = bits(_WIRE_257, 15, 15)
connect _WIRE_256.gf, _T_3464
node _T_3465 = bits(_WIRE_257, 16, 16)
connect _WIRE_256.pf, _T_3465
node _T_3466 = bits(_WIRE_257, 17, 17)
connect _WIRE_256.ae_stage2, _T_3466
node _T_3467 = bits(_WIRE_257, 18, 18)
connect _WIRE_256.ae_final, _T_3467
node _T_3468 = bits(_WIRE_257, 19, 19)
connect _WIRE_256.ae_ptw, _T_3468
node _T_3469 = bits(_WIRE_257, 20, 20)
connect _WIRE_256.g, _T_3469
node _T_3470 = bits(_WIRE_257, 21, 21)
connect _WIRE_256.u, _T_3470
node _T_3471 = bits(_WIRE_257, 41, 22)
connect _WIRE_256.ppn, _T_3471
node _T_3472 = eq(superpage_entries[0].tag_v, hv_8)
node _T_3473 = and(_T_3472, _WIRE_256.fragmented_superpage)
when _T_3473 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
else :
node _T_3474 = eq(hg_8, UInt<1>(0h0))
node _T_3475 = and(_T_3474, io.sfence.bits.rs2)
when _T_3475 :
wire _WIRE_258 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_259 : UInt<42>
connect _WIRE_259, superpage_entries[0].data[0]
node _T_3476 = bits(_WIRE_259, 0, 0)
connect _WIRE_258.fragmented_superpage, _T_3476
node _T_3477 = bits(_WIRE_259, 1, 1)
connect _WIRE_258.c, _T_3477
node _T_3478 = bits(_WIRE_259, 2, 2)
connect _WIRE_258.eff, _T_3478
node _T_3479 = bits(_WIRE_259, 3, 3)
connect _WIRE_258.paa, _T_3479
node _T_3480 = bits(_WIRE_259, 4, 4)
connect _WIRE_258.pal, _T_3480
node _T_3481 = bits(_WIRE_259, 5, 5)
connect _WIRE_258.ppp, _T_3481
node _T_3482 = bits(_WIRE_259, 6, 6)
connect _WIRE_258.pr, _T_3482
node _T_3483 = bits(_WIRE_259, 7, 7)
connect _WIRE_258.px, _T_3483
node _T_3484 = bits(_WIRE_259, 8, 8)
connect _WIRE_258.pw, _T_3484
node _T_3485 = bits(_WIRE_259, 9, 9)
connect _WIRE_258.hr, _T_3485
node _T_3486 = bits(_WIRE_259, 10, 10)
connect _WIRE_258.hx, _T_3486
node _T_3487 = bits(_WIRE_259, 11, 11)
connect _WIRE_258.hw, _T_3487
node _T_3488 = bits(_WIRE_259, 12, 12)
connect _WIRE_258.sr, _T_3488
node _T_3489 = bits(_WIRE_259, 13, 13)
connect _WIRE_258.sx, _T_3489
node _T_3490 = bits(_WIRE_259, 14, 14)
connect _WIRE_258.sw, _T_3490
node _T_3491 = bits(_WIRE_259, 15, 15)
connect _WIRE_258.gf, _T_3491
node _T_3492 = bits(_WIRE_259, 16, 16)
connect _WIRE_258.pf, _T_3492
node _T_3493 = bits(_WIRE_259, 17, 17)
connect _WIRE_258.ae_stage2, _T_3493
node _T_3494 = bits(_WIRE_259, 18, 18)
connect _WIRE_258.ae_final, _T_3494
node _T_3495 = bits(_WIRE_259, 19, 19)
connect _WIRE_258.ae_ptw, _T_3495
node _T_3496 = bits(_WIRE_259, 20, 20)
connect _WIRE_258.g, _T_3496
node _T_3497 = bits(_WIRE_259, 21, 21)
connect _WIRE_258.u, _T_3497
node _T_3498 = bits(_WIRE_259, 41, 22)
connect _WIRE_258.ppn, _T_3498
node _T_3499 = eq(superpage_entries[0].tag_v, hv_8)
node _T_3500 = eq(_WIRE_258.g, UInt<1>(0h0))
node _T_3501 = and(_T_3499, _T_3500)
when _T_3501 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
else :
node _T_3502 = or(hv_8, hg_8)
wire _WIRE_260 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_261 : UInt<42>
connect _WIRE_261, superpage_entries[0].data[0]
node _T_3503 = bits(_WIRE_261, 0, 0)
connect _WIRE_260.fragmented_superpage, _T_3503
node _T_3504 = bits(_WIRE_261, 1, 1)
connect _WIRE_260.c, _T_3504
node _T_3505 = bits(_WIRE_261, 2, 2)
connect _WIRE_260.eff, _T_3505
node _T_3506 = bits(_WIRE_261, 3, 3)
connect _WIRE_260.paa, _T_3506
node _T_3507 = bits(_WIRE_261, 4, 4)
connect _WIRE_260.pal, _T_3507
node _T_3508 = bits(_WIRE_261, 5, 5)
connect _WIRE_260.ppp, _T_3508
node _T_3509 = bits(_WIRE_261, 6, 6)
connect _WIRE_260.pr, _T_3509
node _T_3510 = bits(_WIRE_261, 7, 7)
connect _WIRE_260.px, _T_3510
node _T_3511 = bits(_WIRE_261, 8, 8)
connect _WIRE_260.pw, _T_3511
node _T_3512 = bits(_WIRE_261, 9, 9)
connect _WIRE_260.hr, _T_3512
node _T_3513 = bits(_WIRE_261, 10, 10)
connect _WIRE_260.hx, _T_3513
node _T_3514 = bits(_WIRE_261, 11, 11)
connect _WIRE_260.hw, _T_3514
node _T_3515 = bits(_WIRE_261, 12, 12)
connect _WIRE_260.sr, _T_3515
node _T_3516 = bits(_WIRE_261, 13, 13)
connect _WIRE_260.sx, _T_3516
node _T_3517 = bits(_WIRE_261, 14, 14)
connect _WIRE_260.sw, _T_3517
node _T_3518 = bits(_WIRE_261, 15, 15)
connect _WIRE_260.gf, _T_3518
node _T_3519 = bits(_WIRE_261, 16, 16)
connect _WIRE_260.pf, _T_3519
node _T_3520 = bits(_WIRE_261, 17, 17)
connect _WIRE_260.ae_stage2, _T_3520
node _T_3521 = bits(_WIRE_261, 18, 18)
connect _WIRE_260.ae_final, _T_3521
node _T_3522 = bits(_WIRE_261, 19, 19)
connect _WIRE_260.ae_ptw, _T_3522
node _T_3523 = bits(_WIRE_261, 20, 20)
connect _WIRE_260.g, _T_3523
node _T_3524 = bits(_WIRE_261, 21, 21)
connect _WIRE_260.u, _T_3524
node _T_3525 = bits(_WIRE_261, 41, 22)
connect _WIRE_260.ppn, _T_3525
node _T_3526 = eq(superpage_entries[0].tag_v, _T_3502)
when _T_3526 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
node hv_9 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_9 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3527 = eq(hg_9, UInt<1>(0h0))
node _T_3528 = and(_T_3527, io.sfence.bits.rs1)
when _T_3528 :
node _tagMatch_T_1 = eq(superpage_entries[1].tag_v, hv_9)
node tagMatch_1 = and(superpage_entries[1].valid[0], _tagMatch_T_1)
node _ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0))
node ignore_3 = or(_ignore_T_3, UInt<1>(0h0))
node _T_3529 = xor(superpage_entries[1].tag_vpn, vpn)
node _T_3530 = bits(_T_3529, 26, 18)
node _T_3531 = eq(_T_3530, UInt<1>(0h0))
node _T_3532 = or(ignore_3, _T_3531)
node _T_3533 = and(tagMatch_1, _T_3532)
node _ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1))
node ignore_4 = or(_ignore_T_4, UInt<1>(0h0))
node _T_3534 = xor(superpage_entries[1].tag_vpn, vpn)
node _T_3535 = bits(_T_3534, 17, 9)
node _T_3536 = eq(_T_3535, UInt<1>(0h0))
node _T_3537 = or(ignore_4, _T_3536)
node _T_3538 = and(_T_3533, _T_3537)
node _ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2))
node ignore_5 = or(_ignore_T_5, UInt<1>(0h1))
node _T_3539 = xor(superpage_entries[1].tag_vpn, vpn)
node _T_3540 = bits(_T_3539, 8, 0)
node _T_3541 = eq(_T_3540, UInt<1>(0h0))
node _T_3542 = or(ignore_5, _T_3541)
node _T_3543 = and(_T_3538, _T_3542)
when _T_3543 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
node _T_3544 = xor(superpage_entries[1].tag_vpn, vpn)
node _T_3545 = shr(_T_3544, 18)
node _T_3546 = eq(_T_3545, UInt<1>(0h0))
when _T_3546 :
wire _WIRE_262 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_263 : UInt<42>
connect _WIRE_263, superpage_entries[1].data[0]
node _T_3547 = bits(_WIRE_263, 0, 0)
connect _WIRE_262.fragmented_superpage, _T_3547
node _T_3548 = bits(_WIRE_263, 1, 1)
connect _WIRE_262.c, _T_3548
node _T_3549 = bits(_WIRE_263, 2, 2)
connect _WIRE_262.eff, _T_3549
node _T_3550 = bits(_WIRE_263, 3, 3)
connect _WIRE_262.paa, _T_3550
node _T_3551 = bits(_WIRE_263, 4, 4)
connect _WIRE_262.pal, _T_3551
node _T_3552 = bits(_WIRE_263, 5, 5)
connect _WIRE_262.ppp, _T_3552
node _T_3553 = bits(_WIRE_263, 6, 6)
connect _WIRE_262.pr, _T_3553
node _T_3554 = bits(_WIRE_263, 7, 7)
connect _WIRE_262.px, _T_3554
node _T_3555 = bits(_WIRE_263, 8, 8)
connect _WIRE_262.pw, _T_3555
node _T_3556 = bits(_WIRE_263, 9, 9)
connect _WIRE_262.hr, _T_3556
node _T_3557 = bits(_WIRE_263, 10, 10)
connect _WIRE_262.hx, _T_3557
node _T_3558 = bits(_WIRE_263, 11, 11)
connect _WIRE_262.hw, _T_3558
node _T_3559 = bits(_WIRE_263, 12, 12)
connect _WIRE_262.sr, _T_3559
node _T_3560 = bits(_WIRE_263, 13, 13)
connect _WIRE_262.sx, _T_3560
node _T_3561 = bits(_WIRE_263, 14, 14)
connect _WIRE_262.sw, _T_3561
node _T_3562 = bits(_WIRE_263, 15, 15)
connect _WIRE_262.gf, _T_3562
node _T_3563 = bits(_WIRE_263, 16, 16)
connect _WIRE_262.pf, _T_3563
node _T_3564 = bits(_WIRE_263, 17, 17)
connect _WIRE_262.ae_stage2, _T_3564
node _T_3565 = bits(_WIRE_263, 18, 18)
connect _WIRE_262.ae_final, _T_3565
node _T_3566 = bits(_WIRE_263, 19, 19)
connect _WIRE_262.ae_ptw, _T_3566
node _T_3567 = bits(_WIRE_263, 20, 20)
connect _WIRE_262.g, _T_3567
node _T_3568 = bits(_WIRE_263, 21, 21)
connect _WIRE_262.u, _T_3568
node _T_3569 = bits(_WIRE_263, 41, 22)
connect _WIRE_262.ppn, _T_3569
node _T_3570 = eq(superpage_entries[1].tag_v, hv_9)
node _T_3571 = and(_T_3570, _WIRE_262.fragmented_superpage)
when _T_3571 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
else :
node _T_3572 = eq(hg_9, UInt<1>(0h0))
node _T_3573 = and(_T_3572, io.sfence.bits.rs2)
when _T_3573 :
wire _WIRE_264 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_265 : UInt<42>
connect _WIRE_265, superpage_entries[1].data[0]
node _T_3574 = bits(_WIRE_265, 0, 0)
connect _WIRE_264.fragmented_superpage, _T_3574
node _T_3575 = bits(_WIRE_265, 1, 1)
connect _WIRE_264.c, _T_3575
node _T_3576 = bits(_WIRE_265, 2, 2)
connect _WIRE_264.eff, _T_3576
node _T_3577 = bits(_WIRE_265, 3, 3)
connect _WIRE_264.paa, _T_3577
node _T_3578 = bits(_WIRE_265, 4, 4)
connect _WIRE_264.pal, _T_3578
node _T_3579 = bits(_WIRE_265, 5, 5)
connect _WIRE_264.ppp, _T_3579
node _T_3580 = bits(_WIRE_265, 6, 6)
connect _WIRE_264.pr, _T_3580
node _T_3581 = bits(_WIRE_265, 7, 7)
connect _WIRE_264.px, _T_3581
node _T_3582 = bits(_WIRE_265, 8, 8)
connect _WIRE_264.pw, _T_3582
node _T_3583 = bits(_WIRE_265, 9, 9)
connect _WIRE_264.hr, _T_3583
node _T_3584 = bits(_WIRE_265, 10, 10)
connect _WIRE_264.hx, _T_3584
node _T_3585 = bits(_WIRE_265, 11, 11)
connect _WIRE_264.hw, _T_3585
node _T_3586 = bits(_WIRE_265, 12, 12)
connect _WIRE_264.sr, _T_3586
node _T_3587 = bits(_WIRE_265, 13, 13)
connect _WIRE_264.sx, _T_3587
node _T_3588 = bits(_WIRE_265, 14, 14)
connect _WIRE_264.sw, _T_3588
node _T_3589 = bits(_WIRE_265, 15, 15)
connect _WIRE_264.gf, _T_3589
node _T_3590 = bits(_WIRE_265, 16, 16)
connect _WIRE_264.pf, _T_3590
node _T_3591 = bits(_WIRE_265, 17, 17)
connect _WIRE_264.ae_stage2, _T_3591
node _T_3592 = bits(_WIRE_265, 18, 18)
connect _WIRE_264.ae_final, _T_3592
node _T_3593 = bits(_WIRE_265, 19, 19)
connect _WIRE_264.ae_ptw, _T_3593
node _T_3594 = bits(_WIRE_265, 20, 20)
connect _WIRE_264.g, _T_3594
node _T_3595 = bits(_WIRE_265, 21, 21)
connect _WIRE_264.u, _T_3595
node _T_3596 = bits(_WIRE_265, 41, 22)
connect _WIRE_264.ppn, _T_3596
node _T_3597 = eq(superpage_entries[1].tag_v, hv_9)
node _T_3598 = eq(_WIRE_264.g, UInt<1>(0h0))
node _T_3599 = and(_T_3597, _T_3598)
when _T_3599 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
else :
node _T_3600 = or(hv_9, hg_9)
wire _WIRE_266 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_267 : UInt<42>
connect _WIRE_267, superpage_entries[1].data[0]
node _T_3601 = bits(_WIRE_267, 0, 0)
connect _WIRE_266.fragmented_superpage, _T_3601
node _T_3602 = bits(_WIRE_267, 1, 1)
connect _WIRE_266.c, _T_3602
node _T_3603 = bits(_WIRE_267, 2, 2)
connect _WIRE_266.eff, _T_3603
node _T_3604 = bits(_WIRE_267, 3, 3)
connect _WIRE_266.paa, _T_3604
node _T_3605 = bits(_WIRE_267, 4, 4)
connect _WIRE_266.pal, _T_3605
node _T_3606 = bits(_WIRE_267, 5, 5)
connect _WIRE_266.ppp, _T_3606
node _T_3607 = bits(_WIRE_267, 6, 6)
connect _WIRE_266.pr, _T_3607
node _T_3608 = bits(_WIRE_267, 7, 7)
connect _WIRE_266.px, _T_3608
node _T_3609 = bits(_WIRE_267, 8, 8)
connect _WIRE_266.pw, _T_3609
node _T_3610 = bits(_WIRE_267, 9, 9)
connect _WIRE_266.hr, _T_3610
node _T_3611 = bits(_WIRE_267, 10, 10)
connect _WIRE_266.hx, _T_3611
node _T_3612 = bits(_WIRE_267, 11, 11)
connect _WIRE_266.hw, _T_3612
node _T_3613 = bits(_WIRE_267, 12, 12)
connect _WIRE_266.sr, _T_3613
node _T_3614 = bits(_WIRE_267, 13, 13)
connect _WIRE_266.sx, _T_3614
node _T_3615 = bits(_WIRE_267, 14, 14)
connect _WIRE_266.sw, _T_3615
node _T_3616 = bits(_WIRE_267, 15, 15)
connect _WIRE_266.gf, _T_3616
node _T_3617 = bits(_WIRE_267, 16, 16)
connect _WIRE_266.pf, _T_3617
node _T_3618 = bits(_WIRE_267, 17, 17)
connect _WIRE_266.ae_stage2, _T_3618
node _T_3619 = bits(_WIRE_267, 18, 18)
connect _WIRE_266.ae_final, _T_3619
node _T_3620 = bits(_WIRE_267, 19, 19)
connect _WIRE_266.ae_ptw, _T_3620
node _T_3621 = bits(_WIRE_267, 20, 20)
connect _WIRE_266.g, _T_3621
node _T_3622 = bits(_WIRE_267, 21, 21)
connect _WIRE_266.u, _T_3622
node _T_3623 = bits(_WIRE_267, 41, 22)
connect _WIRE_266.ppn, _T_3623
node _T_3624 = eq(superpage_entries[1].tag_v, _T_3600)
when _T_3624 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
node hv_10 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_10 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3625 = eq(hg_10, UInt<1>(0h0))
node _T_3626 = and(_T_3625, io.sfence.bits.rs1)
when _T_3626 :
node _tagMatch_T_2 = eq(superpage_entries[2].tag_v, hv_10)
node tagMatch_2 = and(superpage_entries[2].valid[0], _tagMatch_T_2)
node _ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0))
node ignore_6 = or(_ignore_T_6, UInt<1>(0h0))
node _T_3627 = xor(superpage_entries[2].tag_vpn, vpn)
node _T_3628 = bits(_T_3627, 26, 18)
node _T_3629 = eq(_T_3628, UInt<1>(0h0))
node _T_3630 = or(ignore_6, _T_3629)
node _T_3631 = and(tagMatch_2, _T_3630)
node _ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1))
node ignore_7 = or(_ignore_T_7, UInt<1>(0h0))
node _T_3632 = xor(superpage_entries[2].tag_vpn, vpn)
node _T_3633 = bits(_T_3632, 17, 9)
node _T_3634 = eq(_T_3633, UInt<1>(0h0))
node _T_3635 = or(ignore_7, _T_3634)
node _T_3636 = and(_T_3631, _T_3635)
node _ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2))
node ignore_8 = or(_ignore_T_8, UInt<1>(0h1))
node _T_3637 = xor(superpage_entries[2].tag_vpn, vpn)
node _T_3638 = bits(_T_3637, 8, 0)
node _T_3639 = eq(_T_3638, UInt<1>(0h0))
node _T_3640 = or(ignore_8, _T_3639)
node _T_3641 = and(_T_3636, _T_3640)
when _T_3641 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
node _T_3642 = xor(superpage_entries[2].tag_vpn, vpn)
node _T_3643 = shr(_T_3642, 18)
node _T_3644 = eq(_T_3643, UInt<1>(0h0))
when _T_3644 :
wire _WIRE_268 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_269 : UInt<42>
connect _WIRE_269, superpage_entries[2].data[0]
node _T_3645 = bits(_WIRE_269, 0, 0)
connect _WIRE_268.fragmented_superpage, _T_3645
node _T_3646 = bits(_WIRE_269, 1, 1)
connect _WIRE_268.c, _T_3646
node _T_3647 = bits(_WIRE_269, 2, 2)
connect _WIRE_268.eff, _T_3647
node _T_3648 = bits(_WIRE_269, 3, 3)
connect _WIRE_268.paa, _T_3648
node _T_3649 = bits(_WIRE_269, 4, 4)
connect _WIRE_268.pal, _T_3649
node _T_3650 = bits(_WIRE_269, 5, 5)
connect _WIRE_268.ppp, _T_3650
node _T_3651 = bits(_WIRE_269, 6, 6)
connect _WIRE_268.pr, _T_3651
node _T_3652 = bits(_WIRE_269, 7, 7)
connect _WIRE_268.px, _T_3652
node _T_3653 = bits(_WIRE_269, 8, 8)
connect _WIRE_268.pw, _T_3653
node _T_3654 = bits(_WIRE_269, 9, 9)
connect _WIRE_268.hr, _T_3654
node _T_3655 = bits(_WIRE_269, 10, 10)
connect _WIRE_268.hx, _T_3655
node _T_3656 = bits(_WIRE_269, 11, 11)
connect _WIRE_268.hw, _T_3656
node _T_3657 = bits(_WIRE_269, 12, 12)
connect _WIRE_268.sr, _T_3657
node _T_3658 = bits(_WIRE_269, 13, 13)
connect _WIRE_268.sx, _T_3658
node _T_3659 = bits(_WIRE_269, 14, 14)
connect _WIRE_268.sw, _T_3659
node _T_3660 = bits(_WIRE_269, 15, 15)
connect _WIRE_268.gf, _T_3660
node _T_3661 = bits(_WIRE_269, 16, 16)
connect _WIRE_268.pf, _T_3661
node _T_3662 = bits(_WIRE_269, 17, 17)
connect _WIRE_268.ae_stage2, _T_3662
node _T_3663 = bits(_WIRE_269, 18, 18)
connect _WIRE_268.ae_final, _T_3663
node _T_3664 = bits(_WIRE_269, 19, 19)
connect _WIRE_268.ae_ptw, _T_3664
node _T_3665 = bits(_WIRE_269, 20, 20)
connect _WIRE_268.g, _T_3665
node _T_3666 = bits(_WIRE_269, 21, 21)
connect _WIRE_268.u, _T_3666
node _T_3667 = bits(_WIRE_269, 41, 22)
connect _WIRE_268.ppn, _T_3667
node _T_3668 = eq(superpage_entries[2].tag_v, hv_10)
node _T_3669 = and(_T_3668, _WIRE_268.fragmented_superpage)
when _T_3669 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
else :
node _T_3670 = eq(hg_10, UInt<1>(0h0))
node _T_3671 = and(_T_3670, io.sfence.bits.rs2)
when _T_3671 :
wire _WIRE_270 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_271 : UInt<42>
connect _WIRE_271, superpage_entries[2].data[0]
node _T_3672 = bits(_WIRE_271, 0, 0)
connect _WIRE_270.fragmented_superpage, _T_3672
node _T_3673 = bits(_WIRE_271, 1, 1)
connect _WIRE_270.c, _T_3673
node _T_3674 = bits(_WIRE_271, 2, 2)
connect _WIRE_270.eff, _T_3674
node _T_3675 = bits(_WIRE_271, 3, 3)
connect _WIRE_270.paa, _T_3675
node _T_3676 = bits(_WIRE_271, 4, 4)
connect _WIRE_270.pal, _T_3676
node _T_3677 = bits(_WIRE_271, 5, 5)
connect _WIRE_270.ppp, _T_3677
node _T_3678 = bits(_WIRE_271, 6, 6)
connect _WIRE_270.pr, _T_3678
node _T_3679 = bits(_WIRE_271, 7, 7)
connect _WIRE_270.px, _T_3679
node _T_3680 = bits(_WIRE_271, 8, 8)
connect _WIRE_270.pw, _T_3680
node _T_3681 = bits(_WIRE_271, 9, 9)
connect _WIRE_270.hr, _T_3681
node _T_3682 = bits(_WIRE_271, 10, 10)
connect _WIRE_270.hx, _T_3682
node _T_3683 = bits(_WIRE_271, 11, 11)
connect _WIRE_270.hw, _T_3683
node _T_3684 = bits(_WIRE_271, 12, 12)
connect _WIRE_270.sr, _T_3684
node _T_3685 = bits(_WIRE_271, 13, 13)
connect _WIRE_270.sx, _T_3685
node _T_3686 = bits(_WIRE_271, 14, 14)
connect _WIRE_270.sw, _T_3686
node _T_3687 = bits(_WIRE_271, 15, 15)
connect _WIRE_270.gf, _T_3687
node _T_3688 = bits(_WIRE_271, 16, 16)
connect _WIRE_270.pf, _T_3688
node _T_3689 = bits(_WIRE_271, 17, 17)
connect _WIRE_270.ae_stage2, _T_3689
node _T_3690 = bits(_WIRE_271, 18, 18)
connect _WIRE_270.ae_final, _T_3690
node _T_3691 = bits(_WIRE_271, 19, 19)
connect _WIRE_270.ae_ptw, _T_3691
node _T_3692 = bits(_WIRE_271, 20, 20)
connect _WIRE_270.g, _T_3692
node _T_3693 = bits(_WIRE_271, 21, 21)
connect _WIRE_270.u, _T_3693
node _T_3694 = bits(_WIRE_271, 41, 22)
connect _WIRE_270.ppn, _T_3694
node _T_3695 = eq(superpage_entries[2].tag_v, hv_10)
node _T_3696 = eq(_WIRE_270.g, UInt<1>(0h0))
node _T_3697 = and(_T_3695, _T_3696)
when _T_3697 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
else :
node _T_3698 = or(hv_10, hg_10)
wire _WIRE_272 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_273 : UInt<42>
connect _WIRE_273, superpage_entries[2].data[0]
node _T_3699 = bits(_WIRE_273, 0, 0)
connect _WIRE_272.fragmented_superpage, _T_3699
node _T_3700 = bits(_WIRE_273, 1, 1)
connect _WIRE_272.c, _T_3700
node _T_3701 = bits(_WIRE_273, 2, 2)
connect _WIRE_272.eff, _T_3701
node _T_3702 = bits(_WIRE_273, 3, 3)
connect _WIRE_272.paa, _T_3702
node _T_3703 = bits(_WIRE_273, 4, 4)
connect _WIRE_272.pal, _T_3703
node _T_3704 = bits(_WIRE_273, 5, 5)
connect _WIRE_272.ppp, _T_3704
node _T_3705 = bits(_WIRE_273, 6, 6)
connect _WIRE_272.pr, _T_3705
node _T_3706 = bits(_WIRE_273, 7, 7)
connect _WIRE_272.px, _T_3706
node _T_3707 = bits(_WIRE_273, 8, 8)
connect _WIRE_272.pw, _T_3707
node _T_3708 = bits(_WIRE_273, 9, 9)
connect _WIRE_272.hr, _T_3708
node _T_3709 = bits(_WIRE_273, 10, 10)
connect _WIRE_272.hx, _T_3709
node _T_3710 = bits(_WIRE_273, 11, 11)
connect _WIRE_272.hw, _T_3710
node _T_3711 = bits(_WIRE_273, 12, 12)
connect _WIRE_272.sr, _T_3711
node _T_3712 = bits(_WIRE_273, 13, 13)
connect _WIRE_272.sx, _T_3712
node _T_3713 = bits(_WIRE_273, 14, 14)
connect _WIRE_272.sw, _T_3713
node _T_3714 = bits(_WIRE_273, 15, 15)
connect _WIRE_272.gf, _T_3714
node _T_3715 = bits(_WIRE_273, 16, 16)
connect _WIRE_272.pf, _T_3715
node _T_3716 = bits(_WIRE_273, 17, 17)
connect _WIRE_272.ae_stage2, _T_3716
node _T_3717 = bits(_WIRE_273, 18, 18)
connect _WIRE_272.ae_final, _T_3717
node _T_3718 = bits(_WIRE_273, 19, 19)
connect _WIRE_272.ae_ptw, _T_3718
node _T_3719 = bits(_WIRE_273, 20, 20)
connect _WIRE_272.g, _T_3719
node _T_3720 = bits(_WIRE_273, 21, 21)
connect _WIRE_272.u, _T_3720
node _T_3721 = bits(_WIRE_273, 41, 22)
connect _WIRE_272.ppn, _T_3721
node _T_3722 = eq(superpage_entries[2].tag_v, _T_3698)
when _T_3722 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
node hv_11 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_11 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3723 = eq(hg_11, UInt<1>(0h0))
node _T_3724 = and(_T_3723, io.sfence.bits.rs1)
when _T_3724 :
node _tagMatch_T_3 = eq(superpage_entries[3].tag_v, hv_11)
node tagMatch_3 = and(superpage_entries[3].valid[0], _tagMatch_T_3)
node _ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0))
node ignore_9 = or(_ignore_T_9, UInt<1>(0h0))
node _T_3725 = xor(superpage_entries[3].tag_vpn, vpn)
node _T_3726 = bits(_T_3725, 26, 18)
node _T_3727 = eq(_T_3726, UInt<1>(0h0))
node _T_3728 = or(ignore_9, _T_3727)
node _T_3729 = and(tagMatch_3, _T_3728)
node _ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1))
node ignore_10 = or(_ignore_T_10, UInt<1>(0h0))
node _T_3730 = xor(superpage_entries[3].tag_vpn, vpn)
node _T_3731 = bits(_T_3730, 17, 9)
node _T_3732 = eq(_T_3731, UInt<1>(0h0))
node _T_3733 = or(ignore_10, _T_3732)
node _T_3734 = and(_T_3729, _T_3733)
node _ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2))
node ignore_11 = or(_ignore_T_11, UInt<1>(0h1))
node _T_3735 = xor(superpage_entries[3].tag_vpn, vpn)
node _T_3736 = bits(_T_3735, 8, 0)
node _T_3737 = eq(_T_3736, UInt<1>(0h0))
node _T_3738 = or(ignore_11, _T_3737)
node _T_3739 = and(_T_3734, _T_3738)
when _T_3739 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
node _T_3740 = xor(superpage_entries[3].tag_vpn, vpn)
node _T_3741 = shr(_T_3740, 18)
node _T_3742 = eq(_T_3741, UInt<1>(0h0))
when _T_3742 :
wire _WIRE_274 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_275 : UInt<42>
connect _WIRE_275, superpage_entries[3].data[0]
node _T_3743 = bits(_WIRE_275, 0, 0)
connect _WIRE_274.fragmented_superpage, _T_3743
node _T_3744 = bits(_WIRE_275, 1, 1)
connect _WIRE_274.c, _T_3744
node _T_3745 = bits(_WIRE_275, 2, 2)
connect _WIRE_274.eff, _T_3745
node _T_3746 = bits(_WIRE_275, 3, 3)
connect _WIRE_274.paa, _T_3746
node _T_3747 = bits(_WIRE_275, 4, 4)
connect _WIRE_274.pal, _T_3747
node _T_3748 = bits(_WIRE_275, 5, 5)
connect _WIRE_274.ppp, _T_3748
node _T_3749 = bits(_WIRE_275, 6, 6)
connect _WIRE_274.pr, _T_3749
node _T_3750 = bits(_WIRE_275, 7, 7)
connect _WIRE_274.px, _T_3750
node _T_3751 = bits(_WIRE_275, 8, 8)
connect _WIRE_274.pw, _T_3751
node _T_3752 = bits(_WIRE_275, 9, 9)
connect _WIRE_274.hr, _T_3752
node _T_3753 = bits(_WIRE_275, 10, 10)
connect _WIRE_274.hx, _T_3753
node _T_3754 = bits(_WIRE_275, 11, 11)
connect _WIRE_274.hw, _T_3754
node _T_3755 = bits(_WIRE_275, 12, 12)
connect _WIRE_274.sr, _T_3755
node _T_3756 = bits(_WIRE_275, 13, 13)
connect _WIRE_274.sx, _T_3756
node _T_3757 = bits(_WIRE_275, 14, 14)
connect _WIRE_274.sw, _T_3757
node _T_3758 = bits(_WIRE_275, 15, 15)
connect _WIRE_274.gf, _T_3758
node _T_3759 = bits(_WIRE_275, 16, 16)
connect _WIRE_274.pf, _T_3759
node _T_3760 = bits(_WIRE_275, 17, 17)
connect _WIRE_274.ae_stage2, _T_3760
node _T_3761 = bits(_WIRE_275, 18, 18)
connect _WIRE_274.ae_final, _T_3761
node _T_3762 = bits(_WIRE_275, 19, 19)
connect _WIRE_274.ae_ptw, _T_3762
node _T_3763 = bits(_WIRE_275, 20, 20)
connect _WIRE_274.g, _T_3763
node _T_3764 = bits(_WIRE_275, 21, 21)
connect _WIRE_274.u, _T_3764
node _T_3765 = bits(_WIRE_275, 41, 22)
connect _WIRE_274.ppn, _T_3765
node _T_3766 = eq(superpage_entries[3].tag_v, hv_11)
node _T_3767 = and(_T_3766, _WIRE_274.fragmented_superpage)
when _T_3767 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
else :
node _T_3768 = eq(hg_11, UInt<1>(0h0))
node _T_3769 = and(_T_3768, io.sfence.bits.rs2)
when _T_3769 :
wire _WIRE_276 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_277 : UInt<42>
connect _WIRE_277, superpage_entries[3].data[0]
node _T_3770 = bits(_WIRE_277, 0, 0)
connect _WIRE_276.fragmented_superpage, _T_3770
node _T_3771 = bits(_WIRE_277, 1, 1)
connect _WIRE_276.c, _T_3771
node _T_3772 = bits(_WIRE_277, 2, 2)
connect _WIRE_276.eff, _T_3772
node _T_3773 = bits(_WIRE_277, 3, 3)
connect _WIRE_276.paa, _T_3773
node _T_3774 = bits(_WIRE_277, 4, 4)
connect _WIRE_276.pal, _T_3774
node _T_3775 = bits(_WIRE_277, 5, 5)
connect _WIRE_276.ppp, _T_3775
node _T_3776 = bits(_WIRE_277, 6, 6)
connect _WIRE_276.pr, _T_3776
node _T_3777 = bits(_WIRE_277, 7, 7)
connect _WIRE_276.px, _T_3777
node _T_3778 = bits(_WIRE_277, 8, 8)
connect _WIRE_276.pw, _T_3778
node _T_3779 = bits(_WIRE_277, 9, 9)
connect _WIRE_276.hr, _T_3779
node _T_3780 = bits(_WIRE_277, 10, 10)
connect _WIRE_276.hx, _T_3780
node _T_3781 = bits(_WIRE_277, 11, 11)
connect _WIRE_276.hw, _T_3781
node _T_3782 = bits(_WIRE_277, 12, 12)
connect _WIRE_276.sr, _T_3782
node _T_3783 = bits(_WIRE_277, 13, 13)
connect _WIRE_276.sx, _T_3783
node _T_3784 = bits(_WIRE_277, 14, 14)
connect _WIRE_276.sw, _T_3784
node _T_3785 = bits(_WIRE_277, 15, 15)
connect _WIRE_276.gf, _T_3785
node _T_3786 = bits(_WIRE_277, 16, 16)
connect _WIRE_276.pf, _T_3786
node _T_3787 = bits(_WIRE_277, 17, 17)
connect _WIRE_276.ae_stage2, _T_3787
node _T_3788 = bits(_WIRE_277, 18, 18)
connect _WIRE_276.ae_final, _T_3788
node _T_3789 = bits(_WIRE_277, 19, 19)
connect _WIRE_276.ae_ptw, _T_3789
node _T_3790 = bits(_WIRE_277, 20, 20)
connect _WIRE_276.g, _T_3790
node _T_3791 = bits(_WIRE_277, 21, 21)
connect _WIRE_276.u, _T_3791
node _T_3792 = bits(_WIRE_277, 41, 22)
connect _WIRE_276.ppn, _T_3792
node _T_3793 = eq(superpage_entries[3].tag_v, hv_11)
node _T_3794 = eq(_WIRE_276.g, UInt<1>(0h0))
node _T_3795 = and(_T_3793, _T_3794)
when _T_3795 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
else :
node _T_3796 = or(hv_11, hg_11)
wire _WIRE_278 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_279 : UInt<42>
connect _WIRE_279, superpage_entries[3].data[0]
node _T_3797 = bits(_WIRE_279, 0, 0)
connect _WIRE_278.fragmented_superpage, _T_3797
node _T_3798 = bits(_WIRE_279, 1, 1)
connect _WIRE_278.c, _T_3798
node _T_3799 = bits(_WIRE_279, 2, 2)
connect _WIRE_278.eff, _T_3799
node _T_3800 = bits(_WIRE_279, 3, 3)
connect _WIRE_278.paa, _T_3800
node _T_3801 = bits(_WIRE_279, 4, 4)
connect _WIRE_278.pal, _T_3801
node _T_3802 = bits(_WIRE_279, 5, 5)
connect _WIRE_278.ppp, _T_3802
node _T_3803 = bits(_WIRE_279, 6, 6)
connect _WIRE_278.pr, _T_3803
node _T_3804 = bits(_WIRE_279, 7, 7)
connect _WIRE_278.px, _T_3804
node _T_3805 = bits(_WIRE_279, 8, 8)
connect _WIRE_278.pw, _T_3805
node _T_3806 = bits(_WIRE_279, 9, 9)
connect _WIRE_278.hr, _T_3806
node _T_3807 = bits(_WIRE_279, 10, 10)
connect _WIRE_278.hx, _T_3807
node _T_3808 = bits(_WIRE_279, 11, 11)
connect _WIRE_278.hw, _T_3808
node _T_3809 = bits(_WIRE_279, 12, 12)
connect _WIRE_278.sr, _T_3809
node _T_3810 = bits(_WIRE_279, 13, 13)
connect _WIRE_278.sx, _T_3810
node _T_3811 = bits(_WIRE_279, 14, 14)
connect _WIRE_278.sw, _T_3811
node _T_3812 = bits(_WIRE_279, 15, 15)
connect _WIRE_278.gf, _T_3812
node _T_3813 = bits(_WIRE_279, 16, 16)
connect _WIRE_278.pf, _T_3813
node _T_3814 = bits(_WIRE_279, 17, 17)
connect _WIRE_278.ae_stage2, _T_3814
node _T_3815 = bits(_WIRE_279, 18, 18)
connect _WIRE_278.ae_final, _T_3815
node _T_3816 = bits(_WIRE_279, 19, 19)
connect _WIRE_278.ae_ptw, _T_3816
node _T_3817 = bits(_WIRE_279, 20, 20)
connect _WIRE_278.g, _T_3817
node _T_3818 = bits(_WIRE_279, 21, 21)
connect _WIRE_278.u, _T_3818
node _T_3819 = bits(_WIRE_279, 41, 22)
connect _WIRE_278.ppn, _T_3819
node _T_3820 = eq(superpage_entries[3].tag_v, _T_3796)
when _T_3820 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
node hv_12 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_12 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3821 = eq(hg_12, UInt<1>(0h0))
node _T_3822 = and(_T_3821, io.sfence.bits.rs1)
when _T_3822 :
node _tagMatch_T_4 = eq(special_entry.tag_v, hv_12)
node tagMatch_4 = and(special_entry.valid[0], _tagMatch_T_4)
node _ignore_T_12 = lt(special_entry.level, UInt<1>(0h0))
node ignore_12 = or(_ignore_T_12, UInt<1>(0h0))
node _T_3823 = xor(special_entry.tag_vpn, vpn)
node _T_3824 = bits(_T_3823, 26, 18)
node _T_3825 = eq(_T_3824, UInt<1>(0h0))
node _T_3826 = or(ignore_12, _T_3825)
node _T_3827 = and(tagMatch_4, _T_3826)
node _ignore_T_13 = lt(special_entry.level, UInt<1>(0h1))
node ignore_13 = or(_ignore_T_13, UInt<1>(0h0))
node _T_3828 = xor(special_entry.tag_vpn, vpn)
node _T_3829 = bits(_T_3828, 17, 9)
node _T_3830 = eq(_T_3829, UInt<1>(0h0))
node _T_3831 = or(ignore_13, _T_3830)
node _T_3832 = and(_T_3827, _T_3831)
node _ignore_T_14 = lt(special_entry.level, UInt<2>(0h2))
node ignore_14 = or(_ignore_T_14, UInt<1>(0h0))
node _T_3833 = xor(special_entry.tag_vpn, vpn)
node _T_3834 = bits(_T_3833, 8, 0)
node _T_3835 = eq(_T_3834, UInt<1>(0h0))
node _T_3836 = or(ignore_14, _T_3835)
node _T_3837 = and(_T_3832, _T_3836)
when _T_3837 :
connect special_entry.valid[0], UInt<1>(0h0)
node _T_3838 = xor(special_entry.tag_vpn, vpn)
node _T_3839 = shr(_T_3838, 18)
node _T_3840 = eq(_T_3839, UInt<1>(0h0))
when _T_3840 :
wire _WIRE_280 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_281 : UInt<42>
connect _WIRE_281, special_entry.data[0]
node _T_3841 = bits(_WIRE_281, 0, 0)
connect _WIRE_280.fragmented_superpage, _T_3841
node _T_3842 = bits(_WIRE_281, 1, 1)
connect _WIRE_280.c, _T_3842
node _T_3843 = bits(_WIRE_281, 2, 2)
connect _WIRE_280.eff, _T_3843
node _T_3844 = bits(_WIRE_281, 3, 3)
connect _WIRE_280.paa, _T_3844
node _T_3845 = bits(_WIRE_281, 4, 4)
connect _WIRE_280.pal, _T_3845
node _T_3846 = bits(_WIRE_281, 5, 5)
connect _WIRE_280.ppp, _T_3846
node _T_3847 = bits(_WIRE_281, 6, 6)
connect _WIRE_280.pr, _T_3847
node _T_3848 = bits(_WIRE_281, 7, 7)
connect _WIRE_280.px, _T_3848
node _T_3849 = bits(_WIRE_281, 8, 8)
connect _WIRE_280.pw, _T_3849
node _T_3850 = bits(_WIRE_281, 9, 9)
connect _WIRE_280.hr, _T_3850
node _T_3851 = bits(_WIRE_281, 10, 10)
connect _WIRE_280.hx, _T_3851
node _T_3852 = bits(_WIRE_281, 11, 11)
connect _WIRE_280.hw, _T_3852
node _T_3853 = bits(_WIRE_281, 12, 12)
connect _WIRE_280.sr, _T_3853
node _T_3854 = bits(_WIRE_281, 13, 13)
connect _WIRE_280.sx, _T_3854
node _T_3855 = bits(_WIRE_281, 14, 14)
connect _WIRE_280.sw, _T_3855
node _T_3856 = bits(_WIRE_281, 15, 15)
connect _WIRE_280.gf, _T_3856
node _T_3857 = bits(_WIRE_281, 16, 16)
connect _WIRE_280.pf, _T_3857
node _T_3858 = bits(_WIRE_281, 17, 17)
connect _WIRE_280.ae_stage2, _T_3858
node _T_3859 = bits(_WIRE_281, 18, 18)
connect _WIRE_280.ae_final, _T_3859
node _T_3860 = bits(_WIRE_281, 19, 19)
connect _WIRE_280.ae_ptw, _T_3860
node _T_3861 = bits(_WIRE_281, 20, 20)
connect _WIRE_280.g, _T_3861
node _T_3862 = bits(_WIRE_281, 21, 21)
connect _WIRE_280.u, _T_3862
node _T_3863 = bits(_WIRE_281, 41, 22)
connect _WIRE_280.ppn, _T_3863
node _T_3864 = eq(special_entry.tag_v, hv_12)
node _T_3865 = and(_T_3864, _WIRE_280.fragmented_superpage)
when _T_3865 :
connect special_entry.valid[0], UInt<1>(0h0)
else :
node _T_3866 = eq(hg_12, UInt<1>(0h0))
node _T_3867 = and(_T_3866, io.sfence.bits.rs2)
when _T_3867 :
wire _WIRE_282 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_283 : UInt<42>
connect _WIRE_283, special_entry.data[0]
node _T_3868 = bits(_WIRE_283, 0, 0)
connect _WIRE_282.fragmented_superpage, _T_3868
node _T_3869 = bits(_WIRE_283, 1, 1)
connect _WIRE_282.c, _T_3869
node _T_3870 = bits(_WIRE_283, 2, 2)
connect _WIRE_282.eff, _T_3870
node _T_3871 = bits(_WIRE_283, 3, 3)
connect _WIRE_282.paa, _T_3871
node _T_3872 = bits(_WIRE_283, 4, 4)
connect _WIRE_282.pal, _T_3872
node _T_3873 = bits(_WIRE_283, 5, 5)
connect _WIRE_282.ppp, _T_3873
node _T_3874 = bits(_WIRE_283, 6, 6)
connect _WIRE_282.pr, _T_3874
node _T_3875 = bits(_WIRE_283, 7, 7)
connect _WIRE_282.px, _T_3875
node _T_3876 = bits(_WIRE_283, 8, 8)
connect _WIRE_282.pw, _T_3876
node _T_3877 = bits(_WIRE_283, 9, 9)
connect _WIRE_282.hr, _T_3877
node _T_3878 = bits(_WIRE_283, 10, 10)
connect _WIRE_282.hx, _T_3878
node _T_3879 = bits(_WIRE_283, 11, 11)
connect _WIRE_282.hw, _T_3879
node _T_3880 = bits(_WIRE_283, 12, 12)
connect _WIRE_282.sr, _T_3880
node _T_3881 = bits(_WIRE_283, 13, 13)
connect _WIRE_282.sx, _T_3881
node _T_3882 = bits(_WIRE_283, 14, 14)
connect _WIRE_282.sw, _T_3882
node _T_3883 = bits(_WIRE_283, 15, 15)
connect _WIRE_282.gf, _T_3883
node _T_3884 = bits(_WIRE_283, 16, 16)
connect _WIRE_282.pf, _T_3884
node _T_3885 = bits(_WIRE_283, 17, 17)
connect _WIRE_282.ae_stage2, _T_3885
node _T_3886 = bits(_WIRE_283, 18, 18)
connect _WIRE_282.ae_final, _T_3886
node _T_3887 = bits(_WIRE_283, 19, 19)
connect _WIRE_282.ae_ptw, _T_3887
node _T_3888 = bits(_WIRE_283, 20, 20)
connect _WIRE_282.g, _T_3888
node _T_3889 = bits(_WIRE_283, 21, 21)
connect _WIRE_282.u, _T_3889
node _T_3890 = bits(_WIRE_283, 41, 22)
connect _WIRE_282.ppn, _T_3890
node _T_3891 = eq(special_entry.tag_v, hv_12)
node _T_3892 = eq(_WIRE_282.g, UInt<1>(0h0))
node _T_3893 = and(_T_3891, _T_3892)
when _T_3893 :
connect special_entry.valid[0], UInt<1>(0h0)
else :
node _T_3894 = or(hv_12, hg_12)
wire _WIRE_284 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_285 : UInt<42>
connect _WIRE_285, special_entry.data[0]
node _T_3895 = bits(_WIRE_285, 0, 0)
connect _WIRE_284.fragmented_superpage, _T_3895
node _T_3896 = bits(_WIRE_285, 1, 1)
connect _WIRE_284.c, _T_3896
node _T_3897 = bits(_WIRE_285, 2, 2)
connect _WIRE_284.eff, _T_3897
node _T_3898 = bits(_WIRE_285, 3, 3)
connect _WIRE_284.paa, _T_3898
node _T_3899 = bits(_WIRE_285, 4, 4)
connect _WIRE_284.pal, _T_3899
node _T_3900 = bits(_WIRE_285, 5, 5)
connect _WIRE_284.ppp, _T_3900
node _T_3901 = bits(_WIRE_285, 6, 6)
connect _WIRE_284.pr, _T_3901
node _T_3902 = bits(_WIRE_285, 7, 7)
connect _WIRE_284.px, _T_3902
node _T_3903 = bits(_WIRE_285, 8, 8)
connect _WIRE_284.pw, _T_3903
node _T_3904 = bits(_WIRE_285, 9, 9)
connect _WIRE_284.hr, _T_3904
node _T_3905 = bits(_WIRE_285, 10, 10)
connect _WIRE_284.hx, _T_3905
node _T_3906 = bits(_WIRE_285, 11, 11)
connect _WIRE_284.hw, _T_3906
node _T_3907 = bits(_WIRE_285, 12, 12)
connect _WIRE_284.sr, _T_3907
node _T_3908 = bits(_WIRE_285, 13, 13)
connect _WIRE_284.sx, _T_3908
node _T_3909 = bits(_WIRE_285, 14, 14)
connect _WIRE_284.sw, _T_3909
node _T_3910 = bits(_WIRE_285, 15, 15)
connect _WIRE_284.gf, _T_3910
node _T_3911 = bits(_WIRE_285, 16, 16)
connect _WIRE_284.pf, _T_3911
node _T_3912 = bits(_WIRE_285, 17, 17)
connect _WIRE_284.ae_stage2, _T_3912
node _T_3913 = bits(_WIRE_285, 18, 18)
connect _WIRE_284.ae_final, _T_3913
node _T_3914 = bits(_WIRE_285, 19, 19)
connect _WIRE_284.ae_ptw, _T_3914
node _T_3915 = bits(_WIRE_285, 20, 20)
connect _WIRE_284.g, _T_3915
node _T_3916 = bits(_WIRE_285, 21, 21)
connect _WIRE_284.u, _T_3916
node _T_3917 = bits(_WIRE_285, 41, 22)
connect _WIRE_284.ppn, _T_3917
node _T_3918 = eq(special_entry.tag_v, _T_3894)
when _T_3918 :
connect special_entry.valid[0], UInt<1>(0h0)
node _T_3919 = and(io.req.ready, io.req.valid)
node _T_3920 = and(_T_3919, vsatp_mode_mismatch)
when _T_3920 :
wire _WIRE_286 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_287 : UInt<42>
connect _WIRE_287, sectored_entries[0][0].data[0]
node _T_3921 = bits(_WIRE_287, 0, 0)
connect _WIRE_286.fragmented_superpage, _T_3921
node _T_3922 = bits(_WIRE_287, 1, 1)
connect _WIRE_286.c, _T_3922
node _T_3923 = bits(_WIRE_287, 2, 2)
connect _WIRE_286.eff, _T_3923
node _T_3924 = bits(_WIRE_287, 3, 3)
connect _WIRE_286.paa, _T_3924
node _T_3925 = bits(_WIRE_287, 4, 4)
connect _WIRE_286.pal, _T_3925
node _T_3926 = bits(_WIRE_287, 5, 5)
connect _WIRE_286.ppp, _T_3926
node _T_3927 = bits(_WIRE_287, 6, 6)
connect _WIRE_286.pr, _T_3927
node _T_3928 = bits(_WIRE_287, 7, 7)
connect _WIRE_286.px, _T_3928
node _T_3929 = bits(_WIRE_287, 8, 8)
connect _WIRE_286.pw, _T_3929
node _T_3930 = bits(_WIRE_287, 9, 9)
connect _WIRE_286.hr, _T_3930
node _T_3931 = bits(_WIRE_287, 10, 10)
connect _WIRE_286.hx, _T_3931
node _T_3932 = bits(_WIRE_287, 11, 11)
connect _WIRE_286.hw, _T_3932
node _T_3933 = bits(_WIRE_287, 12, 12)
connect _WIRE_286.sr, _T_3933
node _T_3934 = bits(_WIRE_287, 13, 13)
connect _WIRE_286.sx, _T_3934
node _T_3935 = bits(_WIRE_287, 14, 14)
connect _WIRE_286.sw, _T_3935
node _T_3936 = bits(_WIRE_287, 15, 15)
connect _WIRE_286.gf, _T_3936
node _T_3937 = bits(_WIRE_287, 16, 16)
connect _WIRE_286.pf, _T_3937
node _T_3938 = bits(_WIRE_287, 17, 17)
connect _WIRE_286.ae_stage2, _T_3938
node _T_3939 = bits(_WIRE_287, 18, 18)
connect _WIRE_286.ae_final, _T_3939
node _T_3940 = bits(_WIRE_287, 19, 19)
connect _WIRE_286.ae_ptw, _T_3940
node _T_3941 = bits(_WIRE_287, 20, 20)
connect _WIRE_286.g, _T_3941
node _T_3942 = bits(_WIRE_287, 21, 21)
connect _WIRE_286.u, _T_3942
node _T_3943 = bits(_WIRE_287, 41, 22)
connect _WIRE_286.ppn, _T_3943
wire _WIRE_288 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_289 : UInt<42>
connect _WIRE_289, sectored_entries[0][0].data[1]
node _T_3944 = bits(_WIRE_289, 0, 0)
connect _WIRE_288.fragmented_superpage, _T_3944
node _T_3945 = bits(_WIRE_289, 1, 1)
connect _WIRE_288.c, _T_3945
node _T_3946 = bits(_WIRE_289, 2, 2)
connect _WIRE_288.eff, _T_3946
node _T_3947 = bits(_WIRE_289, 3, 3)
connect _WIRE_288.paa, _T_3947
node _T_3948 = bits(_WIRE_289, 4, 4)
connect _WIRE_288.pal, _T_3948
node _T_3949 = bits(_WIRE_289, 5, 5)
connect _WIRE_288.ppp, _T_3949
node _T_3950 = bits(_WIRE_289, 6, 6)
connect _WIRE_288.pr, _T_3950
node _T_3951 = bits(_WIRE_289, 7, 7)
connect _WIRE_288.px, _T_3951
node _T_3952 = bits(_WIRE_289, 8, 8)
connect _WIRE_288.pw, _T_3952
node _T_3953 = bits(_WIRE_289, 9, 9)
connect _WIRE_288.hr, _T_3953
node _T_3954 = bits(_WIRE_289, 10, 10)
connect _WIRE_288.hx, _T_3954
node _T_3955 = bits(_WIRE_289, 11, 11)
connect _WIRE_288.hw, _T_3955
node _T_3956 = bits(_WIRE_289, 12, 12)
connect _WIRE_288.sr, _T_3956
node _T_3957 = bits(_WIRE_289, 13, 13)
connect _WIRE_288.sx, _T_3957
node _T_3958 = bits(_WIRE_289, 14, 14)
connect _WIRE_288.sw, _T_3958
node _T_3959 = bits(_WIRE_289, 15, 15)
connect _WIRE_288.gf, _T_3959
node _T_3960 = bits(_WIRE_289, 16, 16)
connect _WIRE_288.pf, _T_3960
node _T_3961 = bits(_WIRE_289, 17, 17)
connect _WIRE_288.ae_stage2, _T_3961
node _T_3962 = bits(_WIRE_289, 18, 18)
connect _WIRE_288.ae_final, _T_3962
node _T_3963 = bits(_WIRE_289, 19, 19)
connect _WIRE_288.ae_ptw, _T_3963
node _T_3964 = bits(_WIRE_289, 20, 20)
connect _WIRE_288.g, _T_3964
node _T_3965 = bits(_WIRE_289, 21, 21)
connect _WIRE_288.u, _T_3965
node _T_3966 = bits(_WIRE_289, 41, 22)
connect _WIRE_288.ppn, _T_3966
wire _WIRE_290 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_291 : UInt<42>
connect _WIRE_291, sectored_entries[0][0].data[2]
node _T_3967 = bits(_WIRE_291, 0, 0)
connect _WIRE_290.fragmented_superpage, _T_3967
node _T_3968 = bits(_WIRE_291, 1, 1)
connect _WIRE_290.c, _T_3968
node _T_3969 = bits(_WIRE_291, 2, 2)
connect _WIRE_290.eff, _T_3969
node _T_3970 = bits(_WIRE_291, 3, 3)
connect _WIRE_290.paa, _T_3970
node _T_3971 = bits(_WIRE_291, 4, 4)
connect _WIRE_290.pal, _T_3971
node _T_3972 = bits(_WIRE_291, 5, 5)
connect _WIRE_290.ppp, _T_3972
node _T_3973 = bits(_WIRE_291, 6, 6)
connect _WIRE_290.pr, _T_3973
node _T_3974 = bits(_WIRE_291, 7, 7)
connect _WIRE_290.px, _T_3974
node _T_3975 = bits(_WIRE_291, 8, 8)
connect _WIRE_290.pw, _T_3975
node _T_3976 = bits(_WIRE_291, 9, 9)
connect _WIRE_290.hr, _T_3976
node _T_3977 = bits(_WIRE_291, 10, 10)
connect _WIRE_290.hx, _T_3977
node _T_3978 = bits(_WIRE_291, 11, 11)
connect _WIRE_290.hw, _T_3978
node _T_3979 = bits(_WIRE_291, 12, 12)
connect _WIRE_290.sr, _T_3979
node _T_3980 = bits(_WIRE_291, 13, 13)
connect _WIRE_290.sx, _T_3980
node _T_3981 = bits(_WIRE_291, 14, 14)
connect _WIRE_290.sw, _T_3981
node _T_3982 = bits(_WIRE_291, 15, 15)
connect _WIRE_290.gf, _T_3982
node _T_3983 = bits(_WIRE_291, 16, 16)
connect _WIRE_290.pf, _T_3983
node _T_3984 = bits(_WIRE_291, 17, 17)
connect _WIRE_290.ae_stage2, _T_3984
node _T_3985 = bits(_WIRE_291, 18, 18)
connect _WIRE_290.ae_final, _T_3985
node _T_3986 = bits(_WIRE_291, 19, 19)
connect _WIRE_290.ae_ptw, _T_3986
node _T_3987 = bits(_WIRE_291, 20, 20)
connect _WIRE_290.g, _T_3987
node _T_3988 = bits(_WIRE_291, 21, 21)
connect _WIRE_290.u, _T_3988
node _T_3989 = bits(_WIRE_291, 41, 22)
connect _WIRE_290.ppn, _T_3989
wire _WIRE_292 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_293 : UInt<42>
connect _WIRE_293, sectored_entries[0][0].data[3]
node _T_3990 = bits(_WIRE_293, 0, 0)
connect _WIRE_292.fragmented_superpage, _T_3990
node _T_3991 = bits(_WIRE_293, 1, 1)
connect _WIRE_292.c, _T_3991
node _T_3992 = bits(_WIRE_293, 2, 2)
connect _WIRE_292.eff, _T_3992
node _T_3993 = bits(_WIRE_293, 3, 3)
connect _WIRE_292.paa, _T_3993
node _T_3994 = bits(_WIRE_293, 4, 4)
connect _WIRE_292.pal, _T_3994
node _T_3995 = bits(_WIRE_293, 5, 5)
connect _WIRE_292.ppp, _T_3995
node _T_3996 = bits(_WIRE_293, 6, 6)
connect _WIRE_292.pr, _T_3996
node _T_3997 = bits(_WIRE_293, 7, 7)
connect _WIRE_292.px, _T_3997
node _T_3998 = bits(_WIRE_293, 8, 8)
connect _WIRE_292.pw, _T_3998
node _T_3999 = bits(_WIRE_293, 9, 9)
connect _WIRE_292.hr, _T_3999
node _T_4000 = bits(_WIRE_293, 10, 10)
connect _WIRE_292.hx, _T_4000
node _T_4001 = bits(_WIRE_293, 11, 11)
connect _WIRE_292.hw, _T_4001
node _T_4002 = bits(_WIRE_293, 12, 12)
connect _WIRE_292.sr, _T_4002
node _T_4003 = bits(_WIRE_293, 13, 13)
connect _WIRE_292.sx, _T_4003
node _T_4004 = bits(_WIRE_293, 14, 14)
connect _WIRE_292.sw, _T_4004
node _T_4005 = bits(_WIRE_293, 15, 15)
connect _WIRE_292.gf, _T_4005
node _T_4006 = bits(_WIRE_293, 16, 16)
connect _WIRE_292.pf, _T_4006
node _T_4007 = bits(_WIRE_293, 17, 17)
connect _WIRE_292.ae_stage2, _T_4007
node _T_4008 = bits(_WIRE_293, 18, 18)
connect _WIRE_292.ae_final, _T_4008
node _T_4009 = bits(_WIRE_293, 19, 19)
connect _WIRE_292.ae_ptw, _T_4009
node _T_4010 = bits(_WIRE_293, 20, 20)
connect _WIRE_292.g, _T_4010
node _T_4011 = bits(_WIRE_293, 21, 21)
connect _WIRE_292.u, _T_4011
node _T_4012 = bits(_WIRE_293, 41, 22)
connect _WIRE_292.ppn, _T_4012
node _T_4013 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1))
when _T_4013 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_4014 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1))
when _T_4014 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_4015 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1))
when _T_4015 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_4016 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1))
when _T_4016 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
wire _WIRE_294 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_295 : UInt<42>
connect _WIRE_295, sectored_entries[0][1].data[0]
node _T_4017 = bits(_WIRE_295, 0, 0)
connect _WIRE_294.fragmented_superpage, _T_4017
node _T_4018 = bits(_WIRE_295, 1, 1)
connect _WIRE_294.c, _T_4018
node _T_4019 = bits(_WIRE_295, 2, 2)
connect _WIRE_294.eff, _T_4019
node _T_4020 = bits(_WIRE_295, 3, 3)
connect _WIRE_294.paa, _T_4020
node _T_4021 = bits(_WIRE_295, 4, 4)
connect _WIRE_294.pal, _T_4021
node _T_4022 = bits(_WIRE_295, 5, 5)
connect _WIRE_294.ppp, _T_4022
node _T_4023 = bits(_WIRE_295, 6, 6)
connect _WIRE_294.pr, _T_4023
node _T_4024 = bits(_WIRE_295, 7, 7)
connect _WIRE_294.px, _T_4024
node _T_4025 = bits(_WIRE_295, 8, 8)
connect _WIRE_294.pw, _T_4025
node _T_4026 = bits(_WIRE_295, 9, 9)
connect _WIRE_294.hr, _T_4026
node _T_4027 = bits(_WIRE_295, 10, 10)
connect _WIRE_294.hx, _T_4027
node _T_4028 = bits(_WIRE_295, 11, 11)
connect _WIRE_294.hw, _T_4028
node _T_4029 = bits(_WIRE_295, 12, 12)
connect _WIRE_294.sr, _T_4029
node _T_4030 = bits(_WIRE_295, 13, 13)
connect _WIRE_294.sx, _T_4030
node _T_4031 = bits(_WIRE_295, 14, 14)
connect _WIRE_294.sw, _T_4031
node _T_4032 = bits(_WIRE_295, 15, 15)
connect _WIRE_294.gf, _T_4032
node _T_4033 = bits(_WIRE_295, 16, 16)
connect _WIRE_294.pf, _T_4033
node _T_4034 = bits(_WIRE_295, 17, 17)
connect _WIRE_294.ae_stage2, _T_4034
node _T_4035 = bits(_WIRE_295, 18, 18)
connect _WIRE_294.ae_final, _T_4035
node _T_4036 = bits(_WIRE_295, 19, 19)
connect _WIRE_294.ae_ptw, _T_4036
node _T_4037 = bits(_WIRE_295, 20, 20)
connect _WIRE_294.g, _T_4037
node _T_4038 = bits(_WIRE_295, 21, 21)
connect _WIRE_294.u, _T_4038
node _T_4039 = bits(_WIRE_295, 41, 22)
connect _WIRE_294.ppn, _T_4039
wire _WIRE_296 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_297 : UInt<42>
connect _WIRE_297, sectored_entries[0][1].data[1]
node _T_4040 = bits(_WIRE_297, 0, 0)
connect _WIRE_296.fragmented_superpage, _T_4040
node _T_4041 = bits(_WIRE_297, 1, 1)
connect _WIRE_296.c, _T_4041
node _T_4042 = bits(_WIRE_297, 2, 2)
connect _WIRE_296.eff, _T_4042
node _T_4043 = bits(_WIRE_297, 3, 3)
connect _WIRE_296.paa, _T_4043
node _T_4044 = bits(_WIRE_297, 4, 4)
connect _WIRE_296.pal, _T_4044
node _T_4045 = bits(_WIRE_297, 5, 5)
connect _WIRE_296.ppp, _T_4045
node _T_4046 = bits(_WIRE_297, 6, 6)
connect _WIRE_296.pr, _T_4046
node _T_4047 = bits(_WIRE_297, 7, 7)
connect _WIRE_296.px, _T_4047
node _T_4048 = bits(_WIRE_297, 8, 8)
connect _WIRE_296.pw, _T_4048
node _T_4049 = bits(_WIRE_297, 9, 9)
connect _WIRE_296.hr, _T_4049
node _T_4050 = bits(_WIRE_297, 10, 10)
connect _WIRE_296.hx, _T_4050
node _T_4051 = bits(_WIRE_297, 11, 11)
connect _WIRE_296.hw, _T_4051
node _T_4052 = bits(_WIRE_297, 12, 12)
connect _WIRE_296.sr, _T_4052
node _T_4053 = bits(_WIRE_297, 13, 13)
connect _WIRE_296.sx, _T_4053
node _T_4054 = bits(_WIRE_297, 14, 14)
connect _WIRE_296.sw, _T_4054
node _T_4055 = bits(_WIRE_297, 15, 15)
connect _WIRE_296.gf, _T_4055
node _T_4056 = bits(_WIRE_297, 16, 16)
connect _WIRE_296.pf, _T_4056
node _T_4057 = bits(_WIRE_297, 17, 17)
connect _WIRE_296.ae_stage2, _T_4057
node _T_4058 = bits(_WIRE_297, 18, 18)
connect _WIRE_296.ae_final, _T_4058
node _T_4059 = bits(_WIRE_297, 19, 19)
connect _WIRE_296.ae_ptw, _T_4059
node _T_4060 = bits(_WIRE_297, 20, 20)
connect _WIRE_296.g, _T_4060
node _T_4061 = bits(_WIRE_297, 21, 21)
connect _WIRE_296.u, _T_4061
node _T_4062 = bits(_WIRE_297, 41, 22)
connect _WIRE_296.ppn, _T_4062
wire _WIRE_298 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_299 : UInt<42>
connect _WIRE_299, sectored_entries[0][1].data[2]
node _T_4063 = bits(_WIRE_299, 0, 0)
connect _WIRE_298.fragmented_superpage, _T_4063
node _T_4064 = bits(_WIRE_299, 1, 1)
connect _WIRE_298.c, _T_4064
node _T_4065 = bits(_WIRE_299, 2, 2)
connect _WIRE_298.eff, _T_4065
node _T_4066 = bits(_WIRE_299, 3, 3)
connect _WIRE_298.paa, _T_4066
node _T_4067 = bits(_WIRE_299, 4, 4)
connect _WIRE_298.pal, _T_4067
node _T_4068 = bits(_WIRE_299, 5, 5)
connect _WIRE_298.ppp, _T_4068
node _T_4069 = bits(_WIRE_299, 6, 6)
connect _WIRE_298.pr, _T_4069
node _T_4070 = bits(_WIRE_299, 7, 7)
connect _WIRE_298.px, _T_4070
node _T_4071 = bits(_WIRE_299, 8, 8)
connect _WIRE_298.pw, _T_4071
node _T_4072 = bits(_WIRE_299, 9, 9)
connect _WIRE_298.hr, _T_4072
node _T_4073 = bits(_WIRE_299, 10, 10)
connect _WIRE_298.hx, _T_4073
node _T_4074 = bits(_WIRE_299, 11, 11)
connect _WIRE_298.hw, _T_4074
node _T_4075 = bits(_WIRE_299, 12, 12)
connect _WIRE_298.sr, _T_4075
node _T_4076 = bits(_WIRE_299, 13, 13)
connect _WIRE_298.sx, _T_4076
node _T_4077 = bits(_WIRE_299, 14, 14)
connect _WIRE_298.sw, _T_4077
node _T_4078 = bits(_WIRE_299, 15, 15)
connect _WIRE_298.gf, _T_4078
node _T_4079 = bits(_WIRE_299, 16, 16)
connect _WIRE_298.pf, _T_4079
node _T_4080 = bits(_WIRE_299, 17, 17)
connect _WIRE_298.ae_stage2, _T_4080
node _T_4081 = bits(_WIRE_299, 18, 18)
connect _WIRE_298.ae_final, _T_4081
node _T_4082 = bits(_WIRE_299, 19, 19)
connect _WIRE_298.ae_ptw, _T_4082
node _T_4083 = bits(_WIRE_299, 20, 20)
connect _WIRE_298.g, _T_4083
node _T_4084 = bits(_WIRE_299, 21, 21)
connect _WIRE_298.u, _T_4084
node _T_4085 = bits(_WIRE_299, 41, 22)
connect _WIRE_298.ppn, _T_4085
wire _WIRE_300 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_301 : UInt<42>
connect _WIRE_301, sectored_entries[0][1].data[3]
node _T_4086 = bits(_WIRE_301, 0, 0)
connect _WIRE_300.fragmented_superpage, _T_4086
node _T_4087 = bits(_WIRE_301, 1, 1)
connect _WIRE_300.c, _T_4087
node _T_4088 = bits(_WIRE_301, 2, 2)
connect _WIRE_300.eff, _T_4088
node _T_4089 = bits(_WIRE_301, 3, 3)
connect _WIRE_300.paa, _T_4089
node _T_4090 = bits(_WIRE_301, 4, 4)
connect _WIRE_300.pal, _T_4090
node _T_4091 = bits(_WIRE_301, 5, 5)
connect _WIRE_300.ppp, _T_4091
node _T_4092 = bits(_WIRE_301, 6, 6)
connect _WIRE_300.pr, _T_4092
node _T_4093 = bits(_WIRE_301, 7, 7)
connect _WIRE_300.px, _T_4093
node _T_4094 = bits(_WIRE_301, 8, 8)
connect _WIRE_300.pw, _T_4094
node _T_4095 = bits(_WIRE_301, 9, 9)
connect _WIRE_300.hr, _T_4095
node _T_4096 = bits(_WIRE_301, 10, 10)
connect _WIRE_300.hx, _T_4096
node _T_4097 = bits(_WIRE_301, 11, 11)
connect _WIRE_300.hw, _T_4097
node _T_4098 = bits(_WIRE_301, 12, 12)
connect _WIRE_300.sr, _T_4098
node _T_4099 = bits(_WIRE_301, 13, 13)
connect _WIRE_300.sx, _T_4099
node _T_4100 = bits(_WIRE_301, 14, 14)
connect _WIRE_300.sw, _T_4100
node _T_4101 = bits(_WIRE_301, 15, 15)
connect _WIRE_300.gf, _T_4101
node _T_4102 = bits(_WIRE_301, 16, 16)
connect _WIRE_300.pf, _T_4102
node _T_4103 = bits(_WIRE_301, 17, 17)
connect _WIRE_300.ae_stage2, _T_4103
node _T_4104 = bits(_WIRE_301, 18, 18)
connect _WIRE_300.ae_final, _T_4104
node _T_4105 = bits(_WIRE_301, 19, 19)
connect _WIRE_300.ae_ptw, _T_4105
node _T_4106 = bits(_WIRE_301, 20, 20)
connect _WIRE_300.g, _T_4106
node _T_4107 = bits(_WIRE_301, 21, 21)
connect _WIRE_300.u, _T_4107
node _T_4108 = bits(_WIRE_301, 41, 22)
connect _WIRE_300.ppn, _T_4108
node _T_4109 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1))
when _T_4109 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_4110 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1))
when _T_4110 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_4111 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1))
when _T_4111 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_4112 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1))
when _T_4112 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
wire _WIRE_302 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_303 : UInt<42>
connect _WIRE_303, sectored_entries[0][2].data[0]
node _T_4113 = bits(_WIRE_303, 0, 0)
connect _WIRE_302.fragmented_superpage, _T_4113
node _T_4114 = bits(_WIRE_303, 1, 1)
connect _WIRE_302.c, _T_4114
node _T_4115 = bits(_WIRE_303, 2, 2)
connect _WIRE_302.eff, _T_4115
node _T_4116 = bits(_WIRE_303, 3, 3)
connect _WIRE_302.paa, _T_4116
node _T_4117 = bits(_WIRE_303, 4, 4)
connect _WIRE_302.pal, _T_4117
node _T_4118 = bits(_WIRE_303, 5, 5)
connect _WIRE_302.ppp, _T_4118
node _T_4119 = bits(_WIRE_303, 6, 6)
connect _WIRE_302.pr, _T_4119
node _T_4120 = bits(_WIRE_303, 7, 7)
connect _WIRE_302.px, _T_4120
node _T_4121 = bits(_WIRE_303, 8, 8)
connect _WIRE_302.pw, _T_4121
node _T_4122 = bits(_WIRE_303, 9, 9)
connect _WIRE_302.hr, _T_4122
node _T_4123 = bits(_WIRE_303, 10, 10)
connect _WIRE_302.hx, _T_4123
node _T_4124 = bits(_WIRE_303, 11, 11)
connect _WIRE_302.hw, _T_4124
node _T_4125 = bits(_WIRE_303, 12, 12)
connect _WIRE_302.sr, _T_4125
node _T_4126 = bits(_WIRE_303, 13, 13)
connect _WIRE_302.sx, _T_4126
node _T_4127 = bits(_WIRE_303, 14, 14)
connect _WIRE_302.sw, _T_4127
node _T_4128 = bits(_WIRE_303, 15, 15)
connect _WIRE_302.gf, _T_4128
node _T_4129 = bits(_WIRE_303, 16, 16)
connect _WIRE_302.pf, _T_4129
node _T_4130 = bits(_WIRE_303, 17, 17)
connect _WIRE_302.ae_stage2, _T_4130
node _T_4131 = bits(_WIRE_303, 18, 18)
connect _WIRE_302.ae_final, _T_4131
node _T_4132 = bits(_WIRE_303, 19, 19)
connect _WIRE_302.ae_ptw, _T_4132
node _T_4133 = bits(_WIRE_303, 20, 20)
connect _WIRE_302.g, _T_4133
node _T_4134 = bits(_WIRE_303, 21, 21)
connect _WIRE_302.u, _T_4134
node _T_4135 = bits(_WIRE_303, 41, 22)
connect _WIRE_302.ppn, _T_4135
wire _WIRE_304 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_305 : UInt<42>
connect _WIRE_305, sectored_entries[0][2].data[1]
node _T_4136 = bits(_WIRE_305, 0, 0)
connect _WIRE_304.fragmented_superpage, _T_4136
node _T_4137 = bits(_WIRE_305, 1, 1)
connect _WIRE_304.c, _T_4137
node _T_4138 = bits(_WIRE_305, 2, 2)
connect _WIRE_304.eff, _T_4138
node _T_4139 = bits(_WIRE_305, 3, 3)
connect _WIRE_304.paa, _T_4139
node _T_4140 = bits(_WIRE_305, 4, 4)
connect _WIRE_304.pal, _T_4140
node _T_4141 = bits(_WIRE_305, 5, 5)
connect _WIRE_304.ppp, _T_4141
node _T_4142 = bits(_WIRE_305, 6, 6)
connect _WIRE_304.pr, _T_4142
node _T_4143 = bits(_WIRE_305, 7, 7)
connect _WIRE_304.px, _T_4143
node _T_4144 = bits(_WIRE_305, 8, 8)
connect _WIRE_304.pw, _T_4144
node _T_4145 = bits(_WIRE_305, 9, 9)
connect _WIRE_304.hr, _T_4145
node _T_4146 = bits(_WIRE_305, 10, 10)
connect _WIRE_304.hx, _T_4146
node _T_4147 = bits(_WIRE_305, 11, 11)
connect _WIRE_304.hw, _T_4147
node _T_4148 = bits(_WIRE_305, 12, 12)
connect _WIRE_304.sr, _T_4148
node _T_4149 = bits(_WIRE_305, 13, 13)
connect _WIRE_304.sx, _T_4149
node _T_4150 = bits(_WIRE_305, 14, 14)
connect _WIRE_304.sw, _T_4150
node _T_4151 = bits(_WIRE_305, 15, 15)
connect _WIRE_304.gf, _T_4151
node _T_4152 = bits(_WIRE_305, 16, 16)
connect _WIRE_304.pf, _T_4152
node _T_4153 = bits(_WIRE_305, 17, 17)
connect _WIRE_304.ae_stage2, _T_4153
node _T_4154 = bits(_WIRE_305, 18, 18)
connect _WIRE_304.ae_final, _T_4154
node _T_4155 = bits(_WIRE_305, 19, 19)
connect _WIRE_304.ae_ptw, _T_4155
node _T_4156 = bits(_WIRE_305, 20, 20)
connect _WIRE_304.g, _T_4156
node _T_4157 = bits(_WIRE_305, 21, 21)
connect _WIRE_304.u, _T_4157
node _T_4158 = bits(_WIRE_305, 41, 22)
connect _WIRE_304.ppn, _T_4158
wire _WIRE_306 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_307 : UInt<42>
connect _WIRE_307, sectored_entries[0][2].data[2]
node _T_4159 = bits(_WIRE_307, 0, 0)
connect _WIRE_306.fragmented_superpage, _T_4159
node _T_4160 = bits(_WIRE_307, 1, 1)
connect _WIRE_306.c, _T_4160
node _T_4161 = bits(_WIRE_307, 2, 2)
connect _WIRE_306.eff, _T_4161
node _T_4162 = bits(_WIRE_307, 3, 3)
connect _WIRE_306.paa, _T_4162
node _T_4163 = bits(_WIRE_307, 4, 4)
connect _WIRE_306.pal, _T_4163
node _T_4164 = bits(_WIRE_307, 5, 5)
connect _WIRE_306.ppp, _T_4164
node _T_4165 = bits(_WIRE_307, 6, 6)
connect _WIRE_306.pr, _T_4165
node _T_4166 = bits(_WIRE_307, 7, 7)
connect _WIRE_306.px, _T_4166
node _T_4167 = bits(_WIRE_307, 8, 8)
connect _WIRE_306.pw, _T_4167
node _T_4168 = bits(_WIRE_307, 9, 9)
connect _WIRE_306.hr, _T_4168
node _T_4169 = bits(_WIRE_307, 10, 10)
connect _WIRE_306.hx, _T_4169
node _T_4170 = bits(_WIRE_307, 11, 11)
connect _WIRE_306.hw, _T_4170
node _T_4171 = bits(_WIRE_307, 12, 12)
connect _WIRE_306.sr, _T_4171
node _T_4172 = bits(_WIRE_307, 13, 13)
connect _WIRE_306.sx, _T_4172
node _T_4173 = bits(_WIRE_307, 14, 14)
connect _WIRE_306.sw, _T_4173
node _T_4174 = bits(_WIRE_307, 15, 15)
connect _WIRE_306.gf, _T_4174
node _T_4175 = bits(_WIRE_307, 16, 16)
connect _WIRE_306.pf, _T_4175
node _T_4176 = bits(_WIRE_307, 17, 17)
connect _WIRE_306.ae_stage2, _T_4176
node _T_4177 = bits(_WIRE_307, 18, 18)
connect _WIRE_306.ae_final, _T_4177
node _T_4178 = bits(_WIRE_307, 19, 19)
connect _WIRE_306.ae_ptw, _T_4178
node _T_4179 = bits(_WIRE_307, 20, 20)
connect _WIRE_306.g, _T_4179
node _T_4180 = bits(_WIRE_307, 21, 21)
connect _WIRE_306.u, _T_4180
node _T_4181 = bits(_WIRE_307, 41, 22)
connect _WIRE_306.ppn, _T_4181
wire _WIRE_308 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_309 : UInt<42>
connect _WIRE_309, sectored_entries[0][2].data[3]
node _T_4182 = bits(_WIRE_309, 0, 0)
connect _WIRE_308.fragmented_superpage, _T_4182
node _T_4183 = bits(_WIRE_309, 1, 1)
connect _WIRE_308.c, _T_4183
node _T_4184 = bits(_WIRE_309, 2, 2)
connect _WIRE_308.eff, _T_4184
node _T_4185 = bits(_WIRE_309, 3, 3)
connect _WIRE_308.paa, _T_4185
node _T_4186 = bits(_WIRE_309, 4, 4)
connect _WIRE_308.pal, _T_4186
node _T_4187 = bits(_WIRE_309, 5, 5)
connect _WIRE_308.ppp, _T_4187
node _T_4188 = bits(_WIRE_309, 6, 6)
connect _WIRE_308.pr, _T_4188
node _T_4189 = bits(_WIRE_309, 7, 7)
connect _WIRE_308.px, _T_4189
node _T_4190 = bits(_WIRE_309, 8, 8)
connect _WIRE_308.pw, _T_4190
node _T_4191 = bits(_WIRE_309, 9, 9)
connect _WIRE_308.hr, _T_4191
node _T_4192 = bits(_WIRE_309, 10, 10)
connect _WIRE_308.hx, _T_4192
node _T_4193 = bits(_WIRE_309, 11, 11)
connect _WIRE_308.hw, _T_4193
node _T_4194 = bits(_WIRE_309, 12, 12)
connect _WIRE_308.sr, _T_4194
node _T_4195 = bits(_WIRE_309, 13, 13)
connect _WIRE_308.sx, _T_4195
node _T_4196 = bits(_WIRE_309, 14, 14)
connect _WIRE_308.sw, _T_4196
node _T_4197 = bits(_WIRE_309, 15, 15)
connect _WIRE_308.gf, _T_4197
node _T_4198 = bits(_WIRE_309, 16, 16)
connect _WIRE_308.pf, _T_4198
node _T_4199 = bits(_WIRE_309, 17, 17)
connect _WIRE_308.ae_stage2, _T_4199
node _T_4200 = bits(_WIRE_309, 18, 18)
connect _WIRE_308.ae_final, _T_4200
node _T_4201 = bits(_WIRE_309, 19, 19)
connect _WIRE_308.ae_ptw, _T_4201
node _T_4202 = bits(_WIRE_309, 20, 20)
connect _WIRE_308.g, _T_4202
node _T_4203 = bits(_WIRE_309, 21, 21)
connect _WIRE_308.u, _T_4203
node _T_4204 = bits(_WIRE_309, 41, 22)
connect _WIRE_308.ppn, _T_4204
node _T_4205 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1))
when _T_4205 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_4206 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1))
when _T_4206 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_4207 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1))
when _T_4207 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_4208 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1))
when _T_4208 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
wire _WIRE_310 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_311 : UInt<42>
connect _WIRE_311, sectored_entries[0][3].data[0]
node _T_4209 = bits(_WIRE_311, 0, 0)
connect _WIRE_310.fragmented_superpage, _T_4209
node _T_4210 = bits(_WIRE_311, 1, 1)
connect _WIRE_310.c, _T_4210
node _T_4211 = bits(_WIRE_311, 2, 2)
connect _WIRE_310.eff, _T_4211
node _T_4212 = bits(_WIRE_311, 3, 3)
connect _WIRE_310.paa, _T_4212
node _T_4213 = bits(_WIRE_311, 4, 4)
connect _WIRE_310.pal, _T_4213
node _T_4214 = bits(_WIRE_311, 5, 5)
connect _WIRE_310.ppp, _T_4214
node _T_4215 = bits(_WIRE_311, 6, 6)
connect _WIRE_310.pr, _T_4215
node _T_4216 = bits(_WIRE_311, 7, 7)
connect _WIRE_310.px, _T_4216
node _T_4217 = bits(_WIRE_311, 8, 8)
connect _WIRE_310.pw, _T_4217
node _T_4218 = bits(_WIRE_311, 9, 9)
connect _WIRE_310.hr, _T_4218
node _T_4219 = bits(_WIRE_311, 10, 10)
connect _WIRE_310.hx, _T_4219
node _T_4220 = bits(_WIRE_311, 11, 11)
connect _WIRE_310.hw, _T_4220
node _T_4221 = bits(_WIRE_311, 12, 12)
connect _WIRE_310.sr, _T_4221
node _T_4222 = bits(_WIRE_311, 13, 13)
connect _WIRE_310.sx, _T_4222
node _T_4223 = bits(_WIRE_311, 14, 14)
connect _WIRE_310.sw, _T_4223
node _T_4224 = bits(_WIRE_311, 15, 15)
connect _WIRE_310.gf, _T_4224
node _T_4225 = bits(_WIRE_311, 16, 16)
connect _WIRE_310.pf, _T_4225
node _T_4226 = bits(_WIRE_311, 17, 17)
connect _WIRE_310.ae_stage2, _T_4226
node _T_4227 = bits(_WIRE_311, 18, 18)
connect _WIRE_310.ae_final, _T_4227
node _T_4228 = bits(_WIRE_311, 19, 19)
connect _WIRE_310.ae_ptw, _T_4228
node _T_4229 = bits(_WIRE_311, 20, 20)
connect _WIRE_310.g, _T_4229
node _T_4230 = bits(_WIRE_311, 21, 21)
connect _WIRE_310.u, _T_4230
node _T_4231 = bits(_WIRE_311, 41, 22)
connect _WIRE_310.ppn, _T_4231
wire _WIRE_312 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_313 : UInt<42>
connect _WIRE_313, sectored_entries[0][3].data[1]
node _T_4232 = bits(_WIRE_313, 0, 0)
connect _WIRE_312.fragmented_superpage, _T_4232
node _T_4233 = bits(_WIRE_313, 1, 1)
connect _WIRE_312.c, _T_4233
node _T_4234 = bits(_WIRE_313, 2, 2)
connect _WIRE_312.eff, _T_4234
node _T_4235 = bits(_WIRE_313, 3, 3)
connect _WIRE_312.paa, _T_4235
node _T_4236 = bits(_WIRE_313, 4, 4)
connect _WIRE_312.pal, _T_4236
node _T_4237 = bits(_WIRE_313, 5, 5)
connect _WIRE_312.ppp, _T_4237
node _T_4238 = bits(_WIRE_313, 6, 6)
connect _WIRE_312.pr, _T_4238
node _T_4239 = bits(_WIRE_313, 7, 7)
connect _WIRE_312.px, _T_4239
node _T_4240 = bits(_WIRE_313, 8, 8)
connect _WIRE_312.pw, _T_4240
node _T_4241 = bits(_WIRE_313, 9, 9)
connect _WIRE_312.hr, _T_4241
node _T_4242 = bits(_WIRE_313, 10, 10)
connect _WIRE_312.hx, _T_4242
node _T_4243 = bits(_WIRE_313, 11, 11)
connect _WIRE_312.hw, _T_4243
node _T_4244 = bits(_WIRE_313, 12, 12)
connect _WIRE_312.sr, _T_4244
node _T_4245 = bits(_WIRE_313, 13, 13)
connect _WIRE_312.sx, _T_4245
node _T_4246 = bits(_WIRE_313, 14, 14)
connect _WIRE_312.sw, _T_4246
node _T_4247 = bits(_WIRE_313, 15, 15)
connect _WIRE_312.gf, _T_4247
node _T_4248 = bits(_WIRE_313, 16, 16)
connect _WIRE_312.pf, _T_4248
node _T_4249 = bits(_WIRE_313, 17, 17)
connect _WIRE_312.ae_stage2, _T_4249
node _T_4250 = bits(_WIRE_313, 18, 18)
connect _WIRE_312.ae_final, _T_4250
node _T_4251 = bits(_WIRE_313, 19, 19)
connect _WIRE_312.ae_ptw, _T_4251
node _T_4252 = bits(_WIRE_313, 20, 20)
connect _WIRE_312.g, _T_4252
node _T_4253 = bits(_WIRE_313, 21, 21)
connect _WIRE_312.u, _T_4253
node _T_4254 = bits(_WIRE_313, 41, 22)
connect _WIRE_312.ppn, _T_4254
wire _WIRE_314 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_315 : UInt<42>
connect _WIRE_315, sectored_entries[0][3].data[2]
node _T_4255 = bits(_WIRE_315, 0, 0)
connect _WIRE_314.fragmented_superpage, _T_4255
node _T_4256 = bits(_WIRE_315, 1, 1)
connect _WIRE_314.c, _T_4256
node _T_4257 = bits(_WIRE_315, 2, 2)
connect _WIRE_314.eff, _T_4257
node _T_4258 = bits(_WIRE_315, 3, 3)
connect _WIRE_314.paa, _T_4258
node _T_4259 = bits(_WIRE_315, 4, 4)
connect _WIRE_314.pal, _T_4259
node _T_4260 = bits(_WIRE_315, 5, 5)
connect _WIRE_314.ppp, _T_4260
node _T_4261 = bits(_WIRE_315, 6, 6)
connect _WIRE_314.pr, _T_4261
node _T_4262 = bits(_WIRE_315, 7, 7)
connect _WIRE_314.px, _T_4262
node _T_4263 = bits(_WIRE_315, 8, 8)
connect _WIRE_314.pw, _T_4263
node _T_4264 = bits(_WIRE_315, 9, 9)
connect _WIRE_314.hr, _T_4264
node _T_4265 = bits(_WIRE_315, 10, 10)
connect _WIRE_314.hx, _T_4265
node _T_4266 = bits(_WIRE_315, 11, 11)
connect _WIRE_314.hw, _T_4266
node _T_4267 = bits(_WIRE_315, 12, 12)
connect _WIRE_314.sr, _T_4267
node _T_4268 = bits(_WIRE_315, 13, 13)
connect _WIRE_314.sx, _T_4268
node _T_4269 = bits(_WIRE_315, 14, 14)
connect _WIRE_314.sw, _T_4269
node _T_4270 = bits(_WIRE_315, 15, 15)
connect _WIRE_314.gf, _T_4270
node _T_4271 = bits(_WIRE_315, 16, 16)
connect _WIRE_314.pf, _T_4271
node _T_4272 = bits(_WIRE_315, 17, 17)
connect _WIRE_314.ae_stage2, _T_4272
node _T_4273 = bits(_WIRE_315, 18, 18)
connect _WIRE_314.ae_final, _T_4273
node _T_4274 = bits(_WIRE_315, 19, 19)
connect _WIRE_314.ae_ptw, _T_4274
node _T_4275 = bits(_WIRE_315, 20, 20)
connect _WIRE_314.g, _T_4275
node _T_4276 = bits(_WIRE_315, 21, 21)
connect _WIRE_314.u, _T_4276
node _T_4277 = bits(_WIRE_315, 41, 22)
connect _WIRE_314.ppn, _T_4277
wire _WIRE_316 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_317 : UInt<42>
connect _WIRE_317, sectored_entries[0][3].data[3]
node _T_4278 = bits(_WIRE_317, 0, 0)
connect _WIRE_316.fragmented_superpage, _T_4278
node _T_4279 = bits(_WIRE_317, 1, 1)
connect _WIRE_316.c, _T_4279
node _T_4280 = bits(_WIRE_317, 2, 2)
connect _WIRE_316.eff, _T_4280
node _T_4281 = bits(_WIRE_317, 3, 3)
connect _WIRE_316.paa, _T_4281
node _T_4282 = bits(_WIRE_317, 4, 4)
connect _WIRE_316.pal, _T_4282
node _T_4283 = bits(_WIRE_317, 5, 5)
connect _WIRE_316.ppp, _T_4283
node _T_4284 = bits(_WIRE_317, 6, 6)
connect _WIRE_316.pr, _T_4284
node _T_4285 = bits(_WIRE_317, 7, 7)
connect _WIRE_316.px, _T_4285
node _T_4286 = bits(_WIRE_317, 8, 8)
connect _WIRE_316.pw, _T_4286
node _T_4287 = bits(_WIRE_317, 9, 9)
connect _WIRE_316.hr, _T_4287
node _T_4288 = bits(_WIRE_317, 10, 10)
connect _WIRE_316.hx, _T_4288
node _T_4289 = bits(_WIRE_317, 11, 11)
connect _WIRE_316.hw, _T_4289
node _T_4290 = bits(_WIRE_317, 12, 12)
connect _WIRE_316.sr, _T_4290
node _T_4291 = bits(_WIRE_317, 13, 13)
connect _WIRE_316.sx, _T_4291
node _T_4292 = bits(_WIRE_317, 14, 14)
connect _WIRE_316.sw, _T_4292
node _T_4293 = bits(_WIRE_317, 15, 15)
connect _WIRE_316.gf, _T_4293
node _T_4294 = bits(_WIRE_317, 16, 16)
connect _WIRE_316.pf, _T_4294
node _T_4295 = bits(_WIRE_317, 17, 17)
connect _WIRE_316.ae_stage2, _T_4295
node _T_4296 = bits(_WIRE_317, 18, 18)
connect _WIRE_316.ae_final, _T_4296
node _T_4297 = bits(_WIRE_317, 19, 19)
connect _WIRE_316.ae_ptw, _T_4297
node _T_4298 = bits(_WIRE_317, 20, 20)
connect _WIRE_316.g, _T_4298
node _T_4299 = bits(_WIRE_317, 21, 21)
connect _WIRE_316.u, _T_4299
node _T_4300 = bits(_WIRE_317, 41, 22)
connect _WIRE_316.ppn, _T_4300
node _T_4301 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1))
when _T_4301 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_4302 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1))
when _T_4302 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_4303 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1))
when _T_4303 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_4304 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1))
when _T_4304 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
wire _WIRE_318 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_319 : UInt<42>
connect _WIRE_319, sectored_entries[0][4].data[0]
node _T_4305 = bits(_WIRE_319, 0, 0)
connect _WIRE_318.fragmented_superpage, _T_4305
node _T_4306 = bits(_WIRE_319, 1, 1)
connect _WIRE_318.c, _T_4306
node _T_4307 = bits(_WIRE_319, 2, 2)
connect _WIRE_318.eff, _T_4307
node _T_4308 = bits(_WIRE_319, 3, 3)
connect _WIRE_318.paa, _T_4308
node _T_4309 = bits(_WIRE_319, 4, 4)
connect _WIRE_318.pal, _T_4309
node _T_4310 = bits(_WIRE_319, 5, 5)
connect _WIRE_318.ppp, _T_4310
node _T_4311 = bits(_WIRE_319, 6, 6)
connect _WIRE_318.pr, _T_4311
node _T_4312 = bits(_WIRE_319, 7, 7)
connect _WIRE_318.px, _T_4312
node _T_4313 = bits(_WIRE_319, 8, 8)
connect _WIRE_318.pw, _T_4313
node _T_4314 = bits(_WIRE_319, 9, 9)
connect _WIRE_318.hr, _T_4314
node _T_4315 = bits(_WIRE_319, 10, 10)
connect _WIRE_318.hx, _T_4315
node _T_4316 = bits(_WIRE_319, 11, 11)
connect _WIRE_318.hw, _T_4316
node _T_4317 = bits(_WIRE_319, 12, 12)
connect _WIRE_318.sr, _T_4317
node _T_4318 = bits(_WIRE_319, 13, 13)
connect _WIRE_318.sx, _T_4318
node _T_4319 = bits(_WIRE_319, 14, 14)
connect _WIRE_318.sw, _T_4319
node _T_4320 = bits(_WIRE_319, 15, 15)
connect _WIRE_318.gf, _T_4320
node _T_4321 = bits(_WIRE_319, 16, 16)
connect _WIRE_318.pf, _T_4321
node _T_4322 = bits(_WIRE_319, 17, 17)
connect _WIRE_318.ae_stage2, _T_4322
node _T_4323 = bits(_WIRE_319, 18, 18)
connect _WIRE_318.ae_final, _T_4323
node _T_4324 = bits(_WIRE_319, 19, 19)
connect _WIRE_318.ae_ptw, _T_4324
node _T_4325 = bits(_WIRE_319, 20, 20)
connect _WIRE_318.g, _T_4325
node _T_4326 = bits(_WIRE_319, 21, 21)
connect _WIRE_318.u, _T_4326
node _T_4327 = bits(_WIRE_319, 41, 22)
connect _WIRE_318.ppn, _T_4327
wire _WIRE_320 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_321 : UInt<42>
connect _WIRE_321, sectored_entries[0][4].data[1]
node _T_4328 = bits(_WIRE_321, 0, 0)
connect _WIRE_320.fragmented_superpage, _T_4328
node _T_4329 = bits(_WIRE_321, 1, 1)
connect _WIRE_320.c, _T_4329
node _T_4330 = bits(_WIRE_321, 2, 2)
connect _WIRE_320.eff, _T_4330
node _T_4331 = bits(_WIRE_321, 3, 3)
connect _WIRE_320.paa, _T_4331
node _T_4332 = bits(_WIRE_321, 4, 4)
connect _WIRE_320.pal, _T_4332
node _T_4333 = bits(_WIRE_321, 5, 5)
connect _WIRE_320.ppp, _T_4333
node _T_4334 = bits(_WIRE_321, 6, 6)
connect _WIRE_320.pr, _T_4334
node _T_4335 = bits(_WIRE_321, 7, 7)
connect _WIRE_320.px, _T_4335
node _T_4336 = bits(_WIRE_321, 8, 8)
connect _WIRE_320.pw, _T_4336
node _T_4337 = bits(_WIRE_321, 9, 9)
connect _WIRE_320.hr, _T_4337
node _T_4338 = bits(_WIRE_321, 10, 10)
connect _WIRE_320.hx, _T_4338
node _T_4339 = bits(_WIRE_321, 11, 11)
connect _WIRE_320.hw, _T_4339
node _T_4340 = bits(_WIRE_321, 12, 12)
connect _WIRE_320.sr, _T_4340
node _T_4341 = bits(_WIRE_321, 13, 13)
connect _WIRE_320.sx, _T_4341
node _T_4342 = bits(_WIRE_321, 14, 14)
connect _WIRE_320.sw, _T_4342
node _T_4343 = bits(_WIRE_321, 15, 15)
connect _WIRE_320.gf, _T_4343
node _T_4344 = bits(_WIRE_321, 16, 16)
connect _WIRE_320.pf, _T_4344
node _T_4345 = bits(_WIRE_321, 17, 17)
connect _WIRE_320.ae_stage2, _T_4345
node _T_4346 = bits(_WIRE_321, 18, 18)
connect _WIRE_320.ae_final, _T_4346
node _T_4347 = bits(_WIRE_321, 19, 19)
connect _WIRE_320.ae_ptw, _T_4347
node _T_4348 = bits(_WIRE_321, 20, 20)
connect _WIRE_320.g, _T_4348
node _T_4349 = bits(_WIRE_321, 21, 21)
connect _WIRE_320.u, _T_4349
node _T_4350 = bits(_WIRE_321, 41, 22)
connect _WIRE_320.ppn, _T_4350
wire _WIRE_322 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_323 : UInt<42>
connect _WIRE_323, sectored_entries[0][4].data[2]
node _T_4351 = bits(_WIRE_323, 0, 0)
connect _WIRE_322.fragmented_superpage, _T_4351
node _T_4352 = bits(_WIRE_323, 1, 1)
connect _WIRE_322.c, _T_4352
node _T_4353 = bits(_WIRE_323, 2, 2)
connect _WIRE_322.eff, _T_4353
node _T_4354 = bits(_WIRE_323, 3, 3)
connect _WIRE_322.paa, _T_4354
node _T_4355 = bits(_WIRE_323, 4, 4)
connect _WIRE_322.pal, _T_4355
node _T_4356 = bits(_WIRE_323, 5, 5)
connect _WIRE_322.ppp, _T_4356
node _T_4357 = bits(_WIRE_323, 6, 6)
connect _WIRE_322.pr, _T_4357
node _T_4358 = bits(_WIRE_323, 7, 7)
connect _WIRE_322.px, _T_4358
node _T_4359 = bits(_WIRE_323, 8, 8)
connect _WIRE_322.pw, _T_4359
node _T_4360 = bits(_WIRE_323, 9, 9)
connect _WIRE_322.hr, _T_4360
node _T_4361 = bits(_WIRE_323, 10, 10)
connect _WIRE_322.hx, _T_4361
node _T_4362 = bits(_WIRE_323, 11, 11)
connect _WIRE_322.hw, _T_4362
node _T_4363 = bits(_WIRE_323, 12, 12)
connect _WIRE_322.sr, _T_4363
node _T_4364 = bits(_WIRE_323, 13, 13)
connect _WIRE_322.sx, _T_4364
node _T_4365 = bits(_WIRE_323, 14, 14)
connect _WIRE_322.sw, _T_4365
node _T_4366 = bits(_WIRE_323, 15, 15)
connect _WIRE_322.gf, _T_4366
node _T_4367 = bits(_WIRE_323, 16, 16)
connect _WIRE_322.pf, _T_4367
node _T_4368 = bits(_WIRE_323, 17, 17)
connect _WIRE_322.ae_stage2, _T_4368
node _T_4369 = bits(_WIRE_323, 18, 18)
connect _WIRE_322.ae_final, _T_4369
node _T_4370 = bits(_WIRE_323, 19, 19)
connect _WIRE_322.ae_ptw, _T_4370
node _T_4371 = bits(_WIRE_323, 20, 20)
connect _WIRE_322.g, _T_4371
node _T_4372 = bits(_WIRE_323, 21, 21)
connect _WIRE_322.u, _T_4372
node _T_4373 = bits(_WIRE_323, 41, 22)
connect _WIRE_322.ppn, _T_4373
wire _WIRE_324 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_325 : UInt<42>
connect _WIRE_325, sectored_entries[0][4].data[3]
node _T_4374 = bits(_WIRE_325, 0, 0)
connect _WIRE_324.fragmented_superpage, _T_4374
node _T_4375 = bits(_WIRE_325, 1, 1)
connect _WIRE_324.c, _T_4375
node _T_4376 = bits(_WIRE_325, 2, 2)
connect _WIRE_324.eff, _T_4376
node _T_4377 = bits(_WIRE_325, 3, 3)
connect _WIRE_324.paa, _T_4377
node _T_4378 = bits(_WIRE_325, 4, 4)
connect _WIRE_324.pal, _T_4378
node _T_4379 = bits(_WIRE_325, 5, 5)
connect _WIRE_324.ppp, _T_4379
node _T_4380 = bits(_WIRE_325, 6, 6)
connect _WIRE_324.pr, _T_4380
node _T_4381 = bits(_WIRE_325, 7, 7)
connect _WIRE_324.px, _T_4381
node _T_4382 = bits(_WIRE_325, 8, 8)
connect _WIRE_324.pw, _T_4382
node _T_4383 = bits(_WIRE_325, 9, 9)
connect _WIRE_324.hr, _T_4383
node _T_4384 = bits(_WIRE_325, 10, 10)
connect _WIRE_324.hx, _T_4384
node _T_4385 = bits(_WIRE_325, 11, 11)
connect _WIRE_324.hw, _T_4385
node _T_4386 = bits(_WIRE_325, 12, 12)
connect _WIRE_324.sr, _T_4386
node _T_4387 = bits(_WIRE_325, 13, 13)
connect _WIRE_324.sx, _T_4387
node _T_4388 = bits(_WIRE_325, 14, 14)
connect _WIRE_324.sw, _T_4388
node _T_4389 = bits(_WIRE_325, 15, 15)
connect _WIRE_324.gf, _T_4389
node _T_4390 = bits(_WIRE_325, 16, 16)
connect _WIRE_324.pf, _T_4390
node _T_4391 = bits(_WIRE_325, 17, 17)
connect _WIRE_324.ae_stage2, _T_4391
node _T_4392 = bits(_WIRE_325, 18, 18)
connect _WIRE_324.ae_final, _T_4392
node _T_4393 = bits(_WIRE_325, 19, 19)
connect _WIRE_324.ae_ptw, _T_4393
node _T_4394 = bits(_WIRE_325, 20, 20)
connect _WIRE_324.g, _T_4394
node _T_4395 = bits(_WIRE_325, 21, 21)
connect _WIRE_324.u, _T_4395
node _T_4396 = bits(_WIRE_325, 41, 22)
connect _WIRE_324.ppn, _T_4396
node _T_4397 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1))
when _T_4397 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_4398 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1))
when _T_4398 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_4399 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1))
when _T_4399 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_4400 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1))
when _T_4400 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
wire _WIRE_326 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_327 : UInt<42>
connect _WIRE_327, sectored_entries[0][5].data[0]
node _T_4401 = bits(_WIRE_327, 0, 0)
connect _WIRE_326.fragmented_superpage, _T_4401
node _T_4402 = bits(_WIRE_327, 1, 1)
connect _WIRE_326.c, _T_4402
node _T_4403 = bits(_WIRE_327, 2, 2)
connect _WIRE_326.eff, _T_4403
node _T_4404 = bits(_WIRE_327, 3, 3)
connect _WIRE_326.paa, _T_4404
node _T_4405 = bits(_WIRE_327, 4, 4)
connect _WIRE_326.pal, _T_4405
node _T_4406 = bits(_WIRE_327, 5, 5)
connect _WIRE_326.ppp, _T_4406
node _T_4407 = bits(_WIRE_327, 6, 6)
connect _WIRE_326.pr, _T_4407
node _T_4408 = bits(_WIRE_327, 7, 7)
connect _WIRE_326.px, _T_4408
node _T_4409 = bits(_WIRE_327, 8, 8)
connect _WIRE_326.pw, _T_4409
node _T_4410 = bits(_WIRE_327, 9, 9)
connect _WIRE_326.hr, _T_4410
node _T_4411 = bits(_WIRE_327, 10, 10)
connect _WIRE_326.hx, _T_4411
node _T_4412 = bits(_WIRE_327, 11, 11)
connect _WIRE_326.hw, _T_4412
node _T_4413 = bits(_WIRE_327, 12, 12)
connect _WIRE_326.sr, _T_4413
node _T_4414 = bits(_WIRE_327, 13, 13)
connect _WIRE_326.sx, _T_4414
node _T_4415 = bits(_WIRE_327, 14, 14)
connect _WIRE_326.sw, _T_4415
node _T_4416 = bits(_WIRE_327, 15, 15)
connect _WIRE_326.gf, _T_4416
node _T_4417 = bits(_WIRE_327, 16, 16)
connect _WIRE_326.pf, _T_4417
node _T_4418 = bits(_WIRE_327, 17, 17)
connect _WIRE_326.ae_stage2, _T_4418
node _T_4419 = bits(_WIRE_327, 18, 18)
connect _WIRE_326.ae_final, _T_4419
node _T_4420 = bits(_WIRE_327, 19, 19)
connect _WIRE_326.ae_ptw, _T_4420
node _T_4421 = bits(_WIRE_327, 20, 20)
connect _WIRE_326.g, _T_4421
node _T_4422 = bits(_WIRE_327, 21, 21)
connect _WIRE_326.u, _T_4422
node _T_4423 = bits(_WIRE_327, 41, 22)
connect _WIRE_326.ppn, _T_4423
wire _WIRE_328 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_329 : UInt<42>
connect _WIRE_329, sectored_entries[0][5].data[1]
node _T_4424 = bits(_WIRE_329, 0, 0)
connect _WIRE_328.fragmented_superpage, _T_4424
node _T_4425 = bits(_WIRE_329, 1, 1)
connect _WIRE_328.c, _T_4425
node _T_4426 = bits(_WIRE_329, 2, 2)
connect _WIRE_328.eff, _T_4426
node _T_4427 = bits(_WIRE_329, 3, 3)
connect _WIRE_328.paa, _T_4427
node _T_4428 = bits(_WIRE_329, 4, 4)
connect _WIRE_328.pal, _T_4428
node _T_4429 = bits(_WIRE_329, 5, 5)
connect _WIRE_328.ppp, _T_4429
node _T_4430 = bits(_WIRE_329, 6, 6)
connect _WIRE_328.pr, _T_4430
node _T_4431 = bits(_WIRE_329, 7, 7)
connect _WIRE_328.px, _T_4431
node _T_4432 = bits(_WIRE_329, 8, 8)
connect _WIRE_328.pw, _T_4432
node _T_4433 = bits(_WIRE_329, 9, 9)
connect _WIRE_328.hr, _T_4433
node _T_4434 = bits(_WIRE_329, 10, 10)
connect _WIRE_328.hx, _T_4434
node _T_4435 = bits(_WIRE_329, 11, 11)
connect _WIRE_328.hw, _T_4435
node _T_4436 = bits(_WIRE_329, 12, 12)
connect _WIRE_328.sr, _T_4436
node _T_4437 = bits(_WIRE_329, 13, 13)
connect _WIRE_328.sx, _T_4437
node _T_4438 = bits(_WIRE_329, 14, 14)
connect _WIRE_328.sw, _T_4438
node _T_4439 = bits(_WIRE_329, 15, 15)
connect _WIRE_328.gf, _T_4439
node _T_4440 = bits(_WIRE_329, 16, 16)
connect _WIRE_328.pf, _T_4440
node _T_4441 = bits(_WIRE_329, 17, 17)
connect _WIRE_328.ae_stage2, _T_4441
node _T_4442 = bits(_WIRE_329, 18, 18)
connect _WIRE_328.ae_final, _T_4442
node _T_4443 = bits(_WIRE_329, 19, 19)
connect _WIRE_328.ae_ptw, _T_4443
node _T_4444 = bits(_WIRE_329, 20, 20)
connect _WIRE_328.g, _T_4444
node _T_4445 = bits(_WIRE_329, 21, 21)
connect _WIRE_328.u, _T_4445
node _T_4446 = bits(_WIRE_329, 41, 22)
connect _WIRE_328.ppn, _T_4446
wire _WIRE_330 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_331 : UInt<42>
connect _WIRE_331, sectored_entries[0][5].data[2]
node _T_4447 = bits(_WIRE_331, 0, 0)
connect _WIRE_330.fragmented_superpage, _T_4447
node _T_4448 = bits(_WIRE_331, 1, 1)
connect _WIRE_330.c, _T_4448
node _T_4449 = bits(_WIRE_331, 2, 2)
connect _WIRE_330.eff, _T_4449
node _T_4450 = bits(_WIRE_331, 3, 3)
connect _WIRE_330.paa, _T_4450
node _T_4451 = bits(_WIRE_331, 4, 4)
connect _WIRE_330.pal, _T_4451
node _T_4452 = bits(_WIRE_331, 5, 5)
connect _WIRE_330.ppp, _T_4452
node _T_4453 = bits(_WIRE_331, 6, 6)
connect _WIRE_330.pr, _T_4453
node _T_4454 = bits(_WIRE_331, 7, 7)
connect _WIRE_330.px, _T_4454
node _T_4455 = bits(_WIRE_331, 8, 8)
connect _WIRE_330.pw, _T_4455
node _T_4456 = bits(_WIRE_331, 9, 9)
connect _WIRE_330.hr, _T_4456
node _T_4457 = bits(_WIRE_331, 10, 10)
connect _WIRE_330.hx, _T_4457
node _T_4458 = bits(_WIRE_331, 11, 11)
connect _WIRE_330.hw, _T_4458
node _T_4459 = bits(_WIRE_331, 12, 12)
connect _WIRE_330.sr, _T_4459
node _T_4460 = bits(_WIRE_331, 13, 13)
connect _WIRE_330.sx, _T_4460
node _T_4461 = bits(_WIRE_331, 14, 14)
connect _WIRE_330.sw, _T_4461
node _T_4462 = bits(_WIRE_331, 15, 15)
connect _WIRE_330.gf, _T_4462
node _T_4463 = bits(_WIRE_331, 16, 16)
connect _WIRE_330.pf, _T_4463
node _T_4464 = bits(_WIRE_331, 17, 17)
connect _WIRE_330.ae_stage2, _T_4464
node _T_4465 = bits(_WIRE_331, 18, 18)
connect _WIRE_330.ae_final, _T_4465
node _T_4466 = bits(_WIRE_331, 19, 19)
connect _WIRE_330.ae_ptw, _T_4466
node _T_4467 = bits(_WIRE_331, 20, 20)
connect _WIRE_330.g, _T_4467
node _T_4468 = bits(_WIRE_331, 21, 21)
connect _WIRE_330.u, _T_4468
node _T_4469 = bits(_WIRE_331, 41, 22)
connect _WIRE_330.ppn, _T_4469
wire _WIRE_332 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_333 : UInt<42>
connect _WIRE_333, sectored_entries[0][5].data[3]
node _T_4470 = bits(_WIRE_333, 0, 0)
connect _WIRE_332.fragmented_superpage, _T_4470
node _T_4471 = bits(_WIRE_333, 1, 1)
connect _WIRE_332.c, _T_4471
node _T_4472 = bits(_WIRE_333, 2, 2)
connect _WIRE_332.eff, _T_4472
node _T_4473 = bits(_WIRE_333, 3, 3)
connect _WIRE_332.paa, _T_4473
node _T_4474 = bits(_WIRE_333, 4, 4)
connect _WIRE_332.pal, _T_4474
node _T_4475 = bits(_WIRE_333, 5, 5)
connect _WIRE_332.ppp, _T_4475
node _T_4476 = bits(_WIRE_333, 6, 6)
connect _WIRE_332.pr, _T_4476
node _T_4477 = bits(_WIRE_333, 7, 7)
connect _WIRE_332.px, _T_4477
node _T_4478 = bits(_WIRE_333, 8, 8)
connect _WIRE_332.pw, _T_4478
node _T_4479 = bits(_WIRE_333, 9, 9)
connect _WIRE_332.hr, _T_4479
node _T_4480 = bits(_WIRE_333, 10, 10)
connect _WIRE_332.hx, _T_4480
node _T_4481 = bits(_WIRE_333, 11, 11)
connect _WIRE_332.hw, _T_4481
node _T_4482 = bits(_WIRE_333, 12, 12)
connect _WIRE_332.sr, _T_4482
node _T_4483 = bits(_WIRE_333, 13, 13)
connect _WIRE_332.sx, _T_4483
node _T_4484 = bits(_WIRE_333, 14, 14)
connect _WIRE_332.sw, _T_4484
node _T_4485 = bits(_WIRE_333, 15, 15)
connect _WIRE_332.gf, _T_4485
node _T_4486 = bits(_WIRE_333, 16, 16)
connect _WIRE_332.pf, _T_4486
node _T_4487 = bits(_WIRE_333, 17, 17)
connect _WIRE_332.ae_stage2, _T_4487
node _T_4488 = bits(_WIRE_333, 18, 18)
connect _WIRE_332.ae_final, _T_4488
node _T_4489 = bits(_WIRE_333, 19, 19)
connect _WIRE_332.ae_ptw, _T_4489
node _T_4490 = bits(_WIRE_333, 20, 20)
connect _WIRE_332.g, _T_4490
node _T_4491 = bits(_WIRE_333, 21, 21)
connect _WIRE_332.u, _T_4491
node _T_4492 = bits(_WIRE_333, 41, 22)
connect _WIRE_332.ppn, _T_4492
node _T_4493 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1))
when _T_4493 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_4494 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1))
when _T_4494 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_4495 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1))
when _T_4495 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_4496 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1))
when _T_4496 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
wire _WIRE_334 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_335 : UInt<42>
connect _WIRE_335, sectored_entries[0][6].data[0]
node _T_4497 = bits(_WIRE_335, 0, 0)
connect _WIRE_334.fragmented_superpage, _T_4497
node _T_4498 = bits(_WIRE_335, 1, 1)
connect _WIRE_334.c, _T_4498
node _T_4499 = bits(_WIRE_335, 2, 2)
connect _WIRE_334.eff, _T_4499
node _T_4500 = bits(_WIRE_335, 3, 3)
connect _WIRE_334.paa, _T_4500
node _T_4501 = bits(_WIRE_335, 4, 4)
connect _WIRE_334.pal, _T_4501
node _T_4502 = bits(_WIRE_335, 5, 5)
connect _WIRE_334.ppp, _T_4502
node _T_4503 = bits(_WIRE_335, 6, 6)
connect _WIRE_334.pr, _T_4503
node _T_4504 = bits(_WIRE_335, 7, 7)
connect _WIRE_334.px, _T_4504
node _T_4505 = bits(_WIRE_335, 8, 8)
connect _WIRE_334.pw, _T_4505
node _T_4506 = bits(_WIRE_335, 9, 9)
connect _WIRE_334.hr, _T_4506
node _T_4507 = bits(_WIRE_335, 10, 10)
connect _WIRE_334.hx, _T_4507
node _T_4508 = bits(_WIRE_335, 11, 11)
connect _WIRE_334.hw, _T_4508
node _T_4509 = bits(_WIRE_335, 12, 12)
connect _WIRE_334.sr, _T_4509
node _T_4510 = bits(_WIRE_335, 13, 13)
connect _WIRE_334.sx, _T_4510
node _T_4511 = bits(_WIRE_335, 14, 14)
connect _WIRE_334.sw, _T_4511
node _T_4512 = bits(_WIRE_335, 15, 15)
connect _WIRE_334.gf, _T_4512
node _T_4513 = bits(_WIRE_335, 16, 16)
connect _WIRE_334.pf, _T_4513
node _T_4514 = bits(_WIRE_335, 17, 17)
connect _WIRE_334.ae_stage2, _T_4514
node _T_4515 = bits(_WIRE_335, 18, 18)
connect _WIRE_334.ae_final, _T_4515
node _T_4516 = bits(_WIRE_335, 19, 19)
connect _WIRE_334.ae_ptw, _T_4516
node _T_4517 = bits(_WIRE_335, 20, 20)
connect _WIRE_334.g, _T_4517
node _T_4518 = bits(_WIRE_335, 21, 21)
connect _WIRE_334.u, _T_4518
node _T_4519 = bits(_WIRE_335, 41, 22)
connect _WIRE_334.ppn, _T_4519
wire _WIRE_336 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_337 : UInt<42>
connect _WIRE_337, sectored_entries[0][6].data[1]
node _T_4520 = bits(_WIRE_337, 0, 0)
connect _WIRE_336.fragmented_superpage, _T_4520
node _T_4521 = bits(_WIRE_337, 1, 1)
connect _WIRE_336.c, _T_4521
node _T_4522 = bits(_WIRE_337, 2, 2)
connect _WIRE_336.eff, _T_4522
node _T_4523 = bits(_WIRE_337, 3, 3)
connect _WIRE_336.paa, _T_4523
node _T_4524 = bits(_WIRE_337, 4, 4)
connect _WIRE_336.pal, _T_4524
node _T_4525 = bits(_WIRE_337, 5, 5)
connect _WIRE_336.ppp, _T_4525
node _T_4526 = bits(_WIRE_337, 6, 6)
connect _WIRE_336.pr, _T_4526
node _T_4527 = bits(_WIRE_337, 7, 7)
connect _WIRE_336.px, _T_4527
node _T_4528 = bits(_WIRE_337, 8, 8)
connect _WIRE_336.pw, _T_4528
node _T_4529 = bits(_WIRE_337, 9, 9)
connect _WIRE_336.hr, _T_4529
node _T_4530 = bits(_WIRE_337, 10, 10)
connect _WIRE_336.hx, _T_4530
node _T_4531 = bits(_WIRE_337, 11, 11)
connect _WIRE_336.hw, _T_4531
node _T_4532 = bits(_WIRE_337, 12, 12)
connect _WIRE_336.sr, _T_4532
node _T_4533 = bits(_WIRE_337, 13, 13)
connect _WIRE_336.sx, _T_4533
node _T_4534 = bits(_WIRE_337, 14, 14)
connect _WIRE_336.sw, _T_4534
node _T_4535 = bits(_WIRE_337, 15, 15)
connect _WIRE_336.gf, _T_4535
node _T_4536 = bits(_WIRE_337, 16, 16)
connect _WIRE_336.pf, _T_4536
node _T_4537 = bits(_WIRE_337, 17, 17)
connect _WIRE_336.ae_stage2, _T_4537
node _T_4538 = bits(_WIRE_337, 18, 18)
connect _WIRE_336.ae_final, _T_4538
node _T_4539 = bits(_WIRE_337, 19, 19)
connect _WIRE_336.ae_ptw, _T_4539
node _T_4540 = bits(_WIRE_337, 20, 20)
connect _WIRE_336.g, _T_4540
node _T_4541 = bits(_WIRE_337, 21, 21)
connect _WIRE_336.u, _T_4541
node _T_4542 = bits(_WIRE_337, 41, 22)
connect _WIRE_336.ppn, _T_4542
wire _WIRE_338 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_339 : UInt<42>
connect _WIRE_339, sectored_entries[0][6].data[2]
node _T_4543 = bits(_WIRE_339, 0, 0)
connect _WIRE_338.fragmented_superpage, _T_4543
node _T_4544 = bits(_WIRE_339, 1, 1)
connect _WIRE_338.c, _T_4544
node _T_4545 = bits(_WIRE_339, 2, 2)
connect _WIRE_338.eff, _T_4545
node _T_4546 = bits(_WIRE_339, 3, 3)
connect _WIRE_338.paa, _T_4546
node _T_4547 = bits(_WIRE_339, 4, 4)
connect _WIRE_338.pal, _T_4547
node _T_4548 = bits(_WIRE_339, 5, 5)
connect _WIRE_338.ppp, _T_4548
node _T_4549 = bits(_WIRE_339, 6, 6)
connect _WIRE_338.pr, _T_4549
node _T_4550 = bits(_WIRE_339, 7, 7)
connect _WIRE_338.px, _T_4550
node _T_4551 = bits(_WIRE_339, 8, 8)
connect _WIRE_338.pw, _T_4551
node _T_4552 = bits(_WIRE_339, 9, 9)
connect _WIRE_338.hr, _T_4552
node _T_4553 = bits(_WIRE_339, 10, 10)
connect _WIRE_338.hx, _T_4553
node _T_4554 = bits(_WIRE_339, 11, 11)
connect _WIRE_338.hw, _T_4554
node _T_4555 = bits(_WIRE_339, 12, 12)
connect _WIRE_338.sr, _T_4555
node _T_4556 = bits(_WIRE_339, 13, 13)
connect _WIRE_338.sx, _T_4556
node _T_4557 = bits(_WIRE_339, 14, 14)
connect _WIRE_338.sw, _T_4557
node _T_4558 = bits(_WIRE_339, 15, 15)
connect _WIRE_338.gf, _T_4558
node _T_4559 = bits(_WIRE_339, 16, 16)
connect _WIRE_338.pf, _T_4559
node _T_4560 = bits(_WIRE_339, 17, 17)
connect _WIRE_338.ae_stage2, _T_4560
node _T_4561 = bits(_WIRE_339, 18, 18)
connect _WIRE_338.ae_final, _T_4561
node _T_4562 = bits(_WIRE_339, 19, 19)
connect _WIRE_338.ae_ptw, _T_4562
node _T_4563 = bits(_WIRE_339, 20, 20)
connect _WIRE_338.g, _T_4563
node _T_4564 = bits(_WIRE_339, 21, 21)
connect _WIRE_338.u, _T_4564
node _T_4565 = bits(_WIRE_339, 41, 22)
connect _WIRE_338.ppn, _T_4565
wire _WIRE_340 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_341 : UInt<42>
connect _WIRE_341, sectored_entries[0][6].data[3]
node _T_4566 = bits(_WIRE_341, 0, 0)
connect _WIRE_340.fragmented_superpage, _T_4566
node _T_4567 = bits(_WIRE_341, 1, 1)
connect _WIRE_340.c, _T_4567
node _T_4568 = bits(_WIRE_341, 2, 2)
connect _WIRE_340.eff, _T_4568
node _T_4569 = bits(_WIRE_341, 3, 3)
connect _WIRE_340.paa, _T_4569
node _T_4570 = bits(_WIRE_341, 4, 4)
connect _WIRE_340.pal, _T_4570
node _T_4571 = bits(_WIRE_341, 5, 5)
connect _WIRE_340.ppp, _T_4571
node _T_4572 = bits(_WIRE_341, 6, 6)
connect _WIRE_340.pr, _T_4572
node _T_4573 = bits(_WIRE_341, 7, 7)
connect _WIRE_340.px, _T_4573
node _T_4574 = bits(_WIRE_341, 8, 8)
connect _WIRE_340.pw, _T_4574
node _T_4575 = bits(_WIRE_341, 9, 9)
connect _WIRE_340.hr, _T_4575
node _T_4576 = bits(_WIRE_341, 10, 10)
connect _WIRE_340.hx, _T_4576
node _T_4577 = bits(_WIRE_341, 11, 11)
connect _WIRE_340.hw, _T_4577
node _T_4578 = bits(_WIRE_341, 12, 12)
connect _WIRE_340.sr, _T_4578
node _T_4579 = bits(_WIRE_341, 13, 13)
connect _WIRE_340.sx, _T_4579
node _T_4580 = bits(_WIRE_341, 14, 14)
connect _WIRE_340.sw, _T_4580
node _T_4581 = bits(_WIRE_341, 15, 15)
connect _WIRE_340.gf, _T_4581
node _T_4582 = bits(_WIRE_341, 16, 16)
connect _WIRE_340.pf, _T_4582
node _T_4583 = bits(_WIRE_341, 17, 17)
connect _WIRE_340.ae_stage2, _T_4583
node _T_4584 = bits(_WIRE_341, 18, 18)
connect _WIRE_340.ae_final, _T_4584
node _T_4585 = bits(_WIRE_341, 19, 19)
connect _WIRE_340.ae_ptw, _T_4585
node _T_4586 = bits(_WIRE_341, 20, 20)
connect _WIRE_340.g, _T_4586
node _T_4587 = bits(_WIRE_341, 21, 21)
connect _WIRE_340.u, _T_4587
node _T_4588 = bits(_WIRE_341, 41, 22)
connect _WIRE_340.ppn, _T_4588
node _T_4589 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1))
when _T_4589 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_4590 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1))
when _T_4590 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_4591 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1))
when _T_4591 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_4592 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1))
when _T_4592 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
wire _WIRE_342 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_343 : UInt<42>
connect _WIRE_343, sectored_entries[0][7].data[0]
node _T_4593 = bits(_WIRE_343, 0, 0)
connect _WIRE_342.fragmented_superpage, _T_4593
node _T_4594 = bits(_WIRE_343, 1, 1)
connect _WIRE_342.c, _T_4594
node _T_4595 = bits(_WIRE_343, 2, 2)
connect _WIRE_342.eff, _T_4595
node _T_4596 = bits(_WIRE_343, 3, 3)
connect _WIRE_342.paa, _T_4596
node _T_4597 = bits(_WIRE_343, 4, 4)
connect _WIRE_342.pal, _T_4597
node _T_4598 = bits(_WIRE_343, 5, 5)
connect _WIRE_342.ppp, _T_4598
node _T_4599 = bits(_WIRE_343, 6, 6)
connect _WIRE_342.pr, _T_4599
node _T_4600 = bits(_WIRE_343, 7, 7)
connect _WIRE_342.px, _T_4600
node _T_4601 = bits(_WIRE_343, 8, 8)
connect _WIRE_342.pw, _T_4601
node _T_4602 = bits(_WIRE_343, 9, 9)
connect _WIRE_342.hr, _T_4602
node _T_4603 = bits(_WIRE_343, 10, 10)
connect _WIRE_342.hx, _T_4603
node _T_4604 = bits(_WIRE_343, 11, 11)
connect _WIRE_342.hw, _T_4604
node _T_4605 = bits(_WIRE_343, 12, 12)
connect _WIRE_342.sr, _T_4605
node _T_4606 = bits(_WIRE_343, 13, 13)
connect _WIRE_342.sx, _T_4606
node _T_4607 = bits(_WIRE_343, 14, 14)
connect _WIRE_342.sw, _T_4607
node _T_4608 = bits(_WIRE_343, 15, 15)
connect _WIRE_342.gf, _T_4608
node _T_4609 = bits(_WIRE_343, 16, 16)
connect _WIRE_342.pf, _T_4609
node _T_4610 = bits(_WIRE_343, 17, 17)
connect _WIRE_342.ae_stage2, _T_4610
node _T_4611 = bits(_WIRE_343, 18, 18)
connect _WIRE_342.ae_final, _T_4611
node _T_4612 = bits(_WIRE_343, 19, 19)
connect _WIRE_342.ae_ptw, _T_4612
node _T_4613 = bits(_WIRE_343, 20, 20)
connect _WIRE_342.g, _T_4613
node _T_4614 = bits(_WIRE_343, 21, 21)
connect _WIRE_342.u, _T_4614
node _T_4615 = bits(_WIRE_343, 41, 22)
connect _WIRE_342.ppn, _T_4615
wire _WIRE_344 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_345 : UInt<42>
connect _WIRE_345, sectored_entries[0][7].data[1]
node _T_4616 = bits(_WIRE_345, 0, 0)
connect _WIRE_344.fragmented_superpage, _T_4616
node _T_4617 = bits(_WIRE_345, 1, 1)
connect _WIRE_344.c, _T_4617
node _T_4618 = bits(_WIRE_345, 2, 2)
connect _WIRE_344.eff, _T_4618
node _T_4619 = bits(_WIRE_345, 3, 3)
connect _WIRE_344.paa, _T_4619
node _T_4620 = bits(_WIRE_345, 4, 4)
connect _WIRE_344.pal, _T_4620
node _T_4621 = bits(_WIRE_345, 5, 5)
connect _WIRE_344.ppp, _T_4621
node _T_4622 = bits(_WIRE_345, 6, 6)
connect _WIRE_344.pr, _T_4622
node _T_4623 = bits(_WIRE_345, 7, 7)
connect _WIRE_344.px, _T_4623
node _T_4624 = bits(_WIRE_345, 8, 8)
connect _WIRE_344.pw, _T_4624
node _T_4625 = bits(_WIRE_345, 9, 9)
connect _WIRE_344.hr, _T_4625
node _T_4626 = bits(_WIRE_345, 10, 10)
connect _WIRE_344.hx, _T_4626
node _T_4627 = bits(_WIRE_345, 11, 11)
connect _WIRE_344.hw, _T_4627
node _T_4628 = bits(_WIRE_345, 12, 12)
connect _WIRE_344.sr, _T_4628
node _T_4629 = bits(_WIRE_345, 13, 13)
connect _WIRE_344.sx, _T_4629
node _T_4630 = bits(_WIRE_345, 14, 14)
connect _WIRE_344.sw, _T_4630
node _T_4631 = bits(_WIRE_345, 15, 15)
connect _WIRE_344.gf, _T_4631
node _T_4632 = bits(_WIRE_345, 16, 16)
connect _WIRE_344.pf, _T_4632
node _T_4633 = bits(_WIRE_345, 17, 17)
connect _WIRE_344.ae_stage2, _T_4633
node _T_4634 = bits(_WIRE_345, 18, 18)
connect _WIRE_344.ae_final, _T_4634
node _T_4635 = bits(_WIRE_345, 19, 19)
connect _WIRE_344.ae_ptw, _T_4635
node _T_4636 = bits(_WIRE_345, 20, 20)
connect _WIRE_344.g, _T_4636
node _T_4637 = bits(_WIRE_345, 21, 21)
connect _WIRE_344.u, _T_4637
node _T_4638 = bits(_WIRE_345, 41, 22)
connect _WIRE_344.ppn, _T_4638
wire _WIRE_346 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_347 : UInt<42>
connect _WIRE_347, sectored_entries[0][7].data[2]
node _T_4639 = bits(_WIRE_347, 0, 0)
connect _WIRE_346.fragmented_superpage, _T_4639
node _T_4640 = bits(_WIRE_347, 1, 1)
connect _WIRE_346.c, _T_4640
node _T_4641 = bits(_WIRE_347, 2, 2)
connect _WIRE_346.eff, _T_4641
node _T_4642 = bits(_WIRE_347, 3, 3)
connect _WIRE_346.paa, _T_4642
node _T_4643 = bits(_WIRE_347, 4, 4)
connect _WIRE_346.pal, _T_4643
node _T_4644 = bits(_WIRE_347, 5, 5)
connect _WIRE_346.ppp, _T_4644
node _T_4645 = bits(_WIRE_347, 6, 6)
connect _WIRE_346.pr, _T_4645
node _T_4646 = bits(_WIRE_347, 7, 7)
connect _WIRE_346.px, _T_4646
node _T_4647 = bits(_WIRE_347, 8, 8)
connect _WIRE_346.pw, _T_4647
node _T_4648 = bits(_WIRE_347, 9, 9)
connect _WIRE_346.hr, _T_4648
node _T_4649 = bits(_WIRE_347, 10, 10)
connect _WIRE_346.hx, _T_4649
node _T_4650 = bits(_WIRE_347, 11, 11)
connect _WIRE_346.hw, _T_4650
node _T_4651 = bits(_WIRE_347, 12, 12)
connect _WIRE_346.sr, _T_4651
node _T_4652 = bits(_WIRE_347, 13, 13)
connect _WIRE_346.sx, _T_4652
node _T_4653 = bits(_WIRE_347, 14, 14)
connect _WIRE_346.sw, _T_4653
node _T_4654 = bits(_WIRE_347, 15, 15)
connect _WIRE_346.gf, _T_4654
node _T_4655 = bits(_WIRE_347, 16, 16)
connect _WIRE_346.pf, _T_4655
node _T_4656 = bits(_WIRE_347, 17, 17)
connect _WIRE_346.ae_stage2, _T_4656
node _T_4657 = bits(_WIRE_347, 18, 18)
connect _WIRE_346.ae_final, _T_4657
node _T_4658 = bits(_WIRE_347, 19, 19)
connect _WIRE_346.ae_ptw, _T_4658
node _T_4659 = bits(_WIRE_347, 20, 20)
connect _WIRE_346.g, _T_4659
node _T_4660 = bits(_WIRE_347, 21, 21)
connect _WIRE_346.u, _T_4660
node _T_4661 = bits(_WIRE_347, 41, 22)
connect _WIRE_346.ppn, _T_4661
wire _WIRE_348 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_349 : UInt<42>
connect _WIRE_349, sectored_entries[0][7].data[3]
node _T_4662 = bits(_WIRE_349, 0, 0)
connect _WIRE_348.fragmented_superpage, _T_4662
node _T_4663 = bits(_WIRE_349, 1, 1)
connect _WIRE_348.c, _T_4663
node _T_4664 = bits(_WIRE_349, 2, 2)
connect _WIRE_348.eff, _T_4664
node _T_4665 = bits(_WIRE_349, 3, 3)
connect _WIRE_348.paa, _T_4665
node _T_4666 = bits(_WIRE_349, 4, 4)
connect _WIRE_348.pal, _T_4666
node _T_4667 = bits(_WIRE_349, 5, 5)
connect _WIRE_348.ppp, _T_4667
node _T_4668 = bits(_WIRE_349, 6, 6)
connect _WIRE_348.pr, _T_4668
node _T_4669 = bits(_WIRE_349, 7, 7)
connect _WIRE_348.px, _T_4669
node _T_4670 = bits(_WIRE_349, 8, 8)
connect _WIRE_348.pw, _T_4670
node _T_4671 = bits(_WIRE_349, 9, 9)
connect _WIRE_348.hr, _T_4671
node _T_4672 = bits(_WIRE_349, 10, 10)
connect _WIRE_348.hx, _T_4672
node _T_4673 = bits(_WIRE_349, 11, 11)
connect _WIRE_348.hw, _T_4673
node _T_4674 = bits(_WIRE_349, 12, 12)
connect _WIRE_348.sr, _T_4674
node _T_4675 = bits(_WIRE_349, 13, 13)
connect _WIRE_348.sx, _T_4675
node _T_4676 = bits(_WIRE_349, 14, 14)
connect _WIRE_348.sw, _T_4676
node _T_4677 = bits(_WIRE_349, 15, 15)
connect _WIRE_348.gf, _T_4677
node _T_4678 = bits(_WIRE_349, 16, 16)
connect _WIRE_348.pf, _T_4678
node _T_4679 = bits(_WIRE_349, 17, 17)
connect _WIRE_348.ae_stage2, _T_4679
node _T_4680 = bits(_WIRE_349, 18, 18)
connect _WIRE_348.ae_final, _T_4680
node _T_4681 = bits(_WIRE_349, 19, 19)
connect _WIRE_348.ae_ptw, _T_4681
node _T_4682 = bits(_WIRE_349, 20, 20)
connect _WIRE_348.g, _T_4682
node _T_4683 = bits(_WIRE_349, 21, 21)
connect _WIRE_348.u, _T_4683
node _T_4684 = bits(_WIRE_349, 41, 22)
connect _WIRE_348.ppn, _T_4684
node _T_4685 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1))
when _T_4685 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_4686 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1))
when _T_4686 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_4687 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1))
when _T_4687 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_4688 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1))
when _T_4688 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
wire _WIRE_350 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_351 : UInt<42>
connect _WIRE_351, superpage_entries[0].data[0]
node _T_4689 = bits(_WIRE_351, 0, 0)
connect _WIRE_350.fragmented_superpage, _T_4689
node _T_4690 = bits(_WIRE_351, 1, 1)
connect _WIRE_350.c, _T_4690
node _T_4691 = bits(_WIRE_351, 2, 2)
connect _WIRE_350.eff, _T_4691
node _T_4692 = bits(_WIRE_351, 3, 3)
connect _WIRE_350.paa, _T_4692
node _T_4693 = bits(_WIRE_351, 4, 4)
connect _WIRE_350.pal, _T_4693
node _T_4694 = bits(_WIRE_351, 5, 5)
connect _WIRE_350.ppp, _T_4694
node _T_4695 = bits(_WIRE_351, 6, 6)
connect _WIRE_350.pr, _T_4695
node _T_4696 = bits(_WIRE_351, 7, 7)
connect _WIRE_350.px, _T_4696
node _T_4697 = bits(_WIRE_351, 8, 8)
connect _WIRE_350.pw, _T_4697
node _T_4698 = bits(_WIRE_351, 9, 9)
connect _WIRE_350.hr, _T_4698
node _T_4699 = bits(_WIRE_351, 10, 10)
connect _WIRE_350.hx, _T_4699
node _T_4700 = bits(_WIRE_351, 11, 11)
connect _WIRE_350.hw, _T_4700
node _T_4701 = bits(_WIRE_351, 12, 12)
connect _WIRE_350.sr, _T_4701
node _T_4702 = bits(_WIRE_351, 13, 13)
connect _WIRE_350.sx, _T_4702
node _T_4703 = bits(_WIRE_351, 14, 14)
connect _WIRE_350.sw, _T_4703
node _T_4704 = bits(_WIRE_351, 15, 15)
connect _WIRE_350.gf, _T_4704
node _T_4705 = bits(_WIRE_351, 16, 16)
connect _WIRE_350.pf, _T_4705
node _T_4706 = bits(_WIRE_351, 17, 17)
connect _WIRE_350.ae_stage2, _T_4706
node _T_4707 = bits(_WIRE_351, 18, 18)
connect _WIRE_350.ae_final, _T_4707
node _T_4708 = bits(_WIRE_351, 19, 19)
connect _WIRE_350.ae_ptw, _T_4708
node _T_4709 = bits(_WIRE_351, 20, 20)
connect _WIRE_350.g, _T_4709
node _T_4710 = bits(_WIRE_351, 21, 21)
connect _WIRE_350.u, _T_4710
node _T_4711 = bits(_WIRE_351, 41, 22)
connect _WIRE_350.ppn, _T_4711
node _T_4712 = eq(superpage_entries[0].tag_v, UInt<1>(0h1))
when _T_4712 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
wire _WIRE_352 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_353 : UInt<42>
connect _WIRE_353, superpage_entries[1].data[0]
node _T_4713 = bits(_WIRE_353, 0, 0)
connect _WIRE_352.fragmented_superpage, _T_4713
node _T_4714 = bits(_WIRE_353, 1, 1)
connect _WIRE_352.c, _T_4714
node _T_4715 = bits(_WIRE_353, 2, 2)
connect _WIRE_352.eff, _T_4715
node _T_4716 = bits(_WIRE_353, 3, 3)
connect _WIRE_352.paa, _T_4716
node _T_4717 = bits(_WIRE_353, 4, 4)
connect _WIRE_352.pal, _T_4717
node _T_4718 = bits(_WIRE_353, 5, 5)
connect _WIRE_352.ppp, _T_4718
node _T_4719 = bits(_WIRE_353, 6, 6)
connect _WIRE_352.pr, _T_4719
node _T_4720 = bits(_WIRE_353, 7, 7)
connect _WIRE_352.px, _T_4720
node _T_4721 = bits(_WIRE_353, 8, 8)
connect _WIRE_352.pw, _T_4721
node _T_4722 = bits(_WIRE_353, 9, 9)
connect _WIRE_352.hr, _T_4722
node _T_4723 = bits(_WIRE_353, 10, 10)
connect _WIRE_352.hx, _T_4723
node _T_4724 = bits(_WIRE_353, 11, 11)
connect _WIRE_352.hw, _T_4724
node _T_4725 = bits(_WIRE_353, 12, 12)
connect _WIRE_352.sr, _T_4725
node _T_4726 = bits(_WIRE_353, 13, 13)
connect _WIRE_352.sx, _T_4726
node _T_4727 = bits(_WIRE_353, 14, 14)
connect _WIRE_352.sw, _T_4727
node _T_4728 = bits(_WIRE_353, 15, 15)
connect _WIRE_352.gf, _T_4728
node _T_4729 = bits(_WIRE_353, 16, 16)
connect _WIRE_352.pf, _T_4729
node _T_4730 = bits(_WIRE_353, 17, 17)
connect _WIRE_352.ae_stage2, _T_4730
node _T_4731 = bits(_WIRE_353, 18, 18)
connect _WIRE_352.ae_final, _T_4731
node _T_4732 = bits(_WIRE_353, 19, 19)
connect _WIRE_352.ae_ptw, _T_4732
node _T_4733 = bits(_WIRE_353, 20, 20)
connect _WIRE_352.g, _T_4733
node _T_4734 = bits(_WIRE_353, 21, 21)
connect _WIRE_352.u, _T_4734
node _T_4735 = bits(_WIRE_353, 41, 22)
connect _WIRE_352.ppn, _T_4735
node _T_4736 = eq(superpage_entries[1].tag_v, UInt<1>(0h1))
when _T_4736 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
wire _WIRE_354 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_355 : UInt<42>
connect _WIRE_355, superpage_entries[2].data[0]
node _T_4737 = bits(_WIRE_355, 0, 0)
connect _WIRE_354.fragmented_superpage, _T_4737
node _T_4738 = bits(_WIRE_355, 1, 1)
connect _WIRE_354.c, _T_4738
node _T_4739 = bits(_WIRE_355, 2, 2)
connect _WIRE_354.eff, _T_4739
node _T_4740 = bits(_WIRE_355, 3, 3)
connect _WIRE_354.paa, _T_4740
node _T_4741 = bits(_WIRE_355, 4, 4)
connect _WIRE_354.pal, _T_4741
node _T_4742 = bits(_WIRE_355, 5, 5)
connect _WIRE_354.ppp, _T_4742
node _T_4743 = bits(_WIRE_355, 6, 6)
connect _WIRE_354.pr, _T_4743
node _T_4744 = bits(_WIRE_355, 7, 7)
connect _WIRE_354.px, _T_4744
node _T_4745 = bits(_WIRE_355, 8, 8)
connect _WIRE_354.pw, _T_4745
node _T_4746 = bits(_WIRE_355, 9, 9)
connect _WIRE_354.hr, _T_4746
node _T_4747 = bits(_WIRE_355, 10, 10)
connect _WIRE_354.hx, _T_4747
node _T_4748 = bits(_WIRE_355, 11, 11)
connect _WIRE_354.hw, _T_4748
node _T_4749 = bits(_WIRE_355, 12, 12)
connect _WIRE_354.sr, _T_4749
node _T_4750 = bits(_WIRE_355, 13, 13)
connect _WIRE_354.sx, _T_4750
node _T_4751 = bits(_WIRE_355, 14, 14)
connect _WIRE_354.sw, _T_4751
node _T_4752 = bits(_WIRE_355, 15, 15)
connect _WIRE_354.gf, _T_4752
node _T_4753 = bits(_WIRE_355, 16, 16)
connect _WIRE_354.pf, _T_4753
node _T_4754 = bits(_WIRE_355, 17, 17)
connect _WIRE_354.ae_stage2, _T_4754
node _T_4755 = bits(_WIRE_355, 18, 18)
connect _WIRE_354.ae_final, _T_4755
node _T_4756 = bits(_WIRE_355, 19, 19)
connect _WIRE_354.ae_ptw, _T_4756
node _T_4757 = bits(_WIRE_355, 20, 20)
connect _WIRE_354.g, _T_4757
node _T_4758 = bits(_WIRE_355, 21, 21)
connect _WIRE_354.u, _T_4758
node _T_4759 = bits(_WIRE_355, 41, 22)
connect _WIRE_354.ppn, _T_4759
node _T_4760 = eq(superpage_entries[2].tag_v, UInt<1>(0h1))
when _T_4760 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
wire _WIRE_356 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_357 : UInt<42>
connect _WIRE_357, superpage_entries[3].data[0]
node _T_4761 = bits(_WIRE_357, 0, 0)
connect _WIRE_356.fragmented_superpage, _T_4761
node _T_4762 = bits(_WIRE_357, 1, 1)
connect _WIRE_356.c, _T_4762
node _T_4763 = bits(_WIRE_357, 2, 2)
connect _WIRE_356.eff, _T_4763
node _T_4764 = bits(_WIRE_357, 3, 3)
connect _WIRE_356.paa, _T_4764
node _T_4765 = bits(_WIRE_357, 4, 4)
connect _WIRE_356.pal, _T_4765
node _T_4766 = bits(_WIRE_357, 5, 5)
connect _WIRE_356.ppp, _T_4766
node _T_4767 = bits(_WIRE_357, 6, 6)
connect _WIRE_356.pr, _T_4767
node _T_4768 = bits(_WIRE_357, 7, 7)
connect _WIRE_356.px, _T_4768
node _T_4769 = bits(_WIRE_357, 8, 8)
connect _WIRE_356.pw, _T_4769
node _T_4770 = bits(_WIRE_357, 9, 9)
connect _WIRE_356.hr, _T_4770
node _T_4771 = bits(_WIRE_357, 10, 10)
connect _WIRE_356.hx, _T_4771
node _T_4772 = bits(_WIRE_357, 11, 11)
connect _WIRE_356.hw, _T_4772
node _T_4773 = bits(_WIRE_357, 12, 12)
connect _WIRE_356.sr, _T_4773
node _T_4774 = bits(_WIRE_357, 13, 13)
connect _WIRE_356.sx, _T_4774
node _T_4775 = bits(_WIRE_357, 14, 14)
connect _WIRE_356.sw, _T_4775
node _T_4776 = bits(_WIRE_357, 15, 15)
connect _WIRE_356.gf, _T_4776
node _T_4777 = bits(_WIRE_357, 16, 16)
connect _WIRE_356.pf, _T_4777
node _T_4778 = bits(_WIRE_357, 17, 17)
connect _WIRE_356.ae_stage2, _T_4778
node _T_4779 = bits(_WIRE_357, 18, 18)
connect _WIRE_356.ae_final, _T_4779
node _T_4780 = bits(_WIRE_357, 19, 19)
connect _WIRE_356.ae_ptw, _T_4780
node _T_4781 = bits(_WIRE_357, 20, 20)
connect _WIRE_356.g, _T_4781
node _T_4782 = bits(_WIRE_357, 21, 21)
connect _WIRE_356.u, _T_4782
node _T_4783 = bits(_WIRE_357, 41, 22)
connect _WIRE_356.ppn, _T_4783
node _T_4784 = eq(superpage_entries[3].tag_v, UInt<1>(0h1))
when _T_4784 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
wire _WIRE_358 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_359 : UInt<42>
connect _WIRE_359, special_entry.data[0]
node _T_4785 = bits(_WIRE_359, 0, 0)
connect _WIRE_358.fragmented_superpage, _T_4785
node _T_4786 = bits(_WIRE_359, 1, 1)
connect _WIRE_358.c, _T_4786
node _T_4787 = bits(_WIRE_359, 2, 2)
connect _WIRE_358.eff, _T_4787
node _T_4788 = bits(_WIRE_359, 3, 3)
connect _WIRE_358.paa, _T_4788
node _T_4789 = bits(_WIRE_359, 4, 4)
connect _WIRE_358.pal, _T_4789
node _T_4790 = bits(_WIRE_359, 5, 5)
connect _WIRE_358.ppp, _T_4790
node _T_4791 = bits(_WIRE_359, 6, 6)
connect _WIRE_358.pr, _T_4791
node _T_4792 = bits(_WIRE_359, 7, 7)
connect _WIRE_358.px, _T_4792
node _T_4793 = bits(_WIRE_359, 8, 8)
connect _WIRE_358.pw, _T_4793
node _T_4794 = bits(_WIRE_359, 9, 9)
connect _WIRE_358.hr, _T_4794
node _T_4795 = bits(_WIRE_359, 10, 10)
connect _WIRE_358.hx, _T_4795
node _T_4796 = bits(_WIRE_359, 11, 11)
connect _WIRE_358.hw, _T_4796
node _T_4797 = bits(_WIRE_359, 12, 12)
connect _WIRE_358.sr, _T_4797
node _T_4798 = bits(_WIRE_359, 13, 13)
connect _WIRE_358.sx, _T_4798
node _T_4799 = bits(_WIRE_359, 14, 14)
connect _WIRE_358.sw, _T_4799
node _T_4800 = bits(_WIRE_359, 15, 15)
connect _WIRE_358.gf, _T_4800
node _T_4801 = bits(_WIRE_359, 16, 16)
connect _WIRE_358.pf, _T_4801
node _T_4802 = bits(_WIRE_359, 17, 17)
connect _WIRE_358.ae_stage2, _T_4802
node _T_4803 = bits(_WIRE_359, 18, 18)
connect _WIRE_358.ae_final, _T_4803
node _T_4804 = bits(_WIRE_359, 19, 19)
connect _WIRE_358.ae_ptw, _T_4804
node _T_4805 = bits(_WIRE_359, 20, 20)
connect _WIRE_358.g, _T_4805
node _T_4806 = bits(_WIRE_359, 21, 21)
connect _WIRE_358.u, _T_4806
node _T_4807 = bits(_WIRE_359, 41, 22)
connect _WIRE_358.ppn, _T_4807
node _T_4808 = eq(special_entry.tag_v, UInt<1>(0h1))
when _T_4808 :
connect special_entry.valid[0], UInt<1>(0h0)
connect v_entries_use_stage1, vstage1_en
node _T_4809 = asUInt(reset)
node _T_4810 = or(multipleHits, _T_4809)
when _T_4810 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
connect superpage_entries[0].valid[0], UInt<1>(0h0)
connect superpage_entries[1].valid[0], UInt<1>(0h0)
connect superpage_entries[2].valid[0], UInt<1>(0h0)
connect superpage_entries[3].valid[0], UInt<1>(0h0)
connect special_entry.valid[0], UInt<1>(0h0)
node _T_4811 = and(io.ptw.req.ready, io.ptw.req.valid)
node _T_4812 = eq(io.ptw.req.ready, UInt<1>(0h0))
node _T_4813 = and(io.ptw.req.valid, _T_4812)
node _T_4814 = eq(state, UInt<2>(0h3))
node _T_4815 = eq(io.sfence.bits.rs1, UInt<1>(0h0))
node _T_4816 = and(io.sfence.valid, _T_4815)
node _T_4817 = eq(io.sfence.bits.rs2, UInt<1>(0h0))
node _T_4818 = and(_T_4816, _T_4817)
node _T_4819 = eq(io.sfence.bits.rs1, UInt<1>(0h0))
node _T_4820 = and(io.sfence.valid, _T_4819)
node _T_4821 = and(_T_4820, io.sfence.bits.rs2)
node _T_4822 = and(io.sfence.valid, io.sfence.bits.rs1)
node _T_4823 = eq(io.sfence.bits.rs2, UInt<1>(0h0))
node _T_4824 = and(_T_4822, _T_4823)
node _T_4825 = and(io.sfence.valid, io.sfence.bits.rs1)
node _T_4826 = and(_T_4825, io.sfence.bits.rs2) | module ITLB_2( // @[TLB.scala:318:7]
input clock, // @[TLB.scala:318:7]
input reset, // @[TLB.scala:318:7]
output io_req_ready, // @[TLB.scala:320:14]
input io_req_valid, // @[TLB.scala:320:14]
input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14]
input [1:0] io_req_bits_prv, // @[TLB.scala:320:14]
input io_req_bits_v, // @[TLB.scala:320:14]
output io_resp_miss, // @[TLB.scala:320:14]
output [31:0] io_resp_paddr, // @[TLB.scala:320:14]
output [39:0] io_resp_gpa, // @[TLB.scala:320:14]
output io_resp_pf_ld, // @[TLB.scala:320:14]
output io_resp_pf_inst, // @[TLB.scala:320:14]
output io_resp_ae_ld, // @[TLB.scala:320:14]
output io_resp_ae_inst, // @[TLB.scala:320:14]
output io_resp_ma_ld, // @[TLB.scala:320:14]
output io_resp_cacheable, // @[TLB.scala:320:14]
output io_resp_prefetchable, // @[TLB.scala:320:14]
input io_sfence_valid, // @[TLB.scala:320:14]
input io_sfence_bits_rs1, // @[TLB.scala:320:14]
input io_sfence_bits_rs2, // @[TLB.scala:320:14]
input [38:0] io_sfence_bits_addr, // @[TLB.scala:320:14]
input io_sfence_bits_asid, // @[TLB.scala:320:14]
input io_sfence_bits_hv, // @[TLB.scala:320:14]
input io_sfence_bits_hg, // @[TLB.scala:320:14]
input io_ptw_req_ready, // @[TLB.scala:320:14]
output io_ptw_req_valid, // @[TLB.scala:320:14]
output io_ptw_req_bits_valid, // @[TLB.scala:320:14]
output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14]
output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14]
input io_ptw_resp_valid, // @[TLB.scala:320:14]
input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14]
input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pf, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gf, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hr, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hw, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hx, // @[TLB.scala:320:14]
input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14]
input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14]
input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14]
input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14]
input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14]
input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14]
input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14]
input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14]
input io_ptw_status_debug, // @[TLB.scala:320:14]
input io_ptw_status_cease, // @[TLB.scala:320:14]
input io_ptw_status_wfi, // @[TLB.scala:320:14]
input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14]
input io_ptw_status_dv, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14]
input io_ptw_status_v, // @[TLB.scala:320:14]
input io_ptw_status_sd, // @[TLB.scala:320:14]
input io_ptw_status_mpv, // @[TLB.scala:320:14]
input io_ptw_status_gva, // @[TLB.scala:320:14]
input io_ptw_status_tsr, // @[TLB.scala:320:14]
input io_ptw_status_tw, // @[TLB.scala:320:14]
input io_ptw_status_tvm, // @[TLB.scala:320:14]
input io_ptw_status_mxr, // @[TLB.scala:320:14]
input io_ptw_status_sum, // @[TLB.scala:320:14]
input io_ptw_status_mprv, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14]
input io_ptw_status_spp, // @[TLB.scala:320:14]
input io_ptw_status_mpie, // @[TLB.scala:320:14]
input io_ptw_status_spie, // @[TLB.scala:320:14]
input io_ptw_status_mie, // @[TLB.scala:320:14]
input io_ptw_status_sie, // @[TLB.scala:320:14]
input io_ptw_hstatus_spvp, // @[TLB.scala:320:14]
input io_ptw_hstatus_spv, // @[TLB.scala:320:14]
input io_ptw_hstatus_gva, // @[TLB.scala:320:14]
input io_ptw_gstatus_debug, // @[TLB.scala:320:14]
input io_ptw_gstatus_cease, // @[TLB.scala:320:14]
input io_ptw_gstatus_wfi, // @[TLB.scala:320:14]
input [31:0] io_ptw_gstatus_isa, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_dprv, // @[TLB.scala:320:14]
input io_ptw_gstatus_dv, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_prv, // @[TLB.scala:320:14]
input io_ptw_gstatus_v, // @[TLB.scala:320:14]
input io_ptw_gstatus_sd, // @[TLB.scala:320:14]
input [22:0] io_ptw_gstatus_zero2, // @[TLB.scala:320:14]
input io_ptw_gstatus_mpv, // @[TLB.scala:320:14]
input io_ptw_gstatus_gva, // @[TLB.scala:320:14]
input io_ptw_gstatus_mbe, // @[TLB.scala:320:14]
input io_ptw_gstatus_sbe, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_sxl, // @[TLB.scala:320:14]
input [7:0] io_ptw_gstatus_zero1, // @[TLB.scala:320:14]
input io_ptw_gstatus_tsr, // @[TLB.scala:320:14]
input io_ptw_gstatus_tw, // @[TLB.scala:320:14]
input io_ptw_gstatus_tvm, // @[TLB.scala:320:14]
input io_ptw_gstatus_mxr, // @[TLB.scala:320:14]
input io_ptw_gstatus_sum, // @[TLB.scala:320:14]
input io_ptw_gstatus_mprv, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_fs, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_mpp, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_vs, // @[TLB.scala:320:14]
input io_ptw_gstatus_spp, // @[TLB.scala:320:14]
input io_ptw_gstatus_mpie, // @[TLB.scala:320:14]
input io_ptw_gstatus_ube, // @[TLB.scala:320:14]
input io_ptw_gstatus_spie, // @[TLB.scala:320:14]
input io_ptw_gstatus_upie, // @[TLB.scala:320:14]
input io_ptw_gstatus_mie, // @[TLB.scala:320:14]
input io_ptw_gstatus_hie, // @[TLB.scala:320:14]
input io_ptw_gstatus_sie, // @[TLB.scala:320:14]
input io_ptw_gstatus_uie, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_0_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_0_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_0_value, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_1_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_1_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_1_value, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_2_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_2_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_2_value, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_3_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_3_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_3_value, // @[TLB.scala:320:14]
input io_kill // @[TLB.scala:320:14]
);
wire [19:0] _entries_barrier_12_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hr; // @[package.scala:267:25]
wire [19:0] _entries_barrier_11_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_10_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_9_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_8_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_7_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_6_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_io_y_c; // @[package.scala:267:25]
wire _pma_io_resp_r; // @[TLB.scala:422:19]
wire _pma_io_resp_w; // @[TLB.scala:422:19]
wire _pma_io_resp_pp; // @[TLB.scala:422:19]
wire _pma_io_resp_al; // @[TLB.scala:422:19]
wire _pma_io_resp_aa; // @[TLB.scala:422:19]
wire _pma_io_resp_x; // @[TLB.scala:422:19]
wire _pma_io_resp_eff; // @[TLB.scala:422:19]
wire _pmp_io_r; // @[TLB.scala:416:19]
wire _pmp_io_w; // @[TLB.scala:416:19]
wire _pmp_io_x; // @[TLB.scala:416:19]
wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25]
wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7]
wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7]
wire [1:0] io_req_bits_prv_0 = io_req_bits_prv; // @[TLB.scala:318:7]
wire io_req_bits_v_0 = io_req_bits_v; // @[TLB.scala:318:7]
wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7]
wire io_sfence_bits_rs1_0 = io_sfence_bits_rs1; // @[TLB.scala:318:7]
wire io_sfence_bits_rs2_0 = io_sfence_bits_rs2; // @[TLB.scala:318:7]
wire [38:0] io_sfence_bits_addr_0 = io_sfence_bits_addr; // @[TLB.scala:318:7]
wire io_sfence_bits_asid_0 = io_sfence_bits_asid; // @[TLB.scala:318:7]
wire io_sfence_bits_hv_0 = io_sfence_bits_hv; // @[TLB.scala:318:7]
wire io_sfence_bits_hg_0 = io_sfence_bits_hg; // @[TLB.scala:318:7]
wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7]
wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7]
wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7]
wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7]
wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7]
wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7]
wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7]
wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7]
wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7]
wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7]
wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7]
wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7]
wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7]
wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7]
wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7]
wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7]
wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7]
wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7]
wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7]
wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7]
wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7]
wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7]
wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7]
wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7]
wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7]
wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7]
wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7]
wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7]
wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7]
wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[TLB.scala:318:7]
wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[TLB.scala:318:7]
wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[TLB.scala:318:7]
wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[TLB.scala:318:7]
wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[TLB.scala:318:7]
wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[TLB.scala:318:7]
wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[TLB.scala:318:7]
wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[TLB.scala:318:7]
wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sd_0 = io_ptw_gstatus_sd; // @[TLB.scala:318:7]
wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[TLB.scala:318:7]
wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[TLB.scala:318:7]
wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[TLB.scala:318:7]
wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[TLB.scala:318:7]
wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[TLB.scala:318:7]
wire io_kill_0 = io_kill; // @[TLB.scala:318:7]
wire io_req_bits_passthrough = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7]
wire io_resp_pf_st = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7]
wire io_resp_ae_st = 1'h0; // @[TLB.scala:318:7]
wire io_resp_ma_st = 1'h0; // @[TLB.scala:318:7]
wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7]
wire io_resp_must_alloc = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_mbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_sbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_ube = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_upie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_hie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_uie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[TLB.scala:318:7]
wire priv_v = 1'h0; // @[TLB.scala:369:34]
wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38]
wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68]
wire vstage1_en = 1'h0; // @[TLB.scala:376:48]
wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38]
wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68]
wire stage2_en = 1'h0; // @[TLB.scala:378:48]
wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52]
wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37]
wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78]
wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34]
wire _superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire _superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire _superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34]
wire refill_v = 1'h0; // @[TLB.scala:448:33]
wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24]
wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24]
wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84]
wire _waddr_T = 1'h0; // @[TLB.scala:477:45]
wire _mxr_T = 1'h0; // @[TLB.scala:518:36]
wire _cmd_lrsc_T = 1'h0; // @[package.scala:16:47]
wire _cmd_lrsc_T_1 = 1'h0; // @[package.scala:16:47]
wire _cmd_lrsc_T_2 = 1'h0; // @[package.scala:81:59]
wire cmd_lrsc = 1'h0; // @[TLB.scala:570:33]
wire _cmd_amo_logical_T = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_logical_T_1 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_logical_T_2 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_logical_T_3 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_logical_T_4 = 1'h0; // @[package.scala:81:59]
wire _cmd_amo_logical_T_5 = 1'h0; // @[package.scala:81:59]
wire _cmd_amo_logical_T_6 = 1'h0; // @[package.scala:81:59]
wire cmd_amo_logical = 1'h0; // @[TLB.scala:571:40]
wire _cmd_amo_arithmetic_T = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_1 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_2 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_3 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_4 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_5 = 1'h0; // @[package.scala:81:59]
wire _cmd_amo_arithmetic_T_6 = 1'h0; // @[package.scala:81:59]
wire _cmd_amo_arithmetic_T_7 = 1'h0; // @[package.scala:81:59]
wire _cmd_amo_arithmetic_T_8 = 1'h0; // @[package.scala:81:59]
wire cmd_amo_arithmetic = 1'h0; // @[TLB.scala:572:43]
wire cmd_put_partial = 1'h0; // @[TLB.scala:573:41]
wire _cmd_read_T_1 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_2 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_3 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_7 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_8 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_9 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_10 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_11 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_12 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_13 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_14 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_15 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_16 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_17 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_18 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_19 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_20 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_21 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_22 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_23 = 1'h0; // @[Consts.scala:87:44]
wire _cmd_readx_T = 1'h0; // @[TLB.scala:575:56]
wire cmd_readx = 1'h0; // @[TLB.scala:575:37]
wire _cmd_write_T = 1'h0; // @[Consts.scala:90:32]
wire _cmd_write_T_1 = 1'h0; // @[Consts.scala:90:49]
wire _cmd_write_T_2 = 1'h0; // @[Consts.scala:90:42]
wire _cmd_write_T_3 = 1'h0; // @[Consts.scala:90:66]
wire _cmd_write_T_4 = 1'h0; // @[Consts.scala:90:59]
wire _cmd_write_T_5 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_6 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_7 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_8 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_9 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_10 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_11 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_12 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_13 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_14 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_15 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_16 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_17 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_18 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_19 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_20 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_21 = 1'h0; // @[Consts.scala:87:44]
wire cmd_write = 1'h0; // @[Consts.scala:90:76]
wire _cmd_write_perms_T = 1'h0; // @[package.scala:16:47]
wire _cmd_write_perms_T_1 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_perms_T_2 = 1'h0; // @[package.scala:81:59]
wire cmd_write_perms = 1'h0; // @[TLB.scala:577:35]
wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32]
wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32]
wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37]
wire _io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28]
wire _io_resp_pf_st_T_2 = 1'h0; // @[TLB.scala:634:72]
wire _io_resp_pf_st_T_3 = 1'h0; // @[TLB.scala:634:48]
wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29]
wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66]
wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42]
wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29]
wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73]
wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49]
wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56]
wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30]
wire _io_resp_ae_st_T_1 = 1'h0; // @[TLB.scala:642:41]
wire _io_resp_ma_st_T = 1'h0; // @[TLB.scala:646:31]
wire _io_resp_must_alloc_T_1 = 1'h0; // @[TLB.scala:649:51]
wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36]
wire hv = 1'h0; // @[TLB.scala:721:36]
wire hg = 1'h0; // @[TLB.scala:722:36]
wire hv_1 = 1'h0; // @[TLB.scala:721:36]
wire hg_1 = 1'h0; // @[TLB.scala:722:36]
wire hv_2 = 1'h0; // @[TLB.scala:721:36]
wire hg_2 = 1'h0; // @[TLB.scala:722:36]
wire hv_3 = 1'h0; // @[TLB.scala:721:36]
wire hg_3 = 1'h0; // @[TLB.scala:722:36]
wire hv_4 = 1'h0; // @[TLB.scala:721:36]
wire hg_4 = 1'h0; // @[TLB.scala:722:36]
wire hv_5 = 1'h0; // @[TLB.scala:721:36]
wire hg_5 = 1'h0; // @[TLB.scala:722:36]
wire hv_6 = 1'h0; // @[TLB.scala:721:36]
wire hg_6 = 1'h0; // @[TLB.scala:722:36]
wire hv_7 = 1'h0; // @[TLB.scala:721:36]
wire hg_7 = 1'h0; // @[TLB.scala:722:36]
wire hv_8 = 1'h0; // @[TLB.scala:721:36]
wire hg_8 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T = 1'h0; // @[TLB.scala:182:28]
wire ignore = 1'h0; // @[TLB.scala:182:34]
wire hv_9 = 1'h0; // @[TLB.scala:721:36]
wire hg_9 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire hv_10 = 1'h0; // @[TLB.scala:721:36]
wire hg_10 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire hv_11 = 1'h0; // @[TLB.scala:721:36]
wire hg_11 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire hv_12 = 1'h0; // @[TLB.scala:721:36]
wire hg_12 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_12 = 1'h0; // @[TLB.scala:182:28]
wire ignore_12 = 1'h0; // @[TLB.scala:182:34]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7]
wire [15:0] satp_asid = 16'h0; // @[TLB.scala:373:17]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[TLB.scala:318:7]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_xs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7]
wire [4:0] io_req_bits_cmd = 5'h0; // @[TLB.scala:318:7]
wire [4:0] io_resp_cmd = 5'h0; // @[TLB.scala:318:7]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7]
wire [1:0] io_req_bits_size = 2'h2; // @[TLB.scala:318:7]
wire [1:0] io_resp_size = 2'h2; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_sxl = 2'h2; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_uxl = 2'h2; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[TLB.scala:318:7]
wire _vm_enabled_T_2 = 1'h1; // @[TLB.scala:399:64]
wire _vsatp_mode_mismatch_T_2 = 1'h1; // @[TLB.scala:403:81]
wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22]
wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40]
wire superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40]
wire superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40]
wire superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40]
wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34]
wire ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34]
wire ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34]
wire ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34]
wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42]
wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26]
wire _cmd_read_T = 1'h1; // @[package.scala:16:47]
wire _cmd_read_T_4 = 1'h1; // @[package.scala:81:59]
wire _cmd_read_T_5 = 1'h1; // @[package.scala:81:59]
wire _cmd_read_T_6 = 1'h1; // @[package.scala:81:59]
wire cmd_read = 1'h1; // @[Consts.scala:89:68]
wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107]
wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32]
wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20]
wire ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire [13:0] _ae_array_T_2 = 14'h0; // @[TLB.scala:583:8]
wire [13:0] _ae_st_array_T_2 = 14'h0; // @[TLB.scala:588:8]
wire [13:0] _ae_st_array_T_4 = 14'h0; // @[TLB.scala:589:8]
wire [13:0] _ae_st_array_T_5 = 14'h0; // @[TLB.scala:588:53]
wire [13:0] _ae_st_array_T_7 = 14'h0; // @[TLB.scala:590:8]
wire [13:0] _ae_st_array_T_8 = 14'h0; // @[TLB.scala:589:53]
wire [13:0] _ae_st_array_T_10 = 14'h0; // @[TLB.scala:591:8]
wire [13:0] ae_st_array = 14'h0; // @[TLB.scala:590:53]
wire [13:0] _must_alloc_array_T_1 = 14'h0; // @[TLB.scala:593:8]
wire [13:0] _must_alloc_array_T_3 = 14'h0; // @[TLB.scala:594:8]
wire [13:0] _must_alloc_array_T_4 = 14'h0; // @[TLB.scala:593:43]
wire [13:0] _must_alloc_array_T_6 = 14'h0; // @[TLB.scala:595:8]
wire [13:0] _must_alloc_array_T_7 = 14'h0; // @[TLB.scala:594:43]
wire [13:0] _must_alloc_array_T_9 = 14'h0; // @[TLB.scala:596:8]
wire [13:0] must_alloc_array = 14'h0; // @[TLB.scala:595:46]
wire [13:0] pf_st_array = 14'h0; // @[TLB.scala:598:24]
wire [13:0] _gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46]
wire [13:0] gf_ld_array = 14'h0; // @[TLB.scala:600:24]
wire [13:0] _gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53]
wire [13:0] gf_st_array = 14'h0; // @[TLB.scala:601:24]
wire [13:0] _gf_inst_array_T = 14'h0; // @[TLB.scala:602:36]
wire [13:0] gf_inst_array = 14'h0; // @[TLB.scala:602:26]
wire [13:0] _io_resp_pf_st_T_1 = 14'h0; // @[TLB.scala:634:64]
wire [13:0] _io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58]
wire [13:0] _io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65]
wire [13:0] _io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48]
wire [13:0] _io_resp_ae_st_T = 14'h0; // @[TLB.scala:642:33]
wire [13:0] _io_resp_must_alloc_T = 14'h0; // @[TLB.scala:649:43]
wire [6:0] _state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25]
wire [12:0] stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27]
wire [12:0] _hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111]
wire [12:0] _hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55]
wire [12:0] _hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55]
wire [12:0] _gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88]
wire [12:0] gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82]
wire [12:0] _gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16]
wire [12:0] gpa_hits = 13'h1FFF; // @[TLB.scala:607:14]
wire [12:0] _stage1_bypass_T = 13'h0; // @[TLB.scala:517:27]
wire [12:0] stage1_bypass = 13'h0; // @[TLB.scala:517:61]
wire [12:0] _gpa_hits_T = 13'h0; // @[TLB.scala:607:30]
wire [13:0] hr_array = 14'h3FFF; // @[TLB.scala:524:21]
wire [13:0] hw_array = 14'h3FFF; // @[TLB.scala:525:21]
wire [13:0] hx_array = 14'h3FFF; // @[TLB.scala:526:21]
wire [13:0] _must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19]
wire [13:0] _gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50]
wire [3:0] _misaligned_T_2 = 4'h3; // @[TLB.scala:550:69]
wire [4:0] _misaligned_T_1 = 5'h3; // @[TLB.scala:550:69]
wire [3:0] _misaligned_T = 4'h4; // @[OneHot.scala:58:35]
wire _io_req_ready_T; // @[TLB.scala:631:25]
wire _io_resp_miss_T_2; // @[TLB.scala:651:64]
wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23]
wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8]
wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41]
wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29]
wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41]
wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41]
wire _io_resp_ma_ld_T; // @[TLB.scala:645:31]
wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41]
wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59]
wire _io_ptw_req_valid_T; // @[TLB.scala:662:29]
wire _io_ptw_req_bits_valid_T; // @[TLB.scala:663:28]
wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29]
wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24]
wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13]
wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17]
wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17]
wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31]
wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16]
wire io_req_ready_0; // @[TLB.scala:318:7]
wire io_resp_pf_ld_0; // @[TLB.scala:318:7]
wire io_resp_pf_inst_0; // @[TLB.scala:318:7]
wire io_resp_ae_ld_0; // @[TLB.scala:318:7]
wire io_resp_ae_inst_0; // @[TLB.scala:318:7]
wire io_resp_ma_ld_0; // @[TLB.scala:318:7]
wire io_resp_miss_0; // @[TLB.scala:318:7]
wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7]
wire [39:0] io_resp_gpa_0; // @[TLB.scala:318:7]
wire io_resp_cacheable_0; // @[TLB.scala:318:7]
wire io_resp_prefetchable_0; // @[TLB.scala:318:7]
wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_valid_0; // @[TLB.scala:318:7]
wire io_ptw_req_valid_0; // @[TLB.scala:318:7]
wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30]
wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] _ppn_T_13 = vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] _ppn_T_21 = vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] _ppn_T_29 = vpn; // @[TLB.scala:198:28, :335:30]
reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_4_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_4_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_4_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_5_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_5_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_5_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_6_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_6_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_6_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_7_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_7_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_7_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_3; // @[TLB.scala:339:29]
reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_0_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_17 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_0_valid_0; // @[TLB.scala:341:30]
reg [1:0] superpage_entries_1_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_1_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_1_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_1_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_19 = superpage_entries_1_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_1_valid_0; // @[TLB.scala:341:30]
reg [1:0] superpage_entries_2_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_2_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_2_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_2_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_21 = superpage_entries_2_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_2_valid_0; // @[TLB.scala:341:30]
reg [1:0] superpage_entries_3_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_3_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_3_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_3_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_23 = superpage_entries_3_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_3_valid_0; // @[TLB.scala:341:30]
reg [1:0] special_entry_level; // @[TLB.scala:346:56]
reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56]
reg special_entry_tag_v; // @[TLB.scala:346:56]
reg [41:0] special_entry_data_0; // @[TLB.scala:346:56]
wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56]
wire [41:0] _entries_WIRE_25 = special_entry_data_0; // @[TLB.scala:170:77, :346:56]
reg special_entry_valid_0; // @[TLB.scala:346:56]
reg [1:0] state; // @[TLB.scala:352:22]
reg [26:0] r_refill_tag; // @[TLB.scala:354:25]
assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25]
reg [1:0] r_superpage_repl_addr; // @[TLB.scala:355:34]
wire [1:0] waddr = r_superpage_repl_addr; // @[TLB.scala:355:34, :477:22]
reg [2:0] r_sectored_repl_addr; // @[TLB.scala:356:33]
reg r_sectored_hit_valid; // @[TLB.scala:357:27]
reg [2:0] r_sectored_hit_bits; // @[TLB.scala:357:27]
reg r_superpage_hit_valid; // @[TLB.scala:358:28]
reg [1:0] r_superpage_hit_bits; // @[TLB.scala:358:28]
reg r_need_gpa; // @[TLB.scala:361:23]
assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23]
reg r_gpa_valid; // @[TLB.scala:362:24]
reg [38:0] r_gpa; // @[TLB.scala:363:18]
reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22]
reg r_gpa_is_pte; // @[TLB.scala:365:25]
wire priv_s = io_req_bits_prv_0[0]; // @[TLB.scala:318:7, :370:20]
wire priv_uses_vm = ~(io_req_bits_prv_0[1]); // @[TLB.scala:318:7, :372:27]
wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41]
wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}]
wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31]
wire _vm_enabled_T_1 = _vm_enabled_T & priv_uses_vm; // @[TLB.scala:372:27, :399:{31,45}]
wire vm_enabled = _vm_enabled_T_1; // @[TLB.scala:399:{45,61}]
wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32]
wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29]
wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44]
wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24]
wire _mpu_priv_T = do_refill; // @[TLB.scala:408:29, :415:52]
wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29]
wire _T_51 = state == 2'h1; // @[package.scala:16:47]
wire _invalidate_refill_T; // @[package.scala:16:47]
assign _invalidate_refill_T = _T_51; // @[package.scala:16:47]
assign _io_ptw_req_valid_T = _T_51; // @[package.scala:16:47]
wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47]
wire _invalidate_refill_T_2 = _invalidate_refill_T | _invalidate_refill_T_1; // @[package.scala:16:47, :81:59]
wire invalidate_refill = _invalidate_refill_T_2 | io_sfence_valid_0; // @[package.scala:81:59]
wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77]
wire _mpu_ppn_T_22; // @[TLB.scala:170:77]
wire _mpu_ppn_T_21; // @[TLB.scala:170:77]
wire _mpu_ppn_T_20; // @[TLB.scala:170:77]
wire _mpu_ppn_T_19; // @[TLB.scala:170:77]
wire _mpu_ppn_T_18; // @[TLB.scala:170:77]
wire _mpu_ppn_T_17; // @[TLB.scala:170:77]
wire _mpu_ppn_T_16; // @[TLB.scala:170:77]
wire _mpu_ppn_T_15; // @[TLB.scala:170:77]
wire _mpu_ppn_T_14; // @[TLB.scala:170:77]
wire _mpu_ppn_T_13; // @[TLB.scala:170:77]
wire _mpu_ppn_T_12; // @[TLB.scala:170:77]
wire _mpu_ppn_T_11; // @[TLB.scala:170:77]
wire _mpu_ppn_T_10; // @[TLB.scala:170:77]
wire _mpu_ppn_T_9; // @[TLB.scala:170:77]
wire _mpu_ppn_T_8; // @[TLB.scala:170:77]
wire _mpu_ppn_T_7; // @[TLB.scala:170:77]
wire _mpu_ppn_T_6; // @[TLB.scala:170:77]
wire _mpu_ppn_T_5; // @[TLB.scala:170:77]
wire _mpu_ppn_T_4; // @[TLB.scala:170:77]
wire _mpu_ppn_T_3; // @[TLB.scala:170:77]
wire _mpu_ppn_T_2; // @[TLB.scala:170:77]
wire _mpu_ppn_T_1; // @[TLB.scala:170:77]
assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77]
assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77]
assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77]
assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77]
assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77]
assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77]
assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77]
assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77]
assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77]
assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77]
assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77]
assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77]
assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77]
assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77]
assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77]
assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77]
assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77]
assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77]
assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77]
assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77]
assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77]
assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77]
assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77]
wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25]
wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56]
wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28]
assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28]
wire _hitsVec_ignore_T_13; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28]
wire _ppn_ignore_T_8; // @[TLB.scala:197:28]
assign _ppn_ignore_T_8 = _GEN; // @[TLB.scala:197:28]
wire _ignore_T_13; // @[TLB.scala:182:28]
assign _ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28]
wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}]
wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}]
wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56]
wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}]
wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}]
wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146]
wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}]
wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20]
wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52]
wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46]
wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82]
wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}]
wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25]
wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25]
wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}]
wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, io_req_bits_prv_0}; // @[TLB.scala:318:7, :415:103]
wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}]
wire cacheable; // @[TLB.scala:425:41]
wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24]
wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46]
wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65]
wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31]
assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31]
assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46]
wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31]
assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31]
assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31]
assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31]
assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31]
assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46]
wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46]
wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46]
wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46]
wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31]
assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31]
assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31]
assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46]
wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46]
wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46]
wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15]
wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31]
assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31]
assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31]
assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46]
wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_51 = _homogeneous_T_50 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_52 = _homogeneous_T_51 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_53 = _homogeneous_T_52 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_54 = _homogeneous_T_53 | _homogeneous_T_24; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_55 = _homogeneous_T_54 | _homogeneous_T_29; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_56 = _homogeneous_T_55 | _homogeneous_T_34; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_57 = _homogeneous_T_56 | _homogeneous_T_39; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_58 = _homogeneous_T_57 | _homogeneous_T_44; // @[TLBPermissions.scala:101:65]
wire homogeneous = _homogeneous_T_58 | _homogeneous_T_49; // @[TLBPermissions.scala:101:65]
wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46]
wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}]
wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46]
wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46]
wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46]
wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46]
wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46]
wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_93 = _homogeneous_T_92 | _homogeneous_T_76; // @[TLBPermissions.scala:85:66]
wire _homogeneous_T_94 = _homogeneous_T_93 | _homogeneous_T_81; // @[TLBPermissions.scala:85:66]
wire _homogeneous_T_95 = _homogeneous_T_94 | _homogeneous_T_86; // @[TLBPermissions.scala:85:66]
wire _homogeneous_T_96 = _homogeneous_T_95 | _homogeneous_T_91; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46]
wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46]
wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_108 = _homogeneous_T_107 | _homogeneous_T_106; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46]
wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}]
wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46]
wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}]
wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39]
wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46]
wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}]
wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33]
wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}]
wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}]
wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24]
wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33]
wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}]
wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}]
wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24]
wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33]
wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}]
wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}]
wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24]
wire _GEN_4 = sectored_entries_0_0_valid_0 | sectored_entries_0_0_valid_1; // @[package.scala:81:59]
wire _sector_hits_T; // @[package.scala:81:59]
assign _sector_hits_T = _GEN_4; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T = _GEN_4; // @[package.scala:81:59]
wire _sector_hits_T_1 = _sector_hits_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_2 = _sector_hits_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59]
wire [26:0] _T_176 = sectored_entries_0_0_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_3; // @[TLB.scala:174:61]
assign _sector_hits_T_3 = _T_176; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T; // @[TLB.scala:174:61]
assign _hitsVec_T = _T_176; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_4 = _sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_5 = _sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_6 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_7 = _sector_hits_T_5 & _sector_hits_T_6; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_0 = _sector_hits_T_2 & _sector_hits_T_7; // @[package.scala:81:59]
wire _GEN_5 = sectored_entries_0_1_valid_0 | sectored_entries_0_1_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_8; // @[package.scala:81:59]
assign _sector_hits_T_8 = _GEN_5; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_3; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_3 = _GEN_5; // @[package.scala:81:59]
wire _sector_hits_T_9 = _sector_hits_T_8 | sectored_entries_0_1_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_10 = _sector_hits_T_9 | sectored_entries_0_1_valid_3; // @[package.scala:81:59]
wire [26:0] _T_597 = sectored_entries_0_1_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_11; // @[TLB.scala:174:61]
assign _sector_hits_T_11 = _T_597; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61]
assign _hitsVec_T_6 = _T_597; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_12 = _sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_13 = _sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_14 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_15 = _sector_hits_T_13 & _sector_hits_T_14; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_1 = _sector_hits_T_10 & _sector_hits_T_15; // @[package.scala:81:59]
wire _GEN_6 = sectored_entries_0_2_valid_0 | sectored_entries_0_2_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_16; // @[package.scala:81:59]
assign _sector_hits_T_16 = _GEN_6; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_6; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_6 = _GEN_6; // @[package.scala:81:59]
wire _sector_hits_T_17 = _sector_hits_T_16 | sectored_entries_0_2_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_18 = _sector_hits_T_17 | sectored_entries_0_2_valid_3; // @[package.scala:81:59]
wire [26:0] _T_1018 = sectored_entries_0_2_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_19; // @[TLB.scala:174:61]
assign _sector_hits_T_19 = _T_1018; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61]
assign _hitsVec_T_12 = _T_1018; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_20 = _sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_21 = _sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_22 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_23 = _sector_hits_T_21 & _sector_hits_T_22; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_2 = _sector_hits_T_18 & _sector_hits_T_23; // @[package.scala:81:59]
wire _GEN_7 = sectored_entries_0_3_valid_0 | sectored_entries_0_3_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_24; // @[package.scala:81:59]
assign _sector_hits_T_24 = _GEN_7; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_9; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_9 = _GEN_7; // @[package.scala:81:59]
wire _sector_hits_T_25 = _sector_hits_T_24 | sectored_entries_0_3_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_26 = _sector_hits_T_25 | sectored_entries_0_3_valid_3; // @[package.scala:81:59]
wire [26:0] _T_1439 = sectored_entries_0_3_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_27; // @[TLB.scala:174:61]
assign _sector_hits_T_27 = _T_1439; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61]
assign _hitsVec_T_18 = _T_1439; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_28 = _sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_29 = _sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_30 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_31 = _sector_hits_T_29 & _sector_hits_T_30; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_3 = _sector_hits_T_26 & _sector_hits_T_31; // @[package.scala:81:59]
wire _GEN_8 = sectored_entries_0_4_valid_0 | sectored_entries_0_4_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_32; // @[package.scala:81:59]
assign _sector_hits_T_32 = _GEN_8; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_12; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_12 = _GEN_8; // @[package.scala:81:59]
wire _sector_hits_T_33 = _sector_hits_T_32 | sectored_entries_0_4_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_34 = _sector_hits_T_33 | sectored_entries_0_4_valid_3; // @[package.scala:81:59]
wire [26:0] _T_1860 = sectored_entries_0_4_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_35; // @[TLB.scala:174:61]
assign _sector_hits_T_35 = _T_1860; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_24; // @[TLB.scala:174:61]
assign _hitsVec_T_24 = _T_1860; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_36 = _sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_37 = _sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_38 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_39 = _sector_hits_T_37 & _sector_hits_T_38; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_4 = _sector_hits_T_34 & _sector_hits_T_39; // @[package.scala:81:59]
wire _GEN_9 = sectored_entries_0_5_valid_0 | sectored_entries_0_5_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_40; // @[package.scala:81:59]
assign _sector_hits_T_40 = _GEN_9; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_15; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_15 = _GEN_9; // @[package.scala:81:59]
wire _sector_hits_T_41 = _sector_hits_T_40 | sectored_entries_0_5_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_42 = _sector_hits_T_41 | sectored_entries_0_5_valid_3; // @[package.scala:81:59]
wire [26:0] _T_2281 = sectored_entries_0_5_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_43; // @[TLB.scala:174:61]
assign _sector_hits_T_43 = _T_2281; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_30; // @[TLB.scala:174:61]
assign _hitsVec_T_30 = _T_2281; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_44 = _sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_45 = _sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_46 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_47 = _sector_hits_T_45 & _sector_hits_T_46; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_5 = _sector_hits_T_42 & _sector_hits_T_47; // @[package.scala:81:59]
wire _GEN_10 = sectored_entries_0_6_valid_0 | sectored_entries_0_6_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_48; // @[package.scala:81:59]
assign _sector_hits_T_48 = _GEN_10; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_18; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_18 = _GEN_10; // @[package.scala:81:59]
wire _sector_hits_T_49 = _sector_hits_T_48 | sectored_entries_0_6_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_50 = _sector_hits_T_49 | sectored_entries_0_6_valid_3; // @[package.scala:81:59]
wire [26:0] _T_2702 = sectored_entries_0_6_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_51; // @[TLB.scala:174:61]
assign _sector_hits_T_51 = _T_2702; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_36; // @[TLB.scala:174:61]
assign _hitsVec_T_36 = _T_2702; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_52 = _sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_53 = _sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_54 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_55 = _sector_hits_T_53 & _sector_hits_T_54; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_6 = _sector_hits_T_50 & _sector_hits_T_55; // @[package.scala:81:59]
wire _GEN_11 = sectored_entries_0_7_valid_0 | sectored_entries_0_7_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_56; // @[package.scala:81:59]
assign _sector_hits_T_56 = _GEN_11; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_21; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_21 = _GEN_11; // @[package.scala:81:59]
wire _sector_hits_T_57 = _sector_hits_T_56 | sectored_entries_0_7_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_58 = _sector_hits_T_57 | sectored_entries_0_7_valid_3; // @[package.scala:81:59]
wire [26:0] _T_3123 = sectored_entries_0_7_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_59; // @[TLB.scala:174:61]
assign _sector_hits_T_59 = _T_3123; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_42; // @[TLB.scala:174:61]
assign _hitsVec_T_42 = _T_3123; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_60 = _sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_61 = _sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_62 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_63 = _sector_hits_T_61 & _sector_hits_T_62; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_7 = _sector_hits_T_58 & _sector_hits_T_63; // @[package.scala:81:59]
wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3446 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52]
assign _superpage_hits_T = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52]
assign _superpage_hits_T_5 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52]
assign _superpage_hits_T_10 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_48; // @[TLB.scala:183:52]
assign _hitsVec_T_48 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_53; // @[TLB.scala:183:52]
assign _hitsVec_T_53 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_58; // @[TLB.scala:183:52]
assign _hitsVec_T_58 = _T_3446; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_12 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28]
wire _ppn_ignore_T; // @[TLB.scala:197:28]
assign _ppn_ignore_T = _GEN_12; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_1; // @[TLB.scala:182:28]
assign _ignore_T_1 = _GEN_12; // @[TLB.scala:182:28]
wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_8 = superpage_hits_ignore_1 | _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}]
wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch_1 = superpage_entries_1_valid_0 & _superpage_hits_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3544 = superpage_entries_1_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T_14; // @[TLB.scala:183:52]
assign _superpage_hits_T_14 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_19; // @[TLB.scala:183:52]
assign _superpage_hits_T_19 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_24; // @[TLB.scala:183:52]
assign _superpage_hits_T_24 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_63; // @[TLB.scala:183:52]
assign _hitsVec_T_63 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_68; // @[TLB.scala:183:52]
assign _hitsVec_T_68 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_73; // @[TLB.scala:183:52]
assign _hitsVec_T_73 = _T_3544; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_15 = _superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_16 = _superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_17 = _superpage_hits_T_16; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_18 = superpage_hits_tagMatch_1 & _superpage_hits_T_17; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_13 = superpage_entries_1_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_4; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28]
wire _ppn_ignore_T_2; // @[TLB.scala:197:28]
assign _ppn_ignore_T_2 = _GEN_13; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_4; // @[TLB.scala:182:28]
assign _ignore_T_4 = _GEN_13; // @[TLB.scala:182:28]
wire superpage_hits_ignore_4 = _superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_20 = _superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_21 = _superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_22 = superpage_hits_ignore_4 | _superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_23 = _superpage_hits_T_18 & _superpage_hits_T_22; // @[TLB.scala:183:{29,40}]
wire superpage_hits_1 = _superpage_hits_T_23; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_25 = _superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_26 = _superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch_2 = superpage_entries_2_valid_0 & _superpage_hits_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3642 = superpage_entries_2_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T_28; // @[TLB.scala:183:52]
assign _superpage_hits_T_28 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_33; // @[TLB.scala:183:52]
assign _superpage_hits_T_33 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_38; // @[TLB.scala:183:52]
assign _superpage_hits_T_38 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_78; // @[TLB.scala:183:52]
assign _hitsVec_T_78 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_83; // @[TLB.scala:183:52]
assign _hitsVec_T_83 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_88; // @[TLB.scala:183:52]
assign _hitsVec_T_88 = _T_3642; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_29 = _superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_30 = _superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_31 = _superpage_hits_T_30; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_32 = superpage_hits_tagMatch_2 & _superpage_hits_T_31; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_14 = superpage_entries_2_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_7; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_7; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28]
wire _ppn_ignore_T_4; // @[TLB.scala:197:28]
assign _ppn_ignore_T_4 = _GEN_14; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_7; // @[TLB.scala:182:28]
assign _ignore_T_7 = _GEN_14; // @[TLB.scala:182:28]
wire superpage_hits_ignore_7 = _superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_34 = _superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_35 = _superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_36 = superpage_hits_ignore_7 | _superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_37 = _superpage_hits_T_32 & _superpage_hits_T_36; // @[TLB.scala:183:{29,40}]
wire superpage_hits_2 = _superpage_hits_T_37; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_39 = _superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_40 = _superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch_3 = superpage_entries_3_valid_0 & _superpage_hits_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3740 = superpage_entries_3_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T_42; // @[TLB.scala:183:52]
assign _superpage_hits_T_42 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_47; // @[TLB.scala:183:52]
assign _superpage_hits_T_47 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_52; // @[TLB.scala:183:52]
assign _superpage_hits_T_52 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_93; // @[TLB.scala:183:52]
assign _hitsVec_T_93 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_98; // @[TLB.scala:183:52]
assign _hitsVec_T_98 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_103; // @[TLB.scala:183:52]
assign _hitsVec_T_103 = _T_3740; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_43 = _superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_44 = _superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_45 = _superpage_hits_T_44; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_46 = superpage_hits_tagMatch_3 & _superpage_hits_T_45; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_15 = superpage_entries_3_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_10; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_10; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28]
wire _ppn_ignore_T_6; // @[TLB.scala:197:28]
assign _ppn_ignore_T_6 = _GEN_15; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_10; // @[TLB.scala:182:28]
assign _ignore_T_10 = _GEN_15; // @[TLB.scala:182:28]
wire superpage_hits_ignore_10 = _superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_48 = _superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_49 = _superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_50 = superpage_hits_ignore_10 | _superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_51 = _superpage_hits_T_46 & _superpage_hits_T_50; // @[TLB.scala:183:{29,40}]
wire superpage_hits_3 = _superpage_hits_T_51; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_53 = _superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_54 = _superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [1:0] hitsVec_idx = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_1 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_2 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_3 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_4 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_5 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_6 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_7 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_24 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_48 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_72 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_96 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_120 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_144 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_168 = vpn[1:0]; // @[package.scala:163:13]
wire [24:0] _hitsVec_T_1 = _hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_2 = _hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_3 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_16 = {{sectored_entries_0_0_valid_3}, {sectored_entries_0_0_valid_2}, {sectored_entries_0_0_valid_1}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_5 = _GEN_16[hitsVec_idx] & _hitsVec_T_4; // @[package.scala:163:13]
wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_7 = _hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_8 = _hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_9 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_17 = {{sectored_entries_0_1_valid_3}, {sectored_entries_0_1_valid_2}, {sectored_entries_0_1_valid_1}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_11 = _GEN_17[hitsVec_idx_1] & _hitsVec_T_10; // @[package.scala:163:13]
wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_13 = _hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_14 = _hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_15 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_18 = {{sectored_entries_0_2_valid_3}, {sectored_entries_0_2_valid_2}, {sectored_entries_0_2_valid_1}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_17 = _GEN_18[hitsVec_idx_2] & _hitsVec_T_16; // @[package.scala:163:13]
wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_19 = _hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_20 = _hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_21 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_19 = {{sectored_entries_0_3_valid_3}, {sectored_entries_0_3_valid_2}, {sectored_entries_0_3_valid_1}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_23 = _GEN_19[hitsVec_idx_3] & _hitsVec_T_22; // @[package.scala:163:13]
wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_25 = _hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_26 = _hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_27 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_28 = _hitsVec_T_26 & _hitsVec_T_27; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_20 = {{sectored_entries_0_4_valid_3}, {sectored_entries_0_4_valid_2}, {sectored_entries_0_4_valid_1}, {sectored_entries_0_4_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_29 = _GEN_20[hitsVec_idx_4] & _hitsVec_T_28; // @[package.scala:163:13]
wire hitsVec_4 = vm_enabled & _hitsVec_T_29; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_31 = _hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_32 = _hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_33 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_34 = _hitsVec_T_32 & _hitsVec_T_33; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_21 = {{sectored_entries_0_5_valid_3}, {sectored_entries_0_5_valid_2}, {sectored_entries_0_5_valid_1}, {sectored_entries_0_5_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_35 = _GEN_21[hitsVec_idx_5] & _hitsVec_T_34; // @[package.scala:163:13]
wire hitsVec_5 = vm_enabled & _hitsVec_T_35; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_37 = _hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_38 = _hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_39 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_40 = _hitsVec_T_38 & _hitsVec_T_39; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_22 = {{sectored_entries_0_6_valid_3}, {sectored_entries_0_6_valid_2}, {sectored_entries_0_6_valid_1}, {sectored_entries_0_6_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_41 = _GEN_22[hitsVec_idx_6] & _hitsVec_T_40; // @[package.scala:163:13]
wire hitsVec_6 = vm_enabled & _hitsVec_T_41; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_43 = _hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_44 = _hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_45 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_46 = _hitsVec_T_44 & _hitsVec_T_45; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_23 = {{sectored_entries_0_7_valid_3}, {sectored_entries_0_7_valid_2}, {sectored_entries_0_7_valid_1}, {sectored_entries_0_7_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_47 = _GEN_23[hitsVec_idx_7] & _hitsVec_T_46; // @[package.scala:163:13]
wire hitsVec_7 = vm_enabled & _hitsVec_T_47; // @[TLB.scala:188:18, :399:61, :440:44]
wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_49 = _hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_50 = _hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_51 = _hitsVec_T_50; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_52 = hitsVec_tagMatch & _hitsVec_T_51; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_54 = _hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_55 = _hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_56 = hitsVec_ignore_1 | _hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_57 = _hitsVec_T_52 & _hitsVec_T_56; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_62 = _hitsVec_T_57; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_59 = _hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_60 = _hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_8 = vm_enabled & _hitsVec_T_62; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch_1 = superpage_entries_1_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_64 = _hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_65 = _hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_66 = _hitsVec_T_65; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_67 = hitsVec_tagMatch_1 & _hitsVec_T_66; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_69 = _hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_70 = _hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_71 = hitsVec_ignore_4 | _hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_72 = _hitsVec_T_67 & _hitsVec_T_71; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_77 = _hitsVec_T_72; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_74 = _hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_75 = _hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_9 = vm_enabled & _hitsVec_T_77; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch_2 = superpage_entries_2_valid_0 & _hitsVec_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_79 = _hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_80 = _hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_81 = _hitsVec_T_80; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_82 = hitsVec_tagMatch_2 & _hitsVec_T_81; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_7 = _hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_84 = _hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_85 = _hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_86 = hitsVec_ignore_7 | _hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_87 = _hitsVec_T_82 & _hitsVec_T_86; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_92 = _hitsVec_T_87; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_89 = _hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_90 = _hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_10 = vm_enabled & _hitsVec_T_92; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch_3 = superpage_entries_3_valid_0 & _hitsVec_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_94 = _hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_95 = _hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_96 = _hitsVec_T_95; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_97 = hitsVec_tagMatch_3 & _hitsVec_T_96; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_10 = _hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_99 = _hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_100 = _hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_101 = hitsVec_ignore_10 | _hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_102 = _hitsVec_T_97 & _hitsVec_T_101; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_107 = _hitsVec_T_102; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_104 = _hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_105 = _hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_11 = vm_enabled & _hitsVec_T_107; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_4 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56]
wire hitsVec_tagMatch_4 = special_entry_valid_0 & _hitsVec_tagMatch_T_4; // @[TLB.scala:178:{33,43}, :346:56]
wire [26:0] _T_3838 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56]
wire [26:0] _hitsVec_T_108; // @[TLB.scala:183:52]
assign _hitsVec_T_108 = _T_3838; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_113; // @[TLB.scala:183:52]
assign _hitsVec_T_113 = _T_3838; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_118; // @[TLB.scala:183:52]
assign _hitsVec_T_118 = _T_3838; // @[TLB.scala:183:52]
wire [8:0] _hitsVec_T_109 = _hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_110 = _hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_111 = _hitsVec_T_110; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_112 = hitsVec_tagMatch_4 & _hitsVec_T_111; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_13 = _hitsVec_ignore_T_13; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_114 = _hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_115 = _hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_116 = hitsVec_ignore_13 | _hitsVec_T_115; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_117 = _hitsVec_T_112 & _hitsVec_T_116; // @[TLB.scala:183:{29,40}]
wire _hitsVec_ignore_T_14 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56]
wire hitsVec_ignore_14 = _hitsVec_ignore_T_14; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_119 = _hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_120 = _hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_121 = hitsVec_ignore_14 | _hitsVec_T_120; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_122 = _hitsVec_T_117 & _hitsVec_T_121; // @[TLB.scala:183:{29,40}]
wire hitsVec_12 = vm_enabled & _hitsVec_T_122; // @[TLB.scala:183:29, :399:61, :440:44]
wire [1:0] real_hits_lo_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27]
wire [2:0] real_hits_lo_lo = {real_hits_lo_lo_hi, hitsVec_0}; // @[package.scala:45:27]
wire [1:0] real_hits_lo_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27]
wire [2:0] real_hits_lo_hi = {real_hits_lo_hi_hi, hitsVec_3}; // @[package.scala:45:27]
wire [5:0] real_hits_lo = {real_hits_lo_hi, real_hits_lo_lo}; // @[package.scala:45:27]
wire [1:0] real_hits_hi_lo_hi = {hitsVec_8, hitsVec_7}; // @[package.scala:45:27]
wire [2:0] real_hits_hi_lo = {real_hits_hi_lo_hi, hitsVec_6}; // @[package.scala:45:27]
wire [1:0] real_hits_hi_hi_lo = {hitsVec_10, hitsVec_9}; // @[package.scala:45:27]
wire [1:0] real_hits_hi_hi_hi = {hitsVec_12, hitsVec_11}; // @[package.scala:45:27]
wire [3:0] real_hits_hi_hi = {real_hits_hi_hi_hi, real_hits_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] real_hits_hi = {real_hits_hi_hi, real_hits_hi_lo}; // @[package.scala:45:27]
wire [12:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27]
wire [12:0] _tlb_hit_T = real_hits; // @[package.scala:45:27]
wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18]
wire [13:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27]
wire _newEntry_g_T; // @[TLB.scala:453:25]
wire _newEntry_sw_T_6; // @[PTW.scala:151:40]
wire _newEntry_sx_T_5; // @[PTW.scala:153:35]
wire _newEntry_sr_T_5; // @[PTW.scala:149:35]
wire newEntry_g; // @[TLB.scala:449:24]
wire newEntry_sw; // @[TLB.scala:449:24]
wire newEntry_sx; // @[TLB.scala:449:24]
wire newEntry_sr; // @[TLB.scala:449:24]
wire newEntry_ppp; // @[TLB.scala:449:24]
wire newEntry_pal; // @[TLB.scala:449:24]
wire newEntry_paa; // @[TLB.scala:449:24]
wire newEntry_eff; // @[TLB.scala:449:24]
assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25]
assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25]
wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53]
wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7]
wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sr_T_1; // @[TLB.scala:318:7]
wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7]
wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7]
assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24]
wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7]
wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sw_T_1; // @[TLB.scala:318:7]
wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7]
wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7]
assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24]
wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7]
wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sx_T_1; // @[TLB.scala:318:7]
wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7]
wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7]
assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24]
wire [1:0] _GEN_24 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] _GEN_25 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_26 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [1:0] _GEN_27 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_28 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [1:0] _GEN_29 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_30 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [20:0] _GEN_31 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24]
wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_0_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_1_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_2_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_3_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_4_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_5_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_6_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_7_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24]
wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_1_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_2_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_3_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_lo_lo_hi = {superpage_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_lo_hi_lo = {superpage_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_1_data_0_lo_hi_hi = {superpage_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_hi_lo_lo = {superpage_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_1_data_0_hi_lo_hi = {superpage_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_1_data_0_hi_lo = {superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_hi_hi_lo = {superpage_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_1_data_0_hi_hi_hi = {superpage_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_lo_lo_hi = {superpage_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_lo_hi_lo = {superpage_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_2_data_0_lo_hi_hi = {superpage_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_hi_lo_lo = {superpage_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_2_data_0_hi_lo_hi = {superpage_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_2_data_0_hi_lo = {superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_hi_hi_lo = {superpage_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_2_data_0_hi_hi_hi = {superpage_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_lo_lo_hi = {superpage_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_lo_hi_lo = {superpage_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_3_data_0_lo_hi_hi = {superpage_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_hi_lo_lo = {superpage_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_3_data_0_hi_lo_hi = {superpage_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_3_data_0_hi_lo = {superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_hi_hi_lo = {superpage_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_3_data_0_hi_hi_hi = {superpage_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22]
wire [1:0] idx = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_1 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_2 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_3 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_4 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_5 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_6 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_7 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [2:0] sectored_entries_0_0_data_lo_lo_hi = {sectored_entries_0_0_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_0_data_lo_lo = {sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_lo_hi_lo = {sectored_entries_0_0_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_0_data_lo_hi_hi = {sectored_entries_0_0_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_0_data_lo_hi = {sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_0_data_lo = {sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_hi_lo_lo = {sectored_entries_0_0_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_0_data_hi_lo_hi = {sectored_entries_0_0_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_0_data_hi_lo = {sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_hi_hi_lo = {sectored_entries_0_0_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_0_data_hi_hi_hi = {sectored_entries_0_0_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_0_data_hi_hi = {sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_0_data_hi = {sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_0_data_T = {sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_lo_lo_hi = {sectored_entries_0_1_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_1_data_lo_lo = {sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_lo_hi_lo = {sectored_entries_0_1_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_1_data_lo_hi_hi = {sectored_entries_0_1_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_1_data_lo_hi = {sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_1_data_lo = {sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_hi_lo_lo = {sectored_entries_0_1_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_1_data_hi_lo_hi = {sectored_entries_0_1_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_1_data_hi_lo = {sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_hi_hi_lo = {sectored_entries_0_1_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_1_data_hi_hi_hi = {sectored_entries_0_1_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_1_data_hi_hi = {sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_1_data_hi = {sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_1_data_T = {sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_lo_lo_hi = {sectored_entries_0_2_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_2_data_lo_lo = {sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_lo_hi_lo = {sectored_entries_0_2_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_2_data_lo_hi_hi = {sectored_entries_0_2_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_2_data_lo_hi = {sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_2_data_lo = {sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_hi_lo_lo = {sectored_entries_0_2_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_2_data_hi_lo_hi = {sectored_entries_0_2_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_2_data_hi_lo = {sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_hi_hi_lo = {sectored_entries_0_2_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_2_data_hi_hi_hi = {sectored_entries_0_2_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_2_data_hi_hi = {sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_2_data_hi = {sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_2_data_T = {sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_lo_lo_hi = {sectored_entries_0_3_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_3_data_lo_lo = {sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_lo_hi_lo = {sectored_entries_0_3_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_3_data_lo_hi_hi = {sectored_entries_0_3_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_3_data_lo_hi = {sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_3_data_lo = {sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_hi_lo_lo = {sectored_entries_0_3_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_3_data_hi_lo_hi = {sectored_entries_0_3_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_3_data_hi_lo = {sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_hi_hi_lo = {sectored_entries_0_3_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_3_data_hi_hi_hi = {sectored_entries_0_3_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_3_data_hi_hi = {sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_3_data_hi = {sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_3_data_T = {sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_lo_lo_hi = {sectored_entries_0_4_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_4_data_lo_lo = {sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_lo_hi_lo = {sectored_entries_0_4_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_4_data_lo_hi_hi = {sectored_entries_0_4_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_4_data_lo_hi = {sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_4_data_lo = {sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_hi_lo_lo = {sectored_entries_0_4_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_4_data_hi_lo_hi = {sectored_entries_0_4_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_4_data_hi_lo = {sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_hi_hi_lo = {sectored_entries_0_4_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_4_data_hi_hi_hi = {sectored_entries_0_4_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_4_data_hi_hi = {sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_4_data_hi = {sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_4_data_T = {sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_lo_lo_hi = {sectored_entries_0_5_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_5_data_lo_lo = {sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_lo_hi_lo = {sectored_entries_0_5_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_5_data_lo_hi_hi = {sectored_entries_0_5_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_5_data_lo_hi = {sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_5_data_lo = {sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_hi_lo_lo = {sectored_entries_0_5_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_5_data_hi_lo_hi = {sectored_entries_0_5_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_5_data_hi_lo = {sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_hi_hi_lo = {sectored_entries_0_5_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_5_data_hi_hi_hi = {sectored_entries_0_5_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_5_data_hi_hi = {sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_5_data_hi = {sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_5_data_T = {sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_lo_lo_hi = {sectored_entries_0_6_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_6_data_lo_lo = {sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_lo_hi_lo = {sectored_entries_0_6_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_6_data_lo_hi_hi = {sectored_entries_0_6_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_6_data_lo_hi = {sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_6_data_lo = {sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_hi_lo_lo = {sectored_entries_0_6_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_6_data_hi_lo_hi = {sectored_entries_0_6_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_6_data_hi_lo = {sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_hi_hi_lo = {sectored_entries_0_6_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_6_data_hi_hi_hi = {sectored_entries_0_6_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_6_data_hi_hi = {sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_6_data_hi = {sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_6_data_T = {sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_lo_lo_hi = {sectored_entries_0_7_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_7_data_lo_lo = {sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_lo_hi_lo = {sectored_entries_0_7_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_7_data_lo_hi_hi = {sectored_entries_0_7_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_7_data_lo_hi = {sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_7_data_lo = {sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_hi_lo_lo = {sectored_entries_0_7_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_7_data_hi_lo_hi = {sectored_entries_0_7_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_7_data_hi_lo = {sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_hi_hi_lo = {sectored_entries_0_7_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_7_data_hi_hi_hi = {sectored_entries_0_7_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_7_data_hi_hi = {sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_7_data_hi = {sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_7_data_T = {sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24]
wire [19:0] _entries_T_23; // @[TLB.scala:170:77]
wire _entries_T_22; // @[TLB.scala:170:77]
wire _entries_T_21; // @[TLB.scala:170:77]
wire _entries_T_20; // @[TLB.scala:170:77]
wire _entries_T_19; // @[TLB.scala:170:77]
wire _entries_T_18; // @[TLB.scala:170:77]
wire _entries_T_17; // @[TLB.scala:170:77]
wire _entries_T_16; // @[TLB.scala:170:77]
wire _entries_T_15; // @[TLB.scala:170:77]
wire _entries_T_14; // @[TLB.scala:170:77]
wire _entries_T_13; // @[TLB.scala:170:77]
wire _entries_T_12; // @[TLB.scala:170:77]
wire _entries_T_11; // @[TLB.scala:170:77]
wire _entries_T_10; // @[TLB.scala:170:77]
wire _entries_T_9; // @[TLB.scala:170:77]
wire _entries_T_8; // @[TLB.scala:170:77]
wire _entries_T_7; // @[TLB.scala:170:77]
wire _entries_T_6; // @[TLB.scala:170:77]
wire _entries_T_5; // @[TLB.scala:170:77]
wire _entries_T_4; // @[TLB.scala:170:77]
wire _entries_T_3; // @[TLB.scala:170:77]
wire _entries_T_2; // @[TLB.scala:170:77]
wire _entries_T_1; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_32 = {{sectored_entries_0_0_data_3}, {sectored_entries_0_0_data_2}, {sectored_entries_0_0_data_1}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_1 = _GEN_32[_entries_T]; // @[package.scala:163:13]
assign _entries_T_1 = _entries_WIRE_1[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[TLB.scala:170:77]
assign _entries_T_2 = _entries_WIRE_1[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_c = _entries_T_2; // @[TLB.scala:170:77]
assign _entries_T_3 = _entries_WIRE_1[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_eff = _entries_T_3; // @[TLB.scala:170:77]
assign _entries_T_4 = _entries_WIRE_1[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_paa = _entries_T_4; // @[TLB.scala:170:77]
assign _entries_T_5 = _entries_WIRE_1[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_pal = _entries_T_5; // @[TLB.scala:170:77]
assign _entries_T_6 = _entries_WIRE_1[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_ppp = _entries_T_6; // @[TLB.scala:170:77]
assign _entries_T_7 = _entries_WIRE_1[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_pr = _entries_T_7; // @[TLB.scala:170:77]
assign _entries_T_8 = _entries_WIRE_1[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_px = _entries_T_8; // @[TLB.scala:170:77]
assign _entries_T_9 = _entries_WIRE_1[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_pw = _entries_T_9; // @[TLB.scala:170:77]
assign _entries_T_10 = _entries_WIRE_1[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_hr = _entries_T_10; // @[TLB.scala:170:77]
assign _entries_T_11 = _entries_WIRE_1[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_hx = _entries_T_11; // @[TLB.scala:170:77]
assign _entries_T_12 = _entries_WIRE_1[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_hw = _entries_T_12; // @[TLB.scala:170:77]
assign _entries_T_13 = _entries_WIRE_1[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_sr = _entries_T_13; // @[TLB.scala:170:77]
assign _entries_T_14 = _entries_WIRE_1[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_sx = _entries_T_14; // @[TLB.scala:170:77]
assign _entries_T_15 = _entries_WIRE_1[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_sw = _entries_T_15; // @[TLB.scala:170:77]
assign _entries_T_16 = _entries_WIRE_1[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_gf = _entries_T_16; // @[TLB.scala:170:77]
assign _entries_T_17 = _entries_WIRE_1[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_pf = _entries_T_17; // @[TLB.scala:170:77]
assign _entries_T_18 = _entries_WIRE_1[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_stage2 = _entries_T_18; // @[TLB.scala:170:77]
assign _entries_T_19 = _entries_WIRE_1[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_final = _entries_T_19; // @[TLB.scala:170:77]
assign _entries_T_20 = _entries_WIRE_1[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_ptw = _entries_T_20; // @[TLB.scala:170:77]
assign _entries_T_21 = _entries_WIRE_1[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_g = _entries_T_21; // @[TLB.scala:170:77]
assign _entries_T_22 = _entries_WIRE_1[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_u = _entries_T_22; // @[TLB.scala:170:77]
assign _entries_T_23 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_ppn = _entries_T_23; // @[TLB.scala:170:77]
wire [19:0] _entries_T_47; // @[TLB.scala:170:77]
wire _entries_T_46; // @[TLB.scala:170:77]
wire _entries_T_45; // @[TLB.scala:170:77]
wire _entries_T_44; // @[TLB.scala:170:77]
wire _entries_T_43; // @[TLB.scala:170:77]
wire _entries_T_42; // @[TLB.scala:170:77]
wire _entries_T_41; // @[TLB.scala:170:77]
wire _entries_T_40; // @[TLB.scala:170:77]
wire _entries_T_39; // @[TLB.scala:170:77]
wire _entries_T_38; // @[TLB.scala:170:77]
wire _entries_T_37; // @[TLB.scala:170:77]
wire _entries_T_36; // @[TLB.scala:170:77]
wire _entries_T_35; // @[TLB.scala:170:77]
wire _entries_T_34; // @[TLB.scala:170:77]
wire _entries_T_33; // @[TLB.scala:170:77]
wire _entries_T_32; // @[TLB.scala:170:77]
wire _entries_T_31; // @[TLB.scala:170:77]
wire _entries_T_30; // @[TLB.scala:170:77]
wire _entries_T_29; // @[TLB.scala:170:77]
wire _entries_T_28; // @[TLB.scala:170:77]
wire _entries_T_27; // @[TLB.scala:170:77]
wire _entries_T_26; // @[TLB.scala:170:77]
wire _entries_T_25; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_33 = {{sectored_entries_0_1_data_3}, {sectored_entries_0_1_data_2}, {sectored_entries_0_1_data_1}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_3 = _GEN_33[_entries_T_24]; // @[package.scala:163:13]
assign _entries_T_25 = _entries_WIRE_3[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_fragmented_superpage = _entries_T_25; // @[TLB.scala:170:77]
assign _entries_T_26 = _entries_WIRE_3[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_c = _entries_T_26; // @[TLB.scala:170:77]
assign _entries_T_27 = _entries_WIRE_3[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_eff = _entries_T_27; // @[TLB.scala:170:77]
assign _entries_T_28 = _entries_WIRE_3[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_paa = _entries_T_28; // @[TLB.scala:170:77]
assign _entries_T_29 = _entries_WIRE_3[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pal = _entries_T_29; // @[TLB.scala:170:77]
assign _entries_T_30 = _entries_WIRE_3[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ppp = _entries_T_30; // @[TLB.scala:170:77]
assign _entries_T_31 = _entries_WIRE_3[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pr = _entries_T_31; // @[TLB.scala:170:77]
assign _entries_T_32 = _entries_WIRE_3[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_px = _entries_T_32; // @[TLB.scala:170:77]
assign _entries_T_33 = _entries_WIRE_3[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pw = _entries_T_33; // @[TLB.scala:170:77]
assign _entries_T_34 = _entries_WIRE_3[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hr = _entries_T_34; // @[TLB.scala:170:77]
assign _entries_T_35 = _entries_WIRE_3[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hx = _entries_T_35; // @[TLB.scala:170:77]
assign _entries_T_36 = _entries_WIRE_3[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hw = _entries_T_36; // @[TLB.scala:170:77]
assign _entries_T_37 = _entries_WIRE_3[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sr = _entries_T_37; // @[TLB.scala:170:77]
assign _entries_T_38 = _entries_WIRE_3[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sx = _entries_T_38; // @[TLB.scala:170:77]
assign _entries_T_39 = _entries_WIRE_3[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sw = _entries_T_39; // @[TLB.scala:170:77]
assign _entries_T_40 = _entries_WIRE_3[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_gf = _entries_T_40; // @[TLB.scala:170:77]
assign _entries_T_41 = _entries_WIRE_3[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pf = _entries_T_41; // @[TLB.scala:170:77]
assign _entries_T_42 = _entries_WIRE_3[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_stage2 = _entries_T_42; // @[TLB.scala:170:77]
assign _entries_T_43 = _entries_WIRE_3[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_final = _entries_T_43; // @[TLB.scala:170:77]
assign _entries_T_44 = _entries_WIRE_3[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_ptw = _entries_T_44; // @[TLB.scala:170:77]
assign _entries_T_45 = _entries_WIRE_3[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_g = _entries_T_45; // @[TLB.scala:170:77]
assign _entries_T_46 = _entries_WIRE_3[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_u = _entries_T_46; // @[TLB.scala:170:77]
assign _entries_T_47 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_2_ppn = _entries_T_47; // @[TLB.scala:170:77]
wire [19:0] _entries_T_71; // @[TLB.scala:170:77]
wire _entries_T_70; // @[TLB.scala:170:77]
wire _entries_T_69; // @[TLB.scala:170:77]
wire _entries_T_68; // @[TLB.scala:170:77]
wire _entries_T_67; // @[TLB.scala:170:77]
wire _entries_T_66; // @[TLB.scala:170:77]
wire _entries_T_65; // @[TLB.scala:170:77]
wire _entries_T_64; // @[TLB.scala:170:77]
wire _entries_T_63; // @[TLB.scala:170:77]
wire _entries_T_62; // @[TLB.scala:170:77]
wire _entries_T_61; // @[TLB.scala:170:77]
wire _entries_T_60; // @[TLB.scala:170:77]
wire _entries_T_59; // @[TLB.scala:170:77]
wire _entries_T_58; // @[TLB.scala:170:77]
wire _entries_T_57; // @[TLB.scala:170:77]
wire _entries_T_56; // @[TLB.scala:170:77]
wire _entries_T_55; // @[TLB.scala:170:77]
wire _entries_T_54; // @[TLB.scala:170:77]
wire _entries_T_53; // @[TLB.scala:170:77]
wire _entries_T_52; // @[TLB.scala:170:77]
wire _entries_T_51; // @[TLB.scala:170:77]
wire _entries_T_50; // @[TLB.scala:170:77]
wire _entries_T_49; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_34 = {{sectored_entries_0_2_data_3}, {sectored_entries_0_2_data_2}, {sectored_entries_0_2_data_1}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_5 = _GEN_34[_entries_T_48]; // @[package.scala:163:13]
assign _entries_T_49 = _entries_WIRE_5[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_fragmented_superpage = _entries_T_49; // @[TLB.scala:170:77]
assign _entries_T_50 = _entries_WIRE_5[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_c = _entries_T_50; // @[TLB.scala:170:77]
assign _entries_T_51 = _entries_WIRE_5[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_eff = _entries_T_51; // @[TLB.scala:170:77]
assign _entries_T_52 = _entries_WIRE_5[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_paa = _entries_T_52; // @[TLB.scala:170:77]
assign _entries_T_53 = _entries_WIRE_5[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pal = _entries_T_53; // @[TLB.scala:170:77]
assign _entries_T_54 = _entries_WIRE_5[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ppp = _entries_T_54; // @[TLB.scala:170:77]
assign _entries_T_55 = _entries_WIRE_5[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pr = _entries_T_55; // @[TLB.scala:170:77]
assign _entries_T_56 = _entries_WIRE_5[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_px = _entries_T_56; // @[TLB.scala:170:77]
assign _entries_T_57 = _entries_WIRE_5[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pw = _entries_T_57; // @[TLB.scala:170:77]
assign _entries_T_58 = _entries_WIRE_5[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hr = _entries_T_58; // @[TLB.scala:170:77]
assign _entries_T_59 = _entries_WIRE_5[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hx = _entries_T_59; // @[TLB.scala:170:77]
assign _entries_T_60 = _entries_WIRE_5[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hw = _entries_T_60; // @[TLB.scala:170:77]
assign _entries_T_61 = _entries_WIRE_5[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sr = _entries_T_61; // @[TLB.scala:170:77]
assign _entries_T_62 = _entries_WIRE_5[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sx = _entries_T_62; // @[TLB.scala:170:77]
assign _entries_T_63 = _entries_WIRE_5[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sw = _entries_T_63; // @[TLB.scala:170:77]
assign _entries_T_64 = _entries_WIRE_5[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_gf = _entries_T_64; // @[TLB.scala:170:77]
assign _entries_T_65 = _entries_WIRE_5[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pf = _entries_T_65; // @[TLB.scala:170:77]
assign _entries_T_66 = _entries_WIRE_5[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_stage2 = _entries_T_66; // @[TLB.scala:170:77]
assign _entries_T_67 = _entries_WIRE_5[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_final = _entries_T_67; // @[TLB.scala:170:77]
assign _entries_T_68 = _entries_WIRE_5[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_ptw = _entries_T_68; // @[TLB.scala:170:77]
assign _entries_T_69 = _entries_WIRE_5[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_g = _entries_T_69; // @[TLB.scala:170:77]
assign _entries_T_70 = _entries_WIRE_5[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_u = _entries_T_70; // @[TLB.scala:170:77]
assign _entries_T_71 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_4_ppn = _entries_T_71; // @[TLB.scala:170:77]
wire [19:0] _entries_T_95; // @[TLB.scala:170:77]
wire _entries_T_94; // @[TLB.scala:170:77]
wire _entries_T_93; // @[TLB.scala:170:77]
wire _entries_T_92; // @[TLB.scala:170:77]
wire _entries_T_91; // @[TLB.scala:170:77]
wire _entries_T_90; // @[TLB.scala:170:77]
wire _entries_T_89; // @[TLB.scala:170:77]
wire _entries_T_88; // @[TLB.scala:170:77]
wire _entries_T_87; // @[TLB.scala:170:77]
wire _entries_T_86; // @[TLB.scala:170:77]
wire _entries_T_85; // @[TLB.scala:170:77]
wire _entries_T_84; // @[TLB.scala:170:77]
wire _entries_T_83; // @[TLB.scala:170:77]
wire _entries_T_82; // @[TLB.scala:170:77]
wire _entries_T_81; // @[TLB.scala:170:77]
wire _entries_T_80; // @[TLB.scala:170:77]
wire _entries_T_79; // @[TLB.scala:170:77]
wire _entries_T_78; // @[TLB.scala:170:77]
wire _entries_T_77; // @[TLB.scala:170:77]
wire _entries_T_76; // @[TLB.scala:170:77]
wire _entries_T_75; // @[TLB.scala:170:77]
wire _entries_T_74; // @[TLB.scala:170:77]
wire _entries_T_73; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_35 = {{sectored_entries_0_3_data_3}, {sectored_entries_0_3_data_2}, {sectored_entries_0_3_data_1}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_7 = _GEN_35[_entries_T_72]; // @[package.scala:163:13]
assign _entries_T_73 = _entries_WIRE_7[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_fragmented_superpage = _entries_T_73; // @[TLB.scala:170:77]
assign _entries_T_74 = _entries_WIRE_7[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_c = _entries_T_74; // @[TLB.scala:170:77]
assign _entries_T_75 = _entries_WIRE_7[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_eff = _entries_T_75; // @[TLB.scala:170:77]
assign _entries_T_76 = _entries_WIRE_7[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_paa = _entries_T_76; // @[TLB.scala:170:77]
assign _entries_T_77 = _entries_WIRE_7[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pal = _entries_T_77; // @[TLB.scala:170:77]
assign _entries_T_78 = _entries_WIRE_7[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ppp = _entries_T_78; // @[TLB.scala:170:77]
assign _entries_T_79 = _entries_WIRE_7[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pr = _entries_T_79; // @[TLB.scala:170:77]
assign _entries_T_80 = _entries_WIRE_7[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_px = _entries_T_80; // @[TLB.scala:170:77]
assign _entries_T_81 = _entries_WIRE_7[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pw = _entries_T_81; // @[TLB.scala:170:77]
assign _entries_T_82 = _entries_WIRE_7[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hr = _entries_T_82; // @[TLB.scala:170:77]
assign _entries_T_83 = _entries_WIRE_7[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hx = _entries_T_83; // @[TLB.scala:170:77]
assign _entries_T_84 = _entries_WIRE_7[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hw = _entries_T_84; // @[TLB.scala:170:77]
assign _entries_T_85 = _entries_WIRE_7[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sr = _entries_T_85; // @[TLB.scala:170:77]
assign _entries_T_86 = _entries_WIRE_7[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sx = _entries_T_86; // @[TLB.scala:170:77]
assign _entries_T_87 = _entries_WIRE_7[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sw = _entries_T_87; // @[TLB.scala:170:77]
assign _entries_T_88 = _entries_WIRE_7[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_gf = _entries_T_88; // @[TLB.scala:170:77]
assign _entries_T_89 = _entries_WIRE_7[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pf = _entries_T_89; // @[TLB.scala:170:77]
assign _entries_T_90 = _entries_WIRE_7[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_stage2 = _entries_T_90; // @[TLB.scala:170:77]
assign _entries_T_91 = _entries_WIRE_7[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_final = _entries_T_91; // @[TLB.scala:170:77]
assign _entries_T_92 = _entries_WIRE_7[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_ptw = _entries_T_92; // @[TLB.scala:170:77]
assign _entries_T_93 = _entries_WIRE_7[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_g = _entries_T_93; // @[TLB.scala:170:77]
assign _entries_T_94 = _entries_WIRE_7[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_u = _entries_T_94; // @[TLB.scala:170:77]
assign _entries_T_95 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_6_ppn = _entries_T_95; // @[TLB.scala:170:77]
wire [19:0] _entries_T_119; // @[TLB.scala:170:77]
wire _entries_T_118; // @[TLB.scala:170:77]
wire _entries_T_117; // @[TLB.scala:170:77]
wire _entries_T_116; // @[TLB.scala:170:77]
wire _entries_T_115; // @[TLB.scala:170:77]
wire _entries_T_114; // @[TLB.scala:170:77]
wire _entries_T_113; // @[TLB.scala:170:77]
wire _entries_T_112; // @[TLB.scala:170:77]
wire _entries_T_111; // @[TLB.scala:170:77]
wire _entries_T_110; // @[TLB.scala:170:77]
wire _entries_T_109; // @[TLB.scala:170:77]
wire _entries_T_108; // @[TLB.scala:170:77]
wire _entries_T_107; // @[TLB.scala:170:77]
wire _entries_T_106; // @[TLB.scala:170:77]
wire _entries_T_105; // @[TLB.scala:170:77]
wire _entries_T_104; // @[TLB.scala:170:77]
wire _entries_T_103; // @[TLB.scala:170:77]
wire _entries_T_102; // @[TLB.scala:170:77]
wire _entries_T_101; // @[TLB.scala:170:77]
wire _entries_T_100; // @[TLB.scala:170:77]
wire _entries_T_99; // @[TLB.scala:170:77]
wire _entries_T_98; // @[TLB.scala:170:77]
wire _entries_T_97; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_36 = {{sectored_entries_0_4_data_3}, {sectored_entries_0_4_data_2}, {sectored_entries_0_4_data_1}, {sectored_entries_0_4_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_9 = _GEN_36[_entries_T_96]; // @[package.scala:163:13]
assign _entries_T_97 = _entries_WIRE_9[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_fragmented_superpage = _entries_T_97; // @[TLB.scala:170:77]
assign _entries_T_98 = _entries_WIRE_9[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_c = _entries_T_98; // @[TLB.scala:170:77]
assign _entries_T_99 = _entries_WIRE_9[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_eff = _entries_T_99; // @[TLB.scala:170:77]
assign _entries_T_100 = _entries_WIRE_9[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_paa = _entries_T_100; // @[TLB.scala:170:77]
assign _entries_T_101 = _entries_WIRE_9[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pal = _entries_T_101; // @[TLB.scala:170:77]
assign _entries_T_102 = _entries_WIRE_9[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ppp = _entries_T_102; // @[TLB.scala:170:77]
assign _entries_T_103 = _entries_WIRE_9[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pr = _entries_T_103; // @[TLB.scala:170:77]
assign _entries_T_104 = _entries_WIRE_9[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_px = _entries_T_104; // @[TLB.scala:170:77]
assign _entries_T_105 = _entries_WIRE_9[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pw = _entries_T_105; // @[TLB.scala:170:77]
assign _entries_T_106 = _entries_WIRE_9[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hr = _entries_T_106; // @[TLB.scala:170:77]
assign _entries_T_107 = _entries_WIRE_9[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hx = _entries_T_107; // @[TLB.scala:170:77]
assign _entries_T_108 = _entries_WIRE_9[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hw = _entries_T_108; // @[TLB.scala:170:77]
assign _entries_T_109 = _entries_WIRE_9[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sr = _entries_T_109; // @[TLB.scala:170:77]
assign _entries_T_110 = _entries_WIRE_9[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sx = _entries_T_110; // @[TLB.scala:170:77]
assign _entries_T_111 = _entries_WIRE_9[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sw = _entries_T_111; // @[TLB.scala:170:77]
assign _entries_T_112 = _entries_WIRE_9[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_gf = _entries_T_112; // @[TLB.scala:170:77]
assign _entries_T_113 = _entries_WIRE_9[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pf = _entries_T_113; // @[TLB.scala:170:77]
assign _entries_T_114 = _entries_WIRE_9[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_stage2 = _entries_T_114; // @[TLB.scala:170:77]
assign _entries_T_115 = _entries_WIRE_9[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_final = _entries_T_115; // @[TLB.scala:170:77]
assign _entries_T_116 = _entries_WIRE_9[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_ptw = _entries_T_116; // @[TLB.scala:170:77]
assign _entries_T_117 = _entries_WIRE_9[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_g = _entries_T_117; // @[TLB.scala:170:77]
assign _entries_T_118 = _entries_WIRE_9[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_u = _entries_T_118; // @[TLB.scala:170:77]
assign _entries_T_119 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_8_ppn = _entries_T_119; // @[TLB.scala:170:77]
wire [19:0] _entries_T_143; // @[TLB.scala:170:77]
wire _entries_T_142; // @[TLB.scala:170:77]
wire _entries_T_141; // @[TLB.scala:170:77]
wire _entries_T_140; // @[TLB.scala:170:77]
wire _entries_T_139; // @[TLB.scala:170:77]
wire _entries_T_138; // @[TLB.scala:170:77]
wire _entries_T_137; // @[TLB.scala:170:77]
wire _entries_T_136; // @[TLB.scala:170:77]
wire _entries_T_135; // @[TLB.scala:170:77]
wire _entries_T_134; // @[TLB.scala:170:77]
wire _entries_T_133; // @[TLB.scala:170:77]
wire _entries_T_132; // @[TLB.scala:170:77]
wire _entries_T_131; // @[TLB.scala:170:77]
wire _entries_T_130; // @[TLB.scala:170:77]
wire _entries_T_129; // @[TLB.scala:170:77]
wire _entries_T_128; // @[TLB.scala:170:77]
wire _entries_T_127; // @[TLB.scala:170:77]
wire _entries_T_126; // @[TLB.scala:170:77]
wire _entries_T_125; // @[TLB.scala:170:77]
wire _entries_T_124; // @[TLB.scala:170:77]
wire _entries_T_123; // @[TLB.scala:170:77]
wire _entries_T_122; // @[TLB.scala:170:77]
wire _entries_T_121; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_37 = {{sectored_entries_0_5_data_3}, {sectored_entries_0_5_data_2}, {sectored_entries_0_5_data_1}, {sectored_entries_0_5_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_11 = _GEN_37[_entries_T_120]; // @[package.scala:163:13]
assign _entries_T_121 = _entries_WIRE_11[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_fragmented_superpage = _entries_T_121; // @[TLB.scala:170:77]
assign _entries_T_122 = _entries_WIRE_11[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_c = _entries_T_122; // @[TLB.scala:170:77]
assign _entries_T_123 = _entries_WIRE_11[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_eff = _entries_T_123; // @[TLB.scala:170:77]
assign _entries_T_124 = _entries_WIRE_11[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_paa = _entries_T_124; // @[TLB.scala:170:77]
assign _entries_T_125 = _entries_WIRE_11[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pal = _entries_T_125; // @[TLB.scala:170:77]
assign _entries_T_126 = _entries_WIRE_11[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ppp = _entries_T_126; // @[TLB.scala:170:77]
assign _entries_T_127 = _entries_WIRE_11[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pr = _entries_T_127; // @[TLB.scala:170:77]
assign _entries_T_128 = _entries_WIRE_11[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_px = _entries_T_128; // @[TLB.scala:170:77]
assign _entries_T_129 = _entries_WIRE_11[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pw = _entries_T_129; // @[TLB.scala:170:77]
assign _entries_T_130 = _entries_WIRE_11[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hr = _entries_T_130; // @[TLB.scala:170:77]
assign _entries_T_131 = _entries_WIRE_11[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hx = _entries_T_131; // @[TLB.scala:170:77]
assign _entries_T_132 = _entries_WIRE_11[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hw = _entries_T_132; // @[TLB.scala:170:77]
assign _entries_T_133 = _entries_WIRE_11[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sr = _entries_T_133; // @[TLB.scala:170:77]
assign _entries_T_134 = _entries_WIRE_11[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sx = _entries_T_134; // @[TLB.scala:170:77]
assign _entries_T_135 = _entries_WIRE_11[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sw = _entries_T_135; // @[TLB.scala:170:77]
assign _entries_T_136 = _entries_WIRE_11[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_gf = _entries_T_136; // @[TLB.scala:170:77]
assign _entries_T_137 = _entries_WIRE_11[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pf = _entries_T_137; // @[TLB.scala:170:77]
assign _entries_T_138 = _entries_WIRE_11[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_stage2 = _entries_T_138; // @[TLB.scala:170:77]
assign _entries_T_139 = _entries_WIRE_11[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_final = _entries_T_139; // @[TLB.scala:170:77]
assign _entries_T_140 = _entries_WIRE_11[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_ptw = _entries_T_140; // @[TLB.scala:170:77]
assign _entries_T_141 = _entries_WIRE_11[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_g = _entries_T_141; // @[TLB.scala:170:77]
assign _entries_T_142 = _entries_WIRE_11[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_u = _entries_T_142; // @[TLB.scala:170:77]
assign _entries_T_143 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_10_ppn = _entries_T_143; // @[TLB.scala:170:77]
wire [19:0] _entries_T_167; // @[TLB.scala:170:77]
wire _entries_T_166; // @[TLB.scala:170:77]
wire _entries_T_165; // @[TLB.scala:170:77]
wire _entries_T_164; // @[TLB.scala:170:77]
wire _entries_T_163; // @[TLB.scala:170:77]
wire _entries_T_162; // @[TLB.scala:170:77]
wire _entries_T_161; // @[TLB.scala:170:77]
wire _entries_T_160; // @[TLB.scala:170:77]
wire _entries_T_159; // @[TLB.scala:170:77]
wire _entries_T_158; // @[TLB.scala:170:77]
wire _entries_T_157; // @[TLB.scala:170:77]
wire _entries_T_156; // @[TLB.scala:170:77]
wire _entries_T_155; // @[TLB.scala:170:77]
wire _entries_T_154; // @[TLB.scala:170:77]
wire _entries_T_153; // @[TLB.scala:170:77]
wire _entries_T_152; // @[TLB.scala:170:77]
wire _entries_T_151; // @[TLB.scala:170:77]
wire _entries_T_150; // @[TLB.scala:170:77]
wire _entries_T_149; // @[TLB.scala:170:77]
wire _entries_T_148; // @[TLB.scala:170:77]
wire _entries_T_147; // @[TLB.scala:170:77]
wire _entries_T_146; // @[TLB.scala:170:77]
wire _entries_T_145; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_38 = {{sectored_entries_0_6_data_3}, {sectored_entries_0_6_data_2}, {sectored_entries_0_6_data_1}, {sectored_entries_0_6_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_13 = _GEN_38[_entries_T_144]; // @[package.scala:163:13]
assign _entries_T_145 = _entries_WIRE_13[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_fragmented_superpage = _entries_T_145; // @[TLB.scala:170:77]
assign _entries_T_146 = _entries_WIRE_13[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_c = _entries_T_146; // @[TLB.scala:170:77]
assign _entries_T_147 = _entries_WIRE_13[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_eff = _entries_T_147; // @[TLB.scala:170:77]
assign _entries_T_148 = _entries_WIRE_13[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_paa = _entries_T_148; // @[TLB.scala:170:77]
assign _entries_T_149 = _entries_WIRE_13[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pal = _entries_T_149; // @[TLB.scala:170:77]
assign _entries_T_150 = _entries_WIRE_13[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ppp = _entries_T_150; // @[TLB.scala:170:77]
assign _entries_T_151 = _entries_WIRE_13[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pr = _entries_T_151; // @[TLB.scala:170:77]
assign _entries_T_152 = _entries_WIRE_13[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_px = _entries_T_152; // @[TLB.scala:170:77]
assign _entries_T_153 = _entries_WIRE_13[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pw = _entries_T_153; // @[TLB.scala:170:77]
assign _entries_T_154 = _entries_WIRE_13[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hr = _entries_T_154; // @[TLB.scala:170:77]
assign _entries_T_155 = _entries_WIRE_13[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hx = _entries_T_155; // @[TLB.scala:170:77]
assign _entries_T_156 = _entries_WIRE_13[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hw = _entries_T_156; // @[TLB.scala:170:77]
assign _entries_T_157 = _entries_WIRE_13[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sr = _entries_T_157; // @[TLB.scala:170:77]
assign _entries_T_158 = _entries_WIRE_13[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sx = _entries_T_158; // @[TLB.scala:170:77]
assign _entries_T_159 = _entries_WIRE_13[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sw = _entries_T_159; // @[TLB.scala:170:77]
assign _entries_T_160 = _entries_WIRE_13[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_gf = _entries_T_160; // @[TLB.scala:170:77]
assign _entries_T_161 = _entries_WIRE_13[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pf = _entries_T_161; // @[TLB.scala:170:77]
assign _entries_T_162 = _entries_WIRE_13[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_stage2 = _entries_T_162; // @[TLB.scala:170:77]
assign _entries_T_163 = _entries_WIRE_13[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_final = _entries_T_163; // @[TLB.scala:170:77]
assign _entries_T_164 = _entries_WIRE_13[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_ptw = _entries_T_164; // @[TLB.scala:170:77]
assign _entries_T_165 = _entries_WIRE_13[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_g = _entries_T_165; // @[TLB.scala:170:77]
assign _entries_T_166 = _entries_WIRE_13[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_u = _entries_T_166; // @[TLB.scala:170:77]
assign _entries_T_167 = _entries_WIRE_13[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_12_ppn = _entries_T_167; // @[TLB.scala:170:77]
wire [19:0] _entries_T_191; // @[TLB.scala:170:77]
wire _entries_T_190; // @[TLB.scala:170:77]
wire _entries_T_189; // @[TLB.scala:170:77]
wire _entries_T_188; // @[TLB.scala:170:77]
wire _entries_T_187; // @[TLB.scala:170:77]
wire _entries_T_186; // @[TLB.scala:170:77]
wire _entries_T_185; // @[TLB.scala:170:77]
wire _entries_T_184; // @[TLB.scala:170:77]
wire _entries_T_183; // @[TLB.scala:170:77]
wire _entries_T_182; // @[TLB.scala:170:77]
wire _entries_T_181; // @[TLB.scala:170:77]
wire _entries_T_180; // @[TLB.scala:170:77]
wire _entries_T_179; // @[TLB.scala:170:77]
wire _entries_T_178; // @[TLB.scala:170:77]
wire _entries_T_177; // @[TLB.scala:170:77]
wire _entries_T_176; // @[TLB.scala:170:77]
wire _entries_T_175; // @[TLB.scala:170:77]
wire _entries_T_174; // @[TLB.scala:170:77]
wire _entries_T_173; // @[TLB.scala:170:77]
wire _entries_T_172; // @[TLB.scala:170:77]
wire _entries_T_171; // @[TLB.scala:170:77]
wire _entries_T_170; // @[TLB.scala:170:77]
wire _entries_T_169; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_39 = {{sectored_entries_0_7_data_3}, {sectored_entries_0_7_data_2}, {sectored_entries_0_7_data_1}, {sectored_entries_0_7_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_15 = _GEN_39[_entries_T_168]; // @[package.scala:163:13]
assign _entries_T_169 = _entries_WIRE_15[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_fragmented_superpage = _entries_T_169; // @[TLB.scala:170:77]
assign _entries_T_170 = _entries_WIRE_15[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_c = _entries_T_170; // @[TLB.scala:170:77]
assign _entries_T_171 = _entries_WIRE_15[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_eff = _entries_T_171; // @[TLB.scala:170:77]
assign _entries_T_172 = _entries_WIRE_15[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_paa = _entries_T_172; // @[TLB.scala:170:77]
assign _entries_T_173 = _entries_WIRE_15[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pal = _entries_T_173; // @[TLB.scala:170:77]
assign _entries_T_174 = _entries_WIRE_15[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ppp = _entries_T_174; // @[TLB.scala:170:77]
assign _entries_T_175 = _entries_WIRE_15[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pr = _entries_T_175; // @[TLB.scala:170:77]
assign _entries_T_176 = _entries_WIRE_15[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_px = _entries_T_176; // @[TLB.scala:170:77]
assign _entries_T_177 = _entries_WIRE_15[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pw = _entries_T_177; // @[TLB.scala:170:77]
assign _entries_T_178 = _entries_WIRE_15[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hr = _entries_T_178; // @[TLB.scala:170:77]
assign _entries_T_179 = _entries_WIRE_15[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hx = _entries_T_179; // @[TLB.scala:170:77]
assign _entries_T_180 = _entries_WIRE_15[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hw = _entries_T_180; // @[TLB.scala:170:77]
assign _entries_T_181 = _entries_WIRE_15[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sr = _entries_T_181; // @[TLB.scala:170:77]
assign _entries_T_182 = _entries_WIRE_15[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sx = _entries_T_182; // @[TLB.scala:170:77]
assign _entries_T_183 = _entries_WIRE_15[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sw = _entries_T_183; // @[TLB.scala:170:77]
assign _entries_T_184 = _entries_WIRE_15[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_gf = _entries_T_184; // @[TLB.scala:170:77]
assign _entries_T_185 = _entries_WIRE_15[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pf = _entries_T_185; // @[TLB.scala:170:77]
assign _entries_T_186 = _entries_WIRE_15[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_stage2 = _entries_T_186; // @[TLB.scala:170:77]
assign _entries_T_187 = _entries_WIRE_15[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_final = _entries_T_187; // @[TLB.scala:170:77]
assign _entries_T_188 = _entries_WIRE_15[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_ptw = _entries_T_188; // @[TLB.scala:170:77]
assign _entries_T_189 = _entries_WIRE_15[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_g = _entries_T_189; // @[TLB.scala:170:77]
assign _entries_T_190 = _entries_WIRE_15[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_u = _entries_T_190; // @[TLB.scala:170:77]
assign _entries_T_191 = _entries_WIRE_15[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_14_ppn = _entries_T_191; // @[TLB.scala:170:77]
wire [19:0] _entries_T_214; // @[TLB.scala:170:77]
wire _entries_T_213; // @[TLB.scala:170:77]
wire _entries_T_212; // @[TLB.scala:170:77]
wire _entries_T_211; // @[TLB.scala:170:77]
wire _entries_T_210; // @[TLB.scala:170:77]
wire _entries_T_209; // @[TLB.scala:170:77]
wire _entries_T_208; // @[TLB.scala:170:77]
wire _entries_T_207; // @[TLB.scala:170:77]
wire _entries_T_206; // @[TLB.scala:170:77]
wire _entries_T_205; // @[TLB.scala:170:77]
wire _entries_T_204; // @[TLB.scala:170:77]
wire _entries_T_203; // @[TLB.scala:170:77]
wire _entries_T_202; // @[TLB.scala:170:77]
wire _entries_T_201; // @[TLB.scala:170:77]
wire _entries_T_200; // @[TLB.scala:170:77]
wire _entries_T_199; // @[TLB.scala:170:77]
wire _entries_T_198; // @[TLB.scala:170:77]
wire _entries_T_197; // @[TLB.scala:170:77]
wire _entries_T_196; // @[TLB.scala:170:77]
wire _entries_T_195; // @[TLB.scala:170:77]
wire _entries_T_194; // @[TLB.scala:170:77]
wire _entries_T_193; // @[TLB.scala:170:77]
wire _entries_T_192; // @[TLB.scala:170:77]
assign _entries_T_192 = _entries_WIRE_17[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_fragmented_superpage = _entries_T_192; // @[TLB.scala:170:77]
assign _entries_T_193 = _entries_WIRE_17[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_c = _entries_T_193; // @[TLB.scala:170:77]
assign _entries_T_194 = _entries_WIRE_17[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_eff = _entries_T_194; // @[TLB.scala:170:77]
assign _entries_T_195 = _entries_WIRE_17[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_paa = _entries_T_195; // @[TLB.scala:170:77]
assign _entries_T_196 = _entries_WIRE_17[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pal = _entries_T_196; // @[TLB.scala:170:77]
assign _entries_T_197 = _entries_WIRE_17[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ppp = _entries_T_197; // @[TLB.scala:170:77]
assign _entries_T_198 = _entries_WIRE_17[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pr = _entries_T_198; // @[TLB.scala:170:77]
assign _entries_T_199 = _entries_WIRE_17[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_px = _entries_T_199; // @[TLB.scala:170:77]
assign _entries_T_200 = _entries_WIRE_17[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pw = _entries_T_200; // @[TLB.scala:170:77]
assign _entries_T_201 = _entries_WIRE_17[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hr = _entries_T_201; // @[TLB.scala:170:77]
assign _entries_T_202 = _entries_WIRE_17[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hx = _entries_T_202; // @[TLB.scala:170:77]
assign _entries_T_203 = _entries_WIRE_17[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hw = _entries_T_203; // @[TLB.scala:170:77]
assign _entries_T_204 = _entries_WIRE_17[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sr = _entries_T_204; // @[TLB.scala:170:77]
assign _entries_T_205 = _entries_WIRE_17[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sx = _entries_T_205; // @[TLB.scala:170:77]
assign _entries_T_206 = _entries_WIRE_17[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sw = _entries_T_206; // @[TLB.scala:170:77]
assign _entries_T_207 = _entries_WIRE_17[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_gf = _entries_T_207; // @[TLB.scala:170:77]
assign _entries_T_208 = _entries_WIRE_17[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pf = _entries_T_208; // @[TLB.scala:170:77]
assign _entries_T_209 = _entries_WIRE_17[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_stage2 = _entries_T_209; // @[TLB.scala:170:77]
assign _entries_T_210 = _entries_WIRE_17[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_final = _entries_T_210; // @[TLB.scala:170:77]
assign _entries_T_211 = _entries_WIRE_17[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_ptw = _entries_T_211; // @[TLB.scala:170:77]
assign _entries_T_212 = _entries_WIRE_17[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_g = _entries_T_212; // @[TLB.scala:170:77]
assign _entries_T_213 = _entries_WIRE_17[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_u = _entries_T_213; // @[TLB.scala:170:77]
assign _entries_T_214 = _entries_WIRE_17[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_16_ppn = _entries_T_214; // @[TLB.scala:170:77]
wire [19:0] _entries_T_237; // @[TLB.scala:170:77]
wire _entries_T_236; // @[TLB.scala:170:77]
wire _entries_T_235; // @[TLB.scala:170:77]
wire _entries_T_234; // @[TLB.scala:170:77]
wire _entries_T_233; // @[TLB.scala:170:77]
wire _entries_T_232; // @[TLB.scala:170:77]
wire _entries_T_231; // @[TLB.scala:170:77]
wire _entries_T_230; // @[TLB.scala:170:77]
wire _entries_T_229; // @[TLB.scala:170:77]
wire _entries_T_228; // @[TLB.scala:170:77]
wire _entries_T_227; // @[TLB.scala:170:77]
wire _entries_T_226; // @[TLB.scala:170:77]
wire _entries_T_225; // @[TLB.scala:170:77]
wire _entries_T_224; // @[TLB.scala:170:77]
wire _entries_T_223; // @[TLB.scala:170:77]
wire _entries_T_222; // @[TLB.scala:170:77]
wire _entries_T_221; // @[TLB.scala:170:77]
wire _entries_T_220; // @[TLB.scala:170:77]
wire _entries_T_219; // @[TLB.scala:170:77]
wire _entries_T_218; // @[TLB.scala:170:77]
wire _entries_T_217; // @[TLB.scala:170:77]
wire _entries_T_216; // @[TLB.scala:170:77]
wire _entries_T_215; // @[TLB.scala:170:77]
assign _entries_T_215 = _entries_WIRE_19[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_fragmented_superpage = _entries_T_215; // @[TLB.scala:170:77]
assign _entries_T_216 = _entries_WIRE_19[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_c = _entries_T_216; // @[TLB.scala:170:77]
assign _entries_T_217 = _entries_WIRE_19[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_eff = _entries_T_217; // @[TLB.scala:170:77]
assign _entries_T_218 = _entries_WIRE_19[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_paa = _entries_T_218; // @[TLB.scala:170:77]
assign _entries_T_219 = _entries_WIRE_19[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pal = _entries_T_219; // @[TLB.scala:170:77]
assign _entries_T_220 = _entries_WIRE_19[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ppp = _entries_T_220; // @[TLB.scala:170:77]
assign _entries_T_221 = _entries_WIRE_19[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pr = _entries_T_221; // @[TLB.scala:170:77]
assign _entries_T_222 = _entries_WIRE_19[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_px = _entries_T_222; // @[TLB.scala:170:77]
assign _entries_T_223 = _entries_WIRE_19[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pw = _entries_T_223; // @[TLB.scala:170:77]
assign _entries_T_224 = _entries_WIRE_19[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hr = _entries_T_224; // @[TLB.scala:170:77]
assign _entries_T_225 = _entries_WIRE_19[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hx = _entries_T_225; // @[TLB.scala:170:77]
assign _entries_T_226 = _entries_WIRE_19[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hw = _entries_T_226; // @[TLB.scala:170:77]
assign _entries_T_227 = _entries_WIRE_19[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sr = _entries_T_227; // @[TLB.scala:170:77]
assign _entries_T_228 = _entries_WIRE_19[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sx = _entries_T_228; // @[TLB.scala:170:77]
assign _entries_T_229 = _entries_WIRE_19[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sw = _entries_T_229; // @[TLB.scala:170:77]
assign _entries_T_230 = _entries_WIRE_19[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_gf = _entries_T_230; // @[TLB.scala:170:77]
assign _entries_T_231 = _entries_WIRE_19[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pf = _entries_T_231; // @[TLB.scala:170:77]
assign _entries_T_232 = _entries_WIRE_19[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_stage2 = _entries_T_232; // @[TLB.scala:170:77]
assign _entries_T_233 = _entries_WIRE_19[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_final = _entries_T_233; // @[TLB.scala:170:77]
assign _entries_T_234 = _entries_WIRE_19[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_ptw = _entries_T_234; // @[TLB.scala:170:77]
assign _entries_T_235 = _entries_WIRE_19[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_g = _entries_T_235; // @[TLB.scala:170:77]
assign _entries_T_236 = _entries_WIRE_19[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_u = _entries_T_236; // @[TLB.scala:170:77]
assign _entries_T_237 = _entries_WIRE_19[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_18_ppn = _entries_T_237; // @[TLB.scala:170:77]
wire [19:0] _entries_T_260; // @[TLB.scala:170:77]
wire _entries_T_259; // @[TLB.scala:170:77]
wire _entries_T_258; // @[TLB.scala:170:77]
wire _entries_T_257; // @[TLB.scala:170:77]
wire _entries_T_256; // @[TLB.scala:170:77]
wire _entries_T_255; // @[TLB.scala:170:77]
wire _entries_T_254; // @[TLB.scala:170:77]
wire _entries_T_253; // @[TLB.scala:170:77]
wire _entries_T_252; // @[TLB.scala:170:77]
wire _entries_T_251; // @[TLB.scala:170:77]
wire _entries_T_250; // @[TLB.scala:170:77]
wire _entries_T_249; // @[TLB.scala:170:77]
wire _entries_T_248; // @[TLB.scala:170:77]
wire _entries_T_247; // @[TLB.scala:170:77]
wire _entries_T_246; // @[TLB.scala:170:77]
wire _entries_T_245; // @[TLB.scala:170:77]
wire _entries_T_244; // @[TLB.scala:170:77]
wire _entries_T_243; // @[TLB.scala:170:77]
wire _entries_T_242; // @[TLB.scala:170:77]
wire _entries_T_241; // @[TLB.scala:170:77]
wire _entries_T_240; // @[TLB.scala:170:77]
wire _entries_T_239; // @[TLB.scala:170:77]
wire _entries_T_238; // @[TLB.scala:170:77]
assign _entries_T_238 = _entries_WIRE_21[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_fragmented_superpage = _entries_T_238; // @[TLB.scala:170:77]
assign _entries_T_239 = _entries_WIRE_21[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_c = _entries_T_239; // @[TLB.scala:170:77]
assign _entries_T_240 = _entries_WIRE_21[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_eff = _entries_T_240; // @[TLB.scala:170:77]
assign _entries_T_241 = _entries_WIRE_21[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_paa = _entries_T_241; // @[TLB.scala:170:77]
assign _entries_T_242 = _entries_WIRE_21[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pal = _entries_T_242; // @[TLB.scala:170:77]
assign _entries_T_243 = _entries_WIRE_21[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ppp = _entries_T_243; // @[TLB.scala:170:77]
assign _entries_T_244 = _entries_WIRE_21[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pr = _entries_T_244; // @[TLB.scala:170:77]
assign _entries_T_245 = _entries_WIRE_21[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_px = _entries_T_245; // @[TLB.scala:170:77]
assign _entries_T_246 = _entries_WIRE_21[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pw = _entries_T_246; // @[TLB.scala:170:77]
assign _entries_T_247 = _entries_WIRE_21[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hr = _entries_T_247; // @[TLB.scala:170:77]
assign _entries_T_248 = _entries_WIRE_21[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hx = _entries_T_248; // @[TLB.scala:170:77]
assign _entries_T_249 = _entries_WIRE_21[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hw = _entries_T_249; // @[TLB.scala:170:77]
assign _entries_T_250 = _entries_WIRE_21[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sr = _entries_T_250; // @[TLB.scala:170:77]
assign _entries_T_251 = _entries_WIRE_21[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sx = _entries_T_251; // @[TLB.scala:170:77]
assign _entries_T_252 = _entries_WIRE_21[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sw = _entries_T_252; // @[TLB.scala:170:77]
assign _entries_T_253 = _entries_WIRE_21[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_gf = _entries_T_253; // @[TLB.scala:170:77]
assign _entries_T_254 = _entries_WIRE_21[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pf = _entries_T_254; // @[TLB.scala:170:77]
assign _entries_T_255 = _entries_WIRE_21[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_stage2 = _entries_T_255; // @[TLB.scala:170:77]
assign _entries_T_256 = _entries_WIRE_21[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_final = _entries_T_256; // @[TLB.scala:170:77]
assign _entries_T_257 = _entries_WIRE_21[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_ptw = _entries_T_257; // @[TLB.scala:170:77]
assign _entries_T_258 = _entries_WIRE_21[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_g = _entries_T_258; // @[TLB.scala:170:77]
assign _entries_T_259 = _entries_WIRE_21[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_u = _entries_T_259; // @[TLB.scala:170:77]
assign _entries_T_260 = _entries_WIRE_21[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_20_ppn = _entries_T_260; // @[TLB.scala:170:77]
wire [19:0] _entries_T_283; // @[TLB.scala:170:77]
wire _entries_T_282; // @[TLB.scala:170:77]
wire _entries_T_281; // @[TLB.scala:170:77]
wire _entries_T_280; // @[TLB.scala:170:77]
wire _entries_T_279; // @[TLB.scala:170:77]
wire _entries_T_278; // @[TLB.scala:170:77]
wire _entries_T_277; // @[TLB.scala:170:77]
wire _entries_T_276; // @[TLB.scala:170:77]
wire _entries_T_275; // @[TLB.scala:170:77]
wire _entries_T_274; // @[TLB.scala:170:77]
wire _entries_T_273; // @[TLB.scala:170:77]
wire _entries_T_272; // @[TLB.scala:170:77]
wire _entries_T_271; // @[TLB.scala:170:77]
wire _entries_T_270; // @[TLB.scala:170:77]
wire _entries_T_269; // @[TLB.scala:170:77]
wire _entries_T_268; // @[TLB.scala:170:77]
wire _entries_T_267; // @[TLB.scala:170:77]
wire _entries_T_266; // @[TLB.scala:170:77]
wire _entries_T_265; // @[TLB.scala:170:77]
wire _entries_T_264; // @[TLB.scala:170:77]
wire _entries_T_263; // @[TLB.scala:170:77]
wire _entries_T_262; // @[TLB.scala:170:77]
wire _entries_T_261; // @[TLB.scala:170:77]
assign _entries_T_261 = _entries_WIRE_23[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_fragmented_superpage = _entries_T_261; // @[TLB.scala:170:77]
assign _entries_T_262 = _entries_WIRE_23[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_c = _entries_T_262; // @[TLB.scala:170:77]
assign _entries_T_263 = _entries_WIRE_23[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_eff = _entries_T_263; // @[TLB.scala:170:77]
assign _entries_T_264 = _entries_WIRE_23[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_paa = _entries_T_264; // @[TLB.scala:170:77]
assign _entries_T_265 = _entries_WIRE_23[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pal = _entries_T_265; // @[TLB.scala:170:77]
assign _entries_T_266 = _entries_WIRE_23[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ppp = _entries_T_266; // @[TLB.scala:170:77]
assign _entries_T_267 = _entries_WIRE_23[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pr = _entries_T_267; // @[TLB.scala:170:77]
assign _entries_T_268 = _entries_WIRE_23[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_px = _entries_T_268; // @[TLB.scala:170:77]
assign _entries_T_269 = _entries_WIRE_23[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pw = _entries_T_269; // @[TLB.scala:170:77]
assign _entries_T_270 = _entries_WIRE_23[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hr = _entries_T_270; // @[TLB.scala:170:77]
assign _entries_T_271 = _entries_WIRE_23[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hx = _entries_T_271; // @[TLB.scala:170:77]
assign _entries_T_272 = _entries_WIRE_23[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hw = _entries_T_272; // @[TLB.scala:170:77]
assign _entries_T_273 = _entries_WIRE_23[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sr = _entries_T_273; // @[TLB.scala:170:77]
assign _entries_T_274 = _entries_WIRE_23[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sx = _entries_T_274; // @[TLB.scala:170:77]
assign _entries_T_275 = _entries_WIRE_23[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sw = _entries_T_275; // @[TLB.scala:170:77]
assign _entries_T_276 = _entries_WIRE_23[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_gf = _entries_T_276; // @[TLB.scala:170:77]
assign _entries_T_277 = _entries_WIRE_23[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pf = _entries_T_277; // @[TLB.scala:170:77]
assign _entries_T_278 = _entries_WIRE_23[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_stage2 = _entries_T_278; // @[TLB.scala:170:77]
assign _entries_T_279 = _entries_WIRE_23[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_final = _entries_T_279; // @[TLB.scala:170:77]
assign _entries_T_280 = _entries_WIRE_23[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_ptw = _entries_T_280; // @[TLB.scala:170:77]
assign _entries_T_281 = _entries_WIRE_23[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_g = _entries_T_281; // @[TLB.scala:170:77]
assign _entries_T_282 = _entries_WIRE_23[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_u = _entries_T_282; // @[TLB.scala:170:77]
assign _entries_T_283 = _entries_WIRE_23[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_22_ppn = _entries_T_283; // @[TLB.scala:170:77]
wire [19:0] _entries_T_306; // @[TLB.scala:170:77]
wire _entries_T_305; // @[TLB.scala:170:77]
wire _entries_T_304; // @[TLB.scala:170:77]
wire _entries_T_303; // @[TLB.scala:170:77]
wire _entries_T_302; // @[TLB.scala:170:77]
wire _entries_T_301; // @[TLB.scala:170:77]
wire _entries_T_300; // @[TLB.scala:170:77]
wire _entries_T_299; // @[TLB.scala:170:77]
wire _entries_T_298; // @[TLB.scala:170:77]
wire _entries_T_297; // @[TLB.scala:170:77]
wire _entries_T_296; // @[TLB.scala:170:77]
wire _entries_T_295; // @[TLB.scala:170:77]
wire _entries_T_294; // @[TLB.scala:170:77]
wire _entries_T_293; // @[TLB.scala:170:77]
wire _entries_T_292; // @[TLB.scala:170:77]
wire _entries_T_291; // @[TLB.scala:170:77]
wire _entries_T_290; // @[TLB.scala:170:77]
wire _entries_T_289; // @[TLB.scala:170:77]
wire _entries_T_288; // @[TLB.scala:170:77]
wire _entries_T_287; // @[TLB.scala:170:77]
wire _entries_T_286; // @[TLB.scala:170:77]
wire _entries_T_285; // @[TLB.scala:170:77]
wire _entries_T_284; // @[TLB.scala:170:77]
assign _entries_T_284 = _entries_WIRE_25[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_fragmented_superpage = _entries_T_284; // @[TLB.scala:170:77]
assign _entries_T_285 = _entries_WIRE_25[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_c = _entries_T_285; // @[TLB.scala:170:77]
assign _entries_T_286 = _entries_WIRE_25[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_eff = _entries_T_286; // @[TLB.scala:170:77]
assign _entries_T_287 = _entries_WIRE_25[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_paa = _entries_T_287; // @[TLB.scala:170:77]
assign _entries_T_288 = _entries_WIRE_25[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pal = _entries_T_288; // @[TLB.scala:170:77]
assign _entries_T_289 = _entries_WIRE_25[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ppp = _entries_T_289; // @[TLB.scala:170:77]
assign _entries_T_290 = _entries_WIRE_25[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pr = _entries_T_290; // @[TLB.scala:170:77]
assign _entries_T_291 = _entries_WIRE_25[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_px = _entries_T_291; // @[TLB.scala:170:77]
assign _entries_T_292 = _entries_WIRE_25[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pw = _entries_T_292; // @[TLB.scala:170:77]
assign _entries_T_293 = _entries_WIRE_25[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hr = _entries_T_293; // @[TLB.scala:170:77]
assign _entries_T_294 = _entries_WIRE_25[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hx = _entries_T_294; // @[TLB.scala:170:77]
assign _entries_T_295 = _entries_WIRE_25[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hw = _entries_T_295; // @[TLB.scala:170:77]
assign _entries_T_296 = _entries_WIRE_25[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sr = _entries_T_296; // @[TLB.scala:170:77]
assign _entries_T_297 = _entries_WIRE_25[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sx = _entries_T_297; // @[TLB.scala:170:77]
assign _entries_T_298 = _entries_WIRE_25[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sw = _entries_T_298; // @[TLB.scala:170:77]
assign _entries_T_299 = _entries_WIRE_25[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_gf = _entries_T_299; // @[TLB.scala:170:77]
assign _entries_T_300 = _entries_WIRE_25[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pf = _entries_T_300; // @[TLB.scala:170:77]
assign _entries_T_301 = _entries_WIRE_25[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_stage2 = _entries_T_301; // @[TLB.scala:170:77]
assign _entries_T_302 = _entries_WIRE_25[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_final = _entries_T_302; // @[TLB.scala:170:77]
assign _entries_T_303 = _entries_WIRE_25[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_ptw = _entries_T_303; // @[TLB.scala:170:77]
assign _entries_T_304 = _entries_WIRE_25[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_g = _entries_T_304; // @[TLB.scala:170:77]
assign _entries_T_305 = _entries_WIRE_25[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_u = _entries_T_305; // @[TLB.scala:170:77]
assign _entries_T_306 = _entries_WIRE_25[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_24_ppn = _entries_T_306; // @[TLB.scala:170:77]
wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30]
wire [1:0] ppn_res = _entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_1 = _entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_3 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_2 = _entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_4 = _ppn_ignore_T_4; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_17 = ppn_ignore_4 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_18 = {_ppn_T_17[26:20], _ppn_T_17[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_19 = _ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_20 = {ppn_res_2, _ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_5 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_22 = {_ppn_T_21[26:20], _ppn_T_21[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_23 = _ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_24 = {_ppn_T_20, _ppn_T_23}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_3 = _entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_6 = _ppn_ignore_T_6; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_25 = ppn_ignore_6 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_26 = {_ppn_T_25[26:20], _ppn_T_25[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_27 = _ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_28 = {ppn_res_3, _ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_7 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_30 = {_ppn_T_29[26:20], _ppn_T_29[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_31 = _ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_32 = {_ppn_T_28, _ppn_T_31}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_4 = _entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_8 = _ppn_ignore_T_8; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_33 = ppn_ignore_8 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_34 = {_ppn_T_33[26:20], _ppn_T_33[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_35 = _ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_36 = {ppn_res_4, _ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_9 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56]
wire ppn_ignore_9 = _ppn_ignore_T_9; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_37 = ppn_ignore_9 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_38 = {_ppn_T_37[26:20], _ppn_T_37[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_39 = _ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_40 = {_ppn_T_36, _ppn_T_39}; // @[TLB.scala:198:{18,58}]
wire [19:0] _ppn_T_41 = vpn[19:0]; // @[TLB.scala:335:30, :502:125]
wire [19:0] _ppn_T_42 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_43 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_44 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_45 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_46 = hitsVec_4 ? _entries_barrier_4_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_47 = hitsVec_5 ? _entries_barrier_5_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_48 = hitsVec_6 ? _entries_barrier_6_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_49 = hitsVec_7 ? _entries_barrier_7_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_50 = hitsVec_8 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_51 = hitsVec_9 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_52 = hitsVec_10 ? _ppn_T_24 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_53 = hitsVec_11 ? _ppn_T_32 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_54 = hitsVec_12 ? _ppn_T_40 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_55 = _ppn_T ? _ppn_T_41 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_56 = _ppn_T_42 | _ppn_T_43; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_57 = _ppn_T_56 | _ppn_T_44; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_58 = _ppn_T_57 | _ppn_T_45; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_59 = _ppn_T_58 | _ppn_T_46; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_60 = _ppn_T_59 | _ppn_T_47; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_61 = _ppn_T_60 | _ppn_T_48; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_62 = _ppn_T_61 | _ppn_T_49; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_63 = _ppn_T_62 | _ppn_T_50; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_64 = _ppn_T_63 | _ppn_T_51; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_65 = _ppn_T_64 | _ppn_T_52; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_66 = _ppn_T_65 | _ppn_T_53; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_67 = _ppn_T_66 | _ppn_T_54; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_68 = _ppn_T_67 | _ppn_T_55; // @[Mux.scala:30:73]
wire [19:0] ppn = _ppn_T_68; // @[Mux.scala:30:73]
wire [1:0] ptw_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_ptw, _entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_ptw, _entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_ptw, _entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27]
wire [1:0] final_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_lo_lo = {final_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_lo_hi = {final_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [5:0] final_ae_array_lo = {final_ae_array_lo_hi, final_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] final_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_final, _entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_hi_lo = {final_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_final, _entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_final, _entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [3:0] final_ae_array_hi_hi = {final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] final_ae_array_hi = {final_ae_array_hi_hi, final_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27]
wire [1:0] ptw_pf_array_lo_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_lo_lo = {ptw_pf_array_lo_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_lo_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_lo_hi = {ptw_pf_array_lo_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, ptw_pf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_pf_array_hi_lo_hi = {_entries_barrier_8_io_y_pf, _entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_hi_lo = {ptw_pf_array_hi_lo_hi, _entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_hi_hi_lo = {_entries_barrier_10_io_y_pf, _entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_hi_hi_hi = {_entries_barrier_12_io_y_pf, _entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_pf_array_hi_hi = {ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, ptw_pf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27]
wire [1:0] ptw_gf_array_lo_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_lo_lo = {ptw_gf_array_lo_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_lo_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_lo_hi = {ptw_gf_array_lo_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, ptw_gf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_gf_array_hi_lo_hi = {_entries_barrier_8_io_y_gf, _entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_hi_lo = {ptw_gf_array_hi_lo_hi, _entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_hi_hi_lo = {_entries_barrier_10_io_y_gf, _entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_hi_hi_hi = {_entries_barrier_12_io_y_gf, _entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_gf_array_hi_hi = {ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, ptw_gf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27]
wire [13:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82]
wire [13:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63]
wire [13:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46]
wire _priv_rw_ok_T = ~priv_s; // @[TLB.scala:370:20, :513:24]
wire _priv_rw_ok_T_1 = _priv_rw_ok_T | sum; // @[TLB.scala:510:16, :513:{24,32}]
wire [1:0] _GEN_40 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27]
assign priv_rw_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27]
assign priv_x_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign priv_x_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_41 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27]
assign priv_x_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign priv_x_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_42 = {_entries_barrier_8_io_y_u, _entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27]
assign priv_rw_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27]
assign priv_x_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign priv_x_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_43 = {_entries_barrier_10_io_y_u, _entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27]
wire [1:0] _GEN_44 = {_entries_barrier_12_io_y_u, _entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27]
wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_1 ? _priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_6 = priv_s ? _priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}]
wire [12:0] priv_rw_ok = _priv_rw_ok_T_3 | _priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}]
wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27]
wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] priv_x_ok = priv_s ? _priv_x_ok_T_1 : _priv_x_ok_T_2; // @[package.scala:45:27]
wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83]
wire [12:0] _stage1_bypass_T_2 = {13{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}]
wire [1:0] stage1_bypass_lo_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_lo_lo = {stage1_bypass_lo_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_lo_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_lo_hi = {stage1_bypass_lo_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [5:0] stage1_bypass_lo = {stage1_bypass_lo_hi, stage1_bypass_lo_lo}; // @[package.scala:45:27]
wire [1:0] stage1_bypass_hi_lo_hi = {_entries_barrier_8_io_y_ae_stage2, _entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_hi_lo = {stage1_bypass_hi_lo_hi, _entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_hi_hi_lo = {_entries_barrier_10_io_y_ae_stage2, _entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_hi_hi_hi = {_entries_barrier_12_io_y_ae_stage2, _entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [3:0] stage1_bypass_hi_hi = {stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] stage1_bypass_hi = {stage1_bypass_hi_hi, stage1_bypass_hi_lo}; // @[package.scala:45:27]
wire [12:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27]
wire [12:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 | _stage1_bypass_T_3; // @[package.scala:45:27]
wire [1:0] r_array_lo_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] r_array_hi_lo_hi = {_entries_barrier_8_io_y_sr, _entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, _entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_lo = {_entries_barrier_10_io_y_sr, _entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_hi = {_entries_barrier_12_io_y_sr, _entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_45 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27]
assign r_array_lo_lo_hi_1 = _GEN_45; // @[package.scala:45:27]
wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27]
assign x_array_lo_lo_hi = _GEN_45; // @[package.scala:45:27]
wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_46 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27]
assign r_array_lo_hi_hi_1 = _GEN_46; // @[package.scala:45:27]
wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27]
assign x_array_lo_hi_hi = _GEN_46; // @[package.scala:45:27]
wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_47 = {_entries_barrier_8_io_y_sx, _entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27]
assign r_array_hi_lo_hi_1 = _GEN_47; // @[package.scala:45:27]
wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27]
assign x_array_hi_lo_hi = _GEN_47; // @[package.scala:45:27]
wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_48 = {_entries_barrier_10_io_y_sx, _entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27]
assign r_array_hi_hi_lo_1 = _GEN_48; // @[package.scala:45:27]
wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27]
assign x_array_hi_hi_lo = _GEN_48; // @[package.scala:45:27]
wire [1:0] _GEN_49 = {_entries_barrier_12_io_y_sx, _entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27]
assign r_array_hi_hi_hi_1 = _GEN_49; // @[package.scala:45:27]
wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27]
assign x_array_hi_hi_hi = _GEN_49; // @[package.scala:45:27]
wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27]
wire [12:0] _r_array_T_2 = mxr ? _r_array_T_1 : 13'h0; // @[package.scala:45:27]
wire [12:0] _r_array_T_3 = _r_array_T | _r_array_T_2; // @[package.scala:45:27]
wire [12:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}]
wire [12:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}]
wire [13:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}]
wire [13:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41]
wire [1:0] w_array_lo_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_lo_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] w_array_hi_lo_hi = {_entries_barrier_8_io_y_sw, _entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, _entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_hi_hi_lo = {_entries_barrier_10_io_y_sw, _entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_hi_hi_hi = {_entries_barrier_12_io_y_sw, _entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27]
wire [12:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27]
wire [12:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}]
wire [13:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}]
wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27]
wire [12:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27]
wire [12:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}]
wire [13:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}]
wire [1:0] hr_array_lo_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_lo_lo = {hr_array_lo_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_lo_hi = {hr_array_lo_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [5:0] hr_array_lo = {hr_array_lo_hi, hr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] hr_array_hi_lo_hi = {_entries_barrier_8_io_y_hr, _entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_hi_lo = {hr_array_hi_lo_hi, _entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_lo = {_entries_barrier_10_io_y_hr, _entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_hi = {_entries_barrier_12_io_y_hr, _entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [3:0] hr_array_hi_hi = {hr_array_hi_hi_hi, hr_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hr_array_hi = {hr_array_hi_hi, hr_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_50 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_lo_hi_1; // @[package.scala:45:27]
assign hr_array_lo_lo_hi_1 = _GEN_50; // @[package.scala:45:27]
wire [1:0] hx_array_lo_lo_hi; // @[package.scala:45:27]
assign hx_array_lo_lo_hi = _GEN_50; // @[package.scala:45:27]
wire [2:0] hr_array_lo_lo_1 = {hr_array_lo_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_51 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_hi_hi_1; // @[package.scala:45:27]
assign hr_array_lo_hi_hi_1 = _GEN_51; // @[package.scala:45:27]
wire [1:0] hx_array_lo_hi_hi; // @[package.scala:45:27]
assign hx_array_lo_hi_hi = _GEN_51; // @[package.scala:45:27]
wire [2:0] hr_array_lo_hi_1 = {hr_array_lo_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] hr_array_lo_1 = {hr_array_lo_hi_1, hr_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_52 = {_entries_barrier_8_io_y_hx, _entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_lo_hi_1; // @[package.scala:45:27]
assign hr_array_hi_lo_hi_1 = _GEN_52; // @[package.scala:45:27]
wire [1:0] hx_array_hi_lo_hi; // @[package.scala:45:27]
assign hx_array_hi_lo_hi = _GEN_52; // @[package.scala:45:27]
wire [2:0] hr_array_hi_lo_1 = {hr_array_hi_lo_hi_1, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_53 = {_entries_barrier_10_io_y_hx, _entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_lo_1; // @[package.scala:45:27]
assign hr_array_hi_hi_lo_1 = _GEN_53; // @[package.scala:45:27]
wire [1:0] hx_array_hi_hi_lo; // @[package.scala:45:27]
assign hx_array_hi_hi_lo = _GEN_53; // @[package.scala:45:27]
wire [1:0] _GEN_54 = {_entries_barrier_12_io_y_hx, _entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_hi_1; // @[package.scala:45:27]
assign hr_array_hi_hi_hi_1 = _GEN_54; // @[package.scala:45:27]
wire [1:0] hx_array_hi_hi_hi; // @[package.scala:45:27]
assign hx_array_hi_hi_hi = _GEN_54; // @[package.scala:45:27]
wire [3:0] hr_array_hi_hi_1 = {hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] hr_array_hi_1 = {hr_array_hi_hi_1, hr_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27]
wire [12:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 13'h0; // @[package.scala:45:27]
wire [12:0] _hr_array_T_3 = _hr_array_T | _hr_array_T_2; // @[package.scala:45:27]
wire [1:0] hw_array_lo_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_lo_lo = {hw_array_lo_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_lo_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_lo_hi = {hw_array_lo_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [5:0] hw_array_lo = {hw_array_lo_hi, hw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] hw_array_hi_lo_hi = {_entries_barrier_8_io_y_hw, _entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_hi_lo = {hw_array_hi_lo_hi, _entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_hi_hi_lo = {_entries_barrier_10_io_y_hw, _entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_hi_hi_hi = {_entries_barrier_12_io_y_hw, _entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [3:0] hw_array_hi_hi = {hw_array_hi_hi_hi, hw_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hw_array_hi = {hw_array_hi_hi, hw_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27]
wire [2:0] hx_array_lo_lo = {hx_array_lo_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [2:0] hx_array_lo_hi = {hx_array_lo_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] hx_array_lo = {hx_array_lo_hi, hx_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] hx_array_hi_lo = {hx_array_hi_lo_hi, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [3:0] hx_array_hi_hi = {hx_array_hi_hi_hi, hx_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hx_array_hi = {hx_array_hi_hi, hx_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27]
wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26]
wire [1:0] pr_array_lo_lo_hi = {_entries_barrier_2_io_y_pr, _entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pr_array_lo_hi_hi = {_entries_barrier_5_io_y_pr, _entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pr_array_hi_lo_hi = {_entries_barrier_8_io_y_pr, _entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, _entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pr_array_hi_hi_hi = {_entries_barrier_11_io_y_pr, _entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, _entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27]
wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27]
wire [13:0] _GEN_55 = ptw_ae_array | final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104]
wire [13:0] _pr_array_T_3; // @[TLB.scala:529:104]
assign _pr_array_T_3 = _GEN_55; // @[TLB.scala:529:104]
wire [13:0] _pw_array_T_3; // @[TLB.scala:531:104]
assign _pw_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :531:104]
wire [13:0] _px_array_T_3; // @[TLB.scala:533:104]
assign _px_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :533:104]
wire [13:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}]
wire [13:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}]
wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26]
wire [1:0] pw_array_lo_lo_hi = {_entries_barrier_2_io_y_pw, _entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pw_array_lo_hi_hi = {_entries_barrier_5_io_y_pw, _entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pw_array_hi_lo_hi = {_entries_barrier_8_io_y_pw, _entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, _entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pw_array_hi_hi_hi = {_entries_barrier_11_io_y_pw, _entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, _entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27]
wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27]
wire [13:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}]
wire [13:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}]
wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26]
wire [1:0] px_array_lo_lo_hi = {_entries_barrier_2_io_y_px, _entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] px_array_lo_hi_hi = {_entries_barrier_5_io_y_px, _entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] px_array_hi_lo_hi = {_entries_barrier_8_io_y_px, _entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, _entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] px_array_hi_hi_hi = {_entries_barrier_11_io_y_px, _entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, _entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27]
wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27]
wire [13:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}]
wire [13:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}]
wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27]
wire [1:0] eff_array_lo_lo_hi = {_entries_barrier_2_io_y_eff, _entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] eff_array_lo_hi_hi = {_entries_barrier_5_io_y_eff, _entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] eff_array_hi_lo_hi = {_entries_barrier_8_io_y_eff, _entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, _entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] eff_array_hi_hi_hi = {_entries_barrier_11_io_y_eff, _entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, _entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27]
wire [13:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27]
wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25]
wire [1:0] _GEN_56 = {_entries_barrier_2_io_y_c, _entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27]
assign c_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27]
wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27]
assign prefetchable_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27]
wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_57 = {_entries_barrier_5_io_y_c, _entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27]
assign c_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27]
wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27]
assign prefetchable_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27]
wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_58 = {_entries_barrier_8_io_y_c, _entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27]
assign c_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27]
wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27]
assign prefetchable_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27]
wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_59 = {_entries_barrier_11_io_y_c, _entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27]
assign c_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27]
wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27]
assign prefetchable_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27]
wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27]
wire [13:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27]
wire [13:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24]
wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27]
wire [1:0] ppp_array_lo_lo_hi = {_entries_barrier_2_io_y_ppp, _entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_lo_lo = {ppp_array_lo_lo_hi, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] ppp_array_lo_hi_hi = {_entries_barrier_5_io_y_ppp, _entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_lo_hi = {ppp_array_lo_hi_hi, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] ppp_array_lo = {ppp_array_lo_hi, ppp_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ppp_array_hi_lo_hi = {_entries_barrier_8_io_y_ppp, _entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_hi_lo = {ppp_array_hi_lo_hi, _entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] ppp_array_hi_hi_hi = {_entries_barrier_11_io_y_ppp, _entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_hi_hi = {ppp_array_hi_hi_hi, _entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] ppp_array_hi = {ppp_array_hi_hi, ppp_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27]
wire [13:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27]
wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27]
wire [1:0] paa_array_lo_lo_hi = {_entries_barrier_2_io_y_paa, _entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] paa_array_lo_hi_hi = {_entries_barrier_5_io_y_paa, _entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] paa_array_hi_lo_hi = {_entries_barrier_8_io_y_paa, _entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, _entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] paa_array_hi_hi_hi = {_entries_barrier_11_io_y_paa, _entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, _entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27]
wire [13:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27]
wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27]
wire [1:0] pal_array_lo_lo_hi = {_entries_barrier_2_io_y_pal, _entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pal_array_lo_hi_hi = {_entries_barrier_5_io_y_pal, _entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pal_array_hi_lo_hi = {_entries_barrier_8_io_y_pal, _entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, _entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pal_array_hi_hi_hi = {_entries_barrier_11_io_y_pal, _entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, _entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27]
wire [13:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27]
wire [13:0] ppp_array_if_cached = ppp_array | c_array; // @[TLB.scala:537:20, :539:22, :544:39]
wire [13:0] paa_array_if_cached = paa_array | c_array; // @[TLB.scala:537:20, :541:22, :545:39]
wire [13:0] pal_array_if_cached = pal_array | c_array; // @[TLB.scala:537:20, :543:22, :546:39]
wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65]
wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}]
wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27]
wire [13:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27]
wire [39:0] _misaligned_T_3 = {38'h0, io_req_bits_vaddr_0[1:0]}; // @[TLB.scala:318:7, :550:39]
wire misaligned = |_misaligned_T_3; // @[TLB.scala:550:{39,77}]
assign _io_resp_ma_ld_T = misaligned; // @[TLB.scala:550:77, :645:31]
wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21]
wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43]
wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51]
wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86]
wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}]
wire _bad_va_T_5 = _bad_va_T_2 | _bad_va_T_4; // @[TLB.scala:560:{51,59,71}]
wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}]
wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}]
wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}]
wire _io_resp_pf_ld_T = bad_va; // @[TLB.scala:568:34, :633:28]
wire [13:0] _ae_array_T = misaligned ? eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8]
wire [13:0] ae_array = _ae_array_T; // @[TLB.scala:582:{8,37}]
wire [13:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19]
wire [13:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46]
wire [13:0] _ae_ld_array_T_1 = ae_array | _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}]
wire [13:0] ae_ld_array = _ae_ld_array_T_1; // @[TLB.scala:586:{24,44}]
wire [13:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37]
wire [13:0] _ae_st_array_T_1 = ae_array | _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}]
wire [13:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26]
wire [13:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26]
wire [13:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29]
wire [13:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26]
wire [13:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26]
wire [13:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29]
wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}]
wire [13:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73]
wire [13:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}]
wire [13:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 | ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}]
wire [13:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106]
wire [13:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}]
wire [13:0] pf_ld_array = _pf_ld_array_T_6; // @[TLB.scala:597:{24,104}]
wire [13:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44]
wire [13:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55]
wire [13:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}]
wire [13:0] _pf_st_array_T_3 = _pf_st_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}]
wire [13:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88]
wire [13:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}]
wire [13:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25]
wire [13:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36]
wire [13:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}]
wire [13:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}]
wire [13:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69]
wire [13:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}]
wire [13:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100]
wire [13:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}]
wire [13:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81]
wire [13:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}]
wire [13:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64]
wire [13:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}]
wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73]
wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}]
wire [11:0] _gpa_hits_hit_mask_T_2 = {12{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}]
wire tlb_hit_if_not_gpa_miss = |real_hits; // @[package.scala:45:27]
wire tlb_hit = |_tlb_hit_T; // @[TLB.scala:611:{28,40}]
wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56]
wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}]
wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67]
wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}]
reg [6:0] state_vec_0; // @[Replacement.scala:305:17]
reg [2:0] state_reg_1; // @[Replacement.scala:168:70]
wire [1:0] _GEN_60 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45]
wire [1:0] lo_lo; // @[OneHot.scala:21:45]
assign lo_lo = _GEN_60; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_lo_lo; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_lo_lo = _GEN_60; // @[OneHot.scala:21:45]
wire [1:0] _GEN_61 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45]
wire [1:0] lo_hi; // @[OneHot.scala:21:45]
assign lo_hi = _GEN_61; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_lo_hi; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_lo_hi = _GEN_61; // @[OneHot.scala:21:45]
wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:21:45]
wire [3:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18]
wire [1:0] _GEN_62 = {sector_hits_5, sector_hits_4}; // @[OneHot.scala:21:45]
wire [1:0] hi_lo; // @[OneHot.scala:21:45]
assign hi_lo = _GEN_62; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_hi_lo; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_hi_lo = _GEN_62; // @[OneHot.scala:21:45]
wire [1:0] _GEN_63 = {sector_hits_7, sector_hits_6}; // @[OneHot.scala:21:45]
wire [1:0] hi_hi; // @[OneHot.scala:21:45]
assign hi_hi = _GEN_63; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_hi_hi; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_hi_hi = _GEN_63; // @[OneHot.scala:21:45]
wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:21:45]
wire [3:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18]
wire [3:0] _T_33 = hi_1 | lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28]
wire [2:0] state_vec_0_touch_way_sized = {|hi_1, |hi_2, hi_2[1] | lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_vec_0_set_left_older_T = state_vec_0_touch_way_sized[2]; // @[package.scala:163:13]
wire state_vec_0_set_left_older = ~_state_vec_0_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire [2:0] state_vec_0_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13]
wire [2:0] r_sectored_repl_addr_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13]
wire [2:0] state_vec_0_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :305:17]
wire [2:0] r_sectored_repl_addr_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :245:38, :305:17]
wire [1:0] _state_vec_0_T = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13]
wire [1:0] _state_vec_0_T_11 = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13]
wire _state_vec_0_set_left_older_T_1 = _state_vec_0_T[1]; // @[package.scala:163:13]
wire state_vec_0_set_left_older_1 = ~_state_vec_0_set_left_older_T_1; // @[Replacement.scala:196:{33,43}]
wire state_vec_0_left_subtree_state_1 = state_vec_0_left_subtree_state[1]; // @[package.scala:163:13]
wire state_vec_0_right_subtree_state_1 = state_vec_0_left_subtree_state[0]; // @[package.scala:163:13]
wire _state_vec_0_T_1 = _state_vec_0_T[0]; // @[package.scala:163:13]
wire _state_vec_0_T_5 = _state_vec_0_T[0]; // @[package.scala:163:13]
wire _state_vec_0_T_2 = _state_vec_0_T_1; // @[package.scala:163:13]
wire _state_vec_0_T_3 = ~_state_vec_0_T_2; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_4 = state_vec_0_set_left_older_1 ? state_vec_0_left_subtree_state_1 : _state_vec_0_T_3; // @[package.scala:163:13]
wire _state_vec_0_T_6 = _state_vec_0_T_5; // @[Replacement.scala:207:62, :218:17]
wire _state_vec_0_T_7 = ~_state_vec_0_T_6; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_8 = state_vec_0_set_left_older_1 ? _state_vec_0_T_7 : state_vec_0_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_vec_0_hi = {state_vec_0_set_left_older_1, _state_vec_0_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_vec_0_T_9 = {state_vec_0_hi, _state_vec_0_T_8}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_vec_0_T_10 = state_vec_0_set_left_older ? state_vec_0_left_subtree_state : _state_vec_0_T_9; // @[package.scala:163:13]
wire _state_vec_0_set_left_older_T_2 = _state_vec_0_T_11[1]; // @[Replacement.scala:196:43, :207:62]
wire state_vec_0_set_left_older_2 = ~_state_vec_0_set_left_older_T_2; // @[Replacement.scala:196:{33,43}]
wire state_vec_0_left_subtree_state_2 = state_vec_0_right_subtree_state[1]; // @[package.scala:163:13]
wire state_vec_0_right_subtree_state_2 = state_vec_0_right_subtree_state[0]; // @[Replacement.scala:198:38]
wire _state_vec_0_T_12 = _state_vec_0_T_11[0]; // @[package.scala:163:13]
wire _state_vec_0_T_16 = _state_vec_0_T_11[0]; // @[package.scala:163:13]
wire _state_vec_0_T_13 = _state_vec_0_T_12; // @[package.scala:163:13]
wire _state_vec_0_T_14 = ~_state_vec_0_T_13; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_15 = state_vec_0_set_left_older_2 ? state_vec_0_left_subtree_state_2 : _state_vec_0_T_14; // @[package.scala:163:13]
wire _state_vec_0_T_17 = _state_vec_0_T_16; // @[Replacement.scala:207:62, :218:17]
wire _state_vec_0_T_18 = ~_state_vec_0_T_17; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_19 = state_vec_0_set_left_older_2 ? _state_vec_0_T_18 : state_vec_0_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_vec_0_hi_1 = {state_vec_0_set_left_older_2, _state_vec_0_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_vec_0_T_20 = {state_vec_0_hi_1, _state_vec_0_T_19}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_vec_0_T_21 = state_vec_0_set_left_older ? _state_vec_0_T_20 : state_vec_0_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_vec_0_hi_2 = {state_vec_0_set_left_older, _state_vec_0_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_vec_0_T_22 = {state_vec_0_hi_2, _state_vec_0_T_21}; // @[Replacement.scala:202:12, :206:16]
wire [1:0] _GEN_64 = {superpage_hits_1, superpage_hits_0}; // @[OneHot.scala:21:45]
wire [1:0] lo_3; // @[OneHot.scala:21:45]
assign lo_3 = _GEN_64; // @[OneHot.scala:21:45]
wire [1:0] r_superpage_hit_bits_lo; // @[OneHot.scala:21:45]
assign r_superpage_hit_bits_lo = _GEN_64; // @[OneHot.scala:21:45]
wire [1:0] lo_4 = lo_3; // @[OneHot.scala:21:45, :31:18]
wire [1:0] _GEN_65 = {superpage_hits_3, superpage_hits_2}; // @[OneHot.scala:21:45]
wire [1:0] hi_3; // @[OneHot.scala:21:45]
assign hi_3 = _GEN_65; // @[OneHot.scala:21:45]
wire [1:0] r_superpage_hit_bits_hi; // @[OneHot.scala:21:45]
assign r_superpage_hit_bits_hi = _GEN_65; // @[OneHot.scala:21:45]
wire [1:0] hi_4 = hi_3; // @[OneHot.scala:21:45, :30:18]
wire [1:0] state_reg_touch_way_sized = {|hi_4, hi_4[1] | lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_reg_set_left_older_T = state_reg_touch_way_sized[1]; // @[package.scala:163:13]
wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13]
wire r_superpage_repl_addr_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38]
wire r_superpage_repl_addr_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire _state_reg_T = state_reg_touch_way_sized[0]; // @[package.scala:163:13]
wire _state_reg_T_4 = state_reg_touch_way_sized[0]; // @[package.scala:163:13]
wire _state_reg_T_1 = _state_reg_T; // @[package.scala:163:13]
wire _state_reg_T_2 = ~_state_reg_T_1; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_3 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_2; // @[package.scala:163:13]
wire _state_reg_T_5 = _state_reg_T_4; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_6 = ~_state_reg_T_5; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_7 = state_reg_set_left_older ? _state_reg_T_6 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi = {state_reg_set_left_older, _state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_8 = {state_reg_hi, _state_reg_T_7}; // @[Replacement.scala:202:12, :206:16]
wire [5:0] _multipleHits_T = real_hits[5:0]; // @[package.scala:45:27]
wire [2:0] _multipleHits_T_1 = _multipleHits_T[2:0]; // @[Misc.scala:181:37]
wire _multipleHits_T_2 = _multipleHits_T_1[0]; // @[Misc.scala:181:37]
wire multipleHits_leftOne = _multipleHits_T_2; // @[Misc.scala:178:18, :181:37]
wire [1:0] _multipleHits_T_3 = _multipleHits_T_1[2:1]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_4 = _multipleHits_T_3[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_1 = _multipleHits_T_4; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_5 = _multipleHits_T_3[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne = _multipleHits_T_5; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_1 = multipleHits_leftOne_1 | multipleHits_rightOne; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_7 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo = _multipleHits_T_7; // @[Misc.scala:183:{49,61}]
wire _multipleHits_T_8 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}]
wire multipleHits_leftOne_2 = multipleHits_leftOne | multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_9 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}]
wire multipleHits_leftTwo = _multipleHits_T_8 | _multipleHits_T_9; // @[Misc.scala:183:{37,49,61}]
wire [2:0] _multipleHits_T_10 = _multipleHits_T[5:3]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_11 = _multipleHits_T_10[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_3 = _multipleHits_T_11; // @[Misc.scala:178:18, :181:37]
wire [1:0] _multipleHits_T_12 = _multipleHits_T_10[2:1]; // @[Misc.scala:182:39]
wire _multipleHits_T_13 = _multipleHits_T_12[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_4 = _multipleHits_T_13; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_14 = _multipleHits_T_12[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne_2 = _multipleHits_T_14; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_3 = multipleHits_leftOne_4 | multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_16 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo_1 = _multipleHits_T_16; // @[Misc.scala:183:{49,61}]
wire _multipleHits_T_17 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}]
wire multipleHits_rightOne_4 = multipleHits_leftOne_3 | multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_18 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}]
wire multipleHits_rightTwo_2 = _multipleHits_T_17 | _multipleHits_T_18; // @[Misc.scala:183:{37,49,61}]
wire multipleHits_leftOne_5 = multipleHits_leftOne_2 | multipleHits_rightOne_4; // @[Misc.scala:183:16]
wire _multipleHits_T_19 = multipleHits_leftTwo | multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}]
wire multipleHits_leftTwo_1 = _multipleHits_T_19 | _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}]
wire [6:0] _multipleHits_T_21 = real_hits[12:6]; // @[package.scala:45:27]
wire [2:0] _multipleHits_T_22 = _multipleHits_T_21[2:0]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_23 = _multipleHits_T_22[0]; // @[Misc.scala:181:37]
wire multipleHits_leftOne_6 = _multipleHits_T_23; // @[Misc.scala:178:18, :181:37]
wire [1:0] _multipleHits_T_24 = _multipleHits_T_22[2:1]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_25 = _multipleHits_T_24[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_7 = _multipleHits_T_25; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_26 = _multipleHits_T_24[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne_5 = _multipleHits_T_26; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_6 = multipleHits_leftOne_7 | multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_28 = multipleHits_leftOne_7 & multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo_3 = _multipleHits_T_28; // @[Misc.scala:183:{49,61}]
wire _multipleHits_T_29 = multipleHits_rightTwo_3; // @[Misc.scala:183:{37,49}]
wire multipleHits_leftOne_8 = multipleHits_leftOne_6 | multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_30 = multipleHits_leftOne_6 & multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:{16,61}]
wire multipleHits_leftTwo_2 = _multipleHits_T_29 | _multipleHits_T_30; // @[Misc.scala:183:{37,49,61}]
wire [3:0] _multipleHits_T_31 = _multipleHits_T_21[6:3]; // @[Misc.scala:182:39]
wire [1:0] _multipleHits_T_32 = _multipleHits_T_31[1:0]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_33 = _multipleHits_T_32[0]; // @[Misc.scala:181:37]
wire multipleHits_leftOne_9 = _multipleHits_T_33; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_34 = _multipleHits_T_32[1]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_rightOne_7 = _multipleHits_T_34; // @[Misc.scala:178:18, :182:39]
wire multipleHits_leftOne_10 = multipleHits_leftOne_9 | multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_36 = multipleHits_leftOne_9 & multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:61]
wire multipleHits_leftTwo_3 = _multipleHits_T_36; // @[Misc.scala:183:{49,61}]
wire [1:0] _multipleHits_T_37 = _multipleHits_T_31[3:2]; // @[Misc.scala:182:39]
wire _multipleHits_T_38 = _multipleHits_T_37[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_11 = _multipleHits_T_38; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_39 = _multipleHits_T_37[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne_8 = _multipleHits_T_39; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_9 = multipleHits_leftOne_11 | multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_41 = multipleHits_leftOne_11 & multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo_4 = _multipleHits_T_41; // @[Misc.scala:183:{49,61}]
wire multipleHits_rightOne_10 = multipleHits_leftOne_10 | multipleHits_rightOne_9; // @[Misc.scala:183:16]
wire _multipleHits_T_42 = multipleHits_leftTwo_3 | multipleHits_rightTwo_4; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_43 = multipleHits_leftOne_10 & multipleHits_rightOne_9; // @[Misc.scala:183:{16,61}]
wire multipleHits_rightTwo_5 = _multipleHits_T_42 | _multipleHits_T_43; // @[Misc.scala:183:{37,49,61}]
wire multipleHits_rightOne_11 = multipleHits_leftOne_8 | multipleHits_rightOne_10; // @[Misc.scala:183:16]
wire _multipleHits_T_44 = multipleHits_leftTwo_2 | multipleHits_rightTwo_5; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_45 = multipleHits_leftOne_8 & multipleHits_rightOne_10; // @[Misc.scala:183:{16,61}]
wire multipleHits_rightTwo_6 = _multipleHits_T_44 | _multipleHits_T_45; // @[Misc.scala:183:{37,49,61}]
wire _multipleHits_T_46 = multipleHits_leftOne_5 | multipleHits_rightOne_11; // @[Misc.scala:183:16]
wire _multipleHits_T_47 = multipleHits_leftTwo_1 | multipleHits_rightTwo_6; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_48 = multipleHits_leftOne_5 & multipleHits_rightOne_11; // @[Misc.scala:183:{16,61}]
wire multipleHits = _multipleHits_T_47 | _multipleHits_T_48; // @[Misc.scala:183:{37,49,61}]
assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25]
assign io_req_ready_0 = _io_req_ready_T; // @[TLB.scala:318:7, :631:25]
wire [13:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57]
wire _io_resp_pf_ld_T_2 = |_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}]
assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T | _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}]
assign io_resp_pf_ld_0 = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41]
wire [13:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47]
wire _io_resp_pf_inst_T_1 = |_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}]
assign _io_resp_pf_inst_T_2 = bad_va | _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}]
assign io_resp_pf_inst_0 = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29]
wire [13:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33]
assign _io_resp_ae_ld_T_1 = |_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}]
assign io_resp_ae_ld_0 = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41]
wire [13:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23]
wire [13:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}]
assign _io_resp_ae_inst_T_2 = |_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}]
assign io_resp_ae_inst_0 = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41]
assign io_resp_ma_ld_0 = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31]
wire [13:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33]
assign _io_resp_cacheable_T_1 = |_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}]
assign io_resp_cacheable_0 = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41]
wire [13:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47]
wire _io_resp_prefetchable_T_1 = |_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}]
assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}]
assign io_resp_prefetchable_0 = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59]
wire _io_resp_miss_T_1 = _io_resp_miss_T | tlb_miss; // @[TLB.scala:613:64, :651:{29,52}]
assign _io_resp_miss_T_2 = _io_resp_miss_T_1 | multipleHits; // @[Misc.scala:183:49]
assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64]
assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73]
assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23]
wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36]
wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}]
wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58]
wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47]
wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}]
assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8]
assign io_resp_gpa_0 = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8]
assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29]
assign _io_ptw_req_bits_valid_T = ~io_kill_0; // @[TLB.scala:318:7, :663:28]
assign io_ptw_req_bits_valid_0 = _io_ptw_req_bits_valid_T; // @[TLB.scala:318:7, :663:28]
wire r_superpage_repl_addr_left_subtree_older = state_reg_1[2]; // @[Replacement.scala:168:70, :243:38]
wire _r_superpage_repl_addr_T = r_superpage_repl_addr_left_subtree_state; // @[package.scala:163:13]
wire _r_superpage_repl_addr_T_1 = r_superpage_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12]
wire _r_superpage_repl_addr_T_2 = r_superpage_repl_addr_left_subtree_older ? _r_superpage_repl_addr_T : _r_superpage_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_superpage_repl_addr_T_3 = {r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] r_superpage_repl_addr_valids_lo = {superpage_entries_1_valid_0, superpage_entries_0_valid_0}; // @[package.scala:45:27]
wire [1:0] r_superpage_repl_addr_valids_hi = {superpage_entries_3_valid_0, superpage_entries_2_valid_0}; // @[package.scala:45:27]
wire [3:0] r_superpage_repl_addr_valids = {r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo}; // @[package.scala:45:27]
wire _r_superpage_repl_addr_T_4 = &r_superpage_repl_addr_valids; // @[package.scala:45:27]
wire [3:0] _r_superpage_repl_addr_T_5 = ~r_superpage_repl_addr_valids; // @[package.scala:45:27]
wire _r_superpage_repl_addr_T_6 = _r_superpage_repl_addr_T_5[0]; // @[OneHot.scala:48:45]
wire _r_superpage_repl_addr_T_7 = _r_superpage_repl_addr_T_5[1]; // @[OneHot.scala:48:45]
wire _r_superpage_repl_addr_T_8 = _r_superpage_repl_addr_T_5[2]; // @[OneHot.scala:48:45]
wire _r_superpage_repl_addr_T_9 = _r_superpage_repl_addr_T_5[3]; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_10 = {1'h1, ~_r_superpage_repl_addr_T_8}; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_11 = _r_superpage_repl_addr_T_7 ? 2'h1 : _r_superpage_repl_addr_T_10; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_12 = _r_superpage_repl_addr_T_6 ? 2'h0 : _r_superpage_repl_addr_T_11; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_13 = _r_superpage_repl_addr_T_4 ? _r_superpage_repl_addr_T_3 : _r_superpage_repl_addr_T_12; // @[Mux.scala:50:70]
wire r_sectored_repl_addr_left_subtree_older = state_vec_0[6]; // @[Replacement.scala:243:38, :305:17]
wire r_sectored_repl_addr_left_subtree_older_1 = r_sectored_repl_addr_left_subtree_state[2]; // @[package.scala:163:13]
wire r_sectored_repl_addr_left_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[1]; // @[package.scala:163:13]
wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state_1; // @[package.scala:163:13]
wire r_sectored_repl_addr_right_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[0]; // @[package.scala:163:13]
wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12]
wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older_1 ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire r_sectored_repl_addr_left_subtree_older_2 = r_sectored_repl_addr_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38]
wire r_sectored_repl_addr_left_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[1]; // @[package.scala:163:13]
wire _r_sectored_repl_addr_T_4 = r_sectored_repl_addr_left_subtree_state_2; // @[package.scala:163:13]
wire r_sectored_repl_addr_right_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[0]; // @[Replacement.scala:245:38]
wire _r_sectored_repl_addr_T_5 = r_sectored_repl_addr_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12]
wire _r_sectored_repl_addr_T_6 = r_sectored_repl_addr_left_subtree_older_2 ? _r_sectored_repl_addr_T_4 : _r_sectored_repl_addr_T_5; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_sectored_repl_addr_T_7 = {r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] _r_sectored_repl_addr_T_8 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_7; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [2:0] _r_sectored_repl_addr_T_9 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire _r_sectored_repl_addr_valids_T_1 = _r_sectored_repl_addr_valids_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_2 = _r_sectored_repl_addr_valids_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_4 = _r_sectored_repl_addr_valids_T_3 | sectored_entries_0_1_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_5 = _r_sectored_repl_addr_valids_T_4 | sectored_entries_0_1_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_7 = _r_sectored_repl_addr_valids_T_6 | sectored_entries_0_2_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_8 = _r_sectored_repl_addr_valids_T_7 | sectored_entries_0_2_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_10 = _r_sectored_repl_addr_valids_T_9 | sectored_entries_0_3_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_11 = _r_sectored_repl_addr_valids_T_10 | sectored_entries_0_3_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_13 = _r_sectored_repl_addr_valids_T_12 | sectored_entries_0_4_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_14 = _r_sectored_repl_addr_valids_T_13 | sectored_entries_0_4_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_16 = _r_sectored_repl_addr_valids_T_15 | sectored_entries_0_5_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_17 = _r_sectored_repl_addr_valids_T_16 | sectored_entries_0_5_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_19 = _r_sectored_repl_addr_valids_T_18 | sectored_entries_0_6_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_20 = _r_sectored_repl_addr_valids_T_19 | sectored_entries_0_6_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_22 = _r_sectored_repl_addr_valids_T_21 | sectored_entries_0_7_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_23 = _r_sectored_repl_addr_valids_T_22 | sectored_entries_0_7_valid_3; // @[package.scala:81:59]
wire [1:0] r_sectored_repl_addr_valids_lo_lo = {_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2}; // @[package.scala:45:27, :81:59]
wire [1:0] r_sectored_repl_addr_valids_lo_hi = {_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8}; // @[package.scala:45:27, :81:59]
wire [3:0] r_sectored_repl_addr_valids_lo = {r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo}; // @[package.scala:45:27]
wire [1:0] r_sectored_repl_addr_valids_hi_lo = {_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14}; // @[package.scala:45:27, :81:59]
wire [1:0] r_sectored_repl_addr_valids_hi_hi = {_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20}; // @[package.scala:45:27, :81:59]
wire [3:0] r_sectored_repl_addr_valids_hi = {r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo}; // @[package.scala:45:27]
wire [7:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27]
wire _r_sectored_repl_addr_T_10 = &r_sectored_repl_addr_valids; // @[package.scala:45:27]
wire [7:0] _r_sectored_repl_addr_T_11 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27]
wire _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_11[0]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_11[1]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_14 = _r_sectored_repl_addr_T_11[2]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_15 = _r_sectored_repl_addr_T_11[3]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_16 = _r_sectored_repl_addr_T_11[4]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_17 = _r_sectored_repl_addr_T_11[5]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_18 = _r_sectored_repl_addr_T_11[6]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_19 = _r_sectored_repl_addr_T_11[7]; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_20 = {2'h3, ~_r_sectored_repl_addr_T_18}; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_21 = _r_sectored_repl_addr_T_17 ? 3'h5 : _r_sectored_repl_addr_T_20; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_22 = _r_sectored_repl_addr_T_16 ? 3'h4 : _r_sectored_repl_addr_T_21; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_23 = _r_sectored_repl_addr_T_15 ? 3'h3 : _r_sectored_repl_addr_T_22; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_24 = _r_sectored_repl_addr_T_14 ? 3'h2 : _r_sectored_repl_addr_T_23; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_25 = _r_sectored_repl_addr_T_13 ? 3'h1 : _r_sectored_repl_addr_T_24; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_26 = _r_sectored_repl_addr_T_12 ? 3'h0 : _r_sectored_repl_addr_T_25; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_27 = _r_sectored_repl_addr_T_10 ? _r_sectored_repl_addr_T_9 : _r_sectored_repl_addr_T_26; // @[Mux.scala:50:70]
wire _r_sectored_hit_valid_T = sector_hits_0 | sector_hits_1; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T | sector_hits_2; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 | sector_hits_3; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_3 = _r_sectored_hit_valid_T_2 | sector_hits_4; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_4 = _r_sectored_hit_valid_T_3 | sector_hits_5; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_5 = _r_sectored_hit_valid_T_4 | sector_hits_6; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_6 = _r_sectored_hit_valid_T_5 | sector_hits_7; // @[package.scala:81:59]
wire [3:0] r_sectored_hit_bits_lo = {r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo}; // @[OneHot.scala:21:45]
wire [3:0] r_sectored_hit_bits_hi = {r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo}; // @[OneHot.scala:21:45]
wire [7:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45]
wire [3:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[7:4]; // @[OneHot.scala:21:45, :30:18]
wire [3:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[3:0]; // @[OneHot.scala:21:45, :31:18]
wire _r_sectored_hit_bits_T_1 = |r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 | r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] r_sectored_hit_bits_hi_2 = _r_sectored_hit_bits_T_2[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] r_sectored_hit_bits_lo_2 = _r_sectored_hit_bits_T_2[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _r_sectored_hit_bits_T_3 = |r_sectored_hit_bits_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _r_sectored_hit_bits_T_4 = r_sectored_hit_bits_hi_2 | r_sectored_hit_bits_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _r_sectored_hit_bits_T_5 = _r_sectored_hit_bits_T_4[1]; // @[OneHot.scala:32:28]
wire [1:0] _r_sectored_hit_bits_T_6 = {_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _r_sectored_hit_bits_T_7 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6}; // @[OneHot.scala:32:{10,14}]
wire _r_superpage_hit_valid_T = superpage_hits_0 | superpage_hits_1; // @[package.scala:81:59]
wire _r_superpage_hit_valid_T_1 = _r_superpage_hit_valid_T | superpage_hits_2; // @[package.scala:81:59]
wire _r_superpage_hit_valid_T_2 = _r_superpage_hit_valid_T_1 | superpage_hits_3; // @[package.scala:81:59]
wire [3:0] _r_superpage_hit_bits_T = {r_superpage_hit_bits_hi, r_superpage_hit_bits_lo}; // @[OneHot.scala:21:45]
wire [1:0] r_superpage_hit_bits_hi_1 = _r_superpage_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18]
wire [1:0] r_superpage_hit_bits_lo_1 = _r_superpage_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18]
wire _r_superpage_hit_bits_T_1 = |r_superpage_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _r_superpage_hit_bits_T_2 = r_superpage_hit_bits_hi_1 | r_superpage_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _r_superpage_hit_bits_T_3 = _r_superpage_hit_bits_T_2[1]; // @[OneHot.scala:32:28]
wire [1:0] _r_superpage_hit_bits_T_4 = {_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}]
wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45] |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_113 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_return : UInt<10>, vc_free : UInt<10>}}
wire _in_flight_WIRE : UInt<1>[10]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
connect _in_flight_WIRE[5], UInt<1>(0h0)
connect _in_flight_WIRE[6], UInt<1>(0h0)
connect _in_flight_WIRE[7], UInt<1>(0h0)
connect _in_flight_WIRE[8], UInt<1>(0h0)
connect _in_flight_WIRE[9], UInt<1>(0h0)
regreset in_flight : UInt<1>[10], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = or(_T_5, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_11 = or(_T_10, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_16 = or(_T_15, UInt<1>(0h0))
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_21 = or(_T_20, UInt<1>(0h0))
node _T_22 = asUInt(reset)
node _T_23 = eq(_T_22, UInt<1>(0h0))
when _T_23 :
node _T_24 = eq(_T_21, UInt<1>(0h0))
when _T_24 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_21, UInt<1>(0h1), "") : assert_4
node _T_25 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_26 = or(_T_25, UInt<1>(0h0))
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
node _T_29 = eq(_T_26, UInt<1>(0h0))
when _T_29 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_26, UInt<1>(0h1), "") : assert_5
node _T_30 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5))
node _T_31 = or(_T_30, UInt<1>(0h0))
node _T_32 = asUInt(reset)
node _T_33 = eq(_T_32, UInt<1>(0h0))
when _T_33 :
node _T_34 = eq(_T_31, UInt<1>(0h0))
when _T_34 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6
assert(clock, _T_31, UInt<1>(0h1), "") : assert_6
node _T_35 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6))
node _T_36 = or(_T_35, UInt<1>(0h0))
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7
assert(clock, _T_36, UInt<1>(0h1), "") : assert_7
node _T_40 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7))
node _T_41 = or(_T_40, UInt<1>(0h0))
node _T_42 = asUInt(reset)
node _T_43 = eq(_T_42, UInt<1>(0h0))
when _T_43 :
node _T_44 = eq(_T_41, UInt<1>(0h0))
when _T_44 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8
assert(clock, _T_41, UInt<1>(0h1), "") : assert_8
node _T_45 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8))
node _T_46 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_47 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7))
node _T_48 = and(_T_46, _T_47)
node _T_49 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_50 = and(_T_48, _T_49)
node _T_51 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_52 = and(_T_50, _T_51)
node _T_53 = or(_T_45, _T_52)
node _T_54 = asUInt(reset)
node _T_55 = eq(_T_54, UInt<1>(0h0))
when _T_55 :
node _T_56 = eq(_T_53, UInt<1>(0h0))
when _T_56 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_9
assert(clock, _T_53, UInt<1>(0h1), "") : assert_9
node _T_57 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h9))
node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_59 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7))
node _T_60 = and(_T_58, _T_59)
node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_62 = and(_T_60, _T_61)
node _T_63 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_64 = and(_T_62, _T_63)
node _T_65 = or(_T_57, _T_64)
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_10
assert(clock, _T_65, UInt<1>(0h1), "") : assert_10 | module NoCMonitor_113( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26]
reg in_flight_8; // @[Monitor.scala:16:26]
reg in_flight_9; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 4'h0; // @[Monitor.scala:21:46]
wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 4'h1; // @[Monitor.scala:21:46]
wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 4'h2; // @[Monitor.scala:21:46]
wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 4'h3; // @[Monitor.scala:21:46]
wire _GEN_3 = io_in_flit_0_bits_virt_channel_id == 4'h4; // @[Monitor.scala:21:46]
wire _GEN_4 = io_in_flit_0_bits_virt_channel_id == 4'h5; // @[Monitor.scala:21:46]
wire _GEN_5 = io_in_flit_0_bits_virt_channel_id == 4'h6; // @[Monitor.scala:21:46]
wire _GEN_6 = io_in_flit_0_bits_virt_channel_id == 4'h7; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_43 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_43(); // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = 9'h2B; // @[rawFloatFromRecFN.scala:51:21]
wire [9:0] rawIn_sExp = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [9:0] _rawIn_out_sExp_T = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [1:0] _rawIn_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _rawIn_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [22:0] _rawIn_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49]
wire [24:0] rawIn_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _rawIn_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire rawIn_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53, :55:23, :56:{33,41}, :57:{33,41}, :61:35]
wire rawIn_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:53:53, :55:23, :56:{33,41}, :57:{33,41}, :61:35]
wire rawIn_isInf = 1'h0; // @[rawFloatFromRecFN.scala:53:53, :55:23, :56:{33,41}, :57:{33,41}, :61:35]
wire _rawIn_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:53:53, :55:23, :56:{33,41}, :57:{33,41}, :61:35]
wire _rawIn_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:53:53, :55:23, :56:{33,41}, :57:{33,41}, :61:35]
wire _rawIn_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:53:53, :55:23, :56:{33,41}, :57:{33,41}, :61:35]
wire _rawIn_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:53:53, :55:23, :56:{33,41}, :57:{33,41}, :61:35]
wire _rawIn_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:53:53, :55:23, :56:{33,41}, :57:{33,41}, :61:35]
wire _io_exceptionFlags_T = 1'h0; // @[rawFloatFromRecFN.scala:53:53, :55:23, :56:{33,41}, :57:{33,41}, :61:35]
wire _io_exceptionFlags_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:53:53, :55:23, :56:{33,41}, :57:{33,41}, :61:35]
wire [4:0] io_exceptionFlags = 5'h0; // @[RecFNToRecFN.scala:44:5, :48:16, :65:54]
wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RecFNToRecFN.scala:44:5, :48:16, :65:54]
wire io_detectTininess = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25]
wire rawIn_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25]
wire rawIn_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25]
wire rawIn_sign = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25]
wire _rawIn_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25]
wire _rawIn_out_sign_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25]
wire _io_exceptionFlags_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25]
wire [2:0] io_roundingMode = 3'h0; // @[rawFloatFromRecFN.scala:52:28]
wire [2:0] _rawIn_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28]
wire [32:0] io_in = 33'h115800000; // @[RecFNToRecFN.scala:44:5, :48:16, :64:35]
wire [32:0] io_out = 33'h115800000; // @[RecFNToRecFN.scala:44:5, :48:16, :64:35]
wire [32:0] _io_out_T = 33'h115800000; // @[RecFNToRecFN.scala:44:5, :48:16, :64:35]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLNoC_2_router_6ClockSinkDomain :
output auto : { routers_debug_out : { va_stall : UInt[4], sa_stall : UInt[4]}, routers_egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, routers_egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip routers_ingress_nodes_in_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip routers_ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip routers_ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, routers_source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip routers_dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst routers of Router_53
connect routers.clock, childClock
connect routers.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect clockNodeIn, auto.clock_in
connect routers.auto.dest_nodes_in, auto.routers_dest_nodes_in
connect routers.auto.source_nodes_out.vc_free, auto.routers_source_nodes_out.vc_free
connect routers.auto.source_nodes_out.credit_return, auto.routers_source_nodes_out.credit_return
connect auto.routers_source_nodes_out.flit, routers.auto.source_nodes_out.flit
connect routers.auto.ingress_nodes_in_0, auto.routers_ingress_nodes_in_0
connect routers.auto.ingress_nodes_in_1, auto.routers_ingress_nodes_in_1
connect routers.auto.ingress_nodes_in_2, auto.routers_ingress_nodes_in_2
connect auto.routers_egress_nodes_out_0.flit.bits, routers.auto.egress_nodes_out_0.flit.bits
connect auto.routers_egress_nodes_out_0.flit.valid, routers.auto.egress_nodes_out_0.flit.valid
connect routers.auto.egress_nodes_out_0.flit.ready, auto.routers_egress_nodes_out_0.flit.ready
connect auto.routers_egress_nodes_out_1.flit.bits, routers.auto.egress_nodes_out_1.flit.bits
connect auto.routers_egress_nodes_out_1.flit.valid, routers.auto.egress_nodes_out_1.flit.valid
connect routers.auto.egress_nodes_out_1.flit.ready, auto.routers_egress_nodes_out_1.flit.ready
connect auto.routers_debug_out, routers.auto.debug_out
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module TLNoC_2_router_6ClockSinkDomain( // @[ClockDomain.scala:14:9]
output [3:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
Router_53 routers ( // @[NoC.scala:67:22]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0),
.auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1),
.auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0),
.auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1),
.auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready),
.auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid),
.auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head),
.auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail),
.auto_egress_nodes_out_1_flit_bits_payload (auto_routers_egress_nodes_out_1_flit_bits_payload),
.auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready),
.auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid),
.auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head),
.auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail),
.auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready),
.auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid),
.auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head),
.auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail),
.auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload),
.auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id),
.auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid),
.auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head),
.auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail),
.auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload),
.auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return),
.auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free),
.auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid),
.auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head),
.auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail),
.auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload),
.auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return),
.auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free)
); // @[NoC.scala:67:22]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ComposedBranchPredictorBank_3 :
input clock : Clock
input reset : Reset
output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}}
connect io.resp, io.resp_in[0]
connect io.f3_meta, UInt<1>(0h0)
node s0_idx = shr(io.f0_pc, 4)
reg s1_idx : UInt, clock
connect s1_idx, s0_idx
reg s2_idx : UInt, clock
connect s2_idx, s1_idx
reg s3_idx : UInt, clock
connect s3_idx, s2_idx
reg s1_valid : UInt<1>, clock
connect s1_valid, io.f0_valid
reg s2_valid : UInt<1>, clock
connect s2_valid, s1_valid
reg s3_valid : UInt<1>, clock
connect s3_valid, s2_valid
reg s1_mask : UInt, clock
connect s1_mask, io.f0_mask
reg s2_mask : UInt, clock
connect s2_mask, s1_mask
reg s3_mask : UInt, clock
connect s3_mask, s2_mask
reg s1_pc : UInt, clock
connect s1_pc, io.f0_pc
node s0_update_idx = shr(io.update.bits.pc, 4)
reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock
connect s1_update.bits.meta, io.update.bits.meta
connect s1_update.bits.target, io.update.bits.target
connect s1_update.bits.lhist, io.update.bits.lhist
connect s1_update.bits.ghist, io.update.bits.ghist
connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken
connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect s1_update.bits.br_mask, io.update.bits.br_mask
connect s1_update.bits.pc, io.update.bits.pc
connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update
connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect s1_update.valid, io.update.valid
reg s1_update_idx : UInt, clock
connect s1_update_idx, s0_update_idx
reg s1_update_valid : UInt<1>, clock
connect s1_update_valid, io.update.valid
inst loop of LoopBranchPredictorBank_3
connect loop.clock, clock
connect loop.reset, reset
inst tage of TageBranchPredictorBank_3
connect tage.clock, clock
connect tage.reset, reset
inst btb of BTBBranchPredictorBank_3
connect btb.clock, clock
connect btb.reset, reset
inst bim of BIMBranchPredictorBank_3
connect bim.clock, clock
connect bim.reset, reset
inst ubtb of FAMicroBTBBranchPredictorBank_3
connect ubtb.clock, clock
connect ubtb.reset, reset
invalidate loop.io.update.bits.meta
invalidate loop.io.update.bits.target
invalidate loop.io.update.bits.lhist
invalidate loop.io.update.bits.ghist
invalidate loop.io.update.bits.cfi_is_jalr
invalidate loop.io.update.bits.cfi_is_jal
invalidate loop.io.update.bits.cfi_is_br
invalidate loop.io.update.bits.cfi_mispredicted
invalidate loop.io.update.bits.cfi_taken
invalidate loop.io.update.bits.cfi_idx.bits
invalidate loop.io.update.bits.cfi_idx.valid
invalidate loop.io.update.bits.br_mask
invalidate loop.io.update.bits.pc
invalidate loop.io.update.bits.btb_mispredicts
invalidate loop.io.update.bits.is_repair_update
invalidate loop.io.update.bits.is_mispredict_update
invalidate loop.io.update.valid
invalidate loop.io.f3_fire
invalidate loop.io.f3_meta
invalidate loop.io.resp.f3[0].predicted_pc.bits
invalidate loop.io.resp.f3[0].predicted_pc.valid
invalidate loop.io.resp.f3[0].is_jal
invalidate loop.io.resp.f3[0].is_br
invalidate loop.io.resp.f3[0].taken
invalidate loop.io.resp.f3[1].predicted_pc.bits
invalidate loop.io.resp.f3[1].predicted_pc.valid
invalidate loop.io.resp.f3[1].is_jal
invalidate loop.io.resp.f3[1].is_br
invalidate loop.io.resp.f3[1].taken
invalidate loop.io.resp.f3[2].predicted_pc.bits
invalidate loop.io.resp.f3[2].predicted_pc.valid
invalidate loop.io.resp.f3[2].is_jal
invalidate loop.io.resp.f3[2].is_br
invalidate loop.io.resp.f3[2].taken
invalidate loop.io.resp.f3[3].predicted_pc.bits
invalidate loop.io.resp.f3[3].predicted_pc.valid
invalidate loop.io.resp.f3[3].is_jal
invalidate loop.io.resp.f3[3].is_br
invalidate loop.io.resp.f3[3].taken
invalidate loop.io.resp.f2[0].predicted_pc.bits
invalidate loop.io.resp.f2[0].predicted_pc.valid
invalidate loop.io.resp.f2[0].is_jal
invalidate loop.io.resp.f2[0].is_br
invalidate loop.io.resp.f2[0].taken
invalidate loop.io.resp.f2[1].predicted_pc.bits
invalidate loop.io.resp.f2[1].predicted_pc.valid
invalidate loop.io.resp.f2[1].is_jal
invalidate loop.io.resp.f2[1].is_br
invalidate loop.io.resp.f2[1].taken
invalidate loop.io.resp.f2[2].predicted_pc.bits
invalidate loop.io.resp.f2[2].predicted_pc.valid
invalidate loop.io.resp.f2[2].is_jal
invalidate loop.io.resp.f2[2].is_br
invalidate loop.io.resp.f2[2].taken
invalidate loop.io.resp.f2[3].predicted_pc.bits
invalidate loop.io.resp.f2[3].predicted_pc.valid
invalidate loop.io.resp.f2[3].is_jal
invalidate loop.io.resp.f2[3].is_br
invalidate loop.io.resp.f2[3].taken
invalidate loop.io.resp.f1[0].predicted_pc.bits
invalidate loop.io.resp.f1[0].predicted_pc.valid
invalidate loop.io.resp.f1[0].is_jal
invalidate loop.io.resp.f1[0].is_br
invalidate loop.io.resp.f1[0].taken
invalidate loop.io.resp.f1[1].predicted_pc.bits
invalidate loop.io.resp.f1[1].predicted_pc.valid
invalidate loop.io.resp.f1[1].is_jal
invalidate loop.io.resp.f1[1].is_br
invalidate loop.io.resp.f1[1].taken
invalidate loop.io.resp.f1[2].predicted_pc.bits
invalidate loop.io.resp.f1[2].predicted_pc.valid
invalidate loop.io.resp.f1[2].is_jal
invalidate loop.io.resp.f1[2].is_br
invalidate loop.io.resp.f1[2].taken
invalidate loop.io.resp.f1[3].predicted_pc.bits
invalidate loop.io.resp.f1[3].predicted_pc.valid
invalidate loop.io.resp.f1[3].is_jal
invalidate loop.io.resp.f1[3].is_br
invalidate loop.io.resp.f1[3].taken
invalidate loop.io.resp_in[0].f3[0].predicted_pc.bits
invalidate loop.io.resp_in[0].f3[0].predicted_pc.valid
invalidate loop.io.resp_in[0].f3[0].is_jal
invalidate loop.io.resp_in[0].f3[0].is_br
invalidate loop.io.resp_in[0].f3[0].taken
invalidate loop.io.resp_in[0].f3[1].predicted_pc.bits
invalidate loop.io.resp_in[0].f3[1].predicted_pc.valid
invalidate loop.io.resp_in[0].f3[1].is_jal
invalidate loop.io.resp_in[0].f3[1].is_br
invalidate loop.io.resp_in[0].f3[1].taken
invalidate loop.io.resp_in[0].f3[2].predicted_pc.bits
invalidate loop.io.resp_in[0].f3[2].predicted_pc.valid
invalidate loop.io.resp_in[0].f3[2].is_jal
invalidate loop.io.resp_in[0].f3[2].is_br
invalidate loop.io.resp_in[0].f3[2].taken
invalidate loop.io.resp_in[0].f3[3].predicted_pc.bits
invalidate loop.io.resp_in[0].f3[3].predicted_pc.valid
invalidate loop.io.resp_in[0].f3[3].is_jal
invalidate loop.io.resp_in[0].f3[3].is_br
invalidate loop.io.resp_in[0].f3[3].taken
invalidate loop.io.resp_in[0].f2[0].predicted_pc.bits
invalidate loop.io.resp_in[0].f2[0].predicted_pc.valid
invalidate loop.io.resp_in[0].f2[0].is_jal
invalidate loop.io.resp_in[0].f2[0].is_br
invalidate loop.io.resp_in[0].f2[0].taken
invalidate loop.io.resp_in[0].f2[1].predicted_pc.bits
invalidate loop.io.resp_in[0].f2[1].predicted_pc.valid
invalidate loop.io.resp_in[0].f2[1].is_jal
invalidate loop.io.resp_in[0].f2[1].is_br
invalidate loop.io.resp_in[0].f2[1].taken
invalidate loop.io.resp_in[0].f2[2].predicted_pc.bits
invalidate loop.io.resp_in[0].f2[2].predicted_pc.valid
invalidate loop.io.resp_in[0].f2[2].is_jal
invalidate loop.io.resp_in[0].f2[2].is_br
invalidate loop.io.resp_in[0].f2[2].taken
invalidate loop.io.resp_in[0].f2[3].predicted_pc.bits
invalidate loop.io.resp_in[0].f2[3].predicted_pc.valid
invalidate loop.io.resp_in[0].f2[3].is_jal
invalidate loop.io.resp_in[0].f2[3].is_br
invalidate loop.io.resp_in[0].f2[3].taken
invalidate loop.io.resp_in[0].f1[0].predicted_pc.bits
invalidate loop.io.resp_in[0].f1[0].predicted_pc.valid
invalidate loop.io.resp_in[0].f1[0].is_jal
invalidate loop.io.resp_in[0].f1[0].is_br
invalidate loop.io.resp_in[0].f1[0].taken
invalidate loop.io.resp_in[0].f1[1].predicted_pc.bits
invalidate loop.io.resp_in[0].f1[1].predicted_pc.valid
invalidate loop.io.resp_in[0].f1[1].is_jal
invalidate loop.io.resp_in[0].f1[1].is_br
invalidate loop.io.resp_in[0].f1[1].taken
invalidate loop.io.resp_in[0].f1[2].predicted_pc.bits
invalidate loop.io.resp_in[0].f1[2].predicted_pc.valid
invalidate loop.io.resp_in[0].f1[2].is_jal
invalidate loop.io.resp_in[0].f1[2].is_br
invalidate loop.io.resp_in[0].f1[2].taken
invalidate loop.io.resp_in[0].f1[3].predicted_pc.bits
invalidate loop.io.resp_in[0].f1[3].predicted_pc.valid
invalidate loop.io.resp_in[0].f1[3].is_jal
invalidate loop.io.resp_in[0].f1[3].is_br
invalidate loop.io.resp_in[0].f1[3].taken
invalidate loop.io.f1_lhist
invalidate loop.io.f1_ghist
invalidate loop.io.f0_mask
invalidate loop.io.f0_pc
invalidate loop.io.f0_valid
invalidate tage.io.update.bits.meta
invalidate tage.io.update.bits.target
invalidate tage.io.update.bits.lhist
invalidate tage.io.update.bits.ghist
invalidate tage.io.update.bits.cfi_is_jalr
invalidate tage.io.update.bits.cfi_is_jal
invalidate tage.io.update.bits.cfi_is_br
invalidate tage.io.update.bits.cfi_mispredicted
invalidate tage.io.update.bits.cfi_taken
invalidate tage.io.update.bits.cfi_idx.bits
invalidate tage.io.update.bits.cfi_idx.valid
invalidate tage.io.update.bits.br_mask
invalidate tage.io.update.bits.pc
invalidate tage.io.update.bits.btb_mispredicts
invalidate tage.io.update.bits.is_repair_update
invalidate tage.io.update.bits.is_mispredict_update
invalidate tage.io.update.valid
invalidate tage.io.f3_fire
invalidate tage.io.f3_meta
invalidate tage.io.resp.f3[0].predicted_pc.bits
invalidate tage.io.resp.f3[0].predicted_pc.valid
invalidate tage.io.resp.f3[0].is_jal
invalidate tage.io.resp.f3[0].is_br
invalidate tage.io.resp.f3[0].taken
invalidate tage.io.resp.f3[1].predicted_pc.bits
invalidate tage.io.resp.f3[1].predicted_pc.valid
invalidate tage.io.resp.f3[1].is_jal
invalidate tage.io.resp.f3[1].is_br
invalidate tage.io.resp.f3[1].taken
invalidate tage.io.resp.f3[2].predicted_pc.bits
invalidate tage.io.resp.f3[2].predicted_pc.valid
invalidate tage.io.resp.f3[2].is_jal
invalidate tage.io.resp.f3[2].is_br
invalidate tage.io.resp.f3[2].taken
invalidate tage.io.resp.f3[3].predicted_pc.bits
invalidate tage.io.resp.f3[3].predicted_pc.valid
invalidate tage.io.resp.f3[3].is_jal
invalidate tage.io.resp.f3[3].is_br
invalidate tage.io.resp.f3[3].taken
invalidate tage.io.resp.f2[0].predicted_pc.bits
invalidate tage.io.resp.f2[0].predicted_pc.valid
invalidate tage.io.resp.f2[0].is_jal
invalidate tage.io.resp.f2[0].is_br
invalidate tage.io.resp.f2[0].taken
invalidate tage.io.resp.f2[1].predicted_pc.bits
invalidate tage.io.resp.f2[1].predicted_pc.valid
invalidate tage.io.resp.f2[1].is_jal
invalidate tage.io.resp.f2[1].is_br
invalidate tage.io.resp.f2[1].taken
invalidate tage.io.resp.f2[2].predicted_pc.bits
invalidate tage.io.resp.f2[2].predicted_pc.valid
invalidate tage.io.resp.f2[2].is_jal
invalidate tage.io.resp.f2[2].is_br
invalidate tage.io.resp.f2[2].taken
invalidate tage.io.resp.f2[3].predicted_pc.bits
invalidate tage.io.resp.f2[3].predicted_pc.valid
invalidate tage.io.resp.f2[3].is_jal
invalidate tage.io.resp.f2[3].is_br
invalidate tage.io.resp.f2[3].taken
invalidate tage.io.resp.f1[0].predicted_pc.bits
invalidate tage.io.resp.f1[0].predicted_pc.valid
invalidate tage.io.resp.f1[0].is_jal
invalidate tage.io.resp.f1[0].is_br
invalidate tage.io.resp.f1[0].taken
invalidate tage.io.resp.f1[1].predicted_pc.bits
invalidate tage.io.resp.f1[1].predicted_pc.valid
invalidate tage.io.resp.f1[1].is_jal
invalidate tage.io.resp.f1[1].is_br
invalidate tage.io.resp.f1[1].taken
invalidate tage.io.resp.f1[2].predicted_pc.bits
invalidate tage.io.resp.f1[2].predicted_pc.valid
invalidate tage.io.resp.f1[2].is_jal
invalidate tage.io.resp.f1[2].is_br
invalidate tage.io.resp.f1[2].taken
invalidate tage.io.resp.f1[3].predicted_pc.bits
invalidate tage.io.resp.f1[3].predicted_pc.valid
invalidate tage.io.resp.f1[3].is_jal
invalidate tage.io.resp.f1[3].is_br
invalidate tage.io.resp.f1[3].taken
invalidate tage.io.resp_in[0].f3[0].predicted_pc.bits
invalidate tage.io.resp_in[0].f3[0].predicted_pc.valid
invalidate tage.io.resp_in[0].f3[0].is_jal
invalidate tage.io.resp_in[0].f3[0].is_br
invalidate tage.io.resp_in[0].f3[0].taken
invalidate tage.io.resp_in[0].f3[1].predicted_pc.bits
invalidate tage.io.resp_in[0].f3[1].predicted_pc.valid
invalidate tage.io.resp_in[0].f3[1].is_jal
invalidate tage.io.resp_in[0].f3[1].is_br
invalidate tage.io.resp_in[0].f3[1].taken
invalidate tage.io.resp_in[0].f3[2].predicted_pc.bits
invalidate tage.io.resp_in[0].f3[2].predicted_pc.valid
invalidate tage.io.resp_in[0].f3[2].is_jal
invalidate tage.io.resp_in[0].f3[2].is_br
invalidate tage.io.resp_in[0].f3[2].taken
invalidate tage.io.resp_in[0].f3[3].predicted_pc.bits
invalidate tage.io.resp_in[0].f3[3].predicted_pc.valid
invalidate tage.io.resp_in[0].f3[3].is_jal
invalidate tage.io.resp_in[0].f3[3].is_br
invalidate tage.io.resp_in[0].f3[3].taken
invalidate tage.io.resp_in[0].f2[0].predicted_pc.bits
invalidate tage.io.resp_in[0].f2[0].predicted_pc.valid
invalidate tage.io.resp_in[0].f2[0].is_jal
invalidate tage.io.resp_in[0].f2[0].is_br
invalidate tage.io.resp_in[0].f2[0].taken
invalidate tage.io.resp_in[0].f2[1].predicted_pc.bits
invalidate tage.io.resp_in[0].f2[1].predicted_pc.valid
invalidate tage.io.resp_in[0].f2[1].is_jal
invalidate tage.io.resp_in[0].f2[1].is_br
invalidate tage.io.resp_in[0].f2[1].taken
invalidate tage.io.resp_in[0].f2[2].predicted_pc.bits
invalidate tage.io.resp_in[0].f2[2].predicted_pc.valid
invalidate tage.io.resp_in[0].f2[2].is_jal
invalidate tage.io.resp_in[0].f2[2].is_br
invalidate tage.io.resp_in[0].f2[2].taken
invalidate tage.io.resp_in[0].f2[3].predicted_pc.bits
invalidate tage.io.resp_in[0].f2[3].predicted_pc.valid
invalidate tage.io.resp_in[0].f2[3].is_jal
invalidate tage.io.resp_in[0].f2[3].is_br
invalidate tage.io.resp_in[0].f2[3].taken
invalidate tage.io.resp_in[0].f1[0].predicted_pc.bits
invalidate tage.io.resp_in[0].f1[0].predicted_pc.valid
invalidate tage.io.resp_in[0].f1[0].is_jal
invalidate tage.io.resp_in[0].f1[0].is_br
invalidate tage.io.resp_in[0].f1[0].taken
invalidate tage.io.resp_in[0].f1[1].predicted_pc.bits
invalidate tage.io.resp_in[0].f1[1].predicted_pc.valid
invalidate tage.io.resp_in[0].f1[1].is_jal
invalidate tage.io.resp_in[0].f1[1].is_br
invalidate tage.io.resp_in[0].f1[1].taken
invalidate tage.io.resp_in[0].f1[2].predicted_pc.bits
invalidate tage.io.resp_in[0].f1[2].predicted_pc.valid
invalidate tage.io.resp_in[0].f1[2].is_jal
invalidate tage.io.resp_in[0].f1[2].is_br
invalidate tage.io.resp_in[0].f1[2].taken
invalidate tage.io.resp_in[0].f1[3].predicted_pc.bits
invalidate tage.io.resp_in[0].f1[3].predicted_pc.valid
invalidate tage.io.resp_in[0].f1[3].is_jal
invalidate tage.io.resp_in[0].f1[3].is_br
invalidate tage.io.resp_in[0].f1[3].taken
invalidate tage.io.f1_lhist
invalidate tage.io.f1_ghist
invalidate tage.io.f0_mask
invalidate tage.io.f0_pc
invalidate tage.io.f0_valid
invalidate btb.io.update.bits.meta
invalidate btb.io.update.bits.target
invalidate btb.io.update.bits.lhist
invalidate btb.io.update.bits.ghist
invalidate btb.io.update.bits.cfi_is_jalr
invalidate btb.io.update.bits.cfi_is_jal
invalidate btb.io.update.bits.cfi_is_br
invalidate btb.io.update.bits.cfi_mispredicted
invalidate btb.io.update.bits.cfi_taken
invalidate btb.io.update.bits.cfi_idx.bits
invalidate btb.io.update.bits.cfi_idx.valid
invalidate btb.io.update.bits.br_mask
invalidate btb.io.update.bits.pc
invalidate btb.io.update.bits.btb_mispredicts
invalidate btb.io.update.bits.is_repair_update
invalidate btb.io.update.bits.is_mispredict_update
invalidate btb.io.update.valid
invalidate btb.io.f3_fire
invalidate btb.io.f3_meta
invalidate btb.io.resp.f3[0].predicted_pc.bits
invalidate btb.io.resp.f3[0].predicted_pc.valid
invalidate btb.io.resp.f3[0].is_jal
invalidate btb.io.resp.f3[0].is_br
invalidate btb.io.resp.f3[0].taken
invalidate btb.io.resp.f3[1].predicted_pc.bits
invalidate btb.io.resp.f3[1].predicted_pc.valid
invalidate btb.io.resp.f3[1].is_jal
invalidate btb.io.resp.f3[1].is_br
invalidate btb.io.resp.f3[1].taken
invalidate btb.io.resp.f3[2].predicted_pc.bits
invalidate btb.io.resp.f3[2].predicted_pc.valid
invalidate btb.io.resp.f3[2].is_jal
invalidate btb.io.resp.f3[2].is_br
invalidate btb.io.resp.f3[2].taken
invalidate btb.io.resp.f3[3].predicted_pc.bits
invalidate btb.io.resp.f3[3].predicted_pc.valid
invalidate btb.io.resp.f3[3].is_jal
invalidate btb.io.resp.f3[3].is_br
invalidate btb.io.resp.f3[3].taken
invalidate btb.io.resp.f2[0].predicted_pc.bits
invalidate btb.io.resp.f2[0].predicted_pc.valid
invalidate btb.io.resp.f2[0].is_jal
invalidate btb.io.resp.f2[0].is_br
invalidate btb.io.resp.f2[0].taken
invalidate btb.io.resp.f2[1].predicted_pc.bits
invalidate btb.io.resp.f2[1].predicted_pc.valid
invalidate btb.io.resp.f2[1].is_jal
invalidate btb.io.resp.f2[1].is_br
invalidate btb.io.resp.f2[1].taken
invalidate btb.io.resp.f2[2].predicted_pc.bits
invalidate btb.io.resp.f2[2].predicted_pc.valid
invalidate btb.io.resp.f2[2].is_jal
invalidate btb.io.resp.f2[2].is_br
invalidate btb.io.resp.f2[2].taken
invalidate btb.io.resp.f2[3].predicted_pc.bits
invalidate btb.io.resp.f2[3].predicted_pc.valid
invalidate btb.io.resp.f2[3].is_jal
invalidate btb.io.resp.f2[3].is_br
invalidate btb.io.resp.f2[3].taken
invalidate btb.io.resp.f1[0].predicted_pc.bits
invalidate btb.io.resp.f1[0].predicted_pc.valid
invalidate btb.io.resp.f1[0].is_jal
invalidate btb.io.resp.f1[0].is_br
invalidate btb.io.resp.f1[0].taken
invalidate btb.io.resp.f1[1].predicted_pc.bits
invalidate btb.io.resp.f1[1].predicted_pc.valid
invalidate btb.io.resp.f1[1].is_jal
invalidate btb.io.resp.f1[1].is_br
invalidate btb.io.resp.f1[1].taken
invalidate btb.io.resp.f1[2].predicted_pc.bits
invalidate btb.io.resp.f1[2].predicted_pc.valid
invalidate btb.io.resp.f1[2].is_jal
invalidate btb.io.resp.f1[2].is_br
invalidate btb.io.resp.f1[2].taken
invalidate btb.io.resp.f1[3].predicted_pc.bits
invalidate btb.io.resp.f1[3].predicted_pc.valid
invalidate btb.io.resp.f1[3].is_jal
invalidate btb.io.resp.f1[3].is_br
invalidate btb.io.resp.f1[3].taken
invalidate btb.io.resp_in[0].f3[0].predicted_pc.bits
invalidate btb.io.resp_in[0].f3[0].predicted_pc.valid
invalidate btb.io.resp_in[0].f3[0].is_jal
invalidate btb.io.resp_in[0].f3[0].is_br
invalidate btb.io.resp_in[0].f3[0].taken
invalidate btb.io.resp_in[0].f3[1].predicted_pc.bits
invalidate btb.io.resp_in[0].f3[1].predicted_pc.valid
invalidate btb.io.resp_in[0].f3[1].is_jal
invalidate btb.io.resp_in[0].f3[1].is_br
invalidate btb.io.resp_in[0].f3[1].taken
invalidate btb.io.resp_in[0].f3[2].predicted_pc.bits
invalidate btb.io.resp_in[0].f3[2].predicted_pc.valid
invalidate btb.io.resp_in[0].f3[2].is_jal
invalidate btb.io.resp_in[0].f3[2].is_br
invalidate btb.io.resp_in[0].f3[2].taken
invalidate btb.io.resp_in[0].f3[3].predicted_pc.bits
invalidate btb.io.resp_in[0].f3[3].predicted_pc.valid
invalidate btb.io.resp_in[0].f3[3].is_jal
invalidate btb.io.resp_in[0].f3[3].is_br
invalidate btb.io.resp_in[0].f3[3].taken
invalidate btb.io.resp_in[0].f2[0].predicted_pc.bits
invalidate btb.io.resp_in[0].f2[0].predicted_pc.valid
invalidate btb.io.resp_in[0].f2[0].is_jal
invalidate btb.io.resp_in[0].f2[0].is_br
invalidate btb.io.resp_in[0].f2[0].taken
invalidate btb.io.resp_in[0].f2[1].predicted_pc.bits
invalidate btb.io.resp_in[0].f2[1].predicted_pc.valid
invalidate btb.io.resp_in[0].f2[1].is_jal
invalidate btb.io.resp_in[0].f2[1].is_br
invalidate btb.io.resp_in[0].f2[1].taken
invalidate btb.io.resp_in[0].f2[2].predicted_pc.bits
invalidate btb.io.resp_in[0].f2[2].predicted_pc.valid
invalidate btb.io.resp_in[0].f2[2].is_jal
invalidate btb.io.resp_in[0].f2[2].is_br
invalidate btb.io.resp_in[0].f2[2].taken
invalidate btb.io.resp_in[0].f2[3].predicted_pc.bits
invalidate btb.io.resp_in[0].f2[3].predicted_pc.valid
invalidate btb.io.resp_in[0].f2[3].is_jal
invalidate btb.io.resp_in[0].f2[3].is_br
invalidate btb.io.resp_in[0].f2[3].taken
invalidate btb.io.resp_in[0].f1[0].predicted_pc.bits
invalidate btb.io.resp_in[0].f1[0].predicted_pc.valid
invalidate btb.io.resp_in[0].f1[0].is_jal
invalidate btb.io.resp_in[0].f1[0].is_br
invalidate btb.io.resp_in[0].f1[0].taken
invalidate btb.io.resp_in[0].f1[1].predicted_pc.bits
invalidate btb.io.resp_in[0].f1[1].predicted_pc.valid
invalidate btb.io.resp_in[0].f1[1].is_jal
invalidate btb.io.resp_in[0].f1[1].is_br
invalidate btb.io.resp_in[0].f1[1].taken
invalidate btb.io.resp_in[0].f1[2].predicted_pc.bits
invalidate btb.io.resp_in[0].f1[2].predicted_pc.valid
invalidate btb.io.resp_in[0].f1[2].is_jal
invalidate btb.io.resp_in[0].f1[2].is_br
invalidate btb.io.resp_in[0].f1[2].taken
invalidate btb.io.resp_in[0].f1[3].predicted_pc.bits
invalidate btb.io.resp_in[0].f1[3].predicted_pc.valid
invalidate btb.io.resp_in[0].f1[3].is_jal
invalidate btb.io.resp_in[0].f1[3].is_br
invalidate btb.io.resp_in[0].f1[3].taken
invalidate btb.io.f1_lhist
invalidate btb.io.f1_ghist
invalidate btb.io.f0_mask
invalidate btb.io.f0_pc
invalidate btb.io.f0_valid
invalidate ubtb.io.update.bits.meta
invalidate ubtb.io.update.bits.target
invalidate ubtb.io.update.bits.lhist
invalidate ubtb.io.update.bits.ghist
invalidate ubtb.io.update.bits.cfi_is_jalr
invalidate ubtb.io.update.bits.cfi_is_jal
invalidate ubtb.io.update.bits.cfi_is_br
invalidate ubtb.io.update.bits.cfi_mispredicted
invalidate ubtb.io.update.bits.cfi_taken
invalidate ubtb.io.update.bits.cfi_idx.bits
invalidate ubtb.io.update.bits.cfi_idx.valid
invalidate ubtb.io.update.bits.br_mask
invalidate ubtb.io.update.bits.pc
invalidate ubtb.io.update.bits.btb_mispredicts
invalidate ubtb.io.update.bits.is_repair_update
invalidate ubtb.io.update.bits.is_mispredict_update
invalidate ubtb.io.update.valid
invalidate ubtb.io.f3_fire
invalidate ubtb.io.f3_meta
invalidate ubtb.io.resp.f3[0].predicted_pc.bits
invalidate ubtb.io.resp.f3[0].predicted_pc.valid
invalidate ubtb.io.resp.f3[0].is_jal
invalidate ubtb.io.resp.f3[0].is_br
invalidate ubtb.io.resp.f3[0].taken
invalidate ubtb.io.resp.f3[1].predicted_pc.bits
invalidate ubtb.io.resp.f3[1].predicted_pc.valid
invalidate ubtb.io.resp.f3[1].is_jal
invalidate ubtb.io.resp.f3[1].is_br
invalidate ubtb.io.resp.f3[1].taken
invalidate ubtb.io.resp.f3[2].predicted_pc.bits
invalidate ubtb.io.resp.f3[2].predicted_pc.valid
invalidate ubtb.io.resp.f3[2].is_jal
invalidate ubtb.io.resp.f3[2].is_br
invalidate ubtb.io.resp.f3[2].taken
invalidate ubtb.io.resp.f3[3].predicted_pc.bits
invalidate ubtb.io.resp.f3[3].predicted_pc.valid
invalidate ubtb.io.resp.f3[3].is_jal
invalidate ubtb.io.resp.f3[3].is_br
invalidate ubtb.io.resp.f3[3].taken
invalidate ubtb.io.resp.f2[0].predicted_pc.bits
invalidate ubtb.io.resp.f2[0].predicted_pc.valid
invalidate ubtb.io.resp.f2[0].is_jal
invalidate ubtb.io.resp.f2[0].is_br
invalidate ubtb.io.resp.f2[0].taken
invalidate ubtb.io.resp.f2[1].predicted_pc.bits
invalidate ubtb.io.resp.f2[1].predicted_pc.valid
invalidate ubtb.io.resp.f2[1].is_jal
invalidate ubtb.io.resp.f2[1].is_br
invalidate ubtb.io.resp.f2[1].taken
invalidate ubtb.io.resp.f2[2].predicted_pc.bits
invalidate ubtb.io.resp.f2[2].predicted_pc.valid
invalidate ubtb.io.resp.f2[2].is_jal
invalidate ubtb.io.resp.f2[2].is_br
invalidate ubtb.io.resp.f2[2].taken
invalidate ubtb.io.resp.f2[3].predicted_pc.bits
invalidate ubtb.io.resp.f2[3].predicted_pc.valid
invalidate ubtb.io.resp.f2[3].is_jal
invalidate ubtb.io.resp.f2[3].is_br
invalidate ubtb.io.resp.f2[3].taken
invalidate ubtb.io.resp.f1[0].predicted_pc.bits
invalidate ubtb.io.resp.f1[0].predicted_pc.valid
invalidate ubtb.io.resp.f1[0].is_jal
invalidate ubtb.io.resp.f1[0].is_br
invalidate ubtb.io.resp.f1[0].taken
invalidate ubtb.io.resp.f1[1].predicted_pc.bits
invalidate ubtb.io.resp.f1[1].predicted_pc.valid
invalidate ubtb.io.resp.f1[1].is_jal
invalidate ubtb.io.resp.f1[1].is_br
invalidate ubtb.io.resp.f1[1].taken
invalidate ubtb.io.resp.f1[2].predicted_pc.bits
invalidate ubtb.io.resp.f1[2].predicted_pc.valid
invalidate ubtb.io.resp.f1[2].is_jal
invalidate ubtb.io.resp.f1[2].is_br
invalidate ubtb.io.resp.f1[2].taken
invalidate ubtb.io.resp.f1[3].predicted_pc.bits
invalidate ubtb.io.resp.f1[3].predicted_pc.valid
invalidate ubtb.io.resp.f1[3].is_jal
invalidate ubtb.io.resp.f1[3].is_br
invalidate ubtb.io.resp.f1[3].taken
invalidate ubtb.io.resp_in[0].f3[0].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f3[0].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f3[0].is_jal
invalidate ubtb.io.resp_in[0].f3[0].is_br
invalidate ubtb.io.resp_in[0].f3[0].taken
invalidate ubtb.io.resp_in[0].f3[1].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f3[1].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f3[1].is_jal
invalidate ubtb.io.resp_in[0].f3[1].is_br
invalidate ubtb.io.resp_in[0].f3[1].taken
invalidate ubtb.io.resp_in[0].f3[2].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f3[2].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f3[2].is_jal
invalidate ubtb.io.resp_in[0].f3[2].is_br
invalidate ubtb.io.resp_in[0].f3[2].taken
invalidate ubtb.io.resp_in[0].f3[3].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f3[3].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f3[3].is_jal
invalidate ubtb.io.resp_in[0].f3[3].is_br
invalidate ubtb.io.resp_in[0].f3[3].taken
invalidate ubtb.io.resp_in[0].f2[0].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f2[0].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f2[0].is_jal
invalidate ubtb.io.resp_in[0].f2[0].is_br
invalidate ubtb.io.resp_in[0].f2[0].taken
invalidate ubtb.io.resp_in[0].f2[1].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f2[1].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f2[1].is_jal
invalidate ubtb.io.resp_in[0].f2[1].is_br
invalidate ubtb.io.resp_in[0].f2[1].taken
invalidate ubtb.io.resp_in[0].f2[2].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f2[2].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f2[2].is_jal
invalidate ubtb.io.resp_in[0].f2[2].is_br
invalidate ubtb.io.resp_in[0].f2[2].taken
invalidate ubtb.io.resp_in[0].f2[3].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f2[3].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f2[3].is_jal
invalidate ubtb.io.resp_in[0].f2[3].is_br
invalidate ubtb.io.resp_in[0].f2[3].taken
invalidate ubtb.io.resp_in[0].f1[0].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f1[0].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f1[0].is_jal
invalidate ubtb.io.resp_in[0].f1[0].is_br
invalidate ubtb.io.resp_in[0].f1[0].taken
invalidate ubtb.io.resp_in[0].f1[1].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f1[1].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f1[1].is_jal
invalidate ubtb.io.resp_in[0].f1[1].is_br
invalidate ubtb.io.resp_in[0].f1[1].taken
invalidate ubtb.io.resp_in[0].f1[2].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f1[2].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f1[2].is_jal
invalidate ubtb.io.resp_in[0].f1[2].is_br
invalidate ubtb.io.resp_in[0].f1[2].taken
invalidate ubtb.io.resp_in[0].f1[3].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f1[3].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f1[3].is_jal
invalidate ubtb.io.resp_in[0].f1[3].is_br
invalidate ubtb.io.resp_in[0].f1[3].taken
invalidate ubtb.io.f1_lhist
invalidate ubtb.io.f1_ghist
invalidate ubtb.io.f0_mask
invalidate ubtb.io.f0_pc
invalidate ubtb.io.f0_valid
invalidate bim.io.update.bits.meta
invalidate bim.io.update.bits.target
invalidate bim.io.update.bits.lhist
invalidate bim.io.update.bits.ghist
invalidate bim.io.update.bits.cfi_is_jalr
invalidate bim.io.update.bits.cfi_is_jal
invalidate bim.io.update.bits.cfi_is_br
invalidate bim.io.update.bits.cfi_mispredicted
invalidate bim.io.update.bits.cfi_taken
invalidate bim.io.update.bits.cfi_idx.bits
invalidate bim.io.update.bits.cfi_idx.valid
invalidate bim.io.update.bits.br_mask
invalidate bim.io.update.bits.pc
invalidate bim.io.update.bits.btb_mispredicts
invalidate bim.io.update.bits.is_repair_update
invalidate bim.io.update.bits.is_mispredict_update
invalidate bim.io.update.valid
invalidate bim.io.f3_fire
invalidate bim.io.f3_meta
invalidate bim.io.resp.f3[0].predicted_pc.bits
invalidate bim.io.resp.f3[0].predicted_pc.valid
invalidate bim.io.resp.f3[0].is_jal
invalidate bim.io.resp.f3[0].is_br
invalidate bim.io.resp.f3[0].taken
invalidate bim.io.resp.f3[1].predicted_pc.bits
invalidate bim.io.resp.f3[1].predicted_pc.valid
invalidate bim.io.resp.f3[1].is_jal
invalidate bim.io.resp.f3[1].is_br
invalidate bim.io.resp.f3[1].taken
invalidate bim.io.resp.f3[2].predicted_pc.bits
invalidate bim.io.resp.f3[2].predicted_pc.valid
invalidate bim.io.resp.f3[2].is_jal
invalidate bim.io.resp.f3[2].is_br
invalidate bim.io.resp.f3[2].taken
invalidate bim.io.resp.f3[3].predicted_pc.bits
invalidate bim.io.resp.f3[3].predicted_pc.valid
invalidate bim.io.resp.f3[3].is_jal
invalidate bim.io.resp.f3[3].is_br
invalidate bim.io.resp.f3[3].taken
invalidate bim.io.resp.f2[0].predicted_pc.bits
invalidate bim.io.resp.f2[0].predicted_pc.valid
invalidate bim.io.resp.f2[0].is_jal
invalidate bim.io.resp.f2[0].is_br
invalidate bim.io.resp.f2[0].taken
invalidate bim.io.resp.f2[1].predicted_pc.bits
invalidate bim.io.resp.f2[1].predicted_pc.valid
invalidate bim.io.resp.f2[1].is_jal
invalidate bim.io.resp.f2[1].is_br
invalidate bim.io.resp.f2[1].taken
invalidate bim.io.resp.f2[2].predicted_pc.bits
invalidate bim.io.resp.f2[2].predicted_pc.valid
invalidate bim.io.resp.f2[2].is_jal
invalidate bim.io.resp.f2[2].is_br
invalidate bim.io.resp.f2[2].taken
invalidate bim.io.resp.f2[3].predicted_pc.bits
invalidate bim.io.resp.f2[3].predicted_pc.valid
invalidate bim.io.resp.f2[3].is_jal
invalidate bim.io.resp.f2[3].is_br
invalidate bim.io.resp.f2[3].taken
invalidate bim.io.resp.f1[0].predicted_pc.bits
invalidate bim.io.resp.f1[0].predicted_pc.valid
invalidate bim.io.resp.f1[0].is_jal
invalidate bim.io.resp.f1[0].is_br
invalidate bim.io.resp.f1[0].taken
invalidate bim.io.resp.f1[1].predicted_pc.bits
invalidate bim.io.resp.f1[1].predicted_pc.valid
invalidate bim.io.resp.f1[1].is_jal
invalidate bim.io.resp.f1[1].is_br
invalidate bim.io.resp.f1[1].taken
invalidate bim.io.resp.f1[2].predicted_pc.bits
invalidate bim.io.resp.f1[2].predicted_pc.valid
invalidate bim.io.resp.f1[2].is_jal
invalidate bim.io.resp.f1[2].is_br
invalidate bim.io.resp.f1[2].taken
invalidate bim.io.resp.f1[3].predicted_pc.bits
invalidate bim.io.resp.f1[3].predicted_pc.valid
invalidate bim.io.resp.f1[3].is_jal
invalidate bim.io.resp.f1[3].is_br
invalidate bim.io.resp.f1[3].taken
invalidate bim.io.resp_in[0].f3[0].predicted_pc.bits
invalidate bim.io.resp_in[0].f3[0].predicted_pc.valid
invalidate bim.io.resp_in[0].f3[0].is_jal
invalidate bim.io.resp_in[0].f3[0].is_br
invalidate bim.io.resp_in[0].f3[0].taken
invalidate bim.io.resp_in[0].f3[1].predicted_pc.bits
invalidate bim.io.resp_in[0].f3[1].predicted_pc.valid
invalidate bim.io.resp_in[0].f3[1].is_jal
invalidate bim.io.resp_in[0].f3[1].is_br
invalidate bim.io.resp_in[0].f3[1].taken
invalidate bim.io.resp_in[0].f3[2].predicted_pc.bits
invalidate bim.io.resp_in[0].f3[2].predicted_pc.valid
invalidate bim.io.resp_in[0].f3[2].is_jal
invalidate bim.io.resp_in[0].f3[2].is_br
invalidate bim.io.resp_in[0].f3[2].taken
invalidate bim.io.resp_in[0].f3[3].predicted_pc.bits
invalidate bim.io.resp_in[0].f3[3].predicted_pc.valid
invalidate bim.io.resp_in[0].f3[3].is_jal
invalidate bim.io.resp_in[0].f3[3].is_br
invalidate bim.io.resp_in[0].f3[3].taken
invalidate bim.io.resp_in[0].f2[0].predicted_pc.bits
invalidate bim.io.resp_in[0].f2[0].predicted_pc.valid
invalidate bim.io.resp_in[0].f2[0].is_jal
invalidate bim.io.resp_in[0].f2[0].is_br
invalidate bim.io.resp_in[0].f2[0].taken
invalidate bim.io.resp_in[0].f2[1].predicted_pc.bits
invalidate bim.io.resp_in[0].f2[1].predicted_pc.valid
invalidate bim.io.resp_in[0].f2[1].is_jal
invalidate bim.io.resp_in[0].f2[1].is_br
invalidate bim.io.resp_in[0].f2[1].taken
invalidate bim.io.resp_in[0].f2[2].predicted_pc.bits
invalidate bim.io.resp_in[0].f2[2].predicted_pc.valid
invalidate bim.io.resp_in[0].f2[2].is_jal
invalidate bim.io.resp_in[0].f2[2].is_br
invalidate bim.io.resp_in[0].f2[2].taken
invalidate bim.io.resp_in[0].f2[3].predicted_pc.bits
invalidate bim.io.resp_in[0].f2[3].predicted_pc.valid
invalidate bim.io.resp_in[0].f2[3].is_jal
invalidate bim.io.resp_in[0].f2[3].is_br
invalidate bim.io.resp_in[0].f2[3].taken
invalidate bim.io.resp_in[0].f1[0].predicted_pc.bits
invalidate bim.io.resp_in[0].f1[0].predicted_pc.valid
invalidate bim.io.resp_in[0].f1[0].is_jal
invalidate bim.io.resp_in[0].f1[0].is_br
invalidate bim.io.resp_in[0].f1[0].taken
invalidate bim.io.resp_in[0].f1[1].predicted_pc.bits
invalidate bim.io.resp_in[0].f1[1].predicted_pc.valid
invalidate bim.io.resp_in[0].f1[1].is_jal
invalidate bim.io.resp_in[0].f1[1].is_br
invalidate bim.io.resp_in[0].f1[1].taken
invalidate bim.io.resp_in[0].f1[2].predicted_pc.bits
invalidate bim.io.resp_in[0].f1[2].predicted_pc.valid
invalidate bim.io.resp_in[0].f1[2].is_jal
invalidate bim.io.resp_in[0].f1[2].is_br
invalidate bim.io.resp_in[0].f1[2].taken
invalidate bim.io.resp_in[0].f1[3].predicted_pc.bits
invalidate bim.io.resp_in[0].f1[3].predicted_pc.valid
invalidate bim.io.resp_in[0].f1[3].is_jal
invalidate bim.io.resp_in[0].f1[3].is_br
invalidate bim.io.resp_in[0].f1[3].taken
invalidate bim.io.f1_lhist
invalidate bim.io.f1_ghist
invalidate bim.io.f0_mask
invalidate bim.io.f0_pc
invalidate bim.io.f0_valid
connect ubtb.io.resp_in[0].f3[0].predicted_pc.bits, io.resp_in[0].f3[0].predicted_pc.bits
connect ubtb.io.resp_in[0].f3[0].predicted_pc.valid, io.resp_in[0].f3[0].predicted_pc.valid
connect ubtb.io.resp_in[0].f3[0].is_jal, io.resp_in[0].f3[0].is_jal
connect ubtb.io.resp_in[0].f3[0].is_br, io.resp_in[0].f3[0].is_br
connect ubtb.io.resp_in[0].f3[0].taken, io.resp_in[0].f3[0].taken
connect ubtb.io.resp_in[0].f3[1].predicted_pc.bits, io.resp_in[0].f3[1].predicted_pc.bits
connect ubtb.io.resp_in[0].f3[1].predicted_pc.valid, io.resp_in[0].f3[1].predicted_pc.valid
connect ubtb.io.resp_in[0].f3[1].is_jal, io.resp_in[0].f3[1].is_jal
connect ubtb.io.resp_in[0].f3[1].is_br, io.resp_in[0].f3[1].is_br
connect ubtb.io.resp_in[0].f3[1].taken, io.resp_in[0].f3[1].taken
connect ubtb.io.resp_in[0].f3[2].predicted_pc.bits, io.resp_in[0].f3[2].predicted_pc.bits
connect ubtb.io.resp_in[0].f3[2].predicted_pc.valid, io.resp_in[0].f3[2].predicted_pc.valid
connect ubtb.io.resp_in[0].f3[2].is_jal, io.resp_in[0].f3[2].is_jal
connect ubtb.io.resp_in[0].f3[2].is_br, io.resp_in[0].f3[2].is_br
connect ubtb.io.resp_in[0].f3[2].taken, io.resp_in[0].f3[2].taken
connect ubtb.io.resp_in[0].f3[3].predicted_pc.bits, io.resp_in[0].f3[3].predicted_pc.bits
connect ubtb.io.resp_in[0].f3[3].predicted_pc.valid, io.resp_in[0].f3[3].predicted_pc.valid
connect ubtb.io.resp_in[0].f3[3].is_jal, io.resp_in[0].f3[3].is_jal
connect ubtb.io.resp_in[0].f3[3].is_br, io.resp_in[0].f3[3].is_br
connect ubtb.io.resp_in[0].f3[3].taken, io.resp_in[0].f3[3].taken
connect ubtb.io.resp_in[0].f2[0].predicted_pc.bits, io.resp_in[0].f2[0].predicted_pc.bits
connect ubtb.io.resp_in[0].f2[0].predicted_pc.valid, io.resp_in[0].f2[0].predicted_pc.valid
connect ubtb.io.resp_in[0].f2[0].is_jal, io.resp_in[0].f2[0].is_jal
connect ubtb.io.resp_in[0].f2[0].is_br, io.resp_in[0].f2[0].is_br
connect ubtb.io.resp_in[0].f2[0].taken, io.resp_in[0].f2[0].taken
connect ubtb.io.resp_in[0].f2[1].predicted_pc.bits, io.resp_in[0].f2[1].predicted_pc.bits
connect ubtb.io.resp_in[0].f2[1].predicted_pc.valid, io.resp_in[0].f2[1].predicted_pc.valid
connect ubtb.io.resp_in[0].f2[1].is_jal, io.resp_in[0].f2[1].is_jal
connect ubtb.io.resp_in[0].f2[1].is_br, io.resp_in[0].f2[1].is_br
connect ubtb.io.resp_in[0].f2[1].taken, io.resp_in[0].f2[1].taken
connect ubtb.io.resp_in[0].f2[2].predicted_pc.bits, io.resp_in[0].f2[2].predicted_pc.bits
connect ubtb.io.resp_in[0].f2[2].predicted_pc.valid, io.resp_in[0].f2[2].predicted_pc.valid
connect ubtb.io.resp_in[0].f2[2].is_jal, io.resp_in[0].f2[2].is_jal
connect ubtb.io.resp_in[0].f2[2].is_br, io.resp_in[0].f2[2].is_br
connect ubtb.io.resp_in[0].f2[2].taken, io.resp_in[0].f2[2].taken
connect ubtb.io.resp_in[0].f2[3].predicted_pc.bits, io.resp_in[0].f2[3].predicted_pc.bits
connect ubtb.io.resp_in[0].f2[3].predicted_pc.valid, io.resp_in[0].f2[3].predicted_pc.valid
connect ubtb.io.resp_in[0].f2[3].is_jal, io.resp_in[0].f2[3].is_jal
connect ubtb.io.resp_in[0].f2[3].is_br, io.resp_in[0].f2[3].is_br
connect ubtb.io.resp_in[0].f2[3].taken, io.resp_in[0].f2[3].taken
connect ubtb.io.resp_in[0].f1[0].predicted_pc.bits, io.resp_in[0].f1[0].predicted_pc.bits
connect ubtb.io.resp_in[0].f1[0].predicted_pc.valid, io.resp_in[0].f1[0].predicted_pc.valid
connect ubtb.io.resp_in[0].f1[0].is_jal, io.resp_in[0].f1[0].is_jal
connect ubtb.io.resp_in[0].f1[0].is_br, io.resp_in[0].f1[0].is_br
connect ubtb.io.resp_in[0].f1[0].taken, io.resp_in[0].f1[0].taken
connect ubtb.io.resp_in[0].f1[1].predicted_pc.bits, io.resp_in[0].f1[1].predicted_pc.bits
connect ubtb.io.resp_in[0].f1[1].predicted_pc.valid, io.resp_in[0].f1[1].predicted_pc.valid
connect ubtb.io.resp_in[0].f1[1].is_jal, io.resp_in[0].f1[1].is_jal
connect ubtb.io.resp_in[0].f1[1].is_br, io.resp_in[0].f1[1].is_br
connect ubtb.io.resp_in[0].f1[1].taken, io.resp_in[0].f1[1].taken
connect ubtb.io.resp_in[0].f1[2].predicted_pc.bits, io.resp_in[0].f1[2].predicted_pc.bits
connect ubtb.io.resp_in[0].f1[2].predicted_pc.valid, io.resp_in[0].f1[2].predicted_pc.valid
connect ubtb.io.resp_in[0].f1[2].is_jal, io.resp_in[0].f1[2].is_jal
connect ubtb.io.resp_in[0].f1[2].is_br, io.resp_in[0].f1[2].is_br
connect ubtb.io.resp_in[0].f1[2].taken, io.resp_in[0].f1[2].taken
connect ubtb.io.resp_in[0].f1[3].predicted_pc.bits, io.resp_in[0].f1[3].predicted_pc.bits
connect ubtb.io.resp_in[0].f1[3].predicted_pc.valid, io.resp_in[0].f1[3].predicted_pc.valid
connect ubtb.io.resp_in[0].f1[3].is_jal, io.resp_in[0].f1[3].is_jal
connect ubtb.io.resp_in[0].f1[3].is_br, io.resp_in[0].f1[3].is_br
connect ubtb.io.resp_in[0].f1[3].taken, io.resp_in[0].f1[3].taken
connect bim.io.resp_in[0].f3[0].predicted_pc.bits, ubtb.io.resp.f3[0].predicted_pc.bits
connect bim.io.resp_in[0].f3[0].predicted_pc.valid, ubtb.io.resp.f3[0].predicted_pc.valid
connect bim.io.resp_in[0].f3[0].is_jal, ubtb.io.resp.f3[0].is_jal
connect bim.io.resp_in[0].f3[0].is_br, ubtb.io.resp.f3[0].is_br
connect bim.io.resp_in[0].f3[0].taken, ubtb.io.resp.f3[0].taken
connect bim.io.resp_in[0].f3[1].predicted_pc.bits, ubtb.io.resp.f3[1].predicted_pc.bits
connect bim.io.resp_in[0].f3[1].predicted_pc.valid, ubtb.io.resp.f3[1].predicted_pc.valid
connect bim.io.resp_in[0].f3[1].is_jal, ubtb.io.resp.f3[1].is_jal
connect bim.io.resp_in[0].f3[1].is_br, ubtb.io.resp.f3[1].is_br
connect bim.io.resp_in[0].f3[1].taken, ubtb.io.resp.f3[1].taken
connect bim.io.resp_in[0].f3[2].predicted_pc.bits, ubtb.io.resp.f3[2].predicted_pc.bits
connect bim.io.resp_in[0].f3[2].predicted_pc.valid, ubtb.io.resp.f3[2].predicted_pc.valid
connect bim.io.resp_in[0].f3[2].is_jal, ubtb.io.resp.f3[2].is_jal
connect bim.io.resp_in[0].f3[2].is_br, ubtb.io.resp.f3[2].is_br
connect bim.io.resp_in[0].f3[2].taken, ubtb.io.resp.f3[2].taken
connect bim.io.resp_in[0].f3[3].predicted_pc.bits, ubtb.io.resp.f3[3].predicted_pc.bits
connect bim.io.resp_in[0].f3[3].predicted_pc.valid, ubtb.io.resp.f3[3].predicted_pc.valid
connect bim.io.resp_in[0].f3[3].is_jal, ubtb.io.resp.f3[3].is_jal
connect bim.io.resp_in[0].f3[3].is_br, ubtb.io.resp.f3[3].is_br
connect bim.io.resp_in[0].f3[3].taken, ubtb.io.resp.f3[3].taken
connect bim.io.resp_in[0].f2[0].predicted_pc.bits, ubtb.io.resp.f2[0].predicted_pc.bits
connect bim.io.resp_in[0].f2[0].predicted_pc.valid, ubtb.io.resp.f2[0].predicted_pc.valid
connect bim.io.resp_in[0].f2[0].is_jal, ubtb.io.resp.f2[0].is_jal
connect bim.io.resp_in[0].f2[0].is_br, ubtb.io.resp.f2[0].is_br
connect bim.io.resp_in[0].f2[0].taken, ubtb.io.resp.f2[0].taken
connect bim.io.resp_in[0].f2[1].predicted_pc.bits, ubtb.io.resp.f2[1].predicted_pc.bits
connect bim.io.resp_in[0].f2[1].predicted_pc.valid, ubtb.io.resp.f2[1].predicted_pc.valid
connect bim.io.resp_in[0].f2[1].is_jal, ubtb.io.resp.f2[1].is_jal
connect bim.io.resp_in[0].f2[1].is_br, ubtb.io.resp.f2[1].is_br
connect bim.io.resp_in[0].f2[1].taken, ubtb.io.resp.f2[1].taken
connect bim.io.resp_in[0].f2[2].predicted_pc.bits, ubtb.io.resp.f2[2].predicted_pc.bits
connect bim.io.resp_in[0].f2[2].predicted_pc.valid, ubtb.io.resp.f2[2].predicted_pc.valid
connect bim.io.resp_in[0].f2[2].is_jal, ubtb.io.resp.f2[2].is_jal
connect bim.io.resp_in[0].f2[2].is_br, ubtb.io.resp.f2[2].is_br
connect bim.io.resp_in[0].f2[2].taken, ubtb.io.resp.f2[2].taken
connect bim.io.resp_in[0].f2[3].predicted_pc.bits, ubtb.io.resp.f2[3].predicted_pc.bits
connect bim.io.resp_in[0].f2[3].predicted_pc.valid, ubtb.io.resp.f2[3].predicted_pc.valid
connect bim.io.resp_in[0].f2[3].is_jal, ubtb.io.resp.f2[3].is_jal
connect bim.io.resp_in[0].f2[3].is_br, ubtb.io.resp.f2[3].is_br
connect bim.io.resp_in[0].f2[3].taken, ubtb.io.resp.f2[3].taken
connect bim.io.resp_in[0].f1[0].predicted_pc.bits, ubtb.io.resp.f1[0].predicted_pc.bits
connect bim.io.resp_in[0].f1[0].predicted_pc.valid, ubtb.io.resp.f1[0].predicted_pc.valid
connect bim.io.resp_in[0].f1[0].is_jal, ubtb.io.resp.f1[0].is_jal
connect bim.io.resp_in[0].f1[0].is_br, ubtb.io.resp.f1[0].is_br
connect bim.io.resp_in[0].f1[0].taken, ubtb.io.resp.f1[0].taken
connect bim.io.resp_in[0].f1[1].predicted_pc.bits, ubtb.io.resp.f1[1].predicted_pc.bits
connect bim.io.resp_in[0].f1[1].predicted_pc.valid, ubtb.io.resp.f1[1].predicted_pc.valid
connect bim.io.resp_in[0].f1[1].is_jal, ubtb.io.resp.f1[1].is_jal
connect bim.io.resp_in[0].f1[1].is_br, ubtb.io.resp.f1[1].is_br
connect bim.io.resp_in[0].f1[1].taken, ubtb.io.resp.f1[1].taken
connect bim.io.resp_in[0].f1[2].predicted_pc.bits, ubtb.io.resp.f1[2].predicted_pc.bits
connect bim.io.resp_in[0].f1[2].predicted_pc.valid, ubtb.io.resp.f1[2].predicted_pc.valid
connect bim.io.resp_in[0].f1[2].is_jal, ubtb.io.resp.f1[2].is_jal
connect bim.io.resp_in[0].f1[2].is_br, ubtb.io.resp.f1[2].is_br
connect bim.io.resp_in[0].f1[2].taken, ubtb.io.resp.f1[2].taken
connect bim.io.resp_in[0].f1[3].predicted_pc.bits, ubtb.io.resp.f1[3].predicted_pc.bits
connect bim.io.resp_in[0].f1[3].predicted_pc.valid, ubtb.io.resp.f1[3].predicted_pc.valid
connect bim.io.resp_in[0].f1[3].is_jal, ubtb.io.resp.f1[3].is_jal
connect bim.io.resp_in[0].f1[3].is_br, ubtb.io.resp.f1[3].is_br
connect bim.io.resp_in[0].f1[3].taken, ubtb.io.resp.f1[3].taken
connect btb.io.resp_in[0].f3[0].predicted_pc.bits, bim.io.resp.f3[0].predicted_pc.bits
connect btb.io.resp_in[0].f3[0].predicted_pc.valid, bim.io.resp.f3[0].predicted_pc.valid
connect btb.io.resp_in[0].f3[0].is_jal, bim.io.resp.f3[0].is_jal
connect btb.io.resp_in[0].f3[0].is_br, bim.io.resp.f3[0].is_br
connect btb.io.resp_in[0].f3[0].taken, bim.io.resp.f3[0].taken
connect btb.io.resp_in[0].f3[1].predicted_pc.bits, bim.io.resp.f3[1].predicted_pc.bits
connect btb.io.resp_in[0].f3[1].predicted_pc.valid, bim.io.resp.f3[1].predicted_pc.valid
connect btb.io.resp_in[0].f3[1].is_jal, bim.io.resp.f3[1].is_jal
connect btb.io.resp_in[0].f3[1].is_br, bim.io.resp.f3[1].is_br
connect btb.io.resp_in[0].f3[1].taken, bim.io.resp.f3[1].taken
connect btb.io.resp_in[0].f3[2].predicted_pc.bits, bim.io.resp.f3[2].predicted_pc.bits
connect btb.io.resp_in[0].f3[2].predicted_pc.valid, bim.io.resp.f3[2].predicted_pc.valid
connect btb.io.resp_in[0].f3[2].is_jal, bim.io.resp.f3[2].is_jal
connect btb.io.resp_in[0].f3[2].is_br, bim.io.resp.f3[2].is_br
connect btb.io.resp_in[0].f3[2].taken, bim.io.resp.f3[2].taken
connect btb.io.resp_in[0].f3[3].predicted_pc.bits, bim.io.resp.f3[3].predicted_pc.bits
connect btb.io.resp_in[0].f3[3].predicted_pc.valid, bim.io.resp.f3[3].predicted_pc.valid
connect btb.io.resp_in[0].f3[3].is_jal, bim.io.resp.f3[3].is_jal
connect btb.io.resp_in[0].f3[3].is_br, bim.io.resp.f3[3].is_br
connect btb.io.resp_in[0].f3[3].taken, bim.io.resp.f3[3].taken
connect btb.io.resp_in[0].f2[0].predicted_pc.bits, bim.io.resp.f2[0].predicted_pc.bits
connect btb.io.resp_in[0].f2[0].predicted_pc.valid, bim.io.resp.f2[0].predicted_pc.valid
connect btb.io.resp_in[0].f2[0].is_jal, bim.io.resp.f2[0].is_jal
connect btb.io.resp_in[0].f2[0].is_br, bim.io.resp.f2[0].is_br
connect btb.io.resp_in[0].f2[0].taken, bim.io.resp.f2[0].taken
connect btb.io.resp_in[0].f2[1].predicted_pc.bits, bim.io.resp.f2[1].predicted_pc.bits
connect btb.io.resp_in[0].f2[1].predicted_pc.valid, bim.io.resp.f2[1].predicted_pc.valid
connect btb.io.resp_in[0].f2[1].is_jal, bim.io.resp.f2[1].is_jal
connect btb.io.resp_in[0].f2[1].is_br, bim.io.resp.f2[1].is_br
connect btb.io.resp_in[0].f2[1].taken, bim.io.resp.f2[1].taken
connect btb.io.resp_in[0].f2[2].predicted_pc.bits, bim.io.resp.f2[2].predicted_pc.bits
connect btb.io.resp_in[0].f2[2].predicted_pc.valid, bim.io.resp.f2[2].predicted_pc.valid
connect btb.io.resp_in[0].f2[2].is_jal, bim.io.resp.f2[2].is_jal
connect btb.io.resp_in[0].f2[2].is_br, bim.io.resp.f2[2].is_br
connect btb.io.resp_in[0].f2[2].taken, bim.io.resp.f2[2].taken
connect btb.io.resp_in[0].f2[3].predicted_pc.bits, bim.io.resp.f2[3].predicted_pc.bits
connect btb.io.resp_in[0].f2[3].predicted_pc.valid, bim.io.resp.f2[3].predicted_pc.valid
connect btb.io.resp_in[0].f2[3].is_jal, bim.io.resp.f2[3].is_jal
connect btb.io.resp_in[0].f2[3].is_br, bim.io.resp.f2[3].is_br
connect btb.io.resp_in[0].f2[3].taken, bim.io.resp.f2[3].taken
connect btb.io.resp_in[0].f1[0].predicted_pc.bits, bim.io.resp.f1[0].predicted_pc.bits
connect btb.io.resp_in[0].f1[0].predicted_pc.valid, bim.io.resp.f1[0].predicted_pc.valid
connect btb.io.resp_in[0].f1[0].is_jal, bim.io.resp.f1[0].is_jal
connect btb.io.resp_in[0].f1[0].is_br, bim.io.resp.f1[0].is_br
connect btb.io.resp_in[0].f1[0].taken, bim.io.resp.f1[0].taken
connect btb.io.resp_in[0].f1[1].predicted_pc.bits, bim.io.resp.f1[1].predicted_pc.bits
connect btb.io.resp_in[0].f1[1].predicted_pc.valid, bim.io.resp.f1[1].predicted_pc.valid
connect btb.io.resp_in[0].f1[1].is_jal, bim.io.resp.f1[1].is_jal
connect btb.io.resp_in[0].f1[1].is_br, bim.io.resp.f1[1].is_br
connect btb.io.resp_in[0].f1[1].taken, bim.io.resp.f1[1].taken
connect btb.io.resp_in[0].f1[2].predicted_pc.bits, bim.io.resp.f1[2].predicted_pc.bits
connect btb.io.resp_in[0].f1[2].predicted_pc.valid, bim.io.resp.f1[2].predicted_pc.valid
connect btb.io.resp_in[0].f1[2].is_jal, bim.io.resp.f1[2].is_jal
connect btb.io.resp_in[0].f1[2].is_br, bim.io.resp.f1[2].is_br
connect btb.io.resp_in[0].f1[2].taken, bim.io.resp.f1[2].taken
connect btb.io.resp_in[0].f1[3].predicted_pc.bits, bim.io.resp.f1[3].predicted_pc.bits
connect btb.io.resp_in[0].f1[3].predicted_pc.valid, bim.io.resp.f1[3].predicted_pc.valid
connect btb.io.resp_in[0].f1[3].is_jal, bim.io.resp.f1[3].is_jal
connect btb.io.resp_in[0].f1[3].is_br, bim.io.resp.f1[3].is_br
connect btb.io.resp_in[0].f1[3].taken, bim.io.resp.f1[3].taken
connect tage.io.resp_in[0].f3[0].predicted_pc.bits, btb.io.resp.f3[0].predicted_pc.bits
connect tage.io.resp_in[0].f3[0].predicted_pc.valid, btb.io.resp.f3[0].predicted_pc.valid
connect tage.io.resp_in[0].f3[0].is_jal, btb.io.resp.f3[0].is_jal
connect tage.io.resp_in[0].f3[0].is_br, btb.io.resp.f3[0].is_br
connect tage.io.resp_in[0].f3[0].taken, btb.io.resp.f3[0].taken
connect tage.io.resp_in[0].f3[1].predicted_pc.bits, btb.io.resp.f3[1].predicted_pc.bits
connect tage.io.resp_in[0].f3[1].predicted_pc.valid, btb.io.resp.f3[1].predicted_pc.valid
connect tage.io.resp_in[0].f3[1].is_jal, btb.io.resp.f3[1].is_jal
connect tage.io.resp_in[0].f3[1].is_br, btb.io.resp.f3[1].is_br
connect tage.io.resp_in[0].f3[1].taken, btb.io.resp.f3[1].taken
connect tage.io.resp_in[0].f3[2].predicted_pc.bits, btb.io.resp.f3[2].predicted_pc.bits
connect tage.io.resp_in[0].f3[2].predicted_pc.valid, btb.io.resp.f3[2].predicted_pc.valid
connect tage.io.resp_in[0].f3[2].is_jal, btb.io.resp.f3[2].is_jal
connect tage.io.resp_in[0].f3[2].is_br, btb.io.resp.f3[2].is_br
connect tage.io.resp_in[0].f3[2].taken, btb.io.resp.f3[2].taken
connect tage.io.resp_in[0].f3[3].predicted_pc.bits, btb.io.resp.f3[3].predicted_pc.bits
connect tage.io.resp_in[0].f3[3].predicted_pc.valid, btb.io.resp.f3[3].predicted_pc.valid
connect tage.io.resp_in[0].f3[3].is_jal, btb.io.resp.f3[3].is_jal
connect tage.io.resp_in[0].f3[3].is_br, btb.io.resp.f3[3].is_br
connect tage.io.resp_in[0].f3[3].taken, btb.io.resp.f3[3].taken
connect tage.io.resp_in[0].f2[0].predicted_pc.bits, btb.io.resp.f2[0].predicted_pc.bits
connect tage.io.resp_in[0].f2[0].predicted_pc.valid, btb.io.resp.f2[0].predicted_pc.valid
connect tage.io.resp_in[0].f2[0].is_jal, btb.io.resp.f2[0].is_jal
connect tage.io.resp_in[0].f2[0].is_br, btb.io.resp.f2[0].is_br
connect tage.io.resp_in[0].f2[0].taken, btb.io.resp.f2[0].taken
connect tage.io.resp_in[0].f2[1].predicted_pc.bits, btb.io.resp.f2[1].predicted_pc.bits
connect tage.io.resp_in[0].f2[1].predicted_pc.valid, btb.io.resp.f2[1].predicted_pc.valid
connect tage.io.resp_in[0].f2[1].is_jal, btb.io.resp.f2[1].is_jal
connect tage.io.resp_in[0].f2[1].is_br, btb.io.resp.f2[1].is_br
connect tage.io.resp_in[0].f2[1].taken, btb.io.resp.f2[1].taken
connect tage.io.resp_in[0].f2[2].predicted_pc.bits, btb.io.resp.f2[2].predicted_pc.bits
connect tage.io.resp_in[0].f2[2].predicted_pc.valid, btb.io.resp.f2[2].predicted_pc.valid
connect tage.io.resp_in[0].f2[2].is_jal, btb.io.resp.f2[2].is_jal
connect tage.io.resp_in[0].f2[2].is_br, btb.io.resp.f2[2].is_br
connect tage.io.resp_in[0].f2[2].taken, btb.io.resp.f2[2].taken
connect tage.io.resp_in[0].f2[3].predicted_pc.bits, btb.io.resp.f2[3].predicted_pc.bits
connect tage.io.resp_in[0].f2[3].predicted_pc.valid, btb.io.resp.f2[3].predicted_pc.valid
connect tage.io.resp_in[0].f2[3].is_jal, btb.io.resp.f2[3].is_jal
connect tage.io.resp_in[0].f2[3].is_br, btb.io.resp.f2[3].is_br
connect tage.io.resp_in[0].f2[3].taken, btb.io.resp.f2[3].taken
connect tage.io.resp_in[0].f1[0].predicted_pc.bits, btb.io.resp.f1[0].predicted_pc.bits
connect tage.io.resp_in[0].f1[0].predicted_pc.valid, btb.io.resp.f1[0].predicted_pc.valid
connect tage.io.resp_in[0].f1[0].is_jal, btb.io.resp.f1[0].is_jal
connect tage.io.resp_in[0].f1[0].is_br, btb.io.resp.f1[0].is_br
connect tage.io.resp_in[0].f1[0].taken, btb.io.resp.f1[0].taken
connect tage.io.resp_in[0].f1[1].predicted_pc.bits, btb.io.resp.f1[1].predicted_pc.bits
connect tage.io.resp_in[0].f1[1].predicted_pc.valid, btb.io.resp.f1[1].predicted_pc.valid
connect tage.io.resp_in[0].f1[1].is_jal, btb.io.resp.f1[1].is_jal
connect tage.io.resp_in[0].f1[1].is_br, btb.io.resp.f1[1].is_br
connect tage.io.resp_in[0].f1[1].taken, btb.io.resp.f1[1].taken
connect tage.io.resp_in[0].f1[2].predicted_pc.bits, btb.io.resp.f1[2].predicted_pc.bits
connect tage.io.resp_in[0].f1[2].predicted_pc.valid, btb.io.resp.f1[2].predicted_pc.valid
connect tage.io.resp_in[0].f1[2].is_jal, btb.io.resp.f1[2].is_jal
connect tage.io.resp_in[0].f1[2].is_br, btb.io.resp.f1[2].is_br
connect tage.io.resp_in[0].f1[2].taken, btb.io.resp.f1[2].taken
connect tage.io.resp_in[0].f1[3].predicted_pc.bits, btb.io.resp.f1[3].predicted_pc.bits
connect tage.io.resp_in[0].f1[3].predicted_pc.valid, btb.io.resp.f1[3].predicted_pc.valid
connect tage.io.resp_in[0].f1[3].is_jal, btb.io.resp.f1[3].is_jal
connect tage.io.resp_in[0].f1[3].is_br, btb.io.resp.f1[3].is_br
connect tage.io.resp_in[0].f1[3].taken, btb.io.resp.f1[3].taken
connect loop.io.resp_in[0].f3[0].predicted_pc.bits, tage.io.resp.f3[0].predicted_pc.bits
connect loop.io.resp_in[0].f3[0].predicted_pc.valid, tage.io.resp.f3[0].predicted_pc.valid
connect loop.io.resp_in[0].f3[0].is_jal, tage.io.resp.f3[0].is_jal
connect loop.io.resp_in[0].f3[0].is_br, tage.io.resp.f3[0].is_br
connect loop.io.resp_in[0].f3[0].taken, tage.io.resp.f3[0].taken
connect loop.io.resp_in[0].f3[1].predicted_pc.bits, tage.io.resp.f3[1].predicted_pc.bits
connect loop.io.resp_in[0].f3[1].predicted_pc.valid, tage.io.resp.f3[1].predicted_pc.valid
connect loop.io.resp_in[0].f3[1].is_jal, tage.io.resp.f3[1].is_jal
connect loop.io.resp_in[0].f3[1].is_br, tage.io.resp.f3[1].is_br
connect loop.io.resp_in[0].f3[1].taken, tage.io.resp.f3[1].taken
connect loop.io.resp_in[0].f3[2].predicted_pc.bits, tage.io.resp.f3[2].predicted_pc.bits
connect loop.io.resp_in[0].f3[2].predicted_pc.valid, tage.io.resp.f3[2].predicted_pc.valid
connect loop.io.resp_in[0].f3[2].is_jal, tage.io.resp.f3[2].is_jal
connect loop.io.resp_in[0].f3[2].is_br, tage.io.resp.f3[2].is_br
connect loop.io.resp_in[0].f3[2].taken, tage.io.resp.f3[2].taken
connect loop.io.resp_in[0].f3[3].predicted_pc.bits, tage.io.resp.f3[3].predicted_pc.bits
connect loop.io.resp_in[0].f3[3].predicted_pc.valid, tage.io.resp.f3[3].predicted_pc.valid
connect loop.io.resp_in[0].f3[3].is_jal, tage.io.resp.f3[3].is_jal
connect loop.io.resp_in[0].f3[3].is_br, tage.io.resp.f3[3].is_br
connect loop.io.resp_in[0].f3[3].taken, tage.io.resp.f3[3].taken
connect loop.io.resp_in[0].f2[0].predicted_pc.bits, tage.io.resp.f2[0].predicted_pc.bits
connect loop.io.resp_in[0].f2[0].predicted_pc.valid, tage.io.resp.f2[0].predicted_pc.valid
connect loop.io.resp_in[0].f2[0].is_jal, tage.io.resp.f2[0].is_jal
connect loop.io.resp_in[0].f2[0].is_br, tage.io.resp.f2[0].is_br
connect loop.io.resp_in[0].f2[0].taken, tage.io.resp.f2[0].taken
connect loop.io.resp_in[0].f2[1].predicted_pc.bits, tage.io.resp.f2[1].predicted_pc.bits
connect loop.io.resp_in[0].f2[1].predicted_pc.valid, tage.io.resp.f2[1].predicted_pc.valid
connect loop.io.resp_in[0].f2[1].is_jal, tage.io.resp.f2[1].is_jal
connect loop.io.resp_in[0].f2[1].is_br, tage.io.resp.f2[1].is_br
connect loop.io.resp_in[0].f2[1].taken, tage.io.resp.f2[1].taken
connect loop.io.resp_in[0].f2[2].predicted_pc.bits, tage.io.resp.f2[2].predicted_pc.bits
connect loop.io.resp_in[0].f2[2].predicted_pc.valid, tage.io.resp.f2[2].predicted_pc.valid
connect loop.io.resp_in[0].f2[2].is_jal, tage.io.resp.f2[2].is_jal
connect loop.io.resp_in[0].f2[2].is_br, tage.io.resp.f2[2].is_br
connect loop.io.resp_in[0].f2[2].taken, tage.io.resp.f2[2].taken
connect loop.io.resp_in[0].f2[3].predicted_pc.bits, tage.io.resp.f2[3].predicted_pc.bits
connect loop.io.resp_in[0].f2[3].predicted_pc.valid, tage.io.resp.f2[3].predicted_pc.valid
connect loop.io.resp_in[0].f2[3].is_jal, tage.io.resp.f2[3].is_jal
connect loop.io.resp_in[0].f2[3].is_br, tage.io.resp.f2[3].is_br
connect loop.io.resp_in[0].f2[3].taken, tage.io.resp.f2[3].taken
connect loop.io.resp_in[0].f1[0].predicted_pc.bits, tage.io.resp.f1[0].predicted_pc.bits
connect loop.io.resp_in[0].f1[0].predicted_pc.valid, tage.io.resp.f1[0].predicted_pc.valid
connect loop.io.resp_in[0].f1[0].is_jal, tage.io.resp.f1[0].is_jal
connect loop.io.resp_in[0].f1[0].is_br, tage.io.resp.f1[0].is_br
connect loop.io.resp_in[0].f1[0].taken, tage.io.resp.f1[0].taken
connect loop.io.resp_in[0].f1[1].predicted_pc.bits, tage.io.resp.f1[1].predicted_pc.bits
connect loop.io.resp_in[0].f1[1].predicted_pc.valid, tage.io.resp.f1[1].predicted_pc.valid
connect loop.io.resp_in[0].f1[1].is_jal, tage.io.resp.f1[1].is_jal
connect loop.io.resp_in[0].f1[1].is_br, tage.io.resp.f1[1].is_br
connect loop.io.resp_in[0].f1[1].taken, tage.io.resp.f1[1].taken
connect loop.io.resp_in[0].f1[2].predicted_pc.bits, tage.io.resp.f1[2].predicted_pc.bits
connect loop.io.resp_in[0].f1[2].predicted_pc.valid, tage.io.resp.f1[2].predicted_pc.valid
connect loop.io.resp_in[0].f1[2].is_jal, tage.io.resp.f1[2].is_jal
connect loop.io.resp_in[0].f1[2].is_br, tage.io.resp.f1[2].is_br
connect loop.io.resp_in[0].f1[2].taken, tage.io.resp.f1[2].taken
connect loop.io.resp_in[0].f1[3].predicted_pc.bits, tage.io.resp.f1[3].predicted_pc.bits
connect loop.io.resp_in[0].f1[3].predicted_pc.valid, tage.io.resp.f1[3].predicted_pc.valid
connect loop.io.resp_in[0].f1[3].is_jal, tage.io.resp.f1[3].is_jal
connect loop.io.resp_in[0].f1[3].is_br, tage.io.resp.f1[3].is_br
connect loop.io.resp_in[0].f1[3].taken, tage.io.resp.f1[3].taken
connect io.resp, loop.io.resp
connect loop.io.f0_valid, io.f0_valid
connect loop.io.f0_pc, io.f0_pc
connect loop.io.f0_mask, io.f0_mask
connect loop.io.f1_ghist, io.f1_ghist
connect loop.io.f1_lhist, io.f1_lhist
connect loop.io.f3_fire, io.f3_fire
node _T = shl(UInt<1>(0h0), 40)
node _T_1 = bits(loop.io.f3_meta, 39, 0)
node _T_2 = or(_T, _T_1)
connect tage.io.f0_valid, io.f0_valid
connect tage.io.f0_pc, io.f0_pc
connect tage.io.f0_mask, io.f0_mask
connect tage.io.f1_ghist, io.f1_ghist
connect tage.io.f1_lhist, io.f1_lhist
connect tage.io.f3_fire, io.f3_fire
node _T_3 = shl(_T_2, 56)
node _T_4 = bits(tage.io.f3_meta, 55, 0)
node _T_5 = or(_T_3, _T_4)
connect btb.io.f0_valid, io.f0_valid
connect btb.io.f0_pc, io.f0_pc
connect btb.io.f0_mask, io.f0_mask
connect btb.io.f1_ghist, io.f1_ghist
connect btb.io.f1_lhist, io.f1_lhist
connect btb.io.f3_fire, io.f3_fire
node _T_6 = shl(_T_5, 1)
node _T_7 = bits(btb.io.f3_meta, 0, 0)
node _T_8 = or(_T_6, _T_7)
connect ubtb.io.f0_valid, io.f0_valid
connect ubtb.io.f0_pc, io.f0_pc
connect ubtb.io.f0_mask, io.f0_mask
connect ubtb.io.f1_ghist, io.f1_ghist
connect ubtb.io.f1_lhist, io.f1_lhist
connect ubtb.io.f3_fire, io.f3_fire
node _T_9 = shl(_T_8, 8)
node _T_10 = bits(ubtb.io.f3_meta, 7, 0)
node _T_11 = or(_T_9, _T_10)
connect bim.io.f0_valid, io.f0_valid
connect bim.io.f0_pc, io.f0_pc
connect bim.io.f0_mask, io.f0_mask
connect bim.io.f1_ghist, io.f1_ghist
connect bim.io.f1_lhist, io.f1_lhist
connect bim.io.f3_fire, io.f3_fire
node _T_12 = shl(_T_11, 8)
node _T_13 = bits(bim.io.f3_meta, 7, 0)
node _T_14 = or(_T_12, _T_13)
connect io.f3_meta, _T_14
connect bim.io.update.bits.meta, io.update.bits.meta
connect bim.io.update.bits.target, io.update.bits.target
connect bim.io.update.bits.lhist, io.update.bits.lhist
connect bim.io.update.bits.ghist, io.update.bits.ghist
connect bim.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect bim.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect bim.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect bim.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect bim.io.update.bits.cfi_taken, io.update.bits.cfi_taken
connect bim.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect bim.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect bim.io.update.bits.br_mask, io.update.bits.br_mask
connect bim.io.update.bits.pc, io.update.bits.pc
connect bim.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect bim.io.update.bits.is_repair_update, io.update.bits.is_repair_update
connect bim.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect bim.io.update.valid, io.update.valid
connect bim.io.update.bits.meta, io.update.bits.meta
node _T_15 = shr(io.update.bits.meta, 8)
connect ubtb.io.update.bits.meta, io.update.bits.meta
connect ubtb.io.update.bits.target, io.update.bits.target
connect ubtb.io.update.bits.lhist, io.update.bits.lhist
connect ubtb.io.update.bits.ghist, io.update.bits.ghist
connect ubtb.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect ubtb.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect ubtb.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect ubtb.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect ubtb.io.update.bits.cfi_taken, io.update.bits.cfi_taken
connect ubtb.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect ubtb.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect ubtb.io.update.bits.br_mask, io.update.bits.br_mask
connect ubtb.io.update.bits.pc, io.update.bits.pc
connect ubtb.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect ubtb.io.update.bits.is_repair_update, io.update.bits.is_repair_update
connect ubtb.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect ubtb.io.update.valid, io.update.valid
connect ubtb.io.update.bits.meta, _T_15
node _T_16 = shr(_T_15, 8)
connect btb.io.update.bits.meta, io.update.bits.meta
connect btb.io.update.bits.target, io.update.bits.target
connect btb.io.update.bits.lhist, io.update.bits.lhist
connect btb.io.update.bits.ghist, io.update.bits.ghist
connect btb.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect btb.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect btb.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect btb.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect btb.io.update.bits.cfi_taken, io.update.bits.cfi_taken
connect btb.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect btb.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect btb.io.update.bits.br_mask, io.update.bits.br_mask
connect btb.io.update.bits.pc, io.update.bits.pc
connect btb.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect btb.io.update.bits.is_repair_update, io.update.bits.is_repair_update
connect btb.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect btb.io.update.valid, io.update.valid
connect btb.io.update.bits.meta, _T_16
node _T_17 = shr(_T_16, 1)
connect tage.io.update.bits.meta, io.update.bits.meta
connect tage.io.update.bits.target, io.update.bits.target
connect tage.io.update.bits.lhist, io.update.bits.lhist
connect tage.io.update.bits.ghist, io.update.bits.ghist
connect tage.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect tage.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect tage.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect tage.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect tage.io.update.bits.cfi_taken, io.update.bits.cfi_taken
connect tage.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect tage.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect tage.io.update.bits.br_mask, io.update.bits.br_mask
connect tage.io.update.bits.pc, io.update.bits.pc
connect tage.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect tage.io.update.bits.is_repair_update, io.update.bits.is_repair_update
connect tage.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect tage.io.update.valid, io.update.valid
connect tage.io.update.bits.meta, _T_17
node _T_18 = shr(_T_17, 56)
connect loop.io.update.bits.meta, io.update.bits.meta
connect loop.io.update.bits.target, io.update.bits.target
connect loop.io.update.bits.lhist, io.update.bits.lhist
connect loop.io.update.bits.ghist, io.update.bits.ghist
connect loop.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect loop.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect loop.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect loop.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect loop.io.update.bits.cfi_taken, io.update.bits.cfi_taken
connect loop.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect loop.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect loop.io.update.bits.br_mask, io.update.bits.br_mask
connect loop.io.update.bits.pc, io.update.bits.pc
connect loop.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect loop.io.update.bits.is_repair_update, io.update.bits.is_repair_update
connect loop.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect loop.io.update.valid, io.update.valid
connect loop.io.update.bits.meta, _T_18
node _T_19 = shr(_T_18, 40) | module ComposedBranchPredictorBank_3( // @[composer.scala:14:7]
input clock, // @[composer.scala:14:7]
input reset, // @[composer.scala:14:7]
input io_f0_valid, // @[predictor.scala:140:14]
input [39:0] io_f0_pc, // @[predictor.scala:140:14]
input [3:0] io_f0_mask, // @[predictor.scala:140:14]
input [63:0] io_f1_ghist, // @[predictor.scala:140:14]
output io_resp_f1_0_taken, // @[predictor.scala:140:14]
output io_resp_f1_0_is_br, // @[predictor.scala:140:14]
output io_resp_f1_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_1_taken, // @[predictor.scala:140:14]
output io_resp_f1_1_is_br, // @[predictor.scala:140:14]
output io_resp_f1_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_2_taken, // @[predictor.scala:140:14]
output io_resp_f1_2_is_br, // @[predictor.scala:140:14]
output io_resp_f1_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_3_taken, // @[predictor.scala:140:14]
output io_resp_f1_3_is_br, // @[predictor.scala:140:14]
output io_resp_f1_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_0_taken, // @[predictor.scala:140:14]
output io_resp_f2_0_is_br, // @[predictor.scala:140:14]
output io_resp_f2_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_1_taken, // @[predictor.scala:140:14]
output io_resp_f2_1_is_br, // @[predictor.scala:140:14]
output io_resp_f2_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_2_taken, // @[predictor.scala:140:14]
output io_resp_f2_2_is_br, // @[predictor.scala:140:14]
output io_resp_f2_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_3_taken, // @[predictor.scala:140:14]
output io_resp_f2_3_is_br, // @[predictor.scala:140:14]
output io_resp_f2_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_0_taken, // @[predictor.scala:140:14]
output io_resp_f3_0_is_br, // @[predictor.scala:140:14]
output io_resp_f3_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_1_taken, // @[predictor.scala:140:14]
output io_resp_f3_1_is_br, // @[predictor.scala:140:14]
output io_resp_f3_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_2_taken, // @[predictor.scala:140:14]
output io_resp_f3_2_is_br, // @[predictor.scala:140:14]
output io_resp_f3_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_3_taken, // @[predictor.scala:140:14]
output io_resp_f3_3_is_br, // @[predictor.scala:140:14]
output io_resp_f3_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14]
output [119:0] io_f3_meta, // @[predictor.scala:140:14]
input io_f3_fire, // @[predictor.scala:140:14]
input io_update_valid, // @[predictor.scala:140:14]
input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14]
input io_update_bits_is_repair_update, // @[predictor.scala:140:14]
input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14]
input [39:0] io_update_bits_pc, // @[predictor.scala:140:14]
input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14]
input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14]
input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14]
input io_update_bits_cfi_taken, // @[predictor.scala:140:14]
input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_br, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14]
input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14]
input io_update_bits_lhist, // @[predictor.scala:140:14]
input [39:0] io_update_bits_target, // @[predictor.scala:140:14]
input [119:0] io_update_bits_meta // @[predictor.scala:140:14]
);
wire _ubtb_io_resp_f1_0_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_0_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_0_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_1_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_1_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_1_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_2_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_2_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_2_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_3_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_3_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_3_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_0_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_0_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_0_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_1_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_1_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_1_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_2_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_2_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_2_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_3_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_3_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_3_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_0_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_0_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_0_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_1_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_1_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_1_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_2_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_2_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_2_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_3_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_3_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_3_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire [119:0] _ubtb_io_f3_meta; // @[config-mixins.scala:449:26]
wire _bim_io_resp_f1_0_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_0_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_0_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_1_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_1_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_1_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_2_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_2_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_2_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_3_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_3_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_3_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_0_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_0_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_0_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_1_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_1_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_1_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_2_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_2_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_2_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_3_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_3_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_3_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_0_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_0_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_0_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_1_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_1_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_1_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_2_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_2_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_2_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_3_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_3_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_3_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire [119:0] _bim_io_f3_meta; // @[config-mixins.scala:448:25]
wire _btb_io_resp_f1_0_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_0_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_0_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_1_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_1_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_1_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_2_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_2_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_2_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_3_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_3_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_3_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_0_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_0_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_0_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_1_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_1_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_1_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_2_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_2_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_2_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_3_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_3_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_3_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_0_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_0_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_0_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_1_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_1_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_1_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_2_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_2_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_2_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_3_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_3_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_3_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire [119:0] _btb_io_f3_meta; // @[config-mixins.scala:447:25]
wire _tage_io_resp_f1_0_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_0_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_0_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_1_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_1_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_1_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_2_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_2_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_2_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_3_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_3_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_3_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_0_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_0_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_0_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_1_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_1_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_1_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_2_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_2_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_2_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_3_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_3_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_3_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_0_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_0_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_0_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_1_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_1_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_1_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_2_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_2_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_2_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_3_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_3_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_3_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire [119:0] _tage_io_f3_meta; // @[config-mixins.scala:446:26]
wire [119:0] _loop_io_f3_meta; // @[config-mixins.scala:445:26]
wire io_f0_valid_0 = io_f0_valid; // @[composer.scala:14:7]
wire [39:0] io_f0_pc_0 = io_f0_pc; // @[composer.scala:14:7]
wire [3:0] io_f0_mask_0 = io_f0_mask; // @[composer.scala:14:7]
wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[composer.scala:14:7]
wire io_f3_fire_0 = io_f3_fire; // @[composer.scala:14:7]
wire io_update_valid_0 = io_update_valid; // @[composer.scala:14:7]
wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[composer.scala:14:7]
wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[composer.scala:14:7]
wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[composer.scala:14:7]
wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[composer.scala:14:7]
wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[composer.scala:14:7]
wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[composer.scala:14:7]
wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[composer.scala:14:7]
wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[composer.scala:14:7]
wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[composer.scala:14:7]
wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[composer.scala:14:7]
wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[composer.scala:14:7]
wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[composer.scala:14:7]
wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[composer.scala:14:7]
wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[composer.scala:14:7]
wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[composer.scala:14:7]
wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[composer.scala:14:7]
wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire io_f1_lhist = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_0_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_0_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_0_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_1_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_1_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_1_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_2_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_2_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_2_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_3_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_3_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_3_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_0_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_0_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_0_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_1_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_1_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_1_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_2_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_2_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_2_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_3_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_3_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_3_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_0_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_0_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_0_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_1_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_1_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_1_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_2_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_2_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_2_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_3_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_3_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_3_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_f1_0_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f1_0_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f1_0_taken_0; // @[composer.scala:14:7]
wire io_resp_f1_0_is_br_0; // @[composer.scala:14:7]
wire io_resp_f1_0_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f1_1_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f1_1_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f1_1_taken_0; // @[composer.scala:14:7]
wire io_resp_f1_1_is_br_0; // @[composer.scala:14:7]
wire io_resp_f1_1_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f1_2_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f1_2_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f1_2_taken_0; // @[composer.scala:14:7]
wire io_resp_f1_2_is_br_0; // @[composer.scala:14:7]
wire io_resp_f1_2_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f1_3_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f1_3_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f1_3_taken_0; // @[composer.scala:14:7]
wire io_resp_f1_3_is_br_0; // @[composer.scala:14:7]
wire io_resp_f1_3_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f2_0_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f2_0_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f2_0_taken_0; // @[composer.scala:14:7]
wire io_resp_f2_0_is_br_0; // @[composer.scala:14:7]
wire io_resp_f2_0_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f2_1_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f2_1_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f2_1_taken_0; // @[composer.scala:14:7]
wire io_resp_f2_1_is_br_0; // @[composer.scala:14:7]
wire io_resp_f2_1_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f2_2_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f2_2_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f2_2_taken_0; // @[composer.scala:14:7]
wire io_resp_f2_2_is_br_0; // @[composer.scala:14:7]
wire io_resp_f2_2_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f2_3_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f2_3_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f2_3_taken_0; // @[composer.scala:14:7]
wire io_resp_f2_3_is_br_0; // @[composer.scala:14:7]
wire io_resp_f2_3_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f3_0_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f3_0_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f3_0_taken_0; // @[composer.scala:14:7]
wire io_resp_f3_0_is_br_0; // @[composer.scala:14:7]
wire io_resp_f3_0_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f3_1_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f3_1_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f3_1_taken_0; // @[composer.scala:14:7]
wire io_resp_f3_1_is_br_0; // @[composer.scala:14:7]
wire io_resp_f3_1_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f3_2_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f3_2_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f3_2_taken_0; // @[composer.scala:14:7]
wire io_resp_f3_2_is_br_0; // @[composer.scala:14:7]
wire io_resp_f3_2_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f3_3_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f3_3_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f3_3_taken_0; // @[composer.scala:14:7]
wire io_resp_f3_3_is_br_0; // @[composer.scala:14:7]
wire io_resp_f3_3_is_jal_0; // @[composer.scala:14:7]
wire [119:0] io_f3_meta_0; // @[composer.scala:14:7]
wire [35:0] s0_idx = io_f0_pc_0[39:4]; // @[frontend.scala:162:35]
reg [35:0] s1_idx; // @[predictor.scala:163:29]
reg [35:0] s2_idx; // @[predictor.scala:164:29]
reg [35:0] s3_idx; // @[predictor.scala:165:29]
reg s1_valid; // @[predictor.scala:168:25]
reg s2_valid; // @[predictor.scala:169:25]
reg s3_valid; // @[predictor.scala:170:25]
reg [3:0] s1_mask; // @[predictor.scala:173:24]
reg [3:0] s2_mask; // @[predictor.scala:174:24]
reg [3:0] s3_mask; // @[predictor.scala:175:24]
reg [39:0] s1_pc; // @[predictor.scala:178:22]
wire [35:0] s0_update_idx = io_update_bits_pc_0[39:4]; // @[frontend.scala:162:35]
reg s1_update_valid; // @[predictor.scala:184:30]
reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30]
reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30]
reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30]
reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30]
reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30]
reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30]
reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30]
reg s1_update_bits_lhist; // @[predictor.scala:184:30]
reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30]
reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30]
reg [35:0] s1_update_idx; // @[predictor.scala:185:30]
reg s1_update_valid_0; // @[predictor.scala:186:32]
assign io_f3_meta_0 = {7'h0, _loop_io_f3_meta[39:0], _tage_io_f3_meta[55:0], _btb_io_f3_meta[0], _ubtb_io_f3_meta[7:0], _bim_io_f3_meta[7:0]}; // @[composer.scala:14:7, :31:49, :36:14]
always @(posedge clock) begin // @[composer.scala:14:7]
s1_idx <= s0_idx; // @[frontend.scala:162:35]
s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29]
s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29]
s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25]
s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25]
s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25]
s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24]
s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24]
s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24]
s1_pc <= io_f0_pc_0; // @[predictor.scala:178:22]
s1_update_valid <= io_update_valid_0; // @[predictor.scala:184:30]
s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:184:30]
s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:184:30]
s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:184:30]
s1_update_bits_pc <= io_update_bits_pc_0; // @[predictor.scala:184:30]
s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:184:30]
s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:184:30]
s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:184:30]
s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:184:30]
s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:184:30]
s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35]
s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:186:32]
always @(posedge)
LoopBranchPredictorBank_3 loop ( // @[config-mixins.scala:445:26]
.clock (clock),
.reset (reset),
.io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7]
.io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7]
.io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7]
.io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7]
.io_resp_in_0_f1_0_taken (_tage_io_resp_f1_0_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_0_is_br (_tage_io_resp_f1_0_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_0_is_jal (_tage_io_resp_f1_0_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_0_predicted_pc_valid (_tage_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_0_predicted_pc_bits (_tage_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_1_taken (_tage_io_resp_f1_1_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_1_is_br (_tage_io_resp_f1_1_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_1_is_jal (_tage_io_resp_f1_1_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_1_predicted_pc_valid (_tage_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_1_predicted_pc_bits (_tage_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_2_taken (_tage_io_resp_f1_2_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_2_is_br (_tage_io_resp_f1_2_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_2_is_jal (_tage_io_resp_f1_2_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_2_predicted_pc_valid (_tage_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_2_predicted_pc_bits (_tage_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_3_taken (_tage_io_resp_f1_3_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_3_is_br (_tage_io_resp_f1_3_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_3_is_jal (_tage_io_resp_f1_3_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_3_predicted_pc_valid (_tage_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_3_predicted_pc_bits (_tage_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_0_taken (_tage_io_resp_f2_0_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_0_is_br (_tage_io_resp_f2_0_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_0_is_jal (_tage_io_resp_f2_0_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_0_predicted_pc_valid (_tage_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_0_predicted_pc_bits (_tage_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_1_taken (_tage_io_resp_f2_1_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_1_is_br (_tage_io_resp_f2_1_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_1_is_jal (_tage_io_resp_f2_1_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_1_predicted_pc_valid (_tage_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_1_predicted_pc_bits (_tage_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_2_taken (_tage_io_resp_f2_2_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_2_is_br (_tage_io_resp_f2_2_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_2_is_jal (_tage_io_resp_f2_2_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_2_predicted_pc_valid (_tage_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_2_predicted_pc_bits (_tage_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_3_taken (_tage_io_resp_f2_3_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_3_is_br (_tage_io_resp_f2_3_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_3_is_jal (_tage_io_resp_f2_3_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_3_predicted_pc_valid (_tage_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_3_predicted_pc_bits (_tage_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_0_taken (_tage_io_resp_f3_0_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_0_is_br (_tage_io_resp_f3_0_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_0_is_jal (_tage_io_resp_f3_0_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_0_predicted_pc_valid (_tage_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_0_predicted_pc_bits (_tage_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_1_taken (_tage_io_resp_f3_1_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_1_is_br (_tage_io_resp_f3_1_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_1_is_jal (_tage_io_resp_f3_1_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_1_predicted_pc_valid (_tage_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_1_predicted_pc_bits (_tage_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_2_taken (_tage_io_resp_f3_2_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_2_is_br (_tage_io_resp_f3_2_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_2_is_jal (_tage_io_resp_f3_2_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_2_predicted_pc_valid (_tage_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_2_predicted_pc_bits (_tage_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_3_taken (_tage_io_resp_f3_3_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_3_is_br (_tage_io_resp_f3_3_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_3_is_jal (_tage_io_resp_f3_3_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_3_predicted_pc_valid (_tage_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_3_predicted_pc_bits (_tage_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_f1_0_taken (io_resp_f1_0_taken_0),
.io_resp_f1_0_is_br (io_resp_f1_0_is_br_0),
.io_resp_f1_0_is_jal (io_resp_f1_0_is_jal_0),
.io_resp_f1_0_predicted_pc_valid (io_resp_f1_0_predicted_pc_valid_0),
.io_resp_f1_0_predicted_pc_bits (io_resp_f1_0_predicted_pc_bits_0),
.io_resp_f1_1_taken (io_resp_f1_1_taken_0),
.io_resp_f1_1_is_br (io_resp_f1_1_is_br_0),
.io_resp_f1_1_is_jal (io_resp_f1_1_is_jal_0),
.io_resp_f1_1_predicted_pc_valid (io_resp_f1_1_predicted_pc_valid_0),
.io_resp_f1_1_predicted_pc_bits (io_resp_f1_1_predicted_pc_bits_0),
.io_resp_f1_2_taken (io_resp_f1_2_taken_0),
.io_resp_f1_2_is_br (io_resp_f1_2_is_br_0),
.io_resp_f1_2_is_jal (io_resp_f1_2_is_jal_0),
.io_resp_f1_2_predicted_pc_valid (io_resp_f1_2_predicted_pc_valid_0),
.io_resp_f1_2_predicted_pc_bits (io_resp_f1_2_predicted_pc_bits_0),
.io_resp_f1_3_taken (io_resp_f1_3_taken_0),
.io_resp_f1_3_is_br (io_resp_f1_3_is_br_0),
.io_resp_f1_3_is_jal (io_resp_f1_3_is_jal_0),
.io_resp_f1_3_predicted_pc_valid (io_resp_f1_3_predicted_pc_valid_0),
.io_resp_f1_3_predicted_pc_bits (io_resp_f1_3_predicted_pc_bits_0),
.io_resp_f2_0_taken (io_resp_f2_0_taken_0),
.io_resp_f2_0_is_br (io_resp_f2_0_is_br_0),
.io_resp_f2_0_is_jal (io_resp_f2_0_is_jal_0),
.io_resp_f2_0_predicted_pc_valid (io_resp_f2_0_predicted_pc_valid_0),
.io_resp_f2_0_predicted_pc_bits (io_resp_f2_0_predicted_pc_bits_0),
.io_resp_f2_1_taken (io_resp_f2_1_taken_0),
.io_resp_f2_1_is_br (io_resp_f2_1_is_br_0),
.io_resp_f2_1_is_jal (io_resp_f2_1_is_jal_0),
.io_resp_f2_1_predicted_pc_valid (io_resp_f2_1_predicted_pc_valid_0),
.io_resp_f2_1_predicted_pc_bits (io_resp_f2_1_predicted_pc_bits_0),
.io_resp_f2_2_taken (io_resp_f2_2_taken_0),
.io_resp_f2_2_is_br (io_resp_f2_2_is_br_0),
.io_resp_f2_2_is_jal (io_resp_f2_2_is_jal_0),
.io_resp_f2_2_predicted_pc_valid (io_resp_f2_2_predicted_pc_valid_0),
.io_resp_f2_2_predicted_pc_bits (io_resp_f2_2_predicted_pc_bits_0),
.io_resp_f2_3_taken (io_resp_f2_3_taken_0),
.io_resp_f2_3_is_br (io_resp_f2_3_is_br_0),
.io_resp_f2_3_is_jal (io_resp_f2_3_is_jal_0),
.io_resp_f2_3_predicted_pc_valid (io_resp_f2_3_predicted_pc_valid_0),
.io_resp_f2_3_predicted_pc_bits (io_resp_f2_3_predicted_pc_bits_0),
.io_resp_f3_0_taken (io_resp_f3_0_taken_0),
.io_resp_f3_0_is_br (io_resp_f3_0_is_br_0),
.io_resp_f3_0_is_jal (io_resp_f3_0_is_jal_0),
.io_resp_f3_0_predicted_pc_valid (io_resp_f3_0_predicted_pc_valid_0),
.io_resp_f3_0_predicted_pc_bits (io_resp_f3_0_predicted_pc_bits_0),
.io_resp_f3_1_taken (io_resp_f3_1_taken_0),
.io_resp_f3_1_is_br (io_resp_f3_1_is_br_0),
.io_resp_f3_1_is_jal (io_resp_f3_1_is_jal_0),
.io_resp_f3_1_predicted_pc_valid (io_resp_f3_1_predicted_pc_valid_0),
.io_resp_f3_1_predicted_pc_bits (io_resp_f3_1_predicted_pc_bits_0),
.io_resp_f3_2_taken (io_resp_f3_2_taken_0),
.io_resp_f3_2_is_br (io_resp_f3_2_is_br_0),
.io_resp_f3_2_is_jal (io_resp_f3_2_is_jal_0),
.io_resp_f3_2_predicted_pc_valid (io_resp_f3_2_predicted_pc_valid_0),
.io_resp_f3_2_predicted_pc_bits (io_resp_f3_2_predicted_pc_bits_0),
.io_resp_f3_3_taken (io_resp_f3_3_taken_0),
.io_resp_f3_3_is_br (io_resp_f3_3_is_br_0),
.io_resp_f3_3_is_jal (io_resp_f3_3_is_jal_0),
.io_resp_f3_3_predicted_pc_valid (io_resp_f3_3_predicted_pc_valid_0),
.io_resp_f3_3_predicted_pc_bits (io_resp_f3_3_predicted_pc_bits_0),
.io_f3_meta (_loop_io_f3_meta),
.io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7]
.io_update_valid (io_update_valid_0), // @[composer.scala:14:7]
.io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7]
.io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7]
.io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7]
.io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7]
.io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7]
.io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7]
.io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7]
.io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7]
.io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7]
.io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7]
.io_update_bits_meta ({73'h0, io_update_bits_meta_0[119:73]}) // @[composer.scala:14:7, :42:27, :43:31]
); // @[config-mixins.scala:445:26]
TageBranchPredictorBank_3 tage ( // @[config-mixins.scala:446:26]
.clock (clock),
.reset (reset),
.io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7]
.io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7]
.io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7]
.io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7]
.io_resp_in_0_f1_0_taken (_btb_io_resp_f1_0_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_0_is_br (_btb_io_resp_f1_0_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_0_is_jal (_btb_io_resp_f1_0_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_0_predicted_pc_valid (_btb_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_0_predicted_pc_bits (_btb_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_1_taken (_btb_io_resp_f1_1_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_1_is_br (_btb_io_resp_f1_1_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_1_is_jal (_btb_io_resp_f1_1_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_1_predicted_pc_valid (_btb_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_1_predicted_pc_bits (_btb_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_2_taken (_btb_io_resp_f1_2_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_2_is_br (_btb_io_resp_f1_2_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_2_is_jal (_btb_io_resp_f1_2_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_2_predicted_pc_valid (_btb_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_2_predicted_pc_bits (_btb_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_3_taken (_btb_io_resp_f1_3_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_3_is_br (_btb_io_resp_f1_3_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_3_is_jal (_btb_io_resp_f1_3_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_3_predicted_pc_valid (_btb_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_3_predicted_pc_bits (_btb_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_0_taken (_btb_io_resp_f2_0_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_0_is_br (_btb_io_resp_f2_0_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_0_is_jal (_btb_io_resp_f2_0_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_0_predicted_pc_valid (_btb_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_0_predicted_pc_bits (_btb_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_1_taken (_btb_io_resp_f2_1_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_1_is_br (_btb_io_resp_f2_1_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_1_is_jal (_btb_io_resp_f2_1_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_1_predicted_pc_valid (_btb_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_1_predicted_pc_bits (_btb_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_2_taken (_btb_io_resp_f2_2_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_2_is_br (_btb_io_resp_f2_2_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_2_is_jal (_btb_io_resp_f2_2_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_2_predicted_pc_valid (_btb_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_2_predicted_pc_bits (_btb_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_3_taken (_btb_io_resp_f2_3_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_3_is_br (_btb_io_resp_f2_3_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_3_is_jal (_btb_io_resp_f2_3_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_3_predicted_pc_valid (_btb_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_3_predicted_pc_bits (_btb_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_0_taken (_btb_io_resp_f3_0_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_0_is_br (_btb_io_resp_f3_0_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_0_is_jal (_btb_io_resp_f3_0_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_0_predicted_pc_valid (_btb_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_0_predicted_pc_bits (_btb_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_1_taken (_btb_io_resp_f3_1_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_1_is_br (_btb_io_resp_f3_1_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_1_is_jal (_btb_io_resp_f3_1_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_1_predicted_pc_valid (_btb_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_1_predicted_pc_bits (_btb_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_2_taken (_btb_io_resp_f3_2_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_2_is_br (_btb_io_resp_f3_2_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_2_is_jal (_btb_io_resp_f3_2_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_2_predicted_pc_valid (_btb_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_2_predicted_pc_bits (_btb_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_3_taken (_btb_io_resp_f3_3_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_3_is_br (_btb_io_resp_f3_3_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_3_is_jal (_btb_io_resp_f3_3_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_3_predicted_pc_valid (_btb_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_3_predicted_pc_bits (_btb_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_f1_0_taken (_tage_io_resp_f1_0_taken),
.io_resp_f1_0_is_br (_tage_io_resp_f1_0_is_br),
.io_resp_f1_0_is_jal (_tage_io_resp_f1_0_is_jal),
.io_resp_f1_0_predicted_pc_valid (_tage_io_resp_f1_0_predicted_pc_valid),
.io_resp_f1_0_predicted_pc_bits (_tage_io_resp_f1_0_predicted_pc_bits),
.io_resp_f1_1_taken (_tage_io_resp_f1_1_taken),
.io_resp_f1_1_is_br (_tage_io_resp_f1_1_is_br),
.io_resp_f1_1_is_jal (_tage_io_resp_f1_1_is_jal),
.io_resp_f1_1_predicted_pc_valid (_tage_io_resp_f1_1_predicted_pc_valid),
.io_resp_f1_1_predicted_pc_bits (_tage_io_resp_f1_1_predicted_pc_bits),
.io_resp_f1_2_taken (_tage_io_resp_f1_2_taken),
.io_resp_f1_2_is_br (_tage_io_resp_f1_2_is_br),
.io_resp_f1_2_is_jal (_tage_io_resp_f1_2_is_jal),
.io_resp_f1_2_predicted_pc_valid (_tage_io_resp_f1_2_predicted_pc_valid),
.io_resp_f1_2_predicted_pc_bits (_tage_io_resp_f1_2_predicted_pc_bits),
.io_resp_f1_3_taken (_tage_io_resp_f1_3_taken),
.io_resp_f1_3_is_br (_tage_io_resp_f1_3_is_br),
.io_resp_f1_3_is_jal (_tage_io_resp_f1_3_is_jal),
.io_resp_f1_3_predicted_pc_valid (_tage_io_resp_f1_3_predicted_pc_valid),
.io_resp_f1_3_predicted_pc_bits (_tage_io_resp_f1_3_predicted_pc_bits),
.io_resp_f2_0_taken (_tage_io_resp_f2_0_taken),
.io_resp_f2_0_is_br (_tage_io_resp_f2_0_is_br),
.io_resp_f2_0_is_jal (_tage_io_resp_f2_0_is_jal),
.io_resp_f2_0_predicted_pc_valid (_tage_io_resp_f2_0_predicted_pc_valid),
.io_resp_f2_0_predicted_pc_bits (_tage_io_resp_f2_0_predicted_pc_bits),
.io_resp_f2_1_taken (_tage_io_resp_f2_1_taken),
.io_resp_f2_1_is_br (_tage_io_resp_f2_1_is_br),
.io_resp_f2_1_is_jal (_tage_io_resp_f2_1_is_jal),
.io_resp_f2_1_predicted_pc_valid (_tage_io_resp_f2_1_predicted_pc_valid),
.io_resp_f2_1_predicted_pc_bits (_tage_io_resp_f2_1_predicted_pc_bits),
.io_resp_f2_2_taken (_tage_io_resp_f2_2_taken),
.io_resp_f2_2_is_br (_tage_io_resp_f2_2_is_br),
.io_resp_f2_2_is_jal (_tage_io_resp_f2_2_is_jal),
.io_resp_f2_2_predicted_pc_valid (_tage_io_resp_f2_2_predicted_pc_valid),
.io_resp_f2_2_predicted_pc_bits (_tage_io_resp_f2_2_predicted_pc_bits),
.io_resp_f2_3_taken (_tage_io_resp_f2_3_taken),
.io_resp_f2_3_is_br (_tage_io_resp_f2_3_is_br),
.io_resp_f2_3_is_jal (_tage_io_resp_f2_3_is_jal),
.io_resp_f2_3_predicted_pc_valid (_tage_io_resp_f2_3_predicted_pc_valid),
.io_resp_f2_3_predicted_pc_bits (_tage_io_resp_f2_3_predicted_pc_bits),
.io_resp_f3_0_taken (_tage_io_resp_f3_0_taken),
.io_resp_f3_0_is_br (_tage_io_resp_f3_0_is_br),
.io_resp_f3_0_is_jal (_tage_io_resp_f3_0_is_jal),
.io_resp_f3_0_predicted_pc_valid (_tage_io_resp_f3_0_predicted_pc_valid),
.io_resp_f3_0_predicted_pc_bits (_tage_io_resp_f3_0_predicted_pc_bits),
.io_resp_f3_1_taken (_tage_io_resp_f3_1_taken),
.io_resp_f3_1_is_br (_tage_io_resp_f3_1_is_br),
.io_resp_f3_1_is_jal (_tage_io_resp_f3_1_is_jal),
.io_resp_f3_1_predicted_pc_valid (_tage_io_resp_f3_1_predicted_pc_valid),
.io_resp_f3_1_predicted_pc_bits (_tage_io_resp_f3_1_predicted_pc_bits),
.io_resp_f3_2_taken (_tage_io_resp_f3_2_taken),
.io_resp_f3_2_is_br (_tage_io_resp_f3_2_is_br),
.io_resp_f3_2_is_jal (_tage_io_resp_f3_2_is_jal),
.io_resp_f3_2_predicted_pc_valid (_tage_io_resp_f3_2_predicted_pc_valid),
.io_resp_f3_2_predicted_pc_bits (_tage_io_resp_f3_2_predicted_pc_bits),
.io_resp_f3_3_taken (_tage_io_resp_f3_3_taken),
.io_resp_f3_3_is_br (_tage_io_resp_f3_3_is_br),
.io_resp_f3_3_is_jal (_tage_io_resp_f3_3_is_jal),
.io_resp_f3_3_predicted_pc_valid (_tage_io_resp_f3_3_predicted_pc_valid),
.io_resp_f3_3_predicted_pc_bits (_tage_io_resp_f3_3_predicted_pc_bits),
.io_f3_meta (_tage_io_f3_meta),
.io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7]
.io_update_valid (io_update_valid_0), // @[composer.scala:14:7]
.io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7]
.io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7]
.io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7]
.io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7]
.io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7]
.io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7]
.io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7]
.io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7]
.io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7]
.io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7]
.io_update_bits_meta ({17'h0, io_update_bits_meta_0[119:17]}) // @[composer.scala:14:7, :42:27, :43:31]
); // @[config-mixins.scala:446:26]
BTBBranchPredictorBank_3 btb ( // @[config-mixins.scala:447:25]
.clock (clock),
.reset (reset),
.io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7]
.io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7]
.io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7]
.io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7]
.io_resp_in_0_f1_0_taken (_bim_io_resp_f1_0_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_0_is_br (_bim_io_resp_f1_0_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_0_is_jal (_bim_io_resp_f1_0_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_0_predicted_pc_valid (_bim_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_0_predicted_pc_bits (_bim_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_1_taken (_bim_io_resp_f1_1_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_1_is_br (_bim_io_resp_f1_1_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_1_is_jal (_bim_io_resp_f1_1_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_1_predicted_pc_valid (_bim_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_1_predicted_pc_bits (_bim_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_2_taken (_bim_io_resp_f1_2_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_2_is_br (_bim_io_resp_f1_2_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_2_is_jal (_bim_io_resp_f1_2_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_2_predicted_pc_valid (_bim_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_2_predicted_pc_bits (_bim_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_3_taken (_bim_io_resp_f1_3_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_3_is_br (_bim_io_resp_f1_3_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_3_is_jal (_bim_io_resp_f1_3_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_3_predicted_pc_valid (_bim_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_3_predicted_pc_bits (_bim_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_0_taken (_bim_io_resp_f2_0_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_0_is_br (_bim_io_resp_f2_0_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_0_is_jal (_bim_io_resp_f2_0_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_0_predicted_pc_valid (_bim_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_0_predicted_pc_bits (_bim_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_1_taken (_bim_io_resp_f2_1_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_1_is_br (_bim_io_resp_f2_1_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_1_is_jal (_bim_io_resp_f2_1_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_1_predicted_pc_valid (_bim_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_1_predicted_pc_bits (_bim_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_2_taken (_bim_io_resp_f2_2_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_2_is_br (_bim_io_resp_f2_2_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_2_is_jal (_bim_io_resp_f2_2_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_2_predicted_pc_valid (_bim_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_2_predicted_pc_bits (_bim_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_3_taken (_bim_io_resp_f2_3_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_3_is_br (_bim_io_resp_f2_3_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_3_is_jal (_bim_io_resp_f2_3_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_3_predicted_pc_valid (_bim_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_3_predicted_pc_bits (_bim_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_0_taken (_bim_io_resp_f3_0_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_0_is_br (_bim_io_resp_f3_0_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_0_is_jal (_bim_io_resp_f3_0_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_0_predicted_pc_valid (_bim_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_0_predicted_pc_bits (_bim_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_1_taken (_bim_io_resp_f3_1_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_1_is_br (_bim_io_resp_f3_1_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_1_is_jal (_bim_io_resp_f3_1_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_1_predicted_pc_valid (_bim_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_1_predicted_pc_bits (_bim_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_2_taken (_bim_io_resp_f3_2_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_2_is_br (_bim_io_resp_f3_2_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_2_is_jal (_bim_io_resp_f3_2_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_2_predicted_pc_valid (_bim_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_2_predicted_pc_bits (_bim_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_3_taken (_bim_io_resp_f3_3_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_3_is_br (_bim_io_resp_f3_3_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_3_is_jal (_bim_io_resp_f3_3_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_3_predicted_pc_valid (_bim_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_3_predicted_pc_bits (_bim_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_f1_0_taken (_btb_io_resp_f1_0_taken),
.io_resp_f1_0_is_br (_btb_io_resp_f1_0_is_br),
.io_resp_f1_0_is_jal (_btb_io_resp_f1_0_is_jal),
.io_resp_f1_0_predicted_pc_valid (_btb_io_resp_f1_0_predicted_pc_valid),
.io_resp_f1_0_predicted_pc_bits (_btb_io_resp_f1_0_predicted_pc_bits),
.io_resp_f1_1_taken (_btb_io_resp_f1_1_taken),
.io_resp_f1_1_is_br (_btb_io_resp_f1_1_is_br),
.io_resp_f1_1_is_jal (_btb_io_resp_f1_1_is_jal),
.io_resp_f1_1_predicted_pc_valid (_btb_io_resp_f1_1_predicted_pc_valid),
.io_resp_f1_1_predicted_pc_bits (_btb_io_resp_f1_1_predicted_pc_bits),
.io_resp_f1_2_taken (_btb_io_resp_f1_2_taken),
.io_resp_f1_2_is_br (_btb_io_resp_f1_2_is_br),
.io_resp_f1_2_is_jal (_btb_io_resp_f1_2_is_jal),
.io_resp_f1_2_predicted_pc_valid (_btb_io_resp_f1_2_predicted_pc_valid),
.io_resp_f1_2_predicted_pc_bits (_btb_io_resp_f1_2_predicted_pc_bits),
.io_resp_f1_3_taken (_btb_io_resp_f1_3_taken),
.io_resp_f1_3_is_br (_btb_io_resp_f1_3_is_br),
.io_resp_f1_3_is_jal (_btb_io_resp_f1_3_is_jal),
.io_resp_f1_3_predicted_pc_valid (_btb_io_resp_f1_3_predicted_pc_valid),
.io_resp_f1_3_predicted_pc_bits (_btb_io_resp_f1_3_predicted_pc_bits),
.io_resp_f2_0_taken (_btb_io_resp_f2_0_taken),
.io_resp_f2_0_is_br (_btb_io_resp_f2_0_is_br),
.io_resp_f2_0_is_jal (_btb_io_resp_f2_0_is_jal),
.io_resp_f2_0_predicted_pc_valid (_btb_io_resp_f2_0_predicted_pc_valid),
.io_resp_f2_0_predicted_pc_bits (_btb_io_resp_f2_0_predicted_pc_bits),
.io_resp_f2_1_taken (_btb_io_resp_f2_1_taken),
.io_resp_f2_1_is_br (_btb_io_resp_f2_1_is_br),
.io_resp_f2_1_is_jal (_btb_io_resp_f2_1_is_jal),
.io_resp_f2_1_predicted_pc_valid (_btb_io_resp_f2_1_predicted_pc_valid),
.io_resp_f2_1_predicted_pc_bits (_btb_io_resp_f2_1_predicted_pc_bits),
.io_resp_f2_2_taken (_btb_io_resp_f2_2_taken),
.io_resp_f2_2_is_br (_btb_io_resp_f2_2_is_br),
.io_resp_f2_2_is_jal (_btb_io_resp_f2_2_is_jal),
.io_resp_f2_2_predicted_pc_valid (_btb_io_resp_f2_2_predicted_pc_valid),
.io_resp_f2_2_predicted_pc_bits (_btb_io_resp_f2_2_predicted_pc_bits),
.io_resp_f2_3_taken (_btb_io_resp_f2_3_taken),
.io_resp_f2_3_is_br (_btb_io_resp_f2_3_is_br),
.io_resp_f2_3_is_jal (_btb_io_resp_f2_3_is_jal),
.io_resp_f2_3_predicted_pc_valid (_btb_io_resp_f2_3_predicted_pc_valid),
.io_resp_f2_3_predicted_pc_bits (_btb_io_resp_f2_3_predicted_pc_bits),
.io_resp_f3_0_taken (_btb_io_resp_f3_0_taken),
.io_resp_f3_0_is_br (_btb_io_resp_f3_0_is_br),
.io_resp_f3_0_is_jal (_btb_io_resp_f3_0_is_jal),
.io_resp_f3_0_predicted_pc_valid (_btb_io_resp_f3_0_predicted_pc_valid),
.io_resp_f3_0_predicted_pc_bits (_btb_io_resp_f3_0_predicted_pc_bits),
.io_resp_f3_1_taken (_btb_io_resp_f3_1_taken),
.io_resp_f3_1_is_br (_btb_io_resp_f3_1_is_br),
.io_resp_f3_1_is_jal (_btb_io_resp_f3_1_is_jal),
.io_resp_f3_1_predicted_pc_valid (_btb_io_resp_f3_1_predicted_pc_valid),
.io_resp_f3_1_predicted_pc_bits (_btb_io_resp_f3_1_predicted_pc_bits),
.io_resp_f3_2_taken (_btb_io_resp_f3_2_taken),
.io_resp_f3_2_is_br (_btb_io_resp_f3_2_is_br),
.io_resp_f3_2_is_jal (_btb_io_resp_f3_2_is_jal),
.io_resp_f3_2_predicted_pc_valid (_btb_io_resp_f3_2_predicted_pc_valid),
.io_resp_f3_2_predicted_pc_bits (_btb_io_resp_f3_2_predicted_pc_bits),
.io_resp_f3_3_taken (_btb_io_resp_f3_3_taken),
.io_resp_f3_3_is_br (_btb_io_resp_f3_3_is_br),
.io_resp_f3_3_is_jal (_btb_io_resp_f3_3_is_jal),
.io_resp_f3_3_predicted_pc_valid (_btb_io_resp_f3_3_predicted_pc_valid),
.io_resp_f3_3_predicted_pc_bits (_btb_io_resp_f3_3_predicted_pc_bits),
.io_f3_meta (_btb_io_f3_meta),
.io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7]
.io_update_valid (io_update_valid_0), // @[composer.scala:14:7]
.io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7]
.io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7]
.io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7]
.io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7]
.io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7]
.io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7]
.io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7]
.io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7]
.io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7]
.io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7]
.io_update_bits_meta ({16'h0, io_update_bits_meta_0[119:16]}) // @[composer.scala:14:7, :42:27, :43:31]
); // @[config-mixins.scala:447:25]
BIMBranchPredictorBank_3 bim ( // @[config-mixins.scala:448:25]
.clock (clock),
.reset (reset),
.io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7]
.io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7]
.io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7]
.io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7]
.io_resp_in_0_f1_0_taken (_ubtb_io_resp_f1_0_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_0_is_br (_ubtb_io_resp_f1_0_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_0_is_jal (_ubtb_io_resp_f1_0_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_0_predicted_pc_valid (_ubtb_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_0_predicted_pc_bits (_ubtb_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_1_taken (_ubtb_io_resp_f1_1_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_1_is_br (_ubtb_io_resp_f1_1_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_1_is_jal (_ubtb_io_resp_f1_1_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_1_predicted_pc_valid (_ubtb_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_1_predicted_pc_bits (_ubtb_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_2_taken (_ubtb_io_resp_f1_2_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_2_is_br (_ubtb_io_resp_f1_2_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_2_is_jal (_ubtb_io_resp_f1_2_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_2_predicted_pc_valid (_ubtb_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_2_predicted_pc_bits (_ubtb_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_3_taken (_ubtb_io_resp_f1_3_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_3_is_br (_ubtb_io_resp_f1_3_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_3_is_jal (_ubtb_io_resp_f1_3_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_3_predicted_pc_valid (_ubtb_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_3_predicted_pc_bits (_ubtb_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_0_taken (_ubtb_io_resp_f2_0_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_0_is_br (_ubtb_io_resp_f2_0_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_0_is_jal (_ubtb_io_resp_f2_0_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_0_predicted_pc_valid (_ubtb_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_0_predicted_pc_bits (_ubtb_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_1_taken (_ubtb_io_resp_f2_1_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_1_is_br (_ubtb_io_resp_f2_1_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_1_is_jal (_ubtb_io_resp_f2_1_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_1_predicted_pc_valid (_ubtb_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_1_predicted_pc_bits (_ubtb_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_2_taken (_ubtb_io_resp_f2_2_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_2_is_br (_ubtb_io_resp_f2_2_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_2_is_jal (_ubtb_io_resp_f2_2_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_2_predicted_pc_valid (_ubtb_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_2_predicted_pc_bits (_ubtb_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_3_taken (_ubtb_io_resp_f2_3_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_3_is_br (_ubtb_io_resp_f2_3_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_3_is_jal (_ubtb_io_resp_f2_3_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_3_predicted_pc_valid (_ubtb_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_3_predicted_pc_bits (_ubtb_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_0_taken (_ubtb_io_resp_f3_0_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_0_is_br (_ubtb_io_resp_f3_0_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_0_is_jal (_ubtb_io_resp_f3_0_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_0_predicted_pc_valid (_ubtb_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_0_predicted_pc_bits (_ubtb_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_1_taken (_ubtb_io_resp_f3_1_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_1_is_br (_ubtb_io_resp_f3_1_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_1_is_jal (_ubtb_io_resp_f3_1_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_1_predicted_pc_valid (_ubtb_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_1_predicted_pc_bits (_ubtb_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_2_taken (_ubtb_io_resp_f3_2_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_2_is_br (_ubtb_io_resp_f3_2_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_2_is_jal (_ubtb_io_resp_f3_2_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_2_predicted_pc_valid (_ubtb_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_2_predicted_pc_bits (_ubtb_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_3_taken (_ubtb_io_resp_f3_3_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_3_is_br (_ubtb_io_resp_f3_3_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_3_is_jal (_ubtb_io_resp_f3_3_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_3_predicted_pc_valid (_ubtb_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_3_predicted_pc_bits (_ubtb_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_f1_0_taken (_bim_io_resp_f1_0_taken),
.io_resp_f1_0_is_br (_bim_io_resp_f1_0_is_br),
.io_resp_f1_0_is_jal (_bim_io_resp_f1_0_is_jal),
.io_resp_f1_0_predicted_pc_valid (_bim_io_resp_f1_0_predicted_pc_valid),
.io_resp_f1_0_predicted_pc_bits (_bim_io_resp_f1_0_predicted_pc_bits),
.io_resp_f1_1_taken (_bim_io_resp_f1_1_taken),
.io_resp_f1_1_is_br (_bim_io_resp_f1_1_is_br),
.io_resp_f1_1_is_jal (_bim_io_resp_f1_1_is_jal),
.io_resp_f1_1_predicted_pc_valid (_bim_io_resp_f1_1_predicted_pc_valid),
.io_resp_f1_1_predicted_pc_bits (_bim_io_resp_f1_1_predicted_pc_bits),
.io_resp_f1_2_taken (_bim_io_resp_f1_2_taken),
.io_resp_f1_2_is_br (_bim_io_resp_f1_2_is_br),
.io_resp_f1_2_is_jal (_bim_io_resp_f1_2_is_jal),
.io_resp_f1_2_predicted_pc_valid (_bim_io_resp_f1_2_predicted_pc_valid),
.io_resp_f1_2_predicted_pc_bits (_bim_io_resp_f1_2_predicted_pc_bits),
.io_resp_f1_3_taken (_bim_io_resp_f1_3_taken),
.io_resp_f1_3_is_br (_bim_io_resp_f1_3_is_br),
.io_resp_f1_3_is_jal (_bim_io_resp_f1_3_is_jal),
.io_resp_f1_3_predicted_pc_valid (_bim_io_resp_f1_3_predicted_pc_valid),
.io_resp_f1_3_predicted_pc_bits (_bim_io_resp_f1_3_predicted_pc_bits),
.io_resp_f2_0_taken (_bim_io_resp_f2_0_taken),
.io_resp_f2_0_is_br (_bim_io_resp_f2_0_is_br),
.io_resp_f2_0_is_jal (_bim_io_resp_f2_0_is_jal),
.io_resp_f2_0_predicted_pc_valid (_bim_io_resp_f2_0_predicted_pc_valid),
.io_resp_f2_0_predicted_pc_bits (_bim_io_resp_f2_0_predicted_pc_bits),
.io_resp_f2_1_taken (_bim_io_resp_f2_1_taken),
.io_resp_f2_1_is_br (_bim_io_resp_f2_1_is_br),
.io_resp_f2_1_is_jal (_bim_io_resp_f2_1_is_jal),
.io_resp_f2_1_predicted_pc_valid (_bim_io_resp_f2_1_predicted_pc_valid),
.io_resp_f2_1_predicted_pc_bits (_bim_io_resp_f2_1_predicted_pc_bits),
.io_resp_f2_2_taken (_bim_io_resp_f2_2_taken),
.io_resp_f2_2_is_br (_bim_io_resp_f2_2_is_br),
.io_resp_f2_2_is_jal (_bim_io_resp_f2_2_is_jal),
.io_resp_f2_2_predicted_pc_valid (_bim_io_resp_f2_2_predicted_pc_valid),
.io_resp_f2_2_predicted_pc_bits (_bim_io_resp_f2_2_predicted_pc_bits),
.io_resp_f2_3_taken (_bim_io_resp_f2_3_taken),
.io_resp_f2_3_is_br (_bim_io_resp_f2_3_is_br),
.io_resp_f2_3_is_jal (_bim_io_resp_f2_3_is_jal),
.io_resp_f2_3_predicted_pc_valid (_bim_io_resp_f2_3_predicted_pc_valid),
.io_resp_f2_3_predicted_pc_bits (_bim_io_resp_f2_3_predicted_pc_bits),
.io_resp_f3_0_taken (_bim_io_resp_f3_0_taken),
.io_resp_f3_0_is_br (_bim_io_resp_f3_0_is_br),
.io_resp_f3_0_is_jal (_bim_io_resp_f3_0_is_jal),
.io_resp_f3_0_predicted_pc_valid (_bim_io_resp_f3_0_predicted_pc_valid),
.io_resp_f3_0_predicted_pc_bits (_bim_io_resp_f3_0_predicted_pc_bits),
.io_resp_f3_1_taken (_bim_io_resp_f3_1_taken),
.io_resp_f3_1_is_br (_bim_io_resp_f3_1_is_br),
.io_resp_f3_1_is_jal (_bim_io_resp_f3_1_is_jal),
.io_resp_f3_1_predicted_pc_valid (_bim_io_resp_f3_1_predicted_pc_valid),
.io_resp_f3_1_predicted_pc_bits (_bim_io_resp_f3_1_predicted_pc_bits),
.io_resp_f3_2_taken (_bim_io_resp_f3_2_taken),
.io_resp_f3_2_is_br (_bim_io_resp_f3_2_is_br),
.io_resp_f3_2_is_jal (_bim_io_resp_f3_2_is_jal),
.io_resp_f3_2_predicted_pc_valid (_bim_io_resp_f3_2_predicted_pc_valid),
.io_resp_f3_2_predicted_pc_bits (_bim_io_resp_f3_2_predicted_pc_bits),
.io_resp_f3_3_taken (_bim_io_resp_f3_3_taken),
.io_resp_f3_3_is_br (_bim_io_resp_f3_3_is_br),
.io_resp_f3_3_is_jal (_bim_io_resp_f3_3_is_jal),
.io_resp_f3_3_predicted_pc_valid (_bim_io_resp_f3_3_predicted_pc_valid),
.io_resp_f3_3_predicted_pc_bits (_bim_io_resp_f3_3_predicted_pc_bits),
.io_f3_meta (_bim_io_f3_meta),
.io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7]
.io_update_valid (io_update_valid_0), // @[composer.scala:14:7]
.io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7]
.io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7]
.io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7]
.io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7]
.io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7]
.io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7]
.io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7]
.io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7]
.io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7]
.io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7]
.io_update_bits_meta (io_update_bits_meta_0) // @[composer.scala:14:7]
); // @[config-mixins.scala:448:25]
FAMicroBTBBranchPredictorBank_3 ubtb ( // @[config-mixins.scala:449:26]
.clock (clock),
.reset (reset),
.io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7]
.io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7]
.io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7]
.io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7]
.io_resp_f1_0_taken (_ubtb_io_resp_f1_0_taken),
.io_resp_f1_0_is_br (_ubtb_io_resp_f1_0_is_br),
.io_resp_f1_0_is_jal (_ubtb_io_resp_f1_0_is_jal),
.io_resp_f1_0_predicted_pc_valid (_ubtb_io_resp_f1_0_predicted_pc_valid),
.io_resp_f1_0_predicted_pc_bits (_ubtb_io_resp_f1_0_predicted_pc_bits),
.io_resp_f1_1_taken (_ubtb_io_resp_f1_1_taken),
.io_resp_f1_1_is_br (_ubtb_io_resp_f1_1_is_br),
.io_resp_f1_1_is_jal (_ubtb_io_resp_f1_1_is_jal),
.io_resp_f1_1_predicted_pc_valid (_ubtb_io_resp_f1_1_predicted_pc_valid),
.io_resp_f1_1_predicted_pc_bits (_ubtb_io_resp_f1_1_predicted_pc_bits),
.io_resp_f1_2_taken (_ubtb_io_resp_f1_2_taken),
.io_resp_f1_2_is_br (_ubtb_io_resp_f1_2_is_br),
.io_resp_f1_2_is_jal (_ubtb_io_resp_f1_2_is_jal),
.io_resp_f1_2_predicted_pc_valid (_ubtb_io_resp_f1_2_predicted_pc_valid),
.io_resp_f1_2_predicted_pc_bits (_ubtb_io_resp_f1_2_predicted_pc_bits),
.io_resp_f1_3_taken (_ubtb_io_resp_f1_3_taken),
.io_resp_f1_3_is_br (_ubtb_io_resp_f1_3_is_br),
.io_resp_f1_3_is_jal (_ubtb_io_resp_f1_3_is_jal),
.io_resp_f1_3_predicted_pc_valid (_ubtb_io_resp_f1_3_predicted_pc_valid),
.io_resp_f1_3_predicted_pc_bits (_ubtb_io_resp_f1_3_predicted_pc_bits),
.io_resp_f2_0_taken (_ubtb_io_resp_f2_0_taken),
.io_resp_f2_0_is_br (_ubtb_io_resp_f2_0_is_br),
.io_resp_f2_0_is_jal (_ubtb_io_resp_f2_0_is_jal),
.io_resp_f2_0_predicted_pc_valid (_ubtb_io_resp_f2_0_predicted_pc_valid),
.io_resp_f2_0_predicted_pc_bits (_ubtb_io_resp_f2_0_predicted_pc_bits),
.io_resp_f2_1_taken (_ubtb_io_resp_f2_1_taken),
.io_resp_f2_1_is_br (_ubtb_io_resp_f2_1_is_br),
.io_resp_f2_1_is_jal (_ubtb_io_resp_f2_1_is_jal),
.io_resp_f2_1_predicted_pc_valid (_ubtb_io_resp_f2_1_predicted_pc_valid),
.io_resp_f2_1_predicted_pc_bits (_ubtb_io_resp_f2_1_predicted_pc_bits),
.io_resp_f2_2_taken (_ubtb_io_resp_f2_2_taken),
.io_resp_f2_2_is_br (_ubtb_io_resp_f2_2_is_br),
.io_resp_f2_2_is_jal (_ubtb_io_resp_f2_2_is_jal),
.io_resp_f2_2_predicted_pc_valid (_ubtb_io_resp_f2_2_predicted_pc_valid),
.io_resp_f2_2_predicted_pc_bits (_ubtb_io_resp_f2_2_predicted_pc_bits),
.io_resp_f2_3_taken (_ubtb_io_resp_f2_3_taken),
.io_resp_f2_3_is_br (_ubtb_io_resp_f2_3_is_br),
.io_resp_f2_3_is_jal (_ubtb_io_resp_f2_3_is_jal),
.io_resp_f2_3_predicted_pc_valid (_ubtb_io_resp_f2_3_predicted_pc_valid),
.io_resp_f2_3_predicted_pc_bits (_ubtb_io_resp_f2_3_predicted_pc_bits),
.io_resp_f3_0_taken (_ubtb_io_resp_f3_0_taken),
.io_resp_f3_0_is_br (_ubtb_io_resp_f3_0_is_br),
.io_resp_f3_0_is_jal (_ubtb_io_resp_f3_0_is_jal),
.io_resp_f3_0_predicted_pc_valid (_ubtb_io_resp_f3_0_predicted_pc_valid),
.io_resp_f3_0_predicted_pc_bits (_ubtb_io_resp_f3_0_predicted_pc_bits),
.io_resp_f3_1_taken (_ubtb_io_resp_f3_1_taken),
.io_resp_f3_1_is_br (_ubtb_io_resp_f3_1_is_br),
.io_resp_f3_1_is_jal (_ubtb_io_resp_f3_1_is_jal),
.io_resp_f3_1_predicted_pc_valid (_ubtb_io_resp_f3_1_predicted_pc_valid),
.io_resp_f3_1_predicted_pc_bits (_ubtb_io_resp_f3_1_predicted_pc_bits),
.io_resp_f3_2_taken (_ubtb_io_resp_f3_2_taken),
.io_resp_f3_2_is_br (_ubtb_io_resp_f3_2_is_br),
.io_resp_f3_2_is_jal (_ubtb_io_resp_f3_2_is_jal),
.io_resp_f3_2_predicted_pc_valid (_ubtb_io_resp_f3_2_predicted_pc_valid),
.io_resp_f3_2_predicted_pc_bits (_ubtb_io_resp_f3_2_predicted_pc_bits),
.io_resp_f3_3_taken (_ubtb_io_resp_f3_3_taken),
.io_resp_f3_3_is_br (_ubtb_io_resp_f3_3_is_br),
.io_resp_f3_3_is_jal (_ubtb_io_resp_f3_3_is_jal),
.io_resp_f3_3_predicted_pc_valid (_ubtb_io_resp_f3_3_predicted_pc_valid),
.io_resp_f3_3_predicted_pc_bits (_ubtb_io_resp_f3_3_predicted_pc_bits),
.io_f3_meta (_ubtb_io_f3_meta),
.io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7]
.io_update_valid (io_update_valid_0), // @[composer.scala:14:7]
.io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7]
.io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7]
.io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7]
.io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7]
.io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7]
.io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7]
.io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7]
.io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7]
.io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7]
.io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7]
.io_update_bits_meta ({8'h0, io_update_bits_meta_0[119:8]}) // @[composer.scala:14:7, :31:22, :42:27, :43:31]
); // @[config-mixins.scala:449:26]
assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[composer.scala:14:7]
assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[composer.scala:14:7]
assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[composer.scala:14:7]
assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[composer.scala:14:7]
assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[composer.scala:14:7]
assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[composer.scala:14:7]
assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[composer.scala:14:7]
assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[composer.scala:14:7]
assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[composer.scala:14:7]
assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[composer.scala:14:7]
assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[composer.scala:14:7]
assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[composer.scala:14:7]
assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[composer.scala:14:7]
assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[composer.scala:14:7]
assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[composer.scala:14:7]
assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[composer.scala:14:7]
assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[composer.scala:14:7]
assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[composer.scala:14:7]
assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[composer.scala:14:7]
assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[composer.scala:14:7]
assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[composer.scala:14:7]
assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[composer.scala:14:7]
assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[composer.scala:14:7]
assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[composer.scala:14:7]
assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_f3_meta = io_f3_meta_0; // @[composer.scala:14:7]
endmodule |
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