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rtl-llm
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chisel-verilog-pairs

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chisel-verilog-pairs

1 contributor

History: 9 commits

abcdvay's picture

Upload firrtl_verilog_training_data.json

a228358 verified 9 days ago

.gitattributes

2.6 kB

Upload 2 files 5 months ago
chisel_verilog_training_data.json

1.69 GB
LFS

Upload chisel_verilog_training_data.json 2 months ago
firrtl_verilog_training_data.json

1.78 GB
LFS

Upload firrtl_verilog_training_data.json 9 days ago
training_data_no_parameters.json

5.66 MB

Upload training_data_no_parameters.json 6 months ago