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rtl-llm
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chisel-verilog-pairs

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chisel-verilog-pairs

Commit History

Upload firrtl_verilog_training_data.json

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abcdvay commited on 9 days ago

Upload firrtl_verilog_training_data.json

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abcdvay commited on 10 days ago

Upload chisel_verilog_training_data.json

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abcdvay commited on Mar 3

Upload chisel_verilog_training_data.json

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abcdvay commited on Feb 11

Upload chisel_verilog_training_data.json

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abcdvay commited on Feb 10

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abcdvay commited on Dec 13, 2024

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abcdvay commited on Dec 13, 2024

Upload training_data_no_parameters.json

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abcdvay commited on Nov 26, 2024

initial commit

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abcdvay commited on Nov 26, 2024

Commit History

Upload firrtl_verilog_training_data.json a228358 verified

Upload firrtl_verilog_training_data.json dccdd28 verified

Upload chisel_verilog_training_data.json 22882f8 verified

Upload chisel_verilog_training_data.json 9fc780f verified

Upload chisel_verilog_training_data.json 3261a02 verified

Upload 2 files 94a96fd verified

Upload 2 files e1775f5 verified

Upload training_data_no_parameters.json b8b481a verified

initial commit 4ec32bd verified