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rtl-llm
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chisel-verilog-pairs

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abcdvay commited on Dec 13, 2024

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e1775f5

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verified ·

1 Parent(s): b8b481a

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Files changed (3) hide show

.gitattributes +2 -0
chisel_verilog_training_data.json +3 -0
firrtl_verilog_training_data.json +3 -0

.gitattributes CHANGED Viewed

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 # Video files - compressed
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+chisel_verilog_training_data.json filter=lfs diff=lfs merge=lfs -text
+firrtl_verilog_training_data.json filter=lfs diff=lfs merge=lfs -text

chisel_verilog_training_data.json ADDED Viewed

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