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Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
class IDPool(numIds: Int, lateValid: Boolean = false, revocableSelect: Boolean = false) extends Module {
require (numIds > 0)
val idWidth = log2Up(numIds)
val io = IO(new Bundle {
val free = Flipped(Valid(UInt(idWidth.W)))
val alloc = if (revocableSelect) Decoupled(UInt(idWidth.W)) else Irrevocable(UInt(idWidth.W))
})
// True indicates that the id is available
val bitmap = RegInit(UInt(numIds.W), -1.S(numIds.W).asUInt)
val select = RegInit(0.U(idWidth.W))
val valid = RegInit(true.B)
io.alloc.valid := (if (lateValid) bitmap.orR else valid)
io.alloc.bits := (if (revocableSelect) PriorityEncoder(bitmap) else select)
val taken = Mux(io.alloc.ready, UIntToOH(io.alloc.bits, numIds), 0.U)
val allocated = Mux(io.free .valid, UIntToOH(io.free .bits, numIds), 0.U)
val bitmap1 = (bitmap & ~taken) | allocated
val select1 = PriorityEncoder(bitmap1)
val valid1 = ( (bitmap.orR && !((PopCount(bitmap) === 1.U) && io.alloc.ready)) // bitmap not zero, and not allocating last bit
|| io.free.valid)
// Clock gate the bitmap
when (io.alloc.ready || io.free.valid) {
bitmap := bitmap1
valid := valid1
}
// Make select irrevocable
when (io.alloc.ready || (!io.alloc.valid && io.free.valid)) {
select := select1
}
// No double freeing
assert (!io.free.valid || !(bitmap & ~taken)(io.free.bits))
// pre-calculations for timing
if (!lateValid) {
assert (valid === bitmap.orR)
}
if (!revocableSelect) {
when (io.alloc.valid && RegNext(io.alloc.ready || (!io.alloc.valid && io.free.valid))) {
assert (select === PriorityEncoder(bitmap))
}
}
} | module IDPool(
input clock,
input reset,
input io_free_valid,
input [2:0] io_free_bits,
input io_alloc_ready,
output io_alloc_valid,
output [2:0] io_alloc_bits
);
reg [7:0] bitmap;
reg [2:0] select;
reg valid;
wire [7:0] taken = io_alloc_ready ? 8'h1 << select : 8'h0;
wire [7:0] _GEN = {5'h0, io_free_bits};
reg REG;
wire [7:0] bitmap1 = bitmap & ~taken | (io_free_valid ? 8'h1 << _GEN : 8'h0);
wire _GEN_1 = io_alloc_ready | ~valid & io_free_valid;
always @(posedge clock) begin
if (reset) begin
bitmap <= 8'hFF;
select <= 3'h0;
valid <= 1'h1;
end
else begin
if (io_alloc_ready | io_free_valid) begin
bitmap <= bitmap1;
valid <= (|bitmap) & ~({1'h0, {1'h0, {1'h0, bitmap[0]} + {1'h0, bitmap[1]}} + {1'h0, {1'h0, bitmap[2]} + {1'h0, bitmap[3]}}} + {1'h0, {1'h0, {1'h0, bitmap[4]} + {1'h0, bitmap[5]}} + {1'h0, {1'h0, bitmap[6]} + {1'h0, bitmap[7]}}} == 4'h1 & io_alloc_ready) | io_free_valid;
end
if (_GEN_1)
select <= bitmap1[0] ? 3'h0 : bitmap1[1] ? 3'h1 : bitmap1[2] ? 3'h2 : bitmap1[3] ? 3'h3 : bitmap1[4] ? 3'h4 : bitmap1[5] ? 3'h5 : {2'h3, ~(bitmap1[6])};
end
REG <= _GEN_1;
end
assign io_alloc_valid = valid;
assign io_alloc_bits = select;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)
{
val queueBits = log2Up(queues)
val entryBits = log2Up(entries)
}
class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle
{
val index = UInt(params.queueBits.W)
val data = Output(params.gen)
}
class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module
{
override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}"
val io = IO(new Bundle {
// push is visible on the same cycle; flow queues
val push = Flipped(Decoupled(new ListBufferPush(params)))
val valid = UInt(params.queues.W)
val pop = Flipped(Valid(UInt(params.queueBits.W)))
val data = Output(params.gen)
})
val valid = RegInit(0.U(params.queues.W))
val head = Mem(params.queues, UInt(params.entryBits.W))
val tail = Mem(params.queues, UInt(params.entryBits.W))
val used = RegInit(0.U(params.entries.W))
val next = Mem(params.entries, UInt(params.entryBits.W))
val data = Mem(params.entries, params.gen)
val freeOH = ~(leftOR(~used) << 1) & ~used
val freeIdx = OHToUInt(freeOH)
val valid_set = WireDefault(0.U(params.queues.W))
val valid_clr = WireDefault(0.U(params.queues.W))
val used_set = WireDefault(0.U(params.entries.W))
val used_clr = WireDefault(0.U(params.entries.W))
val push_tail = tail.read(io.push.bits.index)
val push_valid = valid(io.push.bits.index)
io.push.ready := !used.andR
when (io.push.fire) {
valid_set := UIntToOH(io.push.bits.index, params.queues)
used_set := freeOH
data.write(freeIdx, io.push.bits.data)
when (push_valid) {
next.write(push_tail, freeIdx)
} .otherwise {
head.write(io.push.bits.index, freeIdx)
}
tail.write(io.push.bits.index, freeIdx)
}
val pop_head = head.read(io.pop.bits)
val pop_valid = valid(io.pop.bits)
// Bypass push data to the peek port
io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))
io.valid := (if (!params.bypass) valid else (valid | valid_set))
// It is an error to pop something that is not valid
assert (!io.pop.fire || (io.valid)(io.pop.bits))
when (io.pop.fire) {
used_clr := UIntToOH(pop_head, params.entries)
when (pop_head === tail.read(io.pop.bits)) {
valid_clr := UIntToOH(io.pop.bits, params.queues)
}
head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))
}
// Empty bypass changes no state
when ((!params.bypass).B || !io.pop.valid || pop_valid) {
used := (used & ~used_clr) | used_set
valid := (valid & ~valid_clr) | valid_set
}
} | module data_40x37(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [36:0] R0_data,
input [5:0] W0_addr,
input W0_en,
input W0_clk,
input [36:0] W0_data
);
reg [36:0] Memory[0:39];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 37'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
} | module ClockCrossingReg_w32(
input clock,
input [31:0] io_d,
output [31:0] io_q,
input io_en
);
reg [31:0] cdc_reg;
always @(posedge clock) begin
if (io_en)
cdc_reg <= io_d;
end
assign io_q = cdc_reg;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.jtag for license details.
package freechips.rocketchip.jtag
import chisel3._
import chisel3.reflect.DataMirror
import chisel3.internal.firrtl.KnownWidth
import chisel3.util.{Cat, Valid}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.property
/** Base JTAG shifter IO, viewed from input to shift register chain.
* Can be chained together.
*/
class ShifterIO extends Bundle {
val shift = Bool() // advance the scan chain on clock high
val data = Bool() // as input: bit to be captured into shifter MSB on next rising edge; as output: value of shifter LSB
val capture = Bool() // high in the CaptureIR/DR state when this chain is selected
val update = Bool() // high in the UpdateIR/DR state when this chain is selected
/** Sets a output shifter IO's control signals from a input shifter IO's control signals.
*/
def chainControlFrom(in: ShifterIO): Unit = {
shift := in.shift
capture := in.capture
update := in.update
}
}
trait ChainIO extends Bundle {
val chainIn = Input(new ShifterIO)
val chainOut = Output(new ShifterIO)
}
class Capture[+T <: Data](gen: T) extends Bundle {
val bits = Input(gen) // data to capture, should be always valid
val capture = Output(Bool()) // will be high in capture state (single cycle), captured on following rising edge
}
object Capture {
def apply[T <: Data](gen: T): Capture[T] = new Capture(gen)
}
/** Trait that all JTAG chains (data and instruction registers) must extend, providing basic chain
* IO.
*/
trait Chain extends Module {
val io: ChainIO
}
/** One-element shift register, data register for bypass mode.
*
* Implements Clause 10.
*/
class JtagBypassChain(implicit val p: Parameters) extends Chain {
class ModIO extends ChainIO
val io = IO(new ModIO)
io.chainOut chainControlFrom io.chainIn
val reg = Reg(Bool()) // 10.1.1a single shift register stage
io.chainOut.data := reg
property.cover(io.chainIn.capture, "bypass_chain_capture", "JTAG; bypass_chain_capture; This Bypass Chain captured data")
when (io.chainIn.capture) {
reg := false.B // 10.1.1b capture logic 0 on TCK rising
} .elsewhen (io.chainIn.shift) {
reg := io.chainIn.data
}
assert(!(io.chainIn.capture && io.chainIn.update)
&& !(io.chainIn.capture && io.chainIn.shift)
&& !(io.chainIn.update && io.chainIn.shift))
}
object JtagBypassChain {
def apply()(implicit p: Parameters) = new JtagBypassChain
}
/** Simple shift register with parallel capture only, for read-only data registers.
*
* Number of stages is the number of bits in gen, which must have a known width.
*
* Useful notes:
* 7.2.1c shifter shifts on TCK rising edge
* 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge
*/
class CaptureChain[+T <: Data](gen: T)(implicit val p: Parameters) extends Chain {
override def desiredName = s"CaptureChain_${gen.typeName}"
class ModIO extends ChainIO {
val capture = Capture(gen)
}
val io = IO(new ModIO)
io.chainOut chainControlFrom io.chainIn
val n = DataMirror.widthOf(gen) match {
case KnownWidth(x) => x
case _ => require(false, s"can't generate chain for unknown width data type $gen"); -1 // TODO: remove -1 type hack
}
val regs = (0 until n) map (x => Reg(Bool()))
io.chainOut.data := regs(0)
property.cover(io.chainIn.capture, "chain_capture", "JTAG; chain_capture; This Chain captured data")
when (io.chainIn.capture) {
(0 until n) map (x => regs(x) := io.capture.bits.asUInt(x))
io.capture.capture := true.B
} .elsewhen (io.chainIn.shift) {
regs(n-1) := io.chainIn.data
(0 until n-1) map (x => regs(x) := regs(x+1))
io.capture.capture := false.B
} .otherwise {
io.capture.capture := false.B
}
assert(!(io.chainIn.capture && io.chainIn.update)
&& !(io.chainIn.capture && io.chainIn.shift)
&& !(io.chainIn.update && io.chainIn.shift))
}
object CaptureChain {
def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureChain(gen)
}
/** Simple shift register with parallel capture and update. Useful for general instruction and data
* scan registers.
*
* Number of stages is the max number of bits in genCapture and genUpdate, both of which must have
* known widths. If there is a width mismatch, the unused most significant bits will be zero.
*
* Useful notes:
* 7.2.1c shifter shifts on TCK rising edge
* 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge
*/
class CaptureUpdateChain[+T <: Data, +V <: Data](genCapture: T, genUpdate: V)(implicit val p: Parameters) extends Chain {
override def desiredName = s"CaptureUpdateChain_${genCapture.typeName}_To_${genUpdate.typeName}"
class ModIO extends ChainIO {
val capture = Capture(genCapture)
val update = Valid(genUpdate) // valid high when in update state (single cycle), contents may change any time after
}
val io = IO(new ModIO)
io.chainOut chainControlFrom io.chainIn
val captureWidth = DataMirror.widthOf(genCapture) match {
case KnownWidth(x) => x
case _ => require(false, s"can't generate chain for unknown width data type $genCapture"); -1 // TODO: remove -1 type hack
}
val updateWidth = DataMirror.widthOf(genUpdate) match {
case KnownWidth(x) => x
case _ => require(false, s"can't generate chain for unknown width data type $genUpdate"); -1 // TODO: remove -1 type hack
}
val n = math.max(captureWidth, updateWidth)
val regs = (0 until n) map (x => Reg(Bool()))
io.chainOut.data := regs(0)
val updateBits = Cat(regs.reverse)(updateWidth-1, 0)
io.update.bits := updateBits.asTypeOf(io.update.bits)
val captureBits = io.capture.bits.asUInt
property.cover(io.chainIn.capture, "chain_capture", "JTAG;chain_capture; This Chain captured data")
property.cover(io.chainIn.capture, "chain_update", "JTAG;chain_update; This Chain updated data")
when (io.chainIn.capture) {
(0 until math.min(n, captureWidth)) map (x => regs(x) := captureBits(x))
(captureWidth until n) map (x => regs(x) := 0.U)
io.capture.capture := true.B
io.update.valid := false.B
} .elsewhen (io.chainIn.update) {
io.capture.capture := false.B
io.update.valid := true.B
} .elsewhen (io.chainIn.shift) {
regs(n-1) := io.chainIn.data
(0 until n-1) map (x => regs(x) := regs(x+1))
io.capture.capture := false.B
io.update.valid := false.B
} .otherwise {
io.capture.capture := false.B
io.update.valid := false.B
}
assert(!(io.chainIn.capture && io.chainIn.update)
&& !(io.chainIn.capture && io.chainIn.shift)
&& !(io.chainIn.update && io.chainIn.shift))
}
object CaptureUpdateChain {
/** Capture-update chain with matching capture and update types.
*/
def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureUpdateChain(gen, gen)
def apply[T <: Data, V <: Data](genCapture: T, genUpdate: V)(implicit p: Parameters) =
new CaptureUpdateChain(genCapture, genUpdate)
} | module CaptureChain_JTAGIdcodeBundle(
input clock,
input reset,
input io_chainIn_shift,
input io_chainIn_data,
input io_chainIn_capture,
input io_chainIn_update,
output io_chainOut_data
);
reg regs_0;
reg regs_1;
reg regs_2;
reg regs_3;
reg regs_4;
reg regs_5;
reg regs_6;
reg regs_7;
reg regs_8;
reg regs_9;
reg regs_10;
reg regs_11;
reg regs_12;
reg regs_13;
reg regs_14;
reg regs_15;
reg regs_16;
reg regs_17;
reg regs_18;
reg regs_19;
reg regs_20;
reg regs_21;
reg regs_22;
reg regs_23;
reg regs_24;
reg regs_25;
reg regs_26;
reg regs_27;
reg regs_28;
reg regs_29;
reg regs_30;
reg regs_31;
always @(posedge clock) begin
if (io_chainIn_capture) begin
regs_0 <= 1'h1;
regs_1 <= 1'h0;
regs_2 <= 1'h0;
regs_3 <= 1'h0;
regs_4 <= 1'h0;
regs_5 <= 1'h0;
regs_6 <= 1'h0;
regs_7 <= 1'h0;
regs_8 <= 1'h0;
regs_9 <= 1'h0;
regs_10 <= 1'h0;
regs_11 <= 1'h0;
regs_12 <= 1'h0;
regs_13 <= 1'h0;
regs_14 <= 1'h0;
regs_15 <= 1'h0;
regs_16 <= 1'h0;
regs_17 <= 1'h0;
regs_18 <= 1'h0;
regs_19 <= 1'h0;
regs_20 <= 1'h0;
regs_21 <= 1'h0;
regs_22 <= 1'h0;
regs_23 <= 1'h0;
regs_24 <= 1'h0;
regs_25 <= 1'h0;
regs_26 <= 1'h0;
regs_27 <= 1'h0;
regs_28 <= 1'h0;
regs_29 <= 1'h0;
regs_30 <= 1'h0;
regs_31 <= 1'h0;
end
else if (io_chainIn_shift) begin
regs_0 <= regs_1;
regs_1 <= regs_2;
regs_2 <= regs_3;
regs_3 <= regs_4;
regs_4 <= regs_5;
regs_5 <= regs_6;
regs_6 <= regs_7;
regs_7 <= regs_8;
regs_8 <= regs_9;
regs_9 <= regs_10;
regs_10 <= regs_11;
regs_11 <= regs_12;
regs_12 <= regs_13;
regs_13 <= regs_14;
regs_14 <= regs_15;
regs_15 <= regs_16;
regs_16 <= regs_17;
regs_17 <= regs_18;
regs_18 <= regs_19;
regs_19 <= regs_20;
regs_20 <= regs_21;
regs_21 <= regs_22;
regs_22 <= regs_23;
regs_23 <= regs_24;
regs_24 <= regs_25;
regs_25 <= regs_26;
regs_26 <= regs_27;
regs_27 <= regs_28;
regs_28 <= regs_29;
regs_29 <= regs_30;
regs_30 <= regs_31;
regs_31 <= io_chainIn_data;
end
end
assign io_chainOut_data = regs_0;
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix}
import scala.math.min
case class BoomLoopPredictorParams(
nWays: Int = 4,
threshold: Int = 7
)
class LoopBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tagSz = 10
override val nSets = 16
class LoopMeta extends Bundle {
val s_cnt = UInt(10.W)
}
class LoopEntry extends Bundle {
val tag = UInt(tagSz.W)
val conf = UInt(3.W)
val age = UInt(3.W)
val p_cnt = UInt(10.W)
val s_cnt = UInt(10.W)
}
class LoopBranchPredictorColumn extends Module {
val io = IO(new Bundle {
val f2_req_valid = Input(Bool())
val f2_req_idx = Input(UInt())
val f3_req_fire = Input(Bool())
val f3_pred_in = Input(Bool())
val f3_pred = Output(Bool())
val f3_meta = Output(new LoopMeta)
val update_mispredict = Input(Bool())
val update_repair = Input(Bool())
val update_idx = Input(UInt())
val update_resolve_dir = Input(Bool())
val update_meta = Input(new LoopMeta)
})
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nSets).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nSets-1).U) { doing_reset := false.B }
val entries = Reg(Vec(nSets, new LoopEntry))
val f2_entry = WireInit(entries(io.f2_req_idx))
when (io.update_repair && io.update_idx === io.f2_req_idx) {
f2_entry.s_cnt := io.update_meta.s_cnt
} .elsewhen (io.update_mispredict && io.update_idx === io.f2_req_idx) {
f2_entry.s_cnt := 0.U
}
val f3_entry = RegNext(f2_entry)
val f3_scnt = Mux(io.update_repair && io.update_idx === RegNext(io.f2_req_idx),
io.update_meta.s_cnt,
f3_entry.s_cnt)
val f3_tag = RegNext(io.f2_req_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets)))
io.f3_pred := io.f3_pred_in
io.f3_meta.s_cnt := f3_scnt
when (f3_entry.tag === f3_tag) {
when (f3_scnt === f3_entry.p_cnt && f3_entry.conf === 7.U) {
io.f3_pred := !io.f3_pred_in
}
}
val f4_fire = RegNext(io.f3_req_fire)
val f4_entry = RegNext(f3_entry)
val f4_tag = RegNext(f3_tag)
val f4_scnt = RegNext(f3_scnt)
val f4_idx = RegNext(RegNext(io.f2_req_idx))
when (f4_fire) {
when (f4_entry.tag === f4_tag) {
when (f4_scnt === f4_entry.p_cnt && f4_entry.conf === 7.U) {
entries(f4_idx).age := 7.U
entries(f4_idx).s_cnt := 0.U
} .otherwise {
entries(f4_idx).s_cnt := f4_scnt + 1.U
entries(f4_idx).age := Mux(f4_entry.age === 7.U, 7.U, f4_entry.age + 1.U)
}
}
}
val entry = entries(io.update_idx)
val tag = io.update_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets))
val tag_match = entry.tag === tag
val ctr_match = entry.p_cnt === io.update_meta.s_cnt
val wentry = WireInit(entry)
when (io.update_mispredict && !doing_reset) {
// Learned, tag match -> decrement confidence
when (entry.conf === 7.U && tag_match) {
wentry.s_cnt := 0.U
wentry.conf := 0.U
// Learned, no tag match -> do nothing? Don't evict super-confident entries?
} .elsewhen (entry.conf === 7.U && !tag_match) {
// Confident, tag match, ctr_match -> increment confidence, reset counter
} .elsewhen (entry.conf =/= 0.U && tag_match && ctr_match) {
wentry.conf := entry.conf + 1.U
wentry.s_cnt := 0.U
// Confident, tag match, no ctr match -> zero confidence, reset counter, set previous counter
} .elsewhen (entry.conf =/= 0.U && tag_match && !ctr_match) {
wentry.conf := 0.U
wentry.s_cnt := 0.U
wentry.p_cnt := io.update_meta.s_cnt
// Confident, no tag match, age is 0 -> replace this entry with our own, set our age high to avoid ping-pong
} .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age === 0.U) {
wentry.tag := tag
wentry.conf := 1.U
wentry.s_cnt := 0.U
wentry.p_cnt := io.update_meta.s_cnt
// Confident, no tag match, age > 0 -> decrement age
} .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age =/= 0.U) {
wentry.age := entry.age - 1.U
// Unconfident, tag match, ctr match -> increment confidence
} .elsewhen (entry.conf === 0.U && tag_match && ctr_match) {
wentry.conf := 1.U
wentry.age := 7.U
wentry.s_cnt := 0.U
// Unconfident, tag match, no ctr match -> set previous counter
} .elsewhen (entry.conf === 0.U && tag_match && !ctr_match) {
wentry.p_cnt := io.update_meta.s_cnt
wentry.age := 7.U
wentry.s_cnt := 0.U
// Unconfident, no tag match -> set previous counter and tag
} .elsewhen (entry.conf === 0.U && !tag_match) {
wentry.tag := tag
wentry.conf := 1.U
wentry.age := 7.U
wentry.s_cnt := 0.U
wentry.p_cnt := io.update_meta.s_cnt
}
entries(io.update_idx) := wentry
} .elsewhen (io.update_repair && !doing_reset) {
when (tag_match && !(f4_fire && io.update_idx === f4_idx)) {
wentry.s_cnt := io.update_meta.s_cnt
entries(io.update_idx) := wentry
}
}
when (doing_reset) {
entries(reset_idx) := (0.U).asTypeOf(new LoopEntry)
}
}
val columns = Seq.fill(bankWidth) { Module(new LoopBranchPredictorColumn) }
val mems = Nil // TODO fix
val f3_meta = Wire(Vec(bankWidth, new LoopMeta))
override val metaSz = f3_meta.asUInt.getWidth
val update_meta = s1_update.bits.meta.asTypeOf(Vec(bankWidth, new LoopMeta))
for (w <- 0 until bankWidth) {
columns(w).io.f2_req_valid := s2_valid
columns(w).io.f2_req_idx := s2_idx
columns(w).io.f3_req_fire := (s3_valid && s3_mask(w) && io.f3_fire &&
RegNext(io.resp_in(0).f2(w).predicted_pc.valid && io.resp_in(0).f2(w).is_br))
columns(w).io.f3_pred_in := io.resp_in(0).f3(w).taken
io.resp.f3(w).taken := columns(w).io.f3_pred
columns(w).io.update_mispredict := (s1_update.valid &&
s1_update.bits.br_mask(w) &&
s1_update.bits.is_mispredict_update &&
s1_update.bits.cfi_mispredicted)
columns(w).io.update_repair := (s1_update.valid &&
s1_update.bits.br_mask(w) &&
s1_update.bits.is_repair_update)
columns(w).io.update_idx := s1_update_idx
columns(w).io.update_resolve_dir := s1_update.bits.cfi_taken
columns(w).io.update_meta := update_meta(w)
f3_meta(w) := columns(w).io.f3_meta
}
io.f3_meta := f3_meta.asUInt
} | module LoopBranchPredictorColumn(
input clock,
input reset,
input [36:0] io_f2_req_idx,
input io_f3_req_fire,
input io_f3_pred_in,
output io_f3_pred,
output [9:0] io_f3_meta_s_cnt,
input io_update_mispredict,
input io_update_repair,
input [36:0] io_update_idx,
input [9:0] io_update_meta_s_cnt
);
reg doing_reset;
reg [3:0] reset_idx;
reg [9:0] entries_0_tag;
reg [2:0] entries_0_conf;
reg [2:0] entries_0_age;
reg [9:0] entries_0_p_cnt;
reg [9:0] entries_0_s_cnt;
reg [9:0] entries_1_tag;
reg [2:0] entries_1_conf;
reg [2:0] entries_1_age;
reg [9:0] entries_1_p_cnt;
reg [9:0] entries_1_s_cnt;
reg [9:0] entries_2_tag;
reg [2:0] entries_2_conf;
reg [2:0] entries_2_age;
reg [9:0] entries_2_p_cnt;
reg [9:0] entries_2_s_cnt;
reg [9:0] entries_3_tag;
reg [2:0] entries_3_conf;
reg [2:0] entries_3_age;
reg [9:0] entries_3_p_cnt;
reg [9:0] entries_3_s_cnt;
reg [9:0] entries_4_tag;
reg [2:0] entries_4_conf;
reg [2:0] entries_4_age;
reg [9:0] entries_4_p_cnt;
reg [9:0] entries_4_s_cnt;
reg [9:0] entries_5_tag;
reg [2:0] entries_5_conf;
reg [2:0] entries_5_age;
reg [9:0] entries_5_p_cnt;
reg [9:0] entries_5_s_cnt;
reg [9:0] entries_6_tag;
reg [2:0] entries_6_conf;
reg [2:0] entries_6_age;
reg [9:0] entries_6_p_cnt;
reg [9:0] entries_6_s_cnt;
reg [9:0] entries_7_tag;
reg [2:0] entries_7_conf;
reg [2:0] entries_7_age;
reg [9:0] entries_7_p_cnt;
reg [9:0] entries_7_s_cnt;
reg [9:0] entries_8_tag;
reg [2:0] entries_8_conf;
reg [2:0] entries_8_age;
reg [9:0] entries_8_p_cnt;
reg [9:0] entries_8_s_cnt;
reg [9:0] entries_9_tag;
reg [2:0] entries_9_conf;
reg [2:0] entries_9_age;
reg [9:0] entries_9_p_cnt;
reg [9:0] entries_9_s_cnt;
reg [9:0] entries_10_tag;
reg [2:0] entries_10_conf;
reg [2:0] entries_10_age;
reg [9:0] entries_10_p_cnt;
reg [9:0] entries_10_s_cnt;
reg [9:0] entries_11_tag;
reg [2:0] entries_11_conf;
reg [2:0] entries_11_age;
reg [9:0] entries_11_p_cnt;
reg [9:0] entries_11_s_cnt;
reg [9:0] entries_12_tag;
reg [2:0] entries_12_conf;
reg [2:0] entries_12_age;
reg [9:0] entries_12_p_cnt;
reg [9:0] entries_12_s_cnt;
reg [9:0] entries_13_tag;
reg [2:0] entries_13_conf;
reg [2:0] entries_13_age;
reg [9:0] entries_13_p_cnt;
reg [9:0] entries_13_s_cnt;
reg [9:0] entries_14_tag;
reg [2:0] entries_14_conf;
reg [2:0] entries_14_age;
reg [9:0] entries_14_p_cnt;
reg [9:0] entries_14_s_cnt;
reg [9:0] entries_15_tag;
reg [2:0] entries_15_conf;
reg [2:0] entries_15_age;
reg [9:0] entries_15_p_cnt;
reg [9:0] entries_15_s_cnt;
reg [9:0] f3_entry_tag;
reg [2:0] f3_entry_conf;
reg [2:0] f3_entry_age;
reg [9:0] f3_entry_p_cnt;
reg [9:0] f3_entry_s_cnt;
reg [36:0] f3_scnt_REG;
wire [9:0] f3_scnt = io_update_repair & io_update_idx == f3_scnt_REG ? io_update_meta_s_cnt : f3_entry_s_cnt;
reg [9:0] f3_tag;
reg f4_fire;
reg [9:0] f4_entry_tag;
reg [2:0] f4_entry_conf;
reg [2:0] f4_entry_age;
reg [9:0] f4_entry_p_cnt;
reg [9:0] f4_tag;
reg [9:0] f4_scnt;
reg [36:0] f4_idx_REG;
reg [36:0] f4_idx;
wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}};
wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}};
wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}};
wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}};
wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}};
wire _GEN_4 = io_update_idx == io_f2_req_idx;
wire _GEN_5 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf);
wire [9:0] _GEN_6 = _GEN_5 ? 10'h0 : f4_scnt + 10'h1;
wire _GEN_7 = f4_fire & f4_entry_tag == f4_tag;
wire [2:0] _GEN_8 = _GEN_5 | (&f4_entry_age) ? 3'h7 : f4_entry_age + 3'h1;
wire [9:0] _GEN_9 = _GEN[io_update_idx[3:0]];
wire [2:0] _GEN_10 = _GEN_0[io_update_idx[3:0]];
wire [2:0] _GEN_11 = _GEN_1[io_update_idx[3:0]];
wire [9:0] _GEN_12 = _GEN_2[io_update_idx[3:0]];
wire [9:0] _GEN_13 = _GEN_3[io_update_idx[3:0]];
wire tag_match = _GEN_9 == io_update_idx[13:4];
wire ctr_match = _GEN_12 == io_update_meta_s_cnt;
wire _GEN_14 = io_update_mispredict & ~doing_reset;
wire _GEN_15 = (&_GEN_10) & tag_match;
wire _GEN_16 = _GEN_9 != io_update_idx[13:4];
wire _GEN_17 = (&_GEN_10) & _GEN_16;
wire _GEN_18 = (|_GEN_10) & tag_match;
wire _GEN_19 = _GEN_18 & ctr_match;
wire [2:0] _wentry_conf_T = _GEN_10 + 3'h1;
wire _GEN_20 = _GEN_12 != io_update_meta_s_cnt;
wire _GEN_21 = _GEN_18 & _GEN_20;
wire _GEN_22 = (|_GEN_10) & _GEN_16;
wire _GEN_23 = _GEN_22 & ~(|_GEN_11);
wire _GEN_24 = _GEN_22 & (|_GEN_11);
wire [2:0] _wentry_age_T = _GEN_11 - 3'h1;
wire _GEN_25 = ~(|_GEN_10) & tag_match;
wire _GEN_26 = _GEN_25 & ctr_match;
wire _GEN_27 = _GEN_25 & _GEN_20;
wire _GEN_28 = ~(|_GEN_10) & _GEN_16;
wire _GEN_29 = _GEN_26 | _GEN_27;
wire _GEN_30 = _GEN_19 | _GEN_21;
wire _GEN_31 = ~_GEN_14 | _GEN_15 | _GEN_17 | _GEN_30 | ~(_GEN_23 | ~(_GEN_24 | _GEN_29 | ~_GEN_28));
wire _GEN_32 = _GEN_23 | ~(_GEN_24 | ~(_GEN_26 | ~(_GEN_27 | ~_GEN_28)));
wire _GEN_33 = _GEN_27 | _GEN_28;
wire _GEN_34 = _GEN_26 | _GEN_33;
wire _GEN_35 = _GEN_21 | _GEN_23;
wire _GEN_36 = ~_GEN_14 | _GEN_15 | _GEN_17 | _GEN_19 | _GEN_35;
wire _GEN_37 = _GEN_15 | ~(_GEN_17 | ~(_GEN_30 | _GEN_23 | ~(_GEN_24 | ~(_GEN_29 | _GEN_28))));
wire _GEN_38 = ~_GEN_14 | _GEN_15 | _GEN_17 | _GEN_19 | ~(_GEN_35 | ~(_GEN_24 | _GEN_26 | ~_GEN_33));
wire _GEN_39 = io_update_repair & ~doing_reset;
wire _GEN_40 = tag_match & ~(f4_fire & io_update_idx == f4_idx);
wire _GEN_41 = _GEN_39 & _GEN_40;
wire _GEN_42 = _GEN_14 | _GEN_39 & _GEN_40;
always @(posedge clock) begin
if (reset) begin
doing_reset <= 1'h1;
reset_idx <= 4'h0;
end
else begin
doing_reset <= ~(&reset_idx) & doing_reset;
reset_idx <= reset_idx + {3'h0, doing_reset};
end
if (doing_reset & reset_idx == 4'h0) begin
entries_0_tag <= 10'h0;
entries_0_conf <= 3'h0;
entries_0_age <= 3'h0;
entries_0_p_cnt <= 10'h0;
entries_0_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'h0) begin
if (_GEN_31)
entries_0_tag <= _GEN_9;
else
entries_0_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_0_conf <= 3'h0;
else if (_GEN_17)
entries_0_conf <= _GEN_10;
else if (_GEN_19)
entries_0_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_0_conf <= 3'h0;
else if (_GEN_32)
entries_0_conf <= 3'h1;
else
entries_0_conf <= _GEN_10;
end
else
entries_0_conf <= _GEN_10;
if (_GEN_36)
entries_0_age <= _GEN_11;
else if (_GEN_24)
entries_0_age <= _wentry_age_T;
else if (_GEN_34)
entries_0_age <= 3'h7;
else
entries_0_age <= _GEN_11;
if (_GEN_38)
entries_0_p_cnt <= _GEN_12;
else
entries_0_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_0_s_cnt <= 10'h0;
else
entries_0_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_0_s_cnt <= io_update_meta_s_cnt;
else
entries_0_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'h0) begin
entries_0_age <= _GEN_8;
entries_0_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'h1) begin
entries_1_tag <= 10'h0;
entries_1_conf <= 3'h0;
entries_1_age <= 3'h0;
entries_1_p_cnt <= 10'h0;
entries_1_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'h1) begin
if (_GEN_31)
entries_1_tag <= _GEN_9;
else
entries_1_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_1_conf <= 3'h0;
else if (_GEN_17)
entries_1_conf <= _GEN_10;
else if (_GEN_19)
entries_1_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_1_conf <= 3'h0;
else if (_GEN_32)
entries_1_conf <= 3'h1;
else
entries_1_conf <= _GEN_10;
end
else
entries_1_conf <= _GEN_10;
if (_GEN_36)
entries_1_age <= _GEN_11;
else if (_GEN_24)
entries_1_age <= _wentry_age_T;
else if (_GEN_34)
entries_1_age <= 3'h7;
else
entries_1_age <= _GEN_11;
if (_GEN_38)
entries_1_p_cnt <= _GEN_12;
else
entries_1_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_1_s_cnt <= 10'h0;
else
entries_1_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_1_s_cnt <= io_update_meta_s_cnt;
else
entries_1_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'h1) begin
entries_1_age <= _GEN_8;
entries_1_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'h2) begin
entries_2_tag <= 10'h0;
entries_2_conf <= 3'h0;
entries_2_age <= 3'h0;
entries_2_p_cnt <= 10'h0;
entries_2_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'h2) begin
if (_GEN_31)
entries_2_tag <= _GEN_9;
else
entries_2_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_2_conf <= 3'h0;
else if (_GEN_17)
entries_2_conf <= _GEN_10;
else if (_GEN_19)
entries_2_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_2_conf <= 3'h0;
else if (_GEN_32)
entries_2_conf <= 3'h1;
else
entries_2_conf <= _GEN_10;
end
else
entries_2_conf <= _GEN_10;
if (_GEN_36)
entries_2_age <= _GEN_11;
else if (_GEN_24)
entries_2_age <= _wentry_age_T;
else if (_GEN_34)
entries_2_age <= 3'h7;
else
entries_2_age <= _GEN_11;
if (_GEN_38)
entries_2_p_cnt <= _GEN_12;
else
entries_2_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_2_s_cnt <= 10'h0;
else
entries_2_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_2_s_cnt <= io_update_meta_s_cnt;
else
entries_2_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'h2) begin
entries_2_age <= _GEN_8;
entries_2_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'h3) begin
entries_3_tag <= 10'h0;
entries_3_conf <= 3'h0;
entries_3_age <= 3'h0;
entries_3_p_cnt <= 10'h0;
entries_3_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'h3) begin
if (_GEN_31)
entries_3_tag <= _GEN_9;
else
entries_3_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_3_conf <= 3'h0;
else if (_GEN_17)
entries_3_conf <= _GEN_10;
else if (_GEN_19)
entries_3_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_3_conf <= 3'h0;
else if (_GEN_32)
entries_3_conf <= 3'h1;
else
entries_3_conf <= _GEN_10;
end
else
entries_3_conf <= _GEN_10;
if (_GEN_36)
entries_3_age <= _GEN_11;
else if (_GEN_24)
entries_3_age <= _wentry_age_T;
else if (_GEN_34)
entries_3_age <= 3'h7;
else
entries_3_age <= _GEN_11;
if (_GEN_38)
entries_3_p_cnt <= _GEN_12;
else
entries_3_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_3_s_cnt <= 10'h0;
else
entries_3_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_3_s_cnt <= io_update_meta_s_cnt;
else
entries_3_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'h3) begin
entries_3_age <= _GEN_8;
entries_3_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'h4) begin
entries_4_tag <= 10'h0;
entries_4_conf <= 3'h0;
entries_4_age <= 3'h0;
entries_4_p_cnt <= 10'h0;
entries_4_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'h4) begin
if (_GEN_31)
entries_4_tag <= _GEN_9;
else
entries_4_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_4_conf <= 3'h0;
else if (_GEN_17)
entries_4_conf <= _GEN_10;
else if (_GEN_19)
entries_4_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_4_conf <= 3'h0;
else if (_GEN_32)
entries_4_conf <= 3'h1;
else
entries_4_conf <= _GEN_10;
end
else
entries_4_conf <= _GEN_10;
if (_GEN_36)
entries_4_age <= _GEN_11;
else if (_GEN_24)
entries_4_age <= _wentry_age_T;
else if (_GEN_34)
entries_4_age <= 3'h7;
else
entries_4_age <= _GEN_11;
if (_GEN_38)
entries_4_p_cnt <= _GEN_12;
else
entries_4_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_4_s_cnt <= 10'h0;
else
entries_4_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_4_s_cnt <= io_update_meta_s_cnt;
else
entries_4_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'h4) begin
entries_4_age <= _GEN_8;
entries_4_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'h5) begin
entries_5_tag <= 10'h0;
entries_5_conf <= 3'h0;
entries_5_age <= 3'h0;
entries_5_p_cnt <= 10'h0;
entries_5_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'h5) begin
if (_GEN_31)
entries_5_tag <= _GEN_9;
else
entries_5_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_5_conf <= 3'h0;
else if (_GEN_17)
entries_5_conf <= _GEN_10;
else if (_GEN_19)
entries_5_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_5_conf <= 3'h0;
else if (_GEN_32)
entries_5_conf <= 3'h1;
else
entries_5_conf <= _GEN_10;
end
else
entries_5_conf <= _GEN_10;
if (_GEN_36)
entries_5_age <= _GEN_11;
else if (_GEN_24)
entries_5_age <= _wentry_age_T;
else if (_GEN_34)
entries_5_age <= 3'h7;
else
entries_5_age <= _GEN_11;
if (_GEN_38)
entries_5_p_cnt <= _GEN_12;
else
entries_5_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_5_s_cnt <= 10'h0;
else
entries_5_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_5_s_cnt <= io_update_meta_s_cnt;
else
entries_5_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'h5) begin
entries_5_age <= _GEN_8;
entries_5_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'h6) begin
entries_6_tag <= 10'h0;
entries_6_conf <= 3'h0;
entries_6_age <= 3'h0;
entries_6_p_cnt <= 10'h0;
entries_6_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'h6) begin
if (_GEN_31)
entries_6_tag <= _GEN_9;
else
entries_6_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_6_conf <= 3'h0;
else if (_GEN_17)
entries_6_conf <= _GEN_10;
else if (_GEN_19)
entries_6_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_6_conf <= 3'h0;
else if (_GEN_32)
entries_6_conf <= 3'h1;
else
entries_6_conf <= _GEN_10;
end
else
entries_6_conf <= _GEN_10;
if (_GEN_36)
entries_6_age <= _GEN_11;
else if (_GEN_24)
entries_6_age <= _wentry_age_T;
else if (_GEN_34)
entries_6_age <= 3'h7;
else
entries_6_age <= _GEN_11;
if (_GEN_38)
entries_6_p_cnt <= _GEN_12;
else
entries_6_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_6_s_cnt <= 10'h0;
else
entries_6_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_6_s_cnt <= io_update_meta_s_cnt;
else
entries_6_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'h6) begin
entries_6_age <= _GEN_8;
entries_6_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'h7) begin
entries_7_tag <= 10'h0;
entries_7_conf <= 3'h0;
entries_7_age <= 3'h0;
entries_7_p_cnt <= 10'h0;
entries_7_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'h7) begin
if (_GEN_31)
entries_7_tag <= _GEN_9;
else
entries_7_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_7_conf <= 3'h0;
else if (_GEN_17)
entries_7_conf <= _GEN_10;
else if (_GEN_19)
entries_7_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_7_conf <= 3'h0;
else if (_GEN_32)
entries_7_conf <= 3'h1;
else
entries_7_conf <= _GEN_10;
end
else
entries_7_conf <= _GEN_10;
if (_GEN_36)
entries_7_age <= _GEN_11;
else if (_GEN_24)
entries_7_age <= _wentry_age_T;
else if (_GEN_34)
entries_7_age <= 3'h7;
else
entries_7_age <= _GEN_11;
if (_GEN_38)
entries_7_p_cnt <= _GEN_12;
else
entries_7_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_7_s_cnt <= 10'h0;
else
entries_7_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_7_s_cnt <= io_update_meta_s_cnt;
else
entries_7_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'h7) begin
entries_7_age <= _GEN_8;
entries_7_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'h8) begin
entries_8_tag <= 10'h0;
entries_8_conf <= 3'h0;
entries_8_age <= 3'h0;
entries_8_p_cnt <= 10'h0;
entries_8_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'h8) begin
if (_GEN_31)
entries_8_tag <= _GEN_9;
else
entries_8_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_8_conf <= 3'h0;
else if (_GEN_17)
entries_8_conf <= _GEN_10;
else if (_GEN_19)
entries_8_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_8_conf <= 3'h0;
else if (_GEN_32)
entries_8_conf <= 3'h1;
else
entries_8_conf <= _GEN_10;
end
else
entries_8_conf <= _GEN_10;
if (_GEN_36)
entries_8_age <= _GEN_11;
else if (_GEN_24)
entries_8_age <= _wentry_age_T;
else if (_GEN_34)
entries_8_age <= 3'h7;
else
entries_8_age <= _GEN_11;
if (_GEN_38)
entries_8_p_cnt <= _GEN_12;
else
entries_8_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_8_s_cnt <= 10'h0;
else
entries_8_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_8_s_cnt <= io_update_meta_s_cnt;
else
entries_8_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'h8) begin
entries_8_age <= _GEN_8;
entries_8_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'h9) begin
entries_9_tag <= 10'h0;
entries_9_conf <= 3'h0;
entries_9_age <= 3'h0;
entries_9_p_cnt <= 10'h0;
entries_9_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'h9) begin
if (_GEN_31)
entries_9_tag <= _GEN_9;
else
entries_9_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_9_conf <= 3'h0;
else if (_GEN_17)
entries_9_conf <= _GEN_10;
else if (_GEN_19)
entries_9_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_9_conf <= 3'h0;
else if (_GEN_32)
entries_9_conf <= 3'h1;
else
entries_9_conf <= _GEN_10;
end
else
entries_9_conf <= _GEN_10;
if (_GEN_36)
entries_9_age <= _GEN_11;
else if (_GEN_24)
entries_9_age <= _wentry_age_T;
else if (_GEN_34)
entries_9_age <= 3'h7;
else
entries_9_age <= _GEN_11;
if (_GEN_38)
entries_9_p_cnt <= _GEN_12;
else
entries_9_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_9_s_cnt <= 10'h0;
else
entries_9_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_9_s_cnt <= io_update_meta_s_cnt;
else
entries_9_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'h9) begin
entries_9_age <= _GEN_8;
entries_9_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'hA) begin
entries_10_tag <= 10'h0;
entries_10_conf <= 3'h0;
entries_10_age <= 3'h0;
entries_10_p_cnt <= 10'h0;
entries_10_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'hA) begin
if (_GEN_31)
entries_10_tag <= _GEN_9;
else
entries_10_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_10_conf <= 3'h0;
else if (_GEN_17)
entries_10_conf <= _GEN_10;
else if (_GEN_19)
entries_10_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_10_conf <= 3'h0;
else if (_GEN_32)
entries_10_conf <= 3'h1;
else
entries_10_conf <= _GEN_10;
end
else
entries_10_conf <= _GEN_10;
if (_GEN_36)
entries_10_age <= _GEN_11;
else if (_GEN_24)
entries_10_age <= _wentry_age_T;
else if (_GEN_34)
entries_10_age <= 3'h7;
else
entries_10_age <= _GEN_11;
if (_GEN_38)
entries_10_p_cnt <= _GEN_12;
else
entries_10_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_10_s_cnt <= 10'h0;
else
entries_10_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_10_s_cnt <= io_update_meta_s_cnt;
else
entries_10_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'hA) begin
entries_10_age <= _GEN_8;
entries_10_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'hB) begin
entries_11_tag <= 10'h0;
entries_11_conf <= 3'h0;
entries_11_age <= 3'h0;
entries_11_p_cnt <= 10'h0;
entries_11_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'hB) begin
if (_GEN_31)
entries_11_tag <= _GEN_9;
else
entries_11_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_11_conf <= 3'h0;
else if (_GEN_17)
entries_11_conf <= _GEN_10;
else if (_GEN_19)
entries_11_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_11_conf <= 3'h0;
else if (_GEN_32)
entries_11_conf <= 3'h1;
else
entries_11_conf <= _GEN_10;
end
else
entries_11_conf <= _GEN_10;
if (_GEN_36)
entries_11_age <= _GEN_11;
else if (_GEN_24)
entries_11_age <= _wentry_age_T;
else if (_GEN_34)
entries_11_age <= 3'h7;
else
entries_11_age <= _GEN_11;
if (_GEN_38)
entries_11_p_cnt <= _GEN_12;
else
entries_11_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_11_s_cnt <= 10'h0;
else
entries_11_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_11_s_cnt <= io_update_meta_s_cnt;
else
entries_11_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'hB) begin
entries_11_age <= _GEN_8;
entries_11_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'hC) begin
entries_12_tag <= 10'h0;
entries_12_conf <= 3'h0;
entries_12_age <= 3'h0;
entries_12_p_cnt <= 10'h0;
entries_12_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'hC) begin
if (_GEN_31)
entries_12_tag <= _GEN_9;
else
entries_12_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_12_conf <= 3'h0;
else if (_GEN_17)
entries_12_conf <= _GEN_10;
else if (_GEN_19)
entries_12_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_12_conf <= 3'h0;
else if (_GEN_32)
entries_12_conf <= 3'h1;
else
entries_12_conf <= _GEN_10;
end
else
entries_12_conf <= _GEN_10;
if (_GEN_36)
entries_12_age <= _GEN_11;
else if (_GEN_24)
entries_12_age <= _wentry_age_T;
else if (_GEN_34)
entries_12_age <= 3'h7;
else
entries_12_age <= _GEN_11;
if (_GEN_38)
entries_12_p_cnt <= _GEN_12;
else
entries_12_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_12_s_cnt <= 10'h0;
else
entries_12_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_12_s_cnt <= io_update_meta_s_cnt;
else
entries_12_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'hC) begin
entries_12_age <= _GEN_8;
entries_12_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'hD) begin
entries_13_tag <= 10'h0;
entries_13_conf <= 3'h0;
entries_13_age <= 3'h0;
entries_13_p_cnt <= 10'h0;
entries_13_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'hD) begin
if (_GEN_31)
entries_13_tag <= _GEN_9;
else
entries_13_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_13_conf <= 3'h0;
else if (_GEN_17)
entries_13_conf <= _GEN_10;
else if (_GEN_19)
entries_13_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_13_conf <= 3'h0;
else if (_GEN_32)
entries_13_conf <= 3'h1;
else
entries_13_conf <= _GEN_10;
end
else
entries_13_conf <= _GEN_10;
if (_GEN_36)
entries_13_age <= _GEN_11;
else if (_GEN_24)
entries_13_age <= _wentry_age_T;
else if (_GEN_34)
entries_13_age <= 3'h7;
else
entries_13_age <= _GEN_11;
if (_GEN_38)
entries_13_p_cnt <= _GEN_12;
else
entries_13_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_13_s_cnt <= 10'h0;
else
entries_13_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_13_s_cnt <= io_update_meta_s_cnt;
else
entries_13_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'hD) begin
entries_13_age <= _GEN_8;
entries_13_s_cnt <= _GEN_6;
end
if (doing_reset & reset_idx == 4'hE) begin
entries_14_tag <= 10'h0;
entries_14_conf <= 3'h0;
entries_14_age <= 3'h0;
entries_14_p_cnt <= 10'h0;
entries_14_s_cnt <= 10'h0;
end
else if (_GEN_42 & io_update_idx[3:0] == 4'hE) begin
if (_GEN_31)
entries_14_tag <= _GEN_9;
else
entries_14_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_14_conf <= 3'h0;
else if (_GEN_17)
entries_14_conf <= _GEN_10;
else if (_GEN_19)
entries_14_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_14_conf <= 3'h0;
else if (_GEN_32)
entries_14_conf <= 3'h1;
else
entries_14_conf <= _GEN_10;
end
else
entries_14_conf <= _GEN_10;
if (_GEN_36)
entries_14_age <= _GEN_11;
else if (_GEN_24)
entries_14_age <= _wentry_age_T;
else if (_GEN_34)
entries_14_age <= 3'h7;
else
entries_14_age <= _GEN_11;
if (_GEN_38)
entries_14_p_cnt <= _GEN_12;
else
entries_14_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_14_s_cnt <= 10'h0;
else
entries_14_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_14_s_cnt <= io_update_meta_s_cnt;
else
entries_14_s_cnt <= _GEN_13;
end
else if (_GEN_7 & f4_idx[3:0] == 4'hE) begin
entries_14_age <= _GEN_8;
entries_14_s_cnt <= _GEN_6;
end
if (doing_reset & (&reset_idx)) begin
entries_15_tag <= 10'h0;
entries_15_conf <= 3'h0;
entries_15_age <= 3'h0;
entries_15_p_cnt <= 10'h0;
entries_15_s_cnt <= 10'h0;
end
else if (_GEN_42 & (&(io_update_idx[3:0]))) begin
if (_GEN_31)
entries_15_tag <= _GEN_9;
else
entries_15_tag <= io_update_idx[13:4];
if (_GEN_14) begin
if (_GEN_15)
entries_15_conf <= 3'h0;
else if (_GEN_17)
entries_15_conf <= _GEN_10;
else if (_GEN_19)
entries_15_conf <= _wentry_conf_T;
else if (_GEN_21)
entries_15_conf <= 3'h0;
else if (_GEN_32)
entries_15_conf <= 3'h1;
else
entries_15_conf <= _GEN_10;
end
else
entries_15_conf <= _GEN_10;
if (_GEN_36)
entries_15_age <= _GEN_11;
else if (_GEN_24)
entries_15_age <= _wentry_age_T;
else if (_GEN_34)
entries_15_age <= 3'h7;
else
entries_15_age <= _GEN_11;
if (_GEN_38)
entries_15_p_cnt <= _GEN_12;
else
entries_15_p_cnt <= io_update_meta_s_cnt;
if (_GEN_14) begin
if (_GEN_37)
entries_15_s_cnt <= 10'h0;
else
entries_15_s_cnt <= _GEN_13;
end
else if (_GEN_41)
entries_15_s_cnt <= io_update_meta_s_cnt;
else
entries_15_s_cnt <= _GEN_13;
end
else if (_GEN_7 & (&(f4_idx[3:0]))) begin
entries_15_age <= _GEN_8;
entries_15_s_cnt <= _GEN_6;
end
f3_entry_tag <= _GEN[io_f2_req_idx[3:0]];
f3_entry_conf <= _GEN_0[io_f2_req_idx[3:0]];
f3_entry_age <= _GEN_1[io_f2_req_idx[3:0]];
f3_entry_p_cnt <= _GEN_2[io_f2_req_idx[3:0]];
f3_entry_s_cnt <= io_update_repair & _GEN_4 ? io_update_meta_s_cnt : io_update_mispredict & _GEN_4 ? 10'h0 : _GEN_3[io_f2_req_idx[3:0]];
f3_scnt_REG <= io_f2_req_idx;
f3_tag <= io_f2_req_idx[13:4];
f4_fire <= io_f3_req_fire;
f4_entry_tag <= f3_entry_tag;
f4_entry_conf <= f3_entry_conf;
f4_entry_age <= f3_entry_age;
f4_entry_p_cnt <= f3_entry_p_cnt;
f4_tag <= f3_tag;
f4_scnt <= f3_scnt;
f4_idx_REG <= io_f2_req_idx;
f4_idx <= f4_idx_REG;
end
assign io_f3_pred = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ^ io_f3_pred_in;
assign io_f3_meta_s_cnt = f3_scnt;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
} | module RoundRawFNToRecFN_e8_s24(
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [9:0] io_in_sExp,
input [26:0] io_in_sig,
input [2:0] io_roundingMode,
output [32:0] io_out,
output [4:0] io_exceptionFlags
);
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24 roundAnyRawFNToRecFN (
.io_invalidExc (io_invalidExc),
.io_in_isNaN (io_in_isNaN),
.io_in_isInf (io_in_isInf),
.io_in_isZero (io_in_isZero),
.io_in_sign (io_in_sign),
.io_in_sExp (io_in_sExp),
.io_in_sig (io_in_sig),
.io_roundingMode (io_roundingMode),
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix}
import scala.math.min
case class BoomBTBParams(
nSets: Int = 128,
nWays: Int = 2,
offsetSz: Int = 13,
extendedNSets: Int = 128
)
class BTBBranchPredictorBank(params: BoomBTBParams = BoomBTBParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
override val nSets = params.nSets
override val nWays = params.nWays
val tagSz = vaddrBitsExtended - log2Ceil(nSets) - log2Ceil(fetchWidth) - 1
val offsetSz = params.offsetSz
val extendedNSets = params.extendedNSets
require(isPow2(nSets))
require(isPow2(extendedNSets) || extendedNSets == 0)
require(extendedNSets <= nSets)
require(extendedNSets >= 1)
class BTBEntry extends Bundle {
val offset = SInt(offsetSz.W)
val extended = Bool()
}
val btbEntrySz = offsetSz + 1
class BTBMeta extends Bundle {
val is_br = Bool()
val tag = UInt(tagSz.W)
}
val btbMetaSz = tagSz + 1
class BTBPredictMeta extends Bundle {
val write_way = UInt(log2Ceil(nWays).W)
}
val s1_meta = Wire(new BTBPredictMeta)
val f3_meta = RegNext(RegNext(s1_meta))
io.f3_meta := f3_meta.asUInt
override val metaSz = s1_meta.asUInt.getWidth
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nSets).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nSets-1).U) { doing_reset := false.B }
val meta = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbMetaSz.W))) }
val btb = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbEntrySz.W))) }
val ebtb = SyncReadMem(extendedNSets, UInt(vaddrBitsExtended.W))
val mems = (((0 until nWays) map ({w:Int => Seq(
(f"btb_meta_way$w", nSets, bankWidth * btbMetaSz),
(f"btb_data_way$w", nSets, bankWidth * btbEntrySz))})).flatten ++ Seq(("ebtb", extendedNSets, vaddrBitsExtended)))
val s1_req_rbtb = VecInit(btb.map { b => VecInit(b.read(s0_idx , s0_valid).map(_.asTypeOf(new BTBEntry))) })
val s1_req_rmeta = VecInit(meta.map { m => VecInit(m.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBMeta))) })
val s1_req_rebtb = ebtb.read(s0_idx, s0_valid)
val s1_req_tag = s1_idx >> log2Ceil(nSets)
val s1_resp = Wire(Vec(bankWidth, Valid(UInt(vaddrBitsExtended.W))))
val s1_is_br = Wire(Vec(bankWidth, Bool()))
val s1_is_jal = Wire(Vec(bankWidth, Bool()))
val s1_hit_ohs = VecInit((0 until bankWidth) map { i =>
VecInit((0 until nWays) map { w =>
s1_req_rmeta(w)(i).tag === s1_req_tag(tagSz-1,0)
})
})
val s1_hits = s1_hit_ohs.map { oh => oh.reduce(_||_) }
val s1_hit_ways = s1_hit_ohs.map { oh => PriorityEncoder(oh) }
for (w <- 0 until bankWidth) {
val entry_meta = s1_req_rmeta(s1_hit_ways(w))(w)
val entry_btb = s1_req_rbtb(s1_hit_ways(w))(w)
s1_resp(w).valid := !doing_reset && s1_valid && s1_hits(w)
s1_resp(w).bits := Mux(
entry_btb.extended,
s1_req_rebtb,
(s1_pc.asSInt + (w << 1).S + entry_btb.offset).asUInt)
s1_is_br(w) := !doing_reset && s1_resp(w).valid && entry_meta.is_br
s1_is_jal(w) := !doing_reset && s1_resp(w).valid && !entry_meta.is_br
io.resp.f2(w) := io.resp_in(0).f2(w)
io.resp.f3(w) := io.resp_in(0).f3(w)
when (RegNext(s1_hits(w))) {
io.resp.f2(w).predicted_pc := RegNext(s1_resp(w))
io.resp.f2(w).is_br := RegNext(s1_is_br(w))
io.resp.f2(w).is_jal := RegNext(s1_is_jal(w))
when (RegNext(s1_is_jal(w))) {
io.resp.f2(w).taken := true.B
}
}
when (RegNext(RegNext(s1_hits(w)))) {
io.resp.f3(w).predicted_pc := RegNext(io.resp.f2(w).predicted_pc)
io.resp.f3(w).is_br := RegNext(io.resp.f2(w).is_br)
io.resp.f3(w).is_jal := RegNext(io.resp.f2(w).is_jal)
when (RegNext(RegNext(s1_is_jal(w)))) {
io.resp.f3(w).taken := true.B
}
}
}
val alloc_way = if (nWays > 1) {
val r_metas = Cat(VecInit(s1_req_rmeta.map { w => VecInit(w.map(_.tag)) }).asUInt, s1_req_tag(tagSz-1,0))
val l = log2Ceil(nWays)
val nChunks = (r_metas.getWidth + l - 1) / l
val chunks = (0 until nChunks) map { i =>
r_metas(min((i+1)*l, r_metas.getWidth)-1, i*l)
}
chunks.reduce(_^_)
} else {
0.U
}
s1_meta.write_way := Mux(s1_hits.reduce(_||_),
PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_|_)),
alloc_way)
val s1_update_cfi_idx = s1_update.bits.cfi_idx.bits
val s1_update_meta = s1_update.bits.meta.asTypeOf(new BTBPredictMeta)
val max_offset_value = Cat(0.B, ~(0.U((offsetSz-1).W))).asSInt
val min_offset_value = Cat(1.B, (0.U((offsetSz-1).W))).asSInt
val new_offset_value = (s1_update.bits.target.asSInt -
(s1_update.bits.pc + (s1_update.bits.cfi_idx.bits << 1)).asSInt)
val offset_is_extended = (new_offset_value > max_offset_value ||
new_offset_value < min_offset_value)
val s1_update_wbtb_data = Wire(new BTBEntry)
s1_update_wbtb_data.extended := offset_is_extended
s1_update_wbtb_data.offset := new_offset_value
val s1_update_wbtb_mask = (UIntToOH(s1_update_cfi_idx) &
Fill(bankWidth, s1_update.bits.cfi_idx.valid && s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.is_commit_update))
val s1_update_wmeta_mask = ((s1_update_wbtb_mask | s1_update.bits.br_mask) &
(Fill(bankWidth, s1_update.valid && s1_update.bits.is_commit_update) |
(Fill(bankWidth, s1_update.valid) & s1_update.bits.btb_mispredicts)
)
)
val s1_update_wmeta_data = Wire(Vec(bankWidth, new BTBMeta))
for (w <- 0 until bankWidth) {
s1_update_wmeta_data(w).tag := Mux(s1_update.bits.btb_mispredicts(w), 0.U, s1_update_idx >> log2Ceil(nSets))
s1_update_wmeta_data(w).is_br := s1_update.bits.br_mask(w)
}
for (w <- 0 until nWays) {
when (doing_reset || s1_update_meta.write_way === w.U || (w == 0 && nWays == 1).B) {
btb(w).write(
Mux(doing_reset,
reset_idx,
s1_update_idx),
Mux(doing_reset,
VecInit(Seq.fill(bankWidth) { 0.U(btbEntrySz.W) }),
VecInit(Seq.fill(bankWidth) { s1_update_wbtb_data.asUInt })),
Mux(doing_reset,
(~(0.U(bankWidth.W))),
s1_update_wbtb_mask).asBools
)
meta(w).write(
Mux(doing_reset,
reset_idx,
s1_update_idx),
Mux(doing_reset,
VecInit(Seq.fill(bankWidth) { 0.U(btbMetaSz.W) }),
VecInit(s1_update_wmeta_data.map(_.asUInt))),
Mux(doing_reset,
(~(0.U(bankWidth.W))),
s1_update_wmeta_mask).asBools
)
}
}
when (s1_update_wbtb_mask =/= 0.U && offset_is_extended) {
ebtb.write(s1_update_idx, s1_update.bits.target)
}
} | module ebtb(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [39:0] R0_data,
input [6:0] W0_addr,
input W0_en,
input W0_clk,
input [39:0] W0_data
);
ebtb_ext ebtb_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Register File (Abstract class and Synthesizable RegFile)
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.exu
import scala.collection.mutable.ArrayBuffer
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix}
/**
* IO bundle for a register read port
*
* @param addrWidth size of register address in bits
* @param dataWidth size of register in bits
*/
class RegisterFileReadPortIO(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
{
val addr = Input(UInt(addrWidth.W))
val data = Output(UInt(dataWidth.W))
}
/**
* IO bundle for the register write port
*
* @param addrWidth size of register address in bits
* @param dataWidth size of register in bits
*/
class RegisterFileWritePort(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
{
val addr = UInt(addrWidth.W)
val data = UInt(dataWidth.W)
}
/**
* Utility function to turn ExeUnitResps to match the regfile's WritePort I/Os.
*/
object WritePort
{
def apply(enq: DecoupledIO[ExeUnitResp], addrWidth: Int, dataWidth: Int, rtype: UInt)
(implicit p: Parameters): Valid[RegisterFileWritePort] = {
val wport = Wire(Valid(new RegisterFileWritePort(addrWidth, dataWidth)))
wport.valid := enq.valid && enq.bits.uop.dst_rtype === rtype
wport.bits.addr := enq.bits.uop.pdst
wport.bits.data := enq.bits.data
enq.ready := true.B
wport
}
}
/**
* Register file abstract class
*
* @param numRegisters number of registers
* @param numReadPorts number of read ports
* @param numWritePorts number of write ports
* @param registerWidth size of registers in bits
* @param bypassableArray list of write ports from func units to the read port of the regfile
*/
abstract class RegisterFile(
numRegisters: Int,
numReadPorts: Int,
numWritePorts: Int,
registerWidth: Int,
bypassableArray: Seq[Boolean]) // which write ports can be bypassed to the read ports?
(implicit p: Parameters) extends BoomModule
{
val io = IO(new BoomBundle {
val read_ports = Vec(numReadPorts, new RegisterFileReadPortIO(maxPregSz, registerWidth))
val write_ports = Flipped(Vec(numWritePorts, Valid(new RegisterFileWritePort(maxPregSz, registerWidth))))
})
private val rf_cost = (numReadPorts + numWritePorts) * (numReadPorts + 2*numWritePorts)
private val type_str = if (registerWidth == fLen+1) "Floating Point" else "Integer"
override def toString: String = BoomCoreStringPrefix(
"==" + type_str + " Regfile==",
"Num RF Read Ports : " + numReadPorts,
"Num RF Write Ports : " + numWritePorts,
"RF Cost (R+W)*(R+2W) : " + rf_cost,
"Bypassable Units : " + bypassableArray)
}
/**
* A synthesizable model of a Register File. You will likely want to blackbox this for more than modest port counts.
*
* @param numRegisters number of registers
* @param numReadPorts number of read ports
* @param numWritePorts number of write ports
* @param registerWidth size of registers in bits
* @param bypassableArray list of write ports from func units to the read port of the regfile
*/
class RegisterFileSynthesizable(
numRegisters: Int,
numReadPorts: Int,
numWritePorts: Int,
registerWidth: Int,
bypassableArray: Seq[Boolean])
(implicit p: Parameters)
extends RegisterFile(numRegisters, numReadPorts, numWritePorts, registerWidth, bypassableArray)
{
// --------------------------------------------------------------
val regfile = Mem(numRegisters, UInt(registerWidth.W))
// --------------------------------------------------------------
// Read ports.
val read_data = Wire(Vec(numReadPorts, UInt(registerWidth.W)))
// Register the read port addresses to give a full cycle to the RegisterRead Stage (if desired).
val read_addrs = io.read_ports.map(p => RegNext(p.addr))
for (i <- 0 until numReadPorts) {
read_data(i) := regfile(read_addrs(i))
}
// --------------------------------------------------------------
// Bypass out of the ALU's write ports.
// We are assuming we cannot bypass a writer to a reader within the regfile memory
// for a write that occurs at the end of cycle S1 and a read that returns data on cycle S1.
// But since these bypasses are expensive, and not all write ports need to bypass their data,
// only perform the w->r bypass on a select number of write ports.
require (bypassableArray.length == io.write_ports.length)
if (bypassableArray.reduce(_||_)) {
val bypassable_wports = ArrayBuffer[Valid[RegisterFileWritePort]]()
io.write_ports zip bypassableArray map { case (wport, b) => if (b) { bypassable_wports += wport} }
for (i <- 0 until numReadPorts) {
val bypass_ens = bypassable_wports.map(x => x.valid &&
x.bits.addr === read_addrs(i))
val bypass_data = Mux1H(VecInit(bypass_ens.toSeq), VecInit(bypassable_wports.map(_.bits.data).toSeq))
io.read_ports(i).data := Mux(bypass_ens.reduce(_|_), bypass_data, read_data(i))
}
} else {
for (i <- 0 until numReadPorts) {
io.read_ports(i).data := read_data(i)
}
}
// --------------------------------------------------------------
// Write ports.
for (wport <- io.write_ports) {
when (wport.valid) {
regfile(wport.bits.addr) := wport.bits.data
}
}
// ensure there is only 1 writer per register (unless to preg0)
if (numWritePorts > 1) {
for (i <- 0 until (numWritePorts - 1)) {
for (j <- (i + 1) until numWritePorts) {
assert(!io.write_ports(i).valid ||
!io.write_ports(j).valid ||
(io.write_ports(i).bits.addr =/= io.write_ports(j).bits.addr) ||
(io.write_ports(i).bits.addr === 0.U), // note: you only have to check one here
"[regfile] too many writers a register")
}
}
}
} | module regfile_48x65(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [64:0] R0_data,
input [5:0] R1_addr,
input R1_en,
input R1_clk,
output [64:0] R1_data,
input [5:0] R2_addr,
input R2_en,
input R2_clk,
output [64:0] R2_data,
input [5:0] W0_addr,
input W0_en,
input W0_clk,
input [64:0] W0_data,
input [5:0] W1_addr,
input W1_en,
input W1_clk,
input [64:0] W1_data
);
reg [64:0] Memory[0:47];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
if (W1_en & 1'h1)
Memory[W1_addr] <= W1_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 65'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 65'bx;
assign R2_data = R2_en ? Memory[R2_addr] : 65'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of
the University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.log2Up
import scala.math._
import consts._
class RecFNToIN(expWidth: Int, sigWidth: Int, intWidth: Int) extends chisel3.Module
{
override def desiredName = s"RecFNToIN_e${expWidth}_s${sigWidth}_i${intWidth}"
val io = IO(new Bundle {
val in = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val signedOut = Input(Bool())
val out = Output(Bits(intWidth.W))
val intExceptionFlags = Output(Bits(3.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawIn = rawFloatFromRecFN(expWidth, sigWidth, io.in)
val magGeOne = rawIn.sExp(expWidth)
val posExp = rawIn.sExp(expWidth - 1, 0)
val magJustBelowOne = !magGeOne && posExp.andR
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
/*------------------------------------------------------------------------
| Assuming the input floating-point value is not a NaN, its magnitude is
| at least 1, and it is not obviously so large as to lead to overflow,
| convert its significand to fixed-point (i.e., with the binary point in a
| fixed location). For a non-NaN input with a magnitude less than 1, this
| expression contrives to ensure that the integer bits of 'alignedSig'
| will all be zeros.
*------------------------------------------------------------------------*/
val shiftedSig =
(magGeOne ## rawIn.sig(sigWidth - 2, 0))<<
Mux(magGeOne,
rawIn.sExp(min(expWidth - 2, log2Up(intWidth) - 1), 0),
0.U
)
val alignedSig =
(shiftedSig>>(sigWidth - 2)) ## shiftedSig(sigWidth - 3, 0).orR
val unroundedInt = 0.U(intWidth.W) | alignedSig>>2
val common_inexact = Mux(magGeOne, alignedSig(1, 0).orR, !rawIn.isZero)
val roundIncr_near_even =
(magGeOne && (alignedSig(2, 1).andR || alignedSig(1, 0).andR)) ||
(magJustBelowOne && alignedSig(1, 0).orR)
val roundIncr_near_maxMag = (magGeOne && alignedSig(1)) || magJustBelowOne
val roundIncr =
(roundingMode_near_even && roundIncr_near_even ) ||
(roundingMode_near_maxMag && roundIncr_near_maxMag) ||
((roundingMode_min || roundingMode_odd) &&
(rawIn.sign && common_inexact)) ||
(roundingMode_max && (!rawIn.sign && common_inexact))
val complUnroundedInt = Mux(rawIn.sign, ~unroundedInt, unroundedInt)
val roundedInt =
Mux(roundIncr ^ rawIn.sign,
complUnroundedInt + 1.U,
complUnroundedInt
) | (roundingMode_odd && common_inexact)
val magGeOne_atOverflowEdge = (posExp === (intWidth - 1).U)
//*** CHANGE TO TAKE BITS FROM THE ORIGINAL 'rawIn.sig' INSTEAD OF FROM
//*** 'unroundedInt'?:
val roundCarryBut2 = unroundedInt(intWidth - 3, 0).andR && roundIncr
val common_overflow =
Mux(magGeOne,
(posExp >= intWidth.U) ||
Mux(io.signedOut,
Mux(rawIn.sign,
magGeOne_atOverflowEdge &&
(unroundedInt(intWidth - 2, 0).orR || roundIncr),
magGeOne_atOverflowEdge ||
((posExp === (intWidth - 2).U) && roundCarryBut2)
),
rawIn.sign ||
(magGeOne_atOverflowEdge &&
unroundedInt(intWidth - 2) && roundCarryBut2)
),
!io.signedOut && rawIn.sign && roundIncr
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val invalidExc = rawIn.isNaN || rawIn.isInf
val overflow = !invalidExc && common_overflow
val inexact = !invalidExc && !common_overflow && common_inexact
val excSign = !rawIn.isNaN && rawIn.sign
val excOut =
Mux((io.signedOut === excSign),
(BigInt(1)<<(intWidth - 1)).U,
0.U
) |
Mux(!excSign, ((BigInt(1)<<(intWidth - 1)) - 1).U, 0.U)
io.out := Mux(invalidExc || common_overflow, excOut, roundedInt)
io.intExceptionFlags := invalidExc ## overflow ## inexact
} | module RecFNToIN_e11_s53_i64(
input [64:0] io_in,
input [2:0] io_roundingMode,
input io_signedOut,
output [63:0] io_out,
output [2:0] io_intExceptionFlags
);
wire rawIn_isNaN = (&(io_in[63:62])) & io_in[61];
wire magJustBelowOne = ~(io_in[63]) & (&(io_in[62:52]));
wire roundingMode_odd = io_roundingMode == 3'h6;
wire [115:0] shiftedSig = {63'h0, io_in[63], io_in[51:0]} << (io_in[63] ? io_in[57:52] : 6'h0);
wire [1:0] _roundIncr_near_even_T_6 = {shiftedSig[51], |(shiftedSig[50:0])};
wire common_inexact = io_in[63] ? (|_roundIncr_near_even_T_6) : (|(io_in[63:61]));
wire roundIncr = io_roundingMode == 3'h0 & (io_in[63] & ((&(shiftedSig[52:51])) | (&_roundIncr_near_even_T_6)) | magJustBelowOne & (|_roundIncr_near_even_T_6)) | io_roundingMode == 3'h4 & (io_in[63] & shiftedSig[51] | magJustBelowOne) | (io_roundingMode == 3'h2 | roundingMode_odd) & io_in[64] & common_inexact | io_roundingMode == 3'h3 & ~(io_in[64]) & common_inexact;
wire [63:0] complUnroundedInt = {64{io_in[64]}} ^ shiftedSig[115:52];
wire [63:0] _roundedInt_T_3 = roundIncr ^ io_in[64] ? complUnroundedInt + 64'h1 : complUnroundedInt;
wire magGeOne_atOverflowEdge = io_in[62:52] == 11'h3F;
wire roundCarryBut2 = (&(shiftedSig[113:52])) & roundIncr;
wire common_overflow = io_in[63] ? (|(io_in[62:58])) | (io_signedOut ? (io_in[64] ? magGeOne_atOverflowEdge & ((|(shiftedSig[114:52])) | roundIncr) : magGeOne_atOverflowEdge | io_in[62:52] == 11'h3E & roundCarryBut2) : io_in[64] | magGeOne_atOverflowEdge & shiftedSig[114] & roundCarryBut2) : ~io_signedOut & io_in[64] & roundIncr;
wire invalidExc = rawIn_isNaN | (&(io_in[63:62])) & ~(io_in[61]);
wire excSign = ~rawIn_isNaN & io_in[64];
assign io_out = invalidExc | common_overflow ? {io_signedOut == excSign, {63{~excSign}}} : {_roundedInt_T_3[63:1], _roundedInt_T_3[0] | roundingMode_odd & common_inexact};
assign io_intExceptionFlags = {invalidExc, ~invalidExc & common_overflow, ~invalidExc & ~common_overflow & common_inexact};
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
package boom.v3.exu
import chisel3._
import chisel3.util._
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile.FPConstants._
import freechips.rocketchip.tile.{FPUCtrlSigs, HasFPUParameters}
import freechips.rocketchip.tile
import freechips.rocketchip.rocket
import freechips.rocketchip.util.uintToBitPat
import boom.v3.common._
import boom.v3.util.{ImmGenRm, ImmGenTyp}
/**
* FP Decoder for the FPU
*
* TODO get rid of this decoder and move into the Decode stage? Or the RRd stage?
* most of these signals are already created, just need to be translated
* to the Rocket FPU-speak
*/
class UOPCodeFPUDecoder(implicit p: Parameters) extends BoomModule with HasFPUParameters
{
val io = IO(new Bundle {
val uopc = Input(Bits(UOPC_SZ.W))
val sigs = Output(new FPUCtrlSigs())
})
// TODO change N,Y,X to BitPat("b1"), BitPat("b0"), and BitPat("b?")
val N = false.B
val Y = true.B
val X = false.B
val default: List[BitPat] = List(X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X)
val f_table: Array[(BitPat, List[BitPat])] =
// Note: not all of these signals are used or necessary, but we're
// constrained by the need to fit the rocket.FPU units' ctrl signals.
// swap12 fma
// | swap32 | div
// | | typeTagIn | | sqrt
// ldst | | | typeTagOut | | wflags
// | wen | | | | from_int | | |
// | | ren1 | | | | | to_int | | |
// | | | ren2 | | | | | | fastpipe |
// | | | | ren3 | | | | | | | | | |
// | | | | | | | | | | | | | | | |
Array(
BitPat(uopFCLASS_S) -> List(X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,N),
BitPat(uopFMV_W_X) -> List(X,X,N,N,N, X,X,S,D,Y,N,N, N,N,N,N),
BitPat(uopFMV_X_W) -> List(X,X,Y,N,N, N,X,D,S,N,Y,N, N,N,N,N),
BitPat(uopFCVT_S_X) -> List(X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y),
BitPat(uopFCVT_X_S) -> List(X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y),
BitPat(uopCMPR_S) -> List(X,X,Y,Y,N, N,N,S,S,N,Y,N, N,N,N,Y),
BitPat(uopFSGNJ_S) -> List(X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,N),
BitPat(uopFMINMAX_S)-> List(X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,Y),
BitPat(uopFADD_S) -> List(X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFSUB_S) -> List(X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFMUL_S) -> List(X,X,Y,Y,N, N,N,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFMADD_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFMSUB_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFNMADD_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y),
BitPat(uopFNMSUB_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y)
)
val d_table: Array[(BitPat, List[BitPat])] =
Array(
BitPat(uopFCLASS_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N),
BitPat(uopFMV_D_X) -> List(X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,N),
BitPat(uopFMV_X_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N),
BitPat(uopFCVT_S_D) -> List(X,X,Y,N,N, N,X,D,S,N,N,Y, N,N,N,Y),
BitPat(uopFCVT_D_S) -> List(X,X,Y,N,N, N,X,S,D,N,N,Y, N,N,N,Y),
BitPat(uopFCVT_D_X) -> List(X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y),
BitPat(uopFCVT_X_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y),
BitPat(uopCMPR_D) -> List(X,X,Y,Y,N, N,N,D,D,N,Y,N, N,N,N,Y),
BitPat(uopFSGNJ_D) -> List(X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,N),
BitPat(uopFMINMAX_D)-> List(X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,Y),
BitPat(uopFADD_D) -> List(X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFSUB_D) -> List(X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFMUL_D) -> List(X,X,Y,Y,N, N,N,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFMADD_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFMSUB_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFNMADD_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y),
BitPat(uopFNMSUB_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y)
)
// val insns = fLen match {
// case 32 => f_table
// case 64 => f_table ++ d_table
// }
val insns = f_table ++ d_table
val decoder = rocket.DecodeLogic(io.uopc, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma,
s.div, s.sqrt, s.wflags)
sigs zip decoder map {case(s,d) => s := d}
s.vec := false.B
}
/**
* FP fused multiple add decoder for the FPU
*/
class FMADecoder extends Module
{
val io = IO(new Bundle {
val uopc = Input(UInt(UOPC_SZ.W))
val cmd = Output(UInt(2.W))
})
val default: List[BitPat] = List(BitPat("b??"))
val table: Array[(BitPat, List[BitPat])] =
Array(
BitPat(uopFADD_S) -> List(BitPat("b00")),
BitPat(uopFSUB_S) -> List(BitPat("b01")),
BitPat(uopFMUL_S) -> List(BitPat("b00")),
BitPat(uopFMADD_S) -> List(BitPat("b00")),
BitPat(uopFMSUB_S) -> List(BitPat("b01")),
BitPat(uopFNMADD_S) -> List(BitPat("b11")),
BitPat(uopFNMSUB_S) -> List(BitPat("b10")),
BitPat(uopFADD_D) -> List(BitPat("b00")),
BitPat(uopFSUB_D) -> List(BitPat("b01")),
BitPat(uopFMUL_D) -> List(BitPat("b00")),
BitPat(uopFMADD_D) -> List(BitPat("b00")),
BitPat(uopFMSUB_D) -> List(BitPat("b01")),
BitPat(uopFNMADD_D) -> List(BitPat("b11")),
BitPat(uopFNMSUB_D) -> List(BitPat("b10"))
)
val decoder = rocket.DecodeLogic(io.uopc, default, table)
val (cmd: UInt) :: Nil = decoder
io.cmd := cmd
}
/**
* Bundle representing data to be sent to the FPU
*/
class FpuReq()(implicit p: Parameters) extends BoomBundle
{
val uop = new MicroOp()
val rs1_data = Bits(65.W)
val rs2_data = Bits(65.W)
val rs3_data = Bits(65.W)
val fcsr_rm = Bits(tile.FPConstants.RM_SZ.W)
}
/**
* FPU unit that wraps the RocketChip FPU units (which in turn wrap hardfloat)
*/
class FPU(implicit p: Parameters) extends BoomModule with tile.HasFPUParameters
{
val io = IO(new Bundle {
val req = Flipped(new ValidIO(new FpuReq))
val resp = new ValidIO(new ExeUnitResp(65))
})
io.resp.bits := DontCare
// all FP units are padded out to the same latency for easy scheduling of the write port
val fpu_latency = dfmaLatency
val io_req = io.req.bits
val fp_decoder = Module(new UOPCodeFPUDecoder)
fp_decoder.io.uopc := io_req.uop.uopc
val fp_ctrl = fp_decoder.io.sigs
val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io_req.fcsr_rm, ImmGenRm(io_req.uop.imm_packed))
def fuInput(minT: Option[tile.FType]): tile.FPInput = {
val req = Wire(new tile.FPInput)
val tag = fp_ctrl.typeTagIn
req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl
req.rm := fp_rm
req.in1 := unbox(io_req.rs1_data, tag, minT)
req.in2 := unbox(io_req.rs2_data, tag, minT)
req.in3 := unbox(io_req.rs3_data, tag, minT)
when (fp_ctrl.swap23) { req.in3 := req.in2 }
req.typ := ImmGenTyp(io_req.uop.imm_packed)
req.fmt := Mux(tag === S, 0.U, 1.U) // TODO support Zfh and avoid special-case below
when (io_req.uop.uopc === uopFMV_X_W) {
req.fmt := 0.U
}
val fma_decoder = Module(new FMADecoder)
fma_decoder.io.uopc := io_req.uop.uopc
req.fmaCmd := fma_decoder.io.cmd // ex_reg_inst(3,2) | (!fp_ctrl.ren3 && ex_reg_inst(27))
req
}
val dfma = Module(new tile.FPUFMAPipe(latency = fpu_latency, t = tile.FType.D))
dfma.io.in.valid := io.req.valid && fp_ctrl.fma && (fp_ctrl.typeTagOut === D)
dfma.io.in.bits := fuInput(Some(dfma.t))
val sfma = Module(new tile.FPUFMAPipe(latency = fpu_latency, t = tile.FType.S))
sfma.io.in.valid := io.req.valid && fp_ctrl.fma && (fp_ctrl.typeTagOut === S)
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new tile.FPToInt)
fpiu.io.in.valid := io.req.valid && (fp_ctrl.toint || (fp_ctrl.fastpipe && fp_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
val fpiu_out = Pipe(RegNext(fpiu.io.in.valid && !fp_ctrl.fastpipe),
fpiu.io.out.bits, fpu_latency-1)
val fpiu_result = Wire(new tile.FPResult)
fpiu_result.data := fpiu_out.bits.toint
fpiu_result.exc := fpiu_out.bits.exc
val fpmu = Module(new tile.FPToFP(fpu_latency)) // latency 2 for rocket
fpmu.io.in.valid := io.req.valid && fp_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val fpmu_double = Pipe(io.req.valid && fp_ctrl.fastpipe, fp_ctrl.typeTagOut === D, fpu_latency).bits
// Response (all FP units have been padded out to the same latency)
io.resp.valid := fpiu_out.valid ||
fpmu.io.out.valid ||
sfma.io.out.valid ||
dfma.io.out.valid
val fpu_out_data =
Mux(dfma.io.out.valid, box(dfma.io.out.bits.data, true.B),
Mux(sfma.io.out.valid, box(sfma.io.out.bits.data, false.B),
Mux(fpiu_out.valid, fpiu_result.data,
box(fpmu.io.out.bits.data, fpmu_double))))
val fpu_out_exc =
Mux(dfma.io.out.valid, dfma.io.out.bits.exc,
Mux(sfma.io.out.valid, sfma.io.out.bits.exc,
Mux(fpiu_out.valid, fpiu_result.exc,
fpmu.io.out.bits.exc)))
io.resp.bits.data := fpu_out_data
io.resp.bits.fflags.valid := io.resp.valid
io.resp.bits.fflags.bits.flags := fpu_out_exc
} | module FMADecoder(
input [6:0] io_uopc,
output [1:0] io_cmd
);
wire [5:0] decoder_decoded_invInputs = ~(io_uopc[5:0]);
assign io_cmd = {|{&{io_uopc[0], io_uopc[1], io_uopc[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]}, &{io_uopc[0], io_uopc[1], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]}}, |{&{decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], decoder_decoded_invInputs[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[0], io_uopc[1], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[1], io_uopc[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[1], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]}}};
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of
the University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.log2Up
import scala.math._
import consts._
class RecFNToIN(expWidth: Int, sigWidth: Int, intWidth: Int) extends chisel3.Module
{
override def desiredName = s"RecFNToIN_e${expWidth}_s${sigWidth}_i${intWidth}"
val io = IO(new Bundle {
val in = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val signedOut = Input(Bool())
val out = Output(Bits(intWidth.W))
val intExceptionFlags = Output(Bits(3.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawIn = rawFloatFromRecFN(expWidth, sigWidth, io.in)
val magGeOne = rawIn.sExp(expWidth)
val posExp = rawIn.sExp(expWidth - 1, 0)
val magJustBelowOne = !magGeOne && posExp.andR
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
/*------------------------------------------------------------------------
| Assuming the input floating-point value is not a NaN, its magnitude is
| at least 1, and it is not obviously so large as to lead to overflow,
| convert its significand to fixed-point (i.e., with the binary point in a
| fixed location). For a non-NaN input with a magnitude less than 1, this
| expression contrives to ensure that the integer bits of 'alignedSig'
| will all be zeros.
*------------------------------------------------------------------------*/
val shiftedSig =
(magGeOne ## rawIn.sig(sigWidth - 2, 0))<<
Mux(magGeOne,
rawIn.sExp(min(expWidth - 2, log2Up(intWidth) - 1), 0),
0.U
)
val alignedSig =
(shiftedSig>>(sigWidth - 2)) ## shiftedSig(sigWidth - 3, 0).orR
val unroundedInt = 0.U(intWidth.W) | alignedSig>>2
val common_inexact = Mux(magGeOne, alignedSig(1, 0).orR, !rawIn.isZero)
val roundIncr_near_even =
(magGeOne && (alignedSig(2, 1).andR || alignedSig(1, 0).andR)) ||
(magJustBelowOne && alignedSig(1, 0).orR)
val roundIncr_near_maxMag = (magGeOne && alignedSig(1)) || magJustBelowOne
val roundIncr =
(roundingMode_near_even && roundIncr_near_even ) ||
(roundingMode_near_maxMag && roundIncr_near_maxMag) ||
((roundingMode_min || roundingMode_odd) &&
(rawIn.sign && common_inexact)) ||
(roundingMode_max && (!rawIn.sign && common_inexact))
val complUnroundedInt = Mux(rawIn.sign, ~unroundedInt, unroundedInt)
val roundedInt =
Mux(roundIncr ^ rawIn.sign,
complUnroundedInt + 1.U,
complUnroundedInt
) | (roundingMode_odd && common_inexact)
val magGeOne_atOverflowEdge = (posExp === (intWidth - 1).U)
//*** CHANGE TO TAKE BITS FROM THE ORIGINAL 'rawIn.sig' INSTEAD OF FROM
//*** 'unroundedInt'?:
val roundCarryBut2 = unroundedInt(intWidth - 3, 0).andR && roundIncr
val common_overflow =
Mux(magGeOne,
(posExp >= intWidth.U) ||
Mux(io.signedOut,
Mux(rawIn.sign,
magGeOne_atOverflowEdge &&
(unroundedInt(intWidth - 2, 0).orR || roundIncr),
magGeOne_atOverflowEdge ||
((posExp === (intWidth - 2).U) && roundCarryBut2)
),
rawIn.sign ||
(magGeOne_atOverflowEdge &&
unroundedInt(intWidth - 2) && roundCarryBut2)
),
!io.signedOut && rawIn.sign && roundIncr
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val invalidExc = rawIn.isNaN || rawIn.isInf
val overflow = !invalidExc && common_overflow
val inexact = !invalidExc && !common_overflow && common_inexact
val excSign = !rawIn.isNaN && rawIn.sign
val excOut =
Mux((io.signedOut === excSign),
(BigInt(1)<<(intWidth - 1)).U,
0.U
) |
Mux(!excSign, ((BigInt(1)<<(intWidth - 1)) - 1).U, 0.U)
io.out := Mux(invalidExc || common_overflow, excOut, roundedInt)
io.intExceptionFlags := invalidExc ## overflow ## inexact
} | module RecFNToIN_e11_s53_i32(
input [64:0] io_in,
input [2:0] io_roundingMode,
input io_signedOut,
output [2:0] io_intExceptionFlags
);
wire magJustBelowOne = ~(io_in[63]) & (&(io_in[62:52]));
wire [83:0] shiftedSig = {31'h0, io_in[63], io_in[51:0]} << (io_in[63] ? io_in[56:52] : 5'h0);
wire [1:0] _roundIncr_near_even_T_6 = {shiftedSig[51], |(shiftedSig[50:0])};
wire common_inexact = io_in[63] ? (|_roundIncr_near_even_T_6) : (|(io_in[63:61]));
wire roundIncr = io_roundingMode == 3'h0 & (io_in[63] & ((&(shiftedSig[52:51])) | (&_roundIncr_near_even_T_6)) | magJustBelowOne & (|_roundIncr_near_even_T_6)) | io_roundingMode == 3'h4 & (io_in[63] & shiftedSig[51] | magJustBelowOne) | (io_roundingMode == 3'h2 | io_roundingMode == 3'h6) & io_in[64] & common_inexact | io_roundingMode == 3'h3 & ~(io_in[64]) & common_inexact;
wire magGeOne_atOverflowEdge = io_in[62:52] == 11'h1F;
wire roundCarryBut2 = (&(shiftedSig[81:52])) & roundIncr;
wire common_overflow = io_in[63] ? (|(io_in[62:57])) | (io_signedOut ? (io_in[64] ? magGeOne_atOverflowEdge & ((|(shiftedSig[82:52])) | roundIncr) : magGeOne_atOverflowEdge | io_in[62:52] == 11'h1E & roundCarryBut2) : io_in[64] | magGeOne_atOverflowEdge & shiftedSig[82] & roundCarryBut2) : ~io_signedOut & io_in[64] & roundIncr;
wire invalidExc = (&(io_in[63:62])) & io_in[61] | (&(io_in[63:62])) & ~(io_in[61]);
assign io_intExceptionFlags = {invalidExc, ~invalidExc & common_overflow, ~invalidExc & ~common_overflow & common_inexact};
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
} | module TageTable_1(
input clock,
input reset,
input io_f1_req_valid,
input [39:0] io_f1_req_pc,
input [63:0] io_f1_req_ghist,
output io_f3_resp_0_valid,
output [2:0] io_f3_resp_0_bits_ctr,
output [1:0] io_f3_resp_0_bits_u,
output io_f3_resp_1_valid,
output [2:0] io_f3_resp_1_bits_ctr,
output [1:0] io_f3_resp_1_bits_u,
output io_f3_resp_2_valid,
output [2:0] io_f3_resp_2_bits_ctr,
output [1:0] io_f3_resp_2_bits_u,
output io_f3_resp_3_valid,
output [2:0] io_f3_resp_3_bits_ctr,
output [1:0] io_f3_resp_3_bits_u,
input io_update_mask_0,
input io_update_mask_1,
input io_update_mask_2,
input io_update_mask_3,
input io_update_taken_0,
input io_update_taken_1,
input io_update_taken_2,
input io_update_taken_3,
input io_update_alloc_0,
input io_update_alloc_1,
input io_update_alloc_2,
input io_update_alloc_3,
input [2:0] io_update_old_ctr_0,
input [2:0] io_update_old_ctr_1,
input [2:0] io_update_old_ctr_2,
input [2:0] io_update_old_ctr_3,
input [39:0] io_update_pc,
input [63:0] io_update_hist,
input io_update_u_mask_0,
input io_update_u_mask_1,
input io_update_u_mask_2,
input io_update_u_mask_3,
input [1:0] io_update_u_0,
input [1:0] io_update_u_1,
input [1:0] io_update_u_2,
input [1:0] io_update_u_3
);
wire update_lo_wdata_3;
wire update_hi_wdata_3;
wire [2:0] update_wdata_3_ctr;
wire update_lo_wdata_2;
wire update_hi_wdata_2;
wire [2:0] update_wdata_2_ctr;
wire update_lo_wdata_1;
wire update_hi_wdata_1;
wire [2:0] update_wdata_1_ctr;
wire update_lo_wdata_0;
wire update_hi_wdata_0;
wire [2:0] update_wdata_0_ctr;
wire lo_us_MPORT_2_data_3;
wire lo_us_MPORT_2_data_2;
wire lo_us_MPORT_2_data_1;
wire lo_us_MPORT_2_data_0;
wire hi_us_MPORT_1_data_3;
wire hi_us_MPORT_1_data_2;
wire hi_us_MPORT_1_data_1;
wire hi_us_MPORT_1_data_0;
wire [10:0] table_MPORT_data_3;
wire [10:0] table_MPORT_data_2;
wire [10:0] table_MPORT_data_1;
wire [10:0] table_MPORT_data_0;
wire [43:0] _table_R0_data;
wire [3:0] _lo_us_R0_data;
wire [3:0] _hi_us_R0_data;
reg doing_reset;
reg [6:0] reset_idx;
wire [6:0] s1_hashed_idx = {io_f1_req_pc[9:7], io_f1_req_pc[6:3] ^ io_f1_req_ghist[3:0]};
reg [6:0] s2_tag;
reg io_f3_resp_0_valid_REG;
reg [1:0] io_f3_resp_0_bits_u_REG;
reg [2:0] io_f3_resp_0_bits_ctr_REG;
reg io_f3_resp_1_valid_REG;
reg [1:0] io_f3_resp_1_bits_u_REG;
reg [2:0] io_f3_resp_1_bits_ctr_REG;
reg io_f3_resp_2_valid_REG;
reg [1:0] io_f3_resp_2_bits_u_REG;
reg [2:0] io_f3_resp_2_bits_ctr_REG;
reg io_f3_resp_3_valid_REG;
reg [1:0] io_f3_resp_3_bits_u_REG;
reg [2:0] io_f3_resp_3_bits_ctr_REG;
reg [18:0] clear_u_ctr;
wire doing_clear_u = clear_u_ctr[10:0] == 11'h0;
wire doing_clear_u_hi = doing_clear_u & clear_u_ctr[18];
wire doing_clear_u_lo = doing_clear_u & ~(clear_u_ctr[18]);
wire [3:0] _GEN = io_update_pc[6:3] ^ io_update_hist[3:0];
wire [6:0] update_idx = {io_update_pc[9:7], _GEN};
wire [3:0] _GEN_0 = io_update_pc[13:10] ^ io_update_hist[3:0];
wire [6:0] update_tag = {io_update_pc[16:14], _GEN_0};
assign table_MPORT_data_0 = doing_reset ? 11'h0 : {1'h1, io_update_pc[16:14], _GEN_0, update_wdata_0_ctr};
assign table_MPORT_data_1 = doing_reset ? 11'h0 : {1'h1, io_update_pc[16:14], _GEN_0, update_wdata_1_ctr};
assign table_MPORT_data_2 = doing_reset ? 11'h0 : {1'h1, io_update_pc[16:14], _GEN_0, update_wdata_2_ctr};
assign table_MPORT_data_3 = doing_reset ? 11'h0 : {1'h1, io_update_pc[16:14], _GEN_0, update_wdata_3_ctr};
wire [6:0] _GEN_1 = {io_update_pc[9:7], _GEN};
wire _GEN_2 = doing_reset | doing_clear_u_hi;
assign hi_us_MPORT_1_data_0 = ~_GEN_2 & update_hi_wdata_0;
assign hi_us_MPORT_1_data_1 = ~_GEN_2 & update_hi_wdata_1;
assign hi_us_MPORT_1_data_2 = ~_GEN_2 & update_hi_wdata_2;
assign hi_us_MPORT_1_data_3 = ~_GEN_2 & update_hi_wdata_3;
wire [3:0] _GEN_3 = {io_update_u_mask_3, io_update_u_mask_2, io_update_u_mask_1, io_update_u_mask_0};
wire _GEN_4 = doing_reset | doing_clear_u_lo;
assign lo_us_MPORT_2_data_0 = ~_GEN_4 & update_lo_wdata_0;
assign lo_us_MPORT_2_data_1 = ~_GEN_4 & update_lo_wdata_1;
assign lo_us_MPORT_2_data_2 = ~_GEN_4 & update_lo_wdata_2;
assign lo_us_MPORT_2_data_3 = ~_GEN_4 & update_lo_wdata_3;
reg [6:0] wrbypass_tags_0;
reg [6:0] wrbypass_tags_1;
reg [6:0] wrbypass_idxs_0;
reg [6:0] wrbypass_idxs_1;
reg [2:0] wrbypass_0_0;
reg [2:0] wrbypass_0_1;
reg [2:0] wrbypass_0_2;
reg [2:0] wrbypass_0_3;
reg [2:0] wrbypass_1_0;
reg [2:0] wrbypass_1_1;
reg [2:0] wrbypass_1_2;
reg [2:0] wrbypass_1_3;
reg wrbypass_enq_idx;
wire wrbypass_hits_0 = ~doing_reset & wrbypass_tags_0 == update_tag & wrbypass_idxs_0 == update_idx;
wire wrbypass_hit = wrbypass_hits_0 | ~doing_reset & wrbypass_tags_1 == update_tag & wrbypass_idxs_1 == update_idx;
wire [2:0] _GEN_5 = wrbypass_hits_0 ? wrbypass_0_0 : wrbypass_1_0;
wire [2:0] _GEN_6 = wrbypass_hits_0 ? wrbypass_0_1 : wrbypass_1_1;
wire [2:0] _GEN_7 = wrbypass_hits_0 ? wrbypass_0_2 : wrbypass_1_2;
wire [2:0] _GEN_8 = wrbypass_hits_0 ? wrbypass_0_3 : wrbypass_1_3;
assign update_wdata_0_ctr = io_update_alloc_0 ? (io_update_taken_0 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_0 ? ((&_GEN_5) ? 3'h7 : _GEN_5 + 3'h1) : _GEN_5 == 3'h0 ? 3'h0 : _GEN_5 - 3'h1) : io_update_taken_0 ? ((&io_update_old_ctr_0) ? 3'h7 : io_update_old_ctr_0 + 3'h1) : io_update_old_ctr_0 == 3'h0 ? 3'h0 : io_update_old_ctr_0 - 3'h1;
assign update_hi_wdata_0 = io_update_u_0[1];
assign update_lo_wdata_0 = io_update_u_0[0];
assign update_wdata_1_ctr = io_update_alloc_1 ? (io_update_taken_1 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_1 ? ((&_GEN_6) ? 3'h7 : _GEN_6 + 3'h1) : _GEN_6 == 3'h0 ? 3'h0 : _GEN_6 - 3'h1) : io_update_taken_1 ? ((&io_update_old_ctr_1) ? 3'h7 : io_update_old_ctr_1 + 3'h1) : io_update_old_ctr_1 == 3'h0 ? 3'h0 : io_update_old_ctr_1 - 3'h1;
assign update_hi_wdata_1 = io_update_u_1[1];
assign update_lo_wdata_1 = io_update_u_1[0];
assign update_wdata_2_ctr = io_update_alloc_2 ? (io_update_taken_2 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_2 ? ((&_GEN_7) ? 3'h7 : _GEN_7 + 3'h1) : _GEN_7 == 3'h0 ? 3'h0 : _GEN_7 - 3'h1) : io_update_taken_2 ? ((&io_update_old_ctr_2) ? 3'h7 : io_update_old_ctr_2 + 3'h1) : io_update_old_ctr_2 == 3'h0 ? 3'h0 : io_update_old_ctr_2 - 3'h1;
assign update_hi_wdata_2 = io_update_u_2[1];
assign update_lo_wdata_2 = io_update_u_2[0];
assign update_wdata_3_ctr = io_update_alloc_3 ? (io_update_taken_3 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_3 ? ((&_GEN_8) ? 3'h7 : _GEN_8 + 3'h1) : _GEN_8 == 3'h0 ? 3'h0 : _GEN_8 - 3'h1) : io_update_taken_3 ? ((&io_update_old_ctr_3) ? 3'h7 : io_update_old_ctr_3 + 3'h1) : io_update_old_ctr_3 == 3'h0 ? 3'h0 : io_update_old_ctr_3 - 3'h1;
assign update_hi_wdata_3 = io_update_u_3[1];
assign update_lo_wdata_3 = io_update_u_3[0];
wire _GEN_9 = io_update_mask_0 | io_update_mask_1 | io_update_mask_2 | io_update_mask_3;
wire _GEN_10 = ~_GEN_9 | wrbypass_hit | wrbypass_enq_idx;
wire _GEN_11 = ~_GEN_9 | wrbypass_hit | ~wrbypass_enq_idx;
always @(posedge clock) begin
if (reset) begin
doing_reset <= 1'h1;
reset_idx <= 7'h0;
clear_u_ctr <= 19'h0;
wrbypass_enq_idx <= 1'h0;
end
else begin
doing_reset <= reset_idx != 7'h7F & doing_reset;
reset_idx <= reset_idx + {6'h0, doing_reset};
clear_u_ctr <= doing_reset ? 19'h1 : clear_u_ctr + 19'h1;
if (~_GEN_9 | wrbypass_hit) begin
end
else
wrbypass_enq_idx <= wrbypass_enq_idx - 1'h1;
end
s2_tag <= {io_f1_req_pc[16:14], io_f1_req_pc[13:10] ^ io_f1_req_ghist[3:0]};
io_f3_resp_0_valid_REG <= _table_R0_data[10] & _table_R0_data[9:3] == s2_tag & ~doing_reset;
io_f3_resp_0_bits_u_REG <= {_hi_us_R0_data[0], _lo_us_R0_data[0]};
io_f3_resp_0_bits_ctr_REG <= _table_R0_data[2:0];
io_f3_resp_1_valid_REG <= _table_R0_data[21] & _table_R0_data[20:14] == s2_tag & ~doing_reset;
io_f3_resp_1_bits_u_REG <= {_hi_us_R0_data[1], _lo_us_R0_data[1]};
io_f3_resp_1_bits_ctr_REG <= _table_R0_data[13:11];
io_f3_resp_2_valid_REG <= _table_R0_data[32] & _table_R0_data[31:25] == s2_tag & ~doing_reset;
io_f3_resp_2_bits_u_REG <= {_hi_us_R0_data[2], _lo_us_R0_data[2]};
io_f3_resp_2_bits_ctr_REG <= _table_R0_data[24:22];
io_f3_resp_3_valid_REG <= _table_R0_data[43] & _table_R0_data[42:36] == s2_tag & ~doing_reset;
io_f3_resp_3_bits_u_REG <= {_hi_us_R0_data[3], _lo_us_R0_data[3]};
io_f3_resp_3_bits_ctr_REG <= _table_R0_data[35:33];
if (_GEN_10) begin
end
else
wrbypass_tags_0 <= update_tag;
if (_GEN_11) begin
end
else
wrbypass_tags_1 <= update_tag;
if (_GEN_10) begin
end
else
wrbypass_idxs_0 <= update_idx;
if (_GEN_11) begin
end
else
wrbypass_idxs_1 <= update_idx;
if (_GEN_9) begin
if (wrbypass_hit) begin
if (wrbypass_hits_0) begin
wrbypass_0_0 <= update_wdata_0_ctr;
wrbypass_0_1 <= update_wdata_1_ctr;
wrbypass_0_2 <= update_wdata_2_ctr;
wrbypass_0_3 <= update_wdata_3_ctr;
end
else begin
wrbypass_1_0 <= update_wdata_0_ctr;
wrbypass_1_1 <= update_wdata_1_ctr;
wrbypass_1_2 <= update_wdata_2_ctr;
wrbypass_1_3 <= update_wdata_3_ctr;
end
end
else if (wrbypass_enq_idx) begin
wrbypass_1_0 <= update_wdata_0_ctr;
wrbypass_1_1 <= update_wdata_1_ctr;
wrbypass_1_2 <= update_wdata_2_ctr;
wrbypass_1_3 <= update_wdata_3_ctr;
end
else begin
wrbypass_0_0 <= update_wdata_0_ctr;
wrbypass_0_1 <= update_wdata_1_ctr;
wrbypass_0_2 <= update_wdata_2_ctr;
wrbypass_0_3 <= update_wdata_3_ctr;
end
end
end
hi_us_0 hi_us (
.R0_addr (s1_hashed_idx),
.R0_en (io_f1_req_valid),
.R0_clk (clock),
.R0_data (_hi_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_ctr[17:11] : _GEN_1),
.W0_clk (clock),
.W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}),
.W0_mask (_GEN_2 ? 4'hF : _GEN_3)
);
lo_us_0 lo_us (
.R0_addr (s1_hashed_idx),
.R0_en (io_f1_req_valid),
.R0_clk (clock),
.R0_data (_lo_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_ctr[17:11] : _GEN_1),
.W0_clk (clock),
.W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}),
.W0_mask (_GEN_4 ? 4'hF : _GEN_3)
);
table_0_0 table_0 (
.R0_addr (s1_hashed_idx),
.R0_en (io_f1_req_valid),
.R0_clk (clock),
.R0_data (_table_R0_data),
.W0_addr (doing_reset ? reset_idx : update_idx),
.W0_clk (clock),
.W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}),
.W0_mask (doing_reset ? 4'hF : {io_update_mask_3, io_update_mask_2, io_update_mask_1, io_update_mask_0})
);
assign io_f3_resp_0_valid = io_f3_resp_0_valid_REG;
assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_REG;
assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_REG;
assign io_f3_resp_1_valid = io_f3_resp_1_valid_REG;
assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_REG;
assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_REG;
assign io_f3_resp_2_valid = io_f3_resp_2_valid_REG;
assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_REG;
assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_REG;
assign io_f3_resp_3_valid = io_f3_resp_3_valid_REG;
assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_REG;
assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_REG;
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Fetch Target Queue (FTQ)
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Each entry in the FTQ holds the fetch address and branch prediction snapshot state.
//
// TODO:
// * reduce port counts.
package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.util.{Str}
import boom.v3.common._
import boom.v3.exu._
import boom.v3.util._
/**
* FTQ Parameters used in configurations
*
* @param nEntries # of entries in the FTQ
*/
case class FtqParameters(
nEntries: Int = 16
)
/**
* Bundle to add to the FTQ RAM and to be used as the pass in IO
*/
class FTQBundle(implicit p: Parameters) extends BoomBundle
with HasBoomFrontendParameters
{
// // TODO compress out high-order bits
// val fetch_pc = UInt(vaddrBitsExtended.W)
// IDX of instruction that was predicted taken, if any
val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W))
// Was the CFI in this bundle found to be taken? or not
val cfi_taken = Bool()
// Was this CFI mispredicted by the branch prediction pipeline?
val cfi_mispredicted = Bool()
// What type of CFI was taken out of this bundle
val cfi_type = UInt(CFI_SZ.W)
// mask of branches which were visible in this fetch bundle
val br_mask = UInt(fetchWidth.W)
// This CFI is likely a CALL
val cfi_is_call = Bool()
// This CFI is likely a RET
val cfi_is_ret = Bool()
// Is the NPC after the CFI +4 or +2
val cfi_npc_plus4 = Bool()
// What was the top of the RAS that this bundle saw?
val ras_top = UInt(vaddrBitsExtended.W)
val ras_idx = UInt(log2Ceil(nRasEntries).W)
// Which bank did this start from?
val start_bank = UInt(1.W)
// // Metadata for the branch predictor
// val bpd_meta = Vec(nBanks, UInt(bpdMaxMetaLength.W))
}
/**
* IO to provide a port for a FunctionalUnit to get the PC of an instruction.
* And for JALRs, the PC of the next instruction.
*/
class GetPCFromFtqIO(implicit p: Parameters) extends BoomBundle
{
val ftq_idx = Input(UInt(log2Ceil(ftqSz).W))
val entry = Output(new FTQBundle)
val ghist = Output(new GlobalHistory)
val pc = Output(UInt(vaddrBitsExtended.W))
val com_pc = Output(UInt(vaddrBitsExtended.W))
// the next_pc may not be valid (stalled or still being fetched)
val next_val = Output(Bool())
val next_pc = Output(UInt(vaddrBitsExtended.W))
}
/**
* Queue to store the fetch PC and other relevant branch predictor signals that are inflight in the
* processor.
*
* @param num_entries # of entries in the FTQ
*/
class FetchTargetQueue(implicit p: Parameters) extends BoomModule
with HasBoomCoreParameters
with HasBoomFrontendParameters
{
val num_entries = ftqSz
private val idx_sz = log2Ceil(num_entries)
val io = IO(new BoomBundle {
// Enqueue one entry for every fetch cycle.
val enq = Flipped(Decoupled(new FetchBundle()))
// Pass to FetchBuffer (newly fetched instructions).
val enq_idx = Output(UInt(idx_sz.W))
// ROB tells us the youngest committed ftq_idx to remove from FTQ.
val deq = Flipped(Valid(UInt(idx_sz.W)))
// Give PC info to BranchUnit.
val get_ftq_pc = Vec(2, new GetPCFromFtqIO())
// Used to regenerate PC for trace port stuff in FireSim
// Don't tape this out, this blows up the FTQ
val debug_ftq_idx = Input(Vec(coreWidth, UInt(log2Ceil(ftqSz).W)))
val debug_fetch_pc = Output(Vec(coreWidth, UInt(vaddrBitsExtended.W)))
val redirect = Input(Valid(UInt(idx_sz.W)))
val brupdate = Input(new BrUpdateInfo)
val bpdupdate = Output(Valid(new BranchPredictionUpdate))
val ras_update = Output(Bool())
val ras_update_idx = Output(UInt(log2Ceil(nRasEntries).W))
val ras_update_pc = Output(UInt(vaddrBitsExtended.W))
})
val bpd_ptr = RegInit(0.U(idx_sz.W))
val deq_ptr = RegInit(0.U(idx_sz.W))
val enq_ptr = RegInit(1.U(idx_sz.W))
val full = ((WrapInc(WrapInc(enq_ptr, num_entries), num_entries) === bpd_ptr) ||
(WrapInc(enq_ptr, num_entries) === bpd_ptr))
val pcs = Reg(Vec(num_entries, UInt(vaddrBitsExtended.W)))
val meta = SyncReadMem(num_entries, Vec(nBanks, UInt(bpdMaxMetaLength.W)))
val ram = Reg(Vec(num_entries, new FTQBundle))
val ghist = Seq.fill(2) { SyncReadMem(num_entries, new GlobalHistory) }
val lhist = if (useLHist) {
Some(SyncReadMem(num_entries, Vec(nBanks, UInt(localHistoryLength.W))))
} else {
None
}
val do_enq = io.enq.fire
// This register lets us initialize the ghist to 0
val prev_ghist = RegInit((0.U).asTypeOf(new GlobalHistory))
val prev_entry = RegInit((0.U).asTypeOf(new FTQBundle))
val prev_pc = RegInit(0.U(vaddrBitsExtended.W))
when (do_enq) {
pcs(enq_ptr) := io.enq.bits.pc
val new_entry = Wire(new FTQBundle)
new_entry.cfi_idx := io.enq.bits.cfi_idx
// Initially, if we see a CFI, it is assumed to be taken.
// Branch resolutions may change this
new_entry.cfi_taken := io.enq.bits.cfi_idx.valid
new_entry.cfi_mispredicted := false.B
new_entry.cfi_type := io.enq.bits.cfi_type
new_entry.cfi_is_call := io.enq.bits.cfi_is_call
new_entry.cfi_is_ret := io.enq.bits.cfi_is_ret
new_entry.cfi_npc_plus4 := io.enq.bits.cfi_npc_plus4
new_entry.ras_top := io.enq.bits.ras_top
new_entry.ras_idx := io.enq.bits.ghist.ras_idx
new_entry.br_mask := io.enq.bits.br_mask & io.enq.bits.mask
new_entry.start_bank := bank(io.enq.bits.pc)
val new_ghist = Mux(io.enq.bits.ghist.current_saw_branch_not_taken,
io.enq.bits.ghist,
prev_ghist.update(
prev_entry.br_mask,
prev_entry.cfi_taken,
prev_entry.br_mask(prev_entry.cfi_idx.bits),
prev_entry.cfi_idx.bits,
prev_entry.cfi_idx.valid,
prev_pc,
prev_entry.cfi_is_call,
prev_entry.cfi_is_ret
)
)
lhist.map( l => l.write(enq_ptr, io.enq.bits.lhist))
ghist.map( g => g.write(enq_ptr, new_ghist))
meta.write(enq_ptr, io.enq.bits.bpd_meta)
ram(enq_ptr) := new_entry
prev_pc := io.enq.bits.pc
prev_entry := new_entry
prev_ghist := new_ghist
enq_ptr := WrapInc(enq_ptr, num_entries)
}
io.enq_idx := enq_ptr
io.bpdupdate.valid := false.B
io.bpdupdate.bits := DontCare
when (io.deq.valid) {
deq_ptr := io.deq.bits
}
// This register avoids a spurious bpd update on the first fetch packet
val first_empty = RegInit(true.B)
// We can update the branch predictors when we know the target of the
// CFI in this fetch bundle
val ras_update = WireInit(false.B)
val ras_update_pc = WireInit(0.U(vaddrBitsExtended.W))
val ras_update_idx = WireInit(0.U(log2Ceil(nRasEntries).W))
io.ras_update := RegNext(ras_update)
io.ras_update_pc := RegNext(ras_update_pc)
io.ras_update_idx := RegNext(ras_update_idx)
val bpd_update_mispredict = RegInit(false.B)
val bpd_update_repair = RegInit(false.B)
val bpd_repair_idx = Reg(UInt(log2Ceil(ftqSz).W))
val bpd_end_idx = Reg(UInt(log2Ceil(ftqSz).W))
val bpd_repair_pc = Reg(UInt(vaddrBitsExtended.W))
val bpd_idx = Mux(io.redirect.valid, io.redirect.bits,
Mux(bpd_update_repair || bpd_update_mispredict, bpd_repair_idx, bpd_ptr))
val bpd_entry = RegNext(ram(bpd_idx))
val bpd_ghist = ghist(0).read(bpd_idx, true.B)
val bpd_lhist = if (useLHist) {
lhist.get.read(bpd_idx, true.B)
} else {
VecInit(Seq.fill(nBanks) { 0.U })
}
val bpd_meta = meta.read(bpd_idx, true.B) // TODO fix these SRAMs
val bpd_pc = RegNext(pcs(bpd_idx))
val bpd_target = RegNext(pcs(WrapInc(bpd_idx, num_entries)))
when (io.redirect.valid) {
bpd_update_mispredict := false.B
bpd_update_repair := false.B
} .elsewhen (RegNext(io.brupdate.b2.mispredict)) {
bpd_update_mispredict := true.B
bpd_repair_idx := RegNext(io.brupdate.b2.uop.ftq_idx)
bpd_end_idx := RegNext(enq_ptr)
} .elsewhen (bpd_update_mispredict) {
bpd_update_mispredict := false.B
bpd_update_repair := true.B
bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)
} .elsewhen (bpd_update_repair && RegNext(bpd_update_mispredict)) {
bpd_repair_pc := bpd_pc
bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)
} .elsewhen (bpd_update_repair) {
bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)
when (WrapInc(bpd_repair_idx, num_entries) === bpd_end_idx ||
bpd_pc === bpd_repair_pc) {
bpd_update_repair := false.B
}
}
val do_commit_update = (!bpd_update_mispredict &&
!bpd_update_repair &&
bpd_ptr =/= deq_ptr &&
enq_ptr =/= WrapInc(bpd_ptr, num_entries) &&
!io.brupdate.b2.mispredict &&
!io.redirect.valid && !RegNext(io.redirect.valid))
val do_mispredict_update = bpd_update_mispredict
val do_repair_update = bpd_update_repair
when (RegNext(do_commit_update || do_repair_update || do_mispredict_update)) {
val cfi_idx = bpd_entry.cfi_idx.bits
val valid_repair = bpd_pc =/= bpd_repair_pc
io.bpdupdate.valid := (!first_empty &&
(bpd_entry.cfi_idx.valid || bpd_entry.br_mask =/= 0.U) &&
!(RegNext(do_repair_update) && !valid_repair))
io.bpdupdate.bits.is_mispredict_update := RegNext(do_mispredict_update)
io.bpdupdate.bits.is_repair_update := RegNext(do_repair_update)
io.bpdupdate.bits.pc := bpd_pc
io.bpdupdate.bits.btb_mispredicts := 0.U
io.bpdupdate.bits.br_mask := Mux(bpd_entry.cfi_idx.valid,
MaskLower(UIntToOH(cfi_idx)) & bpd_entry.br_mask, bpd_entry.br_mask)
io.bpdupdate.bits.cfi_idx := bpd_entry.cfi_idx
io.bpdupdate.bits.cfi_mispredicted := bpd_entry.cfi_mispredicted
io.bpdupdate.bits.cfi_taken := bpd_entry.cfi_taken
io.bpdupdate.bits.target := bpd_target
io.bpdupdate.bits.cfi_is_br := bpd_entry.br_mask(cfi_idx)
io.bpdupdate.bits.cfi_is_jal := bpd_entry.cfi_type === CFI_JAL || bpd_entry.cfi_type === CFI_JALR
io.bpdupdate.bits.ghist := bpd_ghist
io.bpdupdate.bits.lhist := bpd_lhist
io.bpdupdate.bits.meta := bpd_meta
first_empty := false.B
}
when (do_commit_update) {
bpd_ptr := WrapInc(bpd_ptr, num_entries)
}
io.enq.ready := RegNext(!full || do_commit_update)
val redirect_idx = io.redirect.bits
val redirect_entry = ram(redirect_idx)
val redirect_new_entry = WireInit(redirect_entry)
when (io.redirect.valid) {
enq_ptr := WrapInc(io.redirect.bits, num_entries)
when (io.brupdate.b2.mispredict) {
val new_cfi_idx = (io.brupdate.b2.uop.pc_lob ^
Mux(redirect_entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U))(log2Ceil(fetchWidth), 1)
redirect_new_entry.cfi_idx.valid := true.B
redirect_new_entry.cfi_idx.bits := new_cfi_idx
redirect_new_entry.cfi_mispredicted := true.B
redirect_new_entry.cfi_taken := io.brupdate.b2.taken
redirect_new_entry.cfi_is_call := redirect_entry.cfi_is_call && redirect_entry.cfi_idx.bits === new_cfi_idx
redirect_new_entry.cfi_is_ret := redirect_entry.cfi_is_ret && redirect_entry.cfi_idx.bits === new_cfi_idx
}
ras_update := true.B
ras_update_pc := redirect_entry.ras_top
ras_update_idx := redirect_entry.ras_idx
} .elsewhen (RegNext(io.redirect.valid)) {
prev_entry := RegNext(redirect_new_entry)
prev_ghist := bpd_ghist
prev_pc := bpd_pc
ram(RegNext(io.redirect.bits)) := RegNext(redirect_new_entry)
}
//-------------------------------------------------------------
// **** Core Read PCs ****
//-------------------------------------------------------------
for (i <- 0 until 2) {
val idx = io.get_ftq_pc(i).ftq_idx
val next_idx = WrapInc(idx, num_entries)
val next_is_enq = (next_idx === enq_ptr) && io.enq.fire
val next_pc = Mux(next_is_enq, io.enq.bits.pc, pcs(next_idx))
val get_entry = ram(idx)
val next_entry = ram(next_idx)
io.get_ftq_pc(i).entry := RegNext(get_entry)
if (i == 1)
io.get_ftq_pc(i).ghist := ghist(1).read(idx, true.B)
else
io.get_ftq_pc(i).ghist := DontCare
io.get_ftq_pc(i).pc := RegNext(pcs(idx))
io.get_ftq_pc(i).next_pc := RegNext(next_pc)
io.get_ftq_pc(i).next_val := RegNext(next_idx =/= enq_ptr || next_is_enq)
io.get_ftq_pc(i).com_pc := RegNext(pcs(Mux(io.deq.valid, io.deq.bits, deq_ptr)))
}
for (w <- 0 until coreWidth) {
io.debug_fetch_pc(w) := RegNext(pcs(io.debug_ftq_idx(w)))
}
} | module ghist_1(
input [3:0] R0_addr,
input R0_clk,
output [71:0] R0_data,
input [3:0] W0_addr,
input W0_en,
input W0_clk,
input [71:0] W0_data
);
ghist_0_ext ghist_0_ext (
.R0_addr (R0_addr),
.R0_en (1'h1),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat, log2Up, log2Ceil, log2Floor, Log2, Decoupled, Enum, Fill, Valid, Pipe}
import freechips.rocketchip.util._
import ALU._
class MultiplierReq(dataBits: Int, tagBits: Int) extends Bundle {
val fn = Bits(SZ_ALU_FN.W)
val dw = Bits(SZ_DW.W)
val in1 = Bits(dataBits.W)
val in2 = Bits(dataBits.W)
val tag = UInt(tagBits.W)
}
class MultiplierResp(dataBits: Int, tagBits: Int) extends Bundle {
val data = Bits(dataBits.W)
val full_data = Bits((2*dataBits).W)
val tag = UInt(tagBits.W)
}
class MultiplierIO(val dataBits: Int, val tagBits: Int) extends Bundle {
val req = Flipped(Decoupled(new MultiplierReq(dataBits, tagBits)))
val kill = Input(Bool())
val resp = Decoupled(new MultiplierResp(dataBits, tagBits))
}
case class MulDivParams(
mulUnroll: Int = 1,
divUnroll: Int = 1,
mulEarlyOut: Boolean = false,
divEarlyOut: Boolean = false,
divEarlyOutGranularity: Int = 1
)
class MulDiv(cfg: MulDivParams, width: Int, nXpr: Int = 32) extends Module {
private def minDivLatency = (cfg.divUnroll > 0).option(if (cfg.divEarlyOut) 3 else 1 + w/cfg.divUnroll)
private def minMulLatency = (cfg.mulUnroll > 0).option(if (cfg.mulEarlyOut) 2 else w/cfg.mulUnroll)
def minLatency: Int = (minDivLatency ++ minMulLatency).min
val io = IO(new MultiplierIO(width, log2Up(nXpr)))
val w = io.req.bits.in1.getWidth
val mulw = if (cfg.mulUnroll == 0) w else (w + cfg.mulUnroll - 1) / cfg.mulUnroll * cfg.mulUnroll
val fastMulW = if (cfg.mulUnroll == 0) false else w/2 > cfg.mulUnroll && w % (2*cfg.mulUnroll) == 0
val s_ready :: s_neg_inputs :: s_mul :: s_div :: s_dummy :: s_neg_output :: s_done_mul :: s_done_div :: Nil = Enum(8)
val state = RegInit(s_ready)
val req = Reg(chiselTypeOf(io.req.bits))
val count = Reg(UInt(log2Ceil(
((cfg.divUnroll != 0).option(w/cfg.divUnroll + 1).toSeq ++
(cfg.mulUnroll != 0).option(mulw/cfg.mulUnroll)).reduce(_ max _)).W))
val neg_out = Reg(Bool())
val isHi = Reg(Bool())
val resHi = Reg(Bool())
val divisor = Reg(Bits((w+1).W)) // div only needs w bits
val remainder = Reg(Bits((2*mulw+2).W)) // div only needs 2*w+1 bits
val mulDecode = List(
FN_MUL -> List(Y, N, X, X),
FN_MULH -> List(Y, Y, Y, Y),
FN_MULHU -> List(Y, Y, N, N),
FN_MULHSU -> List(Y, Y, Y, N))
val divDecode = List(
FN_DIV -> List(N, N, Y, Y),
FN_REM -> List(N, Y, Y, Y),
FN_DIVU -> List(N, N, N, N),
FN_REMU -> List(N, Y, N, N))
val cmdMul :: cmdHi :: lhsSigned :: rhsSigned :: Nil =
DecodeLogic(io.req.bits.fn, List(X, X, X, X),
(if (cfg.divUnroll != 0) divDecode else Nil) ++ (if (cfg.mulUnroll != 0) mulDecode else Nil)).map(_.asBool)
require(w == 32 || w == 64)
def halfWidth(req: MultiplierReq) = (w > 32).B && req.dw === DW_32
def sext(x: Bits, halfW: Bool, signed: Bool) = {
val sign = signed && Mux(halfW, x(w/2-1), x(w-1))
val hi = Mux(halfW, Fill(w/2, sign), x(w-1,w/2))
(Cat(hi, x(w/2-1,0)), sign)
}
val (lhs_in, lhs_sign) = sext(io.req.bits.in1, halfWidth(io.req.bits), lhsSigned)
val (rhs_in, rhs_sign) = sext(io.req.bits.in2, halfWidth(io.req.bits), rhsSigned)
val subtractor = remainder(2*w,w) - divisor
val result = Mux(resHi, remainder(2*w, w+1), remainder(w-1, 0))
val negated_remainder = -result
if (cfg.divUnroll != 0) when (state === s_neg_inputs) {
when (remainder(w-1)) {
remainder := negated_remainder
}
when (divisor(w-1)) {
divisor := subtractor
}
state := s_div
}
if (cfg.divUnroll != 0) when (state === s_neg_output) {
remainder := negated_remainder
state := s_done_div
resHi := false.B
}
if (cfg.mulUnroll != 0) when (state === s_mul) {
val mulReg = Cat(remainder(2*mulw+1,w+1),remainder(w-1,0))
val mplierSign = remainder(w)
val mplier = mulReg(mulw-1,0)
val accum = mulReg(2*mulw,mulw).asSInt
val mpcand = divisor.asSInt
val prod = Cat(mplierSign, mplier(cfg.mulUnroll-1, 0)).asSInt * mpcand + accum
val nextMulReg = Cat(prod, mplier(mulw-1, cfg.mulUnroll))
val nextMplierSign = count === (mulw/cfg.mulUnroll-2).U && neg_out
val eOutMask = ((BigInt(-1) << mulw).S >> (count * cfg.mulUnroll.U)(log2Up(mulw)-1,0))(mulw-1,0)
val eOut = (cfg.mulEarlyOut).B && count =/= (mulw/cfg.mulUnroll-1).U && count =/= 0.U &&
!isHi && (mplier & ~eOutMask) === 0.U
val eOutRes = (mulReg >> (mulw.U - count * cfg.mulUnroll.U)(log2Up(mulw)-1,0))
val nextMulReg1 = Cat(nextMulReg(2*mulw,mulw), Mux(eOut, eOutRes, nextMulReg)(mulw-1,0))
remainder := Cat(nextMulReg1 >> w, nextMplierSign, nextMulReg1(w-1,0))
count := count + 1.U
when (eOut || count === (mulw/cfg.mulUnroll-1).U) {
state := s_done_mul
resHi := isHi
}
}
if (cfg.divUnroll != 0) when (state === s_div) {
val unrolls = ((0 until cfg.divUnroll) scanLeft remainder) { case (rem, i) =>
// the special case for iteration 0 is to save HW, not for correctness
val difference = if (i == 0) subtractor else rem(2*w,w) - divisor(w-1,0)
val less = difference(w)
Cat(Mux(less, rem(2*w-1,w), difference(w-1,0)), rem(w-1,0), !less)
}.tail
remainder := unrolls.last
when (count === (w/cfg.divUnroll).U) {
state := Mux(neg_out, s_neg_output, s_done_div)
resHi := isHi
if (w % cfg.divUnroll < cfg.divUnroll - 1)
remainder := unrolls(w % cfg.divUnroll)
}
count := count + 1.U
val divby0 = count === 0.U && !subtractor(w)
if (cfg.divEarlyOut) {
val align = 1 << log2Floor(cfg.divUnroll max cfg.divEarlyOutGranularity)
val alignMask = ~((align-1).U(log2Ceil(w).W))
val divisorMSB = Log2(divisor(w-1,0), w) & alignMask
val dividendMSB = Log2(remainder(w-1,0), w) | ~alignMask
val eOutPos = ~(dividendMSB - divisorMSB)
val eOut = count === 0.U && !divby0 && eOutPos >= align.U
when (eOut) {
remainder := remainder(w-1,0) << eOutPos
count := eOutPos >> log2Floor(cfg.divUnroll)
}
}
when (divby0 && !isHi) { neg_out := false.B }
}
when (io.resp.fire || io.kill) {
state := s_ready
}
when (io.req.fire) {
state := Mux(cmdMul, s_mul, Mux(lhs_sign || rhs_sign, s_neg_inputs, s_div))
isHi := cmdHi
resHi := false.B
count := (if (fastMulW) Mux[UInt](cmdMul && halfWidth(io.req.bits), (w/cfg.mulUnroll/2).U, 0.U) else 0.U)
neg_out := Mux(cmdHi, lhs_sign, lhs_sign =/= rhs_sign)
divisor := Cat(rhs_sign, rhs_in)
remainder := lhs_in
req := io.req.bits
}
val outMul = (state & (s_done_mul ^ s_done_div)) === (s_done_mul & ~s_done_div)
val loOut = Mux(fastMulW.B && halfWidth(req) && outMul, result(w-1,w/2), result(w/2-1,0))
val hiOut = Mux(halfWidth(req), Fill(w/2, loOut(w/2-1)), result(w-1,w/2))
io.resp.bits.tag := req.tag
io.resp.bits.data := Cat(hiOut, loOut)
io.resp.bits.full_data := Cat(remainder(2*w, w+1), remainder(w-1, 0))
io.resp.valid := (state === s_done_mul || state === s_done_div)
io.req.ready := state === s_ready
}
class PipelinedMultiplier(width: Int, latency: Int, nXpr: Int = 32) extends Module with ShouldBeRetimed {
val io = IO(new Bundle {
val req = Flipped(Valid(new MultiplierReq(width, log2Ceil(nXpr))))
val resp = Valid(new MultiplierResp(width, log2Ceil(nXpr)))
})
val in = Pipe(io.req)
val decode = List(
FN_MUL -> List(N, X, X),
FN_MULH -> List(Y, Y, Y),
FN_MULHU -> List(Y, N, N),
FN_MULHSU -> List(Y, Y, N))
val cmdHi :: lhsSigned :: rhsSigned :: Nil =
DecodeLogic(in.bits.fn, List(X, X, X), decode).map(_.asBool)
val cmdHalf = (width > 32).B && in.bits.dw === DW_32
val lhs = Cat(lhsSigned && in.bits.in1(width-1), in.bits.in1).asSInt
val rhs = Cat(rhsSigned && in.bits.in2(width-1), in.bits.in2).asSInt
val prod = lhs * rhs
val muxed = Mux(cmdHi, prod(2*width-1, width), Mux(cmdHalf, prod(width/2-1, 0).sextTo(width), prod(width-1, 0)))
val resp = Pipe(in, latency-1)
io.resp.valid := resp.valid
io.resp.bits.tag := resp.bits.tag
io.resp.bits.data := Pipe(in.valid, muxed, latency-1).bits
io.resp.bits.full_data := Pipe(in.valid, prod, latency-1).bits.asUInt
} | module PipelinedMultiplier(
input clock,
input reset,
input io_req_valid,
input [4:0] io_req_bits_fn,
input io_req_bits_dw,
input [63:0] io_req_bits_in1,
input [63:0] io_req_bits_in2,
output [63:0] io_resp_bits_data
);
reg in_pipe_v;
reg [4:0] in_pipe_b_fn;
reg in_pipe_b_dw;
reg [63:0] in_pipe_b_in1;
reg [63:0] in_pipe_b_in2;
reg io_resp_bits_data_pipe_v;
reg [63:0] io_resp_bits_data_pipe_b;
reg [63:0] io_resp_bits_data_pipe_pipe_b;
wire [1:0] decoded_invInputs = ~(in_pipe_b_fn[1:0]);
wire [127:0] prod = {{64{(|{decoded_invInputs[1], &{decoded_invInputs[0], in_pipe_b_fn[1]}}) & in_pipe_b_in1[63]}}, in_pipe_b_in1} * {{64{decoded_invInputs[1] & in_pipe_b_in2[63]}}, in_pipe_b_in2};
always @(posedge clock) begin
if (reset) begin
in_pipe_v <= 1'h0;
io_resp_bits_data_pipe_v <= 1'h0;
end
else begin
in_pipe_v <= io_req_valid;
io_resp_bits_data_pipe_v <= in_pipe_v;
end
if (io_req_valid) begin
in_pipe_b_fn <= io_req_bits_fn;
in_pipe_b_dw <= io_req_bits_dw;
in_pipe_b_in1 <= io_req_bits_in1;
in_pipe_b_in2 <= io_req_bits_in2;
end
if (in_pipe_v)
io_resp_bits_data_pipe_b <= (|{in_pipe_b_fn[0], in_pipe_b_fn[1]}) ? prod[127:64] : in_pipe_b_dw ? prod[63:0] : {{32{prod[31]}}, prod[31:0]};
if (io_resp_bits_data_pipe_v)
io_resp_bits_data_pipe_pipe_b <= io_resp_bits_data_pipe_b;
end
assign io_resp_bits_data = io_resp_bits_data_pipe_pipe_b;
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
} | module TageTable_5(
input clock,
input reset,
input io_f1_req_valid,
input [39:0] io_f1_req_pc,
input [63:0] io_f1_req_ghist,
output io_f3_resp_0_valid,
output [2:0] io_f3_resp_0_bits_ctr,
output [1:0] io_f3_resp_0_bits_u,
output io_f3_resp_1_valid,
output [2:0] io_f3_resp_1_bits_ctr,
output [1:0] io_f3_resp_1_bits_u,
output io_f3_resp_2_valid,
output [2:0] io_f3_resp_2_bits_ctr,
output [1:0] io_f3_resp_2_bits_u,
output io_f3_resp_3_valid,
output [2:0] io_f3_resp_3_bits_ctr,
output [1:0] io_f3_resp_3_bits_u,
input io_update_mask_0,
input io_update_mask_1,
input io_update_mask_2,
input io_update_mask_3,
input io_update_taken_0,
input io_update_taken_1,
input io_update_taken_2,
input io_update_taken_3,
input io_update_alloc_0,
input io_update_alloc_1,
input io_update_alloc_2,
input io_update_alloc_3,
input [2:0] io_update_old_ctr_0,
input [2:0] io_update_old_ctr_1,
input [2:0] io_update_old_ctr_2,
input [2:0] io_update_old_ctr_3,
input [39:0] io_update_pc,
input [63:0] io_update_hist,
input io_update_u_mask_0,
input io_update_u_mask_1,
input io_update_u_mask_2,
input io_update_u_mask_3,
input [1:0] io_update_u_0,
input [1:0] io_update_u_1,
input [1:0] io_update_u_2,
input [1:0] io_update_u_3
);
wire update_lo_wdata_3;
wire update_hi_wdata_3;
wire [2:0] update_wdata_3_ctr;
wire update_lo_wdata_2;
wire update_hi_wdata_2;
wire [2:0] update_wdata_2_ctr;
wire update_lo_wdata_1;
wire update_hi_wdata_1;
wire [2:0] update_wdata_1_ctr;
wire update_lo_wdata_0;
wire update_hi_wdata_0;
wire [2:0] update_wdata_0_ctr;
wire lo_us_MPORT_2_data_3;
wire lo_us_MPORT_2_data_2;
wire lo_us_MPORT_2_data_1;
wire lo_us_MPORT_2_data_0;
wire hi_us_MPORT_1_data_3;
wire hi_us_MPORT_1_data_2;
wire hi_us_MPORT_1_data_1;
wire hi_us_MPORT_1_data_0;
wire [12:0] table_MPORT_data_3;
wire [12:0] table_MPORT_data_2;
wire [12:0] table_MPORT_data_1;
wire [12:0] table_MPORT_data_0;
wire [51:0] _table_R0_data;
wire [3:0] _lo_us_R0_data;
wire [3:0] _hi_us_R0_data;
reg doing_reset;
reg [6:0] reset_idx;
wire [6:0] _idx_history_T_7 = io_f1_req_ghist[6:0] ^ io_f1_req_ghist[13:7] ^ io_f1_req_ghist[20:14] ^ io_f1_req_ghist[27:21] ^ io_f1_req_ghist[34:28] ^ io_f1_req_ghist[41:35] ^ io_f1_req_ghist[48:42] ^ io_f1_req_ghist[55:49] ^ io_f1_req_ghist[62:56];
wire [6:0] s1_hashed_idx = io_f1_req_pc[9:3] ^ {_idx_history_T_7[6:1], _idx_history_T_7[0] ^ io_f1_req_ghist[63]};
reg [8:0] s2_tag;
reg io_f3_resp_0_valid_REG;
reg [1:0] io_f3_resp_0_bits_u_REG;
reg [2:0] io_f3_resp_0_bits_ctr_REG;
reg io_f3_resp_1_valid_REG;
reg [1:0] io_f3_resp_1_bits_u_REG;
reg [2:0] io_f3_resp_1_bits_ctr_REG;
reg io_f3_resp_2_valid_REG;
reg [1:0] io_f3_resp_2_bits_u_REG;
reg [2:0] io_f3_resp_2_bits_ctr_REG;
reg io_f3_resp_3_valid_REG;
reg [1:0] io_f3_resp_3_bits_u_REG;
reg [2:0] io_f3_resp_3_bits_ctr_REG;
reg [18:0] clear_u_ctr;
wire doing_clear_u = clear_u_ctr[10:0] == 11'h0;
wire doing_clear_u_hi = doing_clear_u & clear_u_ctr[18];
wire doing_clear_u_lo = doing_clear_u & ~(clear_u_ctr[18]);
wire [6:0] _idx_history_T_15 = io_update_hist[6:0] ^ io_update_hist[13:7] ^ io_update_hist[20:14] ^ io_update_hist[27:21] ^ io_update_hist[34:28] ^ io_update_hist[41:35] ^ io_update_hist[48:42] ^ io_update_hist[55:49] ^ io_update_hist[62:56];
wire [6:0] update_idx = io_update_pc[9:3] ^ {_idx_history_T_15[6:1], _idx_history_T_15[0] ^ io_update_hist[63]};
wire [8:0] _tag_history_T_11 = io_update_hist[8:0] ^ io_update_hist[17:9] ^ io_update_hist[26:18] ^ io_update_hist[35:27] ^ io_update_hist[44:36] ^ io_update_hist[53:45] ^ io_update_hist[62:54];
wire [8:0] update_tag = io_update_pc[18:10] ^ {_tag_history_T_11[8:1], _tag_history_T_11[0] ^ io_update_hist[63]};
assign table_MPORT_data_0 = doing_reset ? 13'h0 : {1'h1, update_tag, update_wdata_0_ctr};
assign table_MPORT_data_1 = doing_reset ? 13'h0 : {1'h1, update_tag, update_wdata_1_ctr};
assign table_MPORT_data_2 = doing_reset ? 13'h0 : {1'h1, update_tag, update_wdata_2_ctr};
assign table_MPORT_data_3 = doing_reset ? 13'h0 : {1'h1, update_tag, update_wdata_3_ctr};
wire _GEN = doing_reset | doing_clear_u_hi;
assign hi_us_MPORT_1_data_0 = ~_GEN & update_hi_wdata_0;
assign hi_us_MPORT_1_data_1 = ~_GEN & update_hi_wdata_1;
assign hi_us_MPORT_1_data_2 = ~_GEN & update_hi_wdata_2;
assign hi_us_MPORT_1_data_3 = ~_GEN & update_hi_wdata_3;
wire [3:0] _GEN_0 = {io_update_u_mask_3, io_update_u_mask_2, io_update_u_mask_1, io_update_u_mask_0};
wire _GEN_1 = doing_reset | doing_clear_u_lo;
assign lo_us_MPORT_2_data_0 = ~_GEN_1 & update_lo_wdata_0;
assign lo_us_MPORT_2_data_1 = ~_GEN_1 & update_lo_wdata_1;
assign lo_us_MPORT_2_data_2 = ~_GEN_1 & update_lo_wdata_2;
assign lo_us_MPORT_2_data_3 = ~_GEN_1 & update_lo_wdata_3;
reg [8:0] wrbypass_tags_0;
reg [8:0] wrbypass_tags_1;
reg [6:0] wrbypass_idxs_0;
reg [6:0] wrbypass_idxs_1;
reg [2:0] wrbypass_0_0;
reg [2:0] wrbypass_0_1;
reg [2:0] wrbypass_0_2;
reg [2:0] wrbypass_0_3;
reg [2:0] wrbypass_1_0;
reg [2:0] wrbypass_1_1;
reg [2:0] wrbypass_1_2;
reg [2:0] wrbypass_1_3;
reg wrbypass_enq_idx;
wire wrbypass_hits_0 = ~doing_reset & wrbypass_tags_0 == update_tag & wrbypass_idxs_0 == update_idx;
wire wrbypass_hit = wrbypass_hits_0 | ~doing_reset & wrbypass_tags_1 == update_tag & wrbypass_idxs_1 == update_idx;
wire [2:0] _GEN_2 = wrbypass_hits_0 ? wrbypass_0_0 : wrbypass_1_0;
wire [2:0] _GEN_3 = wrbypass_hits_0 ? wrbypass_0_1 : wrbypass_1_1;
wire [2:0] _GEN_4 = wrbypass_hits_0 ? wrbypass_0_2 : wrbypass_1_2;
wire [2:0] _GEN_5 = wrbypass_hits_0 ? wrbypass_0_3 : wrbypass_1_3;
assign update_wdata_0_ctr = io_update_alloc_0 ? (io_update_taken_0 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_0 ? ((&_GEN_2) ? 3'h7 : _GEN_2 + 3'h1) : _GEN_2 == 3'h0 ? 3'h0 : _GEN_2 - 3'h1) : io_update_taken_0 ? ((&io_update_old_ctr_0) ? 3'h7 : io_update_old_ctr_0 + 3'h1) : io_update_old_ctr_0 == 3'h0 ? 3'h0 : io_update_old_ctr_0 - 3'h1;
assign update_hi_wdata_0 = io_update_u_0[1];
assign update_lo_wdata_0 = io_update_u_0[0];
assign update_wdata_1_ctr = io_update_alloc_1 ? (io_update_taken_1 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_1 ? ((&_GEN_3) ? 3'h7 : _GEN_3 + 3'h1) : _GEN_3 == 3'h0 ? 3'h0 : _GEN_3 - 3'h1) : io_update_taken_1 ? ((&io_update_old_ctr_1) ? 3'h7 : io_update_old_ctr_1 + 3'h1) : io_update_old_ctr_1 == 3'h0 ? 3'h0 : io_update_old_ctr_1 - 3'h1;
assign update_hi_wdata_1 = io_update_u_1[1];
assign update_lo_wdata_1 = io_update_u_1[0];
assign update_wdata_2_ctr = io_update_alloc_2 ? (io_update_taken_2 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_2 ? ((&_GEN_4) ? 3'h7 : _GEN_4 + 3'h1) : _GEN_4 == 3'h0 ? 3'h0 : _GEN_4 - 3'h1) : io_update_taken_2 ? ((&io_update_old_ctr_2) ? 3'h7 : io_update_old_ctr_2 + 3'h1) : io_update_old_ctr_2 == 3'h0 ? 3'h0 : io_update_old_ctr_2 - 3'h1;
assign update_hi_wdata_2 = io_update_u_2[1];
assign update_lo_wdata_2 = io_update_u_2[0];
assign update_wdata_3_ctr = io_update_alloc_3 ? (io_update_taken_3 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_3 ? ((&_GEN_5) ? 3'h7 : _GEN_5 + 3'h1) : _GEN_5 == 3'h0 ? 3'h0 : _GEN_5 - 3'h1) : io_update_taken_3 ? ((&io_update_old_ctr_3) ? 3'h7 : io_update_old_ctr_3 + 3'h1) : io_update_old_ctr_3 == 3'h0 ? 3'h0 : io_update_old_ctr_3 - 3'h1;
assign update_hi_wdata_3 = io_update_u_3[1];
assign update_lo_wdata_3 = io_update_u_3[0];
wire [8:0] _tag_history_T_5 = io_f1_req_ghist[8:0] ^ io_f1_req_ghist[17:9] ^ io_f1_req_ghist[26:18] ^ io_f1_req_ghist[35:27] ^ io_f1_req_ghist[44:36] ^ io_f1_req_ghist[53:45] ^ io_f1_req_ghist[62:54];
wire _GEN_6 = io_update_mask_0 | io_update_mask_1 | io_update_mask_2 | io_update_mask_3;
wire _GEN_7 = ~_GEN_6 | wrbypass_hit | wrbypass_enq_idx;
wire _GEN_8 = ~_GEN_6 | wrbypass_hit | ~wrbypass_enq_idx;
always @(posedge clock) begin
if (reset) begin
doing_reset <= 1'h1;
reset_idx <= 7'h0;
clear_u_ctr <= 19'h0;
wrbypass_enq_idx <= 1'h0;
end
else begin
doing_reset <= reset_idx != 7'h7F & doing_reset;
reset_idx <= reset_idx + {6'h0, doing_reset};
clear_u_ctr <= doing_reset ? 19'h1 : clear_u_ctr + 19'h1;
if (~_GEN_6 | wrbypass_hit) begin
end
else
wrbypass_enq_idx <= wrbypass_enq_idx - 1'h1;
end
s2_tag <= io_f1_req_pc[18:10] ^ {_tag_history_T_5[8:1], _tag_history_T_5[0] ^ io_f1_req_ghist[63]};
io_f3_resp_0_valid_REG <= _table_R0_data[12] & _table_R0_data[11:3] == s2_tag & ~doing_reset;
io_f3_resp_0_bits_u_REG <= {_hi_us_R0_data[0], _lo_us_R0_data[0]};
io_f3_resp_0_bits_ctr_REG <= _table_R0_data[2:0];
io_f3_resp_1_valid_REG <= _table_R0_data[25] & _table_R0_data[24:16] == s2_tag & ~doing_reset;
io_f3_resp_1_bits_u_REG <= {_hi_us_R0_data[1], _lo_us_R0_data[1]};
io_f3_resp_1_bits_ctr_REG <= _table_R0_data[15:13];
io_f3_resp_2_valid_REG <= _table_R0_data[38] & _table_R0_data[37:29] == s2_tag & ~doing_reset;
io_f3_resp_2_bits_u_REG <= {_hi_us_R0_data[2], _lo_us_R0_data[2]};
io_f3_resp_2_bits_ctr_REG <= _table_R0_data[28:26];
io_f3_resp_3_valid_REG <= _table_R0_data[51] & _table_R0_data[50:42] == s2_tag & ~doing_reset;
io_f3_resp_3_bits_u_REG <= {_hi_us_R0_data[3], _lo_us_R0_data[3]};
io_f3_resp_3_bits_ctr_REG <= _table_R0_data[41:39];
if (_GEN_7) begin
end
else
wrbypass_tags_0 <= update_tag;
if (_GEN_8) begin
end
else
wrbypass_tags_1 <= update_tag;
if (_GEN_7) begin
end
else
wrbypass_idxs_0 <= update_idx;
if (_GEN_8) begin
end
else
wrbypass_idxs_1 <= update_idx;
if (_GEN_6) begin
if (wrbypass_hit) begin
if (wrbypass_hits_0) begin
wrbypass_0_0 <= update_wdata_0_ctr;
wrbypass_0_1 <= update_wdata_1_ctr;
wrbypass_0_2 <= update_wdata_2_ctr;
wrbypass_0_3 <= update_wdata_3_ctr;
end
else begin
wrbypass_1_0 <= update_wdata_0_ctr;
wrbypass_1_1 <= update_wdata_1_ctr;
wrbypass_1_2 <= update_wdata_2_ctr;
wrbypass_1_3 <= update_wdata_3_ctr;
end
end
else if (wrbypass_enq_idx) begin
wrbypass_1_0 <= update_wdata_0_ctr;
wrbypass_1_1 <= update_wdata_1_ctr;
wrbypass_1_2 <= update_wdata_2_ctr;
wrbypass_1_3 <= update_wdata_3_ctr;
end
else begin
wrbypass_0_0 <= update_wdata_0_ctr;
wrbypass_0_1 <= update_wdata_1_ctr;
wrbypass_0_2 <= update_wdata_2_ctr;
wrbypass_0_3 <= update_wdata_3_ctr;
end
end
end
hi_us_4 hi_us (
.R0_addr (s1_hashed_idx),
.R0_en (io_f1_req_valid),
.R0_clk (clock),
.R0_data (_hi_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_ctr[17:11] : update_idx),
.W0_clk (clock),
.W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}),
.W0_mask (_GEN ? 4'hF : _GEN_0)
);
lo_us_4 lo_us (
.R0_addr (s1_hashed_idx),
.R0_en (io_f1_req_valid),
.R0_clk (clock),
.R0_data (_lo_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_ctr[17:11] : update_idx),
.W0_clk (clock),
.W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}),
.W0_mask (_GEN_1 ? 4'hF : _GEN_0)
);
table_4 table_0 (
.R0_addr (s1_hashed_idx),
.R0_en (io_f1_req_valid),
.R0_clk (clock),
.R0_data (_table_R0_data),
.W0_addr (doing_reset ? reset_idx : update_idx),
.W0_clk (clock),
.W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}),
.W0_mask (doing_reset ? 4'hF : {io_update_mask_3, io_update_mask_2, io_update_mask_1, io_update_mask_0})
);
assign io_f3_resp_0_valid = io_f3_resp_0_valid_REG;
assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_REG;
assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_REG;
assign io_f3_resp_1_valid = io_f3_resp_1_valid_REG;
assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_REG;
assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_REG;
assign io_f3_resp_2_valid = io_f3_resp_2_valid_REG;
assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_REG;
assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_REG;
assign io_f3_resp_3_valid = io_f3_resp_3_valid_REG;
assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_REG;
assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_REG;
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
} | module TageTable_4(
input clock,
input reset,
input io_f1_req_valid,
input [39:0] io_f1_req_pc,
input [63:0] io_f1_req_ghist,
output io_f3_resp_0_valid,
output [2:0] io_f3_resp_0_bits_ctr,
output [1:0] io_f3_resp_0_bits_u,
output io_f3_resp_1_valid,
output [2:0] io_f3_resp_1_bits_ctr,
output [1:0] io_f3_resp_1_bits_u,
output io_f3_resp_2_valid,
output [2:0] io_f3_resp_2_bits_ctr,
output [1:0] io_f3_resp_2_bits_u,
output io_f3_resp_3_valid,
output [2:0] io_f3_resp_3_bits_ctr,
output [1:0] io_f3_resp_3_bits_u,
input io_update_mask_0,
input io_update_mask_1,
input io_update_mask_2,
input io_update_mask_3,
input io_update_taken_0,
input io_update_taken_1,
input io_update_taken_2,
input io_update_taken_3,
input io_update_alloc_0,
input io_update_alloc_1,
input io_update_alloc_2,
input io_update_alloc_3,
input [2:0] io_update_old_ctr_0,
input [2:0] io_update_old_ctr_1,
input [2:0] io_update_old_ctr_2,
input [2:0] io_update_old_ctr_3,
input [39:0] io_update_pc,
input [63:0] io_update_hist,
input io_update_u_mask_0,
input io_update_u_mask_1,
input io_update_u_mask_2,
input io_update_u_mask_3,
input [1:0] io_update_u_0,
input [1:0] io_update_u_1,
input [1:0] io_update_u_2,
input [1:0] io_update_u_3
);
wire update_lo_wdata_3;
wire update_hi_wdata_3;
wire [2:0] update_wdata_3_ctr;
wire update_lo_wdata_2;
wire update_hi_wdata_2;
wire [2:0] update_wdata_2_ctr;
wire update_lo_wdata_1;
wire update_hi_wdata_1;
wire [2:0] update_wdata_1_ctr;
wire update_lo_wdata_0;
wire update_hi_wdata_0;
wire [2:0] update_wdata_0_ctr;
wire lo_us_MPORT_2_data_3;
wire lo_us_MPORT_2_data_2;
wire lo_us_MPORT_2_data_1;
wire lo_us_MPORT_2_data_0;
wire hi_us_MPORT_1_data_3;
wire hi_us_MPORT_1_data_2;
wire hi_us_MPORT_1_data_1;
wire hi_us_MPORT_1_data_0;
wire [12:0] table_MPORT_data_3;
wire [12:0] table_MPORT_data_2;
wire [12:0] table_MPORT_data_1;
wire [12:0] table_MPORT_data_0;
wire [51:0] _table_R0_data;
wire [3:0] _lo_us_R0_data;
wire [3:0] _hi_us_R0_data;
reg doing_reset;
reg [6:0] reset_idx;
wire [6:0] _idx_history_T_2 = io_f1_req_ghist[6:0] ^ io_f1_req_ghist[13:7] ^ io_f1_req_ghist[20:14] ^ io_f1_req_ghist[27:21];
wire [6:0] s1_hashed_idx = io_f1_req_pc[9:3] ^ {_idx_history_T_2[6:4], _idx_history_T_2[3:0] ^ io_f1_req_ghist[31:28]};
reg [8:0] s2_tag;
reg io_f3_resp_0_valid_REG;
reg [1:0] io_f3_resp_0_bits_u_REG;
reg [2:0] io_f3_resp_0_bits_ctr_REG;
reg io_f3_resp_1_valid_REG;
reg [1:0] io_f3_resp_1_bits_u_REG;
reg [2:0] io_f3_resp_1_bits_ctr_REG;
reg io_f3_resp_2_valid_REG;
reg [1:0] io_f3_resp_2_bits_u_REG;
reg [2:0] io_f3_resp_2_bits_ctr_REG;
reg io_f3_resp_3_valid_REG;
reg [1:0] io_f3_resp_3_bits_u_REG;
reg [2:0] io_f3_resp_3_bits_ctr_REG;
reg [18:0] clear_u_ctr;
wire doing_clear_u = clear_u_ctr[10:0] == 11'h0;
wire doing_clear_u_hi = doing_clear_u & clear_u_ctr[18];
wire doing_clear_u_lo = doing_clear_u & ~(clear_u_ctr[18]);
wire [6:0] _idx_history_T_5 = io_update_hist[6:0] ^ io_update_hist[13:7] ^ io_update_hist[20:14] ^ io_update_hist[27:21];
wire [6:0] update_idx = io_update_pc[9:3] ^ {_idx_history_T_5[6:4], _idx_history_T_5[3:0] ^ io_update_hist[31:28]};
wire [8:0] _tag_history_T_3 = io_update_hist[8:0] ^ io_update_hist[17:9] ^ io_update_hist[26:18];
wire [8:0] update_tag = io_update_pc[18:10] ^ {_tag_history_T_3[8:5], _tag_history_T_3[4:0] ^ io_update_hist[31:27]};
assign table_MPORT_data_0 = doing_reset ? 13'h0 : {1'h1, update_tag, update_wdata_0_ctr};
assign table_MPORT_data_1 = doing_reset ? 13'h0 : {1'h1, update_tag, update_wdata_1_ctr};
assign table_MPORT_data_2 = doing_reset ? 13'h0 : {1'h1, update_tag, update_wdata_2_ctr};
assign table_MPORT_data_3 = doing_reset ? 13'h0 : {1'h1, update_tag, update_wdata_3_ctr};
wire _GEN = doing_reset | doing_clear_u_hi;
assign hi_us_MPORT_1_data_0 = ~_GEN & update_hi_wdata_0;
assign hi_us_MPORT_1_data_1 = ~_GEN & update_hi_wdata_1;
assign hi_us_MPORT_1_data_2 = ~_GEN & update_hi_wdata_2;
assign hi_us_MPORT_1_data_3 = ~_GEN & update_hi_wdata_3;
wire [3:0] _GEN_0 = {io_update_u_mask_3, io_update_u_mask_2, io_update_u_mask_1, io_update_u_mask_0};
wire _GEN_1 = doing_reset | doing_clear_u_lo;
assign lo_us_MPORT_2_data_0 = ~_GEN_1 & update_lo_wdata_0;
assign lo_us_MPORT_2_data_1 = ~_GEN_1 & update_lo_wdata_1;
assign lo_us_MPORT_2_data_2 = ~_GEN_1 & update_lo_wdata_2;
assign lo_us_MPORT_2_data_3 = ~_GEN_1 & update_lo_wdata_3;
reg [8:0] wrbypass_tags_0;
reg [8:0] wrbypass_tags_1;
reg [6:0] wrbypass_idxs_0;
reg [6:0] wrbypass_idxs_1;
reg [2:0] wrbypass_0_0;
reg [2:0] wrbypass_0_1;
reg [2:0] wrbypass_0_2;
reg [2:0] wrbypass_0_3;
reg [2:0] wrbypass_1_0;
reg [2:0] wrbypass_1_1;
reg [2:0] wrbypass_1_2;
reg [2:0] wrbypass_1_3;
reg wrbypass_enq_idx;
wire wrbypass_hits_0 = ~doing_reset & wrbypass_tags_0 == update_tag & wrbypass_idxs_0 == update_idx;
wire wrbypass_hit = wrbypass_hits_0 | ~doing_reset & wrbypass_tags_1 == update_tag & wrbypass_idxs_1 == update_idx;
wire [2:0] _GEN_2 = wrbypass_hits_0 ? wrbypass_0_0 : wrbypass_1_0;
wire [2:0] _GEN_3 = wrbypass_hits_0 ? wrbypass_0_1 : wrbypass_1_1;
wire [2:0] _GEN_4 = wrbypass_hits_0 ? wrbypass_0_2 : wrbypass_1_2;
wire [2:0] _GEN_5 = wrbypass_hits_0 ? wrbypass_0_3 : wrbypass_1_3;
assign update_wdata_0_ctr = io_update_alloc_0 ? (io_update_taken_0 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_0 ? ((&_GEN_2) ? 3'h7 : _GEN_2 + 3'h1) : _GEN_2 == 3'h0 ? 3'h0 : _GEN_2 - 3'h1) : io_update_taken_0 ? ((&io_update_old_ctr_0) ? 3'h7 : io_update_old_ctr_0 + 3'h1) : io_update_old_ctr_0 == 3'h0 ? 3'h0 : io_update_old_ctr_0 - 3'h1;
assign update_hi_wdata_0 = io_update_u_0[1];
assign update_lo_wdata_0 = io_update_u_0[0];
assign update_wdata_1_ctr = io_update_alloc_1 ? (io_update_taken_1 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_1 ? ((&_GEN_3) ? 3'h7 : _GEN_3 + 3'h1) : _GEN_3 == 3'h0 ? 3'h0 : _GEN_3 - 3'h1) : io_update_taken_1 ? ((&io_update_old_ctr_1) ? 3'h7 : io_update_old_ctr_1 + 3'h1) : io_update_old_ctr_1 == 3'h0 ? 3'h0 : io_update_old_ctr_1 - 3'h1;
assign update_hi_wdata_1 = io_update_u_1[1];
assign update_lo_wdata_1 = io_update_u_1[0];
assign update_wdata_2_ctr = io_update_alloc_2 ? (io_update_taken_2 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_2 ? ((&_GEN_4) ? 3'h7 : _GEN_4 + 3'h1) : _GEN_4 == 3'h0 ? 3'h0 : _GEN_4 - 3'h1) : io_update_taken_2 ? ((&io_update_old_ctr_2) ? 3'h7 : io_update_old_ctr_2 + 3'h1) : io_update_old_ctr_2 == 3'h0 ? 3'h0 : io_update_old_ctr_2 - 3'h1;
assign update_hi_wdata_2 = io_update_u_2[1];
assign update_lo_wdata_2 = io_update_u_2[0];
assign update_wdata_3_ctr = io_update_alloc_3 ? (io_update_taken_3 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_3 ? ((&_GEN_5) ? 3'h7 : _GEN_5 + 3'h1) : _GEN_5 == 3'h0 ? 3'h0 : _GEN_5 - 3'h1) : io_update_taken_3 ? ((&io_update_old_ctr_3) ? 3'h7 : io_update_old_ctr_3 + 3'h1) : io_update_old_ctr_3 == 3'h0 ? 3'h0 : io_update_old_ctr_3 - 3'h1;
assign update_hi_wdata_3 = io_update_u_3[1];
assign update_lo_wdata_3 = io_update_u_3[0];
wire [8:0] _tag_history_T_1 = io_f1_req_ghist[8:0] ^ io_f1_req_ghist[17:9] ^ io_f1_req_ghist[26:18];
wire _GEN_6 = io_update_mask_0 | io_update_mask_1 | io_update_mask_2 | io_update_mask_3;
wire _GEN_7 = ~_GEN_6 | wrbypass_hit | wrbypass_enq_idx;
wire _GEN_8 = ~_GEN_6 | wrbypass_hit | ~wrbypass_enq_idx;
always @(posedge clock) begin
if (reset) begin
doing_reset <= 1'h1;
reset_idx <= 7'h0;
clear_u_ctr <= 19'h0;
wrbypass_enq_idx <= 1'h0;
end
else begin
doing_reset <= reset_idx != 7'h7F & doing_reset;
reset_idx <= reset_idx + {6'h0, doing_reset};
clear_u_ctr <= doing_reset ? 19'h1 : clear_u_ctr + 19'h1;
if (~_GEN_6 | wrbypass_hit) begin
end
else
wrbypass_enq_idx <= wrbypass_enq_idx - 1'h1;
end
s2_tag <= io_f1_req_pc[18:10] ^ {_tag_history_T_1[8:5], _tag_history_T_1[4:0] ^ io_f1_req_ghist[31:27]};
io_f3_resp_0_valid_REG <= _table_R0_data[12] & _table_R0_data[11:3] == s2_tag & ~doing_reset;
io_f3_resp_0_bits_u_REG <= {_hi_us_R0_data[0], _lo_us_R0_data[0]};
io_f3_resp_0_bits_ctr_REG <= _table_R0_data[2:0];
io_f3_resp_1_valid_REG <= _table_R0_data[25] & _table_R0_data[24:16] == s2_tag & ~doing_reset;
io_f3_resp_1_bits_u_REG <= {_hi_us_R0_data[1], _lo_us_R0_data[1]};
io_f3_resp_1_bits_ctr_REG <= _table_R0_data[15:13];
io_f3_resp_2_valid_REG <= _table_R0_data[38] & _table_R0_data[37:29] == s2_tag & ~doing_reset;
io_f3_resp_2_bits_u_REG <= {_hi_us_R0_data[2], _lo_us_R0_data[2]};
io_f3_resp_2_bits_ctr_REG <= _table_R0_data[28:26];
io_f3_resp_3_valid_REG <= _table_R0_data[51] & _table_R0_data[50:42] == s2_tag & ~doing_reset;
io_f3_resp_3_bits_u_REG <= {_hi_us_R0_data[3], _lo_us_R0_data[3]};
io_f3_resp_3_bits_ctr_REG <= _table_R0_data[41:39];
if (_GEN_7) begin
end
else
wrbypass_tags_0 <= update_tag;
if (_GEN_8) begin
end
else
wrbypass_tags_1 <= update_tag;
if (_GEN_7) begin
end
else
wrbypass_idxs_0 <= update_idx;
if (_GEN_8) begin
end
else
wrbypass_idxs_1 <= update_idx;
if (_GEN_6) begin
if (wrbypass_hit) begin
if (wrbypass_hits_0) begin
wrbypass_0_0 <= update_wdata_0_ctr;
wrbypass_0_1 <= update_wdata_1_ctr;
wrbypass_0_2 <= update_wdata_2_ctr;
wrbypass_0_3 <= update_wdata_3_ctr;
end
else begin
wrbypass_1_0 <= update_wdata_0_ctr;
wrbypass_1_1 <= update_wdata_1_ctr;
wrbypass_1_2 <= update_wdata_2_ctr;
wrbypass_1_3 <= update_wdata_3_ctr;
end
end
else if (wrbypass_enq_idx) begin
wrbypass_1_0 <= update_wdata_0_ctr;
wrbypass_1_1 <= update_wdata_1_ctr;
wrbypass_1_2 <= update_wdata_2_ctr;
wrbypass_1_3 <= update_wdata_3_ctr;
end
else begin
wrbypass_0_0 <= update_wdata_0_ctr;
wrbypass_0_1 <= update_wdata_1_ctr;
wrbypass_0_2 <= update_wdata_2_ctr;
wrbypass_0_3 <= update_wdata_3_ctr;
end
end
end
hi_us_3 hi_us (
.R0_addr (s1_hashed_idx),
.R0_en (io_f1_req_valid),
.R0_clk (clock),
.R0_data (_hi_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_ctr[17:11] : update_idx),
.W0_clk (clock),
.W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}),
.W0_mask (_GEN ? 4'hF : _GEN_0)
);
lo_us_3 lo_us (
.R0_addr (s1_hashed_idx),
.R0_en (io_f1_req_valid),
.R0_clk (clock),
.R0_data (_lo_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_ctr[17:11] : update_idx),
.W0_clk (clock),
.W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}),
.W0_mask (_GEN_1 ? 4'hF : _GEN_0)
);
table_3 table_0 (
.R0_addr (s1_hashed_idx),
.R0_en (io_f1_req_valid),
.R0_clk (clock),
.R0_data (_table_R0_data),
.W0_addr (doing_reset ? reset_idx : update_idx),
.W0_clk (clock),
.W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}),
.W0_mask (doing_reset ? 4'hF : {io_update_mask_3, io_update_mask_2, io_update_mask_1, io_update_mask_0})
);
assign io_f3_resp_0_valid = io_f3_resp_0_valid_REG;
assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_REG;
assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_REG;
assign io_f3_resp_1_valid = io_f3_resp_1_valid_REG;
assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_REG;
assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_REG;
assign io_f3_resp_2_valid = io_f3_resp_2_valid_REG;
assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_REG;
assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_REG;
assign io_f3_resp_3_valid = io_f3_resp_3_valid_REG;
assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_REG;
assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_REG;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)
{
val queueBits = log2Up(queues)
val entryBits = log2Up(entries)
}
class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle
{
val index = UInt(params.queueBits.W)
val data = Output(params.gen)
}
class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module
{
override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}"
val io = IO(new Bundle {
// push is visible on the same cycle; flow queues
val push = Flipped(Decoupled(new ListBufferPush(params)))
val valid = UInt(params.queues.W)
val pop = Flipped(Valid(UInt(params.queueBits.W)))
val data = Output(params.gen)
})
val valid = RegInit(0.U(params.queues.W))
val head = Mem(params.queues, UInt(params.entryBits.W))
val tail = Mem(params.queues, UInt(params.entryBits.W))
val used = RegInit(0.U(params.entries.W))
val next = Mem(params.entries, UInt(params.entryBits.W))
val data = Mem(params.entries, params.gen)
val freeOH = ~(leftOR(~used) << 1) & ~used
val freeIdx = OHToUInt(freeOH)
val valid_set = WireDefault(0.U(params.queues.W))
val valid_clr = WireDefault(0.U(params.queues.W))
val used_set = WireDefault(0.U(params.entries.W))
val used_clr = WireDefault(0.U(params.entries.W))
val push_tail = tail.read(io.push.bits.index)
val push_valid = valid(io.push.bits.index)
io.push.ready := !used.andR
when (io.push.fire) {
valid_set := UIntToOH(io.push.bits.index, params.queues)
used_set := freeOH
data.write(freeIdx, io.push.bits.data)
when (push_valid) {
next.write(push_tail, freeIdx)
} .otherwise {
head.write(io.push.bits.index, freeIdx)
}
tail.write(io.push.bits.index, freeIdx)
}
val pop_head = head.read(io.pop.bits)
val pop_valid = valid(io.pop.bits)
// Bypass push data to the peek port
io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))
io.valid := (if (!params.bypass) valid else (valid | valid_set))
// It is an error to pop something that is not valid
assert (!io.pop.fire || (io.valid)(io.pop.bits))
when (io.pop.fire) {
used_clr := UIntToOH(pop_head, params.entries)
when (pop_head === tail.read(io.pop.bits)) {
valid_clr := UIntToOH(io.pop.bits, params.queues)
}
head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))
}
// Empty bypass changes no state
when ((!params.bypass).B || !io.pop.valid || pop_valid) {
used := (used & ~used_clr) | used_set
valid := (valid & ~valid_clr) | valid_set
}
} | module tail_40x6(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [5:0] R0_data,
input [5:0] R1_addr,
input R1_en,
input R1_clk,
output [5:0] R1_data,
input [5:0] W0_addr,
input W0_en,
input W0_clk,
input [5:0] W0_data
);
reg [5:0] Memory[0:39];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 6'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 6'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Functional Units
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// If regfile bypassing is disabled, then the functional unit must do its own
// bypassing in here on the WB stage (i.e., bypassing the io.resp.data)
//
// TODO: explore possibility of conditional IO fields? if a branch unit... how to add extra to IO in subclass?
package boom.v3.exu
import chisel3._
import chisel3.util._
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
import freechips.rocketchip.tile
import freechips.rocketchip.rocket.{PipelinedMultiplier,BP,BreakpointUnit,Causes,CSR}
import boom.v3.common._
import boom.v3.ifu._
import boom.v3.util._
/**t
* Functional unit constants
*/
object FUConstants
{
// bit mask, since a given execution pipeline may support multiple functional units
val FUC_SZ = 10
val FU_X = BitPat.dontCare(FUC_SZ)
val FU_ALU = 1.U(FUC_SZ.W)
val FU_JMP = 2.U(FUC_SZ.W)
val FU_MEM = 4.U(FUC_SZ.W)
val FU_MUL = 8.U(FUC_SZ.W)
val FU_DIV = 16.U(FUC_SZ.W)
val FU_CSR = 32.U(FUC_SZ.W)
val FU_FPU = 64.U(FUC_SZ.W)
val FU_FDV = 128.U(FUC_SZ.W)
val FU_I2F = 256.U(FUC_SZ.W)
val FU_F2I = 512.U(FUC_SZ.W)
// FP stores generate data through FP F2I, and generate address through MemAddrCalc
val FU_F2IMEM = 516.U(FUC_SZ.W)
}
import FUConstants._
/**
* Class to tell the FUDecoders what units it needs to support
*
* @param alu support alu unit?
* @param bru support br unit?
* @param mem support mem unit?
* @param muld support multiple div unit?
* @param fpu support FP unit?
* @param csr support csr writing unit?
* @param fdiv support FP div unit?
* @param ifpu support int to FP unit?
*/
class SupportedFuncUnits(
val alu: Boolean = false,
val jmp: Boolean = false,
val mem: Boolean = false,
val muld: Boolean = false,
val fpu: Boolean = false,
val csr: Boolean = false,
val fdiv: Boolean = false,
val ifpu: Boolean = false)
{
}
/**
* Bundle for signals sent to the functional unit
*
* @param dataWidth width of the data sent to the functional unit
*/
class FuncUnitReq(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
with HasBoomUOP
{
val numOperands = 3
val rs1_data = UInt(dataWidth.W)
val rs2_data = UInt(dataWidth.W)
val rs3_data = UInt(dataWidth.W) // only used for FMA units
val pred_data = Bool()
val kill = Bool() // kill everything
}
/**
* Bundle for the signals sent out of the function unit
*
* @param dataWidth data sent from the functional unit
*/
class FuncUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
with HasBoomUOP
{
val predicated = Bool() // Was this response from a predicated-off instruction
val data = UInt(dataWidth.W)
val fflags = new ValidIO(new FFlagsResp)
val addr = UInt((vaddrBits+1).W) // only for maddr -> LSU
val mxcpt = new ValidIO(UInt((freechips.rocketchip.rocket.Causes.all.max+2).W)) //only for maddr->LSU
val sfence = Valid(new freechips.rocketchip.rocket.SFenceReq) // only for mcalc
}
/**
* Branch resolution information given from the branch unit
*/
class BrResolutionInfo(implicit p: Parameters) extends BoomBundle
{
val uop = new MicroOp
val valid = Bool()
val mispredict = Bool()
val taken = Bool() // which direction did the branch go?
val cfi_type = UInt(CFI_SZ.W)
// Info for recalculating the pc for this branch
val pc_sel = UInt(2.W)
val jalr_target = UInt(vaddrBitsExtended.W)
val target_offset = SInt()
}
class BrUpdateInfo(implicit p: Parameters) extends BoomBundle
{
// On the first cycle we get masks to kill registers
val b1 = new BrUpdateMasks
// On the second cycle we get indices to reset pointers
val b2 = new BrResolutionInfo
}
class BrUpdateMasks(implicit p: Parameters) extends BoomBundle
{
val resolve_mask = UInt(maxBrCount.W)
val mispredict_mask = UInt(maxBrCount.W)
}
/**
* Abstract top level functional unit class that wraps a lower level hand made functional unit
*
* @param isPipelined is the functional unit pipelined?
* @param numStages how many pipeline stages does the functional unit have
* @param numBypassStages how many bypass stages does the function unit have
* @param dataWidth width of the data being operated on in the functional unit
* @param hasBranchUnit does this functional unit have a branch unit?
*/
abstract class FunctionalUnit(
val isPipelined: Boolean,
val numStages: Int,
val numBypassStages: Int,
val dataWidth: Int,
val isJmpUnit: Boolean = false,
val isAluUnit: Boolean = false,
val isMemAddrCalcUnit: Boolean = false,
val needsFcsr: Boolean = false)
(implicit p: Parameters) extends BoomModule
{
val io = IO(new Bundle {
val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth)))
val resp = (new DecoupledIO(new FuncUnitResp(dataWidth)))
val brupdate = Input(new BrUpdateInfo())
val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth))))
// only used by the fpu unit
val fcsr_rm = if (needsFcsr) Input(UInt(tile.FPConstants.RM_SZ.W)) else null
// only used by branch unit
val brinfo = if (isAluUnit) Output(new BrResolutionInfo()) else null
val get_ftq_pc = if (isJmpUnit) Flipped(new GetPCFromFtqIO()) else null
val status = if (isMemAddrCalcUnit) Input(new freechips.rocketchip.rocket.MStatus()) else null
// only used by memaddr calc unit
val bp = if (isMemAddrCalcUnit) Input(Vec(nBreakpoints, new BP)) else null
val mcontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.mcontextWidth.W)) else null
val scontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.scontextWidth.W)) else null
})
io.bypass.foreach { b => b.valid := false.B; b.bits := DontCare }
io.resp.valid := false.B
io.resp.bits := DontCare
if (isJmpUnit) {
io.get_ftq_pc.ftq_idx := DontCare
}
}
/**
* Abstract top level pipelined functional unit
*
* Note: this helps track which uops get killed while in intermediate stages,
* but it is the job of the consumer to check for kills on the same cycle as consumption!!!
*
* @param numStages how many pipeline stages does the functional unit have
* @param numBypassStages how many bypass stages does the function unit have
* @param earliestBypassStage first stage that you can start bypassing from
* @param dataWidth width of the data being operated on in the functional unit
* @param hasBranchUnit does this functional unit have a branch unit?
*/
abstract class PipelinedFunctionalUnit(
numStages: Int,
numBypassStages: Int,
earliestBypassStage: Int,
dataWidth: Int,
isJmpUnit: Boolean = false,
isAluUnit: Boolean = false,
isMemAddrCalcUnit: Boolean = false,
needsFcsr: Boolean = false
)(implicit p: Parameters) extends FunctionalUnit(
isPipelined = true,
numStages = numStages,
numBypassStages = numBypassStages,
dataWidth = dataWidth,
isJmpUnit = isJmpUnit,
isAluUnit = isAluUnit,
isMemAddrCalcUnit = isMemAddrCalcUnit,
needsFcsr = needsFcsr)
{
// Pipelined functional unit is always ready.
io.req.ready := true.B
if (numStages > 0) {
val r_valids = RegInit(VecInit(Seq.fill(numStages) { false.B }))
val r_uops = Reg(Vec(numStages, new MicroOp()))
// handle incoming request
r_valids(0) := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) && !io.req.bits.kill
r_uops(0) := io.req.bits.uop
r_uops(0).br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)
// handle middle of the pipeline
for (i <- 1 until numStages) {
r_valids(i) := r_valids(i-1) && !IsKilledByBranch(io.brupdate, r_uops(i-1)) && !io.req.bits.kill
r_uops(i) := r_uops(i-1)
r_uops(i).br_mask := GetNewBrMask(io.brupdate, r_uops(i-1))
if (numBypassStages > 0) {
io.bypass(i-1).bits.uop := r_uops(i-1)
}
}
// handle outgoing (branch could still kill it)
// consumer must also check for pipeline flushes (kills)
io.resp.valid := r_valids(numStages-1) && !IsKilledByBranch(io.brupdate, r_uops(numStages-1))
io.resp.bits.predicated := false.B
io.resp.bits.uop := r_uops(numStages-1)
io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, r_uops(numStages-1))
// bypassing (TODO allow bypass vector to have a different size from numStages)
if (numBypassStages > 0 && earliestBypassStage == 0) {
io.bypass(0).bits.uop := io.req.bits.uop
for (i <- 1 until numBypassStages) {
io.bypass(i).bits.uop := r_uops(i-1)
}
}
} else {
require (numStages == 0)
// pass req straight through to response
// valid doesn't check kill signals, let consumer deal with it.
// The LSU already handles it and this hurts critical path.
io.resp.valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop)
io.resp.bits.predicated := false.B
io.resp.bits.uop := io.req.bits.uop
io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)
}
}
/**
* Functional unit that wraps RocketChips ALU
*
* @param isBranchUnit is this a branch unit?
* @param numStages how many pipeline stages does the functional unit have
* @param dataWidth width of the data being operated on in the functional unit
*/
class ALUUnit(isJmpUnit: Boolean = false, numStages: Int = 1, dataWidth: Int)(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = numStages,
numBypassStages = numStages,
isAluUnit = true,
earliestBypassStage = 0,
dataWidth = dataWidth,
isJmpUnit = isJmpUnit)
with boom.v3.ifu.HasBoomFrontendParameters
{
val uop = io.req.bits.uop
// immediate generation
val imm_xprlen = ImmGen(uop.imm_packed, uop.ctrl.imm_sel)
// operand 1 select
var op1_data: UInt = null
if (isJmpUnit) {
// Get the uop PC for jumps
val block_pc = AlignPCToBoundary(io.get_ftq_pc.pc, icBlockBytes)
val uop_pc = (block_pc | uop.pc_lob) - Mux(uop.edge_inst, 2.U, 0.U)
op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data,
Mux(uop.ctrl.op1_sel.asUInt === OP1_PC , Sext(uop_pc, xLen),
0.U))
} else {
op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data,
0.U)
}
// operand 2 select
val op2_data = Mux(uop.ctrl.op2_sel === OP2_IMM, Sext(imm_xprlen.asUInt, xLen),
Mux(uop.ctrl.op2_sel === OP2_IMMC, io.req.bits.uop.prs1(4,0),
Mux(uop.ctrl.op2_sel === OP2_RS2 , io.req.bits.rs2_data,
Mux(uop.ctrl.op2_sel === OP2_NEXT, Mux(uop.is_rvc, 2.U, 4.U),
0.U))))
val alu = Module(new freechips.rocketchip.rocket.ALU())
alu.io.in1 := op1_data.asUInt
alu.io.in2 := op2_data.asUInt
alu.io.fn := uop.ctrl.op_fcn
alu.io.dw := uop.ctrl.fcn_dw
// Did I just get killed by the previous cycle's branch,
// or by a flush pipeline?
val killed = WireInit(false.B)
when (io.req.bits.kill || IsKilledByBranch(io.brupdate, uop)) {
killed := true.B
}
val rs1 = io.req.bits.rs1_data
val rs2 = io.req.bits.rs2_data
val br_eq = (rs1 === rs2)
val br_ltu = (rs1.asUInt < rs2.asUInt)
val br_lt = (~(rs1(xLen-1) ^ rs2(xLen-1)) & br_ltu |
rs1(xLen-1) & ~rs2(xLen-1)).asBool
val pc_sel = MuxLookup(uop.ctrl.br_type, PC_PLUS4)(
Seq( BR_N -> PC_PLUS4,
BR_NE -> Mux(!br_eq, PC_BRJMP, PC_PLUS4),
BR_EQ -> Mux( br_eq, PC_BRJMP, PC_PLUS4),
BR_GE -> Mux(!br_lt, PC_BRJMP, PC_PLUS4),
BR_GEU -> Mux(!br_ltu, PC_BRJMP, PC_PLUS4),
BR_LT -> Mux( br_lt, PC_BRJMP, PC_PLUS4),
BR_LTU -> Mux( br_ltu, PC_BRJMP, PC_PLUS4),
BR_J -> PC_BRJMP,
BR_JR -> PC_JALR
))
val is_taken = io.req.valid &&
!killed &&
(uop.is_br || uop.is_jalr || uop.is_jal) &&
(pc_sel =/= PC_PLUS4)
// "mispredict" means that a branch has been resolved and it must be killed
val mispredict = WireInit(false.B)
val is_br = io.req.valid && !killed && uop.is_br && !uop.is_sfb
val is_jal = io.req.valid && !killed && uop.is_jal
val is_jalr = io.req.valid && !killed && uop.is_jalr
when (is_br || is_jalr) {
if (!isJmpUnit) {
assert (pc_sel =/= PC_JALR)
}
when (pc_sel === PC_PLUS4) {
mispredict := uop.taken
}
when (pc_sel === PC_BRJMP) {
mispredict := !uop.taken
}
}
val brinfo = Wire(new BrResolutionInfo)
// note: jal doesn't allocate a branch-mask, so don't clear a br-mask bit
brinfo.valid := is_br || is_jalr
brinfo.mispredict := mispredict
brinfo.uop := uop
brinfo.cfi_type := Mux(is_jalr, CFI_JALR,
Mux(is_br , CFI_BR, CFI_X))
brinfo.taken := is_taken
brinfo.pc_sel := pc_sel
brinfo.jalr_target := DontCare
// Branch/Jump Target Calculation
// For jumps we read the FTQ, and can calculate the target
// For branches we emit the offset for the core to redirect if necessary
val target_offset = imm_xprlen(20,0).asSInt
brinfo.jalr_target := DontCare
if (isJmpUnit) {
def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) {
ea
} else {
// Efficient means to compress 64-bit VA into vaddrBits+1 bits.
// (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)).
val a = a0.asSInt >> vaddrBits
val msb = Mux(a === 0.S || a === -1.S, ea(vaddrBits), !ea(vaddrBits-1))
Cat(msb, ea(vaddrBits-1,0))
}
val jalr_target_base = io.req.bits.rs1_data.asSInt
val jalr_target_xlen = Wire(UInt(xLen.W))
jalr_target_xlen := (jalr_target_base + target_offset).asUInt
val jalr_target = (encodeVirtualAddress(jalr_target_xlen, jalr_target_xlen).asSInt & -2.S).asUInt
brinfo.jalr_target := jalr_target
val cfi_idx = ((uop.pc_lob ^ Mux(io.get_ftq_pc.entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U)))(log2Ceil(fetchWidth),1)
when (pc_sel === PC_JALR) {
mispredict := !io.get_ftq_pc.next_val ||
(io.get_ftq_pc.next_pc =/= jalr_target) ||
!io.get_ftq_pc.entry.cfi_idx.valid ||
(io.get_ftq_pc.entry.cfi_idx.bits =/= cfi_idx)
}
}
brinfo.target_offset := target_offset
io.brinfo := brinfo
// Response
// TODO add clock gate on resp bits from functional units
// io.resp.bits.data := RegEnable(alu.io.out, io.req.valid)
// val reg_data = Reg(outType = Bits(width = xLen))
// reg_data := alu.io.out
// io.resp.bits.data := reg_data
val r_val = RegInit(VecInit(Seq.fill(numStages) { false.B }))
val r_data = Reg(Vec(numStages, UInt(xLen.W)))
val r_pred = Reg(Vec(numStages, Bool()))
val alu_out = Mux(io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data,
Mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data),
Mux(io.req.bits.uop.uopc === uopMOV, io.req.bits.rs2_data, alu.io.out))
r_val (0) := io.req.valid
r_data(0) := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out)
r_pred(0) := io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data
for (i <- 1 until numStages) {
r_val(i) := r_val(i-1)
r_data(i) := r_data(i-1)
r_pred(i) := r_pred(i-1)
}
io.resp.bits.data := r_data(numStages-1)
io.resp.bits.predicated := r_pred(numStages-1)
// Bypass
// for the ALU, we can bypass same cycle as compute
require (numStages >= 1)
require (numBypassStages >= 1)
io.bypass(0).valid := io.req.valid
io.bypass(0).bits.data := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out)
for (i <- 1 until numStages) {
io.bypass(i).valid := r_val(i-1)
io.bypass(i).bits.data := r_data(i-1)
}
// Exceptions
io.resp.bits.fflags.valid := false.B
}
/**
* Functional unit that passes in base+imm to calculate addresses, and passes store data
* to the LSU.
* For floating point, 65bit FP store-data needs to be decoded into 64bit FP form
*/
class MemAddrCalcUnit(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = 0,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = 65, // TODO enable this only if FP is enabled?
isMemAddrCalcUnit = true)
with freechips.rocketchip.rocket.constants.MemoryOpConstants
with freechips.rocketchip.rocket.constants.ScalarOpConstants
{
// perform address calculation
val sum = (io.req.bits.rs1_data.asSInt + io.req.bits.uop.imm_packed(19,8).asSInt).asUInt
val ea_sign = Mux(sum(vaddrBits-1), ~sum(63,vaddrBits) === 0.U,
sum(63,vaddrBits) =/= 0.U)
val effective_address = Cat(ea_sign, sum(vaddrBits-1,0)).asUInt
val store_data = io.req.bits.rs2_data
io.resp.bits.addr := effective_address
io.resp.bits.data := store_data
if (dataWidth > 63) {
assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std &&
io.resp.bits.data(64).asBool === true.B), "65th bit set in MemAddrCalcUnit.")
assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std && io.req.bits.uop.fp_val),
"FP store-data should now be going through a different unit.")
}
assert (!(io.req.bits.uop.fp_val && io.req.valid && io.req.bits.uop.uopc =/=
uopLD && io.req.bits.uop.uopc =/= uopSTA),
"[maddrcalc] assert we never get store data in here.")
// Handle misaligned exceptions
val size = io.req.bits.uop.mem_size
val misaligned =
(size === 1.U && (effective_address(0) =/= 0.U)) ||
(size === 2.U && (effective_address(1,0) =/= 0.U)) ||
(size === 3.U && (effective_address(2,0) =/= 0.U))
val bkptu = Module(new BreakpointUnit(nBreakpoints))
bkptu.io.status := io.status
bkptu.io.bp := io.bp
bkptu.io.pc := DontCare
bkptu.io.ea := effective_address
bkptu.io.mcontext := io.mcontext
bkptu.io.scontext := io.scontext
val ma_ld = io.req.valid && io.req.bits.uop.uopc === uopLD && misaligned
val ma_st = io.req.valid && (io.req.bits.uop.uopc === uopSTA || io.req.bits.uop.uopc === uopAMO_AG) && misaligned
val dbg_bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.debug_ld) ||
(io.req.bits.uop.uopc === uopSTA && bkptu.io.debug_st))
val bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.xcpt_ld) ||
(io.req.bits.uop.uopc === uopSTA && bkptu.io.xcpt_st))
def checkExceptions(x: Seq[(Bool, UInt)]) =
(x.map(_._1).reduce(_||_), PriorityMux(x))
val (xcpt_val, xcpt_cause) = checkExceptions(List(
(ma_ld, (Causes.misaligned_load).U),
(ma_st, (Causes.misaligned_store).U),
(dbg_bp, (CSR.debugTriggerCause).U),
(bp, (Causes.breakpoint).U)))
io.resp.bits.mxcpt.valid := xcpt_val
io.resp.bits.mxcpt.bits := xcpt_cause
assert (!(ma_ld && ma_st), "Mutually-exclusive exceptions are firing.")
io.resp.bits.sfence.valid := io.req.valid && io.req.bits.uop.mem_cmd === M_SFENCE
io.resp.bits.sfence.bits.rs1 := io.req.bits.uop.mem_size(0)
io.resp.bits.sfence.bits.rs2 := io.req.bits.uop.mem_size(1)
io.resp.bits.sfence.bits.addr := io.req.bits.rs1_data
io.resp.bits.sfence.bits.asid := io.req.bits.rs2_data
}
/**
* Functional unit to wrap lower level FPU
*
* Currently, bypassing is unsupported!
* All FP instructions are padded out to the max latency unit for easy
* write-port scheduling.
*/
class FPUUnit(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = p(tile.TileKey).core.fpu.get.dfmaLatency,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = 65,
needsFcsr = true)
{
val fpu = Module(new FPU())
fpu.io.req.valid := io.req.valid
fpu.io.req.bits.uop := io.req.bits.uop
fpu.io.req.bits.rs1_data := io.req.bits.rs1_data
fpu.io.req.bits.rs2_data := io.req.bits.rs2_data
fpu.io.req.bits.rs3_data := io.req.bits.rs3_data
fpu.io.req.bits.fcsr_rm := io.fcsr_rm
io.resp.bits.data := fpu.io.resp.bits.data
io.resp.bits.fflags.valid := fpu.io.resp.bits.fflags.valid
io.resp.bits.fflags.bits.uop := io.resp.bits.uop
io.resp.bits.fflags.bits.flags := fpu.io.resp.bits.fflags.bits.flags // kill me now
}
/**
* Int to FP conversion functional unit
*
* @param latency the amount of stages to delay by
*/
class IntToFPUnit(latency: Int)(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = latency,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = 65,
needsFcsr = true)
with tile.HasFPUParameters
{
val fp_decoder = Module(new UOPCodeFPUDecoder) // TODO use a simpler decoder
val io_req = io.req.bits
fp_decoder.io.uopc := io_req.uop.uopc
val fp_ctrl = fp_decoder.io.sigs
val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io.fcsr_rm, ImmGenRm(io_req.uop.imm_packed))
val req = Wire(new tile.FPInput)
val tag = fp_ctrl.typeTagIn
req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl
req.rm := fp_rm
req.in1 := unbox(io_req.rs1_data, tag, None)
req.in2 := unbox(io_req.rs2_data, tag, None)
req.in3 := DontCare
req.typ := ImmGenTyp(io_req.uop.imm_packed)
req.fmt := DontCare // FIXME: this may not be the right thing to do here
req.fmaCmd := DontCare
assert (!(io.req.valid && fp_ctrl.fromint && req.in1(xLen).asBool),
"[func] IntToFP integer input has 65th high-order bit set!")
assert (!(io.req.valid && !fp_ctrl.fromint),
"[func] Only support fromInt micro-ops.")
val ifpu = Module(new tile.IntToFP(intToFpLatency))
ifpu.io.in.valid := io.req.valid
ifpu.io.in.bits := req
ifpu.io.in.bits.in1 := io_req.rs1_data
val out_double = Pipe(io.req.valid, fp_ctrl.typeTagOut === D, intToFpLatency).bits
//io.resp.bits.data := box(ifpu.io.out.bits.data, !io.resp.bits.uop.fp_single)
io.resp.bits.data := box(ifpu.io.out.bits.data, out_double)
io.resp.bits.fflags.valid := ifpu.io.out.valid
io.resp.bits.fflags.bits.uop := io.resp.bits.uop
io.resp.bits.fflags.bits.flags := ifpu.io.out.bits.exc
}
/**
* Iterative/unpipelined functional unit, can only hold a single MicroOp at a time
* assumes at least one register between request and response
*
* TODO allow up to N micro-ops simultaneously.
*
* @param dataWidth width of the data to be passed into the functional unit
*/
abstract class IterativeFunctionalUnit(dataWidth: Int)(implicit p: Parameters)
extends FunctionalUnit(
isPipelined = false,
numStages = 1,
numBypassStages = 0,
dataWidth = dataWidth)
{
val r_uop = Reg(new MicroOp())
val do_kill = Wire(Bool())
do_kill := io.req.bits.kill // irrelevant default
when (io.req.fire) {
// update incoming uop
do_kill := IsKilledByBranch(io.brupdate, io.req.bits.uop) || io.req.bits.kill
r_uop := io.req.bits.uop
r_uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)
} .otherwise {
do_kill := IsKilledByBranch(io.brupdate, r_uop) || io.req.bits.kill
r_uop.br_mask := GetNewBrMask(io.brupdate, r_uop)
}
// assumes at least one pipeline register between request and response
io.resp.bits.uop := r_uop
}
/**
* Divide functional unit.
*
* @param dataWidth data to be passed into the functional unit
*/
class DivUnit(dataWidth: Int)(implicit p: Parameters)
extends IterativeFunctionalUnit(dataWidth)
{
// We don't use the iterative multiply functionality here.
// Instead we use the PipelinedMultiplier
val div = Module(new freechips.rocketchip.rocket.MulDiv(mulDivParams, width = dataWidth))
// request
div.io.req.valid := io.req.valid && !this.do_kill
div.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw
div.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn
div.io.req.bits.in1 := io.req.bits.rs1_data
div.io.req.bits.in2 := io.req.bits.rs2_data
div.io.req.bits.tag := DontCare
io.req.ready := div.io.req.ready
// handle pipeline kills and branch misspeculations
div.io.kill := this.do_kill
// response
io.resp.valid := div.io.resp.valid && !this.do_kill
div.io.resp.ready := io.resp.ready
io.resp.bits.data := div.io.resp.bits.data
}
/**
* Pipelined multiplier functional unit that wraps around the RocketChip pipelined multiplier
*
* @param numStages number of pipeline stages
* @param dataWidth size of the data being passed into the functional unit
*/
class PipelinedMulUnit(numStages: Int, dataWidth: Int)(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = numStages,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = dataWidth)
{
val imul = Module(new PipelinedMultiplier(xLen, numStages))
// request
imul.io.req.valid := io.req.valid
imul.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn
imul.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw
imul.io.req.bits.in1 := io.req.bits.rs1_data
imul.io.req.bits.in2 := io.req.bits.rs2_data
imul.io.req.bits.tag := DontCare
// response
io.resp.bits.data := imul.io.resp.bits.data
} | module DivUnit(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [4:0] io_req_bits_uop_ctrl_op_fcn,
input io_req_bits_uop_ctrl_fcn_dw,
input [7:0] io_req_bits_uop_br_mask,
input [4:0] io_req_bits_uop_rob_idx,
input [5:0] io_req_bits_uop_pdst,
input io_req_bits_uop_bypassable,
input io_req_bits_uop_is_amo,
input io_req_bits_uop_uses_stq,
input [1:0] io_req_bits_uop_dst_rtype,
input [63:0] io_req_bits_rs1_data,
input [63:0] io_req_bits_rs2_data,
input io_req_bits_kill,
input io_resp_ready,
output io_resp_valid,
output [4:0] io_resp_bits_uop_rob_idx,
output [5:0] io_resp_bits_uop_pdst,
output io_resp_bits_uop_bypassable,
output io_resp_bits_uop_is_amo,
output io_resp_bits_uop_uses_stq,
output [1:0] io_resp_bits_uop_dst_rtype,
output [63:0] io_resp_bits_data,
input [7:0] io_brupdate_b1_resolve_mask,
input [7:0] io_brupdate_b1_mispredict_mask
);
wire _div_io_req_ready;
wire _div_io_resp_valid;
reg [7:0] r_uop_br_mask;
reg [4:0] r_uop_rob_idx;
reg [5:0] r_uop_pdst;
reg r_uop_bypassable;
reg r_uop_is_amo;
reg r_uop_uses_stq;
reg [1:0] r_uop_dst_rtype;
wire _GEN = _div_io_req_ready & io_req_valid;
wire do_kill = _GEN ? (|(io_brupdate_b1_mispredict_mask & io_req_bits_uop_br_mask)) | io_req_bits_kill : (|(io_brupdate_b1_mispredict_mask & r_uop_br_mask)) | io_req_bits_kill;
always @(posedge clock) begin
r_uop_br_mask <= _GEN ? io_req_bits_uop_br_mask & ~io_brupdate_b1_resolve_mask : r_uop_br_mask & ~io_brupdate_b1_resolve_mask;
if (_GEN) begin
r_uop_rob_idx <= io_req_bits_uop_rob_idx;
r_uop_pdst <= io_req_bits_uop_pdst;
r_uop_bypassable <= io_req_bits_uop_bypassable;
r_uop_is_amo <= io_req_bits_uop_is_amo;
r_uop_uses_stq <= io_req_bits_uop_uses_stq;
r_uop_dst_rtype <= io_req_bits_uop_dst_rtype;
end
end
MulDiv div (
.clock (clock),
.reset (reset),
.io_req_ready (_div_io_req_ready),
.io_req_valid (io_req_valid & ~do_kill),
.io_req_bits_fn (io_req_bits_uop_ctrl_op_fcn),
.io_req_bits_dw (io_req_bits_uop_ctrl_fcn_dw),
.io_req_bits_in1 (io_req_bits_rs1_data),
.io_req_bits_in2 (io_req_bits_rs2_data),
.io_kill (do_kill),
.io_resp_ready (io_resp_ready),
.io_resp_valid (_div_io_resp_valid),
.io_resp_bits_data (io_resp_bits_data)
);
assign io_req_ready = _div_io_req_ready;
assign io_resp_valid = _div_io_resp_valid & ~do_kill;
assign io_resp_bits_uop_rob_idx = r_uop_rob_idx;
assign io_resp_bits_uop_pdst = r_uop_pdst;
assign io_resp_bits_uop_bypassable = r_uop_bypassable;
assign io_resp_bits_uop_is_amo = r_uop_is_amo;
assign io_resp_bits_uop_uses_stq = r_uop_uses_stq;
assign io_resp_bits_uop_dst_rtype = r_uop_dst_rtype;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
} | module dataArrayWay_1(
input [8:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [63:0] RW0_wdata,
output [63:0] RW0_rdata
);
dataArrayWay_0_ext dataArrayWay_0_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2012 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// BOOM Instruction Dispatcher
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util._
class DispatchIO(implicit p: Parameters) extends BoomBundle
{
// incoming microops from rename2
val ren_uops = Vec(coreWidth, Flipped(DecoupledIO(new MicroOp)))
// outgoing microops to issue queues
// N issues each accept up to dispatchWidth uops
// dispatchWidth may vary between issue queues
val dis_uops = MixedVec(issueParams.map(ip=>Vec(ip.dispatchWidth, DecoupledIO(new MicroOp))))
}
abstract class Dispatcher(implicit p: Parameters) extends BoomModule
{
val io = IO(new DispatchIO)
}
/**
* This Dispatcher assumes worst case, all dispatched uops go to 1 issue queue
* This is equivalent to BOOMv2 behavior
*/
class BasicDispatcher(implicit p: Parameters) extends Dispatcher
{
issueParams.map(ip=>require(ip.dispatchWidth == coreWidth))
val ren_readys = io.dis_uops.map(d=>VecInit(d.map(_.ready)).asUInt).reduce(_&_)
for (w <- 0 until coreWidth) {
io.ren_uops(w).ready := ren_readys(w)
}
for {i <- 0 until issueParams.size
w <- 0 until coreWidth} {
val issueParam = issueParams(i)
val dis = io.dis_uops(i)
dis(w).valid := io.ren_uops(w).valid && ((io.ren_uops(w).bits.iq_type & issueParam.iqType.U) =/= 0.U)
dis(w).bits := io.ren_uops(w).bits
}
}
/**
* Tries to dispatch as many uops as it can to issue queues,
* which may accept fewer than coreWidth per cycle.
* When dispatchWidth == coreWidth, its behavior differs
* from the BasicDispatcher in that it will only stall dispatch when
* an issue queue required by a uop is full.
*/
class CompactingDispatcher(implicit p: Parameters) extends Dispatcher
{
issueParams.map(ip => require(ip.dispatchWidth >= ip.issueWidth))
val ren_readys = Wire(Vec(issueParams.size, Vec(coreWidth, Bool())))
for (((ip, dis), rdy) <- issueParams zip io.dis_uops zip ren_readys) {
val ren = Wire(Vec(coreWidth, Decoupled(new MicroOp)))
ren <> io.ren_uops
val uses_iq = ren map (u => (u.bits.iq_type & ip.iqType.U).orR)
// Only request an issue slot if the uop needs to enter that queue.
(ren zip io.ren_uops zip uses_iq) foreach {case ((u,v),q) =>
u.valid := v.valid && q}
val compactor = Module(new Compactor(coreWidth, ip.dispatchWidth, new MicroOp))
compactor.io.in <> ren
dis <> compactor.io.out
// The queue is considered ready if the uop doesn't use it.
rdy := ren zip uses_iq map {case (u,q) => u.ready || !q}
}
(ren_readys.reduce((r,i) =>
VecInit(r zip i map {case (r,i) =>
r && i})) zip io.ren_uops) foreach {case (r,u) =>
u.ready := r}
} | module BasicDispatcher(
output io_ren_uops_0_ready,
input io_ren_uops_0_valid,
input [6:0] io_ren_uops_0_bits_uopc,
input [31:0] io_ren_uops_0_bits_inst,
input [31:0] io_ren_uops_0_bits_debug_inst,
input io_ren_uops_0_bits_is_rvc,
input [39:0] io_ren_uops_0_bits_debug_pc,
input [2:0] io_ren_uops_0_bits_iq_type,
input [9:0] io_ren_uops_0_bits_fu_code,
input io_ren_uops_0_bits_is_br,
input io_ren_uops_0_bits_is_jalr,
input io_ren_uops_0_bits_is_jal,
input io_ren_uops_0_bits_is_sfb,
input [7:0] io_ren_uops_0_bits_br_mask,
input [2:0] io_ren_uops_0_bits_br_tag,
input [3:0] io_ren_uops_0_bits_ftq_idx,
input io_ren_uops_0_bits_edge_inst,
input [5:0] io_ren_uops_0_bits_pc_lob,
input io_ren_uops_0_bits_taken,
input [19:0] io_ren_uops_0_bits_imm_packed,
input [11:0] io_ren_uops_0_bits_csr_addr,
input [4:0] io_ren_uops_0_bits_rob_idx,
input [2:0] io_ren_uops_0_bits_ldq_idx,
input [2:0] io_ren_uops_0_bits_stq_idx,
input [1:0] io_ren_uops_0_bits_rxq_idx,
input [5:0] io_ren_uops_0_bits_pdst,
input [5:0] io_ren_uops_0_bits_prs1,
input [5:0] io_ren_uops_0_bits_prs2,
input [5:0] io_ren_uops_0_bits_prs3,
input io_ren_uops_0_bits_prs1_busy,
input io_ren_uops_0_bits_prs2_busy,
input io_ren_uops_0_bits_prs3_busy,
input [5:0] io_ren_uops_0_bits_stale_pdst,
input io_ren_uops_0_bits_exception,
input [63:0] io_ren_uops_0_bits_exc_cause,
input io_ren_uops_0_bits_bypassable,
input [4:0] io_ren_uops_0_bits_mem_cmd,
input [1:0] io_ren_uops_0_bits_mem_size,
input io_ren_uops_0_bits_mem_signed,
input io_ren_uops_0_bits_is_fence,
input io_ren_uops_0_bits_is_fencei,
input io_ren_uops_0_bits_is_amo,
input io_ren_uops_0_bits_uses_ldq,
input io_ren_uops_0_bits_uses_stq,
input io_ren_uops_0_bits_is_sys_pc2epc,
input io_ren_uops_0_bits_is_unique,
input io_ren_uops_0_bits_flush_on_commit,
input io_ren_uops_0_bits_ldst_is_rs1,
input [5:0] io_ren_uops_0_bits_ldst,
input [5:0] io_ren_uops_0_bits_lrs1,
input [5:0] io_ren_uops_0_bits_lrs2,
input [5:0] io_ren_uops_0_bits_lrs3,
input io_ren_uops_0_bits_ldst_val,
input [1:0] io_ren_uops_0_bits_dst_rtype,
input [1:0] io_ren_uops_0_bits_lrs1_rtype,
input [1:0] io_ren_uops_0_bits_lrs2_rtype,
input io_ren_uops_0_bits_frs3_en,
input io_ren_uops_0_bits_fp_val,
input io_ren_uops_0_bits_fp_single,
input io_ren_uops_0_bits_xcpt_pf_if,
input io_ren_uops_0_bits_xcpt_ae_if,
input io_ren_uops_0_bits_xcpt_ma_if,
input io_ren_uops_0_bits_bp_debug_if,
input io_ren_uops_0_bits_bp_xcpt_if,
input [1:0] io_ren_uops_0_bits_debug_fsrc,
input [1:0] io_ren_uops_0_bits_debug_tsrc,
input io_dis_uops_2_0_ready,
output io_dis_uops_2_0_valid,
output [6:0] io_dis_uops_2_0_bits_uopc,
output [31:0] io_dis_uops_2_0_bits_inst,
output [31:0] io_dis_uops_2_0_bits_debug_inst,
output io_dis_uops_2_0_bits_is_rvc,
output [39:0] io_dis_uops_2_0_bits_debug_pc,
output [2:0] io_dis_uops_2_0_bits_iq_type,
output [9:0] io_dis_uops_2_0_bits_fu_code,
output io_dis_uops_2_0_bits_is_br,
output io_dis_uops_2_0_bits_is_jalr,
output io_dis_uops_2_0_bits_is_jal,
output io_dis_uops_2_0_bits_is_sfb,
output [7:0] io_dis_uops_2_0_bits_br_mask,
output [2:0] io_dis_uops_2_0_bits_br_tag,
output [3:0] io_dis_uops_2_0_bits_ftq_idx,
output io_dis_uops_2_0_bits_edge_inst,
output [5:0] io_dis_uops_2_0_bits_pc_lob,
output io_dis_uops_2_0_bits_taken,
output [19:0] io_dis_uops_2_0_bits_imm_packed,
output [11:0] io_dis_uops_2_0_bits_csr_addr,
output [4:0] io_dis_uops_2_0_bits_rob_idx,
output [2:0] io_dis_uops_2_0_bits_ldq_idx,
output [2:0] io_dis_uops_2_0_bits_stq_idx,
output [1:0] io_dis_uops_2_0_bits_rxq_idx,
output [5:0] io_dis_uops_2_0_bits_pdst,
output [5:0] io_dis_uops_2_0_bits_prs1,
output [5:0] io_dis_uops_2_0_bits_prs2,
output [5:0] io_dis_uops_2_0_bits_prs3,
output io_dis_uops_2_0_bits_prs1_busy,
output io_dis_uops_2_0_bits_prs2_busy,
output io_dis_uops_2_0_bits_prs3_busy,
output [5:0] io_dis_uops_2_0_bits_stale_pdst,
output io_dis_uops_2_0_bits_exception,
output [63:0] io_dis_uops_2_0_bits_exc_cause,
output io_dis_uops_2_0_bits_bypassable,
output [4:0] io_dis_uops_2_0_bits_mem_cmd,
output [1:0] io_dis_uops_2_0_bits_mem_size,
output io_dis_uops_2_0_bits_mem_signed,
output io_dis_uops_2_0_bits_is_fence,
output io_dis_uops_2_0_bits_is_fencei,
output io_dis_uops_2_0_bits_is_amo,
output io_dis_uops_2_0_bits_uses_ldq,
output io_dis_uops_2_0_bits_uses_stq,
output io_dis_uops_2_0_bits_is_sys_pc2epc,
output io_dis_uops_2_0_bits_is_unique,
output io_dis_uops_2_0_bits_flush_on_commit,
output io_dis_uops_2_0_bits_ldst_is_rs1,
output [5:0] io_dis_uops_2_0_bits_ldst,
output [5:0] io_dis_uops_2_0_bits_lrs1,
output [5:0] io_dis_uops_2_0_bits_lrs2,
output [5:0] io_dis_uops_2_0_bits_lrs3,
output io_dis_uops_2_0_bits_ldst_val,
output [1:0] io_dis_uops_2_0_bits_dst_rtype,
output [1:0] io_dis_uops_2_0_bits_lrs1_rtype,
output [1:0] io_dis_uops_2_0_bits_lrs2_rtype,
output io_dis_uops_2_0_bits_frs3_en,
output io_dis_uops_2_0_bits_fp_val,
output io_dis_uops_2_0_bits_fp_single,
output io_dis_uops_2_0_bits_xcpt_pf_if,
output io_dis_uops_2_0_bits_xcpt_ae_if,
output io_dis_uops_2_0_bits_xcpt_ma_if,
output io_dis_uops_2_0_bits_bp_debug_if,
output io_dis_uops_2_0_bits_bp_xcpt_if,
output [1:0] io_dis_uops_2_0_bits_debug_fsrc,
output [1:0] io_dis_uops_2_0_bits_debug_tsrc,
input io_dis_uops_1_0_ready,
output io_dis_uops_1_0_valid,
output [6:0] io_dis_uops_1_0_bits_uopc,
output [31:0] io_dis_uops_1_0_bits_inst,
output [31:0] io_dis_uops_1_0_bits_debug_inst,
output io_dis_uops_1_0_bits_is_rvc,
output [39:0] io_dis_uops_1_0_bits_debug_pc,
output [2:0] io_dis_uops_1_0_bits_iq_type,
output [9:0] io_dis_uops_1_0_bits_fu_code,
output io_dis_uops_1_0_bits_is_br,
output io_dis_uops_1_0_bits_is_jalr,
output io_dis_uops_1_0_bits_is_jal,
output io_dis_uops_1_0_bits_is_sfb,
output [7:0] io_dis_uops_1_0_bits_br_mask,
output [2:0] io_dis_uops_1_0_bits_br_tag,
output [3:0] io_dis_uops_1_0_bits_ftq_idx,
output io_dis_uops_1_0_bits_edge_inst,
output [5:0] io_dis_uops_1_0_bits_pc_lob,
output io_dis_uops_1_0_bits_taken,
output [19:0] io_dis_uops_1_0_bits_imm_packed,
output [11:0] io_dis_uops_1_0_bits_csr_addr,
output [4:0] io_dis_uops_1_0_bits_rob_idx,
output [2:0] io_dis_uops_1_0_bits_ldq_idx,
output [2:0] io_dis_uops_1_0_bits_stq_idx,
output [1:0] io_dis_uops_1_0_bits_rxq_idx,
output [5:0] io_dis_uops_1_0_bits_pdst,
output [5:0] io_dis_uops_1_0_bits_prs1,
output [5:0] io_dis_uops_1_0_bits_prs2,
output [5:0] io_dis_uops_1_0_bits_prs3,
output io_dis_uops_1_0_bits_prs1_busy,
output io_dis_uops_1_0_bits_prs2_busy,
output [5:0] io_dis_uops_1_0_bits_stale_pdst,
output io_dis_uops_1_0_bits_exception,
output [63:0] io_dis_uops_1_0_bits_exc_cause,
output io_dis_uops_1_0_bits_bypassable,
output [4:0] io_dis_uops_1_0_bits_mem_cmd,
output [1:0] io_dis_uops_1_0_bits_mem_size,
output io_dis_uops_1_0_bits_mem_signed,
output io_dis_uops_1_0_bits_is_fence,
output io_dis_uops_1_0_bits_is_fencei,
output io_dis_uops_1_0_bits_is_amo,
output io_dis_uops_1_0_bits_uses_ldq,
output io_dis_uops_1_0_bits_uses_stq,
output io_dis_uops_1_0_bits_is_sys_pc2epc,
output io_dis_uops_1_0_bits_is_unique,
output io_dis_uops_1_0_bits_flush_on_commit,
output io_dis_uops_1_0_bits_ldst_is_rs1,
output [5:0] io_dis_uops_1_0_bits_ldst,
output [5:0] io_dis_uops_1_0_bits_lrs1,
output [5:0] io_dis_uops_1_0_bits_lrs2,
output [5:0] io_dis_uops_1_0_bits_lrs3,
output io_dis_uops_1_0_bits_ldst_val,
output [1:0] io_dis_uops_1_0_bits_dst_rtype,
output [1:0] io_dis_uops_1_0_bits_lrs1_rtype,
output [1:0] io_dis_uops_1_0_bits_lrs2_rtype,
output io_dis_uops_1_0_bits_frs3_en,
output io_dis_uops_1_0_bits_fp_val,
output io_dis_uops_1_0_bits_fp_single,
output io_dis_uops_1_0_bits_xcpt_pf_if,
output io_dis_uops_1_0_bits_xcpt_ae_if,
output io_dis_uops_1_0_bits_xcpt_ma_if,
output io_dis_uops_1_0_bits_bp_debug_if,
output io_dis_uops_1_0_bits_bp_xcpt_if,
output [1:0] io_dis_uops_1_0_bits_debug_fsrc,
output [1:0] io_dis_uops_1_0_bits_debug_tsrc,
input io_dis_uops_0_0_ready,
output io_dis_uops_0_0_valid,
output [6:0] io_dis_uops_0_0_bits_uopc,
output [31:0] io_dis_uops_0_0_bits_inst,
output [31:0] io_dis_uops_0_0_bits_debug_inst,
output io_dis_uops_0_0_bits_is_rvc,
output [39:0] io_dis_uops_0_0_bits_debug_pc,
output [2:0] io_dis_uops_0_0_bits_iq_type,
output [9:0] io_dis_uops_0_0_bits_fu_code,
output io_dis_uops_0_0_bits_is_br,
output io_dis_uops_0_0_bits_is_jalr,
output io_dis_uops_0_0_bits_is_jal,
output io_dis_uops_0_0_bits_is_sfb,
output [7:0] io_dis_uops_0_0_bits_br_mask,
output [2:0] io_dis_uops_0_0_bits_br_tag,
output [3:0] io_dis_uops_0_0_bits_ftq_idx,
output io_dis_uops_0_0_bits_edge_inst,
output [5:0] io_dis_uops_0_0_bits_pc_lob,
output io_dis_uops_0_0_bits_taken,
output [19:0] io_dis_uops_0_0_bits_imm_packed,
output [11:0] io_dis_uops_0_0_bits_csr_addr,
output [4:0] io_dis_uops_0_0_bits_rob_idx,
output [2:0] io_dis_uops_0_0_bits_ldq_idx,
output [2:0] io_dis_uops_0_0_bits_stq_idx,
output [1:0] io_dis_uops_0_0_bits_rxq_idx,
output [5:0] io_dis_uops_0_0_bits_pdst,
output [5:0] io_dis_uops_0_0_bits_prs1,
output [5:0] io_dis_uops_0_0_bits_prs2,
output [5:0] io_dis_uops_0_0_bits_prs3,
output io_dis_uops_0_0_bits_prs1_busy,
output io_dis_uops_0_0_bits_prs2_busy,
output [5:0] io_dis_uops_0_0_bits_stale_pdst,
output io_dis_uops_0_0_bits_exception,
output [63:0] io_dis_uops_0_0_bits_exc_cause,
output io_dis_uops_0_0_bits_bypassable,
output [4:0] io_dis_uops_0_0_bits_mem_cmd,
output [1:0] io_dis_uops_0_0_bits_mem_size,
output io_dis_uops_0_0_bits_mem_signed,
output io_dis_uops_0_0_bits_is_fence,
output io_dis_uops_0_0_bits_is_fencei,
output io_dis_uops_0_0_bits_is_amo,
output io_dis_uops_0_0_bits_uses_ldq,
output io_dis_uops_0_0_bits_uses_stq,
output io_dis_uops_0_0_bits_is_sys_pc2epc,
output io_dis_uops_0_0_bits_is_unique,
output io_dis_uops_0_0_bits_flush_on_commit,
output io_dis_uops_0_0_bits_ldst_is_rs1,
output [5:0] io_dis_uops_0_0_bits_ldst,
output [5:0] io_dis_uops_0_0_bits_lrs1,
output [5:0] io_dis_uops_0_0_bits_lrs2,
output [5:0] io_dis_uops_0_0_bits_lrs3,
output io_dis_uops_0_0_bits_ldst_val,
output [1:0] io_dis_uops_0_0_bits_dst_rtype,
output [1:0] io_dis_uops_0_0_bits_lrs1_rtype,
output [1:0] io_dis_uops_0_0_bits_lrs2_rtype,
output io_dis_uops_0_0_bits_frs3_en,
output io_dis_uops_0_0_bits_fp_val,
output io_dis_uops_0_0_bits_fp_single,
output io_dis_uops_0_0_bits_xcpt_pf_if,
output io_dis_uops_0_0_bits_xcpt_ae_if,
output io_dis_uops_0_0_bits_xcpt_ma_if,
output io_dis_uops_0_0_bits_bp_debug_if,
output io_dis_uops_0_0_bits_bp_xcpt_if,
output [1:0] io_dis_uops_0_0_bits_debug_fsrc,
output [1:0] io_dis_uops_0_0_bits_debug_tsrc
);
assign io_ren_uops_0_ready = io_dis_uops_0_0_ready & io_dis_uops_1_0_ready & io_dis_uops_2_0_ready;
assign io_dis_uops_2_0_valid = io_ren_uops_0_valid & io_ren_uops_0_bits_iq_type[2];
assign io_dis_uops_2_0_bits_uopc = io_ren_uops_0_bits_uopc;
assign io_dis_uops_2_0_bits_inst = io_ren_uops_0_bits_inst;
assign io_dis_uops_2_0_bits_debug_inst = io_ren_uops_0_bits_debug_inst;
assign io_dis_uops_2_0_bits_is_rvc = io_ren_uops_0_bits_is_rvc;
assign io_dis_uops_2_0_bits_debug_pc = io_ren_uops_0_bits_debug_pc;
assign io_dis_uops_2_0_bits_iq_type = io_ren_uops_0_bits_iq_type;
assign io_dis_uops_2_0_bits_fu_code = io_ren_uops_0_bits_fu_code;
assign io_dis_uops_2_0_bits_is_br = io_ren_uops_0_bits_is_br;
assign io_dis_uops_2_0_bits_is_jalr = io_ren_uops_0_bits_is_jalr;
assign io_dis_uops_2_0_bits_is_jal = io_ren_uops_0_bits_is_jal;
assign io_dis_uops_2_0_bits_is_sfb = io_ren_uops_0_bits_is_sfb;
assign io_dis_uops_2_0_bits_br_mask = io_ren_uops_0_bits_br_mask;
assign io_dis_uops_2_0_bits_br_tag = io_ren_uops_0_bits_br_tag;
assign io_dis_uops_2_0_bits_ftq_idx = io_ren_uops_0_bits_ftq_idx;
assign io_dis_uops_2_0_bits_edge_inst = io_ren_uops_0_bits_edge_inst;
assign io_dis_uops_2_0_bits_pc_lob = io_ren_uops_0_bits_pc_lob;
assign io_dis_uops_2_0_bits_taken = io_ren_uops_0_bits_taken;
assign io_dis_uops_2_0_bits_imm_packed = io_ren_uops_0_bits_imm_packed;
assign io_dis_uops_2_0_bits_csr_addr = io_ren_uops_0_bits_csr_addr;
assign io_dis_uops_2_0_bits_rob_idx = io_ren_uops_0_bits_rob_idx;
assign io_dis_uops_2_0_bits_ldq_idx = io_ren_uops_0_bits_ldq_idx;
assign io_dis_uops_2_0_bits_stq_idx = io_ren_uops_0_bits_stq_idx;
assign io_dis_uops_2_0_bits_rxq_idx = io_ren_uops_0_bits_rxq_idx;
assign io_dis_uops_2_0_bits_pdst = io_ren_uops_0_bits_pdst;
assign io_dis_uops_2_0_bits_prs1 = io_ren_uops_0_bits_prs1;
assign io_dis_uops_2_0_bits_prs2 = io_ren_uops_0_bits_prs2;
assign io_dis_uops_2_0_bits_prs3 = io_ren_uops_0_bits_prs3;
assign io_dis_uops_2_0_bits_prs1_busy = io_ren_uops_0_bits_prs1_busy;
assign io_dis_uops_2_0_bits_prs2_busy = io_ren_uops_0_bits_prs2_busy;
assign io_dis_uops_2_0_bits_prs3_busy = io_ren_uops_0_bits_prs3_busy;
assign io_dis_uops_2_0_bits_stale_pdst = io_ren_uops_0_bits_stale_pdst;
assign io_dis_uops_2_0_bits_exception = io_ren_uops_0_bits_exception;
assign io_dis_uops_2_0_bits_exc_cause = io_ren_uops_0_bits_exc_cause;
assign io_dis_uops_2_0_bits_bypassable = io_ren_uops_0_bits_bypassable;
assign io_dis_uops_2_0_bits_mem_cmd = io_ren_uops_0_bits_mem_cmd;
assign io_dis_uops_2_0_bits_mem_size = io_ren_uops_0_bits_mem_size;
assign io_dis_uops_2_0_bits_mem_signed = io_ren_uops_0_bits_mem_signed;
assign io_dis_uops_2_0_bits_is_fence = io_ren_uops_0_bits_is_fence;
assign io_dis_uops_2_0_bits_is_fencei = io_ren_uops_0_bits_is_fencei;
assign io_dis_uops_2_0_bits_is_amo = io_ren_uops_0_bits_is_amo;
assign io_dis_uops_2_0_bits_uses_ldq = io_ren_uops_0_bits_uses_ldq;
assign io_dis_uops_2_0_bits_uses_stq = io_ren_uops_0_bits_uses_stq;
assign io_dis_uops_2_0_bits_is_sys_pc2epc = io_ren_uops_0_bits_is_sys_pc2epc;
assign io_dis_uops_2_0_bits_is_unique = io_ren_uops_0_bits_is_unique;
assign io_dis_uops_2_0_bits_flush_on_commit = io_ren_uops_0_bits_flush_on_commit;
assign io_dis_uops_2_0_bits_ldst_is_rs1 = io_ren_uops_0_bits_ldst_is_rs1;
assign io_dis_uops_2_0_bits_ldst = io_ren_uops_0_bits_ldst;
assign io_dis_uops_2_0_bits_lrs1 = io_ren_uops_0_bits_lrs1;
assign io_dis_uops_2_0_bits_lrs2 = io_ren_uops_0_bits_lrs2;
assign io_dis_uops_2_0_bits_lrs3 = io_ren_uops_0_bits_lrs3;
assign io_dis_uops_2_0_bits_ldst_val = io_ren_uops_0_bits_ldst_val;
assign io_dis_uops_2_0_bits_dst_rtype = io_ren_uops_0_bits_dst_rtype;
assign io_dis_uops_2_0_bits_lrs1_rtype = io_ren_uops_0_bits_lrs1_rtype;
assign io_dis_uops_2_0_bits_lrs2_rtype = io_ren_uops_0_bits_lrs2_rtype;
assign io_dis_uops_2_0_bits_frs3_en = io_ren_uops_0_bits_frs3_en;
assign io_dis_uops_2_0_bits_fp_val = io_ren_uops_0_bits_fp_val;
assign io_dis_uops_2_0_bits_fp_single = io_ren_uops_0_bits_fp_single;
assign io_dis_uops_2_0_bits_xcpt_pf_if = io_ren_uops_0_bits_xcpt_pf_if;
assign io_dis_uops_2_0_bits_xcpt_ae_if = io_ren_uops_0_bits_xcpt_ae_if;
assign io_dis_uops_2_0_bits_xcpt_ma_if = io_ren_uops_0_bits_xcpt_ma_if;
assign io_dis_uops_2_0_bits_bp_debug_if = io_ren_uops_0_bits_bp_debug_if;
assign io_dis_uops_2_0_bits_bp_xcpt_if = io_ren_uops_0_bits_bp_xcpt_if;
assign io_dis_uops_2_0_bits_debug_fsrc = io_ren_uops_0_bits_debug_fsrc;
assign io_dis_uops_2_0_bits_debug_tsrc = io_ren_uops_0_bits_debug_tsrc;
assign io_dis_uops_1_0_valid = io_ren_uops_0_valid & io_ren_uops_0_bits_iq_type[0];
assign io_dis_uops_1_0_bits_uopc = io_ren_uops_0_bits_uopc;
assign io_dis_uops_1_0_bits_inst = io_ren_uops_0_bits_inst;
assign io_dis_uops_1_0_bits_debug_inst = io_ren_uops_0_bits_debug_inst;
assign io_dis_uops_1_0_bits_is_rvc = io_ren_uops_0_bits_is_rvc;
assign io_dis_uops_1_0_bits_debug_pc = io_ren_uops_0_bits_debug_pc;
assign io_dis_uops_1_0_bits_iq_type = io_ren_uops_0_bits_iq_type;
assign io_dis_uops_1_0_bits_fu_code = io_ren_uops_0_bits_fu_code;
assign io_dis_uops_1_0_bits_is_br = io_ren_uops_0_bits_is_br;
assign io_dis_uops_1_0_bits_is_jalr = io_ren_uops_0_bits_is_jalr;
assign io_dis_uops_1_0_bits_is_jal = io_ren_uops_0_bits_is_jal;
assign io_dis_uops_1_0_bits_is_sfb = io_ren_uops_0_bits_is_sfb;
assign io_dis_uops_1_0_bits_br_mask = io_ren_uops_0_bits_br_mask;
assign io_dis_uops_1_0_bits_br_tag = io_ren_uops_0_bits_br_tag;
assign io_dis_uops_1_0_bits_ftq_idx = io_ren_uops_0_bits_ftq_idx;
assign io_dis_uops_1_0_bits_edge_inst = io_ren_uops_0_bits_edge_inst;
assign io_dis_uops_1_0_bits_pc_lob = io_ren_uops_0_bits_pc_lob;
assign io_dis_uops_1_0_bits_taken = io_ren_uops_0_bits_taken;
assign io_dis_uops_1_0_bits_imm_packed = io_ren_uops_0_bits_imm_packed;
assign io_dis_uops_1_0_bits_csr_addr = io_ren_uops_0_bits_csr_addr;
assign io_dis_uops_1_0_bits_rob_idx = io_ren_uops_0_bits_rob_idx;
assign io_dis_uops_1_0_bits_ldq_idx = io_ren_uops_0_bits_ldq_idx;
assign io_dis_uops_1_0_bits_stq_idx = io_ren_uops_0_bits_stq_idx;
assign io_dis_uops_1_0_bits_rxq_idx = io_ren_uops_0_bits_rxq_idx;
assign io_dis_uops_1_0_bits_pdst = io_ren_uops_0_bits_pdst;
assign io_dis_uops_1_0_bits_prs1 = io_ren_uops_0_bits_prs1;
assign io_dis_uops_1_0_bits_prs2 = io_ren_uops_0_bits_prs2;
assign io_dis_uops_1_0_bits_prs3 = io_ren_uops_0_bits_prs3;
assign io_dis_uops_1_0_bits_prs1_busy = io_ren_uops_0_bits_prs1_busy;
assign io_dis_uops_1_0_bits_prs2_busy = io_ren_uops_0_bits_prs2_busy;
assign io_dis_uops_1_0_bits_stale_pdst = io_ren_uops_0_bits_stale_pdst;
assign io_dis_uops_1_0_bits_exception = io_ren_uops_0_bits_exception;
assign io_dis_uops_1_0_bits_exc_cause = io_ren_uops_0_bits_exc_cause;
assign io_dis_uops_1_0_bits_bypassable = io_ren_uops_0_bits_bypassable;
assign io_dis_uops_1_0_bits_mem_cmd = io_ren_uops_0_bits_mem_cmd;
assign io_dis_uops_1_0_bits_mem_size = io_ren_uops_0_bits_mem_size;
assign io_dis_uops_1_0_bits_mem_signed = io_ren_uops_0_bits_mem_signed;
assign io_dis_uops_1_0_bits_is_fence = io_ren_uops_0_bits_is_fence;
assign io_dis_uops_1_0_bits_is_fencei = io_ren_uops_0_bits_is_fencei;
assign io_dis_uops_1_0_bits_is_amo = io_ren_uops_0_bits_is_amo;
assign io_dis_uops_1_0_bits_uses_ldq = io_ren_uops_0_bits_uses_ldq;
assign io_dis_uops_1_0_bits_uses_stq = io_ren_uops_0_bits_uses_stq;
assign io_dis_uops_1_0_bits_is_sys_pc2epc = io_ren_uops_0_bits_is_sys_pc2epc;
assign io_dis_uops_1_0_bits_is_unique = io_ren_uops_0_bits_is_unique;
assign io_dis_uops_1_0_bits_flush_on_commit = io_ren_uops_0_bits_flush_on_commit;
assign io_dis_uops_1_0_bits_ldst_is_rs1 = io_ren_uops_0_bits_ldst_is_rs1;
assign io_dis_uops_1_0_bits_ldst = io_ren_uops_0_bits_ldst;
assign io_dis_uops_1_0_bits_lrs1 = io_ren_uops_0_bits_lrs1;
assign io_dis_uops_1_0_bits_lrs2 = io_ren_uops_0_bits_lrs2;
assign io_dis_uops_1_0_bits_lrs3 = io_ren_uops_0_bits_lrs3;
assign io_dis_uops_1_0_bits_ldst_val = io_ren_uops_0_bits_ldst_val;
assign io_dis_uops_1_0_bits_dst_rtype = io_ren_uops_0_bits_dst_rtype;
assign io_dis_uops_1_0_bits_lrs1_rtype = io_ren_uops_0_bits_lrs1_rtype;
assign io_dis_uops_1_0_bits_lrs2_rtype = io_ren_uops_0_bits_lrs2_rtype;
assign io_dis_uops_1_0_bits_frs3_en = io_ren_uops_0_bits_frs3_en;
assign io_dis_uops_1_0_bits_fp_val = io_ren_uops_0_bits_fp_val;
assign io_dis_uops_1_0_bits_fp_single = io_ren_uops_0_bits_fp_single;
assign io_dis_uops_1_0_bits_xcpt_pf_if = io_ren_uops_0_bits_xcpt_pf_if;
assign io_dis_uops_1_0_bits_xcpt_ae_if = io_ren_uops_0_bits_xcpt_ae_if;
assign io_dis_uops_1_0_bits_xcpt_ma_if = io_ren_uops_0_bits_xcpt_ma_if;
assign io_dis_uops_1_0_bits_bp_debug_if = io_ren_uops_0_bits_bp_debug_if;
assign io_dis_uops_1_0_bits_bp_xcpt_if = io_ren_uops_0_bits_bp_xcpt_if;
assign io_dis_uops_1_0_bits_debug_fsrc = io_ren_uops_0_bits_debug_fsrc;
assign io_dis_uops_1_0_bits_debug_tsrc = io_ren_uops_0_bits_debug_tsrc;
assign io_dis_uops_0_0_valid = io_ren_uops_0_valid & io_ren_uops_0_bits_iq_type[1];
assign io_dis_uops_0_0_bits_uopc = io_ren_uops_0_bits_uopc;
assign io_dis_uops_0_0_bits_inst = io_ren_uops_0_bits_inst;
assign io_dis_uops_0_0_bits_debug_inst = io_ren_uops_0_bits_debug_inst;
assign io_dis_uops_0_0_bits_is_rvc = io_ren_uops_0_bits_is_rvc;
assign io_dis_uops_0_0_bits_debug_pc = io_ren_uops_0_bits_debug_pc;
assign io_dis_uops_0_0_bits_iq_type = io_ren_uops_0_bits_iq_type;
assign io_dis_uops_0_0_bits_fu_code = io_ren_uops_0_bits_fu_code;
assign io_dis_uops_0_0_bits_is_br = io_ren_uops_0_bits_is_br;
assign io_dis_uops_0_0_bits_is_jalr = io_ren_uops_0_bits_is_jalr;
assign io_dis_uops_0_0_bits_is_jal = io_ren_uops_0_bits_is_jal;
assign io_dis_uops_0_0_bits_is_sfb = io_ren_uops_0_bits_is_sfb;
assign io_dis_uops_0_0_bits_br_mask = io_ren_uops_0_bits_br_mask;
assign io_dis_uops_0_0_bits_br_tag = io_ren_uops_0_bits_br_tag;
assign io_dis_uops_0_0_bits_ftq_idx = io_ren_uops_0_bits_ftq_idx;
assign io_dis_uops_0_0_bits_edge_inst = io_ren_uops_0_bits_edge_inst;
assign io_dis_uops_0_0_bits_pc_lob = io_ren_uops_0_bits_pc_lob;
assign io_dis_uops_0_0_bits_taken = io_ren_uops_0_bits_taken;
assign io_dis_uops_0_0_bits_imm_packed = io_ren_uops_0_bits_imm_packed;
assign io_dis_uops_0_0_bits_csr_addr = io_ren_uops_0_bits_csr_addr;
assign io_dis_uops_0_0_bits_rob_idx = io_ren_uops_0_bits_rob_idx;
assign io_dis_uops_0_0_bits_ldq_idx = io_ren_uops_0_bits_ldq_idx;
assign io_dis_uops_0_0_bits_stq_idx = io_ren_uops_0_bits_stq_idx;
assign io_dis_uops_0_0_bits_rxq_idx = io_ren_uops_0_bits_rxq_idx;
assign io_dis_uops_0_0_bits_pdst = io_ren_uops_0_bits_pdst;
assign io_dis_uops_0_0_bits_prs1 = io_ren_uops_0_bits_prs1;
assign io_dis_uops_0_0_bits_prs2 = io_ren_uops_0_bits_prs2;
assign io_dis_uops_0_0_bits_prs3 = io_ren_uops_0_bits_prs3;
assign io_dis_uops_0_0_bits_prs1_busy = io_ren_uops_0_bits_prs1_busy;
assign io_dis_uops_0_0_bits_prs2_busy = io_ren_uops_0_bits_prs2_busy;
assign io_dis_uops_0_0_bits_stale_pdst = io_ren_uops_0_bits_stale_pdst;
assign io_dis_uops_0_0_bits_exception = io_ren_uops_0_bits_exception;
assign io_dis_uops_0_0_bits_exc_cause = io_ren_uops_0_bits_exc_cause;
assign io_dis_uops_0_0_bits_bypassable = io_ren_uops_0_bits_bypassable;
assign io_dis_uops_0_0_bits_mem_cmd = io_ren_uops_0_bits_mem_cmd;
assign io_dis_uops_0_0_bits_mem_size = io_ren_uops_0_bits_mem_size;
assign io_dis_uops_0_0_bits_mem_signed = io_ren_uops_0_bits_mem_signed;
assign io_dis_uops_0_0_bits_is_fence = io_ren_uops_0_bits_is_fence;
assign io_dis_uops_0_0_bits_is_fencei = io_ren_uops_0_bits_is_fencei;
assign io_dis_uops_0_0_bits_is_amo = io_ren_uops_0_bits_is_amo;
assign io_dis_uops_0_0_bits_uses_ldq = io_ren_uops_0_bits_uses_ldq;
assign io_dis_uops_0_0_bits_uses_stq = io_ren_uops_0_bits_uses_stq;
assign io_dis_uops_0_0_bits_is_sys_pc2epc = io_ren_uops_0_bits_is_sys_pc2epc;
assign io_dis_uops_0_0_bits_is_unique = io_ren_uops_0_bits_is_unique;
assign io_dis_uops_0_0_bits_flush_on_commit = io_ren_uops_0_bits_flush_on_commit;
assign io_dis_uops_0_0_bits_ldst_is_rs1 = io_ren_uops_0_bits_ldst_is_rs1;
assign io_dis_uops_0_0_bits_ldst = io_ren_uops_0_bits_ldst;
assign io_dis_uops_0_0_bits_lrs1 = io_ren_uops_0_bits_lrs1;
assign io_dis_uops_0_0_bits_lrs2 = io_ren_uops_0_bits_lrs2;
assign io_dis_uops_0_0_bits_lrs3 = io_ren_uops_0_bits_lrs3;
assign io_dis_uops_0_0_bits_ldst_val = io_ren_uops_0_bits_ldst_val;
assign io_dis_uops_0_0_bits_dst_rtype = io_ren_uops_0_bits_dst_rtype;
assign io_dis_uops_0_0_bits_lrs1_rtype = io_ren_uops_0_bits_lrs1_rtype;
assign io_dis_uops_0_0_bits_lrs2_rtype = io_ren_uops_0_bits_lrs2_rtype;
assign io_dis_uops_0_0_bits_frs3_en = io_ren_uops_0_bits_frs3_en;
assign io_dis_uops_0_0_bits_fp_val = io_ren_uops_0_bits_fp_val;
assign io_dis_uops_0_0_bits_fp_single = io_ren_uops_0_bits_fp_single;
assign io_dis_uops_0_0_bits_xcpt_pf_if = io_ren_uops_0_bits_xcpt_pf_if;
assign io_dis_uops_0_0_bits_xcpt_ae_if = io_ren_uops_0_bits_xcpt_ae_if;
assign io_dis_uops_0_0_bits_xcpt_ma_if = io_ren_uops_0_bits_xcpt_ma_if;
assign io_dis_uops_0_0_bits_bp_debug_if = io_ren_uops_0_bits_bp_debug_if;
assign io_dis_uops_0_0_bits_bp_xcpt_if = io_ren_uops_0_bits_bp_xcpt_if;
assign io_dis_uops_0_0_bits_debug_fsrc = io_ren_uops_0_bits_debug_fsrc;
assign io_dis_uops_0_0_bits_debug_tsrc = io_ren_uops_0_bits_debug_tsrc;
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(t))
val out = Decoupled(new Flit(flitWidth))
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))
data(0) := DontCare // unused, DCE this
}
}
io.busy := io.out.valid
}
class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(t)
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits := (if (dataBeats == 1) {
io.in.bits.flit.asTypeOf(t)
} else {
Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)
})
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit
}
}
}
io.busy := beat =/= 0.U
}
class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Phit(phitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail
}
}
}
object FlitToPhit {
def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {
val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))
flit2phit.io.in <> flit
flit2phit.io.out
}
}
class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Decoupled(new Flit(flitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat) := io.in.bits.phit
}
}
}
}
object PhitToFlit {
def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in <> phit
phit2flit.io.out
}
def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in.valid := phit.valid
phit2flit.io.in.bits := phit.bits
when (phit.valid) { assert(phit2flit.io.in.ready) }
val out = Wire(Valid(new Flit(flitWidth)))
out.valid := phit2flit.io.out.valid
out.bits := phit2flit.io.out.bits
phit2flit.io.out.ready := true.B
out
}
}
class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))
val out = Decoupled(new Phit(phitWidth))
})
if (channels == 1) {
io.out <> io.in(0)
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val chosen_reg = Reg(UInt(headerWidth.W))
val chosen_prio = PriorityEncoder(io.in.map(_.valid))
val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.out.valid := VecInit(io.in.map(_.valid))(chosen)
io.out.bits.phit := Mux(beat < headerBeats.U,
chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),
VecInit(io.in.map(_.bits.phit))(chosen))
for (i <- 0 until channels) {
io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U
}
when (io.out.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) { chosen_reg := chosen_prio }
}
}
}
class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Vec(channels, Decoupled(new Phit(phitWidth)))
})
if (channels == 1) {
io.out(0) <> io.in
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))
val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)
for (c <- 0 until channels) {
io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U
io.out(c).bits.phit := io.in.bits.phit
}
when (io.in.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat < headerBeats.U) {
channel_vec(header_idx) := io.in.bits.phit
}
}
}
}
class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Flipped(Decoupled(new Flit(flitWidth)))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = io.out.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)
}
io.out.valid := io.in.valid && credits < bufferSz.U
io.out.bits.flit := io.in.bits.flit
io.in.ready := io.out.ready && credits < bufferSz.U
io.credit.ready := true.B
}
class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Decoupled(new Flit(flitWidth))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = buffer.io.deq.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credit_incr + Mux(credit_decr, 0.U, credits)
}
buffer.io.enq.valid := io.in.valid
buffer.io.enq.bits := io.in.bits
io.in.ready := true.B
when (io.in.valid) { assert(buffer.io.enq.ready) }
io.out <> buffer.io.deq
io.credit.valid := credits =/= 0.U
io.credit.bits.flit := credits - 1.U
} | module GenericDeserializer_TLBeatw87_f32(
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits_flit,
input io_out_ready,
output io_out_valid,
output io_out_bits_head,
output io_out_bits_tail
);
reg [31:0] data_0;
reg [31:0] data_1;
reg [1:0] beat;
wire io_in_ready_0 = io_out_ready | beat != 2'h2;
wire _beat_T = beat == 2'h2;
wire _GEN = io_in_ready_0 & io_in_valid;
wire _GEN_0 = beat == 2'h2;
always @(posedge clock) begin
if (~_GEN | _GEN_0 | beat[0]) begin
end
else
data_0 <= io_in_bits_flit;
if (~_GEN | _GEN_0 | ~(beat[0])) begin
end
else
data_1 <= io_in_bits_flit;
if (reset)
beat <= 2'h0;
else if (_GEN)
beat <= _beat_T ? 2'h0 : beat + 2'h1;
end
assign io_in_ready = io_in_ready_0;
assign io_out_valid = io_in_valid & _beat_T;
assign io_out_bits_head = data_0[1];
assign io_out_bits_tail = data_0[0];
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
} | module hi_us_4(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input [6:0] W0_addr,
input W0_clk,
input [3:0] W0_data,
input [3:0] W0_mask
);
hi_us_ext hi_us_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (1'h1),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix}
// A branch prediction for a single instruction
class BranchPrediction(implicit p: Parameters) extends BoomBundle()(p)
{
// If this is a branch, do we take it?
val taken = Bool()
// Is this a branch?
val is_br = Bool()
// Is this a JAL?
val is_jal = Bool()
// What is the target of his branch/jump? Do we know the target?
val predicted_pc = Valid(UInt(vaddrBitsExtended.W))
}
// A branch prediction for a entire fetch-width worth of instructions
// This is typically merged from individual predictions from the banked
// predictor
class BranchPredictionBundle(implicit p: Parameters) extends BoomBundle()(p)
with HasBoomFrontendParameters
{
val pc = UInt(vaddrBitsExtended.W)
val preds = Vec(fetchWidth, new BranchPrediction)
val meta = Output(Vec(nBanks, UInt(bpdMaxMetaLength.W)))
val lhist = Output(Vec(nBanks, UInt(localHistoryLength.W)))
}
// A branch update for a fetch-width worth of instructions
class BranchPredictionUpdate(implicit p: Parameters) extends BoomBundle()(p)
with HasBoomFrontendParameters
{
// Indicates that this update is due to a speculated misprediction
// Local predictors typically update themselves with speculative info
// Global predictors only care about non-speculative updates
val is_mispredict_update = Bool()
val is_repair_update = Bool()
val btb_mispredicts = UInt(fetchWidth.W)
def is_btb_mispredict_update = btb_mispredicts =/= 0.U
def is_commit_update = !(is_mispredict_update || is_repair_update || is_btb_mispredict_update)
val pc = UInt(vaddrBitsExtended.W)
// Mask of instructions which are branches.
// If these are not cfi_idx, then they were predicted not taken
val br_mask = UInt(fetchWidth.W)
// Which CFI was taken/mispredicted (if any)
val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W))
// Was the cfi taken?
val cfi_taken = Bool()
// Was the cfi mispredicted from the original prediction?
val cfi_mispredicted = Bool()
// Was the cfi a br?
val cfi_is_br = Bool()
// Was the cfi a jal/jalr?
val cfi_is_jal = Bool()
// Was the cfi a jalr
val cfi_is_jalr = Bool()
//val cfi_is_ret = Bool()
val ghist = new GlobalHistory
val lhist = Vec(nBanks, UInt(localHistoryLength.W))
// What did this CFI jump to?
val target = UInt(vaddrBitsExtended.W)
val meta = Vec(nBanks, UInt(bpdMaxMetaLength.W))
}
// A branch update to a single bank
class BranchPredictionBankUpdate(implicit p: Parameters) extends BoomBundle()(p)
with HasBoomFrontendParameters
{
val is_mispredict_update = Bool()
val is_repair_update = Bool()
val btb_mispredicts = UInt(bankWidth.W)
def is_btb_mispredict_update = btb_mispredicts =/= 0.U
def is_commit_update = !(is_mispredict_update || is_repair_update || is_btb_mispredict_update)
val pc = UInt(vaddrBitsExtended.W)
val br_mask = UInt(bankWidth.W)
val cfi_idx = Valid(UInt(log2Ceil(bankWidth).W))
val cfi_taken = Bool()
val cfi_mispredicted = Bool()
val cfi_is_br = Bool()
val cfi_is_jal = Bool()
val cfi_is_jalr = Bool()
val ghist = UInt(globalHistoryLength.W)
val lhist = UInt(localHistoryLength.W)
val target = UInt(vaddrBitsExtended.W)
val meta = UInt(bpdMaxMetaLength.W)
}
class BranchPredictionRequest(implicit p: Parameters) extends BoomBundle()(p)
{
val pc = UInt(vaddrBitsExtended.W)
val ghist = new GlobalHistory
}
class BranchPredictionBankResponse(implicit p: Parameters) extends BoomBundle()(p)
with HasBoomFrontendParameters
{
val f1 = Vec(bankWidth, new BranchPrediction)
val f2 = Vec(bankWidth, new BranchPrediction)
val f3 = Vec(bankWidth, new BranchPrediction)
}
abstract class BranchPredictorBank(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
val metaSz = 0
def nInputs = 1
val mems: Seq[Tuple3[String, Int, Int]]
val io = IO(new Bundle {
val f0_valid = Input(Bool())
val f0_pc = Input(UInt(vaddrBitsExtended.W))
val f0_mask = Input(UInt(bankWidth.W))
// Local history not available until end of f1
val f1_ghist = Input(UInt(globalHistoryLength.W))
val f1_lhist = Input(UInt(localHistoryLength.W))
val resp_in = Input(Vec(nInputs, new BranchPredictionBankResponse))
val resp = Output(new BranchPredictionBankResponse)
// Store the meta as a UInt, use width inference to figure out the shape
val f3_meta = Output(UInt(bpdMaxMetaLength.W))
val f3_fire = Input(Bool())
val update = Input(Valid(new BranchPredictionBankUpdate))
})
io.resp := io.resp_in(0)
io.f3_meta := 0.U
val s0_idx = fetchIdx(io.f0_pc)
val s1_idx = RegNext(s0_idx)
val s2_idx = RegNext(s1_idx)
val s3_idx = RegNext(s2_idx)
val s0_valid = io.f0_valid
val s1_valid = RegNext(s0_valid)
val s2_valid = RegNext(s1_valid)
val s3_valid = RegNext(s2_valid)
val s0_mask = io.f0_mask
val s1_mask = RegNext(s0_mask)
val s2_mask = RegNext(s1_mask)
val s3_mask = RegNext(s2_mask)
val s0_pc = io.f0_pc
val s1_pc = RegNext(s0_pc)
val s0_update = io.update
val s0_update_idx = fetchIdx(io.update.bits.pc)
val s0_update_valid = io.update.valid
val s1_update = RegNext(s0_update)
val s1_update_idx = RegNext(s0_update_idx)
val s1_update_valid = RegNext(s0_update_valid)
}
class BranchPredictor(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
val io = IO(new Bundle {
// Requests and responses
val f0_req = Input(Valid(new BranchPredictionRequest))
val resp = Output(new Bundle {
val f1 = new BranchPredictionBundle
val f2 = new BranchPredictionBundle
val f3 = new BranchPredictionBundle
})
val f3_fire = Input(Bool())
// Update
val update = Input(Valid(new BranchPredictionUpdate))
})
var total_memsize = 0
val bpdStr = new StringBuilder
bpdStr.append(BoomCoreStringPrefix("==Branch Predictor Memory Sizes==\n"))
val banked_predictors = (0 until nBanks) map ( b => {
val m = Module(if (useBPD) new ComposedBranchPredictorBank else new NullBranchPredictorBank)
for ((n, d, w) <- m.mems) {
bpdStr.append(BoomCoreStringPrefix(f"bank$b $n: $d x $w = ${d * w / 8}"))
total_memsize = total_memsize + d * w / 8
}
m
})
bpdStr.append(BoomCoreStringPrefix(f"Total bpd size: ${total_memsize / 1024} KB\n"))
override def toString: String = bpdStr.toString
val banked_lhist_providers = Seq.fill(nBanks) { Module(if (localHistoryNSets > 0) new LocalBranchPredictorBank else new NullLocalBranchPredictorBank) }
if (nBanks == 1) {
banked_lhist_providers(0).io.f0_valid := io.f0_req.valid
banked_lhist_providers(0).io.f0_pc := bankAlign(io.f0_req.bits.pc)
banked_predictors(0).io.f0_valid := io.f0_req.valid
banked_predictors(0).io.f0_pc := bankAlign(io.f0_req.bits.pc)
banked_predictors(0).io.f0_mask := fetchMask(io.f0_req.bits.pc)
banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0))
banked_predictors(0).io.f1_lhist := banked_lhist_providers(0).io.f1_lhist
banked_predictors(0).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse)
} else {
require(nBanks == 2)
banked_predictors(0).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse)
banked_predictors(1).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse)
banked_predictors(0).io.f1_lhist := banked_lhist_providers(0).io.f1_lhist
banked_predictors(1).io.f1_lhist := banked_lhist_providers(1).io.f1_lhist
when (bank(io.f0_req.bits.pc) === 0.U) {
banked_lhist_providers(0).io.f0_valid := io.f0_req.valid
banked_lhist_providers(0).io.f0_pc := bankAlign(io.f0_req.bits.pc)
banked_lhist_providers(1).io.f0_valid := io.f0_req.valid
banked_lhist_providers(1).io.f0_pc := nextBank(io.f0_req.bits.pc)
banked_predictors(0).io.f0_valid := io.f0_req.valid
banked_predictors(0).io.f0_pc := bankAlign(io.f0_req.bits.pc)
banked_predictors(0).io.f0_mask := fetchMask(io.f0_req.bits.pc)
banked_predictors(1).io.f0_valid := io.f0_req.valid
banked_predictors(1).io.f0_pc := nextBank(io.f0_req.bits.pc)
banked_predictors(1).io.f0_mask := ~(0.U(bankWidth.W))
} .otherwise {
banked_lhist_providers(0).io.f0_valid := io.f0_req.valid && !mayNotBeDualBanked(io.f0_req.bits.pc)
banked_lhist_providers(0).io.f0_pc := nextBank(io.f0_req.bits.pc)
banked_lhist_providers(1).io.f0_valid := io.f0_req.valid
banked_lhist_providers(1).io.f0_pc := bankAlign(io.f0_req.bits.pc)
banked_predictors(0).io.f0_valid := io.f0_req.valid && !mayNotBeDualBanked(io.f0_req.bits.pc)
banked_predictors(0).io.f0_pc := nextBank(io.f0_req.bits.pc)
banked_predictors(0).io.f0_mask := ~(0.U(bankWidth.W))
banked_predictors(1).io.f0_valid := io.f0_req.valid
banked_predictors(1).io.f0_pc := bankAlign(io.f0_req.bits.pc)
banked_predictors(1).io.f0_mask := fetchMask(io.f0_req.bits.pc)
}
when (RegNext(bank(io.f0_req.bits.pc) === 0.U)) {
banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0))
banked_predictors(1).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(1))
} .otherwise {
banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(1))
banked_predictors(1).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0))
}
}
for (i <- 0 until nBanks) {
banked_lhist_providers(i).io.f3_taken_br := banked_predictors(i).io.resp.f3.map ( p =>
p.is_br && p.predicted_pc.valid && p.taken
).reduce(_||_)
}
if (nBanks == 1) {
io.resp.f1.preds := banked_predictors(0).io.resp.f1
io.resp.f2.preds := banked_predictors(0).io.resp.f2
io.resp.f3.preds := banked_predictors(0).io.resp.f3
io.resp.f3.meta(0) := banked_predictors(0).io.f3_meta
io.resp.f3.lhist(0) := banked_lhist_providers(0).io.f3_lhist
banked_predictors(0).io.f3_fire := io.f3_fire
banked_lhist_providers(0).io.f3_fire := io.f3_fire
} else {
require(nBanks == 2)
val b0_fire = io.f3_fire && RegNext(RegNext(RegNext(banked_predictors(0).io.f0_valid)))
val b1_fire = io.f3_fire && RegNext(RegNext(RegNext(banked_predictors(1).io.f0_valid)))
banked_predictors(0).io.f3_fire := b0_fire
banked_predictors(1).io.f3_fire := b1_fire
banked_lhist_providers(0).io.f3_fire := b0_fire
banked_lhist_providers(1).io.f3_fire := b1_fire
// The branch prediction metadata is stored un-shuffled
io.resp.f3.meta(0) := banked_predictors(0).io.f3_meta
io.resp.f3.meta(1) := banked_predictors(1).io.f3_meta
io.resp.f3.lhist(0) := banked_lhist_providers(0).io.f3_lhist
io.resp.f3.lhist(1) := banked_lhist_providers(1).io.f3_lhist
when (bank(io.resp.f1.pc) === 0.U) {
for (i <- 0 until bankWidth) {
io.resp.f1.preds(i) := banked_predictors(0).io.resp.f1(i)
io.resp.f1.preds(i+bankWidth) := banked_predictors(1).io.resp.f1(i)
}
} .otherwise {
for (i <- 0 until bankWidth) {
io.resp.f1.preds(i) := banked_predictors(1).io.resp.f1(i)
io.resp.f1.preds(i+bankWidth) := banked_predictors(0).io.resp.f1(i)
}
}
when (bank(io.resp.f2.pc) === 0.U) {
for (i <- 0 until bankWidth) {
io.resp.f2.preds(i) := banked_predictors(0).io.resp.f2(i)
io.resp.f2.preds(i+bankWidth) := banked_predictors(1).io.resp.f2(i)
}
} .otherwise {
for (i <- 0 until bankWidth) {
io.resp.f2.preds(i) := banked_predictors(1).io.resp.f2(i)
io.resp.f2.preds(i+bankWidth) := banked_predictors(0).io.resp.f2(i)
}
}
when (bank(io.resp.f3.pc) === 0.U) {
for (i <- 0 until bankWidth) {
io.resp.f3.preds(i) := banked_predictors(0).io.resp.f3(i)
io.resp.f3.preds(i+bankWidth) := banked_predictors(1).io.resp.f3(i)
}
} .otherwise {
for (i <- 0 until bankWidth) {
io.resp.f3.preds(i) := banked_predictors(1).io.resp.f3(i)
io.resp.f3.preds(i+bankWidth) := banked_predictors(0).io.resp.f3(i)
}
}
}
io.resp.f1.pc := RegNext(io.f0_req.bits.pc)
io.resp.f2.pc := RegNext(io.resp.f1.pc)
io.resp.f3.pc := RegNext(io.resp.f2.pc)
// We don't care about meta from the f1 and f2 resps
// Use the meta from the latest resp
io.resp.f1.meta := DontCare
io.resp.f2.meta := DontCare
io.resp.f1.lhist := DontCare
io.resp.f2.lhist := DontCare
for (i <- 0 until nBanks) {
banked_predictors(i).io.update.bits.is_mispredict_update := io.update.bits.is_mispredict_update
banked_predictors(i).io.update.bits.is_repair_update := io.update.bits.is_repair_update
banked_predictors(i).io.update.bits.meta := io.update.bits.meta(i)
banked_predictors(i).io.update.bits.lhist := io.update.bits.lhist(i)
banked_predictors(i).io.update.bits.cfi_idx.bits := io.update.bits.cfi_idx.bits
banked_predictors(i).io.update.bits.cfi_taken := io.update.bits.cfi_taken
banked_predictors(i).io.update.bits.cfi_mispredicted := io.update.bits.cfi_mispredicted
banked_predictors(i).io.update.bits.cfi_is_br := io.update.bits.cfi_is_br
banked_predictors(i).io.update.bits.cfi_is_jal := io.update.bits.cfi_is_jal
banked_predictors(i).io.update.bits.cfi_is_jalr := io.update.bits.cfi_is_jalr
banked_predictors(i).io.update.bits.target := io.update.bits.target
banked_lhist_providers(i).io.update.mispredict := io.update.bits.is_mispredict_update
banked_lhist_providers(i).io.update.repair := io.update.bits.is_repair_update
banked_lhist_providers(i).io.update.lhist := io.update.bits.lhist(i)
}
if (nBanks == 1) {
banked_predictors(0).io.update.valid := io.update.valid
banked_predictors(0).io.update.bits.pc := bankAlign(io.update.bits.pc)
banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask
banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts
banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid
banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(0)
banked_lhist_providers(0).io.update.valid := io.update.valid && io.update.bits.br_mask =/= 0.U
banked_lhist_providers(0).io.update.pc := bankAlign(io.update.bits.pc)
} else {
require(nBanks == 2)
// Split the single update bundle for the fetchpacket into two updates
// 1 for each bank.
when (bank(io.update.bits.pc) === 0.U) {
val b1_update_valid = io.update.valid &&
(!io.update.bits.cfi_idx.valid || io.update.bits.cfi_idx.bits >= bankWidth.U)
banked_lhist_providers(0).io.update.valid := io.update.valid && io.update.bits.br_mask(bankWidth-1,0) =/= 0.U
banked_lhist_providers(1).io.update.valid := b1_update_valid && io.update.bits.br_mask(fetchWidth-1,bankWidth) =/= 0.U
banked_lhist_providers(0).io.update.pc := bankAlign(io.update.bits.pc)
banked_lhist_providers(1).io.update.pc := nextBank(io.update.bits.pc)
banked_predictors(0).io.update.valid := io.update.valid
banked_predictors(1).io.update.valid := b1_update_valid
banked_predictors(0).io.update.bits.pc := bankAlign(io.update.bits.pc)
banked_predictors(1).io.update.bits.pc := nextBank(io.update.bits.pc)
banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask
banked_predictors(1).io.update.bits.br_mask := io.update.bits.br_mask >> bankWidth
banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts
banked_predictors(1).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts >> bankWidth
banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits < bankWidth.U
banked_predictors(1).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits >= bankWidth.U
banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(0)
banked_predictors(1).io.update.bits.ghist := io.update.bits.ghist.histories(1)
} .otherwise {
val b0_update_valid = io.update.valid && !mayNotBeDualBanked(io.update.bits.pc) &&
(!io.update.bits.cfi_idx.valid || io.update.bits.cfi_idx.bits >= bankWidth.U)
banked_lhist_providers(1).io.update.valid := io.update.valid && io.update.bits.br_mask(bankWidth-1,0) =/= 0.U
banked_lhist_providers(0).io.update.valid := b0_update_valid && io.update.bits.br_mask(fetchWidth-1,bankWidth) =/= 0.U
banked_lhist_providers(1).io.update.pc := bankAlign(io.update.bits.pc)
banked_lhist_providers(0).io.update.pc := nextBank(io.update.bits.pc)
banked_predictors(1).io.update.valid := io.update.valid
banked_predictors(0).io.update.valid := b0_update_valid
banked_predictors(1).io.update.bits.pc := bankAlign(io.update.bits.pc)
banked_predictors(0).io.update.bits.pc := nextBank(io.update.bits.pc)
banked_predictors(1).io.update.bits.br_mask := io.update.bits.br_mask
banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask >> bankWidth
banked_predictors(1).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts
banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts >> bankWidth
banked_predictors(1).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits < bankWidth.U
banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits >= bankWidth.U
banked_predictors(1).io.update.bits.ghist := io.update.bits.ghist.histories(0)
banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(1)
}
}
when (io.update.valid) {
when (io.update.bits.cfi_is_br && io.update.bits.cfi_idx.valid) {
assert(io.update.bits.br_mask(io.update.bits.cfi_idx.bits))
}
}
}
class NullBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p) {
val mems = Nil
} | module BranchPredictor(
input clock,
input reset,
input io_f0_req_valid,
input [39:0] io_f0_req_bits_pc,
input [63:0] io_f0_req_bits_ghist_old_history,
output io_resp_f1_preds_0_taken,
output io_resp_f1_preds_0_is_br,
output io_resp_f1_preds_0_is_jal,
output io_resp_f1_preds_0_predicted_pc_valid,
output [39:0] io_resp_f1_preds_0_predicted_pc_bits,
output io_resp_f1_preds_1_taken,
output io_resp_f1_preds_1_is_br,
output io_resp_f1_preds_1_is_jal,
output io_resp_f1_preds_1_predicted_pc_valid,
output [39:0] io_resp_f1_preds_1_predicted_pc_bits,
output io_resp_f1_preds_2_taken,
output io_resp_f1_preds_2_is_br,
output io_resp_f1_preds_2_is_jal,
output io_resp_f1_preds_2_predicted_pc_valid,
output [39:0] io_resp_f1_preds_2_predicted_pc_bits,
output io_resp_f1_preds_3_taken,
output io_resp_f1_preds_3_is_br,
output io_resp_f1_preds_3_is_jal,
output io_resp_f1_preds_3_predicted_pc_valid,
output [39:0] io_resp_f1_preds_3_predicted_pc_bits,
output io_resp_f2_preds_0_taken,
output io_resp_f2_preds_0_is_br,
output io_resp_f2_preds_0_is_jal,
output io_resp_f2_preds_0_predicted_pc_valid,
output [39:0] io_resp_f2_preds_0_predicted_pc_bits,
output io_resp_f2_preds_1_taken,
output io_resp_f2_preds_1_is_br,
output io_resp_f2_preds_1_is_jal,
output io_resp_f2_preds_1_predicted_pc_valid,
output [39:0] io_resp_f2_preds_1_predicted_pc_bits,
output io_resp_f2_preds_2_taken,
output io_resp_f2_preds_2_is_br,
output io_resp_f2_preds_2_is_jal,
output io_resp_f2_preds_2_predicted_pc_valid,
output [39:0] io_resp_f2_preds_2_predicted_pc_bits,
output io_resp_f2_preds_3_taken,
output io_resp_f2_preds_3_is_br,
output io_resp_f2_preds_3_is_jal,
output io_resp_f2_preds_3_predicted_pc_valid,
output [39:0] io_resp_f2_preds_3_predicted_pc_bits,
output [39:0] io_resp_f3_pc,
output io_resp_f3_preds_0_taken,
output io_resp_f3_preds_0_is_br,
output io_resp_f3_preds_0_is_jal,
output io_resp_f3_preds_0_predicted_pc_valid,
output [39:0] io_resp_f3_preds_0_predicted_pc_bits,
output io_resp_f3_preds_1_taken,
output io_resp_f3_preds_1_is_br,
output io_resp_f3_preds_1_is_jal,
output io_resp_f3_preds_1_predicted_pc_valid,
output [39:0] io_resp_f3_preds_1_predicted_pc_bits,
output io_resp_f3_preds_2_taken,
output io_resp_f3_preds_2_is_br,
output io_resp_f3_preds_2_is_jal,
output io_resp_f3_preds_2_predicted_pc_valid,
output [39:0] io_resp_f3_preds_2_predicted_pc_bits,
output io_resp_f3_preds_3_taken,
output io_resp_f3_preds_3_is_br,
output io_resp_f3_preds_3_is_jal,
output io_resp_f3_preds_3_predicted_pc_valid,
output [39:0] io_resp_f3_preds_3_predicted_pc_bits,
output [119:0] io_resp_f3_meta_0,
input io_f3_fire,
input io_update_valid,
input io_update_bits_is_mispredict_update,
input io_update_bits_is_repair_update,
input [3:0] io_update_bits_btb_mispredicts,
input [39:0] io_update_bits_pc,
input [3:0] io_update_bits_br_mask,
input io_update_bits_cfi_idx_valid,
input [1:0] io_update_bits_cfi_idx_bits,
input io_update_bits_cfi_taken,
input io_update_bits_cfi_mispredicted,
input io_update_bits_cfi_is_br,
input io_update_bits_cfi_is_jal,
input [63:0] io_update_bits_ghist_old_history,
input [39:0] io_update_bits_target,
input [119:0] io_update_bits_meta_0
);
wire [6:0] _banked_predictors_0_io_f0_mask_T = 7'hF << io_f0_req_bits_pc[2:1];
reg [63:0] banked_predictors_0_io_f1_ghist_REG;
reg [39:0] io_resp_f1_pc_REG;
reg [39:0] io_resp_f2_pc_REG;
reg [39:0] io_resp_f3_pc_REG;
always @(posedge clock) begin
banked_predictors_0_io_f1_ghist_REG <= io_f0_req_bits_ghist_old_history;
io_resp_f1_pc_REG <= io_f0_req_bits_pc;
io_resp_f2_pc_REG <= io_resp_f1_pc_REG;
io_resp_f3_pc_REG <= io_resp_f2_pc_REG;
end
ComposedBranchPredictorBank banked_predictors_0 (
.clock (clock),
.reset (reset),
.io_f0_valid (io_f0_req_valid),
.io_f0_pc ({io_f0_req_bits_pc[39:3], 3'h0}),
.io_f0_mask (_banked_predictors_0_io_f0_mask_T[3:0]),
.io_f1_ghist (banked_predictors_0_io_f1_ghist_REG),
.io_resp_f1_0_taken (io_resp_f1_preds_0_taken),
.io_resp_f1_0_is_br (io_resp_f1_preds_0_is_br),
.io_resp_f1_0_is_jal (io_resp_f1_preds_0_is_jal),
.io_resp_f1_0_predicted_pc_valid (io_resp_f1_preds_0_predicted_pc_valid),
.io_resp_f1_0_predicted_pc_bits (io_resp_f1_preds_0_predicted_pc_bits),
.io_resp_f1_1_taken (io_resp_f1_preds_1_taken),
.io_resp_f1_1_is_br (io_resp_f1_preds_1_is_br),
.io_resp_f1_1_is_jal (io_resp_f1_preds_1_is_jal),
.io_resp_f1_1_predicted_pc_valid (io_resp_f1_preds_1_predicted_pc_valid),
.io_resp_f1_1_predicted_pc_bits (io_resp_f1_preds_1_predicted_pc_bits),
.io_resp_f1_2_taken (io_resp_f1_preds_2_taken),
.io_resp_f1_2_is_br (io_resp_f1_preds_2_is_br),
.io_resp_f1_2_is_jal (io_resp_f1_preds_2_is_jal),
.io_resp_f1_2_predicted_pc_valid (io_resp_f1_preds_2_predicted_pc_valid),
.io_resp_f1_2_predicted_pc_bits (io_resp_f1_preds_2_predicted_pc_bits),
.io_resp_f1_3_taken (io_resp_f1_preds_3_taken),
.io_resp_f1_3_is_br (io_resp_f1_preds_3_is_br),
.io_resp_f1_3_is_jal (io_resp_f1_preds_3_is_jal),
.io_resp_f1_3_predicted_pc_valid (io_resp_f1_preds_3_predicted_pc_valid),
.io_resp_f1_3_predicted_pc_bits (io_resp_f1_preds_3_predicted_pc_bits),
.io_resp_f2_0_taken (io_resp_f2_preds_0_taken),
.io_resp_f2_0_is_br (io_resp_f2_preds_0_is_br),
.io_resp_f2_0_is_jal (io_resp_f2_preds_0_is_jal),
.io_resp_f2_0_predicted_pc_valid (io_resp_f2_preds_0_predicted_pc_valid),
.io_resp_f2_0_predicted_pc_bits (io_resp_f2_preds_0_predicted_pc_bits),
.io_resp_f2_1_taken (io_resp_f2_preds_1_taken),
.io_resp_f2_1_is_br (io_resp_f2_preds_1_is_br),
.io_resp_f2_1_is_jal (io_resp_f2_preds_1_is_jal),
.io_resp_f2_1_predicted_pc_valid (io_resp_f2_preds_1_predicted_pc_valid),
.io_resp_f2_1_predicted_pc_bits (io_resp_f2_preds_1_predicted_pc_bits),
.io_resp_f2_2_taken (io_resp_f2_preds_2_taken),
.io_resp_f2_2_is_br (io_resp_f2_preds_2_is_br),
.io_resp_f2_2_is_jal (io_resp_f2_preds_2_is_jal),
.io_resp_f2_2_predicted_pc_valid (io_resp_f2_preds_2_predicted_pc_valid),
.io_resp_f2_2_predicted_pc_bits (io_resp_f2_preds_2_predicted_pc_bits),
.io_resp_f2_3_taken (io_resp_f2_preds_3_taken),
.io_resp_f2_3_is_br (io_resp_f2_preds_3_is_br),
.io_resp_f2_3_is_jal (io_resp_f2_preds_3_is_jal),
.io_resp_f2_3_predicted_pc_valid (io_resp_f2_preds_3_predicted_pc_valid),
.io_resp_f2_3_predicted_pc_bits (io_resp_f2_preds_3_predicted_pc_bits),
.io_resp_f3_0_taken (io_resp_f3_preds_0_taken),
.io_resp_f3_0_is_br (io_resp_f3_preds_0_is_br),
.io_resp_f3_0_is_jal (io_resp_f3_preds_0_is_jal),
.io_resp_f3_0_predicted_pc_valid (io_resp_f3_preds_0_predicted_pc_valid),
.io_resp_f3_0_predicted_pc_bits (io_resp_f3_preds_0_predicted_pc_bits),
.io_resp_f3_1_taken (io_resp_f3_preds_1_taken),
.io_resp_f3_1_is_br (io_resp_f3_preds_1_is_br),
.io_resp_f3_1_is_jal (io_resp_f3_preds_1_is_jal),
.io_resp_f3_1_predicted_pc_valid (io_resp_f3_preds_1_predicted_pc_valid),
.io_resp_f3_1_predicted_pc_bits (io_resp_f3_preds_1_predicted_pc_bits),
.io_resp_f3_2_taken (io_resp_f3_preds_2_taken),
.io_resp_f3_2_is_br (io_resp_f3_preds_2_is_br),
.io_resp_f3_2_is_jal (io_resp_f3_preds_2_is_jal),
.io_resp_f3_2_predicted_pc_valid (io_resp_f3_preds_2_predicted_pc_valid),
.io_resp_f3_2_predicted_pc_bits (io_resp_f3_preds_2_predicted_pc_bits),
.io_resp_f3_3_taken (io_resp_f3_preds_3_taken),
.io_resp_f3_3_is_br (io_resp_f3_preds_3_is_br),
.io_resp_f3_3_is_jal (io_resp_f3_preds_3_is_jal),
.io_resp_f3_3_predicted_pc_valid (io_resp_f3_preds_3_predicted_pc_valid),
.io_resp_f3_3_predicted_pc_bits (io_resp_f3_preds_3_predicted_pc_bits),
.io_f3_meta (io_resp_f3_meta_0),
.io_f3_fire (io_f3_fire),
.io_update_valid (io_update_valid),
.io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update),
.io_update_bits_is_repair_update (io_update_bits_is_repair_update),
.io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts),
.io_update_bits_pc ({io_update_bits_pc[39:3], 3'h0}),
.io_update_bits_br_mask (io_update_bits_br_mask),
.io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid),
.io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits),
.io_update_bits_cfi_taken (io_update_bits_cfi_taken),
.io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted),
.io_update_bits_cfi_is_br (io_update_bits_cfi_is_br),
.io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal),
.io_update_bits_ghist (io_update_bits_ghist_old_history),
.io_update_bits_target (io_update_bits_target),
.io_update_bits_meta (io_update_bits_meta_0)
);
assign io_resp_f3_pc = io_resp_f3_pc_REG;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
} | module ClockCrossingReg_w55(
input clock,
input [54:0] io_d,
output [54:0] io_q,
input io_en
);
reg [54:0] cdc_reg;
always @(posedge clock) begin
if (io_en)
cdc_reg <= io_d;
end
assign io_q = cdc_reg;
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
} | module lo_us_2(
input [7:0] R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input [7:0] W0_addr,
input W0_clk,
input [3:0] W0_data,
input [3:0] W0_mask
);
hi_us_0_ext hi_us_0_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (1'h1),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
class Atomics(params: TLBundleParameters) extends Module
{
val io = IO(new Bundle {
val write = Flipped(Bool()) // ignore opcode
val a = Flipped(new TLBundleA(params))
val data_in = Flipped(UInt(params.dataBits.W))
val data_out = UInt(params.dataBits.W)
})
// Arithmetic, what to do
val adder = io.a.param(2)
val unsigned = io.a.param(1)
val take_max = io.a.param(0)
val signBit = io.a.mask & Cat(1.U, ~io.a.mask >> 1)
val inv_d = Mux(adder, io.data_in, ~io.data_in)
val sum = (FillInterleaved(8, io.a.mask) & io.a.data) + inv_d
def sign(x: UInt): Bool = (Cat(x.asBools.grouped(8).map(_.last).toList.reverse) & signBit).orR
val sign_a = sign(io.a.data)
val sign_d = sign(io.data_in)
val sign_s = sign(sum)
val a_bigger_uneq = unsigned === sign_a // result if high bits are unequal
val a_bigger = Mux(sign_a === sign_d, !sign_s, a_bigger_uneq)
val pick_a = take_max === a_bigger
// Logical, what to do
val lut = VecInit(Seq(
(0x6).U, // XOR
(0xe).U, // OR
(0x8).U, // AND
(0xc).U))( // SWAP
io.a.param(1,0))
val logical = Cat((io.a.data.asBools zip io.data_in.asBools).map { case (a, d) =>
lut(Cat(a, d))
}.reverse)
// Operation, what to do? (0=d, 1=a, 2=sum, 3=logical)
val select = Mux(io.write, 1.U, VecInit(Seq(
1.U, // PutFullData
1.U, // PutPartialData
Mux(adder, 2.U, Mux(pick_a, 1.U, 0.U)), // ArithmeticData
3.U, // LogicalData
0.U, // Get
0.U, // Hint
0.U, // AcquireBlock
0.U))( // AcquirePerm
io.a.opcode))
// Only the masked bytes can be modified
val selects = io.a.mask.asBools.map(b => Mux(b, select, 0.U))
io.data_out := Cat(selects.zipWithIndex.map { case (s, i) =>
VecInit(Seq(io.data_in, io.a.data, sum, logical).map(_((i + 1) * 8 - 1, i * 8)))(s)
}.reverse)
} | module Atomics(
input io_write,
input [2:0] io_a_opcode,
input [2:0] io_a_param,
input [3:0] io_a_mask,
input [31:0] io_a_data,
input [31:0] io_data_in,
output [31:0] io_data_out
);
wire [3:0][3:0] _GEN = '{4'hC, 4'h8, 4'hE, 4'h6};
wire [3:0] signBit = io_a_mask & {1'h1, ~(io_a_mask[3:1])};
wire [31:0] _sum_T_10 = ({{8{io_a_mask[3]}}, {8{io_a_mask[2]}}, {8{io_a_mask[1]}}, {8{io_a_mask[0]}}} & io_a_data) + ({32{~(io_a_param[2])}} ^ io_data_in);
wire [3:0] _sign_a_T_33 = {io_a_data[31], io_a_data[23], io_a_data[15], io_a_data[7]} & signBit;
wire [3:0] _GEN_0 = _GEN[io_a_param[1:0]];
wire [3:0] _logical_T_65 = _GEN_0 >> {2'h0, io_a_data[0], io_data_in[0]};
wire [3:0] _logical_T_68 = _GEN_0 >> {2'h0, io_a_data[1], io_data_in[1]};
wire [3:0] _logical_T_71 = _GEN_0 >> {2'h0, io_a_data[2], io_data_in[2]};
wire [3:0] _logical_T_74 = _GEN_0 >> {2'h0, io_a_data[3], io_data_in[3]};
wire [3:0] _logical_T_77 = _GEN_0 >> {2'h0, io_a_data[4], io_data_in[4]};
wire [3:0] _logical_T_80 = _GEN_0 >> {2'h0, io_a_data[5], io_data_in[5]};
wire [3:0] _logical_T_83 = _GEN_0 >> {2'h0, io_a_data[6], io_data_in[6]};
wire [3:0] _logical_T_86 = _GEN_0 >> {2'h0, io_a_data[7], io_data_in[7]};
wire [3:0] _logical_T_89 = _GEN_0 >> {2'h0, io_a_data[8], io_data_in[8]};
wire [3:0] _logical_T_92 = _GEN_0 >> {2'h0, io_a_data[9], io_data_in[9]};
wire [3:0] _logical_T_95 = _GEN_0 >> {2'h0, io_a_data[10], io_data_in[10]};
wire [3:0] _logical_T_98 = _GEN_0 >> {2'h0, io_a_data[11], io_data_in[11]};
wire [3:0] _logical_T_101 = _GEN_0 >> {2'h0, io_a_data[12], io_data_in[12]};
wire [3:0] _logical_T_104 = _GEN_0 >> {2'h0, io_a_data[13], io_data_in[13]};
wire [3:0] _logical_T_107 = _GEN_0 >> {2'h0, io_a_data[14], io_data_in[14]};
wire [3:0] _logical_T_110 = _GEN_0 >> {2'h0, io_a_data[15], io_data_in[15]};
wire [3:0] _logical_T_113 = _GEN_0 >> {2'h0, io_a_data[16], io_data_in[16]};
wire [3:0] _logical_T_116 = _GEN_0 >> {2'h0, io_a_data[17], io_data_in[17]};
wire [3:0] _logical_T_119 = _GEN_0 >> {2'h0, io_a_data[18], io_data_in[18]};
wire [3:0] _logical_T_122 = _GEN_0 >> {2'h0, io_a_data[19], io_data_in[19]};
wire [3:0] _logical_T_125 = _GEN_0 >> {2'h0, io_a_data[20], io_data_in[20]};
wire [3:0] _logical_T_128 = _GEN_0 >> {2'h0, io_a_data[21], io_data_in[21]};
wire [3:0] _logical_T_131 = _GEN_0 >> {2'h0, io_a_data[22], io_data_in[22]};
wire [3:0] _logical_T_134 = _GEN_0 >> {2'h0, io_a_data[23], io_data_in[23]};
wire [3:0] _logical_T_137 = _GEN_0 >> {2'h0, io_a_data[24], io_data_in[24]};
wire [3:0] _logical_T_140 = _GEN_0 >> {2'h0, io_a_data[25], io_data_in[25]};
wire [3:0] _logical_T_143 = _GEN_0 >> {2'h0, io_a_data[26], io_data_in[26]};
wire [3:0] _logical_T_146 = _GEN_0 >> {2'h0, io_a_data[27], io_data_in[27]};
wire [3:0] _logical_T_149 = _GEN_0 >> {2'h0, io_a_data[28], io_data_in[28]};
wire [3:0] _logical_T_152 = _GEN_0 >> {2'h0, io_a_data[29], io_data_in[29]};
wire [3:0] _logical_T_155 = _GEN_0 >> {2'h0, io_a_data[30], io_data_in[30]};
wire [3:0] _logical_T_158 = _GEN_0 >> {2'h0, io_a_data[31], io_data_in[31]};
wire [7:0][1:0] _GEN_1 = {{2'h0}, {2'h0}, {2'h0}, {2'h0}, {2'h3}, {io_a_param[2] ? 2'h2 : {1'h0, io_a_param[0] == ((|_sign_a_T_33) == (|({io_data_in[31], io_data_in[23], io_data_in[15], io_data_in[7]} & signBit)) ? ({_sum_T_10[31], _sum_T_10[23], _sum_T_10[15], _sum_T_10[7]} & signBit) == 4'h0 : io_a_param[1] == (|_sign_a_T_33))}}, {2'h1}, {2'h1}};
wire [1:0] select = io_write ? 2'h1 : _GEN_1[io_a_opcode];
wire [3:0][7:0] _GEN_2 = {{{_logical_T_110[0], _logical_T_107[0], _logical_T_104[0], _logical_T_101[0], _logical_T_98[0], _logical_T_95[0], _logical_T_92[0], _logical_T_89[0]}}, {_sum_T_10[15:8]}, {io_a_data[15:8]}, {io_data_in[15:8]}};
wire [3:0][7:0] _GEN_3 = {{{_logical_T_86[0], _logical_T_83[0], _logical_T_80[0], _logical_T_77[0], _logical_T_74[0], _logical_T_71[0], _logical_T_68[0], _logical_T_65[0]}}, {_sum_T_10[7:0]}, {io_a_data[7:0]}, {io_data_in[7:0]}};
wire [3:0][7:0] _GEN_4 = {{{_logical_T_158[0], _logical_T_155[0], _logical_T_152[0], _logical_T_149[0], _logical_T_146[0], _logical_T_143[0], _logical_T_140[0], _logical_T_137[0]}}, {_sum_T_10[31:24]}, {io_a_data[31:24]}, {io_data_in[31:24]}};
wire [3:0][7:0] _GEN_5 = {{{_logical_T_134[0], _logical_T_131[0], _logical_T_128[0], _logical_T_125[0], _logical_T_122[0], _logical_T_119[0], _logical_T_116[0], _logical_T_113[0]}}, {_sum_T_10[23:16]}, {io_a_data[23:16]}, {io_data_in[23:16]}};
assign io_data_out = {_GEN_4[io_a_mask[3] ? select : 2'h0], _GEN_5[io_a_mask[2] ? select : 2'h0], _GEN_2[io_a_mask[1] ? select : 2'h0], _GEN_3[io_a_mask[0] ? select : 2'h0]};
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
trait TLFieldHelper {
def getBodyFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleC => Seq( b.data, b.corrupt)
case b: TLBundleD => Seq( b.data, b.corrupt)
case b: TLBundleE => Seq()
}
def getConstFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )
case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)
case b: TLBundleE => Seq( b.sink )
}
def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max
def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max
def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))
}
class TLBeat(val beatWidth: Int) extends Bundle {
val payload = UInt(beatWidth.W)
val head = Bool()
val tail = Bool()
}
abstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Flipped(Decoupled(gen))
val beat = Decoupled(new TLBeat(beatWidth))
})
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
// convert decoupled to irrevocable
val q = Module(new Queue(gen, 1, pipe=true, flow=true))
q.io.enq <> io.protocol
val protocol = q.io.deq
val has_body = Wire(Bool())
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val head = edge.first(protocol.bits, protocol.fire)
val tail = edge.last(protocol.bits, protocol.fire)
val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))
val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))
val is_body = RegInit(false.B)
io.beat.valid := protocol.valid
protocol.ready := io.beat.ready && (is_body || !has_body)
io.beat.bits.head := head && !is_body
io.beat.bits.tail := tail && (is_body || !has_body)
io.beat.bits.payload := Mux(is_body, body, const)
when (io.beat.fire && io.beat.bits.head) { is_body := true.B }
when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }
}
abstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Decoupled(gen)
val beat = Flipped(Decoupled(new TLBeat(beatWidth)))
})
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
val protocol = Wire(Decoupled(gen))
io.protocol <> protocol
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val is_const = RegInit(true.B)
val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))
val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)
io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready
protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid
def assign(i: UInt, sigs: Seq[Data]) = {
var t = i
for (s <- sigs.reverse) {
s := t.asTypeOf(s.cloneType)
t = t >> s.getWidth
}
}
assign(const, const_fields)
assign(io.beat.bits.payload, body_fields)
when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }
when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }
}
class TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)
class TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits)
}
class TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)
class TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p) | module TLEFromBeat_SerialRAM_a64d64s8k8z8c(
input clock,
input reset,
output io_beat_ready,
input io_beat_valid,
input io_beat_bits_head,
input io_beat_bits_tail
);
reg is_const;
wire io_beat_ready_0 = is_const & ~io_beat_bits_tail;
wire _GEN = io_beat_ready_0 & io_beat_valid;
always @(posedge clock) begin
if (reset)
is_const <= 1'h1;
else
is_const <= _GEN & io_beat_bits_tail | ~(_GEN & io_beat_bits_head) & is_const;
end
assign io_beat_ready = io_beat_ready_0;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
class DivSqrtRecF64 extends Module
{
val io = IO(new Bundle {
val inReady_div = Output(Bool())
val inReady_sqrt = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(Bits(65.W))
val b = Input(Bits(65.W))
val roundingMode = Input(Bits(3.W))
val detectTininess = Input(UInt(1.W))
val outValid_div = Output(Bool())
val outValid_sqrt = Output(Bool())
val out = Output(Bits(65.W))
val exceptionFlags = Output(Bits(5.W))
})
val ds = Module(new DivSqrtRecF64_mulAddZ31(0))
io.inReady_div := ds.io.inReady_div
io.inReady_sqrt := ds.io.inReady_sqrt
ds.io.inValid := io.inValid
ds.io.sqrtOp := io.sqrtOp
ds.io.a := io.a
ds.io.b := io.b
ds.io.roundingMode := io.roundingMode
ds.io.detectTininess := io.detectTininess
io.outValid_div := ds.io.outValid_div
io.outValid_sqrt := ds.io.outValid_sqrt
io.out := ds.io.out
io.exceptionFlags := ds.io.exceptionFlags
val mul = Module(new Mul54)
mul.io.val_s0 := ds.io.usingMulAdd(0)
mul.io.latch_a_s0 := ds.io.latchMulAddA_0
mul.io.a_s0 := ds.io.mulAddA_0
mul.io.latch_b_s0 := ds.io.latchMulAddB_0
mul.io.b_s0 := ds.io.mulAddB_0
mul.io.c_s2 := ds.io.mulAddC_2
ds.io.mulAddResult_3 := mul.io.result_s3
}
class Mul54 extends Module
{
val io = IO(new Bundle {
val val_s0 = Input(Bool())
val latch_a_s0 = Input(Bool())
val a_s0 = Input(UInt(54.W))
val latch_b_s0 = Input(Bool())
val b_s0 = Input(UInt(54.W))
val c_s2 = Input(UInt(105.W))
val result_s3 = Output(UInt(105.W))
})
val val_s1 = Reg(Bool())
val val_s2 = Reg(Bool())
val reg_a_s1 = Reg(UInt(54.W))
val reg_b_s1 = Reg(UInt(54.W))
val reg_a_s2 = Reg(UInt(54.W))
val reg_b_s2 = Reg(UInt(54.W))
val reg_result_s3 = Reg(UInt(105.W))
val_s1 := io.val_s0
val_s2 := val_s1
when (io.val_s0) {
when (io.latch_a_s0) {
reg_a_s1 := io.a_s0
}
when (io.latch_b_s0) {
reg_b_s1 := io.b_s0
}
}
when (val_s1) {
reg_a_s2 := reg_a_s1
reg_b_s2 := reg_b_s1
}
when (val_s2) {
reg_result_s3 := (reg_a_s2 * reg_b_s2)(104,0) + io.c_s2
}
io.result_s3 := reg_result_s3
} | module DivSqrtRecF64(
input clock,
input reset,
output io_inReady_div,
output io_inReady_sqrt,
input io_inValid,
input io_sqrtOp,
input [64:0] io_a,
input [64:0] io_b,
input [2:0] io_roundingMode,
output io_outValid_div,
output io_outValid_sqrt,
output [64:0] io_out,
output [4:0] io_exceptionFlags
);
wire [104:0] _mul_io_result_s3;
wire [3:0] _ds_io_usingMulAdd;
wire _ds_io_latchMulAddA_0;
wire [53:0] _ds_io_mulAddA_0;
wire _ds_io_latchMulAddB_0;
wire [53:0] _ds_io_mulAddB_0;
wire [104:0] _ds_io_mulAddC_2;
DivSqrtRecF64_mulAddZ31 ds (
.clock (clock),
.reset (reset),
.io_inReady_div (io_inReady_div),
.io_inReady_sqrt (io_inReady_sqrt),
.io_inValid (io_inValid),
.io_sqrtOp (io_sqrtOp),
.io_a (io_a),
.io_b (io_b),
.io_roundingMode (io_roundingMode),
.io_usingMulAdd (_ds_io_usingMulAdd),
.io_latchMulAddA_0 (_ds_io_latchMulAddA_0),
.io_mulAddA_0 (_ds_io_mulAddA_0),
.io_latchMulAddB_0 (_ds_io_latchMulAddB_0),
.io_mulAddB_0 (_ds_io_mulAddB_0),
.io_mulAddC_2 (_ds_io_mulAddC_2),
.io_mulAddResult_3 (_mul_io_result_s3),
.io_outValid_div (io_outValid_div),
.io_outValid_sqrt (io_outValid_sqrt),
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
);
Mul54 mul (
.clock (clock),
.io_val_s0 (_ds_io_usingMulAdd[0]),
.io_latch_a_s0 (_ds_io_latchMulAddA_0),
.io_a_s0 (_ds_io_mulAddA_0),
.io_latch_b_s0 (_ds_io_latchMulAddB_0),
.io_b_s0 (_ds_io_mulAddB_0),
.io_c_s2 (_ds_io_mulAddC_2),
.io_result_s3 (_mul_io_result_s3)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)
{
val queueBits = log2Up(queues)
val entryBits = log2Up(entries)
}
class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle
{
val index = UInt(params.queueBits.W)
val data = Output(params.gen)
}
class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module
{
override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}"
val io = IO(new Bundle {
// push is visible on the same cycle; flow queues
val push = Flipped(Decoupled(new ListBufferPush(params)))
val valid = UInt(params.queues.W)
val pop = Flipped(Valid(UInt(params.queueBits.W)))
val data = Output(params.gen)
})
val valid = RegInit(0.U(params.queues.W))
val head = Mem(params.queues, UInt(params.entryBits.W))
val tail = Mem(params.queues, UInt(params.entryBits.W))
val used = RegInit(0.U(params.entries.W))
val next = Mem(params.entries, UInt(params.entryBits.W))
val data = Mem(params.entries, params.gen)
val freeOH = ~(leftOR(~used) << 1) & ~used
val freeIdx = OHToUInt(freeOH)
val valid_set = WireDefault(0.U(params.queues.W))
val valid_clr = WireDefault(0.U(params.queues.W))
val used_set = WireDefault(0.U(params.entries.W))
val used_clr = WireDefault(0.U(params.entries.W))
val push_tail = tail.read(io.push.bits.index)
val push_valid = valid(io.push.bits.index)
io.push.ready := !used.andR
when (io.push.fire) {
valid_set := UIntToOH(io.push.bits.index, params.queues)
used_set := freeOH
data.write(freeIdx, io.push.bits.data)
when (push_valid) {
next.write(push_tail, freeIdx)
} .otherwise {
head.write(io.push.bits.index, freeIdx)
}
tail.write(io.push.bits.index, freeIdx)
}
val pop_head = head.read(io.pop.bits)
val pop_valid = valid(io.pop.bits)
// Bypass push data to the peek port
io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))
io.valid := (if (!params.bypass) valid else (valid | valid_set))
// It is an error to pop something that is not valid
assert (!io.pop.fire || (io.valid)(io.pop.bits))
when (io.pop.fire) {
used_clr := UIntToOH(pop_head, params.entries)
when (pop_head === tail.read(io.pop.bits)) {
valid_clr := UIntToOH(io.pop.bits, params.queues)
}
head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))
}
// Empty bypass changes no state
when ((!params.bypass).B || !io.pop.valid || pop_valid) {
used := (used & ~used_clr) | used_set
valid := (valid & ~valid_clr) | valid_set
}
} | module data_35x43(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [42:0] R0_data,
input [5:0] W0_addr,
input W0_en,
input W0_clk,
input [42:0] W0_data
);
reg [42:0] Memory[0:34];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 43'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)
{
val queueBits = log2Up(queues)
val entryBits = log2Up(entries)
}
class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle
{
val index = UInt(params.queueBits.W)
val data = Output(params.gen)
}
class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module
{
override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}"
val io = IO(new Bundle {
// push is visible on the same cycle; flow queues
val push = Flipped(Decoupled(new ListBufferPush(params)))
val valid = UInt(params.queues.W)
val pop = Flipped(Valid(UInt(params.queueBits.W)))
val data = Output(params.gen)
})
val valid = RegInit(0.U(params.queues.W))
val head = Mem(params.queues, UInt(params.entryBits.W))
val tail = Mem(params.queues, UInt(params.entryBits.W))
val used = RegInit(0.U(params.entries.W))
val next = Mem(params.entries, UInt(params.entryBits.W))
val data = Mem(params.entries, params.gen)
val freeOH = ~(leftOR(~used) << 1) & ~used
val freeIdx = OHToUInt(freeOH)
val valid_set = WireDefault(0.U(params.queues.W))
val valid_clr = WireDefault(0.U(params.queues.W))
val used_set = WireDefault(0.U(params.entries.W))
val used_clr = WireDefault(0.U(params.entries.W))
val push_tail = tail.read(io.push.bits.index)
val push_valid = valid(io.push.bits.index)
io.push.ready := !used.andR
when (io.push.fire) {
valid_set := UIntToOH(io.push.bits.index, params.queues)
used_set := freeOH
data.write(freeIdx, io.push.bits.data)
when (push_valid) {
next.write(push_tail, freeIdx)
} .otherwise {
head.write(io.push.bits.index, freeIdx)
}
tail.write(io.push.bits.index, freeIdx)
}
val pop_head = head.read(io.pop.bits)
val pop_valid = valid(io.pop.bits)
// Bypass push data to the peek port
io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))
io.valid := (if (!params.bypass) valid else (valid | valid_set))
// It is an error to pop something that is not valid
assert (!io.pop.fire || (io.valid)(io.pop.bits))
when (io.pop.fire) {
used_clr := UIntToOH(pop_head, params.entries)
when (pop_head === tail.read(io.pop.bits)) {
valid_clr := UIntToOH(io.pop.bits, params.queues)
}
head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))
}
// Empty bypass changes no state
when ((!params.bypass).B || !io.pop.valid || pop_valid) {
used := (used & ~used_clr) | used_set
valid := (valid & ~valid_clr) | valid_set
}
} | module data_33x44(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [43:0] R0_data,
input [5:0] W0_addr,
input W0_en,
input W0_clk,
input [43:0] W0_data
);
reg [43:0] Memory[0:32];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 44'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix}
import scala.math.min
case class BoomBTBParams(
nSets: Int = 128,
nWays: Int = 2,
offsetSz: Int = 13,
extendedNSets: Int = 128
)
class BTBBranchPredictorBank(params: BoomBTBParams = BoomBTBParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
override val nSets = params.nSets
override val nWays = params.nWays
val tagSz = vaddrBitsExtended - log2Ceil(nSets) - log2Ceil(fetchWidth) - 1
val offsetSz = params.offsetSz
val extendedNSets = params.extendedNSets
require(isPow2(nSets))
require(isPow2(extendedNSets) || extendedNSets == 0)
require(extendedNSets <= nSets)
require(extendedNSets >= 1)
class BTBEntry extends Bundle {
val offset = SInt(offsetSz.W)
val extended = Bool()
}
val btbEntrySz = offsetSz + 1
class BTBMeta extends Bundle {
val is_br = Bool()
val tag = UInt(tagSz.W)
}
val btbMetaSz = tagSz + 1
class BTBPredictMeta extends Bundle {
val write_way = UInt(log2Ceil(nWays).W)
}
val s1_meta = Wire(new BTBPredictMeta)
val f3_meta = RegNext(RegNext(s1_meta))
io.f3_meta := f3_meta.asUInt
override val metaSz = s1_meta.asUInt.getWidth
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nSets).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nSets-1).U) { doing_reset := false.B }
val meta = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbMetaSz.W))) }
val btb = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbEntrySz.W))) }
val ebtb = SyncReadMem(extendedNSets, UInt(vaddrBitsExtended.W))
val mems = (((0 until nWays) map ({w:Int => Seq(
(f"btb_meta_way$w", nSets, bankWidth * btbMetaSz),
(f"btb_data_way$w", nSets, bankWidth * btbEntrySz))})).flatten ++ Seq(("ebtb", extendedNSets, vaddrBitsExtended)))
val s1_req_rbtb = VecInit(btb.map { b => VecInit(b.read(s0_idx , s0_valid).map(_.asTypeOf(new BTBEntry))) })
val s1_req_rmeta = VecInit(meta.map { m => VecInit(m.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBMeta))) })
val s1_req_rebtb = ebtb.read(s0_idx, s0_valid)
val s1_req_tag = s1_idx >> log2Ceil(nSets)
val s1_resp = Wire(Vec(bankWidth, Valid(UInt(vaddrBitsExtended.W))))
val s1_is_br = Wire(Vec(bankWidth, Bool()))
val s1_is_jal = Wire(Vec(bankWidth, Bool()))
val s1_hit_ohs = VecInit((0 until bankWidth) map { i =>
VecInit((0 until nWays) map { w =>
s1_req_rmeta(w)(i).tag === s1_req_tag(tagSz-1,0)
})
})
val s1_hits = s1_hit_ohs.map { oh => oh.reduce(_||_) }
val s1_hit_ways = s1_hit_ohs.map { oh => PriorityEncoder(oh) }
for (w <- 0 until bankWidth) {
val entry_meta = s1_req_rmeta(s1_hit_ways(w))(w)
val entry_btb = s1_req_rbtb(s1_hit_ways(w))(w)
s1_resp(w).valid := !doing_reset && s1_valid && s1_hits(w)
s1_resp(w).bits := Mux(
entry_btb.extended,
s1_req_rebtb,
(s1_pc.asSInt + (w << 1).S + entry_btb.offset).asUInt)
s1_is_br(w) := !doing_reset && s1_resp(w).valid && entry_meta.is_br
s1_is_jal(w) := !doing_reset && s1_resp(w).valid && !entry_meta.is_br
io.resp.f2(w) := io.resp_in(0).f2(w)
io.resp.f3(w) := io.resp_in(0).f3(w)
when (RegNext(s1_hits(w))) {
io.resp.f2(w).predicted_pc := RegNext(s1_resp(w))
io.resp.f2(w).is_br := RegNext(s1_is_br(w))
io.resp.f2(w).is_jal := RegNext(s1_is_jal(w))
when (RegNext(s1_is_jal(w))) {
io.resp.f2(w).taken := true.B
}
}
when (RegNext(RegNext(s1_hits(w)))) {
io.resp.f3(w).predicted_pc := RegNext(io.resp.f2(w).predicted_pc)
io.resp.f3(w).is_br := RegNext(io.resp.f2(w).is_br)
io.resp.f3(w).is_jal := RegNext(io.resp.f2(w).is_jal)
when (RegNext(RegNext(s1_is_jal(w)))) {
io.resp.f3(w).taken := true.B
}
}
}
val alloc_way = if (nWays > 1) {
val r_metas = Cat(VecInit(s1_req_rmeta.map { w => VecInit(w.map(_.tag)) }).asUInt, s1_req_tag(tagSz-1,0))
val l = log2Ceil(nWays)
val nChunks = (r_metas.getWidth + l - 1) / l
val chunks = (0 until nChunks) map { i =>
r_metas(min((i+1)*l, r_metas.getWidth)-1, i*l)
}
chunks.reduce(_^_)
} else {
0.U
}
s1_meta.write_way := Mux(s1_hits.reduce(_||_),
PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_|_)),
alloc_way)
val s1_update_cfi_idx = s1_update.bits.cfi_idx.bits
val s1_update_meta = s1_update.bits.meta.asTypeOf(new BTBPredictMeta)
val max_offset_value = Cat(0.B, ~(0.U((offsetSz-1).W))).asSInt
val min_offset_value = Cat(1.B, (0.U((offsetSz-1).W))).asSInt
val new_offset_value = (s1_update.bits.target.asSInt -
(s1_update.bits.pc + (s1_update.bits.cfi_idx.bits << 1)).asSInt)
val offset_is_extended = (new_offset_value > max_offset_value ||
new_offset_value < min_offset_value)
val s1_update_wbtb_data = Wire(new BTBEntry)
s1_update_wbtb_data.extended := offset_is_extended
s1_update_wbtb_data.offset := new_offset_value
val s1_update_wbtb_mask = (UIntToOH(s1_update_cfi_idx) &
Fill(bankWidth, s1_update.bits.cfi_idx.valid && s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.is_commit_update))
val s1_update_wmeta_mask = ((s1_update_wbtb_mask | s1_update.bits.br_mask) &
(Fill(bankWidth, s1_update.valid && s1_update.bits.is_commit_update) |
(Fill(bankWidth, s1_update.valid) & s1_update.bits.btb_mispredicts)
)
)
val s1_update_wmeta_data = Wire(Vec(bankWidth, new BTBMeta))
for (w <- 0 until bankWidth) {
s1_update_wmeta_data(w).tag := Mux(s1_update.bits.btb_mispredicts(w), 0.U, s1_update_idx >> log2Ceil(nSets))
s1_update_wmeta_data(w).is_br := s1_update.bits.br_mask(w)
}
for (w <- 0 until nWays) {
when (doing_reset || s1_update_meta.write_way === w.U || (w == 0 && nWays == 1).B) {
btb(w).write(
Mux(doing_reset,
reset_idx,
s1_update_idx),
Mux(doing_reset,
VecInit(Seq.fill(bankWidth) { 0.U(btbEntrySz.W) }),
VecInit(Seq.fill(bankWidth) { s1_update_wbtb_data.asUInt })),
Mux(doing_reset,
(~(0.U(bankWidth.W))),
s1_update_wbtb_mask).asBools
)
meta(w).write(
Mux(doing_reset,
reset_idx,
s1_update_idx),
Mux(doing_reset,
VecInit(Seq.fill(bankWidth) { 0.U(btbMetaSz.W) }),
VecInit(s1_update_wmeta_data.map(_.asUInt))),
Mux(doing_reset,
(~(0.U(bankWidth.W))),
s1_update_wmeta_mask).asBools
)
}
}
when (s1_update_wbtb_mask =/= 0.U && offset_is_extended) {
ebtb.write(s1_update_idx, s1_update.bits.target)
}
} | module btb_1(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [55:0] R0_data,
input [6:0] W0_addr,
input W0_en,
input W0_clk,
input [55:0] W0_data,
input [3:0] W0_mask
);
btb_0_ext btb_0_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.tilelink._
class SinkEResponse(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val sink = UInt(params.inner.bundle.sinkBits.W)
}
class SinkE(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val resp = Valid(new SinkEResponse(params))
val e = Flipped(Decoupled(new TLBundleE(params.inner.bundle)))
})
if (params.firstLevel) {
// Tie off unused ports
io.resp.valid := false.B
io.resp.bits := DontCare
io.e.ready := true.B
} else {
// No restrictions on buffer
val e = params.micro.innerBuf.e(io.e)
e.ready := true.B
io.resp.valid := e.valid
io.resp.bits.sink := e.bits.sink
}
} | module SinkE(
output io_resp_valid,
output [2:0] io_resp_bits_sink,
input io_e_valid,
input [2:0] io_e_bits_sink
);
assign io_resp_valid = io_e_valid;
assign io_resp_bits_sink = io_e_bits_sink;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
/** This black-boxes an Async Reset
* (or Set)
* Register.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also have to hard-code the set/
* reset behavior.
*
* Do not confuse an asynchronous
* reset signal with an asynchronously
* reset reg. You should still
* properly synchronize your reset
* deassertion.
*
* @param d Data input
* @param q Data Output
* @param clk Clock Input
* @param rst Reset Input
* @param en Write Enable Input
*
*/
class AsyncResetReg(resetValue: Int = 0) extends RawModule {
val io = IO(new Bundle {
val d = Input(Bool())
val q = Output(Bool())
val en = Input(Bool())
val clk = Input(Clock())
val rst = Input(Reset())
})
val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
class SimpleRegIO(val w: Int) extends Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
}
class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
val io = IO(new SimpleRegIO(w))
val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
object AsyncResetReg {
// Create Single Registers
def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {
val reg = Module(new AsyncResetReg(if (init) 1 else 0))
reg.io.d := d
reg.io.clk := clk
reg.io.rst := rst
reg.io.en := true.B
name.foreach(reg.suggestName(_))
reg.io.q
}
def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)
def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))
// Create Vectors of Registers
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {
val w = updateData.getWidth max resetData.bitLength
val reg = Module(new AsyncResetRegVec(w, resetData))
name.foreach(reg.suggestName(_))
reg.io.d := updateData
reg.io.en := enable
reg.io.q
}
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,
resetData, enable, Some(name))
def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)
def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))
def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)
def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))
def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)
def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))
} | module AsyncResetRegVec_w1_i0(
input clock,
input reset,
input io_d,
output io_q
);
reg reg_0;
always @(posedge clock or posedge reset) begin
if (reset)
reg_0 <= 1'h0;
else
reg_0 <= io_d;
end
assign io_q = reg_0;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
} | module RoundAnyRawFNToRecFN_ie8_is24_oe11_os53(
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [9:0] io_in_sExp,
input [24:0] io_in_sig,
output [64:0] io_out
);
wire isNaNOut = io_invalidExc | io_in_isNaN;
assign io_out = {~isNaNOut & io_in_sign, {{2{io_in_sExp[9]}}, io_in_sExp} + 12'h700 & ~(io_in_isZero ? 12'hE00 : 12'h0) & {2'h3, ~io_in_isInf, 9'h1FF} | (io_in_isInf ? 12'hC00 : 12'h0) | (isNaNOut ? 12'hE00 : 12'h0), isNaNOut | io_in_isZero ? {isNaNOut, 51'h0} : {io_in_sig[22:0], 29'h0}};
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2017 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// ICache
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.ifu
import chisel3._
import chisel3.util._
import chisel3.util.random._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property._
import freechips.rocketchip.rocket.{HasL1ICacheParameters, ICacheParams, ICacheErrors, ICacheReq}
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix}
/**
* ICache module
*
* @param icacheParams parameters for the icache
* @param hartId the id of the hardware thread in the cache
* @param enableBlackBox use a blackbox icache
*/
class ICache(
val icacheParams: ICacheParams,
val staticIdForMetadataUseOnly: Int)(implicit p: Parameters)
extends LazyModule
{
lazy val module = new ICacheModule(this)
val masterNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
sourceId = IdRange(0, 1 + icacheParams.prefetch.toInt), // 0=refill, 1=hint
name = s"Core ${staticIdForMetadataUseOnly} ICache")))))
val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes
private val wordBytes = icacheParams.fetchBytes
}
/**
* IO Signals leaving the ICache
*
* @param outer top level ICache class
*/
class ICacheResp(val outer: ICache) extends Bundle
{
val data = UInt((outer.icacheParams.fetchBytes*8).W)
val replay = Bool()
val ae = Bool()
}
/**
* IO Signals for interacting with the ICache
*
* @param outer top level ICache class
*/
class ICacheBundle(val outer: ICache) extends BoomBundle()(outer.p)
with HasBoomFrontendParameters
{
val req = Flipped(Decoupled(new ICacheReq))
val s1_paddr = Input(UInt(paddrBits.W)) // delayed one cycle w.r.t. req
val s1_kill = Input(Bool()) // delayed one cycle w.r.t. req
val s2_kill = Input(Bool()) // delayed two cycles; prevents I$ miss emission
val resp = Valid(new ICacheResp(outer))
val invalidate = Input(Bool())
val perf = Output(new Bundle {
val acquire = Bool()
})
}
/**
* Get a tile-specific property without breaking deduplication
*/
object GetPropertyByHartId
{
def apply[T <: Data](tiles: Seq[RocketTileParams], f: RocketTileParams => Option[T], hartId: UInt): T = {
PriorityMux(tiles.collect { case t if f(t).isDefined => (t.tileId.U === hartId) -> f(t).get })
}
}
/**
* Main ICache module
*
* @param outer top level ICache class
*/
class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
with HasBoomFrontendParameters
{
val enableICacheDelay = tileParams.core.asInstanceOf[BoomCoreParams].enableICacheDelay
val io = IO(new ICacheBundle(outer))
val (tl_out, edge_out) = outer.masterNode.out(0)
require(isPow2(nSets) && isPow2(nWays))
require(usingVM)
require(pgIdxBits >= untagBits)
// How many bits do we intend to fetch at most every cycle?
val wordBits = outer.icacheParams.fetchBytes*8
// Each of these cases require some special-case handling.
require (tl_out.d.bits.data.getWidth == wordBits || (2*tl_out.d.bits.data.getWidth == wordBits && nBanks == 2))
// If TL refill is half the wordBits size and we have two banks, then the
// refill writes to only one bank per cycle (instead of across two banks every
// cycle).
val refillsToOneBank = (2*tl_out.d.bits.data.getWidth == wordBits)
val s0_valid = io.req.fire
val s0_vaddr = io.req.bits.addr
val s1_valid = RegNext(s0_valid)
val s1_tag_hit = Wire(Vec(nWays, Bool()))
val s1_hit = s1_tag_hit.reduce(_||_)
val s2_valid = RegNext(s1_valid && !io.s1_kill)
val s2_hit = RegNext(s1_hit)
val invalidated = Reg(Bool())
val refill_valid = RegInit(false.B)
val refill_fire = tl_out.a.fire
val s2_miss = s2_valid && !s2_hit && !RegNext(refill_valid)
val refill_paddr = RegEnable(io.s1_paddr, s1_valid && !(refill_valid || s2_miss))
val refill_tag = refill_paddr(tagBits+untagBits-1,untagBits)
val refill_idx = refill_paddr(untagBits-1,blockOffBits)
val refill_one_beat = tl_out.d.fire && edge_out.hasData(tl_out.d.bits)
io.req.ready := !refill_one_beat
val (_, _, d_done, refill_cnt) = edge_out.count(tl_out.d)
val refill_done = refill_one_beat && d_done
tl_out.d.ready := true.B
require (edge_out.manager.minLatency > 0)
val repl_way = if (isDM) 0.U else LFSR(16, refill_fire)(log2Ceil(nWays)-1,0)
val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(tagBits.W)))
val tag_rdata = tag_array.read(s0_vaddr(untagBits-1, blockOffBits), !refill_done && s0_valid)
when (refill_done) {
tag_array.write(refill_idx, VecInit(Seq.fill(nWays)(refill_tag)), Seq.tabulate(nWays)(repl_way === _.U))
}
val vb_array = RegInit(0.U((nSets*nWays).W))
when (refill_one_beat) {
vb_array := vb_array.bitSet(Cat(repl_way, refill_idx), refill_done && !invalidated)
}
when (io.invalidate) {
vb_array := 0.U
invalidated := true.B
}
val s2_dout = Wire(Vec(nWays, UInt(wordBits.W)))
val s1_bankid = Wire(Bool())
for (i <- 0 until nWays) {
val s1_idx = io.s1_paddr(untagBits-1,blockOffBits)
val s1_tag = io.s1_paddr(tagBits+untagBits-1,untagBits)
val s1_vb = vb_array(Cat(i.U, s1_idx))
val tag = tag_rdata(i)
s1_tag_hit(i) := s1_vb && tag === s1_tag
}
assert(PopCount(s1_tag_hit) <= 1.U || !s1_valid)
val ramDepth = if (refillsToOneBank && nBanks == 2) {
nSets * refillCycles / 2
} else {
nSets * refillCycles
}
val dataArrays = if (nBanks == 1) {
// Use unbanked icache for narrow accesses.
(0 until nWays).map { x =>
DescribedSRAM(
name = s"dataArrayWay_${x}",
desc = "ICache Data Array",
size = ramDepth,
data = UInt((wordBits).W)
)
}
} else {
// Use two banks, interleaved.
(0 until nWays).map { x =>
DescribedSRAM(
name = s"dataArrayB0Way_${x}",
desc = "ICache Data Array",
size = ramDepth,
data = UInt((wordBits/nBanks).W)
)} ++
(0 until nWays).map { x =>
DescribedSRAM(
name = s"dataArrayB1Way_${x}",
desc = "ICache Data Array",
size = ramDepth,
data = UInt((wordBits/nBanks).W)
)}
}
if (nBanks == 1) {
// Use unbanked icache for narrow accesses.
s1_bankid := 0.U
for ((dataArray, i) <- dataArrays.zipWithIndex) {
def row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles))
val s0_ren = s0_valid
val wen = (refill_one_beat && !invalidated) && repl_way === i.U
val mem_idx = Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) | refill_cnt,
row(s0_vaddr))
when (wen) {
dataArray.write(mem_idx, tl_out.d.bits.data)
}
if (enableICacheDelay)
s2_dout(i) := dataArray.read(RegNext(mem_idx), RegNext(!wen && s0_ren))
else
s2_dout(i) := RegNext(dataArray.read(mem_idx, !wen && s0_ren))
}
} else {
// Use two banks, interleaved.
val dataArraysB0 = dataArrays.take(nWays)
val dataArraysB1 = dataArrays.drop(nWays)
require (nBanks == 2)
// Bank0 row's id wraps around if Bank1 is the starting bank.
def b0Row(addr: UInt) =
if (refillsToOneBank) {
addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)+1) + bank(addr)
} else {
addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)) + bank(addr)
}
// Bank1 row's id stays the same regardless of which Bank has the fetch address.
def b1Row(addr: UInt) =
if (refillsToOneBank) {
addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)+1)
} else {
addr(untagBits-1, blockOffBits-log2Ceil(refillCycles))
}
s1_bankid := RegNext(bank(s0_vaddr))
for (i <- 0 until nWays) {
val s0_ren = s0_valid
val wen = (refill_one_beat && !invalidated)&& repl_way === i.U
var mem_idx0: UInt = null
var mem_idx1: UInt = null
if (refillsToOneBank) {
// write a refill beat across only one beat.
mem_idx0 =
Mux(refill_one_beat, (refill_idx << (log2Ceil(refillCycles)-1)) | (refill_cnt >> 1.U),
b0Row(s0_vaddr))
mem_idx1 =
Mux(refill_one_beat, (refill_idx << (log2Ceil(refillCycles)-1)) | (refill_cnt >> 1.U),
b1Row(s0_vaddr))
when (wen && refill_cnt(0) === 0.U) {
dataArraysB0(i).write(mem_idx0, tl_out.d.bits.data)
}
when (wen && refill_cnt(0) === 1.U) {
dataArraysB1(i).write(mem_idx1, tl_out.d.bits.data)
}
} else {
// write a refill beat across both banks.
mem_idx0 =
Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) | refill_cnt,
b0Row(s0_vaddr))
mem_idx1 =
Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) | refill_cnt,
b1Row(s0_vaddr))
when (wen) {
val data = tl_out.d.bits.data
dataArraysB0(i).write(mem_idx0, data(wordBits/2-1, 0))
dataArraysB1(i).write(mem_idx1, data(wordBits-1, wordBits/2))
}
}
if (enableICacheDelay) {
s2_dout(i) := Cat(dataArraysB1(i).read(RegNext(mem_idx1), RegNext(!wen && s0_ren)),
dataArraysB0(i).read(RegNext(mem_idx0), RegNext(!wen && s0_ren)))
} else {
s2_dout(i) := RegNext(Cat(dataArraysB1(i).read(mem_idx1, !wen && s0_ren),
dataArraysB0(i).read(mem_idx0, !wen && s0_ren)))
}
}
}
val s2_tag_hit = RegNext(s1_tag_hit)
val s2_hit_way = OHToUInt(s2_tag_hit)
val s2_bankid = RegNext(s1_bankid)
val s2_way_mux = Mux1H(s2_tag_hit, s2_dout)
val s2_unbanked_data = s2_way_mux
val sz = s2_way_mux.getWidth
val s2_bank0_data = s2_way_mux(sz/2-1,0)
val s2_bank1_data = s2_way_mux(sz-1,sz/2)
val s2_data =
if (nBanks == 2) {
Mux(s2_bankid,
Cat(s2_bank0_data, s2_bank1_data),
Cat(s2_bank1_data, s2_bank0_data))
} else {
s2_unbanked_data
}
io.resp.bits.ae := DontCare
io.resp.bits.replay := DontCare
io.resp.bits.data := s2_data
io.resp.valid := s2_valid && s2_hit
tl_out.a.valid := s2_miss && !refill_valid && !io.s2_kill
tl_out.a.bits := edge_out.Get(
fromSource = 0.U,
toAddress = (refill_paddr >> blockOffBits) << blockOffBits,
lgSize = lgCacheBlockBytes.U)._2
tl_out.b.ready := true.B
tl_out.c.valid := false.B
tl_out.e.valid := false.B
io.perf.acquire := tl_out.a.fire
when (!refill_valid) { invalidated := false.B }
when (refill_fire) { refill_valid := true.B }
when (refill_done) { refill_valid := false.B }
override def toString: String = BoomCoreStringPrefix(
"==L1-ICache==",
"Fetch bytes : " + cacheParams.fetchBytes,
"Block bytes : " + (1 << blockOffBits),
"Row bytes : " + rowBytes,
"Word bits : " + wordBits,
"Sets : " + nSets,
"Ways : " + nWays,
"Refill cycles : " + refillCycles,
"RAMs : (" + wordBits/nBanks + " x " + nSets*refillCycles + ") using " + nBanks + " banks",
"" + (if (nBanks == 2) "Dual-banked" else "Single-banked"),
"I-TLB ways : " + cacheParams.nTLBWays + "\n")
} | module tag_array_0(
input [5:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [79:0] RW0_wdata,
output [79:0] RW0_rdata,
input [3:0] RW0_wmask
);
tag_array_0_ext tag_array_0_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
trait TLFieldHelper {
def getBodyFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleC => Seq( b.data, b.corrupt)
case b: TLBundleD => Seq( b.data, b.corrupt)
case b: TLBundleE => Seq()
}
def getConstFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )
case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)
case b: TLBundleE => Seq( b.sink )
}
def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max
def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max
def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))
}
class TLBeat(val beatWidth: Int) extends Bundle {
val payload = UInt(beatWidth.W)
val head = Bool()
val tail = Bool()
}
abstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Flipped(Decoupled(gen))
val beat = Decoupled(new TLBeat(beatWidth))
})
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
// convert decoupled to irrevocable
val q = Module(new Queue(gen, 1, pipe=true, flow=true))
q.io.enq <> io.protocol
val protocol = q.io.deq
val has_body = Wire(Bool())
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val head = edge.first(protocol.bits, protocol.fire)
val tail = edge.last(protocol.bits, protocol.fire)
val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))
val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))
val is_body = RegInit(false.B)
io.beat.valid := protocol.valid
protocol.ready := io.beat.ready && (is_body || !has_body)
io.beat.bits.head := head && !is_body
io.beat.bits.tail := tail && (is_body || !has_body)
io.beat.bits.payload := Mux(is_body, body, const)
when (io.beat.fire && io.beat.bits.head) { is_body := true.B }
when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }
}
abstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Decoupled(gen)
val beat = Flipped(Decoupled(new TLBeat(beatWidth)))
})
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
val protocol = Wire(Decoupled(gen))
io.protocol <> protocol
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val is_const = RegInit(true.B)
val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))
val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)
io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready
protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid
def assign(i: UInt, sigs: Seq[Data]) = {
var t = i
for (s <- sigs.reverse) {
s := t.asTypeOf(s.cloneType)
t = t >> s.getWidth
}
}
assign(const, const_fields)
assign(io.beat.bits.payload, body_fields)
when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }
when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }
}
class TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)
class TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits)
}
class TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)
class TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p) | module TLAFromBeat_SerialRAM_a64d64s8k8z8c(
input clock,
input reset,
output io_beat_ready,
input io_beat_valid,
input io_beat_bits_head,
input io_beat_bits_tail
);
reg is_const;
wire io_beat_ready_0 = is_const & ~io_beat_bits_tail;
wire _GEN = io_beat_ready_0 & io_beat_valid;
always @(posedge clock) begin
if (reset)
is_const <= 1'h1;
else
is_const <= _GEN & io_beat_bits_tail | ~(_GEN & io_beat_bits_head) & is_const;
end
assign io_beat_ready = io_beat_ready_0;
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Execution Units
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// The issue window schedules micro-ops onto a specific execution pipeline
// A given execution pipeline may contain multiple functional units; one or more
// read ports, and one or more writeports.
package boom.v3.exu
import scala.collection.mutable.{ArrayBuffer}
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.rocket.{BP}
import freechips.rocketchip.tile
import FUConstants._
import boom.v3.common._
import boom.v3.ifu.{GetPCFromFtqIO}
import boom.v3.util.{ImmGen, IsKilledByBranch, BranchKillableQueue, BoomCoreStringPrefix}
/**
* Response from Execution Unit. Bundles a MicroOp with data
*
* @param dataWidth width of the data coming from the execution unit
*/
class ExeUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
with HasBoomUOP
{
val data = Bits(dataWidth.W)
val predicated = Bool() // Was this predicated off?
val fflags = new ValidIO(new FFlagsResp) // write fflags to ROB // TODO: Do this better
}
/**
* Floating Point flag response
*/
class FFlagsResp(implicit p: Parameters) extends BoomBundle
{
val uop = new MicroOp()
val flags = Bits(tile.FPConstants.FLAGS_SZ.W)
}
/**
* Abstract Top level Execution Unit that wraps lower level functional units to make a
* multi function execution unit.
*
* @param readsIrf does this exe unit need a integer regfile port
* @param writesIrf does this exe unit need a integer regfile port
* @param readsFrf does this exe unit need a integer regfile port
* @param writesFrf does this exe unit need a integer regfile port
* @param writesLlIrf does this exe unit need a integer regfile port
* @param writesLlFrf does this exe unit need a integer regfile port
* @param numBypassStages number of bypass ports for the exe unit
* @param dataWidth width of the data coming out of the exe unit
* @param bypassable is the exe unit able to be bypassed
* @param hasMem does the exe unit have a MemAddrCalcUnit
* @param hasCSR does the exe unit write to the CSRFile
* @param hasBrUnit does the exe unit have a branch unit
* @param hasAlu does the exe unit have a alu
* @param hasFpu does the exe unit have a fpu
* @param hasMul does the exe unit have a multiplier
* @param hasDiv does the exe unit have a divider
* @param hasFdiv does the exe unit have a FP divider
* @param hasIfpu does the exe unit have a int to FP unit
* @param hasFpiu does the exe unit have a FP to int unit
*/
abstract class ExecutionUnit(
val readsIrf : Boolean = false,
val writesIrf : Boolean = false,
val readsFrf : Boolean = false,
val writesFrf : Boolean = false,
val writesLlIrf : Boolean = false,
val writesLlFrf : Boolean = false,
val numBypassStages : Int,
val dataWidth : Int,
val bypassable : Boolean = false, // TODO make override def for code clarity
val alwaysBypassable : Boolean = false,
val hasMem : Boolean = false,
val hasCSR : Boolean = false,
val hasJmpUnit : Boolean = false,
val hasAlu : Boolean = false,
val hasFpu : Boolean = false,
val hasMul : Boolean = false,
val hasDiv : Boolean = false,
val hasFdiv : Boolean = false,
val hasIfpu : Boolean = false,
val hasFpiu : Boolean = false,
val hasRocc : Boolean = false
)(implicit p: Parameters) extends BoomModule
{
val io = IO(new Bundle {
val fu_types = Output(Bits(FUC_SZ.W))
val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth)))
val iresp = if (writesIrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null
val fresp = if (writesFrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null
val ll_iresp = if (writesLlIrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null
val ll_fresp = if (writesLlFrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null
val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth))))
val brupdate = Input(new BrUpdateInfo())
// only used by the rocc unit
val rocc = if (hasRocc) new RoCCShimCoreIO else null
// only used by the branch unit
val brinfo = if (hasAlu) Output(new BrResolutionInfo()) else null
val get_ftq_pc = if (hasJmpUnit) Flipped(new GetPCFromFtqIO()) else null
val status = Input(new freechips.rocketchip.rocket.MStatus())
// only used by the fpu unit
val fcsr_rm = if (hasFcsr) Input(Bits(tile.FPConstants.RM_SZ.W)) else null
// only used by the mem unit
val lsu_io = if (hasMem) Flipped(new boom.v3.lsu.LSUExeIO) else null
val bp = if (hasMem) Input(Vec(nBreakpoints, new BP)) else null
val mcontext = if (hasMem) Input(UInt(coreParams.mcontextWidth.W)) else null
val scontext = if (hasMem) Input(UInt(coreParams.scontextWidth.W)) else null
// TODO move this out of ExecutionUnit
val com_exception = if (hasMem || hasRocc) Input(Bool()) else null
})
io.req.ready := false.B
if (writesIrf) {
io.iresp.valid := false.B
io.iresp.bits := DontCare
io.iresp.bits.fflags.valid := false.B
io.iresp.bits.predicated := false.B
assert(io.iresp.ready)
}
if (writesLlIrf) {
io.ll_iresp.valid := false.B
io.ll_iresp.bits := DontCare
io.ll_iresp.bits.fflags.valid := false.B
io.ll_iresp.bits.predicated := false.B
}
if (writesFrf) {
io.fresp.valid := false.B
io.fresp.bits := DontCare
io.fresp.bits.fflags.valid := false.B
io.fresp.bits.predicated := false.B
assert(io.fresp.ready)
}
if (writesLlFrf) {
io.ll_fresp.valid := false.B
io.ll_fresp.bits := DontCare
io.ll_fresp.bits.fflags.valid := false.B
io.ll_fresp.bits.predicated := false.B
}
// TODO add "number of fflag ports", so we can properly account for FPU+Mem combinations
def hasFFlags : Boolean = hasFpu || hasFdiv
require ((hasFpu || hasFdiv) ^ (hasAlu || hasMul || hasMem || hasIfpu),
"[execute] we no longer support mixing FP and Integer functional units in the same exe unit.")
def hasFcsr = hasIfpu || hasFpu || hasFdiv
require (bypassable || !alwaysBypassable,
"[execute] an execution unit must be bypassable if it is always bypassable")
def supportedFuncUnits = {
new SupportedFuncUnits(
alu = hasAlu,
jmp = hasJmpUnit,
mem = hasMem,
muld = hasMul || hasDiv,
fpu = hasFpu,
csr = hasCSR,
fdiv = hasFdiv,
ifpu = hasIfpu)
}
}
/**
* ALU execution unit that can have a branch, alu, mul, div, int to FP,
* and memory unit.
*
* @param hasBrUnit does the exe unit have a branch unit
* @param hasCSR does the exe unit write to the CSRFile
* @param hasAlu does the exe unit have a alu
* @param hasMul does the exe unit have a multiplier
* @param hasDiv does the exe unit have a divider
* @param hasIfpu does the exe unit have a int to FP unit
* @param hasMem does the exe unit have a MemAddrCalcUnit
*/
class ALUExeUnit(
hasJmpUnit : Boolean = false,
hasCSR : Boolean = false,
hasAlu : Boolean = true,
hasMul : Boolean = false,
hasDiv : Boolean = false,
hasIfpu : Boolean = false,
hasMem : Boolean = false,
hasRocc : Boolean = false)
(implicit p: Parameters)
extends ExecutionUnit(
readsIrf = true,
writesIrf = hasAlu || hasMul || hasDiv,
writesLlIrf = hasMem || hasRocc,
writesLlFrf = (hasIfpu || hasMem) && p(tile.TileKey).core.fpu != None,
numBypassStages =
if (hasAlu && hasMul) 3 //TODO XXX p(tile.TileKey).core.imulLatency
else if (hasAlu) 1 else 0,
dataWidth = 64 + 1,
bypassable = hasAlu,
alwaysBypassable = hasAlu && !(hasMem || hasJmpUnit || hasMul || hasDiv || hasCSR || hasIfpu || hasRocc),
hasCSR = hasCSR,
hasJmpUnit = hasJmpUnit,
hasAlu = hasAlu,
hasMul = hasMul,
hasDiv = hasDiv,
hasIfpu = hasIfpu,
hasMem = hasMem,
hasRocc = hasRocc)
with freechips.rocketchip.rocket.constants.MemoryOpConstants
{
require(!(hasRocc && !hasCSR),
"RoCC needs to be shared with CSR unit")
require(!(hasMem && hasRocc),
"We do not support execution unit with both Mem and Rocc writebacks")
require(!(hasMem && hasIfpu),
"TODO. Currently do not support AluMemExeUnit with FP")
val out_str =
BoomCoreStringPrefix("==ExeUnit==") +
(if (hasAlu) BoomCoreStringPrefix(" - ALU") else "") +
(if (hasMul) BoomCoreStringPrefix(" - Mul") else "") +
(if (hasDiv) BoomCoreStringPrefix(" - Div") else "") +
(if (hasIfpu) BoomCoreStringPrefix(" - IFPU") else "") +
(if (hasMem) BoomCoreStringPrefix(" - Mem") else "") +
(if (hasRocc) BoomCoreStringPrefix(" - RoCC") else "")
override def toString: String = out_str.toString
val div_busy = WireInit(false.B)
val ifpu_busy = WireInit(false.B)
// The Functional Units --------------------
// Specifically the functional units with fast writeback to IRF
val iresp_fu_units = ArrayBuffer[FunctionalUnit]()
io.fu_types := Mux(hasAlu.B, FU_ALU, 0.U) |
Mux(hasMul.B, FU_MUL, 0.U) |
Mux(!div_busy && hasDiv.B, FU_DIV, 0.U) |
Mux(hasCSR.B, FU_CSR, 0.U) |
Mux(hasJmpUnit.B, FU_JMP, 0.U) |
Mux(!ifpu_busy && hasIfpu.B, FU_I2F, 0.U) |
Mux(hasMem.B, FU_MEM, 0.U)
// ALU Unit -------------------------------
var alu: ALUUnit = null
if (hasAlu) {
alu = Module(new ALUUnit(isJmpUnit = hasJmpUnit,
numStages = numBypassStages,
dataWidth = xLen))
alu.io.req.valid := (
io.req.valid &&
(io.req.bits.uop.fu_code === FU_ALU ||
io.req.bits.uop.fu_code === FU_JMP ||
(io.req.bits.uop.fu_code === FU_CSR && io.req.bits.uop.uopc =/= uopROCC)))
//ROCC Rocc Commands are taken by the RoCC unit
alu.io.req.bits.uop := io.req.bits.uop
alu.io.req.bits.kill := io.req.bits.kill
alu.io.req.bits.rs1_data := io.req.bits.rs1_data
alu.io.req.bits.rs2_data := io.req.bits.rs2_data
alu.io.req.bits.rs3_data := DontCare
alu.io.req.bits.pred_data := io.req.bits.pred_data
alu.io.resp.ready := DontCare
alu.io.brupdate := io.brupdate
iresp_fu_units += alu
// Bypassing only applies to ALU
io.bypass := alu.io.bypass
// branch unit is embedded inside the ALU
io.brinfo := alu.io.brinfo
if (hasJmpUnit) {
alu.io.get_ftq_pc <> io.get_ftq_pc
}
}
var rocc: RoCCShim = null
if (hasRocc) {
rocc = Module(new RoCCShim)
rocc.io.req.valid := io.req.valid && io.req.bits.uop.uopc === uopROCC
rocc.io.req.bits := DontCare
rocc.io.req.bits.uop := io.req.bits.uop
rocc.io.req.bits.kill := io.req.bits.kill
rocc.io.req.bits.rs1_data := io.req.bits.rs1_data
rocc.io.req.bits.rs2_data := io.req.bits.rs2_data
rocc.io.brupdate := io.brupdate // We should assert on this somewhere
rocc.io.status := io.status
rocc.io.exception := io.com_exception
io.rocc <> rocc.io.core
rocc.io.resp.ready := io.ll_iresp.ready
io.ll_iresp.valid := rocc.io.resp.valid
io.ll_iresp.bits.uop := rocc.io.resp.bits.uop
io.ll_iresp.bits.data := rocc.io.resp.bits.data
}
// Pipelined, IMul Unit ------------------
var imul: PipelinedMulUnit = null
if (hasMul) {
imul = Module(new PipelinedMulUnit(imulLatency, xLen))
imul.io <> DontCare
imul.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_MUL)
imul.io.req.bits.uop := io.req.bits.uop
imul.io.req.bits.rs1_data := io.req.bits.rs1_data
imul.io.req.bits.rs2_data := io.req.bits.rs2_data
imul.io.req.bits.kill := io.req.bits.kill
imul.io.brupdate := io.brupdate
iresp_fu_units += imul
}
var ifpu: IntToFPUnit = null
if (hasIfpu) {
ifpu = Module(new IntToFPUnit(latency=intToFpLatency))
ifpu.io.req <> io.req
ifpu.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_I2F)
ifpu.io.fcsr_rm := io.fcsr_rm
ifpu.io.brupdate <> io.brupdate
ifpu.io.resp.ready := DontCare
// buffer up results since we share write-port on integer regfile.
val queue = Module(new BranchKillableQueue(new ExeUnitResp(dataWidth),
entries = intToFpLatency + 3)) // TODO being overly conservative
queue.io.enq.valid := ifpu.io.resp.valid
queue.io.enq.bits.uop := ifpu.io.resp.bits.uop
queue.io.enq.bits.data := ifpu.io.resp.bits.data
queue.io.enq.bits.predicated := ifpu.io.resp.bits.predicated
queue.io.enq.bits.fflags := ifpu.io.resp.bits.fflags
queue.io.brupdate := io.brupdate
queue.io.flush := io.req.bits.kill
io.ll_fresp <> queue.io.deq
ifpu_busy := !(queue.io.empty)
assert (queue.io.enq.ready)
}
// Div/Rem Unit -----------------------
var div: DivUnit = null
val div_resp_val = WireInit(false.B)
if (hasDiv) {
div = Module(new DivUnit(xLen))
div.io <> DontCare
div.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_DIV) && hasDiv.B
div.io.req.bits.uop := io.req.bits.uop
div.io.req.bits.rs1_data := io.req.bits.rs1_data
div.io.req.bits.rs2_data := io.req.bits.rs2_data
div.io.brupdate := io.brupdate
div.io.req.bits.kill := io.req.bits.kill
// share write port with the pipelined units
div.io.resp.ready := !(iresp_fu_units.map(_.io.resp.valid).reduce(_|_))
div_resp_val := div.io.resp.valid
div_busy := !div.io.req.ready ||
(io.req.valid && io.req.bits.uop.fu_code_is(FU_DIV))
iresp_fu_units += div
}
// Mem Unit --------------------------
if (hasMem) {
require(!hasAlu)
val maddrcalc = Module(new MemAddrCalcUnit)
maddrcalc.io.req <> io.req
maddrcalc.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_MEM)
maddrcalc.io.brupdate <> io.brupdate
maddrcalc.io.status := io.status
maddrcalc.io.bp := io.bp
maddrcalc.io.mcontext := io.mcontext
maddrcalc.io.scontext := io.scontext
maddrcalc.io.resp.ready := DontCare
require(numBypassStages == 0)
io.lsu_io.req := maddrcalc.io.resp
io.ll_iresp <> io.lsu_io.iresp
if (usingFPU) {
io.ll_fresp <> io.lsu_io.fresp
}
}
// Outputs (Write Port #0) ---------------
if (writesIrf) {
io.iresp.valid := iresp_fu_units.map(_.io.resp.valid).reduce(_|_)
io.iresp.bits.uop := PriorityMux(iresp_fu_units.map(f =>
(f.io.resp.valid, f.io.resp.bits.uop)).toSeq)
io.iresp.bits.data := PriorityMux(iresp_fu_units.map(f =>
(f.io.resp.valid, f.io.resp.bits.data)).toSeq)
io.iresp.bits.predicated := PriorityMux(iresp_fu_units.map(f =>
(f.io.resp.valid, f.io.resp.bits.predicated)).toSeq)
// pulled out for critical path reasons
// TODO: Does this make sense as part of the iresp bundle?
if (hasAlu) {
io.iresp.bits.uop.csr_addr := ImmGen(alu.io.resp.bits.uop.imm_packed, IS_I).asUInt
io.iresp.bits.uop.ctrl.csr_cmd := alu.io.resp.bits.uop.ctrl.csr_cmd
}
}
assert ((PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 1.U && !div_resp_val) ||
(PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 2.U && (div_resp_val)),
"Multiple functional units are fighting over the write port.")
}
/**
* FPU-only unit, with optional second write-port for ToInt micro-ops.
*
* @param hasFpu does the exe unit have a fpu
* @param hasFdiv does the exe unit have a FP divider
* @param hasFpiu does the exe unit have a FP to int unit
*/
class FPUExeUnit(
hasFpu : Boolean = true,
hasFdiv : Boolean = false,
hasFpiu : Boolean = false
)
(implicit p: Parameters)
extends ExecutionUnit(
readsFrf = true,
writesFrf = true,
writesLlIrf = hasFpiu,
writesIrf = false,
numBypassStages = 0,
dataWidth = p(tile.TileKey).core.fpu.get.fLen + 1,
bypassable = false,
hasFpu = hasFpu,
hasFdiv = hasFdiv,
hasFpiu = hasFpiu) with tile.HasFPUParameters
{
val out_str =
BoomCoreStringPrefix("==ExeUnit==")
(if (hasFpu) BoomCoreStringPrefix("- FPU (Latency: " + dfmaLatency + ")") else "") +
(if (hasFdiv) BoomCoreStringPrefix("- FDiv/FSqrt") else "") +
(if (hasFpiu) BoomCoreStringPrefix("- FPIU (writes to Integer RF)") else "")
val fdiv_busy = WireInit(false.B)
val fpiu_busy = WireInit(false.B)
// The Functional Units --------------------
val fu_units = ArrayBuffer[FunctionalUnit]()
io.fu_types := Mux(hasFpu.B, FU_FPU, 0.U) |
Mux(!fdiv_busy && hasFdiv.B, FU_FDV, 0.U) |
Mux(!fpiu_busy && hasFpiu.B, FU_F2I, 0.U)
// FPU Unit -----------------------
var fpu: FPUUnit = null
val fpu_resp_val = WireInit(false.B)
val fpu_resp_fflags = Wire(new ValidIO(new FFlagsResp()))
fpu_resp_fflags.valid := false.B
if (hasFpu) {
fpu = Module(new FPUUnit())
fpu.io.req.valid := io.req.valid &&
(io.req.bits.uop.fu_code_is(FU_FPU) ||
io.req.bits.uop.fu_code_is(FU_F2I)) // TODO move to using a separate unit
fpu.io.req.bits.uop := io.req.bits.uop
fpu.io.req.bits.rs1_data := io.req.bits.rs1_data
fpu.io.req.bits.rs2_data := io.req.bits.rs2_data
fpu.io.req.bits.rs3_data := io.req.bits.rs3_data
fpu.io.req.bits.pred_data := false.B
fpu.io.req.bits.kill := io.req.bits.kill
fpu.io.fcsr_rm := io.fcsr_rm
fpu.io.brupdate := io.brupdate
fpu.io.resp.ready := DontCare
fpu_resp_val := fpu.io.resp.valid
fpu_resp_fflags := fpu.io.resp.bits.fflags
fu_units += fpu
}
// FDiv/FSqrt Unit -----------------------
var fdivsqrt: FDivSqrtUnit = null
val fdiv_resp_fflags = Wire(new ValidIO(new FFlagsResp()))
fdiv_resp_fflags := DontCare
fdiv_resp_fflags.valid := false.B
if (hasFdiv) {
fdivsqrt = Module(new FDivSqrtUnit())
fdivsqrt.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_FDV)
fdivsqrt.io.req.bits.uop := io.req.bits.uop
fdivsqrt.io.req.bits.rs1_data := io.req.bits.rs1_data
fdivsqrt.io.req.bits.rs2_data := io.req.bits.rs2_data
fdivsqrt.io.req.bits.rs3_data := DontCare
fdivsqrt.io.req.bits.pred_data := false.B
fdivsqrt.io.req.bits.kill := io.req.bits.kill
fdivsqrt.io.fcsr_rm := io.fcsr_rm
fdivsqrt.io.brupdate := io.brupdate
// share write port with the pipelined units
fdivsqrt.io.resp.ready := !(fu_units.map(_.io.resp.valid).reduce(_|_)) // TODO PERF will get blocked by fpiu.
fdiv_busy := !fdivsqrt.io.req.ready || (io.req.valid && io.req.bits.uop.fu_code_is(FU_FDV))
fdiv_resp_fflags := fdivsqrt.io.resp.bits.fflags
fu_units += fdivsqrt
}
// Outputs (Write Port #0) ---------------
io.fresp.valid := fu_units.map(_.io.resp.valid).reduce(_|_) &&
!(fpu.io.resp.valid && fpu.io.resp.bits.uop.fu_code_is(FU_F2I))
io.fresp.bits.uop := PriorityMux(fu_units.map(f => (f.io.resp.valid,
f.io.resp.bits.uop)).toSeq)
io.fresp.bits.data:= PriorityMux(fu_units.map(f => (f.io.resp.valid, f.io.resp.bits.data)).toSeq)
io.fresp.bits.fflags := Mux(fpu_resp_val, fpu_resp_fflags, fdiv_resp_fflags)
// Outputs (Write Port #1) -- FpToInt Queuing Unit -----------------------
if (hasFpiu) {
// TODO instantiate our own fpiu; and remove it from fpu.scala.
// buffer up results since we share write-port on integer regfile.
val queue = Module(new BranchKillableQueue(new ExeUnitResp(dataWidth),
entries = dfmaLatency + 3)) // TODO being overly conservative
queue.io.enq.valid := (fpu.io.resp.valid &&
fpu.io.resp.bits.uop.fu_code_is(FU_F2I) &&
fpu.io.resp.bits.uop.uopc =/= uopSTA) // STA means store data gen for floating point
queue.io.enq.bits.uop := fpu.io.resp.bits.uop
queue.io.enq.bits.data := fpu.io.resp.bits.data
queue.io.enq.bits.predicated := fpu.io.resp.bits.predicated
queue.io.enq.bits.fflags := fpu.io.resp.bits.fflags
queue.io.brupdate := io.brupdate
queue.io.flush := io.req.bits.kill
assert (queue.io.enq.ready) // If this backs up, we've miscalculated the size of the queue.
val fp_sdq = Module(new BranchKillableQueue(new ExeUnitResp(dataWidth),
entries = 3)) // Lets us backpressure floating point store data
fp_sdq.io.enq.valid := io.req.valid && io.req.bits.uop.uopc === uopSTA && !IsKilledByBranch(io.brupdate, io.req.bits.uop)
fp_sdq.io.enq.bits.uop := io.req.bits.uop
fp_sdq.io.enq.bits.data := ieee(io.req.bits.rs2_data)
fp_sdq.io.enq.bits.predicated := false.B
fp_sdq.io.enq.bits.fflags := DontCare
fp_sdq.io.brupdate := io.brupdate
fp_sdq.io.flush := io.req.bits.kill
assert(!(fp_sdq.io.enq.valid && !fp_sdq.io.enq.ready))
val resp_arb = Module(new Arbiter(new ExeUnitResp(dataWidth), 2))
resp_arb.io.in(0) <> queue.io.deq
resp_arb.io.in(1) <> fp_sdq.io.deq
io.ll_iresp <> resp_arb.io.out
fpiu_busy := !(queue.io.empty && fp_sdq.io.empty)
}
override def toString: String = out_str.toString
} | module FPUExeUnit(
input clock,
input reset,
output [9:0] io_fu_types,
input io_req_valid,
input [6:0] io_req_bits_uop_uopc,
input [31:0] io_req_bits_uop_inst,
input [31:0] io_req_bits_uop_debug_inst,
input io_req_bits_uop_is_rvc,
input [39:0] io_req_bits_uop_debug_pc,
input [2:0] io_req_bits_uop_iq_type,
input [9:0] io_req_bits_uop_fu_code,
input [3:0] io_req_bits_uop_ctrl_br_type,
input [1:0] io_req_bits_uop_ctrl_op1_sel,
input [2:0] io_req_bits_uop_ctrl_op2_sel,
input [2:0] io_req_bits_uop_ctrl_imm_sel,
input [4:0] io_req_bits_uop_ctrl_op_fcn,
input io_req_bits_uop_ctrl_fcn_dw,
input [2:0] io_req_bits_uop_ctrl_csr_cmd,
input io_req_bits_uop_ctrl_is_load,
input io_req_bits_uop_ctrl_is_sta,
input io_req_bits_uop_ctrl_is_std,
input [1:0] io_req_bits_uop_iw_state,
input io_req_bits_uop_iw_p1_poisoned,
input io_req_bits_uop_iw_p2_poisoned,
input io_req_bits_uop_is_br,
input io_req_bits_uop_is_jalr,
input io_req_bits_uop_is_jal,
input io_req_bits_uop_is_sfb,
input [7:0] io_req_bits_uop_br_mask,
input [2:0] io_req_bits_uop_br_tag,
input [3:0] io_req_bits_uop_ftq_idx,
input io_req_bits_uop_edge_inst,
input [5:0] io_req_bits_uop_pc_lob,
input io_req_bits_uop_taken,
input [19:0] io_req_bits_uop_imm_packed,
input [11:0] io_req_bits_uop_csr_addr,
input [4:0] io_req_bits_uop_rob_idx,
input [2:0] io_req_bits_uop_ldq_idx,
input [2:0] io_req_bits_uop_stq_idx,
input [1:0] io_req_bits_uop_rxq_idx,
input [5:0] io_req_bits_uop_pdst,
input [5:0] io_req_bits_uop_prs1,
input [5:0] io_req_bits_uop_prs2,
input [5:0] io_req_bits_uop_prs3,
input [3:0] io_req_bits_uop_ppred,
input io_req_bits_uop_prs1_busy,
input io_req_bits_uop_prs2_busy,
input io_req_bits_uop_prs3_busy,
input io_req_bits_uop_ppred_busy,
input [5:0] io_req_bits_uop_stale_pdst,
input io_req_bits_uop_exception,
input [63:0] io_req_bits_uop_exc_cause,
input io_req_bits_uop_bypassable,
input [4:0] io_req_bits_uop_mem_cmd,
input [1:0] io_req_bits_uop_mem_size,
input io_req_bits_uop_mem_signed,
input io_req_bits_uop_is_fence,
input io_req_bits_uop_is_fencei,
input io_req_bits_uop_is_amo,
input io_req_bits_uop_uses_ldq,
input io_req_bits_uop_uses_stq,
input io_req_bits_uop_is_sys_pc2epc,
input io_req_bits_uop_is_unique,
input io_req_bits_uop_flush_on_commit,
input io_req_bits_uop_ldst_is_rs1,
input [5:0] io_req_bits_uop_ldst,
input [5:0] io_req_bits_uop_lrs1,
input [5:0] io_req_bits_uop_lrs2,
input [5:0] io_req_bits_uop_lrs3,
input io_req_bits_uop_ldst_val,
input [1:0] io_req_bits_uop_dst_rtype,
input [1:0] io_req_bits_uop_lrs1_rtype,
input [1:0] io_req_bits_uop_lrs2_rtype,
input io_req_bits_uop_frs3_en,
input io_req_bits_uop_fp_val,
input io_req_bits_uop_fp_single,
input io_req_bits_uop_xcpt_pf_if,
input io_req_bits_uop_xcpt_ae_if,
input io_req_bits_uop_xcpt_ma_if,
input io_req_bits_uop_bp_debug_if,
input io_req_bits_uop_bp_xcpt_if,
input [1:0] io_req_bits_uop_debug_fsrc,
input [1:0] io_req_bits_uop_debug_tsrc,
input [64:0] io_req_bits_rs1_data,
input [64:0] io_req_bits_rs2_data,
input [64:0] io_req_bits_rs3_data,
input io_req_bits_kill,
output io_fresp_valid,
output [4:0] io_fresp_bits_uop_rob_idx,
output [5:0] io_fresp_bits_uop_pdst,
output io_fresp_bits_uop_is_amo,
output io_fresp_bits_uop_uses_ldq,
output io_fresp_bits_uop_uses_stq,
output [1:0] io_fresp_bits_uop_dst_rtype,
output io_fresp_bits_uop_fp_val,
output [64:0] io_fresp_bits_data,
output io_fresp_bits_fflags_valid,
output [4:0] io_fresp_bits_fflags_bits_uop_rob_idx,
output [4:0] io_fresp_bits_fflags_bits_flags,
input io_ll_iresp_ready,
output io_ll_iresp_valid,
output [6:0] io_ll_iresp_bits_uop_uopc,
output [7:0] io_ll_iresp_bits_uop_br_mask,
output [4:0] io_ll_iresp_bits_uop_rob_idx,
output [2:0] io_ll_iresp_bits_uop_stq_idx,
output [5:0] io_ll_iresp_bits_uop_pdst,
output io_ll_iresp_bits_uop_is_amo,
output io_ll_iresp_bits_uop_uses_stq,
output [1:0] io_ll_iresp_bits_uop_dst_rtype,
output [64:0] io_ll_iresp_bits_data,
output io_ll_iresp_bits_predicated,
input [7:0] io_brupdate_b1_resolve_mask,
input [7:0] io_brupdate_b1_mispredict_mask,
input [2:0] io_fcsr_rm
);
wire _fpiu_busy_T;
wire fdiv_busy;
wire _resp_arb_io_in_0_ready;
wire _resp_arb_io_in_1_ready;
wire _fp_sdq_io_enq_ready;
wire _fp_sdq_io_deq_valid;
wire [6:0] _fp_sdq_io_deq_bits_uop_uopc;
wire [7:0] _fp_sdq_io_deq_bits_uop_br_mask;
wire [4:0] _fp_sdq_io_deq_bits_uop_rob_idx;
wire [2:0] _fp_sdq_io_deq_bits_uop_stq_idx;
wire [5:0] _fp_sdq_io_deq_bits_uop_pdst;
wire _fp_sdq_io_deq_bits_uop_is_amo;
wire _fp_sdq_io_deq_bits_uop_uses_stq;
wire [1:0] _fp_sdq_io_deq_bits_uop_dst_rtype;
wire _fp_sdq_io_deq_bits_uop_fp_val;
wire [64:0] _fp_sdq_io_deq_bits_data;
wire _fp_sdq_io_deq_bits_predicated;
wire _fp_sdq_io_deq_bits_fflags_valid;
wire [4:0] _fp_sdq_io_deq_bits_fflags_bits_uop_rob_idx;
wire [4:0] _fp_sdq_io_deq_bits_fflags_bits_flags;
wire _fp_sdq_io_empty;
wire _queue_io_enq_ready;
wire _queue_io_deq_valid;
wire [6:0] _queue_io_deq_bits_uop_uopc;
wire [7:0] _queue_io_deq_bits_uop_br_mask;
wire [4:0] _queue_io_deq_bits_uop_rob_idx;
wire [2:0] _queue_io_deq_bits_uop_stq_idx;
wire [5:0] _queue_io_deq_bits_uop_pdst;
wire _queue_io_deq_bits_uop_is_amo;
wire _queue_io_deq_bits_uop_uses_stq;
wire [1:0] _queue_io_deq_bits_uop_dst_rtype;
wire _queue_io_deq_bits_uop_fp_val;
wire [64:0] _queue_io_deq_bits_data;
wire _queue_io_deq_bits_predicated;
wire _queue_io_deq_bits_fflags_valid;
wire [4:0] _queue_io_deq_bits_fflags_bits_uop_rob_idx;
wire [4:0] _queue_io_deq_bits_fflags_bits_flags;
wire _queue_io_empty;
wire _FDivSqrtUnit_io_req_ready;
wire _FDivSqrtUnit_io_resp_valid;
wire [4:0] _FDivSqrtUnit_io_resp_bits_uop_rob_idx;
wire [5:0] _FDivSqrtUnit_io_resp_bits_uop_pdst;
wire _FDivSqrtUnit_io_resp_bits_uop_is_amo;
wire _FDivSqrtUnit_io_resp_bits_uop_uses_ldq;
wire _FDivSqrtUnit_io_resp_bits_uop_uses_stq;
wire [1:0] _FDivSqrtUnit_io_resp_bits_uop_dst_rtype;
wire _FDivSqrtUnit_io_resp_bits_uop_fp_val;
wire [64:0] _FDivSqrtUnit_io_resp_bits_data;
wire _FDivSqrtUnit_io_resp_bits_fflags_valid;
wire [4:0] _FDivSqrtUnit_io_resp_bits_fflags_bits_uop_rob_idx;
wire [4:0] _FDivSqrtUnit_io_resp_bits_fflags_bits_flags;
wire _FPUUnit_io_resp_valid;
wire [6:0] _FPUUnit_io_resp_bits_uop_uopc;
wire [31:0] _FPUUnit_io_resp_bits_uop_inst;
wire [31:0] _FPUUnit_io_resp_bits_uop_debug_inst;
wire _FPUUnit_io_resp_bits_uop_is_rvc;
wire [39:0] _FPUUnit_io_resp_bits_uop_debug_pc;
wire [2:0] _FPUUnit_io_resp_bits_uop_iq_type;
wire [9:0] _FPUUnit_io_resp_bits_uop_fu_code;
wire [3:0] _FPUUnit_io_resp_bits_uop_ctrl_br_type;
wire [1:0] _FPUUnit_io_resp_bits_uop_ctrl_op1_sel;
wire [2:0] _FPUUnit_io_resp_bits_uop_ctrl_op2_sel;
wire [2:0] _FPUUnit_io_resp_bits_uop_ctrl_imm_sel;
wire [4:0] _FPUUnit_io_resp_bits_uop_ctrl_op_fcn;
wire _FPUUnit_io_resp_bits_uop_ctrl_fcn_dw;
wire [2:0] _FPUUnit_io_resp_bits_uop_ctrl_csr_cmd;
wire _FPUUnit_io_resp_bits_uop_ctrl_is_load;
wire _FPUUnit_io_resp_bits_uop_ctrl_is_sta;
wire _FPUUnit_io_resp_bits_uop_ctrl_is_std;
wire [1:0] _FPUUnit_io_resp_bits_uop_iw_state;
wire _FPUUnit_io_resp_bits_uop_iw_p1_poisoned;
wire _FPUUnit_io_resp_bits_uop_iw_p2_poisoned;
wire _FPUUnit_io_resp_bits_uop_is_br;
wire _FPUUnit_io_resp_bits_uop_is_jalr;
wire _FPUUnit_io_resp_bits_uop_is_jal;
wire _FPUUnit_io_resp_bits_uop_is_sfb;
wire [7:0] _FPUUnit_io_resp_bits_uop_br_mask;
wire [2:0] _FPUUnit_io_resp_bits_uop_br_tag;
wire [3:0] _FPUUnit_io_resp_bits_uop_ftq_idx;
wire _FPUUnit_io_resp_bits_uop_edge_inst;
wire [5:0] _FPUUnit_io_resp_bits_uop_pc_lob;
wire _FPUUnit_io_resp_bits_uop_taken;
wire [19:0] _FPUUnit_io_resp_bits_uop_imm_packed;
wire [11:0] _FPUUnit_io_resp_bits_uop_csr_addr;
wire [4:0] _FPUUnit_io_resp_bits_uop_rob_idx;
wire [2:0] _FPUUnit_io_resp_bits_uop_ldq_idx;
wire [2:0] _FPUUnit_io_resp_bits_uop_stq_idx;
wire [1:0] _FPUUnit_io_resp_bits_uop_rxq_idx;
wire [5:0] _FPUUnit_io_resp_bits_uop_pdst;
wire [5:0] _FPUUnit_io_resp_bits_uop_prs1;
wire [5:0] _FPUUnit_io_resp_bits_uop_prs2;
wire [5:0] _FPUUnit_io_resp_bits_uop_prs3;
wire [3:0] _FPUUnit_io_resp_bits_uop_ppred;
wire _FPUUnit_io_resp_bits_uop_prs1_busy;
wire _FPUUnit_io_resp_bits_uop_prs2_busy;
wire _FPUUnit_io_resp_bits_uop_prs3_busy;
wire _FPUUnit_io_resp_bits_uop_ppred_busy;
wire [5:0] _FPUUnit_io_resp_bits_uop_stale_pdst;
wire _FPUUnit_io_resp_bits_uop_exception;
wire [63:0] _FPUUnit_io_resp_bits_uop_exc_cause;
wire _FPUUnit_io_resp_bits_uop_bypassable;
wire [4:0] _FPUUnit_io_resp_bits_uop_mem_cmd;
wire [1:0] _FPUUnit_io_resp_bits_uop_mem_size;
wire _FPUUnit_io_resp_bits_uop_mem_signed;
wire _FPUUnit_io_resp_bits_uop_is_fence;
wire _FPUUnit_io_resp_bits_uop_is_fencei;
wire _FPUUnit_io_resp_bits_uop_is_amo;
wire _FPUUnit_io_resp_bits_uop_uses_ldq;
wire _FPUUnit_io_resp_bits_uop_uses_stq;
wire _FPUUnit_io_resp_bits_uop_is_sys_pc2epc;
wire _FPUUnit_io_resp_bits_uop_is_unique;
wire _FPUUnit_io_resp_bits_uop_flush_on_commit;
wire _FPUUnit_io_resp_bits_uop_ldst_is_rs1;
wire [5:0] _FPUUnit_io_resp_bits_uop_ldst;
wire [5:0] _FPUUnit_io_resp_bits_uop_lrs1;
wire [5:0] _FPUUnit_io_resp_bits_uop_lrs2;
wire [5:0] _FPUUnit_io_resp_bits_uop_lrs3;
wire _FPUUnit_io_resp_bits_uop_ldst_val;
wire [1:0] _FPUUnit_io_resp_bits_uop_dst_rtype;
wire [1:0] _FPUUnit_io_resp_bits_uop_lrs1_rtype;
wire [1:0] _FPUUnit_io_resp_bits_uop_lrs2_rtype;
wire _FPUUnit_io_resp_bits_uop_frs3_en;
wire _FPUUnit_io_resp_bits_uop_fp_val;
wire _FPUUnit_io_resp_bits_uop_fp_single;
wire _FPUUnit_io_resp_bits_uop_xcpt_pf_if;
wire _FPUUnit_io_resp_bits_uop_xcpt_ae_if;
wire _FPUUnit_io_resp_bits_uop_xcpt_ma_if;
wire _FPUUnit_io_resp_bits_uop_bp_debug_if;
wire _FPUUnit_io_resp_bits_uop_bp_xcpt_if;
wire [1:0] _FPUUnit_io_resp_bits_uop_debug_fsrc;
wire [1:0] _FPUUnit_io_resp_bits_uop_debug_tsrc;
wire [64:0] _FPUUnit_io_resp_bits_data;
wire _FPUUnit_io_resp_bits_fflags_valid;
wire [6:0] _FPUUnit_io_resp_bits_fflags_bits_uop_uopc;
wire [31:0] _FPUUnit_io_resp_bits_fflags_bits_uop_inst;
wire [31:0] _FPUUnit_io_resp_bits_fflags_bits_uop_debug_inst;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_rvc;
wire [39:0] _FPUUnit_io_resp_bits_fflags_bits_uop_debug_pc;
wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_iq_type;
wire [9:0] _FPUUnit_io_resp_bits_fflags_bits_uop_fu_code;
wire [3:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_br_type;
wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op1_sel;
wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op2_sel;
wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_imm_sel;
wire [4:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op_fcn;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_fcn_dw;
wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_csr_cmd;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_load;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_sta;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_std;
wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_iw_state;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_iw_p1_poisoned;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_iw_p2_poisoned;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_br;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_jalr;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_jal;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_sfb;
wire [7:0] _FPUUnit_io_resp_bits_fflags_bits_uop_br_mask;
wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_br_tag;
wire [3:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ftq_idx;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_edge_inst;
wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_pc_lob;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_taken;
wire [19:0] _FPUUnit_io_resp_bits_fflags_bits_uop_imm_packed;
wire [11:0] _FPUUnit_io_resp_bits_fflags_bits_uop_csr_addr;
wire [4:0] _FPUUnit_io_resp_bits_fflags_bits_uop_rob_idx;
wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ldq_idx;
wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_stq_idx;
wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_rxq_idx;
wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_pdst;
wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_prs1;
wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_prs2;
wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_prs3;
wire [3:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ppred;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_prs1_busy;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_prs2_busy;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_prs3_busy;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_ppred_busy;
wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_stale_pdst;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_exception;
wire [63:0] _FPUUnit_io_resp_bits_fflags_bits_uop_exc_cause;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_bypassable;
wire [4:0] _FPUUnit_io_resp_bits_fflags_bits_uop_mem_cmd;
wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_mem_size;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_mem_signed;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_fence;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_fencei;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_amo;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_uses_ldq;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_uses_stq;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_sys_pc2epc;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_unique;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_flush_on_commit;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_ldst_is_rs1;
wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ldst;
wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_lrs1;
wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_lrs2;
wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_lrs3;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_ldst_val;
wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_dst_rtype;
wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_lrs1_rtype;
wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_lrs2_rtype;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_frs3_en;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_fp_val;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_fp_single;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_pf_if;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_ae_if;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_ma_if;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_bp_debug_if;
wire _FPUUnit_io_resp_bits_fflags_bits_uop_bp_xcpt_if;
wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_debug_fsrc;
wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_debug_tsrc;
wire [4:0] _FPUUnit_io_resp_bits_fflags_bits_flags;
assign fdiv_busy = ~_FDivSqrtUnit_io_req_ready | io_req_valid & io_req_bits_uop_fu_code[7];
wire fp_sdq_io_enq_valid = io_req_valid & io_req_bits_uop_uopc == 7'h2 & (io_brupdate_b1_mispredict_mask & io_req_bits_uop_br_mask) == 8'h0;
wire fp_sdq_io_enq_bits_data_unrecoded_rawIn_isInf = (&(io_req_bits_rs2_data[63:62])) & ~(io_req_bits_rs2_data[61]);
wire fp_sdq_io_enq_bits_data_unrecoded_isSubnormal = $signed({1'h0, io_req_bits_rs2_data[63:52]}) < 13'sh402;
wire [52:0] _fp_sdq_io_enq_bits_data_unrecoded_denormFract_T_1 = {1'h0, |(io_req_bits_rs2_data[63:61]), io_req_bits_rs2_data[51:1]} >> 6'h1 - io_req_bits_rs2_data[57:52];
wire [51:0] fp_sdq_io_enq_bits_data_unrecoded_fractOut = fp_sdq_io_enq_bits_data_unrecoded_isSubnormal ? _fp_sdq_io_enq_bits_data_unrecoded_denormFract_T_1[51:0] : fp_sdq_io_enq_bits_data_unrecoded_rawIn_isInf ? 52'h0 : io_req_bits_rs2_data[51:0];
wire [1:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isSpecial_T = {io_req_bits_rs2_data[52], io_req_bits_rs2_data[30]};
wire fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isInf = (&_fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isSpecial_T) & ~(io_req_bits_rs2_data[29]);
wire fp_sdq_io_enq_bits_data_prevUnrecoded_isSubnormal = $signed({1'h0, io_req_bits_rs2_data[52], io_req_bits_rs2_data[30:23]}) < 10'sh82;
wire [23:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_denormFract_T_1 = {1'h0, |{io_req_bits_rs2_data[52], io_req_bits_rs2_data[30:29]}, io_req_bits_rs2_data[22:1]} >> 5'h1 - io_req_bits_rs2_data[27:23];
assign _fpiu_busy_T = _queue_io_empty & _fp_sdq_io_empty;
FPUUnit FPUUnit (
.clock (clock),
.reset (reset),
.io_req_valid (io_req_valid & (|{io_req_bits_uop_fu_code[6], io_req_bits_uop_fu_code[9]})),
.io_req_bits_uop_uopc (io_req_bits_uop_uopc),
.io_req_bits_uop_inst (io_req_bits_uop_inst),
.io_req_bits_uop_debug_inst (io_req_bits_uop_debug_inst),
.io_req_bits_uop_is_rvc (io_req_bits_uop_is_rvc),
.io_req_bits_uop_debug_pc (io_req_bits_uop_debug_pc),
.io_req_bits_uop_iq_type (io_req_bits_uop_iq_type),
.io_req_bits_uop_fu_code (io_req_bits_uop_fu_code),
.io_req_bits_uop_ctrl_br_type (io_req_bits_uop_ctrl_br_type),
.io_req_bits_uop_ctrl_op1_sel (io_req_bits_uop_ctrl_op1_sel),
.io_req_bits_uop_ctrl_op2_sel (io_req_bits_uop_ctrl_op2_sel),
.io_req_bits_uop_ctrl_imm_sel (io_req_bits_uop_ctrl_imm_sel),
.io_req_bits_uop_ctrl_op_fcn (io_req_bits_uop_ctrl_op_fcn),
.io_req_bits_uop_ctrl_fcn_dw (io_req_bits_uop_ctrl_fcn_dw),
.io_req_bits_uop_ctrl_csr_cmd (io_req_bits_uop_ctrl_csr_cmd),
.io_req_bits_uop_ctrl_is_load (io_req_bits_uop_ctrl_is_load),
.io_req_bits_uop_ctrl_is_sta (io_req_bits_uop_ctrl_is_sta),
.io_req_bits_uop_ctrl_is_std (io_req_bits_uop_ctrl_is_std),
.io_req_bits_uop_iw_state (io_req_bits_uop_iw_state),
.io_req_bits_uop_iw_p1_poisoned (io_req_bits_uop_iw_p1_poisoned),
.io_req_bits_uop_iw_p2_poisoned (io_req_bits_uop_iw_p2_poisoned),
.io_req_bits_uop_is_br (io_req_bits_uop_is_br),
.io_req_bits_uop_is_jalr (io_req_bits_uop_is_jalr),
.io_req_bits_uop_is_jal (io_req_bits_uop_is_jal),
.io_req_bits_uop_is_sfb (io_req_bits_uop_is_sfb),
.io_req_bits_uop_br_mask (io_req_bits_uop_br_mask),
.io_req_bits_uop_br_tag (io_req_bits_uop_br_tag),
.io_req_bits_uop_ftq_idx (io_req_bits_uop_ftq_idx),
.io_req_bits_uop_edge_inst (io_req_bits_uop_edge_inst),
.io_req_bits_uop_pc_lob (io_req_bits_uop_pc_lob),
.io_req_bits_uop_taken (io_req_bits_uop_taken),
.io_req_bits_uop_imm_packed (io_req_bits_uop_imm_packed),
.io_req_bits_uop_csr_addr (io_req_bits_uop_csr_addr),
.io_req_bits_uop_rob_idx (io_req_bits_uop_rob_idx),
.io_req_bits_uop_ldq_idx (io_req_bits_uop_ldq_idx),
.io_req_bits_uop_stq_idx (io_req_bits_uop_stq_idx),
.io_req_bits_uop_rxq_idx (io_req_bits_uop_rxq_idx),
.io_req_bits_uop_pdst (io_req_bits_uop_pdst),
.io_req_bits_uop_prs1 (io_req_bits_uop_prs1),
.io_req_bits_uop_prs2 (io_req_bits_uop_prs2),
.io_req_bits_uop_prs3 (io_req_bits_uop_prs3),
.io_req_bits_uop_ppred (io_req_bits_uop_ppred),
.io_req_bits_uop_prs1_busy (io_req_bits_uop_prs1_busy),
.io_req_bits_uop_prs2_busy (io_req_bits_uop_prs2_busy),
.io_req_bits_uop_prs3_busy (io_req_bits_uop_prs3_busy),
.io_req_bits_uop_ppred_busy (io_req_bits_uop_ppred_busy),
.io_req_bits_uop_stale_pdst (io_req_bits_uop_stale_pdst),
.io_req_bits_uop_exception (io_req_bits_uop_exception),
.io_req_bits_uop_exc_cause (io_req_bits_uop_exc_cause),
.io_req_bits_uop_bypassable (io_req_bits_uop_bypassable),
.io_req_bits_uop_mem_cmd (io_req_bits_uop_mem_cmd),
.io_req_bits_uop_mem_size (io_req_bits_uop_mem_size),
.io_req_bits_uop_mem_signed (io_req_bits_uop_mem_signed),
.io_req_bits_uop_is_fence (io_req_bits_uop_is_fence),
.io_req_bits_uop_is_fencei (io_req_bits_uop_is_fencei),
.io_req_bits_uop_is_amo (io_req_bits_uop_is_amo),
.io_req_bits_uop_uses_ldq (io_req_bits_uop_uses_ldq),
.io_req_bits_uop_uses_stq (io_req_bits_uop_uses_stq),
.io_req_bits_uop_is_sys_pc2epc (io_req_bits_uop_is_sys_pc2epc),
.io_req_bits_uop_is_unique (io_req_bits_uop_is_unique),
.io_req_bits_uop_flush_on_commit (io_req_bits_uop_flush_on_commit),
.io_req_bits_uop_ldst_is_rs1 (io_req_bits_uop_ldst_is_rs1),
.io_req_bits_uop_ldst (io_req_bits_uop_ldst),
.io_req_bits_uop_lrs1 (io_req_bits_uop_lrs1),
.io_req_bits_uop_lrs2 (io_req_bits_uop_lrs2),
.io_req_bits_uop_lrs3 (io_req_bits_uop_lrs3),
.io_req_bits_uop_ldst_val (io_req_bits_uop_ldst_val),
.io_req_bits_uop_dst_rtype (io_req_bits_uop_dst_rtype),
.io_req_bits_uop_lrs1_rtype (io_req_bits_uop_lrs1_rtype),
.io_req_bits_uop_lrs2_rtype (io_req_bits_uop_lrs2_rtype),
.io_req_bits_uop_frs3_en (io_req_bits_uop_frs3_en),
.io_req_bits_uop_fp_val (io_req_bits_uop_fp_val),
.io_req_bits_uop_fp_single (io_req_bits_uop_fp_single),
.io_req_bits_uop_xcpt_pf_if (io_req_bits_uop_xcpt_pf_if),
.io_req_bits_uop_xcpt_ae_if (io_req_bits_uop_xcpt_ae_if),
.io_req_bits_uop_xcpt_ma_if (io_req_bits_uop_xcpt_ma_if),
.io_req_bits_uop_bp_debug_if (io_req_bits_uop_bp_debug_if),
.io_req_bits_uop_bp_xcpt_if (io_req_bits_uop_bp_xcpt_if),
.io_req_bits_uop_debug_fsrc (io_req_bits_uop_debug_fsrc),
.io_req_bits_uop_debug_tsrc (io_req_bits_uop_debug_tsrc),
.io_req_bits_rs1_data (io_req_bits_rs1_data),
.io_req_bits_rs2_data (io_req_bits_rs2_data),
.io_req_bits_rs3_data (io_req_bits_rs3_data),
.io_req_bits_kill (io_req_bits_kill),
.io_resp_valid (_FPUUnit_io_resp_valid),
.io_resp_bits_uop_uopc (_FPUUnit_io_resp_bits_uop_uopc),
.io_resp_bits_uop_inst (_FPUUnit_io_resp_bits_uop_inst),
.io_resp_bits_uop_debug_inst (_FPUUnit_io_resp_bits_uop_debug_inst),
.io_resp_bits_uop_is_rvc (_FPUUnit_io_resp_bits_uop_is_rvc),
.io_resp_bits_uop_debug_pc (_FPUUnit_io_resp_bits_uop_debug_pc),
.io_resp_bits_uop_iq_type (_FPUUnit_io_resp_bits_uop_iq_type),
.io_resp_bits_uop_fu_code (_FPUUnit_io_resp_bits_uop_fu_code),
.io_resp_bits_uop_ctrl_br_type (_FPUUnit_io_resp_bits_uop_ctrl_br_type),
.io_resp_bits_uop_ctrl_op1_sel (_FPUUnit_io_resp_bits_uop_ctrl_op1_sel),
.io_resp_bits_uop_ctrl_op2_sel (_FPUUnit_io_resp_bits_uop_ctrl_op2_sel),
.io_resp_bits_uop_ctrl_imm_sel (_FPUUnit_io_resp_bits_uop_ctrl_imm_sel),
.io_resp_bits_uop_ctrl_op_fcn (_FPUUnit_io_resp_bits_uop_ctrl_op_fcn),
.io_resp_bits_uop_ctrl_fcn_dw (_FPUUnit_io_resp_bits_uop_ctrl_fcn_dw),
.io_resp_bits_uop_ctrl_csr_cmd (_FPUUnit_io_resp_bits_uop_ctrl_csr_cmd),
.io_resp_bits_uop_ctrl_is_load (_FPUUnit_io_resp_bits_uop_ctrl_is_load),
.io_resp_bits_uop_ctrl_is_sta (_FPUUnit_io_resp_bits_uop_ctrl_is_sta),
.io_resp_bits_uop_ctrl_is_std (_FPUUnit_io_resp_bits_uop_ctrl_is_std),
.io_resp_bits_uop_iw_state (_FPUUnit_io_resp_bits_uop_iw_state),
.io_resp_bits_uop_iw_p1_poisoned (_FPUUnit_io_resp_bits_uop_iw_p1_poisoned),
.io_resp_bits_uop_iw_p2_poisoned (_FPUUnit_io_resp_bits_uop_iw_p2_poisoned),
.io_resp_bits_uop_is_br (_FPUUnit_io_resp_bits_uop_is_br),
.io_resp_bits_uop_is_jalr (_FPUUnit_io_resp_bits_uop_is_jalr),
.io_resp_bits_uop_is_jal (_FPUUnit_io_resp_bits_uop_is_jal),
.io_resp_bits_uop_is_sfb (_FPUUnit_io_resp_bits_uop_is_sfb),
.io_resp_bits_uop_br_mask (_FPUUnit_io_resp_bits_uop_br_mask),
.io_resp_bits_uop_br_tag (_FPUUnit_io_resp_bits_uop_br_tag),
.io_resp_bits_uop_ftq_idx (_FPUUnit_io_resp_bits_uop_ftq_idx),
.io_resp_bits_uop_edge_inst (_FPUUnit_io_resp_bits_uop_edge_inst),
.io_resp_bits_uop_pc_lob (_FPUUnit_io_resp_bits_uop_pc_lob),
.io_resp_bits_uop_taken (_FPUUnit_io_resp_bits_uop_taken),
.io_resp_bits_uop_imm_packed (_FPUUnit_io_resp_bits_uop_imm_packed),
.io_resp_bits_uop_csr_addr (_FPUUnit_io_resp_bits_uop_csr_addr),
.io_resp_bits_uop_rob_idx (_FPUUnit_io_resp_bits_uop_rob_idx),
.io_resp_bits_uop_ldq_idx (_FPUUnit_io_resp_bits_uop_ldq_idx),
.io_resp_bits_uop_stq_idx (_FPUUnit_io_resp_bits_uop_stq_idx),
.io_resp_bits_uop_rxq_idx (_FPUUnit_io_resp_bits_uop_rxq_idx),
.io_resp_bits_uop_pdst (_FPUUnit_io_resp_bits_uop_pdst),
.io_resp_bits_uop_prs1 (_FPUUnit_io_resp_bits_uop_prs1),
.io_resp_bits_uop_prs2 (_FPUUnit_io_resp_bits_uop_prs2),
.io_resp_bits_uop_prs3 (_FPUUnit_io_resp_bits_uop_prs3),
.io_resp_bits_uop_ppred (_FPUUnit_io_resp_bits_uop_ppred),
.io_resp_bits_uop_prs1_busy (_FPUUnit_io_resp_bits_uop_prs1_busy),
.io_resp_bits_uop_prs2_busy (_FPUUnit_io_resp_bits_uop_prs2_busy),
.io_resp_bits_uop_prs3_busy (_FPUUnit_io_resp_bits_uop_prs3_busy),
.io_resp_bits_uop_ppred_busy (_FPUUnit_io_resp_bits_uop_ppred_busy),
.io_resp_bits_uop_stale_pdst (_FPUUnit_io_resp_bits_uop_stale_pdst),
.io_resp_bits_uop_exception (_FPUUnit_io_resp_bits_uop_exception),
.io_resp_bits_uop_exc_cause (_FPUUnit_io_resp_bits_uop_exc_cause),
.io_resp_bits_uop_bypassable (_FPUUnit_io_resp_bits_uop_bypassable),
.io_resp_bits_uop_mem_cmd (_FPUUnit_io_resp_bits_uop_mem_cmd),
.io_resp_bits_uop_mem_size (_FPUUnit_io_resp_bits_uop_mem_size),
.io_resp_bits_uop_mem_signed (_FPUUnit_io_resp_bits_uop_mem_signed),
.io_resp_bits_uop_is_fence (_FPUUnit_io_resp_bits_uop_is_fence),
.io_resp_bits_uop_is_fencei (_FPUUnit_io_resp_bits_uop_is_fencei),
.io_resp_bits_uop_is_amo (_FPUUnit_io_resp_bits_uop_is_amo),
.io_resp_bits_uop_uses_ldq (_FPUUnit_io_resp_bits_uop_uses_ldq),
.io_resp_bits_uop_uses_stq (_FPUUnit_io_resp_bits_uop_uses_stq),
.io_resp_bits_uop_is_sys_pc2epc (_FPUUnit_io_resp_bits_uop_is_sys_pc2epc),
.io_resp_bits_uop_is_unique (_FPUUnit_io_resp_bits_uop_is_unique),
.io_resp_bits_uop_flush_on_commit (_FPUUnit_io_resp_bits_uop_flush_on_commit),
.io_resp_bits_uop_ldst_is_rs1 (_FPUUnit_io_resp_bits_uop_ldst_is_rs1),
.io_resp_bits_uop_ldst (_FPUUnit_io_resp_bits_uop_ldst),
.io_resp_bits_uop_lrs1 (_FPUUnit_io_resp_bits_uop_lrs1),
.io_resp_bits_uop_lrs2 (_FPUUnit_io_resp_bits_uop_lrs2),
.io_resp_bits_uop_lrs3 (_FPUUnit_io_resp_bits_uop_lrs3),
.io_resp_bits_uop_ldst_val (_FPUUnit_io_resp_bits_uop_ldst_val),
.io_resp_bits_uop_dst_rtype (_FPUUnit_io_resp_bits_uop_dst_rtype),
.io_resp_bits_uop_lrs1_rtype (_FPUUnit_io_resp_bits_uop_lrs1_rtype),
.io_resp_bits_uop_lrs2_rtype (_FPUUnit_io_resp_bits_uop_lrs2_rtype),
.io_resp_bits_uop_frs3_en (_FPUUnit_io_resp_bits_uop_frs3_en),
.io_resp_bits_uop_fp_val (_FPUUnit_io_resp_bits_uop_fp_val),
.io_resp_bits_uop_fp_single (_FPUUnit_io_resp_bits_uop_fp_single),
.io_resp_bits_uop_xcpt_pf_if (_FPUUnit_io_resp_bits_uop_xcpt_pf_if),
.io_resp_bits_uop_xcpt_ae_if (_FPUUnit_io_resp_bits_uop_xcpt_ae_if),
.io_resp_bits_uop_xcpt_ma_if (_FPUUnit_io_resp_bits_uop_xcpt_ma_if),
.io_resp_bits_uop_bp_debug_if (_FPUUnit_io_resp_bits_uop_bp_debug_if),
.io_resp_bits_uop_bp_xcpt_if (_FPUUnit_io_resp_bits_uop_bp_xcpt_if),
.io_resp_bits_uop_debug_fsrc (_FPUUnit_io_resp_bits_uop_debug_fsrc),
.io_resp_bits_uop_debug_tsrc (_FPUUnit_io_resp_bits_uop_debug_tsrc),
.io_resp_bits_data (_FPUUnit_io_resp_bits_data),
.io_resp_bits_fflags_valid (_FPUUnit_io_resp_bits_fflags_valid),
.io_resp_bits_fflags_bits_uop_uopc (_FPUUnit_io_resp_bits_fflags_bits_uop_uopc),
.io_resp_bits_fflags_bits_uop_inst (_FPUUnit_io_resp_bits_fflags_bits_uop_inst),
.io_resp_bits_fflags_bits_uop_debug_inst (_FPUUnit_io_resp_bits_fflags_bits_uop_debug_inst),
.io_resp_bits_fflags_bits_uop_is_rvc (_FPUUnit_io_resp_bits_fflags_bits_uop_is_rvc),
.io_resp_bits_fflags_bits_uop_debug_pc (_FPUUnit_io_resp_bits_fflags_bits_uop_debug_pc),
.io_resp_bits_fflags_bits_uop_iq_type (_FPUUnit_io_resp_bits_fflags_bits_uop_iq_type),
.io_resp_bits_fflags_bits_uop_fu_code (_FPUUnit_io_resp_bits_fflags_bits_uop_fu_code),
.io_resp_bits_fflags_bits_uop_ctrl_br_type (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_br_type),
.io_resp_bits_fflags_bits_uop_ctrl_op1_sel (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op1_sel),
.io_resp_bits_fflags_bits_uop_ctrl_op2_sel (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op2_sel),
.io_resp_bits_fflags_bits_uop_ctrl_imm_sel (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_imm_sel),
.io_resp_bits_fflags_bits_uop_ctrl_op_fcn (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op_fcn),
.io_resp_bits_fflags_bits_uop_ctrl_fcn_dw (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_fcn_dw),
.io_resp_bits_fflags_bits_uop_ctrl_csr_cmd (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_csr_cmd),
.io_resp_bits_fflags_bits_uop_ctrl_is_load (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_load),
.io_resp_bits_fflags_bits_uop_ctrl_is_sta (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_sta),
.io_resp_bits_fflags_bits_uop_ctrl_is_std (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_std),
.io_resp_bits_fflags_bits_uop_iw_state (_FPUUnit_io_resp_bits_fflags_bits_uop_iw_state),
.io_resp_bits_fflags_bits_uop_iw_p1_poisoned (_FPUUnit_io_resp_bits_fflags_bits_uop_iw_p1_poisoned),
.io_resp_bits_fflags_bits_uop_iw_p2_poisoned (_FPUUnit_io_resp_bits_fflags_bits_uop_iw_p2_poisoned),
.io_resp_bits_fflags_bits_uop_is_br (_FPUUnit_io_resp_bits_fflags_bits_uop_is_br),
.io_resp_bits_fflags_bits_uop_is_jalr (_FPUUnit_io_resp_bits_fflags_bits_uop_is_jalr),
.io_resp_bits_fflags_bits_uop_is_jal (_FPUUnit_io_resp_bits_fflags_bits_uop_is_jal),
.io_resp_bits_fflags_bits_uop_is_sfb (_FPUUnit_io_resp_bits_fflags_bits_uop_is_sfb),
.io_resp_bits_fflags_bits_uop_br_mask (_FPUUnit_io_resp_bits_fflags_bits_uop_br_mask),
.io_resp_bits_fflags_bits_uop_br_tag (_FPUUnit_io_resp_bits_fflags_bits_uop_br_tag),
.io_resp_bits_fflags_bits_uop_ftq_idx (_FPUUnit_io_resp_bits_fflags_bits_uop_ftq_idx),
.io_resp_bits_fflags_bits_uop_edge_inst (_FPUUnit_io_resp_bits_fflags_bits_uop_edge_inst),
.io_resp_bits_fflags_bits_uop_pc_lob (_FPUUnit_io_resp_bits_fflags_bits_uop_pc_lob),
.io_resp_bits_fflags_bits_uop_taken (_FPUUnit_io_resp_bits_fflags_bits_uop_taken),
.io_resp_bits_fflags_bits_uop_imm_packed (_FPUUnit_io_resp_bits_fflags_bits_uop_imm_packed),
.io_resp_bits_fflags_bits_uop_csr_addr (_FPUUnit_io_resp_bits_fflags_bits_uop_csr_addr),
.io_resp_bits_fflags_bits_uop_rob_idx (_FPUUnit_io_resp_bits_fflags_bits_uop_rob_idx),
.io_resp_bits_fflags_bits_uop_ldq_idx (_FPUUnit_io_resp_bits_fflags_bits_uop_ldq_idx),
.io_resp_bits_fflags_bits_uop_stq_idx (_FPUUnit_io_resp_bits_fflags_bits_uop_stq_idx),
.io_resp_bits_fflags_bits_uop_rxq_idx (_FPUUnit_io_resp_bits_fflags_bits_uop_rxq_idx),
.io_resp_bits_fflags_bits_uop_pdst (_FPUUnit_io_resp_bits_fflags_bits_uop_pdst),
.io_resp_bits_fflags_bits_uop_prs1 (_FPUUnit_io_resp_bits_fflags_bits_uop_prs1),
.io_resp_bits_fflags_bits_uop_prs2 (_FPUUnit_io_resp_bits_fflags_bits_uop_prs2),
.io_resp_bits_fflags_bits_uop_prs3 (_FPUUnit_io_resp_bits_fflags_bits_uop_prs3),
.io_resp_bits_fflags_bits_uop_ppred (_FPUUnit_io_resp_bits_fflags_bits_uop_ppred),
.io_resp_bits_fflags_bits_uop_prs1_busy (_FPUUnit_io_resp_bits_fflags_bits_uop_prs1_busy),
.io_resp_bits_fflags_bits_uop_prs2_busy (_FPUUnit_io_resp_bits_fflags_bits_uop_prs2_busy),
.io_resp_bits_fflags_bits_uop_prs3_busy (_FPUUnit_io_resp_bits_fflags_bits_uop_prs3_busy),
.io_resp_bits_fflags_bits_uop_ppred_busy (_FPUUnit_io_resp_bits_fflags_bits_uop_ppred_busy),
.io_resp_bits_fflags_bits_uop_stale_pdst (_FPUUnit_io_resp_bits_fflags_bits_uop_stale_pdst),
.io_resp_bits_fflags_bits_uop_exception (_FPUUnit_io_resp_bits_fflags_bits_uop_exception),
.io_resp_bits_fflags_bits_uop_exc_cause (_FPUUnit_io_resp_bits_fflags_bits_uop_exc_cause),
.io_resp_bits_fflags_bits_uop_bypassable (_FPUUnit_io_resp_bits_fflags_bits_uop_bypassable),
.io_resp_bits_fflags_bits_uop_mem_cmd (_FPUUnit_io_resp_bits_fflags_bits_uop_mem_cmd),
.io_resp_bits_fflags_bits_uop_mem_size (_FPUUnit_io_resp_bits_fflags_bits_uop_mem_size),
.io_resp_bits_fflags_bits_uop_mem_signed (_FPUUnit_io_resp_bits_fflags_bits_uop_mem_signed),
.io_resp_bits_fflags_bits_uop_is_fence (_FPUUnit_io_resp_bits_fflags_bits_uop_is_fence),
.io_resp_bits_fflags_bits_uop_is_fencei (_FPUUnit_io_resp_bits_fflags_bits_uop_is_fencei),
.io_resp_bits_fflags_bits_uop_is_amo (_FPUUnit_io_resp_bits_fflags_bits_uop_is_amo),
.io_resp_bits_fflags_bits_uop_uses_ldq (_FPUUnit_io_resp_bits_fflags_bits_uop_uses_ldq),
.io_resp_bits_fflags_bits_uop_uses_stq (_FPUUnit_io_resp_bits_fflags_bits_uop_uses_stq),
.io_resp_bits_fflags_bits_uop_is_sys_pc2epc (_FPUUnit_io_resp_bits_fflags_bits_uop_is_sys_pc2epc),
.io_resp_bits_fflags_bits_uop_is_unique (_FPUUnit_io_resp_bits_fflags_bits_uop_is_unique),
.io_resp_bits_fflags_bits_uop_flush_on_commit (_FPUUnit_io_resp_bits_fflags_bits_uop_flush_on_commit),
.io_resp_bits_fflags_bits_uop_ldst_is_rs1 (_FPUUnit_io_resp_bits_fflags_bits_uop_ldst_is_rs1),
.io_resp_bits_fflags_bits_uop_ldst (_FPUUnit_io_resp_bits_fflags_bits_uop_ldst),
.io_resp_bits_fflags_bits_uop_lrs1 (_FPUUnit_io_resp_bits_fflags_bits_uop_lrs1),
.io_resp_bits_fflags_bits_uop_lrs2 (_FPUUnit_io_resp_bits_fflags_bits_uop_lrs2),
.io_resp_bits_fflags_bits_uop_lrs3 (_FPUUnit_io_resp_bits_fflags_bits_uop_lrs3),
.io_resp_bits_fflags_bits_uop_ldst_val (_FPUUnit_io_resp_bits_fflags_bits_uop_ldst_val),
.io_resp_bits_fflags_bits_uop_dst_rtype (_FPUUnit_io_resp_bits_fflags_bits_uop_dst_rtype),
.io_resp_bits_fflags_bits_uop_lrs1_rtype (_FPUUnit_io_resp_bits_fflags_bits_uop_lrs1_rtype),
.io_resp_bits_fflags_bits_uop_lrs2_rtype (_FPUUnit_io_resp_bits_fflags_bits_uop_lrs2_rtype),
.io_resp_bits_fflags_bits_uop_frs3_en (_FPUUnit_io_resp_bits_fflags_bits_uop_frs3_en),
.io_resp_bits_fflags_bits_uop_fp_val (_FPUUnit_io_resp_bits_fflags_bits_uop_fp_val),
.io_resp_bits_fflags_bits_uop_fp_single (_FPUUnit_io_resp_bits_fflags_bits_uop_fp_single),
.io_resp_bits_fflags_bits_uop_xcpt_pf_if (_FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_pf_if),
.io_resp_bits_fflags_bits_uop_xcpt_ae_if (_FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_ae_if),
.io_resp_bits_fflags_bits_uop_xcpt_ma_if (_FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_ma_if),
.io_resp_bits_fflags_bits_uop_bp_debug_if (_FPUUnit_io_resp_bits_fflags_bits_uop_bp_debug_if),
.io_resp_bits_fflags_bits_uop_bp_xcpt_if (_FPUUnit_io_resp_bits_fflags_bits_uop_bp_xcpt_if),
.io_resp_bits_fflags_bits_uop_debug_fsrc (_FPUUnit_io_resp_bits_fflags_bits_uop_debug_fsrc),
.io_resp_bits_fflags_bits_uop_debug_tsrc (_FPUUnit_io_resp_bits_fflags_bits_uop_debug_tsrc),
.io_resp_bits_fflags_bits_flags (_FPUUnit_io_resp_bits_fflags_bits_flags),
.io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask),
.io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask),
.io_fcsr_rm (io_fcsr_rm)
);
FDivSqrtUnit FDivSqrtUnit (
.clock (clock),
.reset (reset),
.io_req_ready (_FDivSqrtUnit_io_req_ready),
.io_req_valid (io_req_valid & io_req_bits_uop_fu_code[7]),
.io_req_bits_uop_uopc (io_req_bits_uop_uopc),
.io_req_bits_uop_br_mask (io_req_bits_uop_br_mask),
.io_req_bits_uop_imm_packed (io_req_bits_uop_imm_packed),
.io_req_bits_uop_rob_idx (io_req_bits_uop_rob_idx),
.io_req_bits_uop_pdst (io_req_bits_uop_pdst),
.io_req_bits_uop_is_amo (io_req_bits_uop_is_amo),
.io_req_bits_uop_uses_ldq (io_req_bits_uop_uses_ldq),
.io_req_bits_uop_uses_stq (io_req_bits_uop_uses_stq),
.io_req_bits_uop_dst_rtype (io_req_bits_uop_dst_rtype),
.io_req_bits_uop_fp_val (io_req_bits_uop_fp_val),
.io_req_bits_rs1_data (io_req_bits_rs1_data),
.io_req_bits_rs2_data (io_req_bits_rs2_data),
.io_req_bits_kill (io_req_bits_kill),
.io_resp_ready (~_FPUUnit_io_resp_valid),
.io_resp_valid (_FDivSqrtUnit_io_resp_valid),
.io_resp_bits_uop_rob_idx (_FDivSqrtUnit_io_resp_bits_uop_rob_idx),
.io_resp_bits_uop_pdst (_FDivSqrtUnit_io_resp_bits_uop_pdst),
.io_resp_bits_uop_is_amo (_FDivSqrtUnit_io_resp_bits_uop_is_amo),
.io_resp_bits_uop_uses_ldq (_FDivSqrtUnit_io_resp_bits_uop_uses_ldq),
.io_resp_bits_uop_uses_stq (_FDivSqrtUnit_io_resp_bits_uop_uses_stq),
.io_resp_bits_uop_dst_rtype (_FDivSqrtUnit_io_resp_bits_uop_dst_rtype),
.io_resp_bits_uop_fp_val (_FDivSqrtUnit_io_resp_bits_uop_fp_val),
.io_resp_bits_data (_FDivSqrtUnit_io_resp_bits_data),
.io_resp_bits_fflags_valid (_FDivSqrtUnit_io_resp_bits_fflags_valid),
.io_resp_bits_fflags_bits_uop_rob_idx (_FDivSqrtUnit_io_resp_bits_fflags_bits_uop_rob_idx),
.io_resp_bits_fflags_bits_flags (_FDivSqrtUnit_io_resp_bits_fflags_bits_flags),
.io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask),
.io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask),
.io_fcsr_rm (io_fcsr_rm)
);
BranchKillableQueue_4 queue (
.clock (clock),
.reset (reset),
.io_enq_ready (_queue_io_enq_ready),
.io_enq_valid (_FPUUnit_io_resp_valid & _FPUUnit_io_resp_bits_uop_fu_code[9] & _FPUUnit_io_resp_bits_uop_uopc != 7'h2),
.io_enq_bits_uop_uopc (_FPUUnit_io_resp_bits_uop_uopc),
.io_enq_bits_uop_inst (_FPUUnit_io_resp_bits_uop_inst),
.io_enq_bits_uop_debug_inst (_FPUUnit_io_resp_bits_uop_debug_inst),
.io_enq_bits_uop_is_rvc (_FPUUnit_io_resp_bits_uop_is_rvc),
.io_enq_bits_uop_debug_pc (_FPUUnit_io_resp_bits_uop_debug_pc),
.io_enq_bits_uop_iq_type (_FPUUnit_io_resp_bits_uop_iq_type),
.io_enq_bits_uop_fu_code (_FPUUnit_io_resp_bits_uop_fu_code),
.io_enq_bits_uop_ctrl_br_type (_FPUUnit_io_resp_bits_uop_ctrl_br_type),
.io_enq_bits_uop_ctrl_op1_sel (_FPUUnit_io_resp_bits_uop_ctrl_op1_sel),
.io_enq_bits_uop_ctrl_op2_sel (_FPUUnit_io_resp_bits_uop_ctrl_op2_sel),
.io_enq_bits_uop_ctrl_imm_sel (_FPUUnit_io_resp_bits_uop_ctrl_imm_sel),
.io_enq_bits_uop_ctrl_op_fcn (_FPUUnit_io_resp_bits_uop_ctrl_op_fcn),
.io_enq_bits_uop_ctrl_fcn_dw (_FPUUnit_io_resp_bits_uop_ctrl_fcn_dw),
.io_enq_bits_uop_ctrl_csr_cmd (_FPUUnit_io_resp_bits_uop_ctrl_csr_cmd),
.io_enq_bits_uop_ctrl_is_load (_FPUUnit_io_resp_bits_uop_ctrl_is_load),
.io_enq_bits_uop_ctrl_is_sta (_FPUUnit_io_resp_bits_uop_ctrl_is_sta),
.io_enq_bits_uop_ctrl_is_std (_FPUUnit_io_resp_bits_uop_ctrl_is_std),
.io_enq_bits_uop_iw_state (_FPUUnit_io_resp_bits_uop_iw_state),
.io_enq_bits_uop_iw_p1_poisoned (_FPUUnit_io_resp_bits_uop_iw_p1_poisoned),
.io_enq_bits_uop_iw_p2_poisoned (_FPUUnit_io_resp_bits_uop_iw_p2_poisoned),
.io_enq_bits_uop_is_br (_FPUUnit_io_resp_bits_uop_is_br),
.io_enq_bits_uop_is_jalr (_FPUUnit_io_resp_bits_uop_is_jalr),
.io_enq_bits_uop_is_jal (_FPUUnit_io_resp_bits_uop_is_jal),
.io_enq_bits_uop_is_sfb (_FPUUnit_io_resp_bits_uop_is_sfb),
.io_enq_bits_uop_br_mask (_FPUUnit_io_resp_bits_uop_br_mask),
.io_enq_bits_uop_br_tag (_FPUUnit_io_resp_bits_uop_br_tag),
.io_enq_bits_uop_ftq_idx (_FPUUnit_io_resp_bits_uop_ftq_idx),
.io_enq_bits_uop_edge_inst (_FPUUnit_io_resp_bits_uop_edge_inst),
.io_enq_bits_uop_pc_lob (_FPUUnit_io_resp_bits_uop_pc_lob),
.io_enq_bits_uop_taken (_FPUUnit_io_resp_bits_uop_taken),
.io_enq_bits_uop_imm_packed (_FPUUnit_io_resp_bits_uop_imm_packed),
.io_enq_bits_uop_csr_addr (_FPUUnit_io_resp_bits_uop_csr_addr),
.io_enq_bits_uop_rob_idx (_FPUUnit_io_resp_bits_uop_rob_idx),
.io_enq_bits_uop_ldq_idx (_FPUUnit_io_resp_bits_uop_ldq_idx),
.io_enq_bits_uop_stq_idx (_FPUUnit_io_resp_bits_uop_stq_idx),
.io_enq_bits_uop_rxq_idx (_FPUUnit_io_resp_bits_uop_rxq_idx),
.io_enq_bits_uop_pdst (_FPUUnit_io_resp_bits_uop_pdst),
.io_enq_bits_uop_prs1 (_FPUUnit_io_resp_bits_uop_prs1),
.io_enq_bits_uop_prs2 (_FPUUnit_io_resp_bits_uop_prs2),
.io_enq_bits_uop_prs3 (_FPUUnit_io_resp_bits_uop_prs3),
.io_enq_bits_uop_ppred (_FPUUnit_io_resp_bits_uop_ppred),
.io_enq_bits_uop_prs1_busy (_FPUUnit_io_resp_bits_uop_prs1_busy),
.io_enq_bits_uop_prs2_busy (_FPUUnit_io_resp_bits_uop_prs2_busy),
.io_enq_bits_uop_prs3_busy (_FPUUnit_io_resp_bits_uop_prs3_busy),
.io_enq_bits_uop_ppred_busy (_FPUUnit_io_resp_bits_uop_ppred_busy),
.io_enq_bits_uop_stale_pdst (_FPUUnit_io_resp_bits_uop_stale_pdst),
.io_enq_bits_uop_exception (_FPUUnit_io_resp_bits_uop_exception),
.io_enq_bits_uop_exc_cause (_FPUUnit_io_resp_bits_uop_exc_cause),
.io_enq_bits_uop_bypassable (_FPUUnit_io_resp_bits_uop_bypassable),
.io_enq_bits_uop_mem_cmd (_FPUUnit_io_resp_bits_uop_mem_cmd),
.io_enq_bits_uop_mem_size (_FPUUnit_io_resp_bits_uop_mem_size),
.io_enq_bits_uop_mem_signed (_FPUUnit_io_resp_bits_uop_mem_signed),
.io_enq_bits_uop_is_fence (_FPUUnit_io_resp_bits_uop_is_fence),
.io_enq_bits_uop_is_fencei (_FPUUnit_io_resp_bits_uop_is_fencei),
.io_enq_bits_uop_is_amo (_FPUUnit_io_resp_bits_uop_is_amo),
.io_enq_bits_uop_uses_ldq (_FPUUnit_io_resp_bits_uop_uses_ldq),
.io_enq_bits_uop_uses_stq (_FPUUnit_io_resp_bits_uop_uses_stq),
.io_enq_bits_uop_is_sys_pc2epc (_FPUUnit_io_resp_bits_uop_is_sys_pc2epc),
.io_enq_bits_uop_is_unique (_FPUUnit_io_resp_bits_uop_is_unique),
.io_enq_bits_uop_flush_on_commit (_FPUUnit_io_resp_bits_uop_flush_on_commit),
.io_enq_bits_uop_ldst_is_rs1 (_FPUUnit_io_resp_bits_uop_ldst_is_rs1),
.io_enq_bits_uop_ldst (_FPUUnit_io_resp_bits_uop_ldst),
.io_enq_bits_uop_lrs1 (_FPUUnit_io_resp_bits_uop_lrs1),
.io_enq_bits_uop_lrs2 (_FPUUnit_io_resp_bits_uop_lrs2),
.io_enq_bits_uop_lrs3 (_FPUUnit_io_resp_bits_uop_lrs3),
.io_enq_bits_uop_ldst_val (_FPUUnit_io_resp_bits_uop_ldst_val),
.io_enq_bits_uop_dst_rtype (_FPUUnit_io_resp_bits_uop_dst_rtype),
.io_enq_bits_uop_lrs1_rtype (_FPUUnit_io_resp_bits_uop_lrs1_rtype),
.io_enq_bits_uop_lrs2_rtype (_FPUUnit_io_resp_bits_uop_lrs2_rtype),
.io_enq_bits_uop_frs3_en (_FPUUnit_io_resp_bits_uop_frs3_en),
.io_enq_bits_uop_fp_val (_FPUUnit_io_resp_bits_uop_fp_val),
.io_enq_bits_uop_fp_single (_FPUUnit_io_resp_bits_uop_fp_single),
.io_enq_bits_uop_xcpt_pf_if (_FPUUnit_io_resp_bits_uop_xcpt_pf_if),
.io_enq_bits_uop_xcpt_ae_if (_FPUUnit_io_resp_bits_uop_xcpt_ae_if),
.io_enq_bits_uop_xcpt_ma_if (_FPUUnit_io_resp_bits_uop_xcpt_ma_if),
.io_enq_bits_uop_bp_debug_if (_FPUUnit_io_resp_bits_uop_bp_debug_if),
.io_enq_bits_uop_bp_xcpt_if (_FPUUnit_io_resp_bits_uop_bp_xcpt_if),
.io_enq_bits_uop_debug_fsrc (_FPUUnit_io_resp_bits_uop_debug_fsrc),
.io_enq_bits_uop_debug_tsrc (_FPUUnit_io_resp_bits_uop_debug_tsrc),
.io_enq_bits_data (_FPUUnit_io_resp_bits_data),
.io_enq_bits_fflags_valid (_FPUUnit_io_resp_bits_fflags_valid),
.io_enq_bits_fflags_bits_uop_uopc (_FPUUnit_io_resp_bits_fflags_bits_uop_uopc),
.io_enq_bits_fflags_bits_uop_inst (_FPUUnit_io_resp_bits_fflags_bits_uop_inst),
.io_enq_bits_fflags_bits_uop_debug_inst (_FPUUnit_io_resp_bits_fflags_bits_uop_debug_inst),
.io_enq_bits_fflags_bits_uop_is_rvc (_FPUUnit_io_resp_bits_fflags_bits_uop_is_rvc),
.io_enq_bits_fflags_bits_uop_debug_pc (_FPUUnit_io_resp_bits_fflags_bits_uop_debug_pc),
.io_enq_bits_fflags_bits_uop_iq_type (_FPUUnit_io_resp_bits_fflags_bits_uop_iq_type),
.io_enq_bits_fflags_bits_uop_fu_code (_FPUUnit_io_resp_bits_fflags_bits_uop_fu_code),
.io_enq_bits_fflags_bits_uop_ctrl_br_type (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_br_type),
.io_enq_bits_fflags_bits_uop_ctrl_op1_sel (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op1_sel),
.io_enq_bits_fflags_bits_uop_ctrl_op2_sel (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op2_sel),
.io_enq_bits_fflags_bits_uop_ctrl_imm_sel (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_imm_sel),
.io_enq_bits_fflags_bits_uop_ctrl_op_fcn (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op_fcn),
.io_enq_bits_fflags_bits_uop_ctrl_fcn_dw (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_fcn_dw),
.io_enq_bits_fflags_bits_uop_ctrl_csr_cmd (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_csr_cmd),
.io_enq_bits_fflags_bits_uop_ctrl_is_load (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_load),
.io_enq_bits_fflags_bits_uop_ctrl_is_sta (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_sta),
.io_enq_bits_fflags_bits_uop_ctrl_is_std (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_std),
.io_enq_bits_fflags_bits_uop_iw_state (_FPUUnit_io_resp_bits_fflags_bits_uop_iw_state),
.io_enq_bits_fflags_bits_uop_iw_p1_poisoned (_FPUUnit_io_resp_bits_fflags_bits_uop_iw_p1_poisoned),
.io_enq_bits_fflags_bits_uop_iw_p2_poisoned (_FPUUnit_io_resp_bits_fflags_bits_uop_iw_p2_poisoned),
.io_enq_bits_fflags_bits_uop_is_br (_FPUUnit_io_resp_bits_fflags_bits_uop_is_br),
.io_enq_bits_fflags_bits_uop_is_jalr (_FPUUnit_io_resp_bits_fflags_bits_uop_is_jalr),
.io_enq_bits_fflags_bits_uop_is_jal (_FPUUnit_io_resp_bits_fflags_bits_uop_is_jal),
.io_enq_bits_fflags_bits_uop_is_sfb (_FPUUnit_io_resp_bits_fflags_bits_uop_is_sfb),
.io_enq_bits_fflags_bits_uop_br_mask (_FPUUnit_io_resp_bits_fflags_bits_uop_br_mask),
.io_enq_bits_fflags_bits_uop_br_tag (_FPUUnit_io_resp_bits_fflags_bits_uop_br_tag),
.io_enq_bits_fflags_bits_uop_ftq_idx (_FPUUnit_io_resp_bits_fflags_bits_uop_ftq_idx),
.io_enq_bits_fflags_bits_uop_edge_inst (_FPUUnit_io_resp_bits_fflags_bits_uop_edge_inst),
.io_enq_bits_fflags_bits_uop_pc_lob (_FPUUnit_io_resp_bits_fflags_bits_uop_pc_lob),
.io_enq_bits_fflags_bits_uop_taken (_FPUUnit_io_resp_bits_fflags_bits_uop_taken),
.io_enq_bits_fflags_bits_uop_imm_packed (_FPUUnit_io_resp_bits_fflags_bits_uop_imm_packed),
.io_enq_bits_fflags_bits_uop_csr_addr (_FPUUnit_io_resp_bits_fflags_bits_uop_csr_addr),
.io_enq_bits_fflags_bits_uop_rob_idx (_FPUUnit_io_resp_bits_fflags_bits_uop_rob_idx),
.io_enq_bits_fflags_bits_uop_ldq_idx (_FPUUnit_io_resp_bits_fflags_bits_uop_ldq_idx),
.io_enq_bits_fflags_bits_uop_stq_idx (_FPUUnit_io_resp_bits_fflags_bits_uop_stq_idx),
.io_enq_bits_fflags_bits_uop_rxq_idx (_FPUUnit_io_resp_bits_fflags_bits_uop_rxq_idx),
.io_enq_bits_fflags_bits_uop_pdst (_FPUUnit_io_resp_bits_fflags_bits_uop_pdst),
.io_enq_bits_fflags_bits_uop_prs1 (_FPUUnit_io_resp_bits_fflags_bits_uop_prs1),
.io_enq_bits_fflags_bits_uop_prs2 (_FPUUnit_io_resp_bits_fflags_bits_uop_prs2),
.io_enq_bits_fflags_bits_uop_prs3 (_FPUUnit_io_resp_bits_fflags_bits_uop_prs3),
.io_enq_bits_fflags_bits_uop_ppred (_FPUUnit_io_resp_bits_fflags_bits_uop_ppred),
.io_enq_bits_fflags_bits_uop_prs1_busy (_FPUUnit_io_resp_bits_fflags_bits_uop_prs1_busy),
.io_enq_bits_fflags_bits_uop_prs2_busy (_FPUUnit_io_resp_bits_fflags_bits_uop_prs2_busy),
.io_enq_bits_fflags_bits_uop_prs3_busy (_FPUUnit_io_resp_bits_fflags_bits_uop_prs3_busy),
.io_enq_bits_fflags_bits_uop_ppred_busy (_FPUUnit_io_resp_bits_fflags_bits_uop_ppred_busy),
.io_enq_bits_fflags_bits_uop_stale_pdst (_FPUUnit_io_resp_bits_fflags_bits_uop_stale_pdst),
.io_enq_bits_fflags_bits_uop_exception (_FPUUnit_io_resp_bits_fflags_bits_uop_exception),
.io_enq_bits_fflags_bits_uop_exc_cause (_FPUUnit_io_resp_bits_fflags_bits_uop_exc_cause),
.io_enq_bits_fflags_bits_uop_bypassable (_FPUUnit_io_resp_bits_fflags_bits_uop_bypassable),
.io_enq_bits_fflags_bits_uop_mem_cmd (_FPUUnit_io_resp_bits_fflags_bits_uop_mem_cmd),
.io_enq_bits_fflags_bits_uop_mem_size (_FPUUnit_io_resp_bits_fflags_bits_uop_mem_size),
.io_enq_bits_fflags_bits_uop_mem_signed (_FPUUnit_io_resp_bits_fflags_bits_uop_mem_signed),
.io_enq_bits_fflags_bits_uop_is_fence (_FPUUnit_io_resp_bits_fflags_bits_uop_is_fence),
.io_enq_bits_fflags_bits_uop_is_fencei (_FPUUnit_io_resp_bits_fflags_bits_uop_is_fencei),
.io_enq_bits_fflags_bits_uop_is_amo (_FPUUnit_io_resp_bits_fflags_bits_uop_is_amo),
.io_enq_bits_fflags_bits_uop_uses_ldq (_FPUUnit_io_resp_bits_fflags_bits_uop_uses_ldq),
.io_enq_bits_fflags_bits_uop_uses_stq (_FPUUnit_io_resp_bits_fflags_bits_uop_uses_stq),
.io_enq_bits_fflags_bits_uop_is_sys_pc2epc (_FPUUnit_io_resp_bits_fflags_bits_uop_is_sys_pc2epc),
.io_enq_bits_fflags_bits_uop_is_unique (_FPUUnit_io_resp_bits_fflags_bits_uop_is_unique),
.io_enq_bits_fflags_bits_uop_flush_on_commit (_FPUUnit_io_resp_bits_fflags_bits_uop_flush_on_commit),
.io_enq_bits_fflags_bits_uop_ldst_is_rs1 (_FPUUnit_io_resp_bits_fflags_bits_uop_ldst_is_rs1),
.io_enq_bits_fflags_bits_uop_ldst (_FPUUnit_io_resp_bits_fflags_bits_uop_ldst),
.io_enq_bits_fflags_bits_uop_lrs1 (_FPUUnit_io_resp_bits_fflags_bits_uop_lrs1),
.io_enq_bits_fflags_bits_uop_lrs2 (_FPUUnit_io_resp_bits_fflags_bits_uop_lrs2),
.io_enq_bits_fflags_bits_uop_lrs3 (_FPUUnit_io_resp_bits_fflags_bits_uop_lrs3),
.io_enq_bits_fflags_bits_uop_ldst_val (_FPUUnit_io_resp_bits_fflags_bits_uop_ldst_val),
.io_enq_bits_fflags_bits_uop_dst_rtype (_FPUUnit_io_resp_bits_fflags_bits_uop_dst_rtype),
.io_enq_bits_fflags_bits_uop_lrs1_rtype (_FPUUnit_io_resp_bits_fflags_bits_uop_lrs1_rtype),
.io_enq_bits_fflags_bits_uop_lrs2_rtype (_FPUUnit_io_resp_bits_fflags_bits_uop_lrs2_rtype),
.io_enq_bits_fflags_bits_uop_frs3_en (_FPUUnit_io_resp_bits_fflags_bits_uop_frs3_en),
.io_enq_bits_fflags_bits_uop_fp_val (_FPUUnit_io_resp_bits_fflags_bits_uop_fp_val),
.io_enq_bits_fflags_bits_uop_fp_single (_FPUUnit_io_resp_bits_fflags_bits_uop_fp_single),
.io_enq_bits_fflags_bits_uop_xcpt_pf_if (_FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_pf_if),
.io_enq_bits_fflags_bits_uop_xcpt_ae_if (_FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_ae_if),
.io_enq_bits_fflags_bits_uop_xcpt_ma_if (_FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_ma_if),
.io_enq_bits_fflags_bits_uop_bp_debug_if (_FPUUnit_io_resp_bits_fflags_bits_uop_bp_debug_if),
.io_enq_bits_fflags_bits_uop_bp_xcpt_if (_FPUUnit_io_resp_bits_fflags_bits_uop_bp_xcpt_if),
.io_enq_bits_fflags_bits_uop_debug_fsrc (_FPUUnit_io_resp_bits_fflags_bits_uop_debug_fsrc),
.io_enq_bits_fflags_bits_uop_debug_tsrc (_FPUUnit_io_resp_bits_fflags_bits_uop_debug_tsrc),
.io_enq_bits_fflags_bits_flags (_FPUUnit_io_resp_bits_fflags_bits_flags),
.io_deq_ready (_resp_arb_io_in_0_ready),
.io_deq_valid (_queue_io_deq_valid),
.io_deq_bits_uop_uopc (_queue_io_deq_bits_uop_uopc),
.io_deq_bits_uop_br_mask (_queue_io_deq_bits_uop_br_mask),
.io_deq_bits_uop_rob_idx (_queue_io_deq_bits_uop_rob_idx),
.io_deq_bits_uop_stq_idx (_queue_io_deq_bits_uop_stq_idx),
.io_deq_bits_uop_pdst (_queue_io_deq_bits_uop_pdst),
.io_deq_bits_uop_is_amo (_queue_io_deq_bits_uop_is_amo),
.io_deq_bits_uop_uses_stq (_queue_io_deq_bits_uop_uses_stq),
.io_deq_bits_uop_dst_rtype (_queue_io_deq_bits_uop_dst_rtype),
.io_deq_bits_uop_fp_val (_queue_io_deq_bits_uop_fp_val),
.io_deq_bits_data (_queue_io_deq_bits_data),
.io_deq_bits_predicated (_queue_io_deq_bits_predicated),
.io_deq_bits_fflags_valid (_queue_io_deq_bits_fflags_valid),
.io_deq_bits_fflags_bits_uop_rob_idx (_queue_io_deq_bits_fflags_bits_uop_rob_idx),
.io_deq_bits_fflags_bits_flags (_queue_io_deq_bits_fflags_bits_flags),
.io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask),
.io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask),
.io_flush (io_req_bits_kill),
.io_empty (_queue_io_empty)
);
BranchKillableQueue_5 fp_sdq (
.clock (clock),
.reset (reset),
.io_enq_ready (_fp_sdq_io_enq_ready),
.io_enq_valid (fp_sdq_io_enq_valid),
.io_enq_bits_uop_uopc (io_req_bits_uop_uopc),
.io_enq_bits_uop_inst (io_req_bits_uop_inst),
.io_enq_bits_uop_debug_inst (io_req_bits_uop_debug_inst),
.io_enq_bits_uop_is_rvc (io_req_bits_uop_is_rvc),
.io_enq_bits_uop_debug_pc (io_req_bits_uop_debug_pc),
.io_enq_bits_uop_iq_type (io_req_bits_uop_iq_type),
.io_enq_bits_uop_fu_code (io_req_bits_uop_fu_code),
.io_enq_bits_uop_ctrl_br_type (io_req_bits_uop_ctrl_br_type),
.io_enq_bits_uop_ctrl_op1_sel (io_req_bits_uop_ctrl_op1_sel),
.io_enq_bits_uop_ctrl_op2_sel (io_req_bits_uop_ctrl_op2_sel),
.io_enq_bits_uop_ctrl_imm_sel (io_req_bits_uop_ctrl_imm_sel),
.io_enq_bits_uop_ctrl_op_fcn (io_req_bits_uop_ctrl_op_fcn),
.io_enq_bits_uop_ctrl_fcn_dw (io_req_bits_uop_ctrl_fcn_dw),
.io_enq_bits_uop_ctrl_csr_cmd (io_req_bits_uop_ctrl_csr_cmd),
.io_enq_bits_uop_ctrl_is_load (io_req_bits_uop_ctrl_is_load),
.io_enq_bits_uop_ctrl_is_sta (io_req_bits_uop_ctrl_is_sta),
.io_enq_bits_uop_ctrl_is_std (io_req_bits_uop_ctrl_is_std),
.io_enq_bits_uop_iw_state (io_req_bits_uop_iw_state),
.io_enq_bits_uop_iw_p1_poisoned (io_req_bits_uop_iw_p1_poisoned),
.io_enq_bits_uop_iw_p2_poisoned (io_req_bits_uop_iw_p2_poisoned),
.io_enq_bits_uop_is_br (io_req_bits_uop_is_br),
.io_enq_bits_uop_is_jalr (io_req_bits_uop_is_jalr),
.io_enq_bits_uop_is_jal (io_req_bits_uop_is_jal),
.io_enq_bits_uop_is_sfb (io_req_bits_uop_is_sfb),
.io_enq_bits_uop_br_mask (io_req_bits_uop_br_mask),
.io_enq_bits_uop_br_tag (io_req_bits_uop_br_tag),
.io_enq_bits_uop_ftq_idx (io_req_bits_uop_ftq_idx),
.io_enq_bits_uop_edge_inst (io_req_bits_uop_edge_inst),
.io_enq_bits_uop_pc_lob (io_req_bits_uop_pc_lob),
.io_enq_bits_uop_taken (io_req_bits_uop_taken),
.io_enq_bits_uop_imm_packed (io_req_bits_uop_imm_packed),
.io_enq_bits_uop_csr_addr (io_req_bits_uop_csr_addr),
.io_enq_bits_uop_rob_idx (io_req_bits_uop_rob_idx),
.io_enq_bits_uop_ldq_idx (io_req_bits_uop_ldq_idx),
.io_enq_bits_uop_stq_idx (io_req_bits_uop_stq_idx),
.io_enq_bits_uop_rxq_idx (io_req_bits_uop_rxq_idx),
.io_enq_bits_uop_pdst (io_req_bits_uop_pdst),
.io_enq_bits_uop_prs1 (io_req_bits_uop_prs1),
.io_enq_bits_uop_prs2 (io_req_bits_uop_prs2),
.io_enq_bits_uop_prs3 (io_req_bits_uop_prs3),
.io_enq_bits_uop_ppred (io_req_bits_uop_ppred),
.io_enq_bits_uop_prs1_busy (io_req_bits_uop_prs1_busy),
.io_enq_bits_uop_prs2_busy (io_req_bits_uop_prs2_busy),
.io_enq_bits_uop_prs3_busy (io_req_bits_uop_prs3_busy),
.io_enq_bits_uop_ppred_busy (io_req_bits_uop_ppred_busy),
.io_enq_bits_uop_stale_pdst (io_req_bits_uop_stale_pdst),
.io_enq_bits_uop_exception (io_req_bits_uop_exception),
.io_enq_bits_uop_exc_cause (io_req_bits_uop_exc_cause),
.io_enq_bits_uop_bypassable (io_req_bits_uop_bypassable),
.io_enq_bits_uop_mem_cmd (io_req_bits_uop_mem_cmd),
.io_enq_bits_uop_mem_size (io_req_bits_uop_mem_size),
.io_enq_bits_uop_mem_signed (io_req_bits_uop_mem_signed),
.io_enq_bits_uop_is_fence (io_req_bits_uop_is_fence),
.io_enq_bits_uop_is_fencei (io_req_bits_uop_is_fencei),
.io_enq_bits_uop_is_amo (io_req_bits_uop_is_amo),
.io_enq_bits_uop_uses_ldq (io_req_bits_uop_uses_ldq),
.io_enq_bits_uop_uses_stq (io_req_bits_uop_uses_stq),
.io_enq_bits_uop_is_sys_pc2epc (io_req_bits_uop_is_sys_pc2epc),
.io_enq_bits_uop_is_unique (io_req_bits_uop_is_unique),
.io_enq_bits_uop_flush_on_commit (io_req_bits_uop_flush_on_commit),
.io_enq_bits_uop_ldst_is_rs1 (io_req_bits_uop_ldst_is_rs1),
.io_enq_bits_uop_ldst (io_req_bits_uop_ldst),
.io_enq_bits_uop_lrs1 (io_req_bits_uop_lrs1),
.io_enq_bits_uop_lrs2 (io_req_bits_uop_lrs2),
.io_enq_bits_uop_lrs3 (io_req_bits_uop_lrs3),
.io_enq_bits_uop_ldst_val (io_req_bits_uop_ldst_val),
.io_enq_bits_uop_dst_rtype (io_req_bits_uop_dst_rtype),
.io_enq_bits_uop_lrs1_rtype (io_req_bits_uop_lrs1_rtype),
.io_enq_bits_uop_lrs2_rtype (io_req_bits_uop_lrs2_rtype),
.io_enq_bits_uop_frs3_en (io_req_bits_uop_frs3_en),
.io_enq_bits_uop_fp_val (io_req_bits_uop_fp_val),
.io_enq_bits_uop_fp_single (io_req_bits_uop_fp_single),
.io_enq_bits_uop_xcpt_pf_if (io_req_bits_uop_xcpt_pf_if),
.io_enq_bits_uop_xcpt_ae_if (io_req_bits_uop_xcpt_ae_if),
.io_enq_bits_uop_xcpt_ma_if (io_req_bits_uop_xcpt_ma_if),
.io_enq_bits_uop_bp_debug_if (io_req_bits_uop_bp_debug_if),
.io_enq_bits_uop_bp_xcpt_if (io_req_bits_uop_bp_xcpt_if),
.io_enq_bits_uop_debug_fsrc (io_req_bits_uop_debug_fsrc),
.io_enq_bits_uop_debug_tsrc (io_req_bits_uop_debug_tsrc),
.io_enq_bits_data ({1'h0, io_req_bits_rs2_data[64], (fp_sdq_io_enq_bits_data_unrecoded_isSubnormal ? 11'h0 : io_req_bits_rs2_data[62:52] + 11'h3FF) | {11{(&(io_req_bits_rs2_data[63:62])) & io_req_bits_rs2_data[61] | fp_sdq_io_enq_bits_data_unrecoded_rawIn_isInf}}, fp_sdq_io_enq_bits_data_unrecoded_fractOut[51:32], (&(io_req_bits_rs2_data[63:61])) ? {io_req_bits_rs2_data[31], (fp_sdq_io_enq_bits_data_prevUnrecoded_isSubnormal ? 8'h0 : io_req_bits_rs2_data[30:23] + 8'h7F) | {8{(&_fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isSpecial_T) & io_req_bits_rs2_data[29] | fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isInf}}, fp_sdq_io_enq_bits_data_prevUnrecoded_isSubnormal ? _fp_sdq_io_enq_bits_data_prevUnrecoded_denormFract_T_1[22:0] : fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isInf ? 23'h0 : io_req_bits_rs2_data[22:0]} : fp_sdq_io_enq_bits_data_unrecoded_fractOut[31:0]}),
.io_deq_ready (_resp_arb_io_in_1_ready),
.io_deq_valid (_fp_sdq_io_deq_valid),
.io_deq_bits_uop_uopc (_fp_sdq_io_deq_bits_uop_uopc),
.io_deq_bits_uop_br_mask (_fp_sdq_io_deq_bits_uop_br_mask),
.io_deq_bits_uop_rob_idx (_fp_sdq_io_deq_bits_uop_rob_idx),
.io_deq_bits_uop_stq_idx (_fp_sdq_io_deq_bits_uop_stq_idx),
.io_deq_bits_uop_pdst (_fp_sdq_io_deq_bits_uop_pdst),
.io_deq_bits_uop_is_amo (_fp_sdq_io_deq_bits_uop_is_amo),
.io_deq_bits_uop_uses_stq (_fp_sdq_io_deq_bits_uop_uses_stq),
.io_deq_bits_uop_dst_rtype (_fp_sdq_io_deq_bits_uop_dst_rtype),
.io_deq_bits_uop_fp_val (_fp_sdq_io_deq_bits_uop_fp_val),
.io_deq_bits_data (_fp_sdq_io_deq_bits_data),
.io_deq_bits_predicated (_fp_sdq_io_deq_bits_predicated),
.io_deq_bits_fflags_valid (_fp_sdq_io_deq_bits_fflags_valid),
.io_deq_bits_fflags_bits_uop_rob_idx (_fp_sdq_io_deq_bits_fflags_bits_uop_rob_idx),
.io_deq_bits_fflags_bits_flags (_fp_sdq_io_deq_bits_fflags_bits_flags),
.io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask),
.io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask),
.io_flush (io_req_bits_kill),
.io_empty (_fp_sdq_io_empty)
);
Arbiter2_ExeUnitResp resp_arb (
.io_in_0_ready (_resp_arb_io_in_0_ready),
.io_in_0_valid (_queue_io_deq_valid),
.io_in_0_bits_uop_uopc (_queue_io_deq_bits_uop_uopc),
.io_in_0_bits_uop_br_mask (_queue_io_deq_bits_uop_br_mask),
.io_in_0_bits_uop_rob_idx (_queue_io_deq_bits_uop_rob_idx),
.io_in_0_bits_uop_stq_idx (_queue_io_deq_bits_uop_stq_idx),
.io_in_0_bits_uop_pdst (_queue_io_deq_bits_uop_pdst),
.io_in_0_bits_uop_is_amo (_queue_io_deq_bits_uop_is_amo),
.io_in_0_bits_uop_uses_stq (_queue_io_deq_bits_uop_uses_stq),
.io_in_0_bits_uop_dst_rtype (_queue_io_deq_bits_uop_dst_rtype),
.io_in_0_bits_uop_fp_val (_queue_io_deq_bits_uop_fp_val),
.io_in_0_bits_data (_queue_io_deq_bits_data),
.io_in_0_bits_predicated (_queue_io_deq_bits_predicated),
.io_in_0_bits_fflags_valid (_queue_io_deq_bits_fflags_valid),
.io_in_0_bits_fflags_bits_uop_rob_idx (_queue_io_deq_bits_fflags_bits_uop_rob_idx),
.io_in_0_bits_fflags_bits_flags (_queue_io_deq_bits_fflags_bits_flags),
.io_in_1_ready (_resp_arb_io_in_1_ready),
.io_in_1_valid (_fp_sdq_io_deq_valid),
.io_in_1_bits_uop_uopc (_fp_sdq_io_deq_bits_uop_uopc),
.io_in_1_bits_uop_br_mask (_fp_sdq_io_deq_bits_uop_br_mask),
.io_in_1_bits_uop_rob_idx (_fp_sdq_io_deq_bits_uop_rob_idx),
.io_in_1_bits_uop_stq_idx (_fp_sdq_io_deq_bits_uop_stq_idx),
.io_in_1_bits_uop_pdst (_fp_sdq_io_deq_bits_uop_pdst),
.io_in_1_bits_uop_is_amo (_fp_sdq_io_deq_bits_uop_is_amo),
.io_in_1_bits_uop_uses_stq (_fp_sdq_io_deq_bits_uop_uses_stq),
.io_in_1_bits_uop_dst_rtype (_fp_sdq_io_deq_bits_uop_dst_rtype),
.io_in_1_bits_uop_fp_val (_fp_sdq_io_deq_bits_uop_fp_val),
.io_in_1_bits_data (_fp_sdq_io_deq_bits_data),
.io_in_1_bits_predicated (_fp_sdq_io_deq_bits_predicated),
.io_in_1_bits_fflags_valid (_fp_sdq_io_deq_bits_fflags_valid),
.io_in_1_bits_fflags_bits_uop_rob_idx (_fp_sdq_io_deq_bits_fflags_bits_uop_rob_idx),
.io_in_1_bits_fflags_bits_flags (_fp_sdq_io_deq_bits_fflags_bits_flags),
.io_out_ready (io_ll_iresp_ready),
.io_out_valid (io_ll_iresp_valid),
.io_out_bits_uop_uopc (io_ll_iresp_bits_uop_uopc),
.io_out_bits_uop_br_mask (io_ll_iresp_bits_uop_br_mask),
.io_out_bits_uop_rob_idx (io_ll_iresp_bits_uop_rob_idx),
.io_out_bits_uop_stq_idx (io_ll_iresp_bits_uop_stq_idx),
.io_out_bits_uop_pdst (io_ll_iresp_bits_uop_pdst),
.io_out_bits_uop_is_amo (io_ll_iresp_bits_uop_is_amo),
.io_out_bits_uop_uses_stq (io_ll_iresp_bits_uop_uses_stq),
.io_out_bits_uop_dst_rtype (io_ll_iresp_bits_uop_dst_rtype),
.io_out_bits_uop_fp_val (/* unused */),
.io_out_bits_data (io_ll_iresp_bits_data),
.io_out_bits_predicated (io_ll_iresp_bits_predicated),
.io_out_bits_fflags_valid (/* unused */),
.io_out_bits_fflags_bits_uop_rob_idx (/* unused */),
.io_out_bits_fflags_bits_flags (/* unused */)
);
assign io_fu_types = {_fpiu_busy_T, 1'h0, ~fdiv_busy, 7'h40};
assign io_fresp_valid = (_FPUUnit_io_resp_valid | _FDivSqrtUnit_io_resp_valid) & ~(_FPUUnit_io_resp_valid & _FPUUnit_io_resp_bits_uop_fu_code[9]);
assign io_fresp_bits_uop_rob_idx = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_rob_idx : _FDivSqrtUnit_io_resp_bits_uop_rob_idx;
assign io_fresp_bits_uop_pdst = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_pdst : _FDivSqrtUnit_io_resp_bits_uop_pdst;
assign io_fresp_bits_uop_is_amo = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_amo : _FDivSqrtUnit_io_resp_bits_uop_is_amo;
assign io_fresp_bits_uop_uses_ldq = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_uses_ldq : _FDivSqrtUnit_io_resp_bits_uop_uses_ldq;
assign io_fresp_bits_uop_uses_stq = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_uses_stq : _FDivSqrtUnit_io_resp_bits_uop_uses_stq;
assign io_fresp_bits_uop_dst_rtype = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_dst_rtype : _FDivSqrtUnit_io_resp_bits_uop_dst_rtype;
assign io_fresp_bits_uop_fp_val = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_fp_val : _FDivSqrtUnit_io_resp_bits_uop_fp_val;
assign io_fresp_bits_data = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_data : _FDivSqrtUnit_io_resp_bits_data;
assign io_fresp_bits_fflags_valid = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_fflags_valid : _FDivSqrtUnit_io_resp_bits_fflags_valid;
assign io_fresp_bits_fflags_bits_uop_rob_idx = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_fflags_bits_uop_rob_idx : _FDivSqrtUnit_io_resp_bits_fflags_bits_uop_rob_idx;
assign io_fresp_bits_fflags_bits_flags = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_fflags_bits_flags : _FDivSqrtUnit_io_resp_bits_fflags_bits_flags;
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(t))
val out = Decoupled(new Flit(flitWidth))
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))
data(0) := DontCare // unused, DCE this
}
}
io.busy := io.out.valid
}
class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(t)
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits := (if (dataBeats == 1) {
io.in.bits.flit.asTypeOf(t)
} else {
Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)
})
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit
}
}
}
io.busy := beat =/= 0.U
}
class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Phit(phitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail
}
}
}
object FlitToPhit {
def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {
val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))
flit2phit.io.in <> flit
flit2phit.io.out
}
}
class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Decoupled(new Flit(flitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat) := io.in.bits.phit
}
}
}
}
object PhitToFlit {
def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in <> phit
phit2flit.io.out
}
def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in.valid := phit.valid
phit2flit.io.in.bits := phit.bits
when (phit.valid) { assert(phit2flit.io.in.ready) }
val out = Wire(Valid(new Flit(flitWidth)))
out.valid := phit2flit.io.out.valid
out.bits := phit2flit.io.out.bits
phit2flit.io.out.ready := true.B
out
}
}
class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))
val out = Decoupled(new Phit(phitWidth))
})
if (channels == 1) {
io.out <> io.in(0)
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val chosen_reg = Reg(UInt(headerWidth.W))
val chosen_prio = PriorityEncoder(io.in.map(_.valid))
val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.out.valid := VecInit(io.in.map(_.valid))(chosen)
io.out.bits.phit := Mux(beat < headerBeats.U,
chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),
VecInit(io.in.map(_.bits.phit))(chosen))
for (i <- 0 until channels) {
io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U
}
when (io.out.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) { chosen_reg := chosen_prio }
}
}
}
class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Vec(channels, Decoupled(new Phit(phitWidth)))
})
if (channels == 1) {
io.out(0) <> io.in
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))
val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)
for (c <- 0 until channels) {
io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U
io.out(c).bits.phit := io.in.bits.phit
}
when (io.in.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat < headerBeats.U) {
channel_vec(header_idx) := io.in.bits.phit
}
}
}
}
class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Flipped(Decoupled(new Flit(flitWidth)))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = io.out.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)
}
io.out.valid := io.in.valid && credits < bufferSz.U
io.out.bits.flit := io.in.bits.flit
io.in.ready := io.out.ready && credits < bufferSz.U
io.credit.ready := true.B
}
class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Decoupled(new Flit(flitWidth))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = buffer.io.deq.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credit_incr + Mux(credit_decr, 0.U, credits)
}
buffer.io.enq.valid := io.in.valid
buffer.io.enq.bits := io.in.bits
io.in.ready := true.B
when (io.in.valid) { assert(buffer.io.enq.ready) }
io.out <> buffer.io.deq
io.credit.valid := credits =/= 0.U
io.credit.bits.flit := credits - 1.U
} | module GenericSerializer_TLBeatw87_f32(
input clock,
input reset,
input io_in_bits_head,
input io_in_bits_tail,
input io_out_ready,
output io_out_valid,
output [31:0] io_out_bits_flit
);
wire [0:0][31:0] _GEN = '{32'h0};
reg [31:0] data_1;
reg [31:0] data_2;
reg [1:0] beat;
wire _io_out_bits_flit_T = beat == 2'h0;
wire [3:0][31:0] _GEN_0 = {_GEN, {{data_2}, {data_1}, {32'h0}}};
wire _GEN_1 = io_out_ready & (|beat);
always @(posedge clock) begin
if (_GEN_1 & _io_out_bits_flit_T) begin
data_1 <= 32'h0;
data_2 <= 32'h0;
end
if (reset)
beat <= 2'h0;
else if (_GEN_1)
beat <= beat == 2'h2 ? 2'h0 : beat + 2'h1;
end
assign io_out_valid = |beat;
assign io_out_bits_flit = _io_out_bits_flit_T ? {30'h0, io_in_bits_head, io_in_bits_tail} : _GEN_0[beat];
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(t))
val out = Decoupled(new Flit(flitWidth))
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))
data(0) := DontCare // unused, DCE this
}
}
io.busy := io.out.valid
}
class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(t)
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits := (if (dataBeats == 1) {
io.in.bits.flit.asTypeOf(t)
} else {
Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)
})
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit
}
}
}
io.busy := beat =/= 0.U
}
class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Phit(phitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail
}
}
}
object FlitToPhit {
def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {
val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))
flit2phit.io.in <> flit
flit2phit.io.out
}
}
class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Decoupled(new Flit(flitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat) := io.in.bits.phit
}
}
}
}
object PhitToFlit {
def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in <> phit
phit2flit.io.out
}
def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in.valid := phit.valid
phit2flit.io.in.bits := phit.bits
when (phit.valid) { assert(phit2flit.io.in.ready) }
val out = Wire(Valid(new Flit(flitWidth)))
out.valid := phit2flit.io.out.valid
out.bits := phit2flit.io.out.bits
phit2flit.io.out.ready := true.B
out
}
}
class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))
val out = Decoupled(new Phit(phitWidth))
})
if (channels == 1) {
io.out <> io.in(0)
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val chosen_reg = Reg(UInt(headerWidth.W))
val chosen_prio = PriorityEncoder(io.in.map(_.valid))
val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.out.valid := VecInit(io.in.map(_.valid))(chosen)
io.out.bits.phit := Mux(beat < headerBeats.U,
chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),
VecInit(io.in.map(_.bits.phit))(chosen))
for (i <- 0 until channels) {
io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U
}
when (io.out.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) { chosen_reg := chosen_prio }
}
}
}
class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Vec(channels, Decoupled(new Phit(phitWidth)))
})
if (channels == 1) {
io.out(0) <> io.in
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))
val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)
for (c <- 0 until channels) {
io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U
io.out(c).bits.phit := io.in.bits.phit
}
when (io.in.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat < headerBeats.U) {
channel_vec(header_idx) := io.in.bits.phit
}
}
}
}
class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Flipped(Decoupled(new Flit(flitWidth)))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = io.out.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)
}
io.out.valid := io.in.valid && credits < bufferSz.U
io.out.bits.flit := io.in.bits.flit
io.in.ready := io.out.ready && credits < bufferSz.U
io.credit.ready := true.B
}
class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Decoupled(new Flit(flitWidth))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = buffer.io.deq.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credit_incr + Mux(credit_decr, 0.U, credits)
}
buffer.io.enq.valid := io.in.valid
buffer.io.enq.bits := io.in.bits
io.in.ready := true.B
when (io.in.valid) { assert(buffer.io.enq.ready) }
io.out <> buffer.io.deq
io.credit.valid := credits =/= 0.U
io.credit.bits.flit := credits - 1.U
} | module GenericSerializer_TLBeatw10_f32(
input io_in_bits_head,
output [31:0] io_out_bits_flit
);
assign io_out_bits_flit = {30'h0, io_in_bits_head, 1'h1};
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(t))
val out = Decoupled(new Flit(flitWidth))
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))
data(0) := DontCare // unused, DCE this
}
}
io.busy := io.out.valid
}
class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(t)
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits := (if (dataBeats == 1) {
io.in.bits.flit.asTypeOf(t)
} else {
Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)
})
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit
}
}
}
io.busy := beat =/= 0.U
}
class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Phit(phitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail
}
}
}
object FlitToPhit {
def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {
val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))
flit2phit.io.in <> flit
flit2phit.io.out
}
}
class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Decoupled(new Flit(flitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat) := io.in.bits.phit
}
}
}
}
object PhitToFlit {
def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in <> phit
phit2flit.io.out
}
def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in.valid := phit.valid
phit2flit.io.in.bits := phit.bits
when (phit.valid) { assert(phit2flit.io.in.ready) }
val out = Wire(Valid(new Flit(flitWidth)))
out.valid := phit2flit.io.out.valid
out.bits := phit2flit.io.out.bits
phit2flit.io.out.ready := true.B
out
}
}
class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))
val out = Decoupled(new Phit(phitWidth))
})
if (channels == 1) {
io.out <> io.in(0)
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val chosen_reg = Reg(UInt(headerWidth.W))
val chosen_prio = PriorityEncoder(io.in.map(_.valid))
val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.out.valid := VecInit(io.in.map(_.valid))(chosen)
io.out.bits.phit := Mux(beat < headerBeats.U,
chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),
VecInit(io.in.map(_.bits.phit))(chosen))
for (i <- 0 until channels) {
io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U
}
when (io.out.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) { chosen_reg := chosen_prio }
}
}
}
class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Vec(channels, Decoupled(new Phit(phitWidth)))
})
if (channels == 1) {
io.out(0) <> io.in
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))
val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)
for (c <- 0 until channels) {
io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U
io.out(c).bits.phit := io.in.bits.phit
}
when (io.in.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat < headerBeats.U) {
channel_vec(header_idx) := io.in.bits.phit
}
}
}
}
class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Flipped(Decoupled(new Flit(flitWidth)))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = io.out.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)
}
io.out.valid := io.in.valid && credits < bufferSz.U
io.out.bits.flit := io.in.bits.flit
io.in.ready := io.out.ready && credits < bufferSz.U
io.credit.ready := true.B
}
class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Decoupled(new Flit(flitWidth))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = buffer.io.deq.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credit_incr + Mux(credit_decr, 0.U, credits)
}
buffer.io.enq.valid := io.in.valid
buffer.io.enq.bits := io.in.bits
io.in.ready := true.B
when (io.in.valid) { assert(buffer.io.enq.ready) }
io.out <> buffer.io.deq
io.credit.valid := credits =/= 0.U
io.credit.bits.flit := credits - 1.U
} | module GenericSerializer_TLBeatw67_f32(
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [64:0] io_in_bits_payload,
input io_in_bits_head,
input io_in_bits_tail,
input io_out_ready,
output io_out_valid,
output [31:0] io_out_bits_flit
);
wire [0:0][31:0] _GEN = '{32'h0};
reg [31:0] data_1;
reg [31:0] data_2;
reg [1:0] beat;
wire _io_out_bits_flit_T = beat == 2'h0;
wire [2:0] _GEN_0 = {io_in_valid, beat};
wire [3:0][31:0] _GEN_1 = {_GEN, {{data_2}, {data_1}, {32'h0}}};
wire _GEN_2 = io_out_ready & (|_GEN_0);
always @(posedge clock) begin
if (_GEN_2 & _io_out_bits_flit_T) begin
data_1 <= io_in_bits_payload[61:30];
data_2 <= {29'h0, io_in_bits_payload[64:62]};
end
if (reset)
beat <= 2'h0;
else if (_GEN_2)
beat <= beat == 2'h2 ? 2'h0 : beat + 2'h1;
end
assign io_in_ready = io_out_ready & _io_out_bits_flit_T;
assign io_out_valid = |_GEN_0;
assign io_out_bits_flit = _io_out_bits_flit_T ? {io_in_bits_payload[29:0], io_in_bits_head, io_in_bits_tail} : _GEN_1[beat];
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Decoupled,log2Ceil,Cat,UIntToOH,Fill}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
class Instruction(implicit val p: Parameters) extends ParameterizedBundle with HasCoreParameters {
val xcpt0 = new FrontendExceptions // exceptions on first half of instruction
val xcpt1 = new FrontendExceptions // exceptions on second half of instruction
val replay = Bool()
val rvc = Bool()
val inst = new ExpandedInstruction
val raw = UInt(32.W)
require(coreInstBits == (if (usingCompressed) 16 else 32))
}
class IBuf(implicit p: Parameters) extends CoreModule {
val io = IO(new Bundle {
val imem = Flipped(Decoupled(new FrontendResp))
val kill = Input(Bool())
val pc = Output(UInt(vaddrBitsExtended.W))
val btb_resp = Output(new BTBResp())
val inst = Vec(retireWidth, Decoupled(new Instruction))
})
// This module is meant to be more general, but it's not there yet
require(decodeWidth == 1)
val n = fetchWidth - 1
val nBufValid = if (n == 0) 0.U else RegInit(init=0.U(log2Ceil(fetchWidth).W))
val buf = Reg(chiselTypeOf(io.imem.bits))
val ibufBTBResp = Reg(new BTBResp)
val pcWordMask = (coreInstBytes*fetchWidth-1).U(vaddrBitsExtended.W)
val pcWordBits = io.imem.bits.pc.extract(log2Ceil(fetchWidth*coreInstBytes)-1, log2Ceil(coreInstBytes))
val nReady = WireDefault(0.U(log2Ceil(fetchWidth+1).W))
val nIC = Mux(io.imem.bits.btb.taken, io.imem.bits.btb.bridx +& 1.U, fetchWidth.U) - pcWordBits
val nICReady = nReady - nBufValid
val nValid = Mux(io.imem.valid, nIC, 0.U) + nBufValid
io.imem.ready := io.inst(0).ready && nReady >= nBufValid && (nICReady >= nIC || n.U >= nIC - nICReady)
if (n > 0) {
when (io.inst(0).ready) {
nBufValid := Mux(nReady >== nBufValid, 0.U, nBufValid - nReady)
if (n > 1) when (nReady > 0.U && nReady < nBufValid) {
val shiftedBuf = shiftInsnRight(buf.data(n*coreInstBits-1, coreInstBits), (nReady-1.U)(log2Ceil(n-1)-1,0))
buf.data := Cat(buf.data(n*coreInstBits-1, (n-1)*coreInstBits), shiftedBuf((n-1)*coreInstBits-1, 0))
buf.pc := buf.pc & ~pcWordMask | (buf.pc + (nReady << log2Ceil(coreInstBytes))) & pcWordMask
}
when (io.imem.valid && nReady >= nBufValid && nICReady < nIC && n.U >= nIC - nICReady) {
val shamt = pcWordBits + nICReady
nBufValid := nIC - nICReady
buf := io.imem.bits
buf.data := shiftInsnRight(io.imem.bits.data, shamt)(n*coreInstBits-1,0)
buf.pc := io.imem.bits.pc & ~pcWordMask | (io.imem.bits.pc + (nICReady << log2Ceil(coreInstBytes))) & pcWordMask
ibufBTBResp := io.imem.bits.btb
}
}
when (io.kill) {
nBufValid := 0.U
}
}
val icShiftAmt = (fetchWidth.U + nBufValid - pcWordBits)(log2Ceil(fetchWidth), 0)
val icData = shiftInsnLeft(Cat(io.imem.bits.data, Fill(fetchWidth, io.imem.bits.data(coreInstBits-1, 0))), icShiftAmt)
.extract(3*fetchWidth*coreInstBits-1, 2*fetchWidth*coreInstBits)
val icMask = (~0.U((fetchWidth*coreInstBits).W) << (nBufValid << log2Ceil(coreInstBits)))(fetchWidth*coreInstBits-1,0)
val inst = icData & icMask | buf.data & ~icMask
val valid = (UIntToOH(nValid) - 1.U)(fetchWidth-1, 0)
val bufMask = UIntToOH(nBufValid) - 1.U
val xcpt = (0 until bufMask.getWidth).map(i => Mux(bufMask(i), buf.xcpt, io.imem.bits.xcpt))
val buf_replay = Mux(buf.replay, bufMask, 0.U)
val ic_replay = buf_replay | Mux(io.imem.bits.replay, valid & ~bufMask, 0.U)
assert(!io.imem.valid || !io.imem.bits.btb.taken || io.imem.bits.btb.bridx >= pcWordBits)
io.btb_resp := io.imem.bits.btb
io.pc := Mux(nBufValid > 0.U, buf.pc, io.imem.bits.pc)
expand(0, 0.U, inst)
def expand(i: Int, j: UInt, curInst: UInt): Unit = if (i < retireWidth) {
val exp = Module(new RVCExpander)
exp.io.in := curInst
io.inst(i).bits.inst := exp.io.out
io.inst(i).bits.raw := curInst
if (usingCompressed) {
val replay = ic_replay(j) || (!exp.io.rvc && ic_replay(j+1.U))
val full_insn = exp.io.rvc || valid(j+1.U) || buf_replay(j)
io.inst(i).valid := valid(j) && full_insn
io.inst(i).bits.xcpt0 := xcpt(j)
io.inst(i).bits.xcpt1 := Mux(exp.io.rvc, 0.U, xcpt(j+1.U).asUInt).asTypeOf(new FrontendExceptions)
io.inst(i).bits.replay := replay
io.inst(i).bits.rvc := exp.io.rvc
when ((bufMask(j) && exp.io.rvc) || bufMask(j+1.U)) { io.btb_resp := ibufBTBResp }
when (full_insn && ((i == 0).B || io.inst(i).ready)) { nReady := Mux(exp.io.rvc, j+1.U, j+2.U) }
expand(i+1, Mux(exp.io.rvc, j+1.U, j+2.U), Mux(exp.io.rvc, curInst >> 16, curInst >> 32))
} else {
when ((i == 0).B || io.inst(i).ready) { nReady := (i+1).U }
io.inst(i).valid := valid(i)
io.inst(i).bits.xcpt0 := xcpt(i)
io.inst(i).bits.xcpt1 := 0.U.asTypeOf(new FrontendExceptions)
io.inst(i).bits.replay := ic_replay(i)
io.inst(i).bits.rvc := false.B
expand(i+1, null, curInst >> 32)
}
}
def shiftInsnLeft(in: UInt, dist: UInt) = {
val r = in.getWidth/coreInstBits
require(in.getWidth % coreInstBits == 0)
val data = Cat(Fill((1 << (log2Ceil(r) + 1)) - r, in >> (r-1)*coreInstBits), in)
data << (dist << log2Ceil(coreInstBits))
}
def shiftInsnRight(in: UInt, dist: UInt) = {
val r = in.getWidth/coreInstBits
require(in.getWidth % coreInstBits == 0)
val data = Cat(Fill((1 << (log2Ceil(r) + 1)) - r, in >> (r-1)*coreInstBits), in)
data >> (dist << log2Ceil(coreInstBits))
}
} | module IBuf(
input clock,
input reset,
output io_imem_ready,
input io_imem_valid,
input io_imem_bits_btb_taken,
input io_imem_bits_btb_bridx,
input [4:0] io_imem_bits_btb_entry,
input [7:0] io_imem_bits_btb_bht_history,
input [39:0] io_imem_bits_pc,
input [31:0] io_imem_bits_data,
input io_imem_bits_xcpt_pf_inst,
input io_imem_bits_xcpt_gf_inst,
input io_imem_bits_xcpt_ae_inst,
input io_imem_bits_replay,
input io_kill,
output [39:0] io_pc,
output [4:0] io_btb_resp_entry,
output [7:0] io_btb_resp_bht_history,
input io_inst_0_ready,
output io_inst_0_valid,
output io_inst_0_bits_xcpt0_pf_inst,
output io_inst_0_bits_xcpt0_gf_inst,
output io_inst_0_bits_xcpt0_ae_inst,
output io_inst_0_bits_xcpt1_pf_inst,
output io_inst_0_bits_xcpt1_gf_inst,
output io_inst_0_bits_xcpt1_ae_inst,
output io_inst_0_bits_replay,
output io_inst_0_bits_rvc,
output [31:0] io_inst_0_bits_inst_bits,
output [4:0] io_inst_0_bits_inst_rd,
output [4:0] io_inst_0_bits_inst_rs1,
output [4:0] io_inst_0_bits_inst_rs2,
output [4:0] io_inst_0_bits_inst_rs3,
output [31:0] io_inst_0_bits_raw
);
wire [1:0] nReady;
wire _exp_io_rvc;
reg nBufValid;
reg [39:0] buf_pc;
reg [31:0] buf_data;
reg buf_xcpt_pf_inst;
reg buf_xcpt_gf_inst;
reg buf_xcpt_ae_inst;
reg buf_replay;
reg [4:0] ibufBTBResp_entry;
reg [7:0] ibufBTBResp_bht_history;
wire [1:0] _GEN = {1'h0, io_imem_bits_pc[1]};
wire [1:0] _nIC_T_2 = (io_imem_bits_btb_taken ? {1'h0, io_imem_bits_btb_bridx} + 2'h1 : 2'h2) - _GEN;
wire [1:0] _GEN_0 = {1'h0, nBufValid};
wire [1:0] _nICReady_T = nReady - _GEN_0;
wire _nBufValid_T = nReady >= _GEN_0;
wire [1:0] _nBufValid_T_6 = _nIC_T_2 - _nICReady_T;
wire [190:0] _icData_T_4 = {63'h0, {2{{2{io_imem_bits_data[31:16]}}}}, io_imem_bits_data, {2{io_imem_bits_data[15:0]}}} << {185'h0, _GEN_0 - 2'h2 - _GEN, 4'h0};
wire [62:0] _icMask_T_2 = 63'hFFFFFFFF << {58'h0, nBufValid, 4'h0};
wire [31:0] inst = _icData_T_4[95:64] & _icMask_T_2[31:0] | buf_data & ~(_icMask_T_2[31:0]);
wire [3:0] _valid_T = 4'h1 << (io_imem_valid ? _nIC_T_2 : 2'h0) + _GEN_0;
wire [1:0] _valid_T_1 = _valid_T[1:0] - 2'h1;
wire [1:0] _bufMask_T_1 = (2'h1 << _GEN_0) - 2'h1;
wire [1:0] buf_replay_0 = buf_replay ? _bufMask_T_1 : 2'h0;
wire [1:0] ic_replay = buf_replay_0 | (io_imem_bits_replay ? _valid_T_1 & ~_bufMask_T_1 : 2'h0);
wire full_insn = _exp_io_rvc | _valid_T_1[1] | buf_replay_0[0];
wire [2:0] _io_inst_0_bits_xcpt1_T_5 = _exp_io_rvc ? 3'h0 : {_bufMask_T_1[1] ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst, _bufMask_T_1[1] ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst, _bufMask_T_1[1] ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst};
wire _GEN_1 = _bufMask_T_1[0] & _exp_io_rvc | _bufMask_T_1[1];
assign nReady = full_insn ? (_exp_io_rvc ? 2'h1 : 2'h2) : 2'h0;
wire [63:0] _buf_data_T_1 = {{2{io_imem_bits_data[31:16]}}, io_imem_bits_data} >> {58'h0, _GEN + _nICReady_T, 4'h0};
wire _GEN_2 = io_imem_valid & _nBufValid_T & _nICReady_T < _nIC_T_2 & ~(_nBufValid_T_6[1]);
always @(posedge clock) begin
if (reset)
nBufValid <= 1'h0;
else
nBufValid <= ~io_kill & (io_inst_0_ready ? (_GEN_2 ? _nBufValid_T_6[0] : ~(_nBufValid_T | ~nBufValid) & nBufValid - nReady[0]) : nBufValid);
if (io_inst_0_ready & _GEN_2) begin
buf_pc <= io_imem_bits_pc & 40'hFFFFFFFFFC | io_imem_bits_pc + {37'h0, _nICReady_T, 1'h0} & 40'h3;
buf_data <= {16'h0, _buf_data_T_1[15:0]};
buf_xcpt_pf_inst <= io_imem_bits_xcpt_pf_inst;
buf_xcpt_gf_inst <= io_imem_bits_xcpt_gf_inst;
buf_xcpt_ae_inst <= io_imem_bits_xcpt_ae_inst;
buf_replay <= io_imem_bits_replay;
ibufBTBResp_entry <= io_imem_bits_btb_entry;
ibufBTBResp_bht_history <= io_imem_bits_btb_bht_history;
end
end
RVCExpander exp (
.io_in (inst),
.io_out_bits (io_inst_0_bits_inst_bits),
.io_out_rd (io_inst_0_bits_inst_rd),
.io_out_rs1 (io_inst_0_bits_inst_rs1),
.io_out_rs2 (io_inst_0_bits_inst_rs2),
.io_out_rs3 (io_inst_0_bits_inst_rs3),
.io_rvc (_exp_io_rvc)
);
assign io_imem_ready = io_inst_0_ready & _nBufValid_T & (_nICReady_T >= _nIC_T_2 | ~(_nBufValid_T_6[1]));
assign io_pc = nBufValid ? buf_pc : io_imem_bits_pc;
assign io_btb_resp_entry = _GEN_1 ? ibufBTBResp_entry : io_imem_bits_btb_entry;
assign io_btb_resp_bht_history = _GEN_1 ? ibufBTBResp_bht_history : io_imem_bits_btb_bht_history;
assign io_inst_0_valid = _valid_T_1[0] & full_insn;
assign io_inst_0_bits_xcpt0_pf_inst = _bufMask_T_1[0] ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst;
assign io_inst_0_bits_xcpt0_gf_inst = _bufMask_T_1[0] ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst;
assign io_inst_0_bits_xcpt0_ae_inst = _bufMask_T_1[0] ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst;
assign io_inst_0_bits_xcpt1_pf_inst = _io_inst_0_bits_xcpt1_T_5[2];
assign io_inst_0_bits_xcpt1_gf_inst = _io_inst_0_bits_xcpt1_T_5[1];
assign io_inst_0_bits_xcpt1_ae_inst = _io_inst_0_bits_xcpt1_T_5[0];
assign io_inst_0_bits_replay = ic_replay[0] | ~_exp_io_rvc & ic_replay[1];
assign io_inst_0_bits_rvc = _exp_io_rvc;
assign io_inst_0_bits_raw = inst;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2017 SiFive, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of SiFive nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY SIFIVE AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL SIFIVE OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*
s = sigWidth
c_i = newBit
Division:
width of a is (s+2)
Normal
------
(qi + ci * 2^(-i))*b <= a
q0 = 0
r0 = a
q(i+1) = qi + ci*2^(-i)
ri = a - qi*b
r(i+1) = a - q(i+1)*b
= a - qi*b - ci*2^(-i)*b
r(i+1) = ri - ci*2^(-i)*b
ci = ri >= 2^(-i)*b
summary_i = ri != 0
i = 0 to s+1
(s+1)th bit plus summary_(i+1) gives enough information for rounding
If (a < b), then we need to calculate (s+2)th bit and summary_(i+1)
because we need s bits ignoring the leading zero. (This is skipCycle2
part of Hauser's code.)
Hauser
------
sig_i = qi
rem_i = 2^(i-2)*ri
cycle_i = s+3-i
sig_0 = 0
rem_0 = a/4
cycle_0 = s+3
bit_0 = 2^0 (= 2^(s+1), since we represent a, b and q with (s+2) bits)
sig(i+1) = sig(i) + ci*bit_i
rem(i+1) = 2rem_i - ci*b/2
ci = 2rem_i >= b/2
bit_i = 2^-i (=2^(cycle_i-2), since we represent a, b and q with (s+2) bits)
cycle(i+1) = cycle_i-1
summary_1 = a <> b
summary(i+1) = if ci then 2rem_i-b/2 <> 0 else summary_i, i <> 0
Proof:
2^i*r(i+1) = 2^i*ri - ci*b. Qed
ci = 2^i*ri >= b. Qed
summary(i+1) = if ci then rem(i+1) else summary_i, i <> 0
Now, note that all of ck's cannot be 0, since that means
a is 0. So when you traverse through a chain of 0 ck's,
from the end,
eventually, you reach a non-zero cj. That is exactly the
value of ri as the reminder remains the same. When all ck's
are 0 except c0 (which must be 1) then summary_1 is set
correctly according
to r1 = a-b != 0. So summary(i+1) is always set correctly
according to r(i+1)
Square root:
width of a is (s+1)
Normal
------
(xi + ci*2^(-i))^2 <= a
xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)) <= a
x0 = 0
x(i+1) = xi + ci*2^(-i)
ri = a - xi^2
r(i+1) = a - x(i+1)^2
= a - (xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)))
= ri - ci*2^(-i)*(2xi+ci*2^(-i))
= ri - ci*2^(-i)*(2xi+2^(-i)) // ci is always 0 or 1
ci = ri >= 2^(-i)*(2xi + 2^(-i))
summary_i = ri != 0
i = 0 to s+1
For odd expression, do 2 steps initially.
(s+1)th bit plus summary_(i+1) gives enough information for rounding.
Hauser
------
sig_i = xi
rem_i = ri*2^(i-1)
cycle_i = s+2-i
bit_i = 2^(-i) (= 2^(s-i) = 2^(cycle_i-2) in terms of bit representation)
sig_0 = 0
rem_0 = a/2
cycle_0 = s+2
bit_0 = 1 (= 2^s in terms of bit representation)
sig(i+1) = sig_i + ci * bit_i
rem(i+1) = 2rem_i - ci*(2sig_i + bit_i)
ci = 2*sig_i + bit_i <= 2*rem_i
bit_i = 2^(cycle_i-2) (in terms of bit representation)
cycle(i+1) = cycle_i-1
summary_1 = a - (2^s) (in terms of bit representation)
summary(i+1) = if ci then rem(i+1) <> 0 else summary_i, i <> 0
Proof:
ci = 2*sig_i + bit_i <= 2*rem_i
ci = 2xi + 2^(-i) <= ri*2^i. Qed
sig(i+1) = sig_i + ci * bit_i
x(i+1) = xi + ci*2^(-i). Qed
rem(i+1) = 2rem_i - ci*(2sig_i + bit_i)
r(i+1)*2^i = ri*2^i - ci*(2xi + 2^(-i))
r(i+1) = ri - ci*2^(-i)*(2xi + 2^(-i)). Qed
Same argument as before for summary.
------------------------------
Note that all registers are updated normally until cycle == 2.
At cycle == 2, rem is not updated, but all other registers are updated normally.
But, cycle == 1 does not read rem to calculate anything (note that final summary
is calculated using the values at cycle = 2).
*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
/*----------------------------------------------------------------------------
| Computes a division or square root for floating-point in recoded form.
| Multiple clock cycles are needed for each division or square-root operation,
| except possibly in special cases.
*----------------------------------------------------------------------------*/
class
DivSqrtRawFN_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRawFN_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(new RawFloat(expWidth, sigWidth))
val b = Input(new RawFloat(expWidth, sigWidth))
val roundingMode = Input(UInt(3.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val rawOutValid_div = Output(Bool())
val rawOutValid_sqrt = Output(Bool())
val roundingModeOut = Output(UInt(3.W))
val invalidExc = Output(Bool())
val infiniteExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val cycleNum = RegInit(0.U(log2Ceil(sigWidth + 3).W))
val inReady = RegInit(true.B) // <-> (cycleNum <= 1)
val rawOutValid = RegInit(false.B) // <-> (cycleNum === 1)
val sqrtOp_Z = Reg(Bool())
val majorExc_Z = Reg(Bool())
//*** REDUCE 3 BITS TO 2-BIT CODE:
val isNaN_Z = Reg(Bool())
val isInf_Z = Reg(Bool())
val isZero_Z = Reg(Bool())
val sign_Z = Reg(Bool())
val sExp_Z = Reg(SInt((expWidth + 2).W))
val fractB_Z = Reg(UInt(sigWidth.W))
val roundingMode_Z = Reg(UInt(3.W))
/*------------------------------------------------------------------------
| (The most-significant and least-significant bits of 'rem_Z' are needed
| only for square roots.)
*------------------------------------------------------------------------*/
val rem_Z = Reg(UInt((sigWidth + 2).W))
val notZeroRem_Z = Reg(Bool())
val sigX_Z = Reg(UInt((sigWidth + 2).W))
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val rawA_S = io.a
val rawB_S = io.b
//*** IMPROVE THESE:
val notSigNaNIn_invalidExc_S_div =
(rawA_S.isZero && rawB_S.isZero) || (rawA_S.isInf && rawB_S.isInf)
val notSigNaNIn_invalidExc_S_sqrt =
! rawA_S.isNaN && ! rawA_S.isZero && rawA_S.sign
val majorExc_S =
Mux(io.sqrtOp,
isSigNaNRawFloat(rawA_S) || notSigNaNIn_invalidExc_S_sqrt,
isSigNaNRawFloat(rawA_S) || isSigNaNRawFloat(rawB_S) ||
notSigNaNIn_invalidExc_S_div ||
(! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero)
)
val isNaN_S =
Mux(io.sqrtOp,
rawA_S.isNaN || notSigNaNIn_invalidExc_S_sqrt,
rawA_S.isNaN || rawB_S.isNaN || notSigNaNIn_invalidExc_S_div
)
val isInf_S = Mux(io.sqrtOp, rawA_S.isInf, rawA_S.isInf || rawB_S.isZero)
val isZero_S = Mux(io.sqrtOp, rawA_S.isZero, rawA_S.isZero || rawB_S.isInf)
val sign_S = rawA_S.sign ^ (! io.sqrtOp && rawB_S.sign)
val specialCaseA_S = rawA_S.isNaN || rawA_S.isInf || rawA_S.isZero
val specialCaseB_S = rawB_S.isNaN || rawB_S.isInf || rawB_S.isZero
val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S
val normalCase_S_sqrt = ! specialCaseA_S && ! rawA_S.sign
val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)
val sExpQuot_S_div =
rawA_S.sExp +&
Cat(rawB_S.sExp(expWidth), ~rawB_S.sExp(expWidth - 1, 0)).asSInt
//*** IS THIS OPTIMAL?:
val sSatExpQuot_S_div =
Cat(Mux(((BigInt(7)<<(expWidth - 2)).S <= sExpQuot_S_div),
6.U,
sExpQuot_S_div(expWidth + 1, expWidth - 2)
),
sExpQuot_S_div(expWidth - 3, 0)
).asSInt
val evenSqrt_S = io.sqrtOp && ! rawA_S.sExp(0)
val oddSqrt_S = io.sqrtOp && rawA_S.sExp(0)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val idle = cycleNum === 0.U
val entering = inReady && io.inValid
val entering_normalCase = entering && normalCase_S
val processTwoBits = cycleNum >= 3.U && ((options & divSqrtOpt_twoBitsPerCycle) != 0).B
val skipCycle2 = cycleNum === 3.U && sigX_Z(sigWidth + 1) && ((options & divSqrtOpt_twoBitsPerCycle) == 0).B
when (! idle || entering) {
def computeCycleNum(f: UInt => UInt): UInt = {
Mux(entering & ! normalCase_S, f(1.U), 0.U) |
Mux(entering_normalCase,
Mux(io.sqrtOp,
Mux(rawA_S.sExp(0), f(sigWidth.U), f((sigWidth + 1).U)),
f((sigWidth + 2).U)
),
0.U
) |
Mux(! entering && ! skipCycle2, f(cycleNum - Mux(processTwoBits, 2.U, 1.U)), 0.U) |
Mux(skipCycle2, f(1.U), 0.U)
}
inReady := computeCycleNum(_ <= 1.U).asBool
rawOutValid := computeCycleNum(_ === 1.U).asBool
cycleNum := computeCycleNum(x => x)
}
io.inReady := inReady
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
when (entering) {
sqrtOp_Z := io.sqrtOp
majorExc_Z := majorExc_S
isNaN_Z := isNaN_S
isInf_Z := isInf_S
isZero_Z := isZero_S
sign_Z := sign_S
sExp_Z :=
Mux(io.sqrtOp,
(rawA_S.sExp>>1) +& (BigInt(1)<<(expWidth - 1)).S,
sSatExpQuot_S_div
)
roundingMode_Z := io.roundingMode
}
when (entering || ! inReady && sqrtOp_Z) {
fractB_Z :=
Mux(inReady && ! io.sqrtOp, rawB_S.sig(sigWidth - 2, 0)<<1, 0.U) |
Mux(inReady && io.sqrtOp && rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 2)).U, 0.U) |
Mux(inReady && io.sqrtOp && ! rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 1)).U, 0.U) |
Mux(! inReady /* sqrtOp_Z */ && processTwoBits, fractB_Z>>2, 0.U) |
Mux(! inReady /* sqrtOp_Z */ && ! processTwoBits, fractB_Z>>1, 0.U)
}
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val rem =
Mux(inReady && ! oddSqrt_S, rawA_S.sig<<1, 0.U) |
Mux(inReady && oddSqrt_S,
Cat(rawA_S.sig(sigWidth - 1, sigWidth - 2) - 1.U,
rawA_S.sig(sigWidth - 3, 0)<<3
),
0.U
) |
Mux(! inReady, rem_Z<<1, 0.U)
val bitMask = (1.U<<cycleNum)>>2
val trialTerm =
Mux(inReady && ! io.sqrtOp, rawB_S.sig<<1, 0.U) |
Mux(inReady && evenSqrt_S, (BigInt(1)<<sigWidth).U, 0.U) |
Mux(inReady && oddSqrt_S, (BigInt(5)<<(sigWidth - 1)).U, 0.U) |
Mux(! inReady, fractB_Z, 0.U) |
Mux(! inReady && ! sqrtOp_Z, 1.U << sigWidth, 0.U) |
Mux(! inReady && sqrtOp_Z, sigX_Z<<1, 0.U)
val trialRem = rem.zext -& trialTerm.zext
val newBit = (0.S <= trialRem)
val nextRem_Z = Mux(newBit, trialRem.asUInt, rem)(sigWidth + 1, 0)
val rem2 = nextRem_Z<<1
val trialTerm2_newBit0 = Mux(sqrtOp_Z, fractB_Z>>1 | sigX_Z<<1, fractB_Z | (1.U << sigWidth))
val trialTerm2_newBit1 = trialTerm2_newBit0 | Mux(sqrtOp_Z, fractB_Z<<1, 0.U)
val trialRem2 =
Mux(newBit,
(trialRem<<1) - trialTerm2_newBit1.zext,
(rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext)
val newBit2 = (0.S <= trialRem2)
val nextNotZeroRem_Z = Mux(inReady || newBit, trialRem =/= 0.S, notZeroRem_Z)
val nextNotZeroRem_Z_2 = // <-> Mux(newBit2, trialRem2 =/= 0.S, nextNotZeroRem_Z)
processTwoBits && newBit && (0.S < (trialRem<<1) - trialTerm2_newBit1.zext) ||
processTwoBits && !newBit && (0.S < (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) ||
!(processTwoBits && newBit2) && nextNotZeroRem_Z
val nextRem_Z_2 =
Mux(processTwoBits && newBit2, trialRem2.asUInt(sigWidth + 1, 0), 0.U) |
Mux(processTwoBits && !newBit2, rem2(sigWidth + 1, 0), 0.U) |
Mux(!processTwoBits, nextRem_Z, 0.U)
when (entering || ! inReady) {
notZeroRem_Z := nextNotZeroRem_Z_2
rem_Z := nextRem_Z_2
sigX_Z :=
Mux(inReady && ! io.sqrtOp, newBit<<(sigWidth + 1), 0.U) |
Mux(inReady && io.sqrtOp, (BigInt(1)<<sigWidth).U, 0.U) |
Mux(inReady && oddSqrt_S, newBit<<(sigWidth - 1), 0.U) |
Mux(! inReady, sigX_Z, 0.U) |
Mux(! inReady && newBit, bitMask, 0.U) |
Mux(processTwoBits && newBit2, bitMask>>1, 0.U)
}
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
io.rawOutValid_div := rawOutValid && ! sqrtOp_Z
io.rawOutValid_sqrt := rawOutValid && sqrtOp_Z
io.roundingModeOut := roundingMode_Z
io.invalidExc := majorExc_Z && isNaN_Z
io.infiniteExc := majorExc_Z && ! isNaN_Z
io.rawOut.isNaN := isNaN_Z
io.rawOut.isInf := isInf_Z
io.rawOut.isZero := isZero_Z
io.rawOut.sign := sign_Z
io.rawOut.sExp := sExp_Z
io.rawOut.sig := sigX_Z<<1 | notZeroRem_Z
}
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
class
DivSqrtRecFNToRaw_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRecFMToRaw_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val rawOutValid_div = Output(Bool())
val rawOutValid_sqrt = Output(Bool())
val roundingModeOut = Output(UInt(3.W))
val invalidExc = Output(Bool())
val infiniteExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
val divSqrtRawFN =
Module(new DivSqrtRawFN_small(expWidth, sigWidth, options))
io.inReady := divSqrtRawFN.io.inReady
divSqrtRawFN.io.inValid := io.inValid
divSqrtRawFN.io.sqrtOp := io.sqrtOp
divSqrtRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a)
divSqrtRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b)
divSqrtRawFN.io.roundingMode := io.roundingMode
io.rawOutValid_div := divSqrtRawFN.io.rawOutValid_div
io.rawOutValid_sqrt := divSqrtRawFN.io.rawOutValid_sqrt
io.roundingModeOut := divSqrtRawFN.io.roundingModeOut
io.invalidExc := divSqrtRawFN.io.invalidExc
io.infiniteExc := divSqrtRawFN.io.infiniteExc
io.rawOut := divSqrtRawFN.io.rawOut
}
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
class
DivSqrtRecFN_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRecFM_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val outValid_div = Output(Bool())
val outValid_sqrt = Output(Bool())
val out = Output(UInt((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(UInt(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val divSqrtRecFNToRaw =
Module(new DivSqrtRecFNToRaw_small(expWidth, sigWidth, options))
io.inReady := divSqrtRecFNToRaw.io.inReady
divSqrtRecFNToRaw.io.inValid := io.inValid
divSqrtRecFNToRaw.io.sqrtOp := io.sqrtOp
divSqrtRecFNToRaw.io.a := io.a
divSqrtRecFNToRaw.io.b := io.b
divSqrtRecFNToRaw.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.outValid_div := divSqrtRecFNToRaw.io.rawOutValid_div
io.outValid_sqrt := divSqrtRecFNToRaw.io.rawOutValid_sqrt
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := divSqrtRecFNToRaw.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := divSqrtRecFNToRaw.io.infiniteExc
roundRawFNToRecFN.io.in := divSqrtRecFNToRaw.io.rawOut
roundRawFNToRecFN.io.roundingMode := divSqrtRecFNToRaw.io.roundingModeOut
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
} | module DivSqrtRecFM_small_e5_s11(
input clock,
input reset,
output io_inReady,
input io_inValid,
input io_sqrtOp,
input [16:0] io_a,
input [16:0] io_b,
input [2:0] io_roundingMode,
output io_outValid_div,
output io_outValid_sqrt,
output [16:0] io_out,
output [4:0] io_exceptionFlags
);
wire [2:0] _divSqrtRecFNToRaw_io_roundingModeOut;
wire _divSqrtRecFNToRaw_io_invalidExc;
wire _divSqrtRecFNToRaw_io_infiniteExc;
wire _divSqrtRecFNToRaw_io_rawOut_isNaN;
wire _divSqrtRecFNToRaw_io_rawOut_isInf;
wire _divSqrtRecFNToRaw_io_rawOut_isZero;
wire _divSqrtRecFNToRaw_io_rawOut_sign;
wire [6:0] _divSqrtRecFNToRaw_io_rawOut_sExp;
wire [13:0] _divSqrtRecFNToRaw_io_rawOut_sig;
DivSqrtRecFMToRaw_small_e5_s11 divSqrtRecFNToRaw (
.clock (clock),
.reset (reset),
.io_inReady (io_inReady),
.io_inValid (io_inValid),
.io_sqrtOp (io_sqrtOp),
.io_a (io_a),
.io_b (io_b),
.io_roundingMode (io_roundingMode),
.io_rawOutValid_div (io_outValid_div),
.io_rawOutValid_sqrt (io_outValid_sqrt),
.io_roundingModeOut (_divSqrtRecFNToRaw_io_roundingModeOut),
.io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc),
.io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc),
.io_rawOut_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN),
.io_rawOut_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf),
.io_rawOut_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero),
.io_rawOut_sign (_divSqrtRecFNToRaw_io_rawOut_sign),
.io_rawOut_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp),
.io_rawOut_sig (_divSqrtRecFNToRaw_io_rawOut_sig)
);
RoundRawFNToRecFN_e5_s11 roundRawFNToRecFN (
.io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc),
.io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc),
.io_in_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN),
.io_in_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf),
.io_in_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero),
.io_in_sign (_divSqrtRecFNToRaw_io_rawOut_sign),
.io_in_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp),
.io_in_sig (_divSqrtRecFNToRaw_io_rawOut_sig),
.io_roundingMode (_divSqrtRecFNToRaw_io_roundingModeOut),
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Re-order Buffer
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Bank the ROB, such that each "dispatch" group gets its own row of the ROB,
// and each instruction in the dispatch group goes to a different bank.
// We can compress out the PC by only saving the high-order bits!
//
// ASSUMPTIONS:
// - dispatch groups are aligned to the PC.
//
// NOTES:
// - Currently we do not compress out bubbles in the ROB.
// - Exceptions are only taken when at the head of the commit bundle --
// this helps deal with loads, stores, and refetch instructions.
package boom.v3.exu
import scala.math.ceil
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
import boom.v3.common._
import boom.v3.util._
/**
* IO bundle to interact with the ROB
*
* @param numWakeupPorts number of wakeup ports to the rob
* @param numFpuPorts number of fpu ports that will write back fflags
*/
class RobIo(
val numWakeupPorts: Int,
val numFpuPorts: Int
)(implicit p: Parameters) extends BoomBundle
{
// Decode Stage
// (Allocate, write instruction to ROB).
val enq_valids = Input(Vec(coreWidth, Bool()))
val enq_uops = Input(Vec(coreWidth, new MicroOp()))
val enq_partial_stall= Input(Bool()) // we're dispatching only a partial packet,
// and stalling on the rest of it (don't
// advance the tail ptr)
val xcpt_fetch_pc = Input(UInt(vaddrBitsExtended.W))
val rob_tail_idx = Output(UInt(robAddrSz.W))
val rob_pnr_idx = Output(UInt(robAddrSz.W))
val rob_head_idx = Output(UInt(robAddrSz.W))
// Handle Branch Misspeculations
val brupdate = Input(new BrUpdateInfo())
// Write-back Stage
// (Update of ROB)
// Instruction is no longer busy and can be committed
val wb_resps = Flipped(Vec(numWakeupPorts, Valid(new ExeUnitResp(xLen max fLen+1))))
// Unbusying ports for stores.
// +1 for fpstdata
val lsu_clr_bsy = Input(Vec(memWidth + 1, Valid(UInt(robAddrSz.W))))
// Port for unmarking loads/stores as speculation hazards..
val lsu_clr_unsafe = Input(Vec(memWidth, Valid(UInt(robAddrSz.W))))
// Track side-effects for debug purposes.
// Also need to know when loads write back, whereas we don't need loads to unbusy.
val debug_wb_valids = Input(Vec(numWakeupPorts, Bool()))
val debug_wb_wdata = Input(Vec(numWakeupPorts, Bits(xLen.W)))
val fflags = Flipped(Vec(numFpuPorts, new ValidIO(new FFlagsResp())))
val lxcpt = Input(Valid(new Exception())) // LSU
val csr_replay = Input(Valid(new Exception()))
// Commit stage (free resources; also used for rollback).
val commit = Output(new CommitSignals())
// tell the LSU that the head of the ROB is a load
// (some loads can only execute once they are at the head of the ROB).
val com_load_is_at_rob_head = Output(Bool())
// Communicate exceptions to the CSRFile
val com_xcpt = Valid(new CommitExceptionSignals())
// Let the CSRFile stall us (e.g., wfi).
val csr_stall = Input(Bool())
// Flush signals (including exceptions, pipeline replays, and memory ordering failures)
// to send to the frontend for redirection.
val flush = Valid(new CommitExceptionSignals)
// Stall Decode as appropriate
val empty = Output(Bool())
val ready = Output(Bool()) // ROB is busy unrolling rename state...
// Stall the frontend if we know we will redirect the PC
val flush_frontend = Output(Bool())
val debug_tsc = Input(UInt(xLen.W))
}
/**
* Bundle to send commit signals across processor
*/
class CommitSignals(implicit p: Parameters) extends BoomBundle
{
val valids = Vec(retireWidth, Bool()) // These instructions may not correspond to an architecturally executed insn
val arch_valids = Vec(retireWidth, Bool())
val uops = Vec(retireWidth, new MicroOp())
val fflags = Valid(UInt(5.W))
// These come a cycle later
val debug_insts = Vec(retireWidth, UInt(32.W))
// Perform rollback of rename state (in conjuction with commit.uops).
val rbk_valids = Vec(retireWidth, Bool())
val rollback = Bool()
val debug_wdata = Vec(retireWidth, UInt(xLen.W))
}
/**
* Bundle to communicate exceptions to CSRFile
*
* TODO combine FlushSignals and ExceptionSignals (currently timed to different cycles).
*/
class CommitExceptionSignals(implicit p: Parameters) extends BoomBundle
{
val ftq_idx = UInt(log2Ceil(ftqSz).W)
val edge_inst = Bool()
val is_rvc = Bool()
val pc_lob = UInt(log2Ceil(icBlockBytes).W)
val cause = UInt(xLen.W)
val badvaddr = UInt(xLen.W)
// The ROB needs to tell the FTQ if there's a pipeline flush (and what type)
// so the FTQ can drive the frontend with the correct redirected PC.
val flush_typ = FlushTypes()
}
/**
* Tell the frontend the type of flush so it can set up the next PC properly.
*/
object FlushTypes
{
def SZ = 3
def apply() = UInt(SZ.W)
def none = 0.U
def xcpt = 1.U // An exception occurred.
def eret = (2+1).U // Execute an environment return instruction.
def refetch = 2.U // Flush and refetch the head instruction.
def next = 4.U // Flush and fetch the next instruction.
def useCsrEvec(typ: UInt): Bool = typ(0) // typ === xcpt.U || typ === eret.U
def useSamePC(typ: UInt): Bool = typ === refetch
def usePCplus4(typ: UInt): Bool = typ === next
def getType(valid: Bool, i_xcpt: Bool, i_eret: Bool, i_refetch: Bool): UInt = {
val ret =
Mux(!valid, none,
Mux(i_eret, eret,
Mux(i_xcpt, xcpt,
Mux(i_refetch, refetch,
next))))
ret
}
}
/**
* Bundle of signals indicating that an exception occurred
*/
class Exception(implicit p: Parameters) extends BoomBundle
{
val uop = new MicroOp()
val cause = Bits(log2Ceil(freechips.rocketchip.rocket.Causes.all.max+2).W)
val badvaddr = UInt(coreMaxAddrBits.W)
}
/**
* Bundle for debug ROB signals
* These should not be synthesized!
*/
class DebugRobSignals(implicit p: Parameters) extends BoomBundle
{
val state = UInt()
val rob_head = UInt(robAddrSz.W)
val rob_pnr = UInt(robAddrSz.W)
val xcpt_val = Bool()
val xcpt_uop = new MicroOp()
val xcpt_badvaddr = UInt(xLen.W)
}
/**
* Reorder Buffer to keep track of dependencies and inflight instructions
*
* @param numWakeupPorts number of wakeup ports to the ROB
* @param numFpuPorts number of FPU units that will write back fflags
*/
class Rob(
val numWakeupPorts: Int,
val numFpuPorts: Int
)(implicit p: Parameters) extends BoomModule
{
val io = IO(new RobIo(numWakeupPorts, numFpuPorts))
// ROB Finite State Machine
val s_reset :: s_normal :: s_rollback :: s_wait_till_empty :: Nil = Enum(4)
val rob_state = RegInit(s_reset)
//commit entries at the head, and unwind exceptions from the tail
val rob_head = RegInit(0.U(log2Ceil(numRobRows).W))
val rob_head_lsb = RegInit(0.U((1 max log2Ceil(coreWidth)).W)) // TODO: Accurately track head LSB (currently always 0)
val rob_head_idx = if (coreWidth == 1) rob_head else Cat(rob_head, rob_head_lsb)
val rob_tail = RegInit(0.U(log2Ceil(numRobRows).W))
val rob_tail_lsb = RegInit(0.U((1 max log2Ceil(coreWidth)).W))
val rob_tail_idx = if (coreWidth == 1) rob_tail else Cat(rob_tail, rob_tail_lsb)
val rob_pnr = RegInit(0.U(log2Ceil(numRobRows).W))
val rob_pnr_lsb = RegInit(0.U((1 max log2Ceil(coreWidth)).W))
val rob_pnr_idx = if (coreWidth == 1) rob_pnr else Cat(rob_pnr , rob_pnr_lsb)
val com_idx = Mux(rob_state === s_rollback, rob_tail, rob_head)
val maybe_full = RegInit(false.B)
val full = Wire(Bool())
val empty = Wire(Bool())
val will_commit = Wire(Vec(coreWidth, Bool()))
val can_commit = Wire(Vec(coreWidth, Bool()))
val can_throw_exception = Wire(Vec(coreWidth, Bool()))
val rob_pnr_unsafe = Wire(Vec(coreWidth, Bool())) // are the instructions at the pnr unsafe?
val rob_head_vals = Wire(Vec(coreWidth, Bool())) // are the instructions at the head valid?
val rob_tail_vals = Wire(Vec(coreWidth, Bool())) // are the instructions at the tail valid? (to track partial row dispatches)
val rob_head_uses_stq = Wire(Vec(coreWidth, Bool()))
val rob_head_uses_ldq = Wire(Vec(coreWidth, Bool()))
val rob_head_fflags = Wire(Vec(coreWidth, UInt(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W)))
val exception_thrown = Wire(Bool())
// exception info
// TODO compress xcpt cause size. Most bits in the middle are zero.
val r_xcpt_val = RegInit(false.B)
val r_xcpt_uop = Reg(new MicroOp())
val r_xcpt_badvaddr = Reg(UInt(coreMaxAddrBits.W))
io.flush_frontend := r_xcpt_val
//--------------------------------------------------
// Utility
def GetRowIdx(rob_idx: UInt): UInt = {
if (coreWidth == 1) return rob_idx
else return rob_idx >> log2Ceil(coreWidth).U
}
def GetBankIdx(rob_idx: UInt): UInt = {
if(coreWidth == 1) { return 0.U }
else { return rob_idx(log2Ceil(coreWidth)-1, 0).asUInt }
}
// **************************************************************************
// Debug
class DebugRobBundle extends BoomBundle
{
val valid = Bool()
val busy = Bool()
val unsafe = Bool()
val uop = new MicroOp()
val exception = Bool()
}
val debug_entry = Wire(Vec(numRobEntries, new DebugRobBundle))
debug_entry := DontCare // override in statements below
// **************************************************************************
// --------------------------------------------------------------------------
// **************************************************************************
// Contains all information the PNR needs to find the oldest instruction which can't be safely speculated past.
val rob_unsafe_masked = WireInit(VecInit(Seq.fill(numRobRows << log2Ceil(coreWidth)){false.B}))
// Used for trace port, for debug purposes only
val rob_debug_inst_mem = SyncReadMem(numRobRows, Vec(coreWidth, UInt(32.W)))
val rob_debug_inst_wmask = WireInit(VecInit(0.U(coreWidth.W).asBools))
val rob_debug_inst_wdata = Wire(Vec(coreWidth, UInt(32.W)))
rob_debug_inst_mem.write(rob_tail, rob_debug_inst_wdata, rob_debug_inst_wmask)
val rob_debug_inst_rdata = rob_debug_inst_mem.read(rob_head, will_commit.reduce(_||_))
val rob_fflags = Seq.fill(coreWidth)(Reg(Vec(numRobRows, UInt(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W))))
for (w <- 0 until coreWidth) {
def MatchBank(bank_idx: UInt): Bool = (bank_idx === w.U)
// one bank
val rob_val = RegInit(VecInit(Seq.fill(numRobRows){false.B}))
val rob_bsy = Reg(Vec(numRobRows, Bool()))
val rob_unsafe = Reg(Vec(numRobRows, Bool()))
val rob_uop = Reg(Vec(numRobRows, new MicroOp()))
val rob_exception = Reg(Vec(numRobRows, Bool()))
val rob_predicated = Reg(Vec(numRobRows, Bool())) // Was this instruction predicated out?
val rob_debug_wdata = Mem(numRobRows, UInt(xLen.W))
//-----------------------------------------------
// Dispatch: Add Entry to ROB
rob_debug_inst_wmask(w) := io.enq_valids(w)
rob_debug_inst_wdata(w) := io.enq_uops(w).debug_inst
when (io.enq_valids(w)) {
rob_val(rob_tail) := true.B
rob_bsy(rob_tail) := !(io.enq_uops(w).is_fence ||
io.enq_uops(w).is_fencei)
rob_unsafe(rob_tail) := io.enq_uops(w).unsafe
rob_uop(rob_tail) := io.enq_uops(w)
rob_exception(rob_tail) := io.enq_uops(w).exception
rob_predicated(rob_tail) := false.B
rob_fflags(w)(rob_tail) := 0.U
assert (rob_val(rob_tail) === false.B, "[rob] overwriting a valid entry.")
assert ((io.enq_uops(w).rob_idx >> log2Ceil(coreWidth)) === rob_tail)
} .elsewhen (io.enq_valids.reduce(_|_) && !rob_val(rob_tail)) {
rob_uop(rob_tail).debug_inst := BUBBLE // just for debug purposes
}
//-----------------------------------------------
// Writeback
for (i <- 0 until numWakeupPorts) {
val wb_resp = io.wb_resps(i)
val wb_uop = wb_resp.bits.uop
val row_idx = GetRowIdx(wb_uop.rob_idx)
when (wb_resp.valid && MatchBank(GetBankIdx(wb_uop.rob_idx))) {
rob_bsy(row_idx) := false.B
rob_unsafe(row_idx) := false.B
rob_predicated(row_idx) := wb_resp.bits.predicated
}
// TODO check that fflags aren't overwritten
// TODO check that the wb is to a valid ROB entry, give it a time stamp
// assert (!(wb_resp.valid && MatchBank(GetBankIdx(wb_uop.rob_idx)) &&
// wb_uop.fp_val && !(wb_uop.is_load || wb_uop.is_store) &&
// rob_exc_cause(row_idx) =/= 0.U),
// "FP instruction writing back exc bits is overriding an existing exception.")
}
// Stores have a separate method to clear busy bits
for (clr_rob_idx <- io.lsu_clr_bsy) {
when (clr_rob_idx.valid && MatchBank(GetBankIdx(clr_rob_idx.bits))) {
val cidx = GetRowIdx(clr_rob_idx.bits)
rob_bsy(cidx) := false.B
rob_unsafe(cidx) := false.B
assert (rob_val(cidx) === true.B, "[rob] store writing back to invalid entry.")
assert (rob_bsy(cidx) === true.B, "[rob] store writing back to a not-busy entry.")
}
}
for (clr <- io.lsu_clr_unsafe) {
when (clr.valid && MatchBank(GetBankIdx(clr.bits))) {
val cidx = GetRowIdx(clr.bits)
rob_unsafe(cidx) := false.B
}
}
//-----------------------------------------------
// Accruing fflags
for (i <- 0 until numFpuPorts) {
val fflag_uop = io.fflags(i).bits.uop
when (io.fflags(i).valid && MatchBank(GetBankIdx(fflag_uop.rob_idx))) {
rob_fflags(w)(GetRowIdx(fflag_uop.rob_idx)) := io.fflags(i).bits.flags
}
}
//-----------------------------------------------------
// Exceptions
// (the cause bits are compressed and stored elsewhere)
when (io.lxcpt.valid && MatchBank(GetBankIdx(io.lxcpt.bits.uop.rob_idx))) {
rob_exception(GetRowIdx(io.lxcpt.bits.uop.rob_idx)) := true.B
when (io.lxcpt.bits.cause =/= MINI_EXCEPTION_MEM_ORDERING) {
// In the case of a mem-ordering failure, the failing load will have been marked safe already.
assert(rob_unsafe(GetRowIdx(io.lxcpt.bits.uop.rob_idx)),
"An instruction marked as safe is causing an exception")
}
}
when (io.csr_replay.valid && MatchBank(GetBankIdx(io.csr_replay.bits.uop.rob_idx))) {
rob_exception(GetRowIdx(io.csr_replay.bits.uop.rob_idx)) := true.B
}
can_throw_exception(w) := rob_val(rob_head) && rob_exception(rob_head)
//-----------------------------------------------
// Commit or Rollback
// Can this instruction commit? (the check for exceptions/rob_state happens later).
can_commit(w) := rob_val(rob_head) && !(rob_bsy(rob_head)) && !io.csr_stall
// use the same "com_uop" for both rollback AND commit
// Perform Commit
io.commit.valids(w) := will_commit(w)
io.commit.arch_valids(w) := will_commit(w) && !rob_predicated(com_idx)
io.commit.uops(w) := rob_uop(com_idx)
io.commit.debug_insts(w) := rob_debug_inst_rdata(w)
// We unbusy branches in b1, but its easier to mark the taken/provider src in b2,
// when the branch might be committing
when (io.brupdate.b2.mispredict &&
MatchBank(GetBankIdx(io.brupdate.b2.uop.rob_idx)) &&
GetRowIdx(io.brupdate.b2.uop.rob_idx) === com_idx) {
io.commit.uops(w).debug_fsrc := BSRC_C
io.commit.uops(w).taken := io.brupdate.b2.taken
}
// Don't attempt to rollback the tail's row when the rob is full.
val rbk_row = rob_state === s_rollback && !full
io.commit.rbk_valids(w) := rbk_row && rob_val(com_idx) && !(enableCommitMapTable.B)
io.commit.rollback := (rob_state === s_rollback)
assert (!(io.commit.valids.reduce(_||_) && io.commit.rbk_valids.reduce(_||_)),
"com_valids and rbk_valids are mutually exclusive")
when (rbk_row) {
rob_val(com_idx) := false.B
rob_exception(com_idx) := false.B
}
if (enableCommitMapTable) {
when (RegNext(exception_thrown)) {
for (i <- 0 until numRobRows) {
rob_val(i) := false.B
rob_bsy(i) := false.B
rob_uop(i).debug_inst := BUBBLE
}
}
}
// -----------------------------------------------
// Kill speculated entries on branch mispredict
for (i <- 0 until numRobRows) {
val br_mask = rob_uop(i).br_mask
//kill instruction if mispredict & br mask match
when (IsKilledByBranch(io.brupdate, br_mask))
{
rob_val(i) := false.B
rob_uop(i.U).debug_inst := BUBBLE
} .elsewhen (rob_val(i)) {
// clear speculation bit even on correct speculation
rob_uop(i).br_mask := GetNewBrMask(io.brupdate, br_mask)
}
}
// Debug signal to figure out which prediction structure
// or core resolved a branch correctly
when (io.brupdate.b2.mispredict &&
MatchBank(GetBankIdx(io.brupdate.b2.uop.rob_idx))) {
rob_uop(GetRowIdx(io.brupdate.b2.uop.rob_idx)).debug_fsrc := BSRC_C
rob_uop(GetRowIdx(io.brupdate.b2.uop.rob_idx)).taken := io.brupdate.b2.taken
}
// -----------------------------------------------
// Commit
when (will_commit(w)) {
rob_val(rob_head) := false.B
}
// -----------------------------------------------
// Outputs
rob_head_vals(w) := rob_val(rob_head)
rob_tail_vals(w) := rob_val(rob_tail)
rob_head_fflags(w) := rob_fflags(w)(rob_head)
rob_head_uses_stq(w) := rob_uop(rob_head).uses_stq
rob_head_uses_ldq(w) := rob_uop(rob_head).uses_ldq
//------------------------------------------------
// Invalid entries are safe; thrown exceptions are unsafe.
for (i <- 0 until numRobRows) {
rob_unsafe_masked((i << log2Ceil(coreWidth)) + w) := rob_val(i) && (rob_unsafe(i) || rob_exception(i))
}
// Read unsafe status of PNR row.
rob_pnr_unsafe(w) := rob_val(rob_pnr) && (rob_unsafe(rob_pnr) || rob_exception(rob_pnr))
// -----------------------------------------------
// debugging write ports that should not be synthesized
when (will_commit(w)) {
rob_uop(rob_head).debug_inst := BUBBLE
} .elsewhen (rbk_row)
{
rob_uop(rob_tail).debug_inst := BUBBLE
}
//--------------------------------------------------
// Debug: for debug purposes, track side-effects to all register destinations
for (i <- 0 until numWakeupPorts) {
val rob_idx = io.wb_resps(i).bits.uop.rob_idx
when (io.debug_wb_valids(i) && MatchBank(GetBankIdx(rob_idx))) {
rob_debug_wdata(GetRowIdx(rob_idx)) := io.debug_wb_wdata(i)
}
val temp_uop = rob_uop(GetRowIdx(rob_idx))
assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&
!rob_val(GetRowIdx(rob_idx))),
"[rob] writeback (" + i + ") occurred to an invalid ROB entry.")
assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&
!rob_bsy(GetRowIdx(rob_idx))),
"[rob] writeback (" + i + ") occurred to a not-busy ROB entry.")
assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&
temp_uop.ldst_val && temp_uop.pdst =/= io.wb_resps(i).bits.uop.pdst),
"[rob] writeback (" + i + ") occurred to the wrong pdst.")
}
io.commit.debug_wdata(w) := rob_debug_wdata(rob_head)
} //for (w <- 0 until coreWidth)
// **************************************************************************
// --------------------------------------------------------------------------
// **************************************************************************
// -----------------------------------------------
// Commit Logic
// need to take a "can_commit" array, and let the first can_commits commit
// previous instructions may block the commit of younger instructions in the commit bundle
// e.g., exception, or (valid && busy).
// Finally, don't throw an exception if there are instructions in front of
// it that want to commit (only throw exception when head of the bundle).
var block_commit = (rob_state =/= s_normal) && (rob_state =/= s_wait_till_empty) || RegNext(exception_thrown) || RegNext(RegNext(exception_thrown))
var will_throw_exception = false.B
var block_xcpt = false.B
for (w <- 0 until coreWidth) {
will_throw_exception = (can_throw_exception(w) && !block_commit && !block_xcpt) || will_throw_exception
will_commit(w) := can_commit(w) && !can_throw_exception(w) && !block_commit
block_commit = (rob_head_vals(w) &&
(!can_commit(w) || can_throw_exception(w))) || block_commit
block_xcpt = will_commit(w)
}
// Note: exception must be in the commit bundle.
// Note: exception must be the first valid instruction in the commit bundle.
exception_thrown := will_throw_exception
val is_mini_exception = io.com_xcpt.bits.cause.isOneOf(MINI_EXCEPTION_MEM_ORDERING, MINI_EXCEPTION_CSR_REPLAY)
io.com_xcpt.valid := exception_thrown && !is_mini_exception
io.com_xcpt.bits := DontCare
io.com_xcpt.bits.cause := r_xcpt_uop.exc_cause
io.com_xcpt.bits.badvaddr := Sext(r_xcpt_badvaddr, xLen)
val insn_sys_pc2epc =
rob_head_vals.reduce(_|_) && PriorityMux(rob_head_vals, io.commit.uops.map{u => u.is_sys_pc2epc})
val refetch_inst = exception_thrown || insn_sys_pc2epc
val com_xcpt_uop = PriorityMux(rob_head_vals, io.commit.uops)
io.com_xcpt.bits.ftq_idx := com_xcpt_uop.ftq_idx
io.com_xcpt.bits.edge_inst := com_xcpt_uop.edge_inst
io.com_xcpt.bits.is_rvc := com_xcpt_uop.is_rvc
io.com_xcpt.bits.pc_lob := com_xcpt_uop.pc_lob
val flush_commit_mask = Range(0,coreWidth).map{i => io.commit.valids(i) && io.commit.uops(i).flush_on_commit}
val flush_commit = flush_commit_mask.reduce(_|_)
val flush_val = exception_thrown || flush_commit
assert(!(PopCount(flush_commit_mask) > 1.U),
"[rob] Can't commit multiple flush_on_commit instructions on one cycle")
val flush_uop = Mux(exception_thrown, com_xcpt_uop, Mux1H(flush_commit_mask, io.commit.uops))
// delay a cycle for critical path considerations
io.flush.valid := flush_val
io.flush.bits := DontCare
io.flush.bits.ftq_idx := flush_uop.ftq_idx
io.flush.bits.pc_lob := flush_uop.pc_lob
io.flush.bits.edge_inst := flush_uop.edge_inst
io.flush.bits.is_rvc := flush_uop.is_rvc
io.flush.bits.flush_typ := FlushTypes.getType(flush_val,
exception_thrown && !is_mini_exception,
flush_commit && flush_uop.uopc === uopERET,
refetch_inst)
// -----------------------------------------------
// FP Exceptions
// send fflags bits to the CSRFile to accrue
val fflags_val = Wire(Vec(coreWidth, Bool()))
val fflags = Wire(Vec(coreWidth, UInt(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W)))
for (w <- 0 until coreWidth) {
fflags_val(w) :=
io.commit.valids(w) &&
io.commit.uops(w).fp_val &&
!io.commit.uops(w).uses_stq
fflags(w) := Mux(fflags_val(w), rob_head_fflags(w), 0.U)
assert (!(io.commit.valids(w) &&
!io.commit.uops(w).fp_val &&
rob_head_fflags(w) =/= 0.U),
"Committed non-FP instruction has non-zero fflag bits.")
assert (!(io.commit.valids(w) &&
io.commit.uops(w).fp_val &&
(io.commit.uops(w).uses_ldq || io.commit.uops(w).uses_stq) &&
rob_head_fflags(w) =/= 0.U),
"Committed FP load or store has non-zero fflag bits.")
}
io.commit.fflags.valid := fflags_val.reduce(_|_)
io.commit.fflags.bits := fflags.reduce(_|_)
// -----------------------------------------------
// Exception Tracking Logic
// only store the oldest exception, since only one can happen!
val next_xcpt_uop = Wire(new MicroOp())
next_xcpt_uop := r_xcpt_uop
val enq_xcpts = Wire(Vec(coreWidth, Bool()))
for (i <- 0 until coreWidth) {
enq_xcpts(i) := io.enq_valids(i) && io.enq_uops(i).exception
}
when (!(io.flush.valid || exception_thrown) && rob_state =/= s_rollback) {
val new_xcpt_valid = io.lxcpt.valid || io.csr_replay.valid
val lxcpt_older = !io.csr_replay.valid || (IsOlder(io.lxcpt.bits.uop.rob_idx, io.csr_replay.bits.uop.rob_idx, rob_head_idx) && io.lxcpt.valid)
val new_xcpt = Mux(lxcpt_older, io.lxcpt.bits, io.csr_replay.bits)
when (new_xcpt_valid) {
when (!r_xcpt_val || IsOlder(new_xcpt.uop.rob_idx, r_xcpt_uop.rob_idx, rob_head_idx)) {
r_xcpt_val := true.B
next_xcpt_uop := new_xcpt.uop
next_xcpt_uop.exc_cause := new_xcpt.cause
r_xcpt_badvaddr := new_xcpt.badvaddr
}
} .elsewhen (!r_xcpt_val && enq_xcpts.reduce(_|_)) {
val idx = enq_xcpts.indexWhere{i: Bool => i}
// if no exception yet, dispatch exception wins
r_xcpt_val := true.B
next_xcpt_uop := io.enq_uops(idx)
r_xcpt_badvaddr := AlignPCToBoundary(io.xcpt_fetch_pc, icBlockBytes) | io.enq_uops(idx).pc_lob
}
}
r_xcpt_uop := next_xcpt_uop
r_xcpt_uop.br_mask := GetNewBrMask(io.brupdate, next_xcpt_uop)
when (io.flush.valid || IsKilledByBranch(io.brupdate, next_xcpt_uop)) {
r_xcpt_val := false.B
}
assert (!(exception_thrown && !r_xcpt_val),
"ROB trying to throw an exception, but it doesn't have a valid xcpt_cause")
assert (!(empty && r_xcpt_val),
"ROB is empty, but believes it has an outstanding exception.")
assert (!(will_throw_exception && (GetRowIdx(r_xcpt_uop.rob_idx) =/= rob_head)),
"ROB is throwing an exception, but the stored exception information's " +
"rob_idx does not match the rob_head")
// -----------------------------------------------
// ROB Head Logic
// remember if we're still waiting on the rest of the dispatch packet, and prevent
// the rob_head from advancing if it commits a partial parket before we
// dispatch the rest of it.
// update when committed ALL valid instructions in commit_bundle
val rob_deq = WireInit(false.B)
val r_partial_row = RegInit(false.B)
when (io.enq_valids.reduce(_|_)) {
r_partial_row := io.enq_partial_stall
}
val finished_committing_row =
(io.commit.valids.asUInt =/= 0.U) &&
((will_commit.asUInt ^ rob_head_vals.asUInt) === 0.U) &&
!(r_partial_row && rob_head === rob_tail && !maybe_full)
when (finished_committing_row) {
rob_head := WrapInc(rob_head, numRobRows)
rob_head_lsb := 0.U
rob_deq := true.B
} .otherwise {
rob_head_lsb := OHToUInt(PriorityEncoderOH(rob_head_vals.asUInt))
}
// -----------------------------------------------
// ROB Point-of-No-Return (PNR) Logic
// Acts as a second head, but only waits on busy instructions which might cause misspeculation.
// TODO is it worth it to add an extra 'parity' bit to all rob pointer logic?
// Makes 'older than' comparisons ~3x cheaper, in case we're going to use the PNR to do a large number of those.
// Also doesn't require the rob tail (or head) to be exported to whatever we want to compare with the PNR.
if (enableFastPNR) {
val unsafe_entry_in_rob = rob_unsafe_masked.reduce(_||_)
val next_rob_pnr_idx = Mux(unsafe_entry_in_rob,
AgePriorityEncoder(rob_unsafe_masked, rob_head_idx),
rob_tail << log2Ceil(coreWidth) | PriorityEncoder(~rob_tail_vals.asUInt))
rob_pnr := next_rob_pnr_idx >> log2Ceil(coreWidth)
if (coreWidth > 1)
rob_pnr_lsb := next_rob_pnr_idx(log2Ceil(coreWidth)-1, 0)
} else {
// Distinguish between PNR being at head/tail when ROB is full.
// Works the same as maybe_full tracking for the ROB tail.
val pnr_maybe_at_tail = RegInit(false.B)
val safe_to_inc = rob_state === s_normal || rob_state === s_wait_till_empty
val do_inc_row = !rob_pnr_unsafe.reduce(_||_) && (rob_pnr =/= rob_tail || (full && !pnr_maybe_at_tail))
when (empty && io.enq_valids.asUInt =/= 0.U) {
// Unforunately for us, the ROB does not use its entries in monotonically
// increasing order, even in the case of no exceptions. The edge case
// arises when partial rows are enqueued and committed, leaving an empty
// ROB.
rob_pnr := rob_head
rob_pnr_lsb := PriorityEncoder(io.enq_valids)
} .elsewhen (safe_to_inc && do_inc_row) {
rob_pnr := WrapInc(rob_pnr, numRobRows)
rob_pnr_lsb := 0.U
} .elsewhen (safe_to_inc && (rob_pnr =/= rob_tail || (full && !pnr_maybe_at_tail))) {
rob_pnr_lsb := PriorityEncoder(rob_pnr_unsafe)
} .elsewhen (safe_to_inc && !full && !empty) {
rob_pnr_lsb := PriorityEncoder(rob_pnr_unsafe.asUInt | ~MaskLower(rob_tail_vals.asUInt))
} .elsewhen (full && pnr_maybe_at_tail) {
rob_pnr_lsb := 0.U
}
pnr_maybe_at_tail := !rob_deq && (do_inc_row || pnr_maybe_at_tail)
}
// Head overrunning PNR likely means an entry hasn't been marked as safe when it should have been.
assert(!IsOlder(rob_pnr_idx, rob_head_idx, rob_tail_idx) || rob_pnr_idx === rob_tail_idx)
// PNR overrunning tail likely means an entry has been marked as safe when it shouldn't have been.
assert(!IsOlder(rob_tail_idx, rob_pnr_idx, rob_head_idx) || full)
// -----------------------------------------------
// ROB Tail Logic
val rob_enq = WireInit(false.B)
when (rob_state === s_rollback && (rob_tail =/= rob_head || maybe_full)) {
// Rollback a row
rob_tail := WrapDec(rob_tail, numRobRows)
rob_tail_lsb := (coreWidth-1).U
rob_deq := true.B
} .elsewhen (rob_state === s_rollback && (rob_tail === rob_head) && !maybe_full) {
// Rollback an entry
rob_tail_lsb := rob_head_lsb
} .elsewhen (io.brupdate.b2.mispredict) {
rob_tail := WrapInc(GetRowIdx(io.brupdate.b2.uop.rob_idx), numRobRows)
rob_tail_lsb := 0.U
} .elsewhen (io.enq_valids.asUInt =/= 0.U && !io.enq_partial_stall) {
rob_tail := WrapInc(rob_tail, numRobRows)
rob_tail_lsb := 0.U
rob_enq := true.B
} .elsewhen (io.enq_valids.asUInt =/= 0.U && io.enq_partial_stall) {
rob_tail_lsb := PriorityEncoder(~MaskLower(io.enq_valids.asUInt))
}
if (enableCommitMapTable) {
when (RegNext(exception_thrown)) {
rob_tail := 0.U
rob_tail_lsb := 0.U
rob_head := 0.U
rob_pnr := 0.U
rob_pnr_lsb := 0.U
}
}
// -----------------------------------------------
// Full/Empty Logic
// The ROB can be completely full, but only if it did not dispatch a row in the prior cycle.
// I.E. at least one entry will be empty when in a steady state of dispatching and committing a row each cycle.
// TODO should we add an extra 'parity bit' onto the ROB pointers to simplify this logic?
maybe_full := !rob_deq && (rob_enq || maybe_full) || io.brupdate.b1.mispredict_mask =/= 0.U
full := rob_tail === rob_head && maybe_full
empty := (rob_head === rob_tail) && (rob_head_vals.asUInt === 0.U)
io.rob_head_idx := rob_head_idx
io.rob_tail_idx := rob_tail_idx
io.rob_pnr_idx := rob_pnr_idx
io.empty := empty
io.ready := (rob_state === s_normal) && !full && !r_xcpt_val
//-----------------------------------------------
//-----------------------------------------------
//-----------------------------------------------
// ROB FSM
if (!enableCommitMapTable) {
switch (rob_state) {
is (s_reset) {
rob_state := s_normal
}
is (s_normal) {
// Delay rollback 2 cycles so branch mispredictions can drain
when (RegNext(RegNext(exception_thrown))) {
rob_state := s_rollback
} .otherwise {
for (w <- 0 until coreWidth) {
when (io.enq_valids(w) && io.enq_uops(w).is_unique) {
rob_state := s_wait_till_empty
}
}
}
}
is (s_rollback) {
when (empty) {
rob_state := s_normal
}
}
is (s_wait_till_empty) {
when (RegNext(exception_thrown)) {
rob_state := s_rollback
} .elsewhen (empty) {
rob_state := s_normal
}
}
}
} else {
switch (rob_state) {
is (s_reset) {
rob_state := s_normal
}
is (s_normal) {
when (exception_thrown) {
; //rob_state := s_rollback
} .otherwise {
for (w <- 0 until coreWidth) {
when (io.enq_valids(w) && io.enq_uops(w).is_unique) {
rob_state := s_wait_till_empty
}
}
}
}
is (s_rollback) {
when (rob_tail_idx === rob_head_idx) {
rob_state := s_normal
}
}
is (s_wait_till_empty) {
when (exception_thrown) {
; //rob_state := s_rollback
} .elsewhen (rob_tail === rob_head) {
rob_state := s_normal
}
}
}
}
// -----------------------------------------------
// Outputs
io.com_load_is_at_rob_head := RegNext(rob_head_uses_ldq(PriorityEncoder(rob_head_vals.asUInt)) &&
!will_commit.reduce(_||_))
override def toString: String = BoomCoreStringPrefix(
"==ROB==",
"Machine Width : " + coreWidth,
"Rob Entries : " + numRobEntries,
"Rob Rows : " + numRobRows,
"Rob Row size : " + log2Ceil(numRobRows),
"log2Ceil(coreWidth): " + log2Ceil(coreWidth),
"FPU FFlag Ports : " + numFpuPorts)
} | module Rob(
input clock,
input reset,
input io_enq_valids_0,
input [6:0] io_enq_uops_0_uopc,
input [31:0] io_enq_uops_0_debug_inst,
input io_enq_uops_0_is_rvc,
input io_enq_uops_0_is_br,
input io_enq_uops_0_is_jalr,
input io_enq_uops_0_is_jal,
input [7:0] io_enq_uops_0_br_mask,
input [3:0] io_enq_uops_0_ftq_idx,
input io_enq_uops_0_edge_inst,
input [5:0] io_enq_uops_0_pc_lob,
input [4:0] io_enq_uops_0_rob_idx,
input [5:0] io_enq_uops_0_pdst,
input [5:0] io_enq_uops_0_stale_pdst,
input io_enq_uops_0_exception,
input [63:0] io_enq_uops_0_exc_cause,
input io_enq_uops_0_is_fence,
input io_enq_uops_0_is_fencei,
input io_enq_uops_0_uses_ldq,
input io_enq_uops_0_uses_stq,
input io_enq_uops_0_is_sys_pc2epc,
input io_enq_uops_0_is_unique,
input io_enq_uops_0_flush_on_commit,
input [5:0] io_enq_uops_0_ldst,
input io_enq_uops_0_ldst_val,
input [1:0] io_enq_uops_0_dst_rtype,
input io_enq_uops_0_fp_val,
input [1:0] io_enq_uops_0_debug_fsrc,
input io_enq_partial_stall,
input [39:0] io_xcpt_fetch_pc,
output [4:0] io_rob_tail_idx,
output [4:0] io_rob_head_idx,
input [7:0] io_brupdate_b1_resolve_mask,
input [7:0] io_brupdate_b1_mispredict_mask,
input [4:0] io_brupdate_b2_uop_rob_idx,
input io_brupdate_b2_mispredict,
input io_wb_resps_0_valid,
input [4:0] io_wb_resps_0_bits_uop_rob_idx,
input [5:0] io_wb_resps_0_bits_uop_pdst,
input io_wb_resps_0_bits_predicated,
input io_wb_resps_1_valid,
input [4:0] io_wb_resps_1_bits_uop_rob_idx,
input [5:0] io_wb_resps_1_bits_uop_pdst,
input io_wb_resps_2_valid,
input [4:0] io_wb_resps_2_bits_uop_rob_idx,
input [5:0] io_wb_resps_2_bits_uop_pdst,
input io_wb_resps_2_bits_predicated,
input io_wb_resps_3_valid,
input [4:0] io_wb_resps_3_bits_uop_rob_idx,
input [5:0] io_wb_resps_3_bits_uop_pdst,
input io_lsu_clr_bsy_0_valid,
input [4:0] io_lsu_clr_bsy_0_bits,
input io_lsu_clr_bsy_1_valid,
input [4:0] io_lsu_clr_bsy_1_bits,
input io_fflags_0_valid,
input [4:0] io_fflags_0_bits_uop_rob_idx,
input [4:0] io_fflags_0_bits_flags,
input io_fflags_1_valid,
input [4:0] io_fflags_1_bits_uop_rob_idx,
input [4:0] io_fflags_1_bits_flags,
input io_lxcpt_valid,
input [7:0] io_lxcpt_bits_uop_br_mask,
input [4:0] io_lxcpt_bits_uop_rob_idx,
input [4:0] io_lxcpt_bits_cause,
input [39:0] io_lxcpt_bits_badvaddr,
output io_commit_valids_0,
output io_commit_arch_valids_0,
output io_commit_uops_0_is_br,
output io_commit_uops_0_is_jalr,
output io_commit_uops_0_is_jal,
output [3:0] io_commit_uops_0_ftq_idx,
output [5:0] io_commit_uops_0_pdst,
output [5:0] io_commit_uops_0_stale_pdst,
output io_commit_uops_0_is_fencei,
output io_commit_uops_0_uses_ldq,
output io_commit_uops_0_uses_stq,
output [5:0] io_commit_uops_0_ldst,
output io_commit_uops_0_ldst_val,
output [1:0] io_commit_uops_0_dst_rtype,
output [1:0] io_commit_uops_0_debug_fsrc,
output io_commit_fflags_valid,
output [4:0] io_commit_fflags_bits,
output io_commit_rbk_valids_0,
output io_commit_rollback,
output io_com_load_is_at_rob_head,
output io_com_xcpt_valid,
output [3:0] io_com_xcpt_bits_ftq_idx,
output io_com_xcpt_bits_edge_inst,
output [5:0] io_com_xcpt_bits_pc_lob,
output [63:0] io_com_xcpt_bits_cause,
output [63:0] io_com_xcpt_bits_badvaddr,
input io_csr_stall,
output io_flush_valid,
output [3:0] io_flush_bits_ftq_idx,
output io_flush_bits_edge_inst,
output io_flush_bits_is_rvc,
output [5:0] io_flush_bits_pc_lob,
output [2:0] io_flush_bits_flush_typ,
output io_empty,
output io_ready,
output io_flush_frontend
);
wire empty;
wire full;
wire will_commit_0;
reg [1:0] rob_state;
reg [4:0] rob_head;
reg [4:0] rob_tail;
reg [4:0] rob_pnr;
wire io_commit_rollback_0 = rob_state == 2'h2;
wire [4:0] com_idx = io_commit_rollback_0 ? rob_tail : rob_head;
reg maybe_full;
reg r_xcpt_val;
reg [7:0] r_xcpt_uop_br_mask;
reg [4:0] r_xcpt_uop_rob_idx;
reg [63:0] r_xcpt_uop_exc_cause;
reg [39:0] r_xcpt_badvaddr;
reg [4:0] rob_fflags_0_0;
reg [4:0] rob_fflags_0_1;
reg [4:0] rob_fflags_0_2;
reg [4:0] rob_fflags_0_3;
reg [4:0] rob_fflags_0_4;
reg [4:0] rob_fflags_0_5;
reg [4:0] rob_fflags_0_6;
reg [4:0] rob_fflags_0_7;
reg [4:0] rob_fflags_0_8;
reg [4:0] rob_fflags_0_9;
reg [4:0] rob_fflags_0_10;
reg [4:0] rob_fflags_0_11;
reg [4:0] rob_fflags_0_12;
reg [4:0] rob_fflags_0_13;
reg [4:0] rob_fflags_0_14;
reg [4:0] rob_fflags_0_15;
reg [4:0] rob_fflags_0_16;
reg [4:0] rob_fflags_0_17;
reg [4:0] rob_fflags_0_18;
reg [4:0] rob_fflags_0_19;
reg [4:0] rob_fflags_0_20;
reg [4:0] rob_fflags_0_21;
reg [4:0] rob_fflags_0_22;
reg [4:0] rob_fflags_0_23;
reg [4:0] rob_fflags_0_24;
reg [4:0] rob_fflags_0_25;
reg [4:0] rob_fflags_0_26;
reg [4:0] rob_fflags_0_27;
reg [4:0] rob_fflags_0_28;
reg [4:0] rob_fflags_0_29;
reg [4:0] rob_fflags_0_30;
reg [4:0] rob_fflags_0_31;
reg rob_val_0;
reg rob_val_1;
reg rob_val_2;
reg rob_val_3;
reg rob_val_4;
reg rob_val_5;
reg rob_val_6;
reg rob_val_7;
reg rob_val_8;
reg rob_val_9;
reg rob_val_10;
reg rob_val_11;
reg rob_val_12;
reg rob_val_13;
reg rob_val_14;
reg rob_val_15;
reg rob_val_16;
reg rob_val_17;
reg rob_val_18;
reg rob_val_19;
reg rob_val_20;
reg rob_val_21;
reg rob_val_22;
reg rob_val_23;
reg rob_val_24;
reg rob_val_25;
reg rob_val_26;
reg rob_val_27;
reg rob_val_28;
reg rob_val_29;
reg rob_val_30;
reg rob_val_31;
reg rob_bsy_0;
reg rob_bsy_1;
reg rob_bsy_2;
reg rob_bsy_3;
reg rob_bsy_4;
reg rob_bsy_5;
reg rob_bsy_6;
reg rob_bsy_7;
reg rob_bsy_8;
reg rob_bsy_9;
reg rob_bsy_10;
reg rob_bsy_11;
reg rob_bsy_12;
reg rob_bsy_13;
reg rob_bsy_14;
reg rob_bsy_15;
reg rob_bsy_16;
reg rob_bsy_17;
reg rob_bsy_18;
reg rob_bsy_19;
reg rob_bsy_20;
reg rob_bsy_21;
reg rob_bsy_22;
reg rob_bsy_23;
reg rob_bsy_24;
reg rob_bsy_25;
reg rob_bsy_26;
reg rob_bsy_27;
reg rob_bsy_28;
reg rob_bsy_29;
reg rob_bsy_30;
reg rob_bsy_31;
reg rob_unsafe_0;
reg rob_unsafe_1;
reg rob_unsafe_2;
reg rob_unsafe_3;
reg rob_unsafe_4;
reg rob_unsafe_5;
reg rob_unsafe_6;
reg rob_unsafe_7;
reg rob_unsafe_8;
reg rob_unsafe_9;
reg rob_unsafe_10;
reg rob_unsafe_11;
reg rob_unsafe_12;
reg rob_unsafe_13;
reg rob_unsafe_14;
reg rob_unsafe_15;
reg rob_unsafe_16;
reg rob_unsafe_17;
reg rob_unsafe_18;
reg rob_unsafe_19;
reg rob_unsafe_20;
reg rob_unsafe_21;
reg rob_unsafe_22;
reg rob_unsafe_23;
reg rob_unsafe_24;
reg rob_unsafe_25;
reg rob_unsafe_26;
reg rob_unsafe_27;
reg rob_unsafe_28;
reg rob_unsafe_29;
reg rob_unsafe_30;
reg rob_unsafe_31;
reg [6:0] rob_uop_0_uopc;
reg rob_uop_0_is_rvc;
reg rob_uop_0_is_br;
reg rob_uop_0_is_jalr;
reg rob_uop_0_is_jal;
reg [7:0] rob_uop_0_br_mask;
reg [3:0] rob_uop_0_ftq_idx;
reg rob_uop_0_edge_inst;
reg [5:0] rob_uop_0_pc_lob;
reg [5:0] rob_uop_0_pdst;
reg [5:0] rob_uop_0_stale_pdst;
reg rob_uop_0_is_fencei;
reg rob_uop_0_uses_ldq;
reg rob_uop_0_uses_stq;
reg rob_uop_0_is_sys_pc2epc;
reg rob_uop_0_flush_on_commit;
reg [5:0] rob_uop_0_ldst;
reg rob_uop_0_ldst_val;
reg [1:0] rob_uop_0_dst_rtype;
reg rob_uop_0_fp_val;
reg [1:0] rob_uop_0_debug_fsrc;
reg [6:0] rob_uop_1_uopc;
reg rob_uop_1_is_rvc;
reg rob_uop_1_is_br;
reg rob_uop_1_is_jalr;
reg rob_uop_1_is_jal;
reg [7:0] rob_uop_1_br_mask;
reg [3:0] rob_uop_1_ftq_idx;
reg rob_uop_1_edge_inst;
reg [5:0] rob_uop_1_pc_lob;
reg [5:0] rob_uop_1_pdst;
reg [5:0] rob_uop_1_stale_pdst;
reg rob_uop_1_is_fencei;
reg rob_uop_1_uses_ldq;
reg rob_uop_1_uses_stq;
reg rob_uop_1_is_sys_pc2epc;
reg rob_uop_1_flush_on_commit;
reg [5:0] rob_uop_1_ldst;
reg rob_uop_1_ldst_val;
reg [1:0] rob_uop_1_dst_rtype;
reg rob_uop_1_fp_val;
reg [1:0] rob_uop_1_debug_fsrc;
reg [6:0] rob_uop_2_uopc;
reg rob_uop_2_is_rvc;
reg rob_uop_2_is_br;
reg rob_uop_2_is_jalr;
reg rob_uop_2_is_jal;
reg [7:0] rob_uop_2_br_mask;
reg [3:0] rob_uop_2_ftq_idx;
reg rob_uop_2_edge_inst;
reg [5:0] rob_uop_2_pc_lob;
reg [5:0] rob_uop_2_pdst;
reg [5:0] rob_uop_2_stale_pdst;
reg rob_uop_2_is_fencei;
reg rob_uop_2_uses_ldq;
reg rob_uop_2_uses_stq;
reg rob_uop_2_is_sys_pc2epc;
reg rob_uop_2_flush_on_commit;
reg [5:0] rob_uop_2_ldst;
reg rob_uop_2_ldst_val;
reg [1:0] rob_uop_2_dst_rtype;
reg rob_uop_2_fp_val;
reg [1:0] rob_uop_2_debug_fsrc;
reg [6:0] rob_uop_3_uopc;
reg rob_uop_3_is_rvc;
reg rob_uop_3_is_br;
reg rob_uop_3_is_jalr;
reg rob_uop_3_is_jal;
reg [7:0] rob_uop_3_br_mask;
reg [3:0] rob_uop_3_ftq_idx;
reg rob_uop_3_edge_inst;
reg [5:0] rob_uop_3_pc_lob;
reg [5:0] rob_uop_3_pdst;
reg [5:0] rob_uop_3_stale_pdst;
reg rob_uop_3_is_fencei;
reg rob_uop_3_uses_ldq;
reg rob_uop_3_uses_stq;
reg rob_uop_3_is_sys_pc2epc;
reg rob_uop_3_flush_on_commit;
reg [5:0] rob_uop_3_ldst;
reg rob_uop_3_ldst_val;
reg [1:0] rob_uop_3_dst_rtype;
reg rob_uop_3_fp_val;
reg [1:0] rob_uop_3_debug_fsrc;
reg [6:0] rob_uop_4_uopc;
reg rob_uop_4_is_rvc;
reg rob_uop_4_is_br;
reg rob_uop_4_is_jalr;
reg rob_uop_4_is_jal;
reg [7:0] rob_uop_4_br_mask;
reg [3:0] rob_uop_4_ftq_idx;
reg rob_uop_4_edge_inst;
reg [5:0] rob_uop_4_pc_lob;
reg [5:0] rob_uop_4_pdst;
reg [5:0] rob_uop_4_stale_pdst;
reg rob_uop_4_is_fencei;
reg rob_uop_4_uses_ldq;
reg rob_uop_4_uses_stq;
reg rob_uop_4_is_sys_pc2epc;
reg rob_uop_4_flush_on_commit;
reg [5:0] rob_uop_4_ldst;
reg rob_uop_4_ldst_val;
reg [1:0] rob_uop_4_dst_rtype;
reg rob_uop_4_fp_val;
reg [1:0] rob_uop_4_debug_fsrc;
reg [6:0] rob_uop_5_uopc;
reg rob_uop_5_is_rvc;
reg rob_uop_5_is_br;
reg rob_uop_5_is_jalr;
reg rob_uop_5_is_jal;
reg [7:0] rob_uop_5_br_mask;
reg [3:0] rob_uop_5_ftq_idx;
reg rob_uop_5_edge_inst;
reg [5:0] rob_uop_5_pc_lob;
reg [5:0] rob_uop_5_pdst;
reg [5:0] rob_uop_5_stale_pdst;
reg rob_uop_5_is_fencei;
reg rob_uop_5_uses_ldq;
reg rob_uop_5_uses_stq;
reg rob_uop_5_is_sys_pc2epc;
reg rob_uop_5_flush_on_commit;
reg [5:0] rob_uop_5_ldst;
reg rob_uop_5_ldst_val;
reg [1:0] rob_uop_5_dst_rtype;
reg rob_uop_5_fp_val;
reg [1:0] rob_uop_5_debug_fsrc;
reg [6:0] rob_uop_6_uopc;
reg rob_uop_6_is_rvc;
reg rob_uop_6_is_br;
reg rob_uop_6_is_jalr;
reg rob_uop_6_is_jal;
reg [7:0] rob_uop_6_br_mask;
reg [3:0] rob_uop_6_ftq_idx;
reg rob_uop_6_edge_inst;
reg [5:0] rob_uop_6_pc_lob;
reg [5:0] rob_uop_6_pdst;
reg [5:0] rob_uop_6_stale_pdst;
reg rob_uop_6_is_fencei;
reg rob_uop_6_uses_ldq;
reg rob_uop_6_uses_stq;
reg rob_uop_6_is_sys_pc2epc;
reg rob_uop_6_flush_on_commit;
reg [5:0] rob_uop_6_ldst;
reg rob_uop_6_ldst_val;
reg [1:0] rob_uop_6_dst_rtype;
reg rob_uop_6_fp_val;
reg [1:0] rob_uop_6_debug_fsrc;
reg [6:0] rob_uop_7_uopc;
reg rob_uop_7_is_rvc;
reg rob_uop_7_is_br;
reg rob_uop_7_is_jalr;
reg rob_uop_7_is_jal;
reg [7:0] rob_uop_7_br_mask;
reg [3:0] rob_uop_7_ftq_idx;
reg rob_uop_7_edge_inst;
reg [5:0] rob_uop_7_pc_lob;
reg [5:0] rob_uop_7_pdst;
reg [5:0] rob_uop_7_stale_pdst;
reg rob_uop_7_is_fencei;
reg rob_uop_7_uses_ldq;
reg rob_uop_7_uses_stq;
reg rob_uop_7_is_sys_pc2epc;
reg rob_uop_7_flush_on_commit;
reg [5:0] rob_uop_7_ldst;
reg rob_uop_7_ldst_val;
reg [1:0] rob_uop_7_dst_rtype;
reg rob_uop_7_fp_val;
reg [1:0] rob_uop_7_debug_fsrc;
reg [6:0] rob_uop_8_uopc;
reg rob_uop_8_is_rvc;
reg rob_uop_8_is_br;
reg rob_uop_8_is_jalr;
reg rob_uop_8_is_jal;
reg [7:0] rob_uop_8_br_mask;
reg [3:0] rob_uop_8_ftq_idx;
reg rob_uop_8_edge_inst;
reg [5:0] rob_uop_8_pc_lob;
reg [5:0] rob_uop_8_pdst;
reg [5:0] rob_uop_8_stale_pdst;
reg rob_uop_8_is_fencei;
reg rob_uop_8_uses_ldq;
reg rob_uop_8_uses_stq;
reg rob_uop_8_is_sys_pc2epc;
reg rob_uop_8_flush_on_commit;
reg [5:0] rob_uop_8_ldst;
reg rob_uop_8_ldst_val;
reg [1:0] rob_uop_8_dst_rtype;
reg rob_uop_8_fp_val;
reg [1:0] rob_uop_8_debug_fsrc;
reg [6:0] rob_uop_9_uopc;
reg rob_uop_9_is_rvc;
reg rob_uop_9_is_br;
reg rob_uop_9_is_jalr;
reg rob_uop_9_is_jal;
reg [7:0] rob_uop_9_br_mask;
reg [3:0] rob_uop_9_ftq_idx;
reg rob_uop_9_edge_inst;
reg [5:0] rob_uop_9_pc_lob;
reg [5:0] rob_uop_9_pdst;
reg [5:0] rob_uop_9_stale_pdst;
reg rob_uop_9_is_fencei;
reg rob_uop_9_uses_ldq;
reg rob_uop_9_uses_stq;
reg rob_uop_9_is_sys_pc2epc;
reg rob_uop_9_flush_on_commit;
reg [5:0] rob_uop_9_ldst;
reg rob_uop_9_ldst_val;
reg [1:0] rob_uop_9_dst_rtype;
reg rob_uop_9_fp_val;
reg [1:0] rob_uop_9_debug_fsrc;
reg [6:0] rob_uop_10_uopc;
reg rob_uop_10_is_rvc;
reg rob_uop_10_is_br;
reg rob_uop_10_is_jalr;
reg rob_uop_10_is_jal;
reg [7:0] rob_uop_10_br_mask;
reg [3:0] rob_uop_10_ftq_idx;
reg rob_uop_10_edge_inst;
reg [5:0] rob_uop_10_pc_lob;
reg [5:0] rob_uop_10_pdst;
reg [5:0] rob_uop_10_stale_pdst;
reg rob_uop_10_is_fencei;
reg rob_uop_10_uses_ldq;
reg rob_uop_10_uses_stq;
reg rob_uop_10_is_sys_pc2epc;
reg rob_uop_10_flush_on_commit;
reg [5:0] rob_uop_10_ldst;
reg rob_uop_10_ldst_val;
reg [1:0] rob_uop_10_dst_rtype;
reg rob_uop_10_fp_val;
reg [1:0] rob_uop_10_debug_fsrc;
reg [6:0] rob_uop_11_uopc;
reg rob_uop_11_is_rvc;
reg rob_uop_11_is_br;
reg rob_uop_11_is_jalr;
reg rob_uop_11_is_jal;
reg [7:0] rob_uop_11_br_mask;
reg [3:0] rob_uop_11_ftq_idx;
reg rob_uop_11_edge_inst;
reg [5:0] rob_uop_11_pc_lob;
reg [5:0] rob_uop_11_pdst;
reg [5:0] rob_uop_11_stale_pdst;
reg rob_uop_11_is_fencei;
reg rob_uop_11_uses_ldq;
reg rob_uop_11_uses_stq;
reg rob_uop_11_is_sys_pc2epc;
reg rob_uop_11_flush_on_commit;
reg [5:0] rob_uop_11_ldst;
reg rob_uop_11_ldst_val;
reg [1:0] rob_uop_11_dst_rtype;
reg rob_uop_11_fp_val;
reg [1:0] rob_uop_11_debug_fsrc;
reg [6:0] rob_uop_12_uopc;
reg rob_uop_12_is_rvc;
reg rob_uop_12_is_br;
reg rob_uop_12_is_jalr;
reg rob_uop_12_is_jal;
reg [7:0] rob_uop_12_br_mask;
reg [3:0] rob_uop_12_ftq_idx;
reg rob_uop_12_edge_inst;
reg [5:0] rob_uop_12_pc_lob;
reg [5:0] rob_uop_12_pdst;
reg [5:0] rob_uop_12_stale_pdst;
reg rob_uop_12_is_fencei;
reg rob_uop_12_uses_ldq;
reg rob_uop_12_uses_stq;
reg rob_uop_12_is_sys_pc2epc;
reg rob_uop_12_flush_on_commit;
reg [5:0] rob_uop_12_ldst;
reg rob_uop_12_ldst_val;
reg [1:0] rob_uop_12_dst_rtype;
reg rob_uop_12_fp_val;
reg [1:0] rob_uop_12_debug_fsrc;
reg [6:0] rob_uop_13_uopc;
reg rob_uop_13_is_rvc;
reg rob_uop_13_is_br;
reg rob_uop_13_is_jalr;
reg rob_uop_13_is_jal;
reg [7:0] rob_uop_13_br_mask;
reg [3:0] rob_uop_13_ftq_idx;
reg rob_uop_13_edge_inst;
reg [5:0] rob_uop_13_pc_lob;
reg [5:0] rob_uop_13_pdst;
reg [5:0] rob_uop_13_stale_pdst;
reg rob_uop_13_is_fencei;
reg rob_uop_13_uses_ldq;
reg rob_uop_13_uses_stq;
reg rob_uop_13_is_sys_pc2epc;
reg rob_uop_13_flush_on_commit;
reg [5:0] rob_uop_13_ldst;
reg rob_uop_13_ldst_val;
reg [1:0] rob_uop_13_dst_rtype;
reg rob_uop_13_fp_val;
reg [1:0] rob_uop_13_debug_fsrc;
reg [6:0] rob_uop_14_uopc;
reg rob_uop_14_is_rvc;
reg rob_uop_14_is_br;
reg rob_uop_14_is_jalr;
reg rob_uop_14_is_jal;
reg [7:0] rob_uop_14_br_mask;
reg [3:0] rob_uop_14_ftq_idx;
reg rob_uop_14_edge_inst;
reg [5:0] rob_uop_14_pc_lob;
reg [5:0] rob_uop_14_pdst;
reg [5:0] rob_uop_14_stale_pdst;
reg rob_uop_14_is_fencei;
reg rob_uop_14_uses_ldq;
reg rob_uop_14_uses_stq;
reg rob_uop_14_is_sys_pc2epc;
reg rob_uop_14_flush_on_commit;
reg [5:0] rob_uop_14_ldst;
reg rob_uop_14_ldst_val;
reg [1:0] rob_uop_14_dst_rtype;
reg rob_uop_14_fp_val;
reg [1:0] rob_uop_14_debug_fsrc;
reg [6:0] rob_uop_15_uopc;
reg rob_uop_15_is_rvc;
reg rob_uop_15_is_br;
reg rob_uop_15_is_jalr;
reg rob_uop_15_is_jal;
reg [7:0] rob_uop_15_br_mask;
reg [3:0] rob_uop_15_ftq_idx;
reg rob_uop_15_edge_inst;
reg [5:0] rob_uop_15_pc_lob;
reg [5:0] rob_uop_15_pdst;
reg [5:0] rob_uop_15_stale_pdst;
reg rob_uop_15_is_fencei;
reg rob_uop_15_uses_ldq;
reg rob_uop_15_uses_stq;
reg rob_uop_15_is_sys_pc2epc;
reg rob_uop_15_flush_on_commit;
reg [5:0] rob_uop_15_ldst;
reg rob_uop_15_ldst_val;
reg [1:0] rob_uop_15_dst_rtype;
reg rob_uop_15_fp_val;
reg [1:0] rob_uop_15_debug_fsrc;
reg [6:0] rob_uop_16_uopc;
reg rob_uop_16_is_rvc;
reg rob_uop_16_is_br;
reg rob_uop_16_is_jalr;
reg rob_uop_16_is_jal;
reg [7:0] rob_uop_16_br_mask;
reg [3:0] rob_uop_16_ftq_idx;
reg rob_uop_16_edge_inst;
reg [5:0] rob_uop_16_pc_lob;
reg [5:0] rob_uop_16_pdst;
reg [5:0] rob_uop_16_stale_pdst;
reg rob_uop_16_is_fencei;
reg rob_uop_16_uses_ldq;
reg rob_uop_16_uses_stq;
reg rob_uop_16_is_sys_pc2epc;
reg rob_uop_16_flush_on_commit;
reg [5:0] rob_uop_16_ldst;
reg rob_uop_16_ldst_val;
reg [1:0] rob_uop_16_dst_rtype;
reg rob_uop_16_fp_val;
reg [1:0] rob_uop_16_debug_fsrc;
reg [6:0] rob_uop_17_uopc;
reg rob_uop_17_is_rvc;
reg rob_uop_17_is_br;
reg rob_uop_17_is_jalr;
reg rob_uop_17_is_jal;
reg [7:0] rob_uop_17_br_mask;
reg [3:0] rob_uop_17_ftq_idx;
reg rob_uop_17_edge_inst;
reg [5:0] rob_uop_17_pc_lob;
reg [5:0] rob_uop_17_pdst;
reg [5:0] rob_uop_17_stale_pdst;
reg rob_uop_17_is_fencei;
reg rob_uop_17_uses_ldq;
reg rob_uop_17_uses_stq;
reg rob_uop_17_is_sys_pc2epc;
reg rob_uop_17_flush_on_commit;
reg [5:0] rob_uop_17_ldst;
reg rob_uop_17_ldst_val;
reg [1:0] rob_uop_17_dst_rtype;
reg rob_uop_17_fp_val;
reg [1:0] rob_uop_17_debug_fsrc;
reg [6:0] rob_uop_18_uopc;
reg rob_uop_18_is_rvc;
reg rob_uop_18_is_br;
reg rob_uop_18_is_jalr;
reg rob_uop_18_is_jal;
reg [7:0] rob_uop_18_br_mask;
reg [3:0] rob_uop_18_ftq_idx;
reg rob_uop_18_edge_inst;
reg [5:0] rob_uop_18_pc_lob;
reg [5:0] rob_uop_18_pdst;
reg [5:0] rob_uop_18_stale_pdst;
reg rob_uop_18_is_fencei;
reg rob_uop_18_uses_ldq;
reg rob_uop_18_uses_stq;
reg rob_uop_18_is_sys_pc2epc;
reg rob_uop_18_flush_on_commit;
reg [5:0] rob_uop_18_ldst;
reg rob_uop_18_ldst_val;
reg [1:0] rob_uop_18_dst_rtype;
reg rob_uop_18_fp_val;
reg [1:0] rob_uop_18_debug_fsrc;
reg [6:0] rob_uop_19_uopc;
reg rob_uop_19_is_rvc;
reg rob_uop_19_is_br;
reg rob_uop_19_is_jalr;
reg rob_uop_19_is_jal;
reg [7:0] rob_uop_19_br_mask;
reg [3:0] rob_uop_19_ftq_idx;
reg rob_uop_19_edge_inst;
reg [5:0] rob_uop_19_pc_lob;
reg [5:0] rob_uop_19_pdst;
reg [5:0] rob_uop_19_stale_pdst;
reg rob_uop_19_is_fencei;
reg rob_uop_19_uses_ldq;
reg rob_uop_19_uses_stq;
reg rob_uop_19_is_sys_pc2epc;
reg rob_uop_19_flush_on_commit;
reg [5:0] rob_uop_19_ldst;
reg rob_uop_19_ldst_val;
reg [1:0] rob_uop_19_dst_rtype;
reg rob_uop_19_fp_val;
reg [1:0] rob_uop_19_debug_fsrc;
reg [6:0] rob_uop_20_uopc;
reg rob_uop_20_is_rvc;
reg rob_uop_20_is_br;
reg rob_uop_20_is_jalr;
reg rob_uop_20_is_jal;
reg [7:0] rob_uop_20_br_mask;
reg [3:0] rob_uop_20_ftq_idx;
reg rob_uop_20_edge_inst;
reg [5:0] rob_uop_20_pc_lob;
reg [5:0] rob_uop_20_pdst;
reg [5:0] rob_uop_20_stale_pdst;
reg rob_uop_20_is_fencei;
reg rob_uop_20_uses_ldq;
reg rob_uop_20_uses_stq;
reg rob_uop_20_is_sys_pc2epc;
reg rob_uop_20_flush_on_commit;
reg [5:0] rob_uop_20_ldst;
reg rob_uop_20_ldst_val;
reg [1:0] rob_uop_20_dst_rtype;
reg rob_uop_20_fp_val;
reg [1:0] rob_uop_20_debug_fsrc;
reg [6:0] rob_uop_21_uopc;
reg rob_uop_21_is_rvc;
reg rob_uop_21_is_br;
reg rob_uop_21_is_jalr;
reg rob_uop_21_is_jal;
reg [7:0] rob_uop_21_br_mask;
reg [3:0] rob_uop_21_ftq_idx;
reg rob_uop_21_edge_inst;
reg [5:0] rob_uop_21_pc_lob;
reg [5:0] rob_uop_21_pdst;
reg [5:0] rob_uop_21_stale_pdst;
reg rob_uop_21_is_fencei;
reg rob_uop_21_uses_ldq;
reg rob_uop_21_uses_stq;
reg rob_uop_21_is_sys_pc2epc;
reg rob_uop_21_flush_on_commit;
reg [5:0] rob_uop_21_ldst;
reg rob_uop_21_ldst_val;
reg [1:0] rob_uop_21_dst_rtype;
reg rob_uop_21_fp_val;
reg [1:0] rob_uop_21_debug_fsrc;
reg [6:0] rob_uop_22_uopc;
reg rob_uop_22_is_rvc;
reg rob_uop_22_is_br;
reg rob_uop_22_is_jalr;
reg rob_uop_22_is_jal;
reg [7:0] rob_uop_22_br_mask;
reg [3:0] rob_uop_22_ftq_idx;
reg rob_uop_22_edge_inst;
reg [5:0] rob_uop_22_pc_lob;
reg [5:0] rob_uop_22_pdst;
reg [5:0] rob_uop_22_stale_pdst;
reg rob_uop_22_is_fencei;
reg rob_uop_22_uses_ldq;
reg rob_uop_22_uses_stq;
reg rob_uop_22_is_sys_pc2epc;
reg rob_uop_22_flush_on_commit;
reg [5:0] rob_uop_22_ldst;
reg rob_uop_22_ldst_val;
reg [1:0] rob_uop_22_dst_rtype;
reg rob_uop_22_fp_val;
reg [1:0] rob_uop_22_debug_fsrc;
reg [6:0] rob_uop_23_uopc;
reg rob_uop_23_is_rvc;
reg rob_uop_23_is_br;
reg rob_uop_23_is_jalr;
reg rob_uop_23_is_jal;
reg [7:0] rob_uop_23_br_mask;
reg [3:0] rob_uop_23_ftq_idx;
reg rob_uop_23_edge_inst;
reg [5:0] rob_uop_23_pc_lob;
reg [5:0] rob_uop_23_pdst;
reg [5:0] rob_uop_23_stale_pdst;
reg rob_uop_23_is_fencei;
reg rob_uop_23_uses_ldq;
reg rob_uop_23_uses_stq;
reg rob_uop_23_is_sys_pc2epc;
reg rob_uop_23_flush_on_commit;
reg [5:0] rob_uop_23_ldst;
reg rob_uop_23_ldst_val;
reg [1:0] rob_uop_23_dst_rtype;
reg rob_uop_23_fp_val;
reg [1:0] rob_uop_23_debug_fsrc;
reg [6:0] rob_uop_24_uopc;
reg rob_uop_24_is_rvc;
reg rob_uop_24_is_br;
reg rob_uop_24_is_jalr;
reg rob_uop_24_is_jal;
reg [7:0] rob_uop_24_br_mask;
reg [3:0] rob_uop_24_ftq_idx;
reg rob_uop_24_edge_inst;
reg [5:0] rob_uop_24_pc_lob;
reg [5:0] rob_uop_24_pdst;
reg [5:0] rob_uop_24_stale_pdst;
reg rob_uop_24_is_fencei;
reg rob_uop_24_uses_ldq;
reg rob_uop_24_uses_stq;
reg rob_uop_24_is_sys_pc2epc;
reg rob_uop_24_flush_on_commit;
reg [5:0] rob_uop_24_ldst;
reg rob_uop_24_ldst_val;
reg [1:0] rob_uop_24_dst_rtype;
reg rob_uop_24_fp_val;
reg [1:0] rob_uop_24_debug_fsrc;
reg [6:0] rob_uop_25_uopc;
reg rob_uop_25_is_rvc;
reg rob_uop_25_is_br;
reg rob_uop_25_is_jalr;
reg rob_uop_25_is_jal;
reg [7:0] rob_uop_25_br_mask;
reg [3:0] rob_uop_25_ftq_idx;
reg rob_uop_25_edge_inst;
reg [5:0] rob_uop_25_pc_lob;
reg [5:0] rob_uop_25_pdst;
reg [5:0] rob_uop_25_stale_pdst;
reg rob_uop_25_is_fencei;
reg rob_uop_25_uses_ldq;
reg rob_uop_25_uses_stq;
reg rob_uop_25_is_sys_pc2epc;
reg rob_uop_25_flush_on_commit;
reg [5:0] rob_uop_25_ldst;
reg rob_uop_25_ldst_val;
reg [1:0] rob_uop_25_dst_rtype;
reg rob_uop_25_fp_val;
reg [1:0] rob_uop_25_debug_fsrc;
reg [6:0] rob_uop_26_uopc;
reg rob_uop_26_is_rvc;
reg rob_uop_26_is_br;
reg rob_uop_26_is_jalr;
reg rob_uop_26_is_jal;
reg [7:0] rob_uop_26_br_mask;
reg [3:0] rob_uop_26_ftq_idx;
reg rob_uop_26_edge_inst;
reg [5:0] rob_uop_26_pc_lob;
reg [5:0] rob_uop_26_pdst;
reg [5:0] rob_uop_26_stale_pdst;
reg rob_uop_26_is_fencei;
reg rob_uop_26_uses_ldq;
reg rob_uop_26_uses_stq;
reg rob_uop_26_is_sys_pc2epc;
reg rob_uop_26_flush_on_commit;
reg [5:0] rob_uop_26_ldst;
reg rob_uop_26_ldst_val;
reg [1:0] rob_uop_26_dst_rtype;
reg rob_uop_26_fp_val;
reg [1:0] rob_uop_26_debug_fsrc;
reg [6:0] rob_uop_27_uopc;
reg rob_uop_27_is_rvc;
reg rob_uop_27_is_br;
reg rob_uop_27_is_jalr;
reg rob_uop_27_is_jal;
reg [7:0] rob_uop_27_br_mask;
reg [3:0] rob_uop_27_ftq_idx;
reg rob_uop_27_edge_inst;
reg [5:0] rob_uop_27_pc_lob;
reg [5:0] rob_uop_27_pdst;
reg [5:0] rob_uop_27_stale_pdst;
reg rob_uop_27_is_fencei;
reg rob_uop_27_uses_ldq;
reg rob_uop_27_uses_stq;
reg rob_uop_27_is_sys_pc2epc;
reg rob_uop_27_flush_on_commit;
reg [5:0] rob_uop_27_ldst;
reg rob_uop_27_ldst_val;
reg [1:0] rob_uop_27_dst_rtype;
reg rob_uop_27_fp_val;
reg [1:0] rob_uop_27_debug_fsrc;
reg [6:0] rob_uop_28_uopc;
reg rob_uop_28_is_rvc;
reg rob_uop_28_is_br;
reg rob_uop_28_is_jalr;
reg rob_uop_28_is_jal;
reg [7:0] rob_uop_28_br_mask;
reg [3:0] rob_uop_28_ftq_idx;
reg rob_uop_28_edge_inst;
reg [5:0] rob_uop_28_pc_lob;
reg [5:0] rob_uop_28_pdst;
reg [5:0] rob_uop_28_stale_pdst;
reg rob_uop_28_is_fencei;
reg rob_uop_28_uses_ldq;
reg rob_uop_28_uses_stq;
reg rob_uop_28_is_sys_pc2epc;
reg rob_uop_28_flush_on_commit;
reg [5:0] rob_uop_28_ldst;
reg rob_uop_28_ldst_val;
reg [1:0] rob_uop_28_dst_rtype;
reg rob_uop_28_fp_val;
reg [1:0] rob_uop_28_debug_fsrc;
reg [6:0] rob_uop_29_uopc;
reg rob_uop_29_is_rvc;
reg rob_uop_29_is_br;
reg rob_uop_29_is_jalr;
reg rob_uop_29_is_jal;
reg [7:0] rob_uop_29_br_mask;
reg [3:0] rob_uop_29_ftq_idx;
reg rob_uop_29_edge_inst;
reg [5:0] rob_uop_29_pc_lob;
reg [5:0] rob_uop_29_pdst;
reg [5:0] rob_uop_29_stale_pdst;
reg rob_uop_29_is_fencei;
reg rob_uop_29_uses_ldq;
reg rob_uop_29_uses_stq;
reg rob_uop_29_is_sys_pc2epc;
reg rob_uop_29_flush_on_commit;
reg [5:0] rob_uop_29_ldst;
reg rob_uop_29_ldst_val;
reg [1:0] rob_uop_29_dst_rtype;
reg rob_uop_29_fp_val;
reg [1:0] rob_uop_29_debug_fsrc;
reg [6:0] rob_uop_30_uopc;
reg rob_uop_30_is_rvc;
reg rob_uop_30_is_br;
reg rob_uop_30_is_jalr;
reg rob_uop_30_is_jal;
reg [7:0] rob_uop_30_br_mask;
reg [3:0] rob_uop_30_ftq_idx;
reg rob_uop_30_edge_inst;
reg [5:0] rob_uop_30_pc_lob;
reg [5:0] rob_uop_30_pdst;
reg [5:0] rob_uop_30_stale_pdst;
reg rob_uop_30_is_fencei;
reg rob_uop_30_uses_ldq;
reg rob_uop_30_uses_stq;
reg rob_uop_30_is_sys_pc2epc;
reg rob_uop_30_flush_on_commit;
reg [5:0] rob_uop_30_ldst;
reg rob_uop_30_ldst_val;
reg [1:0] rob_uop_30_dst_rtype;
reg rob_uop_30_fp_val;
reg [1:0] rob_uop_30_debug_fsrc;
reg [6:0] rob_uop_31_uopc;
reg rob_uop_31_is_rvc;
reg rob_uop_31_is_br;
reg rob_uop_31_is_jalr;
reg rob_uop_31_is_jal;
reg [7:0] rob_uop_31_br_mask;
reg [3:0] rob_uop_31_ftq_idx;
reg rob_uop_31_edge_inst;
reg [5:0] rob_uop_31_pc_lob;
reg [5:0] rob_uop_31_pdst;
reg [5:0] rob_uop_31_stale_pdst;
reg rob_uop_31_is_fencei;
reg rob_uop_31_uses_ldq;
reg rob_uop_31_uses_stq;
reg rob_uop_31_is_sys_pc2epc;
reg rob_uop_31_flush_on_commit;
reg [5:0] rob_uop_31_ldst;
reg rob_uop_31_ldst_val;
reg [1:0] rob_uop_31_dst_rtype;
reg rob_uop_31_fp_val;
reg [1:0] rob_uop_31_debug_fsrc;
reg rob_exception_0;
reg rob_exception_1;
reg rob_exception_2;
reg rob_exception_3;
reg rob_exception_4;
reg rob_exception_5;
reg rob_exception_6;
reg rob_exception_7;
reg rob_exception_8;
reg rob_exception_9;
reg rob_exception_10;
reg rob_exception_11;
reg rob_exception_12;
reg rob_exception_13;
reg rob_exception_14;
reg rob_exception_15;
reg rob_exception_16;
reg rob_exception_17;
reg rob_exception_18;
reg rob_exception_19;
reg rob_exception_20;
reg rob_exception_21;
reg rob_exception_22;
reg rob_exception_23;
reg rob_exception_24;
reg rob_exception_25;
reg rob_exception_26;
reg rob_exception_27;
reg rob_exception_28;
reg rob_exception_29;
reg rob_exception_30;
reg rob_exception_31;
reg rob_predicated_0;
reg rob_predicated_1;
reg rob_predicated_2;
reg rob_predicated_3;
reg rob_predicated_4;
reg rob_predicated_5;
reg rob_predicated_6;
reg rob_predicated_7;
reg rob_predicated_8;
reg rob_predicated_9;
reg rob_predicated_10;
reg rob_predicated_11;
reg rob_predicated_12;
reg rob_predicated_13;
reg rob_predicated_14;
reg rob_predicated_15;
reg rob_predicated_16;
reg rob_predicated_17;
reg rob_predicated_18;
reg rob_predicated_19;
reg rob_predicated_20;
reg rob_predicated_21;
reg rob_predicated_22;
reg rob_predicated_23;
reg rob_predicated_24;
reg rob_predicated_25;
reg rob_predicated_26;
reg rob_predicated_27;
reg rob_predicated_28;
reg rob_predicated_29;
reg rob_predicated_30;
reg rob_predicated_31;
wire [31:0] _GEN = {{rob_val_31}, {rob_val_30}, {rob_val_29}, {rob_val_28}, {rob_val_27}, {rob_val_26}, {rob_val_25}, {rob_val_24}, {rob_val_23}, {rob_val_22}, {rob_val_21}, {rob_val_20}, {rob_val_19}, {rob_val_18}, {rob_val_17}, {rob_val_16}, {rob_val_15}, {rob_val_14}, {rob_val_13}, {rob_val_12}, {rob_val_11}, {rob_val_10}, {rob_val_9}, {rob_val_8}, {rob_val_7}, {rob_val_6}, {rob_val_5}, {rob_val_4}, {rob_val_3}, {rob_val_2}, {rob_val_1}, {rob_val_0}};
wire [31:0] _GEN_0 = {{rob_bsy_31}, {rob_bsy_30}, {rob_bsy_29}, {rob_bsy_28}, {rob_bsy_27}, {rob_bsy_26}, {rob_bsy_25}, {rob_bsy_24}, {rob_bsy_23}, {rob_bsy_22}, {rob_bsy_21}, {rob_bsy_20}, {rob_bsy_19}, {rob_bsy_18}, {rob_bsy_17}, {rob_bsy_16}, {rob_bsy_15}, {rob_bsy_14}, {rob_bsy_13}, {rob_bsy_12}, {rob_bsy_11}, {rob_bsy_10}, {rob_bsy_9}, {rob_bsy_8}, {rob_bsy_7}, {rob_bsy_6}, {rob_bsy_5}, {rob_bsy_4}, {rob_bsy_3}, {rob_bsy_2}, {rob_bsy_1}, {rob_bsy_0}};
wire _GEN_1 = io_lxcpt_valid & io_lxcpt_bits_cause != 5'h10 & ~reset;
wire [31:0] _GEN_2 = {{rob_unsafe_31}, {rob_unsafe_30}, {rob_unsafe_29}, {rob_unsafe_28}, {rob_unsafe_27}, {rob_unsafe_26}, {rob_unsafe_25}, {rob_unsafe_24}, {rob_unsafe_23}, {rob_unsafe_22}, {rob_unsafe_21}, {rob_unsafe_20}, {rob_unsafe_19}, {rob_unsafe_18}, {rob_unsafe_17}, {rob_unsafe_16}, {rob_unsafe_15}, {rob_unsafe_14}, {rob_unsafe_13}, {rob_unsafe_12}, {rob_unsafe_11}, {rob_unsafe_10}, {rob_unsafe_9}, {rob_unsafe_8}, {rob_unsafe_7}, {rob_unsafe_6}, {rob_unsafe_5}, {rob_unsafe_4}, {rob_unsafe_3}, {rob_unsafe_2}, {rob_unsafe_1}, {rob_unsafe_0}};
wire rob_head_vals_0 = _GEN[rob_head];
wire [31:0] _GEN_3 = {{rob_exception_31}, {rob_exception_30}, {rob_exception_29}, {rob_exception_28}, {rob_exception_27}, {rob_exception_26}, {rob_exception_25}, {rob_exception_24}, {rob_exception_23}, {rob_exception_22}, {rob_exception_21}, {rob_exception_20}, {rob_exception_19}, {rob_exception_18}, {rob_exception_17}, {rob_exception_16}, {rob_exception_15}, {rob_exception_14}, {rob_exception_13}, {rob_exception_12}, {rob_exception_11}, {rob_exception_10}, {rob_exception_9}, {rob_exception_8}, {rob_exception_7}, {rob_exception_6}, {rob_exception_5}, {rob_exception_4}, {rob_exception_3}, {rob_exception_2}, {rob_exception_1}, {rob_exception_0}};
wire can_throw_exception_0 = rob_head_vals_0 & _GEN_3[rob_head];
wire [31:0] _GEN_4 = {{rob_predicated_31}, {rob_predicated_30}, {rob_predicated_29}, {rob_predicated_28}, {rob_predicated_27}, {rob_predicated_26}, {rob_predicated_25}, {rob_predicated_24}, {rob_predicated_23}, {rob_predicated_22}, {rob_predicated_21}, {rob_predicated_20}, {rob_predicated_19}, {rob_predicated_18}, {rob_predicated_17}, {rob_predicated_16}, {rob_predicated_15}, {rob_predicated_14}, {rob_predicated_13}, {rob_predicated_12}, {rob_predicated_11}, {rob_predicated_10}, {rob_predicated_9}, {rob_predicated_8}, {rob_predicated_7}, {rob_predicated_6}, {rob_predicated_5}, {rob_predicated_4}, {rob_predicated_3}, {rob_predicated_2}, {rob_predicated_1}, {rob_predicated_0}};
wire [31:0][6:0] _GEN_5 = {{rob_uop_31_uopc}, {rob_uop_30_uopc}, {rob_uop_29_uopc}, {rob_uop_28_uopc}, {rob_uop_27_uopc}, {rob_uop_26_uopc}, {rob_uop_25_uopc}, {rob_uop_24_uopc}, {rob_uop_23_uopc}, {rob_uop_22_uopc}, {rob_uop_21_uopc}, {rob_uop_20_uopc}, {rob_uop_19_uopc}, {rob_uop_18_uopc}, {rob_uop_17_uopc}, {rob_uop_16_uopc}, {rob_uop_15_uopc}, {rob_uop_14_uopc}, {rob_uop_13_uopc}, {rob_uop_12_uopc}, {rob_uop_11_uopc}, {rob_uop_10_uopc}, {rob_uop_9_uopc}, {rob_uop_8_uopc}, {rob_uop_7_uopc}, {rob_uop_6_uopc}, {rob_uop_5_uopc}, {rob_uop_4_uopc}, {rob_uop_3_uopc}, {rob_uop_2_uopc}, {rob_uop_1_uopc}, {rob_uop_0_uopc}};
wire [31:0] _GEN_6 = {{rob_uop_31_is_rvc}, {rob_uop_30_is_rvc}, {rob_uop_29_is_rvc}, {rob_uop_28_is_rvc}, {rob_uop_27_is_rvc}, {rob_uop_26_is_rvc}, {rob_uop_25_is_rvc}, {rob_uop_24_is_rvc}, {rob_uop_23_is_rvc}, {rob_uop_22_is_rvc}, {rob_uop_21_is_rvc}, {rob_uop_20_is_rvc}, {rob_uop_19_is_rvc}, {rob_uop_18_is_rvc}, {rob_uop_17_is_rvc}, {rob_uop_16_is_rvc}, {rob_uop_15_is_rvc}, {rob_uop_14_is_rvc}, {rob_uop_13_is_rvc}, {rob_uop_12_is_rvc}, {rob_uop_11_is_rvc}, {rob_uop_10_is_rvc}, {rob_uop_9_is_rvc}, {rob_uop_8_is_rvc}, {rob_uop_7_is_rvc}, {rob_uop_6_is_rvc}, {rob_uop_5_is_rvc}, {rob_uop_4_is_rvc}, {rob_uop_3_is_rvc}, {rob_uop_2_is_rvc}, {rob_uop_1_is_rvc}, {rob_uop_0_is_rvc}};
wire [31:0] _GEN_7 = {{rob_uop_31_is_br}, {rob_uop_30_is_br}, {rob_uop_29_is_br}, {rob_uop_28_is_br}, {rob_uop_27_is_br}, {rob_uop_26_is_br}, {rob_uop_25_is_br}, {rob_uop_24_is_br}, {rob_uop_23_is_br}, {rob_uop_22_is_br}, {rob_uop_21_is_br}, {rob_uop_20_is_br}, {rob_uop_19_is_br}, {rob_uop_18_is_br}, {rob_uop_17_is_br}, {rob_uop_16_is_br}, {rob_uop_15_is_br}, {rob_uop_14_is_br}, {rob_uop_13_is_br}, {rob_uop_12_is_br}, {rob_uop_11_is_br}, {rob_uop_10_is_br}, {rob_uop_9_is_br}, {rob_uop_8_is_br}, {rob_uop_7_is_br}, {rob_uop_6_is_br}, {rob_uop_5_is_br}, {rob_uop_4_is_br}, {rob_uop_3_is_br}, {rob_uop_2_is_br}, {rob_uop_1_is_br}, {rob_uop_0_is_br}};
wire [31:0] _GEN_8 = {{rob_uop_31_is_jalr}, {rob_uop_30_is_jalr}, {rob_uop_29_is_jalr}, {rob_uop_28_is_jalr}, {rob_uop_27_is_jalr}, {rob_uop_26_is_jalr}, {rob_uop_25_is_jalr}, {rob_uop_24_is_jalr}, {rob_uop_23_is_jalr}, {rob_uop_22_is_jalr}, {rob_uop_21_is_jalr}, {rob_uop_20_is_jalr}, {rob_uop_19_is_jalr}, {rob_uop_18_is_jalr}, {rob_uop_17_is_jalr}, {rob_uop_16_is_jalr}, {rob_uop_15_is_jalr}, {rob_uop_14_is_jalr}, {rob_uop_13_is_jalr}, {rob_uop_12_is_jalr}, {rob_uop_11_is_jalr}, {rob_uop_10_is_jalr}, {rob_uop_9_is_jalr}, {rob_uop_8_is_jalr}, {rob_uop_7_is_jalr}, {rob_uop_6_is_jalr}, {rob_uop_5_is_jalr}, {rob_uop_4_is_jalr}, {rob_uop_3_is_jalr}, {rob_uop_2_is_jalr}, {rob_uop_1_is_jalr}, {rob_uop_0_is_jalr}};
wire [31:0] _GEN_9 = {{rob_uop_31_is_jal}, {rob_uop_30_is_jal}, {rob_uop_29_is_jal}, {rob_uop_28_is_jal}, {rob_uop_27_is_jal}, {rob_uop_26_is_jal}, {rob_uop_25_is_jal}, {rob_uop_24_is_jal}, {rob_uop_23_is_jal}, {rob_uop_22_is_jal}, {rob_uop_21_is_jal}, {rob_uop_20_is_jal}, {rob_uop_19_is_jal}, {rob_uop_18_is_jal}, {rob_uop_17_is_jal}, {rob_uop_16_is_jal}, {rob_uop_15_is_jal}, {rob_uop_14_is_jal}, {rob_uop_13_is_jal}, {rob_uop_12_is_jal}, {rob_uop_11_is_jal}, {rob_uop_10_is_jal}, {rob_uop_9_is_jal}, {rob_uop_8_is_jal}, {rob_uop_7_is_jal}, {rob_uop_6_is_jal}, {rob_uop_5_is_jal}, {rob_uop_4_is_jal}, {rob_uop_3_is_jal}, {rob_uop_2_is_jal}, {rob_uop_1_is_jal}, {rob_uop_0_is_jal}};
wire [31:0][3:0] _GEN_10 = {{rob_uop_31_ftq_idx}, {rob_uop_30_ftq_idx}, {rob_uop_29_ftq_idx}, {rob_uop_28_ftq_idx}, {rob_uop_27_ftq_idx}, {rob_uop_26_ftq_idx}, {rob_uop_25_ftq_idx}, {rob_uop_24_ftq_idx}, {rob_uop_23_ftq_idx}, {rob_uop_22_ftq_idx}, {rob_uop_21_ftq_idx}, {rob_uop_20_ftq_idx}, {rob_uop_19_ftq_idx}, {rob_uop_18_ftq_idx}, {rob_uop_17_ftq_idx}, {rob_uop_16_ftq_idx}, {rob_uop_15_ftq_idx}, {rob_uop_14_ftq_idx}, {rob_uop_13_ftq_idx}, {rob_uop_12_ftq_idx}, {rob_uop_11_ftq_idx}, {rob_uop_10_ftq_idx}, {rob_uop_9_ftq_idx}, {rob_uop_8_ftq_idx}, {rob_uop_7_ftq_idx}, {rob_uop_6_ftq_idx}, {rob_uop_5_ftq_idx}, {rob_uop_4_ftq_idx}, {rob_uop_3_ftq_idx}, {rob_uop_2_ftq_idx}, {rob_uop_1_ftq_idx}, {rob_uop_0_ftq_idx}};
wire [31:0] _GEN_11 = {{rob_uop_31_edge_inst}, {rob_uop_30_edge_inst}, {rob_uop_29_edge_inst}, {rob_uop_28_edge_inst}, {rob_uop_27_edge_inst}, {rob_uop_26_edge_inst}, {rob_uop_25_edge_inst}, {rob_uop_24_edge_inst}, {rob_uop_23_edge_inst}, {rob_uop_22_edge_inst}, {rob_uop_21_edge_inst}, {rob_uop_20_edge_inst}, {rob_uop_19_edge_inst}, {rob_uop_18_edge_inst}, {rob_uop_17_edge_inst}, {rob_uop_16_edge_inst}, {rob_uop_15_edge_inst}, {rob_uop_14_edge_inst}, {rob_uop_13_edge_inst}, {rob_uop_12_edge_inst}, {rob_uop_11_edge_inst}, {rob_uop_10_edge_inst}, {rob_uop_9_edge_inst}, {rob_uop_8_edge_inst}, {rob_uop_7_edge_inst}, {rob_uop_6_edge_inst}, {rob_uop_5_edge_inst}, {rob_uop_4_edge_inst}, {rob_uop_3_edge_inst}, {rob_uop_2_edge_inst}, {rob_uop_1_edge_inst}, {rob_uop_0_edge_inst}};
wire [31:0][5:0] _GEN_12 = {{rob_uop_31_pc_lob}, {rob_uop_30_pc_lob}, {rob_uop_29_pc_lob}, {rob_uop_28_pc_lob}, {rob_uop_27_pc_lob}, {rob_uop_26_pc_lob}, {rob_uop_25_pc_lob}, {rob_uop_24_pc_lob}, {rob_uop_23_pc_lob}, {rob_uop_22_pc_lob}, {rob_uop_21_pc_lob}, {rob_uop_20_pc_lob}, {rob_uop_19_pc_lob}, {rob_uop_18_pc_lob}, {rob_uop_17_pc_lob}, {rob_uop_16_pc_lob}, {rob_uop_15_pc_lob}, {rob_uop_14_pc_lob}, {rob_uop_13_pc_lob}, {rob_uop_12_pc_lob}, {rob_uop_11_pc_lob}, {rob_uop_10_pc_lob}, {rob_uop_9_pc_lob}, {rob_uop_8_pc_lob}, {rob_uop_7_pc_lob}, {rob_uop_6_pc_lob}, {rob_uop_5_pc_lob}, {rob_uop_4_pc_lob}, {rob_uop_3_pc_lob}, {rob_uop_2_pc_lob}, {rob_uop_1_pc_lob}, {rob_uop_0_pc_lob}};
wire [31:0][5:0] _GEN_13 = {{rob_uop_31_pdst}, {rob_uop_30_pdst}, {rob_uop_29_pdst}, {rob_uop_28_pdst}, {rob_uop_27_pdst}, {rob_uop_26_pdst}, {rob_uop_25_pdst}, {rob_uop_24_pdst}, {rob_uop_23_pdst}, {rob_uop_22_pdst}, {rob_uop_21_pdst}, {rob_uop_20_pdst}, {rob_uop_19_pdst}, {rob_uop_18_pdst}, {rob_uop_17_pdst}, {rob_uop_16_pdst}, {rob_uop_15_pdst}, {rob_uop_14_pdst}, {rob_uop_13_pdst}, {rob_uop_12_pdst}, {rob_uop_11_pdst}, {rob_uop_10_pdst}, {rob_uop_9_pdst}, {rob_uop_8_pdst}, {rob_uop_7_pdst}, {rob_uop_6_pdst}, {rob_uop_5_pdst}, {rob_uop_4_pdst}, {rob_uop_3_pdst}, {rob_uop_2_pdst}, {rob_uop_1_pdst}, {rob_uop_0_pdst}};
wire [31:0][5:0] _GEN_14 = {{rob_uop_31_stale_pdst}, {rob_uop_30_stale_pdst}, {rob_uop_29_stale_pdst}, {rob_uop_28_stale_pdst}, {rob_uop_27_stale_pdst}, {rob_uop_26_stale_pdst}, {rob_uop_25_stale_pdst}, {rob_uop_24_stale_pdst}, {rob_uop_23_stale_pdst}, {rob_uop_22_stale_pdst}, {rob_uop_21_stale_pdst}, {rob_uop_20_stale_pdst}, {rob_uop_19_stale_pdst}, {rob_uop_18_stale_pdst}, {rob_uop_17_stale_pdst}, {rob_uop_16_stale_pdst}, {rob_uop_15_stale_pdst}, {rob_uop_14_stale_pdst}, {rob_uop_13_stale_pdst}, {rob_uop_12_stale_pdst}, {rob_uop_11_stale_pdst}, {rob_uop_10_stale_pdst}, {rob_uop_9_stale_pdst}, {rob_uop_8_stale_pdst}, {rob_uop_7_stale_pdst}, {rob_uop_6_stale_pdst}, {rob_uop_5_stale_pdst}, {rob_uop_4_stale_pdst}, {rob_uop_3_stale_pdst}, {rob_uop_2_stale_pdst}, {rob_uop_1_stale_pdst}, {rob_uop_0_stale_pdst}};
wire [31:0] _GEN_15 = {{rob_uop_31_is_fencei}, {rob_uop_30_is_fencei}, {rob_uop_29_is_fencei}, {rob_uop_28_is_fencei}, {rob_uop_27_is_fencei}, {rob_uop_26_is_fencei}, {rob_uop_25_is_fencei}, {rob_uop_24_is_fencei}, {rob_uop_23_is_fencei}, {rob_uop_22_is_fencei}, {rob_uop_21_is_fencei}, {rob_uop_20_is_fencei}, {rob_uop_19_is_fencei}, {rob_uop_18_is_fencei}, {rob_uop_17_is_fencei}, {rob_uop_16_is_fencei}, {rob_uop_15_is_fencei}, {rob_uop_14_is_fencei}, {rob_uop_13_is_fencei}, {rob_uop_12_is_fencei}, {rob_uop_11_is_fencei}, {rob_uop_10_is_fencei}, {rob_uop_9_is_fencei}, {rob_uop_8_is_fencei}, {rob_uop_7_is_fencei}, {rob_uop_6_is_fencei}, {rob_uop_5_is_fencei}, {rob_uop_4_is_fencei}, {rob_uop_3_is_fencei}, {rob_uop_2_is_fencei}, {rob_uop_1_is_fencei}, {rob_uop_0_is_fencei}};
wire [31:0] _GEN_16 = {{rob_uop_31_uses_ldq}, {rob_uop_30_uses_ldq}, {rob_uop_29_uses_ldq}, {rob_uop_28_uses_ldq}, {rob_uop_27_uses_ldq}, {rob_uop_26_uses_ldq}, {rob_uop_25_uses_ldq}, {rob_uop_24_uses_ldq}, {rob_uop_23_uses_ldq}, {rob_uop_22_uses_ldq}, {rob_uop_21_uses_ldq}, {rob_uop_20_uses_ldq}, {rob_uop_19_uses_ldq}, {rob_uop_18_uses_ldq}, {rob_uop_17_uses_ldq}, {rob_uop_16_uses_ldq}, {rob_uop_15_uses_ldq}, {rob_uop_14_uses_ldq}, {rob_uop_13_uses_ldq}, {rob_uop_12_uses_ldq}, {rob_uop_11_uses_ldq}, {rob_uop_10_uses_ldq}, {rob_uop_9_uses_ldq}, {rob_uop_8_uses_ldq}, {rob_uop_7_uses_ldq}, {rob_uop_6_uses_ldq}, {rob_uop_5_uses_ldq}, {rob_uop_4_uses_ldq}, {rob_uop_3_uses_ldq}, {rob_uop_2_uses_ldq}, {rob_uop_1_uses_ldq}, {rob_uop_0_uses_ldq}};
wire [31:0] _GEN_17 = {{rob_uop_31_uses_stq}, {rob_uop_30_uses_stq}, {rob_uop_29_uses_stq}, {rob_uop_28_uses_stq}, {rob_uop_27_uses_stq}, {rob_uop_26_uses_stq}, {rob_uop_25_uses_stq}, {rob_uop_24_uses_stq}, {rob_uop_23_uses_stq}, {rob_uop_22_uses_stq}, {rob_uop_21_uses_stq}, {rob_uop_20_uses_stq}, {rob_uop_19_uses_stq}, {rob_uop_18_uses_stq}, {rob_uop_17_uses_stq}, {rob_uop_16_uses_stq}, {rob_uop_15_uses_stq}, {rob_uop_14_uses_stq}, {rob_uop_13_uses_stq}, {rob_uop_12_uses_stq}, {rob_uop_11_uses_stq}, {rob_uop_10_uses_stq}, {rob_uop_9_uses_stq}, {rob_uop_8_uses_stq}, {rob_uop_7_uses_stq}, {rob_uop_6_uses_stq}, {rob_uop_5_uses_stq}, {rob_uop_4_uses_stq}, {rob_uop_3_uses_stq}, {rob_uop_2_uses_stq}, {rob_uop_1_uses_stq}, {rob_uop_0_uses_stq}};
wire [31:0] _GEN_18 = {{rob_uop_31_is_sys_pc2epc}, {rob_uop_30_is_sys_pc2epc}, {rob_uop_29_is_sys_pc2epc}, {rob_uop_28_is_sys_pc2epc}, {rob_uop_27_is_sys_pc2epc}, {rob_uop_26_is_sys_pc2epc}, {rob_uop_25_is_sys_pc2epc}, {rob_uop_24_is_sys_pc2epc}, {rob_uop_23_is_sys_pc2epc}, {rob_uop_22_is_sys_pc2epc}, {rob_uop_21_is_sys_pc2epc}, {rob_uop_20_is_sys_pc2epc}, {rob_uop_19_is_sys_pc2epc}, {rob_uop_18_is_sys_pc2epc}, {rob_uop_17_is_sys_pc2epc}, {rob_uop_16_is_sys_pc2epc}, {rob_uop_15_is_sys_pc2epc}, {rob_uop_14_is_sys_pc2epc}, {rob_uop_13_is_sys_pc2epc}, {rob_uop_12_is_sys_pc2epc}, {rob_uop_11_is_sys_pc2epc}, {rob_uop_10_is_sys_pc2epc}, {rob_uop_9_is_sys_pc2epc}, {rob_uop_8_is_sys_pc2epc}, {rob_uop_7_is_sys_pc2epc}, {rob_uop_6_is_sys_pc2epc}, {rob_uop_5_is_sys_pc2epc}, {rob_uop_4_is_sys_pc2epc}, {rob_uop_3_is_sys_pc2epc}, {rob_uop_2_is_sys_pc2epc}, {rob_uop_1_is_sys_pc2epc}, {rob_uop_0_is_sys_pc2epc}};
wire [31:0] _GEN_19 = {{rob_uop_31_flush_on_commit}, {rob_uop_30_flush_on_commit}, {rob_uop_29_flush_on_commit}, {rob_uop_28_flush_on_commit}, {rob_uop_27_flush_on_commit}, {rob_uop_26_flush_on_commit}, {rob_uop_25_flush_on_commit}, {rob_uop_24_flush_on_commit}, {rob_uop_23_flush_on_commit}, {rob_uop_22_flush_on_commit}, {rob_uop_21_flush_on_commit}, {rob_uop_20_flush_on_commit}, {rob_uop_19_flush_on_commit}, {rob_uop_18_flush_on_commit}, {rob_uop_17_flush_on_commit}, {rob_uop_16_flush_on_commit}, {rob_uop_15_flush_on_commit}, {rob_uop_14_flush_on_commit}, {rob_uop_13_flush_on_commit}, {rob_uop_12_flush_on_commit}, {rob_uop_11_flush_on_commit}, {rob_uop_10_flush_on_commit}, {rob_uop_9_flush_on_commit}, {rob_uop_8_flush_on_commit}, {rob_uop_7_flush_on_commit}, {rob_uop_6_flush_on_commit}, {rob_uop_5_flush_on_commit}, {rob_uop_4_flush_on_commit}, {rob_uop_3_flush_on_commit}, {rob_uop_2_flush_on_commit}, {rob_uop_1_flush_on_commit}, {rob_uop_0_flush_on_commit}};
wire [31:0][5:0] _GEN_20 = {{rob_uop_31_ldst}, {rob_uop_30_ldst}, {rob_uop_29_ldst}, {rob_uop_28_ldst}, {rob_uop_27_ldst}, {rob_uop_26_ldst}, {rob_uop_25_ldst}, {rob_uop_24_ldst}, {rob_uop_23_ldst}, {rob_uop_22_ldst}, {rob_uop_21_ldst}, {rob_uop_20_ldst}, {rob_uop_19_ldst}, {rob_uop_18_ldst}, {rob_uop_17_ldst}, {rob_uop_16_ldst}, {rob_uop_15_ldst}, {rob_uop_14_ldst}, {rob_uop_13_ldst}, {rob_uop_12_ldst}, {rob_uop_11_ldst}, {rob_uop_10_ldst}, {rob_uop_9_ldst}, {rob_uop_8_ldst}, {rob_uop_7_ldst}, {rob_uop_6_ldst}, {rob_uop_5_ldst}, {rob_uop_4_ldst}, {rob_uop_3_ldst}, {rob_uop_2_ldst}, {rob_uop_1_ldst}, {rob_uop_0_ldst}};
wire [31:0] _GEN_21 = {{rob_uop_31_ldst_val}, {rob_uop_30_ldst_val}, {rob_uop_29_ldst_val}, {rob_uop_28_ldst_val}, {rob_uop_27_ldst_val}, {rob_uop_26_ldst_val}, {rob_uop_25_ldst_val}, {rob_uop_24_ldst_val}, {rob_uop_23_ldst_val}, {rob_uop_22_ldst_val}, {rob_uop_21_ldst_val}, {rob_uop_20_ldst_val}, {rob_uop_19_ldst_val}, {rob_uop_18_ldst_val}, {rob_uop_17_ldst_val}, {rob_uop_16_ldst_val}, {rob_uop_15_ldst_val}, {rob_uop_14_ldst_val}, {rob_uop_13_ldst_val}, {rob_uop_12_ldst_val}, {rob_uop_11_ldst_val}, {rob_uop_10_ldst_val}, {rob_uop_9_ldst_val}, {rob_uop_8_ldst_val}, {rob_uop_7_ldst_val}, {rob_uop_6_ldst_val}, {rob_uop_5_ldst_val}, {rob_uop_4_ldst_val}, {rob_uop_3_ldst_val}, {rob_uop_2_ldst_val}, {rob_uop_1_ldst_val}, {rob_uop_0_ldst_val}};
wire [31:0][1:0] _GEN_22 = {{rob_uop_31_dst_rtype}, {rob_uop_30_dst_rtype}, {rob_uop_29_dst_rtype}, {rob_uop_28_dst_rtype}, {rob_uop_27_dst_rtype}, {rob_uop_26_dst_rtype}, {rob_uop_25_dst_rtype}, {rob_uop_24_dst_rtype}, {rob_uop_23_dst_rtype}, {rob_uop_22_dst_rtype}, {rob_uop_21_dst_rtype}, {rob_uop_20_dst_rtype}, {rob_uop_19_dst_rtype}, {rob_uop_18_dst_rtype}, {rob_uop_17_dst_rtype}, {rob_uop_16_dst_rtype}, {rob_uop_15_dst_rtype}, {rob_uop_14_dst_rtype}, {rob_uop_13_dst_rtype}, {rob_uop_12_dst_rtype}, {rob_uop_11_dst_rtype}, {rob_uop_10_dst_rtype}, {rob_uop_9_dst_rtype}, {rob_uop_8_dst_rtype}, {rob_uop_7_dst_rtype}, {rob_uop_6_dst_rtype}, {rob_uop_5_dst_rtype}, {rob_uop_4_dst_rtype}, {rob_uop_3_dst_rtype}, {rob_uop_2_dst_rtype}, {rob_uop_1_dst_rtype}, {rob_uop_0_dst_rtype}};
wire [31:0] _GEN_23 = {{rob_uop_31_fp_val}, {rob_uop_30_fp_val}, {rob_uop_29_fp_val}, {rob_uop_28_fp_val}, {rob_uop_27_fp_val}, {rob_uop_26_fp_val}, {rob_uop_25_fp_val}, {rob_uop_24_fp_val}, {rob_uop_23_fp_val}, {rob_uop_22_fp_val}, {rob_uop_21_fp_val}, {rob_uop_20_fp_val}, {rob_uop_19_fp_val}, {rob_uop_18_fp_val}, {rob_uop_17_fp_val}, {rob_uop_16_fp_val}, {rob_uop_15_fp_val}, {rob_uop_14_fp_val}, {rob_uop_13_fp_val}, {rob_uop_12_fp_val}, {rob_uop_11_fp_val}, {rob_uop_10_fp_val}, {rob_uop_9_fp_val}, {rob_uop_8_fp_val}, {rob_uop_7_fp_val}, {rob_uop_6_fp_val}, {rob_uop_5_fp_val}, {rob_uop_4_fp_val}, {rob_uop_3_fp_val}, {rob_uop_2_fp_val}, {rob_uop_1_fp_val}, {rob_uop_0_fp_val}};
wire [31:0][1:0] _GEN_24 = {{rob_uop_31_debug_fsrc}, {rob_uop_30_debug_fsrc}, {rob_uop_29_debug_fsrc}, {rob_uop_28_debug_fsrc}, {rob_uop_27_debug_fsrc}, {rob_uop_26_debug_fsrc}, {rob_uop_25_debug_fsrc}, {rob_uop_24_debug_fsrc}, {rob_uop_23_debug_fsrc}, {rob_uop_22_debug_fsrc}, {rob_uop_21_debug_fsrc}, {rob_uop_20_debug_fsrc}, {rob_uop_19_debug_fsrc}, {rob_uop_18_debug_fsrc}, {rob_uop_17_debug_fsrc}, {rob_uop_16_debug_fsrc}, {rob_uop_15_debug_fsrc}, {rob_uop_14_debug_fsrc}, {rob_uop_13_debug_fsrc}, {rob_uop_12_debug_fsrc}, {rob_uop_11_debug_fsrc}, {rob_uop_10_debug_fsrc}, {rob_uop_9_debug_fsrc}, {rob_uop_8_debug_fsrc}, {rob_uop_7_debug_fsrc}, {rob_uop_6_debug_fsrc}, {rob_uop_5_debug_fsrc}, {rob_uop_4_debug_fsrc}, {rob_uop_3_debug_fsrc}, {rob_uop_2_debug_fsrc}, {rob_uop_1_debug_fsrc}, {rob_uop_0_debug_fsrc}};
wire rbk_row = io_commit_rollback_0 & ~full;
wire io_commit_rbk_valids_0_0 = rbk_row & _GEN[com_idx];
wire [31:0][4:0] _GEN_25 = {{rob_fflags_0_31}, {rob_fflags_0_30}, {rob_fflags_0_29}, {rob_fflags_0_28}, {rob_fflags_0_27}, {rob_fflags_0_26}, {rob_fflags_0_25}, {rob_fflags_0_24}, {rob_fflags_0_23}, {rob_fflags_0_22}, {rob_fflags_0_21}, {rob_fflags_0_20}, {rob_fflags_0_19}, {rob_fflags_0_18}, {rob_fflags_0_17}, {rob_fflags_0_16}, {rob_fflags_0_15}, {rob_fflags_0_14}, {rob_fflags_0_13}, {rob_fflags_0_12}, {rob_fflags_0_11}, {rob_fflags_0_10}, {rob_fflags_0_9}, {rob_fflags_0_8}, {rob_fflags_0_7}, {rob_fflags_0_6}, {rob_fflags_0_5}, {rob_fflags_0_4}, {rob_fflags_0_3}, {rob_fflags_0_2}, {rob_fflags_0_1}, {rob_fflags_0_0}};
wire [4:0] rob_head_fflags_0 = _GEN_25[rob_head];
reg block_commit_REG;
reg block_commit_REG_1;
reg block_commit_REG_2;
wire block_commit = rob_state != 2'h1 & rob_state != 2'h3 | block_commit_REG | block_commit_REG_2;
wire exception_thrown = can_throw_exception_0 & ~block_commit;
assign will_commit_0 = rob_head_vals_0 & ~_GEN_0[rob_head] & ~io_csr_stall & ~can_throw_exception_0 & ~block_commit;
wire is_mini_exception = r_xcpt_uop_exc_cause == 64'h10 | r_xcpt_uop_exc_cause == 64'h11;
wire flush_commit_mask_0 = will_commit_0 & _GEN_19[com_idx];
wire flush_val = exception_thrown | flush_commit_mask_0;
wire _fflags_val_0_T = will_commit_0 & _GEN_23[com_idx];
wire fflags_val_0 = _fflags_val_0_T & ~_GEN_17[com_idx];
reg r_partial_row;
wire _empty_T = rob_head == rob_tail;
wire finished_committing_row = will_commit_0 & (will_commit_0 ^ ~rob_head_vals_0) & ~(r_partial_row & _empty_T & ~maybe_full);
reg pnr_maybe_at_tail;
wire _io_ready_T = rob_state == 2'h1;
wire _GEN_30 = io_commit_rollback_0 & (rob_tail != rob_head | maybe_full);
wire rob_deq = _GEN_30 | finished_committing_row;
assign full = _empty_T & maybe_full;
assign empty = _empty_T & ~rob_head_vals_0;
reg REG;
reg REG_1;
reg REG_2;
reg io_com_load_is_at_rob_head_REG;
wire do_inc_row = ~(_GEN[rob_pnr] & (_GEN_2[rob_pnr] | _GEN_3[rob_pnr])) & (rob_pnr != rob_tail | full & ~pnr_maybe_at_tail);
wire _GEN_31 = io_commit_rollback_0 & _empty_T & ~maybe_full;
wire _GEN_32 = io_enq_valids_0 & ~io_enq_partial_stall;
wire [1:0] _GEN_33 = empty ? 2'h1 : rob_state;
wire [3:0][1:0] _GEN_34 = {{REG_2 ? 2'h2 : _GEN_33}, {_GEN_33}, {REG_1 ? 2'h2 : io_enq_valids_0 & io_enq_uops_0_is_unique ? 2'h3 : rob_state}, {2'h1}};
wire _GEN_35 = io_enq_valids_0 & rob_tail == 5'h0;
wire _GEN_36 = io_enq_valids_0 & rob_tail == 5'h1;
wire _GEN_37 = io_enq_valids_0 & rob_tail == 5'h2;
wire _GEN_38 = io_enq_valids_0 & rob_tail == 5'h3;
wire _GEN_39 = io_enq_valids_0 & rob_tail == 5'h4;
wire _GEN_40 = io_enq_valids_0 & rob_tail == 5'h5;
wire _GEN_41 = io_enq_valids_0 & rob_tail == 5'h6;
wire _GEN_42 = io_enq_valids_0 & rob_tail == 5'h7;
wire _GEN_43 = io_enq_valids_0 & rob_tail == 5'h8;
wire _GEN_44 = io_enq_valids_0 & rob_tail == 5'h9;
wire _GEN_45 = io_enq_valids_0 & rob_tail == 5'hA;
wire _GEN_46 = io_enq_valids_0 & rob_tail == 5'hB;
wire _GEN_47 = io_enq_valids_0 & rob_tail == 5'hC;
wire _GEN_48 = io_enq_valids_0 & rob_tail == 5'hD;
wire _GEN_49 = io_enq_valids_0 & rob_tail == 5'hE;
wire _GEN_50 = io_enq_valids_0 & rob_tail == 5'hF;
wire _GEN_51 = io_enq_valids_0 & rob_tail == 5'h10;
wire _GEN_52 = io_enq_valids_0 & rob_tail == 5'h11;
wire _GEN_53 = io_enq_valids_0 & rob_tail == 5'h12;
wire _GEN_54 = io_enq_valids_0 & rob_tail == 5'h13;
wire _GEN_55 = io_enq_valids_0 & rob_tail == 5'h14;
wire _GEN_56 = io_enq_valids_0 & rob_tail == 5'h15;
wire _GEN_57 = io_enq_valids_0 & rob_tail == 5'h16;
wire _GEN_58 = io_enq_valids_0 & rob_tail == 5'h17;
wire _GEN_59 = io_enq_valids_0 & rob_tail == 5'h18;
wire _GEN_60 = io_enq_valids_0 & rob_tail == 5'h19;
wire _GEN_61 = io_enq_valids_0 & rob_tail == 5'h1A;
wire _GEN_62 = io_enq_valids_0 & rob_tail == 5'h1B;
wire _GEN_63 = io_enq_valids_0 & rob_tail == 5'h1C;
wire _GEN_64 = io_enq_valids_0 & rob_tail == 5'h1D;
wire _GEN_65 = io_enq_valids_0 & rob_tail == 5'h1E;
wire _GEN_66 = io_enq_valids_0 & (&rob_tail);
wire _rob_bsy_T = io_enq_uops_0_is_fence | io_enq_uops_0_is_fencei;
wire _GEN_67 = _GEN_35 ? ~_rob_bsy_T : rob_bsy_0;
wire _GEN_68 = _GEN_36 ? ~_rob_bsy_T : rob_bsy_1;
wire _GEN_69 = _GEN_37 ? ~_rob_bsy_T : rob_bsy_2;
wire _GEN_70 = _GEN_38 ? ~_rob_bsy_T : rob_bsy_3;
wire _GEN_71 = _GEN_39 ? ~_rob_bsy_T : rob_bsy_4;
wire _GEN_72 = _GEN_40 ? ~_rob_bsy_T : rob_bsy_5;
wire _GEN_73 = _GEN_41 ? ~_rob_bsy_T : rob_bsy_6;
wire _GEN_74 = _GEN_42 ? ~_rob_bsy_T : rob_bsy_7;
wire _GEN_75 = _GEN_43 ? ~_rob_bsy_T : rob_bsy_8;
wire _GEN_76 = _GEN_44 ? ~_rob_bsy_T : rob_bsy_9;
wire _GEN_77 = _GEN_45 ? ~_rob_bsy_T : rob_bsy_10;
wire _GEN_78 = _GEN_46 ? ~_rob_bsy_T : rob_bsy_11;
wire _GEN_79 = _GEN_47 ? ~_rob_bsy_T : rob_bsy_12;
wire _GEN_80 = _GEN_48 ? ~_rob_bsy_T : rob_bsy_13;
wire _GEN_81 = _GEN_49 ? ~_rob_bsy_T : rob_bsy_14;
wire _GEN_82 = _GEN_50 ? ~_rob_bsy_T : rob_bsy_15;
wire _GEN_83 = _GEN_51 ? ~_rob_bsy_T : rob_bsy_16;
wire _GEN_84 = _GEN_52 ? ~_rob_bsy_T : rob_bsy_17;
wire _GEN_85 = _GEN_53 ? ~_rob_bsy_T : rob_bsy_18;
wire _GEN_86 = _GEN_54 ? ~_rob_bsy_T : rob_bsy_19;
wire _GEN_87 = _GEN_55 ? ~_rob_bsy_T : rob_bsy_20;
wire _GEN_88 = _GEN_56 ? ~_rob_bsy_T : rob_bsy_21;
wire _GEN_89 = _GEN_57 ? ~_rob_bsy_T : rob_bsy_22;
wire _GEN_90 = _GEN_58 ? ~_rob_bsy_T : rob_bsy_23;
wire _GEN_91 = _GEN_59 ? ~_rob_bsy_T : rob_bsy_24;
wire _GEN_92 = _GEN_60 ? ~_rob_bsy_T : rob_bsy_25;
wire _GEN_93 = _GEN_61 ? ~_rob_bsy_T : rob_bsy_26;
wire _GEN_94 = _GEN_62 ? ~_rob_bsy_T : rob_bsy_27;
wire _GEN_95 = _GEN_63 ? ~_rob_bsy_T : rob_bsy_28;
wire _GEN_96 = _GEN_64 ? ~_rob_bsy_T : rob_bsy_29;
wire _GEN_97 = _GEN_65 ? ~_rob_bsy_T : rob_bsy_30;
wire _GEN_98 = _GEN_66 ? ~_rob_bsy_T : rob_bsy_31;
wire _rob_unsafe_T_4 = io_enq_uops_0_uses_ldq | io_enq_uops_0_uses_stq & ~io_enq_uops_0_is_fence | io_enq_uops_0_is_br | io_enq_uops_0_is_jalr;
wire _GEN_99 = _GEN_35 ? _rob_unsafe_T_4 : rob_unsafe_0;
wire _GEN_100 = _GEN_36 ? _rob_unsafe_T_4 : rob_unsafe_1;
wire _GEN_101 = _GEN_37 ? _rob_unsafe_T_4 : rob_unsafe_2;
wire _GEN_102 = _GEN_38 ? _rob_unsafe_T_4 : rob_unsafe_3;
wire _GEN_103 = _GEN_39 ? _rob_unsafe_T_4 : rob_unsafe_4;
wire _GEN_104 = _GEN_40 ? _rob_unsafe_T_4 : rob_unsafe_5;
wire _GEN_105 = _GEN_41 ? _rob_unsafe_T_4 : rob_unsafe_6;
wire _GEN_106 = _GEN_42 ? _rob_unsafe_T_4 : rob_unsafe_7;
wire _GEN_107 = _GEN_43 ? _rob_unsafe_T_4 : rob_unsafe_8;
wire _GEN_108 = _GEN_44 ? _rob_unsafe_T_4 : rob_unsafe_9;
wire _GEN_109 = _GEN_45 ? _rob_unsafe_T_4 : rob_unsafe_10;
wire _GEN_110 = _GEN_46 ? _rob_unsafe_T_4 : rob_unsafe_11;
wire _GEN_111 = _GEN_47 ? _rob_unsafe_T_4 : rob_unsafe_12;
wire _GEN_112 = _GEN_48 ? _rob_unsafe_T_4 : rob_unsafe_13;
wire _GEN_113 = _GEN_49 ? _rob_unsafe_T_4 : rob_unsafe_14;
wire _GEN_114 = _GEN_50 ? _rob_unsafe_T_4 : rob_unsafe_15;
wire _GEN_115 = _GEN_51 ? _rob_unsafe_T_4 : rob_unsafe_16;
wire _GEN_116 = _GEN_52 ? _rob_unsafe_T_4 : rob_unsafe_17;
wire _GEN_117 = _GEN_53 ? _rob_unsafe_T_4 : rob_unsafe_18;
wire _GEN_118 = _GEN_54 ? _rob_unsafe_T_4 : rob_unsafe_19;
wire _GEN_119 = _GEN_55 ? _rob_unsafe_T_4 : rob_unsafe_20;
wire _GEN_120 = _GEN_56 ? _rob_unsafe_T_4 : rob_unsafe_21;
wire _GEN_121 = _GEN_57 ? _rob_unsafe_T_4 : rob_unsafe_22;
wire _GEN_122 = _GEN_58 ? _rob_unsafe_T_4 : rob_unsafe_23;
wire _GEN_123 = _GEN_59 ? _rob_unsafe_T_4 : rob_unsafe_24;
wire _GEN_124 = _GEN_60 ? _rob_unsafe_T_4 : rob_unsafe_25;
wire _GEN_125 = _GEN_61 ? _rob_unsafe_T_4 : rob_unsafe_26;
wire _GEN_126 = _GEN_62 ? _rob_unsafe_T_4 : rob_unsafe_27;
wire _GEN_127 = _GEN_63 ? _rob_unsafe_T_4 : rob_unsafe_28;
wire _GEN_128 = _GEN_64 ? _rob_unsafe_T_4 : rob_unsafe_29;
wire _GEN_129 = _GEN_65 ? _rob_unsafe_T_4 : rob_unsafe_30;
wire _GEN_130 = _GEN_66 ? _rob_unsafe_T_4 : rob_unsafe_31;
wire _GEN_131 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h0;
wire _GEN_132 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h1;
wire _GEN_133 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h2;
wire _GEN_134 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h3;
wire _GEN_135 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h4;
wire _GEN_136 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h5;
wire _GEN_137 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h6;
wire _GEN_138 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h7;
wire _GEN_139 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h8;
wire _GEN_140 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h9;
wire _GEN_141 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'hA;
wire _GEN_142 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'hB;
wire _GEN_143 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'hC;
wire _GEN_144 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'hD;
wire _GEN_145 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'hE;
wire _GEN_146 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'hF;
wire _GEN_147 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h10;
wire _GEN_148 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h11;
wire _GEN_149 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h12;
wire _GEN_150 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h13;
wire _GEN_151 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h14;
wire _GEN_152 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h15;
wire _GEN_153 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h16;
wire _GEN_154 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h17;
wire _GEN_155 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h18;
wire _GEN_156 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h19;
wire _GEN_157 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h1A;
wire _GEN_158 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h1B;
wire _GEN_159 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h1C;
wire _GEN_160 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h1D;
wire _GEN_161 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h1E;
wire _GEN_162 = io_wb_resps_0_valid & (&io_wb_resps_0_bits_uop_rob_idx);
wire _GEN_163 = io_wb_resps_1_bits_uop_rob_idx == 5'h0;
wire _GEN_164 = _GEN_163 | _GEN_131;
wire _GEN_165 = io_wb_resps_1_valid ? ~_GEN_164 & _GEN_67 : ~_GEN_131 & _GEN_67;
wire _GEN_166 = io_wb_resps_1_bits_uop_rob_idx == 5'h1;
wire _GEN_167 = _GEN_166 | _GEN_132;
wire _GEN_168 = io_wb_resps_1_valid ? ~_GEN_167 & _GEN_68 : ~_GEN_132 & _GEN_68;
wire _GEN_169 = io_wb_resps_1_bits_uop_rob_idx == 5'h2;
wire _GEN_170 = _GEN_169 | _GEN_133;
wire _GEN_171 = io_wb_resps_1_valid ? ~_GEN_170 & _GEN_69 : ~_GEN_133 & _GEN_69;
wire _GEN_172 = io_wb_resps_1_bits_uop_rob_idx == 5'h3;
wire _GEN_173 = _GEN_172 | _GEN_134;
wire _GEN_174 = io_wb_resps_1_valid ? ~_GEN_173 & _GEN_70 : ~_GEN_134 & _GEN_70;
wire _GEN_175 = io_wb_resps_1_bits_uop_rob_idx == 5'h4;
wire _GEN_176 = _GEN_175 | _GEN_135;
wire _GEN_177 = io_wb_resps_1_valid ? ~_GEN_176 & _GEN_71 : ~_GEN_135 & _GEN_71;
wire _GEN_178 = io_wb_resps_1_bits_uop_rob_idx == 5'h5;
wire _GEN_179 = _GEN_178 | _GEN_136;
wire _GEN_180 = io_wb_resps_1_valid ? ~_GEN_179 & _GEN_72 : ~_GEN_136 & _GEN_72;
wire _GEN_181 = io_wb_resps_1_bits_uop_rob_idx == 5'h6;
wire _GEN_182 = _GEN_181 | _GEN_137;
wire _GEN_183 = io_wb_resps_1_valid ? ~_GEN_182 & _GEN_73 : ~_GEN_137 & _GEN_73;
wire _GEN_184 = io_wb_resps_1_bits_uop_rob_idx == 5'h7;
wire _GEN_185 = _GEN_184 | _GEN_138;
wire _GEN_186 = io_wb_resps_1_valid ? ~_GEN_185 & _GEN_74 : ~_GEN_138 & _GEN_74;
wire _GEN_187 = io_wb_resps_1_bits_uop_rob_idx == 5'h8;
wire _GEN_188 = _GEN_187 | _GEN_139;
wire _GEN_189 = io_wb_resps_1_valid ? ~_GEN_188 & _GEN_75 : ~_GEN_139 & _GEN_75;
wire _GEN_190 = io_wb_resps_1_bits_uop_rob_idx == 5'h9;
wire _GEN_191 = _GEN_190 | _GEN_140;
wire _GEN_192 = io_wb_resps_1_valid ? ~_GEN_191 & _GEN_76 : ~_GEN_140 & _GEN_76;
wire _GEN_193 = io_wb_resps_1_bits_uop_rob_idx == 5'hA;
wire _GEN_194 = _GEN_193 | _GEN_141;
wire _GEN_195 = io_wb_resps_1_valid ? ~_GEN_194 & _GEN_77 : ~_GEN_141 & _GEN_77;
wire _GEN_196 = io_wb_resps_1_bits_uop_rob_idx == 5'hB;
wire _GEN_197 = _GEN_196 | _GEN_142;
wire _GEN_198 = io_wb_resps_1_valid ? ~_GEN_197 & _GEN_78 : ~_GEN_142 & _GEN_78;
wire _GEN_199 = io_wb_resps_1_bits_uop_rob_idx == 5'hC;
wire _GEN_200 = _GEN_199 | _GEN_143;
wire _GEN_201 = io_wb_resps_1_valid ? ~_GEN_200 & _GEN_79 : ~_GEN_143 & _GEN_79;
wire _GEN_202 = io_wb_resps_1_bits_uop_rob_idx == 5'hD;
wire _GEN_203 = _GEN_202 | _GEN_144;
wire _GEN_204 = io_wb_resps_1_valid ? ~_GEN_203 & _GEN_80 : ~_GEN_144 & _GEN_80;
wire _GEN_205 = io_wb_resps_1_bits_uop_rob_idx == 5'hE;
wire _GEN_206 = _GEN_205 | _GEN_145;
wire _GEN_207 = io_wb_resps_1_valid ? ~_GEN_206 & _GEN_81 : ~_GEN_145 & _GEN_81;
wire _GEN_208 = io_wb_resps_1_bits_uop_rob_idx == 5'hF;
wire _GEN_209 = _GEN_208 | _GEN_146;
wire _GEN_210 = io_wb_resps_1_valid ? ~_GEN_209 & _GEN_82 : ~_GEN_146 & _GEN_82;
wire _GEN_211 = io_wb_resps_1_bits_uop_rob_idx == 5'h10;
wire _GEN_212 = _GEN_211 | _GEN_147;
wire _GEN_213 = io_wb_resps_1_valid ? ~_GEN_212 & _GEN_83 : ~_GEN_147 & _GEN_83;
wire _GEN_214 = io_wb_resps_1_bits_uop_rob_idx == 5'h11;
wire _GEN_215 = _GEN_214 | _GEN_148;
wire _GEN_216 = io_wb_resps_1_valid ? ~_GEN_215 & _GEN_84 : ~_GEN_148 & _GEN_84;
wire _GEN_217 = io_wb_resps_1_bits_uop_rob_idx == 5'h12;
wire _GEN_218 = _GEN_217 | _GEN_149;
wire _GEN_219 = io_wb_resps_1_valid ? ~_GEN_218 & _GEN_85 : ~_GEN_149 & _GEN_85;
wire _GEN_220 = io_wb_resps_1_bits_uop_rob_idx == 5'h13;
wire _GEN_221 = _GEN_220 | _GEN_150;
wire _GEN_222 = io_wb_resps_1_valid ? ~_GEN_221 & _GEN_86 : ~_GEN_150 & _GEN_86;
wire _GEN_223 = io_wb_resps_1_bits_uop_rob_idx == 5'h14;
wire _GEN_224 = _GEN_223 | _GEN_151;
wire _GEN_225 = io_wb_resps_1_valid ? ~_GEN_224 & _GEN_87 : ~_GEN_151 & _GEN_87;
wire _GEN_226 = io_wb_resps_1_bits_uop_rob_idx == 5'h15;
wire _GEN_227 = _GEN_226 | _GEN_152;
wire _GEN_228 = io_wb_resps_1_valid ? ~_GEN_227 & _GEN_88 : ~_GEN_152 & _GEN_88;
wire _GEN_229 = io_wb_resps_1_bits_uop_rob_idx == 5'h16;
wire _GEN_230 = _GEN_229 | _GEN_153;
wire _GEN_231 = io_wb_resps_1_valid ? ~_GEN_230 & _GEN_89 : ~_GEN_153 & _GEN_89;
wire _GEN_232 = io_wb_resps_1_bits_uop_rob_idx == 5'h17;
wire _GEN_233 = _GEN_232 | _GEN_154;
wire _GEN_234 = io_wb_resps_1_valid ? ~_GEN_233 & _GEN_90 : ~_GEN_154 & _GEN_90;
wire _GEN_235 = io_wb_resps_1_bits_uop_rob_idx == 5'h18;
wire _GEN_236 = _GEN_235 | _GEN_155;
wire _GEN_237 = io_wb_resps_1_valid ? ~_GEN_236 & _GEN_91 : ~_GEN_155 & _GEN_91;
wire _GEN_238 = io_wb_resps_1_bits_uop_rob_idx == 5'h19;
wire _GEN_239 = _GEN_238 | _GEN_156;
wire _GEN_240 = io_wb_resps_1_valid ? ~_GEN_239 & _GEN_92 : ~_GEN_156 & _GEN_92;
wire _GEN_241 = io_wb_resps_1_bits_uop_rob_idx == 5'h1A;
wire _GEN_242 = _GEN_241 | _GEN_157;
wire _GEN_243 = io_wb_resps_1_valid ? ~_GEN_242 & _GEN_93 : ~_GEN_157 & _GEN_93;
wire _GEN_244 = io_wb_resps_1_bits_uop_rob_idx == 5'h1B;
wire _GEN_245 = _GEN_244 | _GEN_158;
wire _GEN_246 = io_wb_resps_1_valid ? ~_GEN_245 & _GEN_94 : ~_GEN_158 & _GEN_94;
wire _GEN_247 = io_wb_resps_1_bits_uop_rob_idx == 5'h1C;
wire _GEN_248 = _GEN_247 | _GEN_159;
wire _GEN_249 = io_wb_resps_1_valid ? ~_GEN_248 & _GEN_95 : ~_GEN_159 & _GEN_95;
wire _GEN_250 = io_wb_resps_1_bits_uop_rob_idx == 5'h1D;
wire _GEN_251 = _GEN_250 | _GEN_160;
wire _GEN_252 = io_wb_resps_1_valid ? ~_GEN_251 & _GEN_96 : ~_GEN_160 & _GEN_96;
wire _GEN_253 = io_wb_resps_1_bits_uop_rob_idx == 5'h1E;
wire _GEN_254 = _GEN_253 | _GEN_161;
wire _GEN_255 = io_wb_resps_1_valid ? ~_GEN_254 & _GEN_97 : ~_GEN_161 & _GEN_97;
wire _GEN_256 = (&io_wb_resps_1_bits_uop_rob_idx) | _GEN_162;
wire _GEN_257 = io_wb_resps_1_valid ? ~_GEN_256 & _GEN_98 : ~_GEN_162 & _GEN_98;
wire _GEN_258 = io_wb_resps_1_valid ? ~_GEN_164 & _GEN_99 : ~_GEN_131 & _GEN_99;
wire _GEN_259 = io_wb_resps_1_valid ? ~_GEN_167 & _GEN_100 : ~_GEN_132 & _GEN_100;
wire _GEN_260 = io_wb_resps_1_valid ? ~_GEN_170 & _GEN_101 : ~_GEN_133 & _GEN_101;
wire _GEN_261 = io_wb_resps_1_valid ? ~_GEN_173 & _GEN_102 : ~_GEN_134 & _GEN_102;
wire _GEN_262 = io_wb_resps_1_valid ? ~_GEN_176 & _GEN_103 : ~_GEN_135 & _GEN_103;
wire _GEN_263 = io_wb_resps_1_valid ? ~_GEN_179 & _GEN_104 : ~_GEN_136 & _GEN_104;
wire _GEN_264 = io_wb_resps_1_valid ? ~_GEN_182 & _GEN_105 : ~_GEN_137 & _GEN_105;
wire _GEN_265 = io_wb_resps_1_valid ? ~_GEN_185 & _GEN_106 : ~_GEN_138 & _GEN_106;
wire _GEN_266 = io_wb_resps_1_valid ? ~_GEN_188 & _GEN_107 : ~_GEN_139 & _GEN_107;
wire _GEN_267 = io_wb_resps_1_valid ? ~_GEN_191 & _GEN_108 : ~_GEN_140 & _GEN_108;
wire _GEN_268 = io_wb_resps_1_valid ? ~_GEN_194 & _GEN_109 : ~_GEN_141 & _GEN_109;
wire _GEN_269 = io_wb_resps_1_valid ? ~_GEN_197 & _GEN_110 : ~_GEN_142 & _GEN_110;
wire _GEN_270 = io_wb_resps_1_valid ? ~_GEN_200 & _GEN_111 : ~_GEN_143 & _GEN_111;
wire _GEN_271 = io_wb_resps_1_valid ? ~_GEN_203 & _GEN_112 : ~_GEN_144 & _GEN_112;
wire _GEN_272 = io_wb_resps_1_valid ? ~_GEN_206 & _GEN_113 : ~_GEN_145 & _GEN_113;
wire _GEN_273 = io_wb_resps_1_valid ? ~_GEN_209 & _GEN_114 : ~_GEN_146 & _GEN_114;
wire _GEN_274 = io_wb_resps_1_valid ? ~_GEN_212 & _GEN_115 : ~_GEN_147 & _GEN_115;
wire _GEN_275 = io_wb_resps_1_valid ? ~_GEN_215 & _GEN_116 : ~_GEN_148 & _GEN_116;
wire _GEN_276 = io_wb_resps_1_valid ? ~_GEN_218 & _GEN_117 : ~_GEN_149 & _GEN_117;
wire _GEN_277 = io_wb_resps_1_valid ? ~_GEN_221 & _GEN_118 : ~_GEN_150 & _GEN_118;
wire _GEN_278 = io_wb_resps_1_valid ? ~_GEN_224 & _GEN_119 : ~_GEN_151 & _GEN_119;
wire _GEN_279 = io_wb_resps_1_valid ? ~_GEN_227 & _GEN_120 : ~_GEN_152 & _GEN_120;
wire _GEN_280 = io_wb_resps_1_valid ? ~_GEN_230 & _GEN_121 : ~_GEN_153 & _GEN_121;
wire _GEN_281 = io_wb_resps_1_valid ? ~_GEN_233 & _GEN_122 : ~_GEN_154 & _GEN_122;
wire _GEN_282 = io_wb_resps_1_valid ? ~_GEN_236 & _GEN_123 : ~_GEN_155 & _GEN_123;
wire _GEN_283 = io_wb_resps_1_valid ? ~_GEN_239 & _GEN_124 : ~_GEN_156 & _GEN_124;
wire _GEN_284 = io_wb_resps_1_valid ? ~_GEN_242 & _GEN_125 : ~_GEN_157 & _GEN_125;
wire _GEN_285 = io_wb_resps_1_valid ? ~_GEN_245 & _GEN_126 : ~_GEN_158 & _GEN_126;
wire _GEN_286 = io_wb_resps_1_valid ? ~_GEN_248 & _GEN_127 : ~_GEN_159 & _GEN_127;
wire _GEN_287 = io_wb_resps_1_valid ? ~_GEN_251 & _GEN_128 : ~_GEN_160 & _GEN_128;
wire _GEN_288 = io_wb_resps_1_valid ? ~_GEN_254 & _GEN_129 : ~_GEN_161 & _GEN_129;
wire _GEN_289 = io_wb_resps_1_valid ? ~_GEN_256 & _GEN_130 : ~_GEN_162 & _GEN_130;
wire _GEN_290 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h0;
wire _GEN_291 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h1;
wire _GEN_292 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h2;
wire _GEN_293 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h3;
wire _GEN_294 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h4;
wire _GEN_295 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h5;
wire _GEN_296 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h6;
wire _GEN_297 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h7;
wire _GEN_298 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h8;
wire _GEN_299 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h9;
wire _GEN_300 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'hA;
wire _GEN_301 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'hB;
wire _GEN_302 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'hC;
wire _GEN_303 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'hD;
wire _GEN_304 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'hE;
wire _GEN_305 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'hF;
wire _GEN_306 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h10;
wire _GEN_307 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h11;
wire _GEN_308 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h12;
wire _GEN_309 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h13;
wire _GEN_310 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h14;
wire _GEN_311 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h15;
wire _GEN_312 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h16;
wire _GEN_313 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h17;
wire _GEN_314 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h18;
wire _GEN_315 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h19;
wire _GEN_316 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h1A;
wire _GEN_317 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h1B;
wire _GEN_318 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h1C;
wire _GEN_319 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h1D;
wire _GEN_320 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h1E;
wire _GEN_321 = io_wb_resps_2_valid & (&io_wb_resps_2_bits_uop_rob_idx);
wire _GEN_322 = io_wb_resps_3_bits_uop_rob_idx == 5'h0;
wire _GEN_323 = _GEN_322 | _GEN_290;
wire _GEN_324 = io_wb_resps_3_valid ? ~_GEN_323 & _GEN_165 : ~_GEN_290 & _GEN_165;
wire _GEN_325 = io_wb_resps_3_bits_uop_rob_idx == 5'h1;
wire _GEN_326 = _GEN_325 | _GEN_291;
wire _GEN_327 = io_wb_resps_3_valid ? ~_GEN_326 & _GEN_168 : ~_GEN_291 & _GEN_168;
wire _GEN_328 = io_wb_resps_3_bits_uop_rob_idx == 5'h2;
wire _GEN_329 = _GEN_328 | _GEN_292;
wire _GEN_330 = io_wb_resps_3_valid ? ~_GEN_329 & _GEN_171 : ~_GEN_292 & _GEN_171;
wire _GEN_331 = io_wb_resps_3_bits_uop_rob_idx == 5'h3;
wire _GEN_332 = _GEN_331 | _GEN_293;
wire _GEN_333 = io_wb_resps_3_valid ? ~_GEN_332 & _GEN_174 : ~_GEN_293 & _GEN_174;
wire _GEN_334 = io_wb_resps_3_bits_uop_rob_idx == 5'h4;
wire _GEN_335 = _GEN_334 | _GEN_294;
wire _GEN_336 = io_wb_resps_3_valid ? ~_GEN_335 & _GEN_177 : ~_GEN_294 & _GEN_177;
wire _GEN_337 = io_wb_resps_3_bits_uop_rob_idx == 5'h5;
wire _GEN_338 = _GEN_337 | _GEN_295;
wire _GEN_339 = io_wb_resps_3_valid ? ~_GEN_338 & _GEN_180 : ~_GEN_295 & _GEN_180;
wire _GEN_340 = io_wb_resps_3_bits_uop_rob_idx == 5'h6;
wire _GEN_341 = _GEN_340 | _GEN_296;
wire _GEN_342 = io_wb_resps_3_valid ? ~_GEN_341 & _GEN_183 : ~_GEN_296 & _GEN_183;
wire _GEN_343 = io_wb_resps_3_bits_uop_rob_idx == 5'h7;
wire _GEN_344 = _GEN_343 | _GEN_297;
wire _GEN_345 = io_wb_resps_3_valid ? ~_GEN_344 & _GEN_186 : ~_GEN_297 & _GEN_186;
wire _GEN_346 = io_wb_resps_3_bits_uop_rob_idx == 5'h8;
wire _GEN_347 = _GEN_346 | _GEN_298;
wire _GEN_348 = io_wb_resps_3_valid ? ~_GEN_347 & _GEN_189 : ~_GEN_298 & _GEN_189;
wire _GEN_349 = io_wb_resps_3_bits_uop_rob_idx == 5'h9;
wire _GEN_350 = _GEN_349 | _GEN_299;
wire _GEN_351 = io_wb_resps_3_valid ? ~_GEN_350 & _GEN_192 : ~_GEN_299 & _GEN_192;
wire _GEN_352 = io_wb_resps_3_bits_uop_rob_idx == 5'hA;
wire _GEN_353 = _GEN_352 | _GEN_300;
wire _GEN_354 = io_wb_resps_3_valid ? ~_GEN_353 & _GEN_195 : ~_GEN_300 & _GEN_195;
wire _GEN_355 = io_wb_resps_3_bits_uop_rob_idx == 5'hB;
wire _GEN_356 = _GEN_355 | _GEN_301;
wire _GEN_357 = io_wb_resps_3_valid ? ~_GEN_356 & _GEN_198 : ~_GEN_301 & _GEN_198;
wire _GEN_358 = io_wb_resps_3_bits_uop_rob_idx == 5'hC;
wire _GEN_359 = _GEN_358 | _GEN_302;
wire _GEN_360 = io_wb_resps_3_valid ? ~_GEN_359 & _GEN_201 : ~_GEN_302 & _GEN_201;
wire _GEN_361 = io_wb_resps_3_bits_uop_rob_idx == 5'hD;
wire _GEN_362 = _GEN_361 | _GEN_303;
wire _GEN_363 = io_wb_resps_3_valid ? ~_GEN_362 & _GEN_204 : ~_GEN_303 & _GEN_204;
wire _GEN_364 = io_wb_resps_3_bits_uop_rob_idx == 5'hE;
wire _GEN_365 = _GEN_364 | _GEN_304;
wire _GEN_366 = io_wb_resps_3_valid ? ~_GEN_365 & _GEN_207 : ~_GEN_304 & _GEN_207;
wire _GEN_367 = io_wb_resps_3_bits_uop_rob_idx == 5'hF;
wire _GEN_368 = _GEN_367 | _GEN_305;
wire _GEN_369 = io_wb_resps_3_valid ? ~_GEN_368 & _GEN_210 : ~_GEN_305 & _GEN_210;
wire _GEN_370 = io_wb_resps_3_bits_uop_rob_idx == 5'h10;
wire _GEN_371 = _GEN_370 | _GEN_306;
wire _GEN_372 = io_wb_resps_3_valid ? ~_GEN_371 & _GEN_213 : ~_GEN_306 & _GEN_213;
wire _GEN_373 = io_wb_resps_3_bits_uop_rob_idx == 5'h11;
wire _GEN_374 = _GEN_373 | _GEN_307;
wire _GEN_375 = io_wb_resps_3_valid ? ~_GEN_374 & _GEN_216 : ~_GEN_307 & _GEN_216;
wire _GEN_376 = io_wb_resps_3_bits_uop_rob_idx == 5'h12;
wire _GEN_377 = _GEN_376 | _GEN_308;
wire _GEN_378 = io_wb_resps_3_valid ? ~_GEN_377 & _GEN_219 : ~_GEN_308 & _GEN_219;
wire _GEN_379 = io_wb_resps_3_bits_uop_rob_idx == 5'h13;
wire _GEN_380 = _GEN_379 | _GEN_309;
wire _GEN_381 = io_wb_resps_3_valid ? ~_GEN_380 & _GEN_222 : ~_GEN_309 & _GEN_222;
wire _GEN_382 = io_wb_resps_3_bits_uop_rob_idx == 5'h14;
wire _GEN_383 = _GEN_382 | _GEN_310;
wire _GEN_384 = io_wb_resps_3_valid ? ~_GEN_383 & _GEN_225 : ~_GEN_310 & _GEN_225;
wire _GEN_385 = io_wb_resps_3_bits_uop_rob_idx == 5'h15;
wire _GEN_386 = _GEN_385 | _GEN_311;
wire _GEN_387 = io_wb_resps_3_valid ? ~_GEN_386 & _GEN_228 : ~_GEN_311 & _GEN_228;
wire _GEN_388 = io_wb_resps_3_bits_uop_rob_idx == 5'h16;
wire _GEN_389 = _GEN_388 | _GEN_312;
wire _GEN_390 = io_wb_resps_3_valid ? ~_GEN_389 & _GEN_231 : ~_GEN_312 & _GEN_231;
wire _GEN_391 = io_wb_resps_3_bits_uop_rob_idx == 5'h17;
wire _GEN_392 = _GEN_391 | _GEN_313;
wire _GEN_393 = io_wb_resps_3_valid ? ~_GEN_392 & _GEN_234 : ~_GEN_313 & _GEN_234;
wire _GEN_394 = io_wb_resps_3_bits_uop_rob_idx == 5'h18;
wire _GEN_395 = _GEN_394 | _GEN_314;
wire _GEN_396 = io_wb_resps_3_valid ? ~_GEN_395 & _GEN_237 : ~_GEN_314 & _GEN_237;
wire _GEN_397 = io_wb_resps_3_bits_uop_rob_idx == 5'h19;
wire _GEN_398 = _GEN_397 | _GEN_315;
wire _GEN_399 = io_wb_resps_3_valid ? ~_GEN_398 & _GEN_240 : ~_GEN_315 & _GEN_240;
wire _GEN_400 = io_wb_resps_3_bits_uop_rob_idx == 5'h1A;
wire _GEN_401 = _GEN_400 | _GEN_316;
wire _GEN_402 = io_wb_resps_3_valid ? ~_GEN_401 & _GEN_243 : ~_GEN_316 & _GEN_243;
wire _GEN_403 = io_wb_resps_3_bits_uop_rob_idx == 5'h1B;
wire _GEN_404 = _GEN_403 | _GEN_317;
wire _GEN_405 = io_wb_resps_3_valid ? ~_GEN_404 & _GEN_246 : ~_GEN_317 & _GEN_246;
wire _GEN_406 = io_wb_resps_3_bits_uop_rob_idx == 5'h1C;
wire _GEN_407 = _GEN_406 | _GEN_318;
wire _GEN_408 = io_wb_resps_3_valid ? ~_GEN_407 & _GEN_249 : ~_GEN_318 & _GEN_249;
wire _GEN_409 = io_wb_resps_3_bits_uop_rob_idx == 5'h1D;
wire _GEN_410 = _GEN_409 | _GEN_319;
wire _GEN_411 = io_wb_resps_3_valid ? ~_GEN_410 & _GEN_252 : ~_GEN_319 & _GEN_252;
wire _GEN_412 = io_wb_resps_3_bits_uop_rob_idx == 5'h1E;
wire _GEN_413 = _GEN_412 | _GEN_320;
wire _GEN_414 = io_wb_resps_3_valid ? ~_GEN_413 & _GEN_255 : ~_GEN_320 & _GEN_255;
wire _GEN_415 = (&io_wb_resps_3_bits_uop_rob_idx) | _GEN_321;
wire _GEN_416 = io_wb_resps_3_valid ? ~_GEN_415 & _GEN_257 : ~_GEN_321 & _GEN_257;
wire _GEN_417 = io_wb_resps_3_valid ? ~_GEN_323 & _GEN_258 : ~_GEN_290 & _GEN_258;
wire _GEN_418 = io_wb_resps_3_valid ? ~_GEN_326 & _GEN_259 : ~_GEN_291 & _GEN_259;
wire _GEN_419 = io_wb_resps_3_valid ? ~_GEN_329 & _GEN_260 : ~_GEN_292 & _GEN_260;
wire _GEN_420 = io_wb_resps_3_valid ? ~_GEN_332 & _GEN_261 : ~_GEN_293 & _GEN_261;
wire _GEN_421 = io_wb_resps_3_valid ? ~_GEN_335 & _GEN_262 : ~_GEN_294 & _GEN_262;
wire _GEN_422 = io_wb_resps_3_valid ? ~_GEN_338 & _GEN_263 : ~_GEN_295 & _GEN_263;
wire _GEN_423 = io_wb_resps_3_valid ? ~_GEN_341 & _GEN_264 : ~_GEN_296 & _GEN_264;
wire _GEN_424 = io_wb_resps_3_valid ? ~_GEN_344 & _GEN_265 : ~_GEN_297 & _GEN_265;
wire _GEN_425 = io_wb_resps_3_valid ? ~_GEN_347 & _GEN_266 : ~_GEN_298 & _GEN_266;
wire _GEN_426 = io_wb_resps_3_valid ? ~_GEN_350 & _GEN_267 : ~_GEN_299 & _GEN_267;
wire _GEN_427 = io_wb_resps_3_valid ? ~_GEN_353 & _GEN_268 : ~_GEN_300 & _GEN_268;
wire _GEN_428 = io_wb_resps_3_valid ? ~_GEN_356 & _GEN_269 : ~_GEN_301 & _GEN_269;
wire _GEN_429 = io_wb_resps_3_valid ? ~_GEN_359 & _GEN_270 : ~_GEN_302 & _GEN_270;
wire _GEN_430 = io_wb_resps_3_valid ? ~_GEN_362 & _GEN_271 : ~_GEN_303 & _GEN_271;
wire _GEN_431 = io_wb_resps_3_valid ? ~_GEN_365 & _GEN_272 : ~_GEN_304 & _GEN_272;
wire _GEN_432 = io_wb_resps_3_valid ? ~_GEN_368 & _GEN_273 : ~_GEN_305 & _GEN_273;
wire _GEN_433 = io_wb_resps_3_valid ? ~_GEN_371 & _GEN_274 : ~_GEN_306 & _GEN_274;
wire _GEN_434 = io_wb_resps_3_valid ? ~_GEN_374 & _GEN_275 : ~_GEN_307 & _GEN_275;
wire _GEN_435 = io_wb_resps_3_valid ? ~_GEN_377 & _GEN_276 : ~_GEN_308 & _GEN_276;
wire _GEN_436 = io_wb_resps_3_valid ? ~_GEN_380 & _GEN_277 : ~_GEN_309 & _GEN_277;
wire _GEN_437 = io_wb_resps_3_valid ? ~_GEN_383 & _GEN_278 : ~_GEN_310 & _GEN_278;
wire _GEN_438 = io_wb_resps_3_valid ? ~_GEN_386 & _GEN_279 : ~_GEN_311 & _GEN_279;
wire _GEN_439 = io_wb_resps_3_valid ? ~_GEN_389 & _GEN_280 : ~_GEN_312 & _GEN_280;
wire _GEN_440 = io_wb_resps_3_valid ? ~_GEN_392 & _GEN_281 : ~_GEN_313 & _GEN_281;
wire _GEN_441 = io_wb_resps_3_valid ? ~_GEN_395 & _GEN_282 : ~_GEN_314 & _GEN_282;
wire _GEN_442 = io_wb_resps_3_valid ? ~_GEN_398 & _GEN_283 : ~_GEN_315 & _GEN_283;
wire _GEN_443 = io_wb_resps_3_valid ? ~_GEN_401 & _GEN_284 : ~_GEN_316 & _GEN_284;
wire _GEN_444 = io_wb_resps_3_valid ? ~_GEN_404 & _GEN_285 : ~_GEN_317 & _GEN_285;
wire _GEN_445 = io_wb_resps_3_valid ? ~_GEN_407 & _GEN_286 : ~_GEN_318 & _GEN_286;
wire _GEN_446 = io_wb_resps_3_valid ? ~_GEN_410 & _GEN_287 : ~_GEN_319 & _GEN_287;
wire _GEN_447 = io_wb_resps_3_valid ? ~_GEN_413 & _GEN_288 : ~_GEN_320 & _GEN_288;
wire _GEN_448 = io_wb_resps_3_valid ? ~_GEN_415 & _GEN_289 : ~_GEN_321 & _GEN_289;
wire _GEN_449 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h0;
wire _GEN_450 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h1;
wire _GEN_451 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h2;
wire _GEN_452 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h3;
wire _GEN_453 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h4;
wire _GEN_454 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h5;
wire _GEN_455 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h6;
wire _GEN_456 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h7;
wire _GEN_457 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h8;
wire _GEN_458 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h9;
wire _GEN_459 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'hA;
wire _GEN_460 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'hB;
wire _GEN_461 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'hC;
wire _GEN_462 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'hD;
wire _GEN_463 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'hE;
wire _GEN_464 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'hF;
wire _GEN_465 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h10;
wire _GEN_466 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h11;
wire _GEN_467 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h12;
wire _GEN_468 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h13;
wire _GEN_469 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h14;
wire _GEN_470 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h15;
wire _GEN_471 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h16;
wire _GEN_472 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h17;
wire _GEN_473 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h18;
wire _GEN_474 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h19;
wire _GEN_475 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h1A;
wire _GEN_476 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h1B;
wire _GEN_477 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h1C;
wire _GEN_478 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h1D;
wire _GEN_479 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h1E;
wire _GEN_480 = io_lsu_clr_bsy_0_valid & (&io_lsu_clr_bsy_0_bits);
wire _GEN_481 = io_lsu_clr_bsy_1_bits == 5'h0 | _GEN_449;
wire _GEN_482 = io_lsu_clr_bsy_1_bits == 5'h1 | _GEN_450;
wire _GEN_483 = io_lsu_clr_bsy_1_bits == 5'h2 | _GEN_451;
wire _GEN_484 = io_lsu_clr_bsy_1_bits == 5'h3 | _GEN_452;
wire _GEN_485 = io_lsu_clr_bsy_1_bits == 5'h4 | _GEN_453;
wire _GEN_486 = io_lsu_clr_bsy_1_bits == 5'h5 | _GEN_454;
wire _GEN_487 = io_lsu_clr_bsy_1_bits == 5'h6 | _GEN_455;
wire _GEN_488 = io_lsu_clr_bsy_1_bits == 5'h7 | _GEN_456;
wire _GEN_489 = io_lsu_clr_bsy_1_bits == 5'h8 | _GEN_457;
wire _GEN_490 = io_lsu_clr_bsy_1_bits == 5'h9 | _GEN_458;
wire _GEN_491 = io_lsu_clr_bsy_1_bits == 5'hA | _GEN_459;
wire _GEN_492 = io_lsu_clr_bsy_1_bits == 5'hB | _GEN_460;
wire _GEN_493 = io_lsu_clr_bsy_1_bits == 5'hC | _GEN_461;
wire _GEN_494 = io_lsu_clr_bsy_1_bits == 5'hD | _GEN_462;
wire _GEN_495 = io_lsu_clr_bsy_1_bits == 5'hE | _GEN_463;
wire _GEN_496 = io_lsu_clr_bsy_1_bits == 5'hF | _GEN_464;
wire _GEN_497 = io_lsu_clr_bsy_1_bits == 5'h10 | _GEN_465;
wire _GEN_498 = io_lsu_clr_bsy_1_bits == 5'h11 | _GEN_466;
wire _GEN_499 = io_lsu_clr_bsy_1_bits == 5'h12 | _GEN_467;
wire _GEN_500 = io_lsu_clr_bsy_1_bits == 5'h13 | _GEN_468;
wire _GEN_501 = io_lsu_clr_bsy_1_bits == 5'h14 | _GEN_469;
wire _GEN_502 = io_lsu_clr_bsy_1_bits == 5'h15 | _GEN_470;
wire _GEN_503 = io_lsu_clr_bsy_1_bits == 5'h16 | _GEN_471;
wire _GEN_504 = io_lsu_clr_bsy_1_bits == 5'h17 | _GEN_472;
wire _GEN_505 = io_lsu_clr_bsy_1_bits == 5'h18 | _GEN_473;
wire _GEN_506 = io_lsu_clr_bsy_1_bits == 5'h19 | _GEN_474;
wire _GEN_507 = io_lsu_clr_bsy_1_bits == 5'h1A | _GEN_475;
wire _GEN_508 = io_lsu_clr_bsy_1_bits == 5'h1B | _GEN_476;
wire _GEN_509 = io_lsu_clr_bsy_1_bits == 5'h1C | _GEN_477;
wire _GEN_510 = io_lsu_clr_bsy_1_bits == 5'h1D | _GEN_478;
wire _GEN_511 = io_lsu_clr_bsy_1_bits == 5'h1E | _GEN_479;
wire _GEN_512 = (&io_lsu_clr_bsy_1_bits) | _GEN_480;
wire _GEN_513 = rbk_row & com_idx == 5'h0;
wire _GEN_514 = rbk_row & com_idx == 5'h1;
wire _GEN_515 = rbk_row & com_idx == 5'h2;
wire _GEN_516 = rbk_row & com_idx == 5'h3;
wire _GEN_517 = rbk_row & com_idx == 5'h4;
wire _GEN_518 = rbk_row & com_idx == 5'h5;
wire _GEN_519 = rbk_row & com_idx == 5'h6;
wire _GEN_520 = rbk_row & com_idx == 5'h7;
wire _GEN_521 = rbk_row & com_idx == 5'h8;
wire _GEN_522 = rbk_row & com_idx == 5'h9;
wire _GEN_523 = rbk_row & com_idx == 5'hA;
wire _GEN_524 = rbk_row & com_idx == 5'hB;
wire _GEN_525 = rbk_row & com_idx == 5'hC;
wire _GEN_526 = rbk_row & com_idx == 5'hD;
wire _GEN_527 = rbk_row & com_idx == 5'hE;
wire _GEN_528 = rbk_row & com_idx == 5'hF;
wire _GEN_529 = rbk_row & com_idx == 5'h10;
wire _GEN_530 = rbk_row & com_idx == 5'h11;
wire _GEN_531 = rbk_row & com_idx == 5'h12;
wire _GEN_532 = rbk_row & com_idx == 5'h13;
wire _GEN_533 = rbk_row & com_idx == 5'h14;
wire _GEN_534 = rbk_row & com_idx == 5'h15;
wire _GEN_535 = rbk_row & com_idx == 5'h16;
wire _GEN_536 = rbk_row & com_idx == 5'h17;
wire _GEN_537 = rbk_row & com_idx == 5'h18;
wire _GEN_538 = rbk_row & com_idx == 5'h19;
wire _GEN_539 = rbk_row & com_idx == 5'h1A;
wire _GEN_540 = rbk_row & com_idx == 5'h1B;
wire _GEN_541 = rbk_row & com_idx == 5'h1C;
wire _GEN_542 = rbk_row & com_idx == 5'h1D;
wire _GEN_543 = rbk_row & com_idx == 5'h1E;
wire _GEN_544 = rbk_row & (&com_idx);
wire [7:0] _GEN_545 = io_brupdate_b1_mispredict_mask & rob_uop_0_br_mask;
wire [7:0] _GEN_546 = io_brupdate_b1_mispredict_mask & rob_uop_1_br_mask;
wire [7:0] _GEN_547 = io_brupdate_b1_mispredict_mask & rob_uop_2_br_mask;
wire [7:0] _GEN_548 = io_brupdate_b1_mispredict_mask & rob_uop_3_br_mask;
wire [7:0] _GEN_549 = io_brupdate_b1_mispredict_mask & rob_uop_4_br_mask;
wire [7:0] _GEN_550 = io_brupdate_b1_mispredict_mask & rob_uop_5_br_mask;
wire [7:0] _GEN_551 = io_brupdate_b1_mispredict_mask & rob_uop_6_br_mask;
wire [7:0] _GEN_552 = io_brupdate_b1_mispredict_mask & rob_uop_7_br_mask;
wire [7:0] _GEN_553 = io_brupdate_b1_mispredict_mask & rob_uop_8_br_mask;
wire [7:0] _GEN_554 = io_brupdate_b1_mispredict_mask & rob_uop_9_br_mask;
wire [7:0] _GEN_555 = io_brupdate_b1_mispredict_mask & rob_uop_10_br_mask;
wire [7:0] _GEN_556 = io_brupdate_b1_mispredict_mask & rob_uop_11_br_mask;
wire [7:0] _GEN_557 = io_brupdate_b1_mispredict_mask & rob_uop_12_br_mask;
wire [7:0] _GEN_558 = io_brupdate_b1_mispredict_mask & rob_uop_13_br_mask;
wire [7:0] _GEN_559 = io_brupdate_b1_mispredict_mask & rob_uop_14_br_mask;
wire [7:0] _GEN_560 = io_brupdate_b1_mispredict_mask & rob_uop_15_br_mask;
wire [7:0] _GEN_561 = io_brupdate_b1_mispredict_mask & rob_uop_16_br_mask;
wire [7:0] _GEN_562 = io_brupdate_b1_mispredict_mask & rob_uop_17_br_mask;
wire [7:0] _GEN_563 = io_brupdate_b1_mispredict_mask & rob_uop_18_br_mask;
wire [7:0] _GEN_564 = io_brupdate_b1_mispredict_mask & rob_uop_19_br_mask;
wire [7:0] _GEN_565 = io_brupdate_b1_mispredict_mask & rob_uop_20_br_mask;
wire [7:0] _GEN_566 = io_brupdate_b1_mispredict_mask & rob_uop_21_br_mask;
wire [7:0] _GEN_567 = io_brupdate_b1_mispredict_mask & rob_uop_22_br_mask;
wire [7:0] _GEN_568 = io_brupdate_b1_mispredict_mask & rob_uop_23_br_mask;
wire [7:0] _GEN_569 = io_brupdate_b1_mispredict_mask & rob_uop_24_br_mask;
wire [7:0] _GEN_570 = io_brupdate_b1_mispredict_mask & rob_uop_25_br_mask;
wire [7:0] _GEN_571 = io_brupdate_b1_mispredict_mask & rob_uop_26_br_mask;
wire [7:0] _GEN_572 = io_brupdate_b1_mispredict_mask & rob_uop_27_br_mask;
wire [7:0] _GEN_573 = io_brupdate_b1_mispredict_mask & rob_uop_28_br_mask;
wire [7:0] _GEN_574 = io_brupdate_b1_mispredict_mask & rob_uop_29_br_mask;
wire [7:0] _GEN_575 = io_brupdate_b1_mispredict_mask & rob_uop_30_br_mask;
wire [7:0] _GEN_576 = io_brupdate_b1_mispredict_mask & rob_uop_31_br_mask;
wire _GEN_577 = ~flush_val & rob_state != 2'h2;
wire _GEN_578 = ~r_xcpt_val | io_lxcpt_bits_uop_rob_idx < r_xcpt_uop_rob_idx ^ io_lxcpt_bits_uop_rob_idx < rob_head ^ r_xcpt_uop_rob_idx < rob_head;
wire _GEN_579 = ~r_xcpt_val & io_enq_valids_0 & io_enq_uops_0_exception;
wire [7:0] next_xcpt_uop_br_mask = _GEN_577 ? (io_lxcpt_valid ? (_GEN_578 ? io_lxcpt_bits_uop_br_mask : r_xcpt_uop_br_mask) : _GEN_579 ? io_enq_uops_0_br_mask : r_xcpt_uop_br_mask) : r_xcpt_uop_br_mask;
wire _GEN_580 = _GEN_35 | rob_val_0;
wire _GEN_581 = _GEN_36 | rob_val_1;
wire _GEN_582 = _GEN_37 | rob_val_2;
wire _GEN_583 = _GEN_38 | rob_val_3;
wire _GEN_584 = _GEN_39 | rob_val_4;
wire _GEN_585 = _GEN_40 | rob_val_5;
wire _GEN_586 = _GEN_41 | rob_val_6;
wire _GEN_587 = _GEN_42 | rob_val_7;
wire _GEN_588 = _GEN_43 | rob_val_8;
wire _GEN_589 = _GEN_44 | rob_val_9;
wire _GEN_590 = _GEN_45 | rob_val_10;
wire _GEN_591 = _GEN_46 | rob_val_11;
wire _GEN_592 = _GEN_47 | rob_val_12;
wire _GEN_593 = _GEN_48 | rob_val_13;
wire _GEN_594 = _GEN_49 | rob_val_14;
wire _GEN_595 = _GEN_50 | rob_val_15;
wire _GEN_596 = _GEN_51 | rob_val_16;
wire _GEN_597 = _GEN_52 | rob_val_17;
wire _GEN_598 = _GEN_53 | rob_val_18;
wire _GEN_599 = _GEN_54 | rob_val_19;
wire _GEN_600 = _GEN_55 | rob_val_20;
wire _GEN_601 = _GEN_56 | rob_val_21;
wire _GEN_602 = _GEN_57 | rob_val_22;
wire _GEN_603 = _GEN_58 | rob_val_23;
wire _GEN_604 = _GEN_59 | rob_val_24;
wire _GEN_605 = _GEN_60 | rob_val_25;
wire _GEN_606 = _GEN_61 | rob_val_26;
wire _GEN_607 = _GEN_62 | rob_val_27;
wire _GEN_608 = _GEN_63 | rob_val_28;
wire _GEN_609 = _GEN_64 | rob_val_29;
wire _GEN_610 = _GEN_65 | rob_val_30;
wire _GEN_611 = _GEN_66 | rob_val_31;
always @(posedge clock) begin
if (_GEN_1)
assert__assert_6: assert(_GEN_2[io_lxcpt_bits_uop_rob_idx]);
if (reset) begin
rob_state <= 2'h0;
rob_head <= 5'h0;
rob_tail <= 5'h0;
rob_pnr <= 5'h0;
maybe_full <= 1'h0;
r_xcpt_val <= 1'h0;
rob_val_0 <= 1'h0;
rob_val_1 <= 1'h0;
rob_val_2 <= 1'h0;
rob_val_3 <= 1'h0;
rob_val_4 <= 1'h0;
rob_val_5 <= 1'h0;
rob_val_6 <= 1'h0;
rob_val_7 <= 1'h0;
rob_val_8 <= 1'h0;
rob_val_9 <= 1'h0;
rob_val_10 <= 1'h0;
rob_val_11 <= 1'h0;
rob_val_12 <= 1'h0;
rob_val_13 <= 1'h0;
rob_val_14 <= 1'h0;
rob_val_15 <= 1'h0;
rob_val_16 <= 1'h0;
rob_val_17 <= 1'h0;
rob_val_18 <= 1'h0;
rob_val_19 <= 1'h0;
rob_val_20 <= 1'h0;
rob_val_21 <= 1'h0;
rob_val_22 <= 1'h0;
rob_val_23 <= 1'h0;
rob_val_24 <= 1'h0;
rob_val_25 <= 1'h0;
rob_val_26 <= 1'h0;
rob_val_27 <= 1'h0;
rob_val_28 <= 1'h0;
rob_val_29 <= 1'h0;
rob_val_30 <= 1'h0;
rob_val_31 <= 1'h0;
r_partial_row <= 1'h0;
pnr_maybe_at_tail <= 1'h0;
end
else begin
rob_state <= _GEN_34[rob_state];
if (finished_committing_row)
rob_head <= rob_head + 5'h1;
if (_GEN_30)
rob_tail <= rob_tail - 5'h1;
else if (~_GEN_31) begin
if (io_brupdate_b2_mispredict)
rob_tail <= io_brupdate_b2_uop_rob_idx + 5'h1;
else if (_GEN_32)
rob_tail <= rob_tail + 5'h1;
end
if (empty & io_enq_valids_0)
rob_pnr <= rob_head;
else if ((_io_ready_T | (&rob_state)) & do_inc_row)
rob_pnr <= rob_pnr + 5'h1;
maybe_full <= |{~rob_deq & (~(_GEN_30 | _GEN_31 | io_brupdate_b2_mispredict) & _GEN_32 | maybe_full), io_brupdate_b1_mispredict_mask};
r_xcpt_val <= {flush_val, io_brupdate_b1_mispredict_mask & next_xcpt_uop_br_mask} == 9'h0 & (_GEN_577 ? (io_lxcpt_valid ? _GEN_578 | r_xcpt_val : _GEN_579 | r_xcpt_val) : r_xcpt_val);
rob_val_0 <= will_commit_0 ? ~((|{rob_head == 5'h0, _GEN_545}) | _GEN_513) & _GEN_580 : ~((|_GEN_545) | _GEN_513) & _GEN_580;
rob_val_1 <= will_commit_0 ? ~((|{rob_head == 5'h1, _GEN_546}) | _GEN_514) & _GEN_581 : ~((|_GEN_546) | _GEN_514) & _GEN_581;
rob_val_2 <= will_commit_0 ? ~((|{rob_head == 5'h2, _GEN_547}) | _GEN_515) & _GEN_582 : ~((|_GEN_547) | _GEN_515) & _GEN_582;
rob_val_3 <= will_commit_0 ? ~((|{rob_head == 5'h3, _GEN_548}) | _GEN_516) & _GEN_583 : ~((|_GEN_548) | _GEN_516) & _GEN_583;
rob_val_4 <= will_commit_0 ? ~((|{rob_head == 5'h4, _GEN_549}) | _GEN_517) & _GEN_584 : ~((|_GEN_549) | _GEN_517) & _GEN_584;
rob_val_5 <= will_commit_0 ? ~((|{rob_head == 5'h5, _GEN_550}) | _GEN_518) & _GEN_585 : ~((|_GEN_550) | _GEN_518) & _GEN_585;
rob_val_6 <= will_commit_0 ? ~((|{rob_head == 5'h6, _GEN_551}) | _GEN_519) & _GEN_586 : ~((|_GEN_551) | _GEN_519) & _GEN_586;
rob_val_7 <= will_commit_0 ? ~((|{rob_head == 5'h7, _GEN_552}) | _GEN_520) & _GEN_587 : ~((|_GEN_552) | _GEN_520) & _GEN_587;
rob_val_8 <= will_commit_0 ? ~((|{rob_head == 5'h8, _GEN_553}) | _GEN_521) & _GEN_588 : ~((|_GEN_553) | _GEN_521) & _GEN_588;
rob_val_9 <= will_commit_0 ? ~((|{rob_head == 5'h9, _GEN_554}) | _GEN_522) & _GEN_589 : ~((|_GEN_554) | _GEN_522) & _GEN_589;
rob_val_10 <= will_commit_0 ? ~((|{rob_head == 5'hA, _GEN_555}) | _GEN_523) & _GEN_590 : ~((|_GEN_555) | _GEN_523) & _GEN_590;
rob_val_11 <= will_commit_0 ? ~((|{rob_head == 5'hB, _GEN_556}) | _GEN_524) & _GEN_591 : ~((|_GEN_556) | _GEN_524) & _GEN_591;
rob_val_12 <= will_commit_0 ? ~((|{rob_head == 5'hC, _GEN_557}) | _GEN_525) & _GEN_592 : ~((|_GEN_557) | _GEN_525) & _GEN_592;
rob_val_13 <= will_commit_0 ? ~((|{rob_head == 5'hD, _GEN_558}) | _GEN_526) & _GEN_593 : ~((|_GEN_558) | _GEN_526) & _GEN_593;
rob_val_14 <= will_commit_0 ? ~((|{rob_head == 5'hE, _GEN_559}) | _GEN_527) & _GEN_594 : ~((|_GEN_559) | _GEN_527) & _GEN_594;
rob_val_15 <= will_commit_0 ? ~((|{rob_head == 5'hF, _GEN_560}) | _GEN_528) & _GEN_595 : ~((|_GEN_560) | _GEN_528) & _GEN_595;
rob_val_16 <= will_commit_0 ? ~((|{rob_head == 5'h10, _GEN_561}) | _GEN_529) & _GEN_596 : ~((|_GEN_561) | _GEN_529) & _GEN_596;
rob_val_17 <= will_commit_0 ? ~((|{rob_head == 5'h11, _GEN_562}) | _GEN_530) & _GEN_597 : ~((|_GEN_562) | _GEN_530) & _GEN_597;
rob_val_18 <= will_commit_0 ? ~((|{rob_head == 5'h12, _GEN_563}) | _GEN_531) & _GEN_598 : ~((|_GEN_563) | _GEN_531) & _GEN_598;
rob_val_19 <= will_commit_0 ? ~((|{rob_head == 5'h13, _GEN_564}) | _GEN_532) & _GEN_599 : ~((|_GEN_564) | _GEN_532) & _GEN_599;
rob_val_20 <= will_commit_0 ? ~((|{rob_head == 5'h14, _GEN_565}) | _GEN_533) & _GEN_600 : ~((|_GEN_565) | _GEN_533) & _GEN_600;
rob_val_21 <= will_commit_0 ? ~((|{rob_head == 5'h15, _GEN_566}) | _GEN_534) & _GEN_601 : ~((|_GEN_566) | _GEN_534) & _GEN_601;
rob_val_22 <= will_commit_0 ? ~((|{rob_head == 5'h16, _GEN_567}) | _GEN_535) & _GEN_602 : ~((|_GEN_567) | _GEN_535) & _GEN_602;
rob_val_23 <= will_commit_0 ? ~((|{rob_head == 5'h17, _GEN_568}) | _GEN_536) & _GEN_603 : ~((|_GEN_568) | _GEN_536) & _GEN_603;
rob_val_24 <= will_commit_0 ? ~((|{rob_head == 5'h18, _GEN_569}) | _GEN_537) & _GEN_604 : ~((|_GEN_569) | _GEN_537) & _GEN_604;
rob_val_25 <= will_commit_0 ? ~((|{rob_head == 5'h19, _GEN_570}) | _GEN_538) & _GEN_605 : ~((|_GEN_570) | _GEN_538) & _GEN_605;
rob_val_26 <= will_commit_0 ? ~((|{rob_head == 5'h1A, _GEN_571}) | _GEN_539) & _GEN_606 : ~((|_GEN_571) | _GEN_539) & _GEN_606;
rob_val_27 <= will_commit_0 ? ~((|{rob_head == 5'h1B, _GEN_572}) | _GEN_540) & _GEN_607 : ~((|_GEN_572) | _GEN_540) & _GEN_607;
rob_val_28 <= will_commit_0 ? ~((|{rob_head == 5'h1C, _GEN_573}) | _GEN_541) & _GEN_608 : ~((|_GEN_573) | _GEN_541) & _GEN_608;
rob_val_29 <= will_commit_0 ? ~((|{rob_head == 5'h1D, _GEN_574}) | _GEN_542) & _GEN_609 : ~((|_GEN_574) | _GEN_542) & _GEN_609;
rob_val_30 <= will_commit_0 ? ~((|{rob_head == 5'h1E, _GEN_575}) | _GEN_543) & _GEN_610 : ~((|_GEN_575) | _GEN_543) & _GEN_610;
rob_val_31 <= will_commit_0 ? ~((|{&rob_head, _GEN_576}) | _GEN_544) & _GEN_611 : ~((|_GEN_576) | _GEN_544) & _GEN_611;
if (io_enq_valids_0)
r_partial_row <= io_enq_partial_stall;
pnr_maybe_at_tail <= ~rob_deq & (do_inc_row | pnr_maybe_at_tail);
end
r_xcpt_uop_br_mask <= next_xcpt_uop_br_mask & ~io_brupdate_b1_resolve_mask;
if (_GEN_577) begin
if (io_lxcpt_valid) begin
if (_GEN_578) begin
r_xcpt_uop_rob_idx <= io_lxcpt_bits_uop_rob_idx;
r_xcpt_uop_exc_cause <= {59'h0, io_lxcpt_bits_cause};
r_xcpt_badvaddr <= io_lxcpt_bits_badvaddr;
end
end
else if (_GEN_579) begin
r_xcpt_uop_rob_idx <= io_enq_uops_0_rob_idx;
r_xcpt_uop_exc_cause <= io_enq_uops_0_exc_cause;
r_xcpt_badvaddr <= {io_xcpt_fetch_pc[39:6], io_enq_uops_0_pc_lob};
end
end
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h0)
rob_fflags_0_0 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h0)
rob_fflags_0_0 <= io_fflags_0_bits_flags;
else if (_GEN_35)
rob_fflags_0_0 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h1)
rob_fflags_0_1 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h1)
rob_fflags_0_1 <= io_fflags_0_bits_flags;
else if (_GEN_36)
rob_fflags_0_1 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h2)
rob_fflags_0_2 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h2)
rob_fflags_0_2 <= io_fflags_0_bits_flags;
else if (_GEN_37)
rob_fflags_0_2 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h3)
rob_fflags_0_3 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h3)
rob_fflags_0_3 <= io_fflags_0_bits_flags;
else if (_GEN_38)
rob_fflags_0_3 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h4)
rob_fflags_0_4 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h4)
rob_fflags_0_4 <= io_fflags_0_bits_flags;
else if (_GEN_39)
rob_fflags_0_4 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h5)
rob_fflags_0_5 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h5)
rob_fflags_0_5 <= io_fflags_0_bits_flags;
else if (_GEN_40)
rob_fflags_0_5 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h6)
rob_fflags_0_6 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h6)
rob_fflags_0_6 <= io_fflags_0_bits_flags;
else if (_GEN_41)
rob_fflags_0_6 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h7)
rob_fflags_0_7 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h7)
rob_fflags_0_7 <= io_fflags_0_bits_flags;
else if (_GEN_42)
rob_fflags_0_7 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h8)
rob_fflags_0_8 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h8)
rob_fflags_0_8 <= io_fflags_0_bits_flags;
else if (_GEN_43)
rob_fflags_0_8 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h9)
rob_fflags_0_9 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h9)
rob_fflags_0_9 <= io_fflags_0_bits_flags;
else if (_GEN_44)
rob_fflags_0_9 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'hA)
rob_fflags_0_10 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'hA)
rob_fflags_0_10 <= io_fflags_0_bits_flags;
else if (_GEN_45)
rob_fflags_0_10 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'hB)
rob_fflags_0_11 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'hB)
rob_fflags_0_11 <= io_fflags_0_bits_flags;
else if (_GEN_46)
rob_fflags_0_11 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'hC)
rob_fflags_0_12 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'hC)
rob_fflags_0_12 <= io_fflags_0_bits_flags;
else if (_GEN_47)
rob_fflags_0_12 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'hD)
rob_fflags_0_13 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'hD)
rob_fflags_0_13 <= io_fflags_0_bits_flags;
else if (_GEN_48)
rob_fflags_0_13 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'hE)
rob_fflags_0_14 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'hE)
rob_fflags_0_14 <= io_fflags_0_bits_flags;
else if (_GEN_49)
rob_fflags_0_14 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'hF)
rob_fflags_0_15 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'hF)
rob_fflags_0_15 <= io_fflags_0_bits_flags;
else if (_GEN_50)
rob_fflags_0_15 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h10)
rob_fflags_0_16 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h10)
rob_fflags_0_16 <= io_fflags_0_bits_flags;
else if (_GEN_51)
rob_fflags_0_16 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h11)
rob_fflags_0_17 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h11)
rob_fflags_0_17 <= io_fflags_0_bits_flags;
else if (_GEN_52)
rob_fflags_0_17 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h12)
rob_fflags_0_18 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h12)
rob_fflags_0_18 <= io_fflags_0_bits_flags;
else if (_GEN_53)
rob_fflags_0_18 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h13)
rob_fflags_0_19 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h13)
rob_fflags_0_19 <= io_fflags_0_bits_flags;
else if (_GEN_54)
rob_fflags_0_19 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h14)
rob_fflags_0_20 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h14)
rob_fflags_0_20 <= io_fflags_0_bits_flags;
else if (_GEN_55)
rob_fflags_0_20 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h15)
rob_fflags_0_21 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h15)
rob_fflags_0_21 <= io_fflags_0_bits_flags;
else if (_GEN_56)
rob_fflags_0_21 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h16)
rob_fflags_0_22 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h16)
rob_fflags_0_22 <= io_fflags_0_bits_flags;
else if (_GEN_57)
rob_fflags_0_22 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h17)
rob_fflags_0_23 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h17)
rob_fflags_0_23 <= io_fflags_0_bits_flags;
else if (_GEN_58)
rob_fflags_0_23 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h18)
rob_fflags_0_24 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h18)
rob_fflags_0_24 <= io_fflags_0_bits_flags;
else if (_GEN_59)
rob_fflags_0_24 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h19)
rob_fflags_0_25 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h19)
rob_fflags_0_25 <= io_fflags_0_bits_flags;
else if (_GEN_60)
rob_fflags_0_25 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h1A)
rob_fflags_0_26 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h1A)
rob_fflags_0_26 <= io_fflags_0_bits_flags;
else if (_GEN_61)
rob_fflags_0_26 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h1B)
rob_fflags_0_27 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h1B)
rob_fflags_0_27 <= io_fflags_0_bits_flags;
else if (_GEN_62)
rob_fflags_0_27 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h1C)
rob_fflags_0_28 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h1C)
rob_fflags_0_28 <= io_fflags_0_bits_flags;
else if (_GEN_63)
rob_fflags_0_28 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h1D)
rob_fflags_0_29 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h1D)
rob_fflags_0_29 <= io_fflags_0_bits_flags;
else if (_GEN_64)
rob_fflags_0_29 <= 5'h0;
if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h1E)
rob_fflags_0_30 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h1E)
rob_fflags_0_30 <= io_fflags_0_bits_flags;
else if (_GEN_65)
rob_fflags_0_30 <= 5'h0;
if (io_fflags_1_valid & (&io_fflags_1_bits_uop_rob_idx))
rob_fflags_0_31 <= io_fflags_1_bits_flags;
else if (io_fflags_0_valid & (&io_fflags_0_bits_uop_rob_idx))
rob_fflags_0_31 <= io_fflags_0_bits_flags;
else if (_GEN_66)
rob_fflags_0_31 <= 5'h0;
rob_bsy_0 <= io_lsu_clr_bsy_1_valid ? ~_GEN_481 & _GEN_324 : ~_GEN_449 & _GEN_324;
rob_bsy_1 <= io_lsu_clr_bsy_1_valid ? ~_GEN_482 & _GEN_327 : ~_GEN_450 & _GEN_327;
rob_bsy_2 <= io_lsu_clr_bsy_1_valid ? ~_GEN_483 & _GEN_330 : ~_GEN_451 & _GEN_330;
rob_bsy_3 <= io_lsu_clr_bsy_1_valid ? ~_GEN_484 & _GEN_333 : ~_GEN_452 & _GEN_333;
rob_bsy_4 <= io_lsu_clr_bsy_1_valid ? ~_GEN_485 & _GEN_336 : ~_GEN_453 & _GEN_336;
rob_bsy_5 <= io_lsu_clr_bsy_1_valid ? ~_GEN_486 & _GEN_339 : ~_GEN_454 & _GEN_339;
rob_bsy_6 <= io_lsu_clr_bsy_1_valid ? ~_GEN_487 & _GEN_342 : ~_GEN_455 & _GEN_342;
rob_bsy_7 <= io_lsu_clr_bsy_1_valid ? ~_GEN_488 & _GEN_345 : ~_GEN_456 & _GEN_345;
rob_bsy_8 <= io_lsu_clr_bsy_1_valid ? ~_GEN_489 & _GEN_348 : ~_GEN_457 & _GEN_348;
rob_bsy_9 <= io_lsu_clr_bsy_1_valid ? ~_GEN_490 & _GEN_351 : ~_GEN_458 & _GEN_351;
rob_bsy_10 <= io_lsu_clr_bsy_1_valid ? ~_GEN_491 & _GEN_354 : ~_GEN_459 & _GEN_354;
rob_bsy_11 <= io_lsu_clr_bsy_1_valid ? ~_GEN_492 & _GEN_357 : ~_GEN_460 & _GEN_357;
rob_bsy_12 <= io_lsu_clr_bsy_1_valid ? ~_GEN_493 & _GEN_360 : ~_GEN_461 & _GEN_360;
rob_bsy_13 <= io_lsu_clr_bsy_1_valid ? ~_GEN_494 & _GEN_363 : ~_GEN_462 & _GEN_363;
rob_bsy_14 <= io_lsu_clr_bsy_1_valid ? ~_GEN_495 & _GEN_366 : ~_GEN_463 & _GEN_366;
rob_bsy_15 <= io_lsu_clr_bsy_1_valid ? ~_GEN_496 & _GEN_369 : ~_GEN_464 & _GEN_369;
rob_bsy_16 <= io_lsu_clr_bsy_1_valid ? ~_GEN_497 & _GEN_372 : ~_GEN_465 & _GEN_372;
rob_bsy_17 <= io_lsu_clr_bsy_1_valid ? ~_GEN_498 & _GEN_375 : ~_GEN_466 & _GEN_375;
rob_bsy_18 <= io_lsu_clr_bsy_1_valid ? ~_GEN_499 & _GEN_378 : ~_GEN_467 & _GEN_378;
rob_bsy_19 <= io_lsu_clr_bsy_1_valid ? ~_GEN_500 & _GEN_381 : ~_GEN_468 & _GEN_381;
rob_bsy_20 <= io_lsu_clr_bsy_1_valid ? ~_GEN_501 & _GEN_384 : ~_GEN_469 & _GEN_384;
rob_bsy_21 <= io_lsu_clr_bsy_1_valid ? ~_GEN_502 & _GEN_387 : ~_GEN_470 & _GEN_387;
rob_bsy_22 <= io_lsu_clr_bsy_1_valid ? ~_GEN_503 & _GEN_390 : ~_GEN_471 & _GEN_390;
rob_bsy_23 <= io_lsu_clr_bsy_1_valid ? ~_GEN_504 & _GEN_393 : ~_GEN_472 & _GEN_393;
rob_bsy_24 <= io_lsu_clr_bsy_1_valid ? ~_GEN_505 & _GEN_396 : ~_GEN_473 & _GEN_396;
rob_bsy_25 <= io_lsu_clr_bsy_1_valid ? ~_GEN_506 & _GEN_399 : ~_GEN_474 & _GEN_399;
rob_bsy_26 <= io_lsu_clr_bsy_1_valid ? ~_GEN_507 & _GEN_402 : ~_GEN_475 & _GEN_402;
rob_bsy_27 <= io_lsu_clr_bsy_1_valid ? ~_GEN_508 & _GEN_405 : ~_GEN_476 & _GEN_405;
rob_bsy_28 <= io_lsu_clr_bsy_1_valid ? ~_GEN_509 & _GEN_408 : ~_GEN_477 & _GEN_408;
rob_bsy_29 <= io_lsu_clr_bsy_1_valid ? ~_GEN_510 & _GEN_411 : ~_GEN_478 & _GEN_411;
rob_bsy_30 <= io_lsu_clr_bsy_1_valid ? ~_GEN_511 & _GEN_414 : ~_GEN_479 & _GEN_414;
rob_bsy_31 <= io_lsu_clr_bsy_1_valid ? ~_GEN_512 & _GEN_416 : ~_GEN_480 & _GEN_416;
rob_unsafe_0 <= io_lsu_clr_bsy_1_valid ? ~_GEN_481 & _GEN_417 : ~_GEN_449 & _GEN_417;
rob_unsafe_1 <= io_lsu_clr_bsy_1_valid ? ~_GEN_482 & _GEN_418 : ~_GEN_450 & _GEN_418;
rob_unsafe_2 <= io_lsu_clr_bsy_1_valid ? ~_GEN_483 & _GEN_419 : ~_GEN_451 & _GEN_419;
rob_unsafe_3 <= io_lsu_clr_bsy_1_valid ? ~_GEN_484 & _GEN_420 : ~_GEN_452 & _GEN_420;
rob_unsafe_4 <= io_lsu_clr_bsy_1_valid ? ~_GEN_485 & _GEN_421 : ~_GEN_453 & _GEN_421;
rob_unsafe_5 <= io_lsu_clr_bsy_1_valid ? ~_GEN_486 & _GEN_422 : ~_GEN_454 & _GEN_422;
rob_unsafe_6 <= io_lsu_clr_bsy_1_valid ? ~_GEN_487 & _GEN_423 : ~_GEN_455 & _GEN_423;
rob_unsafe_7 <= io_lsu_clr_bsy_1_valid ? ~_GEN_488 & _GEN_424 : ~_GEN_456 & _GEN_424;
rob_unsafe_8 <= io_lsu_clr_bsy_1_valid ? ~_GEN_489 & _GEN_425 : ~_GEN_457 & _GEN_425;
rob_unsafe_9 <= io_lsu_clr_bsy_1_valid ? ~_GEN_490 & _GEN_426 : ~_GEN_458 & _GEN_426;
rob_unsafe_10 <= io_lsu_clr_bsy_1_valid ? ~_GEN_491 & _GEN_427 : ~_GEN_459 & _GEN_427;
rob_unsafe_11 <= io_lsu_clr_bsy_1_valid ? ~_GEN_492 & _GEN_428 : ~_GEN_460 & _GEN_428;
rob_unsafe_12 <= io_lsu_clr_bsy_1_valid ? ~_GEN_493 & _GEN_429 : ~_GEN_461 & _GEN_429;
rob_unsafe_13 <= io_lsu_clr_bsy_1_valid ? ~_GEN_494 & _GEN_430 : ~_GEN_462 & _GEN_430;
rob_unsafe_14 <= io_lsu_clr_bsy_1_valid ? ~_GEN_495 & _GEN_431 : ~_GEN_463 & _GEN_431;
rob_unsafe_15 <= io_lsu_clr_bsy_1_valid ? ~_GEN_496 & _GEN_432 : ~_GEN_464 & _GEN_432;
rob_unsafe_16 <= io_lsu_clr_bsy_1_valid ? ~_GEN_497 & _GEN_433 : ~_GEN_465 & _GEN_433;
rob_unsafe_17 <= io_lsu_clr_bsy_1_valid ? ~_GEN_498 & _GEN_434 : ~_GEN_466 & _GEN_434;
rob_unsafe_18 <= io_lsu_clr_bsy_1_valid ? ~_GEN_499 & _GEN_435 : ~_GEN_467 & _GEN_435;
rob_unsafe_19 <= io_lsu_clr_bsy_1_valid ? ~_GEN_500 & _GEN_436 : ~_GEN_468 & _GEN_436;
rob_unsafe_20 <= io_lsu_clr_bsy_1_valid ? ~_GEN_501 & _GEN_437 : ~_GEN_469 & _GEN_437;
rob_unsafe_21 <= io_lsu_clr_bsy_1_valid ? ~_GEN_502 & _GEN_438 : ~_GEN_470 & _GEN_438;
rob_unsafe_22 <= io_lsu_clr_bsy_1_valid ? ~_GEN_503 & _GEN_439 : ~_GEN_471 & _GEN_439;
rob_unsafe_23 <= io_lsu_clr_bsy_1_valid ? ~_GEN_504 & _GEN_440 : ~_GEN_472 & _GEN_440;
rob_unsafe_24 <= io_lsu_clr_bsy_1_valid ? ~_GEN_505 & _GEN_441 : ~_GEN_473 & _GEN_441;
rob_unsafe_25 <= io_lsu_clr_bsy_1_valid ? ~_GEN_506 & _GEN_442 : ~_GEN_474 & _GEN_442;
rob_unsafe_26 <= io_lsu_clr_bsy_1_valid ? ~_GEN_507 & _GEN_443 : ~_GEN_475 & _GEN_443;
rob_unsafe_27 <= io_lsu_clr_bsy_1_valid ? ~_GEN_508 & _GEN_444 : ~_GEN_476 & _GEN_444;
rob_unsafe_28 <= io_lsu_clr_bsy_1_valid ? ~_GEN_509 & _GEN_445 : ~_GEN_477 & _GEN_445;
rob_unsafe_29 <= io_lsu_clr_bsy_1_valid ? ~_GEN_510 & _GEN_446 : ~_GEN_478 & _GEN_446;
rob_unsafe_30 <= io_lsu_clr_bsy_1_valid ? ~_GEN_511 & _GEN_447 : ~_GEN_479 & _GEN_447;
rob_unsafe_31 <= io_lsu_clr_bsy_1_valid ? ~_GEN_512 & _GEN_448 : ~_GEN_480 & _GEN_448;
if (_GEN_35) begin
rob_uop_0_uopc <= io_enq_uops_0_uopc;
rob_uop_0_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_0_is_br <= io_enq_uops_0_is_br;
rob_uop_0_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_0_is_jal <= io_enq_uops_0_is_jal;
rob_uop_0_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_0_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_0_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_0_pdst <= io_enq_uops_0_pdst;
rob_uop_0_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_0_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_0_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_0_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_0_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_0_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_0_ldst <= io_enq_uops_0_ldst;
rob_uop_0_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_0_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_0_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_545) | ~rob_val_0) begin
if (_GEN_35)
rob_uop_0_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_0_br_mask <= rob_uop_0_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h0)
rob_uop_0_debug_fsrc <= 2'h3;
else if (_GEN_35)
rob_uop_0_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_36) begin
rob_uop_1_uopc <= io_enq_uops_0_uopc;
rob_uop_1_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_1_is_br <= io_enq_uops_0_is_br;
rob_uop_1_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_1_is_jal <= io_enq_uops_0_is_jal;
rob_uop_1_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_1_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_1_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_1_pdst <= io_enq_uops_0_pdst;
rob_uop_1_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_1_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_1_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_1_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_1_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_1_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_1_ldst <= io_enq_uops_0_ldst;
rob_uop_1_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_1_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_1_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_546) | ~rob_val_1) begin
if (_GEN_36)
rob_uop_1_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_1_br_mask <= rob_uop_1_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h1)
rob_uop_1_debug_fsrc <= 2'h3;
else if (_GEN_36)
rob_uop_1_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_37) begin
rob_uop_2_uopc <= io_enq_uops_0_uopc;
rob_uop_2_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_2_is_br <= io_enq_uops_0_is_br;
rob_uop_2_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_2_is_jal <= io_enq_uops_0_is_jal;
rob_uop_2_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_2_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_2_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_2_pdst <= io_enq_uops_0_pdst;
rob_uop_2_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_2_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_2_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_2_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_2_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_2_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_2_ldst <= io_enq_uops_0_ldst;
rob_uop_2_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_2_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_2_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_547) | ~rob_val_2) begin
if (_GEN_37)
rob_uop_2_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_2_br_mask <= rob_uop_2_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h2)
rob_uop_2_debug_fsrc <= 2'h3;
else if (_GEN_37)
rob_uop_2_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_38) begin
rob_uop_3_uopc <= io_enq_uops_0_uopc;
rob_uop_3_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_3_is_br <= io_enq_uops_0_is_br;
rob_uop_3_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_3_is_jal <= io_enq_uops_0_is_jal;
rob_uop_3_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_3_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_3_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_3_pdst <= io_enq_uops_0_pdst;
rob_uop_3_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_3_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_3_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_3_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_3_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_3_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_3_ldst <= io_enq_uops_0_ldst;
rob_uop_3_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_3_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_3_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_548) | ~rob_val_3) begin
if (_GEN_38)
rob_uop_3_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_3_br_mask <= rob_uop_3_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h3)
rob_uop_3_debug_fsrc <= 2'h3;
else if (_GEN_38)
rob_uop_3_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_39) begin
rob_uop_4_uopc <= io_enq_uops_0_uopc;
rob_uop_4_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_4_is_br <= io_enq_uops_0_is_br;
rob_uop_4_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_4_is_jal <= io_enq_uops_0_is_jal;
rob_uop_4_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_4_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_4_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_4_pdst <= io_enq_uops_0_pdst;
rob_uop_4_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_4_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_4_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_4_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_4_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_4_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_4_ldst <= io_enq_uops_0_ldst;
rob_uop_4_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_4_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_4_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_549) | ~rob_val_4) begin
if (_GEN_39)
rob_uop_4_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_4_br_mask <= rob_uop_4_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h4)
rob_uop_4_debug_fsrc <= 2'h3;
else if (_GEN_39)
rob_uop_4_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_40) begin
rob_uop_5_uopc <= io_enq_uops_0_uopc;
rob_uop_5_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_5_is_br <= io_enq_uops_0_is_br;
rob_uop_5_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_5_is_jal <= io_enq_uops_0_is_jal;
rob_uop_5_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_5_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_5_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_5_pdst <= io_enq_uops_0_pdst;
rob_uop_5_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_5_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_5_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_5_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_5_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_5_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_5_ldst <= io_enq_uops_0_ldst;
rob_uop_5_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_5_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_5_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_550) | ~rob_val_5) begin
if (_GEN_40)
rob_uop_5_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_5_br_mask <= rob_uop_5_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h5)
rob_uop_5_debug_fsrc <= 2'h3;
else if (_GEN_40)
rob_uop_5_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_41) begin
rob_uop_6_uopc <= io_enq_uops_0_uopc;
rob_uop_6_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_6_is_br <= io_enq_uops_0_is_br;
rob_uop_6_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_6_is_jal <= io_enq_uops_0_is_jal;
rob_uop_6_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_6_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_6_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_6_pdst <= io_enq_uops_0_pdst;
rob_uop_6_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_6_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_6_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_6_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_6_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_6_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_6_ldst <= io_enq_uops_0_ldst;
rob_uop_6_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_6_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_6_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_551) | ~rob_val_6) begin
if (_GEN_41)
rob_uop_6_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_6_br_mask <= rob_uop_6_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h6)
rob_uop_6_debug_fsrc <= 2'h3;
else if (_GEN_41)
rob_uop_6_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_42) begin
rob_uop_7_uopc <= io_enq_uops_0_uopc;
rob_uop_7_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_7_is_br <= io_enq_uops_0_is_br;
rob_uop_7_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_7_is_jal <= io_enq_uops_0_is_jal;
rob_uop_7_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_7_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_7_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_7_pdst <= io_enq_uops_0_pdst;
rob_uop_7_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_7_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_7_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_7_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_7_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_7_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_7_ldst <= io_enq_uops_0_ldst;
rob_uop_7_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_7_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_7_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_552) | ~rob_val_7) begin
if (_GEN_42)
rob_uop_7_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_7_br_mask <= rob_uop_7_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h7)
rob_uop_7_debug_fsrc <= 2'h3;
else if (_GEN_42)
rob_uop_7_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_43) begin
rob_uop_8_uopc <= io_enq_uops_0_uopc;
rob_uop_8_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_8_is_br <= io_enq_uops_0_is_br;
rob_uop_8_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_8_is_jal <= io_enq_uops_0_is_jal;
rob_uop_8_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_8_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_8_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_8_pdst <= io_enq_uops_0_pdst;
rob_uop_8_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_8_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_8_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_8_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_8_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_8_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_8_ldst <= io_enq_uops_0_ldst;
rob_uop_8_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_8_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_8_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_553) | ~rob_val_8) begin
if (_GEN_43)
rob_uop_8_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_8_br_mask <= rob_uop_8_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h8)
rob_uop_8_debug_fsrc <= 2'h3;
else if (_GEN_43)
rob_uop_8_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_44) begin
rob_uop_9_uopc <= io_enq_uops_0_uopc;
rob_uop_9_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_9_is_br <= io_enq_uops_0_is_br;
rob_uop_9_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_9_is_jal <= io_enq_uops_0_is_jal;
rob_uop_9_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_9_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_9_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_9_pdst <= io_enq_uops_0_pdst;
rob_uop_9_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_9_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_9_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_9_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_9_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_9_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_9_ldst <= io_enq_uops_0_ldst;
rob_uop_9_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_9_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_9_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_554) | ~rob_val_9) begin
if (_GEN_44)
rob_uop_9_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_9_br_mask <= rob_uop_9_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h9)
rob_uop_9_debug_fsrc <= 2'h3;
else if (_GEN_44)
rob_uop_9_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_45) begin
rob_uop_10_uopc <= io_enq_uops_0_uopc;
rob_uop_10_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_10_is_br <= io_enq_uops_0_is_br;
rob_uop_10_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_10_is_jal <= io_enq_uops_0_is_jal;
rob_uop_10_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_10_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_10_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_10_pdst <= io_enq_uops_0_pdst;
rob_uop_10_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_10_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_10_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_10_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_10_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_10_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_10_ldst <= io_enq_uops_0_ldst;
rob_uop_10_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_10_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_10_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_555) | ~rob_val_10) begin
if (_GEN_45)
rob_uop_10_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_10_br_mask <= rob_uop_10_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'hA)
rob_uop_10_debug_fsrc <= 2'h3;
else if (_GEN_45)
rob_uop_10_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_46) begin
rob_uop_11_uopc <= io_enq_uops_0_uopc;
rob_uop_11_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_11_is_br <= io_enq_uops_0_is_br;
rob_uop_11_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_11_is_jal <= io_enq_uops_0_is_jal;
rob_uop_11_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_11_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_11_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_11_pdst <= io_enq_uops_0_pdst;
rob_uop_11_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_11_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_11_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_11_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_11_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_11_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_11_ldst <= io_enq_uops_0_ldst;
rob_uop_11_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_11_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_11_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_556) | ~rob_val_11) begin
if (_GEN_46)
rob_uop_11_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_11_br_mask <= rob_uop_11_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'hB)
rob_uop_11_debug_fsrc <= 2'h3;
else if (_GEN_46)
rob_uop_11_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_47) begin
rob_uop_12_uopc <= io_enq_uops_0_uopc;
rob_uop_12_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_12_is_br <= io_enq_uops_0_is_br;
rob_uop_12_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_12_is_jal <= io_enq_uops_0_is_jal;
rob_uop_12_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_12_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_12_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_12_pdst <= io_enq_uops_0_pdst;
rob_uop_12_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_12_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_12_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_12_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_12_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_12_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_12_ldst <= io_enq_uops_0_ldst;
rob_uop_12_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_12_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_12_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_557) | ~rob_val_12) begin
if (_GEN_47)
rob_uop_12_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_12_br_mask <= rob_uop_12_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'hC)
rob_uop_12_debug_fsrc <= 2'h3;
else if (_GEN_47)
rob_uop_12_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_48) begin
rob_uop_13_uopc <= io_enq_uops_0_uopc;
rob_uop_13_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_13_is_br <= io_enq_uops_0_is_br;
rob_uop_13_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_13_is_jal <= io_enq_uops_0_is_jal;
rob_uop_13_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_13_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_13_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_13_pdst <= io_enq_uops_0_pdst;
rob_uop_13_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_13_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_13_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_13_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_13_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_13_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_13_ldst <= io_enq_uops_0_ldst;
rob_uop_13_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_13_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_13_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_558) | ~rob_val_13) begin
if (_GEN_48)
rob_uop_13_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_13_br_mask <= rob_uop_13_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'hD)
rob_uop_13_debug_fsrc <= 2'h3;
else if (_GEN_48)
rob_uop_13_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_49) begin
rob_uop_14_uopc <= io_enq_uops_0_uopc;
rob_uop_14_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_14_is_br <= io_enq_uops_0_is_br;
rob_uop_14_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_14_is_jal <= io_enq_uops_0_is_jal;
rob_uop_14_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_14_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_14_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_14_pdst <= io_enq_uops_0_pdst;
rob_uop_14_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_14_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_14_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_14_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_14_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_14_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_14_ldst <= io_enq_uops_0_ldst;
rob_uop_14_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_14_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_14_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_559) | ~rob_val_14) begin
if (_GEN_49)
rob_uop_14_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_14_br_mask <= rob_uop_14_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'hE)
rob_uop_14_debug_fsrc <= 2'h3;
else if (_GEN_49)
rob_uop_14_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_50) begin
rob_uop_15_uopc <= io_enq_uops_0_uopc;
rob_uop_15_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_15_is_br <= io_enq_uops_0_is_br;
rob_uop_15_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_15_is_jal <= io_enq_uops_0_is_jal;
rob_uop_15_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_15_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_15_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_15_pdst <= io_enq_uops_0_pdst;
rob_uop_15_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_15_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_15_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_15_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_15_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_15_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_15_ldst <= io_enq_uops_0_ldst;
rob_uop_15_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_15_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_15_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_560) | ~rob_val_15) begin
if (_GEN_50)
rob_uop_15_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_15_br_mask <= rob_uop_15_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'hF)
rob_uop_15_debug_fsrc <= 2'h3;
else if (_GEN_50)
rob_uop_15_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_51) begin
rob_uop_16_uopc <= io_enq_uops_0_uopc;
rob_uop_16_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_16_is_br <= io_enq_uops_0_is_br;
rob_uop_16_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_16_is_jal <= io_enq_uops_0_is_jal;
rob_uop_16_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_16_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_16_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_16_pdst <= io_enq_uops_0_pdst;
rob_uop_16_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_16_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_16_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_16_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_16_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_16_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_16_ldst <= io_enq_uops_0_ldst;
rob_uop_16_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_16_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_16_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_561) | ~rob_val_16) begin
if (_GEN_51)
rob_uop_16_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_16_br_mask <= rob_uop_16_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h10)
rob_uop_16_debug_fsrc <= 2'h3;
else if (_GEN_51)
rob_uop_16_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_52) begin
rob_uop_17_uopc <= io_enq_uops_0_uopc;
rob_uop_17_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_17_is_br <= io_enq_uops_0_is_br;
rob_uop_17_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_17_is_jal <= io_enq_uops_0_is_jal;
rob_uop_17_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_17_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_17_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_17_pdst <= io_enq_uops_0_pdst;
rob_uop_17_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_17_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_17_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_17_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_17_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_17_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_17_ldst <= io_enq_uops_0_ldst;
rob_uop_17_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_17_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_17_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_562) | ~rob_val_17) begin
if (_GEN_52)
rob_uop_17_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_17_br_mask <= rob_uop_17_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h11)
rob_uop_17_debug_fsrc <= 2'h3;
else if (_GEN_52)
rob_uop_17_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_53) begin
rob_uop_18_uopc <= io_enq_uops_0_uopc;
rob_uop_18_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_18_is_br <= io_enq_uops_0_is_br;
rob_uop_18_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_18_is_jal <= io_enq_uops_0_is_jal;
rob_uop_18_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_18_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_18_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_18_pdst <= io_enq_uops_0_pdst;
rob_uop_18_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_18_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_18_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_18_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_18_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_18_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_18_ldst <= io_enq_uops_0_ldst;
rob_uop_18_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_18_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_18_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_563) | ~rob_val_18) begin
if (_GEN_53)
rob_uop_18_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_18_br_mask <= rob_uop_18_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h12)
rob_uop_18_debug_fsrc <= 2'h3;
else if (_GEN_53)
rob_uop_18_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_54) begin
rob_uop_19_uopc <= io_enq_uops_0_uopc;
rob_uop_19_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_19_is_br <= io_enq_uops_0_is_br;
rob_uop_19_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_19_is_jal <= io_enq_uops_0_is_jal;
rob_uop_19_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_19_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_19_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_19_pdst <= io_enq_uops_0_pdst;
rob_uop_19_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_19_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_19_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_19_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_19_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_19_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_19_ldst <= io_enq_uops_0_ldst;
rob_uop_19_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_19_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_19_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_564) | ~rob_val_19) begin
if (_GEN_54)
rob_uop_19_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_19_br_mask <= rob_uop_19_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h13)
rob_uop_19_debug_fsrc <= 2'h3;
else if (_GEN_54)
rob_uop_19_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_55) begin
rob_uop_20_uopc <= io_enq_uops_0_uopc;
rob_uop_20_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_20_is_br <= io_enq_uops_0_is_br;
rob_uop_20_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_20_is_jal <= io_enq_uops_0_is_jal;
rob_uop_20_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_20_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_20_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_20_pdst <= io_enq_uops_0_pdst;
rob_uop_20_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_20_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_20_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_20_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_20_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_20_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_20_ldst <= io_enq_uops_0_ldst;
rob_uop_20_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_20_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_20_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_565) | ~rob_val_20) begin
if (_GEN_55)
rob_uop_20_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_20_br_mask <= rob_uop_20_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h14)
rob_uop_20_debug_fsrc <= 2'h3;
else if (_GEN_55)
rob_uop_20_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_56) begin
rob_uop_21_uopc <= io_enq_uops_0_uopc;
rob_uop_21_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_21_is_br <= io_enq_uops_0_is_br;
rob_uop_21_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_21_is_jal <= io_enq_uops_0_is_jal;
rob_uop_21_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_21_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_21_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_21_pdst <= io_enq_uops_0_pdst;
rob_uop_21_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_21_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_21_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_21_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_21_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_21_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_21_ldst <= io_enq_uops_0_ldst;
rob_uop_21_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_21_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_21_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_566) | ~rob_val_21) begin
if (_GEN_56)
rob_uop_21_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_21_br_mask <= rob_uop_21_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h15)
rob_uop_21_debug_fsrc <= 2'h3;
else if (_GEN_56)
rob_uop_21_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_57) begin
rob_uop_22_uopc <= io_enq_uops_0_uopc;
rob_uop_22_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_22_is_br <= io_enq_uops_0_is_br;
rob_uop_22_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_22_is_jal <= io_enq_uops_0_is_jal;
rob_uop_22_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_22_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_22_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_22_pdst <= io_enq_uops_0_pdst;
rob_uop_22_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_22_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_22_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_22_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_22_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_22_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_22_ldst <= io_enq_uops_0_ldst;
rob_uop_22_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_22_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_22_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_567) | ~rob_val_22) begin
if (_GEN_57)
rob_uop_22_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_22_br_mask <= rob_uop_22_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h16)
rob_uop_22_debug_fsrc <= 2'h3;
else if (_GEN_57)
rob_uop_22_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_58) begin
rob_uop_23_uopc <= io_enq_uops_0_uopc;
rob_uop_23_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_23_is_br <= io_enq_uops_0_is_br;
rob_uop_23_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_23_is_jal <= io_enq_uops_0_is_jal;
rob_uop_23_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_23_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_23_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_23_pdst <= io_enq_uops_0_pdst;
rob_uop_23_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_23_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_23_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_23_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_23_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_23_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_23_ldst <= io_enq_uops_0_ldst;
rob_uop_23_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_23_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_23_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_568) | ~rob_val_23) begin
if (_GEN_58)
rob_uop_23_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_23_br_mask <= rob_uop_23_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h17)
rob_uop_23_debug_fsrc <= 2'h3;
else if (_GEN_58)
rob_uop_23_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_59) begin
rob_uop_24_uopc <= io_enq_uops_0_uopc;
rob_uop_24_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_24_is_br <= io_enq_uops_0_is_br;
rob_uop_24_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_24_is_jal <= io_enq_uops_0_is_jal;
rob_uop_24_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_24_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_24_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_24_pdst <= io_enq_uops_0_pdst;
rob_uop_24_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_24_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_24_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_24_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_24_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_24_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_24_ldst <= io_enq_uops_0_ldst;
rob_uop_24_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_24_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_24_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_569) | ~rob_val_24) begin
if (_GEN_59)
rob_uop_24_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_24_br_mask <= rob_uop_24_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h18)
rob_uop_24_debug_fsrc <= 2'h3;
else if (_GEN_59)
rob_uop_24_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_60) begin
rob_uop_25_uopc <= io_enq_uops_0_uopc;
rob_uop_25_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_25_is_br <= io_enq_uops_0_is_br;
rob_uop_25_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_25_is_jal <= io_enq_uops_0_is_jal;
rob_uop_25_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_25_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_25_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_25_pdst <= io_enq_uops_0_pdst;
rob_uop_25_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_25_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_25_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_25_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_25_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_25_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_25_ldst <= io_enq_uops_0_ldst;
rob_uop_25_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_25_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_25_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_570) | ~rob_val_25) begin
if (_GEN_60)
rob_uop_25_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_25_br_mask <= rob_uop_25_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h19)
rob_uop_25_debug_fsrc <= 2'h3;
else if (_GEN_60)
rob_uop_25_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_61) begin
rob_uop_26_uopc <= io_enq_uops_0_uopc;
rob_uop_26_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_26_is_br <= io_enq_uops_0_is_br;
rob_uop_26_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_26_is_jal <= io_enq_uops_0_is_jal;
rob_uop_26_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_26_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_26_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_26_pdst <= io_enq_uops_0_pdst;
rob_uop_26_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_26_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_26_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_26_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_26_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_26_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_26_ldst <= io_enq_uops_0_ldst;
rob_uop_26_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_26_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_26_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_571) | ~rob_val_26) begin
if (_GEN_61)
rob_uop_26_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_26_br_mask <= rob_uop_26_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h1A)
rob_uop_26_debug_fsrc <= 2'h3;
else if (_GEN_61)
rob_uop_26_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_62) begin
rob_uop_27_uopc <= io_enq_uops_0_uopc;
rob_uop_27_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_27_is_br <= io_enq_uops_0_is_br;
rob_uop_27_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_27_is_jal <= io_enq_uops_0_is_jal;
rob_uop_27_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_27_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_27_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_27_pdst <= io_enq_uops_0_pdst;
rob_uop_27_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_27_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_27_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_27_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_27_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_27_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_27_ldst <= io_enq_uops_0_ldst;
rob_uop_27_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_27_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_27_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_572) | ~rob_val_27) begin
if (_GEN_62)
rob_uop_27_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_27_br_mask <= rob_uop_27_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h1B)
rob_uop_27_debug_fsrc <= 2'h3;
else if (_GEN_62)
rob_uop_27_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_63) begin
rob_uop_28_uopc <= io_enq_uops_0_uopc;
rob_uop_28_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_28_is_br <= io_enq_uops_0_is_br;
rob_uop_28_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_28_is_jal <= io_enq_uops_0_is_jal;
rob_uop_28_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_28_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_28_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_28_pdst <= io_enq_uops_0_pdst;
rob_uop_28_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_28_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_28_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_28_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_28_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_28_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_28_ldst <= io_enq_uops_0_ldst;
rob_uop_28_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_28_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_28_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_573) | ~rob_val_28) begin
if (_GEN_63)
rob_uop_28_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_28_br_mask <= rob_uop_28_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h1C)
rob_uop_28_debug_fsrc <= 2'h3;
else if (_GEN_63)
rob_uop_28_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_64) begin
rob_uop_29_uopc <= io_enq_uops_0_uopc;
rob_uop_29_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_29_is_br <= io_enq_uops_0_is_br;
rob_uop_29_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_29_is_jal <= io_enq_uops_0_is_jal;
rob_uop_29_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_29_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_29_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_29_pdst <= io_enq_uops_0_pdst;
rob_uop_29_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_29_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_29_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_29_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_29_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_29_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_29_ldst <= io_enq_uops_0_ldst;
rob_uop_29_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_29_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_29_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_574) | ~rob_val_29) begin
if (_GEN_64)
rob_uop_29_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_29_br_mask <= rob_uop_29_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h1D)
rob_uop_29_debug_fsrc <= 2'h3;
else if (_GEN_64)
rob_uop_29_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_65) begin
rob_uop_30_uopc <= io_enq_uops_0_uopc;
rob_uop_30_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_30_is_br <= io_enq_uops_0_is_br;
rob_uop_30_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_30_is_jal <= io_enq_uops_0_is_jal;
rob_uop_30_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_30_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_30_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_30_pdst <= io_enq_uops_0_pdst;
rob_uop_30_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_30_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_30_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_30_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_30_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_30_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_30_ldst <= io_enq_uops_0_ldst;
rob_uop_30_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_30_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_30_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_575) | ~rob_val_30) begin
if (_GEN_65)
rob_uop_30_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_30_br_mask <= rob_uop_30_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h1E)
rob_uop_30_debug_fsrc <= 2'h3;
else if (_GEN_65)
rob_uop_30_debug_fsrc <= io_enq_uops_0_debug_fsrc;
if (_GEN_66) begin
rob_uop_31_uopc <= io_enq_uops_0_uopc;
rob_uop_31_is_rvc <= io_enq_uops_0_is_rvc;
rob_uop_31_is_br <= io_enq_uops_0_is_br;
rob_uop_31_is_jalr <= io_enq_uops_0_is_jalr;
rob_uop_31_is_jal <= io_enq_uops_0_is_jal;
rob_uop_31_ftq_idx <= io_enq_uops_0_ftq_idx;
rob_uop_31_edge_inst <= io_enq_uops_0_edge_inst;
rob_uop_31_pc_lob <= io_enq_uops_0_pc_lob;
rob_uop_31_pdst <= io_enq_uops_0_pdst;
rob_uop_31_stale_pdst <= io_enq_uops_0_stale_pdst;
rob_uop_31_is_fencei <= io_enq_uops_0_is_fencei;
rob_uop_31_uses_ldq <= io_enq_uops_0_uses_ldq;
rob_uop_31_uses_stq <= io_enq_uops_0_uses_stq;
rob_uop_31_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;
rob_uop_31_flush_on_commit <= io_enq_uops_0_flush_on_commit;
rob_uop_31_ldst <= io_enq_uops_0_ldst;
rob_uop_31_ldst_val <= io_enq_uops_0_ldst_val;
rob_uop_31_dst_rtype <= io_enq_uops_0_dst_rtype;
rob_uop_31_fp_val <= io_enq_uops_0_fp_val;
end
if ((|_GEN_576) | ~rob_val_31) begin
if (_GEN_66)
rob_uop_31_br_mask <= io_enq_uops_0_br_mask;
end
else
rob_uop_31_br_mask <= rob_uop_31_br_mask & ~io_brupdate_b1_resolve_mask;
if (io_brupdate_b2_mispredict & (&io_brupdate_b2_uop_rob_idx))
rob_uop_31_debug_fsrc <= 2'h3;
else if (_GEN_66)
rob_uop_31_debug_fsrc <= io_enq_uops_0_debug_fsrc;
rob_exception_0 <= ~_GEN_513 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h0 | (_GEN_35 ? io_enq_uops_0_exception : rob_exception_0));
rob_exception_1 <= ~_GEN_514 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h1 | (_GEN_36 ? io_enq_uops_0_exception : rob_exception_1));
rob_exception_2 <= ~_GEN_515 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h2 | (_GEN_37 ? io_enq_uops_0_exception : rob_exception_2));
rob_exception_3 <= ~_GEN_516 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h3 | (_GEN_38 ? io_enq_uops_0_exception : rob_exception_3));
rob_exception_4 <= ~_GEN_517 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h4 | (_GEN_39 ? io_enq_uops_0_exception : rob_exception_4));
rob_exception_5 <= ~_GEN_518 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h5 | (_GEN_40 ? io_enq_uops_0_exception : rob_exception_5));
rob_exception_6 <= ~_GEN_519 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h6 | (_GEN_41 ? io_enq_uops_0_exception : rob_exception_6));
rob_exception_7 <= ~_GEN_520 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h7 | (_GEN_42 ? io_enq_uops_0_exception : rob_exception_7));
rob_exception_8 <= ~_GEN_521 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h8 | (_GEN_43 ? io_enq_uops_0_exception : rob_exception_8));
rob_exception_9 <= ~_GEN_522 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h9 | (_GEN_44 ? io_enq_uops_0_exception : rob_exception_9));
rob_exception_10 <= ~_GEN_523 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'hA | (_GEN_45 ? io_enq_uops_0_exception : rob_exception_10));
rob_exception_11 <= ~_GEN_524 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'hB | (_GEN_46 ? io_enq_uops_0_exception : rob_exception_11));
rob_exception_12 <= ~_GEN_525 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'hC | (_GEN_47 ? io_enq_uops_0_exception : rob_exception_12));
rob_exception_13 <= ~_GEN_526 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'hD | (_GEN_48 ? io_enq_uops_0_exception : rob_exception_13));
rob_exception_14 <= ~_GEN_527 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'hE | (_GEN_49 ? io_enq_uops_0_exception : rob_exception_14));
rob_exception_15 <= ~_GEN_528 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'hF | (_GEN_50 ? io_enq_uops_0_exception : rob_exception_15));
rob_exception_16 <= ~_GEN_529 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h10 | (_GEN_51 ? io_enq_uops_0_exception : rob_exception_16));
rob_exception_17 <= ~_GEN_530 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h11 | (_GEN_52 ? io_enq_uops_0_exception : rob_exception_17));
rob_exception_18 <= ~_GEN_531 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h12 | (_GEN_53 ? io_enq_uops_0_exception : rob_exception_18));
rob_exception_19 <= ~_GEN_532 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h13 | (_GEN_54 ? io_enq_uops_0_exception : rob_exception_19));
rob_exception_20 <= ~_GEN_533 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h14 | (_GEN_55 ? io_enq_uops_0_exception : rob_exception_20));
rob_exception_21 <= ~_GEN_534 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h15 | (_GEN_56 ? io_enq_uops_0_exception : rob_exception_21));
rob_exception_22 <= ~_GEN_535 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h16 | (_GEN_57 ? io_enq_uops_0_exception : rob_exception_22));
rob_exception_23 <= ~_GEN_536 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h17 | (_GEN_58 ? io_enq_uops_0_exception : rob_exception_23));
rob_exception_24 <= ~_GEN_537 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h18 | (_GEN_59 ? io_enq_uops_0_exception : rob_exception_24));
rob_exception_25 <= ~_GEN_538 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h19 | (_GEN_60 ? io_enq_uops_0_exception : rob_exception_25));
rob_exception_26 <= ~_GEN_539 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h1A | (_GEN_61 ? io_enq_uops_0_exception : rob_exception_26));
rob_exception_27 <= ~_GEN_540 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h1B | (_GEN_62 ? io_enq_uops_0_exception : rob_exception_27));
rob_exception_28 <= ~_GEN_541 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h1C | (_GEN_63 ? io_enq_uops_0_exception : rob_exception_28));
rob_exception_29 <= ~_GEN_542 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h1D | (_GEN_64 ? io_enq_uops_0_exception : rob_exception_29));
rob_exception_30 <= ~_GEN_543 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h1E | (_GEN_65 ? io_enq_uops_0_exception : rob_exception_30));
rob_exception_31 <= ~_GEN_544 & (io_lxcpt_valid & (&io_lxcpt_bits_uop_rob_idx) | (_GEN_66 ? io_enq_uops_0_exception : rob_exception_31));
rob_predicated_0 <= ~(io_wb_resps_3_valid & _GEN_322) & (_GEN_290 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_163) & (_GEN_131 ? io_wb_resps_0_bits_predicated : ~_GEN_35 & rob_predicated_0));
rob_predicated_1 <= ~(io_wb_resps_3_valid & _GEN_325) & (_GEN_291 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_166) & (_GEN_132 ? io_wb_resps_0_bits_predicated : ~_GEN_36 & rob_predicated_1));
rob_predicated_2 <= ~(io_wb_resps_3_valid & _GEN_328) & (_GEN_292 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_169) & (_GEN_133 ? io_wb_resps_0_bits_predicated : ~_GEN_37 & rob_predicated_2));
rob_predicated_3 <= ~(io_wb_resps_3_valid & _GEN_331) & (_GEN_293 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_172) & (_GEN_134 ? io_wb_resps_0_bits_predicated : ~_GEN_38 & rob_predicated_3));
rob_predicated_4 <= ~(io_wb_resps_3_valid & _GEN_334) & (_GEN_294 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_175) & (_GEN_135 ? io_wb_resps_0_bits_predicated : ~_GEN_39 & rob_predicated_4));
rob_predicated_5 <= ~(io_wb_resps_3_valid & _GEN_337) & (_GEN_295 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_178) & (_GEN_136 ? io_wb_resps_0_bits_predicated : ~_GEN_40 & rob_predicated_5));
rob_predicated_6 <= ~(io_wb_resps_3_valid & _GEN_340) & (_GEN_296 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_181) & (_GEN_137 ? io_wb_resps_0_bits_predicated : ~_GEN_41 & rob_predicated_6));
rob_predicated_7 <= ~(io_wb_resps_3_valid & _GEN_343) & (_GEN_297 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_184) & (_GEN_138 ? io_wb_resps_0_bits_predicated : ~_GEN_42 & rob_predicated_7));
rob_predicated_8 <= ~(io_wb_resps_3_valid & _GEN_346) & (_GEN_298 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_187) & (_GEN_139 ? io_wb_resps_0_bits_predicated : ~_GEN_43 & rob_predicated_8));
rob_predicated_9 <= ~(io_wb_resps_3_valid & _GEN_349) & (_GEN_299 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_190) & (_GEN_140 ? io_wb_resps_0_bits_predicated : ~_GEN_44 & rob_predicated_9));
rob_predicated_10 <= ~(io_wb_resps_3_valid & _GEN_352) & (_GEN_300 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_193) & (_GEN_141 ? io_wb_resps_0_bits_predicated : ~_GEN_45 & rob_predicated_10));
rob_predicated_11 <= ~(io_wb_resps_3_valid & _GEN_355) & (_GEN_301 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_196) & (_GEN_142 ? io_wb_resps_0_bits_predicated : ~_GEN_46 & rob_predicated_11));
rob_predicated_12 <= ~(io_wb_resps_3_valid & _GEN_358) & (_GEN_302 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_199) & (_GEN_143 ? io_wb_resps_0_bits_predicated : ~_GEN_47 & rob_predicated_12));
rob_predicated_13 <= ~(io_wb_resps_3_valid & _GEN_361) & (_GEN_303 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_202) & (_GEN_144 ? io_wb_resps_0_bits_predicated : ~_GEN_48 & rob_predicated_13));
rob_predicated_14 <= ~(io_wb_resps_3_valid & _GEN_364) & (_GEN_304 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_205) & (_GEN_145 ? io_wb_resps_0_bits_predicated : ~_GEN_49 & rob_predicated_14));
rob_predicated_15 <= ~(io_wb_resps_3_valid & _GEN_367) & (_GEN_305 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_208) & (_GEN_146 ? io_wb_resps_0_bits_predicated : ~_GEN_50 & rob_predicated_15));
rob_predicated_16 <= ~(io_wb_resps_3_valid & _GEN_370) & (_GEN_306 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_211) & (_GEN_147 ? io_wb_resps_0_bits_predicated : ~_GEN_51 & rob_predicated_16));
rob_predicated_17 <= ~(io_wb_resps_3_valid & _GEN_373) & (_GEN_307 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_214) & (_GEN_148 ? io_wb_resps_0_bits_predicated : ~_GEN_52 & rob_predicated_17));
rob_predicated_18 <= ~(io_wb_resps_3_valid & _GEN_376) & (_GEN_308 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_217) & (_GEN_149 ? io_wb_resps_0_bits_predicated : ~_GEN_53 & rob_predicated_18));
rob_predicated_19 <= ~(io_wb_resps_3_valid & _GEN_379) & (_GEN_309 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_220) & (_GEN_150 ? io_wb_resps_0_bits_predicated : ~_GEN_54 & rob_predicated_19));
rob_predicated_20 <= ~(io_wb_resps_3_valid & _GEN_382) & (_GEN_310 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_223) & (_GEN_151 ? io_wb_resps_0_bits_predicated : ~_GEN_55 & rob_predicated_20));
rob_predicated_21 <= ~(io_wb_resps_3_valid & _GEN_385) & (_GEN_311 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_226) & (_GEN_152 ? io_wb_resps_0_bits_predicated : ~_GEN_56 & rob_predicated_21));
rob_predicated_22 <= ~(io_wb_resps_3_valid & _GEN_388) & (_GEN_312 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_229) & (_GEN_153 ? io_wb_resps_0_bits_predicated : ~_GEN_57 & rob_predicated_22));
rob_predicated_23 <= ~(io_wb_resps_3_valid & _GEN_391) & (_GEN_313 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_232) & (_GEN_154 ? io_wb_resps_0_bits_predicated : ~_GEN_58 & rob_predicated_23));
rob_predicated_24 <= ~(io_wb_resps_3_valid & _GEN_394) & (_GEN_314 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_235) & (_GEN_155 ? io_wb_resps_0_bits_predicated : ~_GEN_59 & rob_predicated_24));
rob_predicated_25 <= ~(io_wb_resps_3_valid & _GEN_397) & (_GEN_315 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_238) & (_GEN_156 ? io_wb_resps_0_bits_predicated : ~_GEN_60 & rob_predicated_25));
rob_predicated_26 <= ~(io_wb_resps_3_valid & _GEN_400) & (_GEN_316 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_241) & (_GEN_157 ? io_wb_resps_0_bits_predicated : ~_GEN_61 & rob_predicated_26));
rob_predicated_27 <= ~(io_wb_resps_3_valid & _GEN_403) & (_GEN_317 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_244) & (_GEN_158 ? io_wb_resps_0_bits_predicated : ~_GEN_62 & rob_predicated_27));
rob_predicated_28 <= ~(io_wb_resps_3_valid & _GEN_406) & (_GEN_318 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_247) & (_GEN_159 ? io_wb_resps_0_bits_predicated : ~_GEN_63 & rob_predicated_28));
rob_predicated_29 <= ~(io_wb_resps_3_valid & _GEN_409) & (_GEN_319 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_250) & (_GEN_160 ? io_wb_resps_0_bits_predicated : ~_GEN_64 & rob_predicated_29));
rob_predicated_30 <= ~(io_wb_resps_3_valid & _GEN_412) & (_GEN_320 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_253) & (_GEN_161 ? io_wb_resps_0_bits_predicated : ~_GEN_65 & rob_predicated_30));
rob_predicated_31 <= ~(io_wb_resps_3_valid & (&io_wb_resps_3_bits_uop_rob_idx)) & (_GEN_321 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & (&io_wb_resps_1_bits_uop_rob_idx)) & (_GEN_162 ? io_wb_resps_0_bits_predicated : ~_GEN_66 & rob_predicated_31));
block_commit_REG <= exception_thrown;
block_commit_REG_1 <= exception_thrown;
block_commit_REG_2 <= block_commit_REG_1;
REG <= exception_thrown;
REG_1 <= REG;
REG_2 <= exception_thrown;
io_com_load_is_at_rob_head_REG <= _GEN_16[rob_head] & ~will_commit_0;
end
rob_debug_inst_mem_0 rob_debug_inst_mem_0 (
.R0_addr (rob_head),
.R0_en (will_commit_0),
.R0_clk (clock),
.W0_addr (rob_tail),
.W0_en (io_enq_valids_0),
.W0_clk (clock),
.W0_data (io_enq_uops_0_debug_inst)
);
assign io_rob_tail_idx = rob_tail;
assign io_rob_head_idx = rob_head;
assign io_commit_valids_0 = will_commit_0;
assign io_commit_arch_valids_0 = will_commit_0 & ~_GEN_4[com_idx];
assign io_commit_uops_0_is_br = _GEN_7[com_idx];
assign io_commit_uops_0_is_jalr = _GEN_8[com_idx];
assign io_commit_uops_0_is_jal = _GEN_9[com_idx];
assign io_commit_uops_0_ftq_idx = _GEN_10[com_idx];
assign io_commit_uops_0_pdst = _GEN_13[com_idx];
assign io_commit_uops_0_stale_pdst = _GEN_14[com_idx];
assign io_commit_uops_0_is_fencei = _GEN_15[com_idx];
assign io_commit_uops_0_uses_ldq = _GEN_16[com_idx];
assign io_commit_uops_0_uses_stq = _GEN_17[com_idx];
assign io_commit_uops_0_ldst = _GEN_20[com_idx];
assign io_commit_uops_0_ldst_val = _GEN_21[com_idx];
assign io_commit_uops_0_dst_rtype = _GEN_22[com_idx];
assign io_commit_uops_0_debug_fsrc = io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == com_idx ? 2'h3 : _GEN_24[com_idx];
assign io_commit_fflags_valid = fflags_val_0;
assign io_commit_fflags_bits = fflags_val_0 ? rob_head_fflags_0 : 5'h0;
assign io_commit_rbk_valids_0 = io_commit_rbk_valids_0_0;
assign io_commit_rollback = io_commit_rollback_0;
assign io_com_load_is_at_rob_head = io_com_load_is_at_rob_head_REG;
assign io_com_xcpt_valid = exception_thrown & ~is_mini_exception;
assign io_com_xcpt_bits_ftq_idx = _GEN_10[com_idx];
assign io_com_xcpt_bits_edge_inst = _GEN_11[com_idx];
assign io_com_xcpt_bits_pc_lob = _GEN_12[com_idx];
assign io_com_xcpt_bits_cause = r_xcpt_uop_exc_cause;
assign io_com_xcpt_bits_badvaddr = {{24{r_xcpt_badvaddr[39]}}, r_xcpt_badvaddr};
assign io_flush_valid = flush_val;
assign io_flush_bits_ftq_idx = _GEN_10[com_idx];
assign io_flush_bits_edge_inst = _GEN_11[com_idx];
assign io_flush_bits_is_rvc = _GEN_6[com_idx];
assign io_flush_bits_pc_lob = _GEN_12[com_idx];
assign io_flush_bits_flush_typ = flush_val ? (flush_commit_mask_0 & _GEN_5[com_idx] == 7'h6A ? 3'h3 : exception_thrown & ~is_mini_exception ? 3'h1 : exception_thrown | rob_head_vals_0 & _GEN_18[com_idx] ? 3'h2 : 3'h4) : 3'h0;
assign io_empty = empty;
assign io_ready = _io_ready_T & ~full & ~r_xcpt_val;
assign io_flush_frontend = r_xcpt_val;
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(t))
val out = Decoupled(new Flit(flitWidth))
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))
data(0) := DontCare // unused, DCE this
}
}
io.busy := io.out.valid
}
class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(t)
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits := (if (dataBeats == 1) {
io.in.bits.flit.asTypeOf(t)
} else {
Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)
})
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit
}
}
}
io.busy := beat =/= 0.U
}
class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Phit(phitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail
}
}
}
object FlitToPhit {
def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {
val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))
flit2phit.io.in <> flit
flit2phit.io.out
}
}
class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Decoupled(new Flit(flitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat) := io.in.bits.phit
}
}
}
}
object PhitToFlit {
def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in <> phit
phit2flit.io.out
}
def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in.valid := phit.valid
phit2flit.io.in.bits := phit.bits
when (phit.valid) { assert(phit2flit.io.in.ready) }
val out = Wire(Valid(new Flit(flitWidth)))
out.valid := phit2flit.io.out.valid
out.bits := phit2flit.io.out.bits
phit2flit.io.out.ready := true.B
out
}
}
class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))
val out = Decoupled(new Phit(phitWidth))
})
if (channels == 1) {
io.out <> io.in(0)
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val chosen_reg = Reg(UInt(headerWidth.W))
val chosen_prio = PriorityEncoder(io.in.map(_.valid))
val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.out.valid := VecInit(io.in.map(_.valid))(chosen)
io.out.bits.phit := Mux(beat < headerBeats.U,
chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),
VecInit(io.in.map(_.bits.phit))(chosen))
for (i <- 0 until channels) {
io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U
}
when (io.out.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) { chosen_reg := chosen_prio }
}
}
}
class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Vec(channels, Decoupled(new Phit(phitWidth)))
})
if (channels == 1) {
io.out(0) <> io.in
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))
val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)
for (c <- 0 until channels) {
io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U
io.out(c).bits.phit := io.in.bits.phit
}
when (io.in.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat < headerBeats.U) {
channel_vec(header_idx) := io.in.bits.phit
}
}
}
}
class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Flipped(Decoupled(new Flit(flitWidth)))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = io.out.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)
}
io.out.valid := io.in.valid && credits < bufferSz.U
io.out.bits.flit := io.in.bits.flit
io.in.ready := io.out.ready && credits < bufferSz.U
io.credit.ready := true.B
}
class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Decoupled(new Flit(flitWidth))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = buffer.io.deq.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credit_incr + Mux(credit_decr, 0.U, credits)
}
buffer.io.enq.valid := io.in.valid
buffer.io.enq.bits := io.in.bits
io.in.ready := true.B
when (io.in.valid) { assert(buffer.io.enq.ready) }
io.out <> buffer.io.deq
io.credit.valid := credits =/= 0.U
io.credit.bits.flit := credits - 1.U
} | module PhitToFlit_p32_f32_TestHarness_UNIQUIFIED(
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits_phit,
input io_out_ready,
output io_out_valid,
output [31:0] io_out_bits_flit
);
assign io_in_ready = io_out_ready;
assign io_out_valid = io_in_valid;
assign io_out_bits_flit = io_in_bits_phit;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
} | module MulAddRecFNToRaw_postMul_e11_s53(
input io_fromPreMul_isSigNaNAny,
input io_fromPreMul_isNaNAOrB,
input io_fromPreMul_isInfA,
input io_fromPreMul_isZeroA,
input io_fromPreMul_isInfB,
input io_fromPreMul_isZeroB,
input io_fromPreMul_signProd,
input io_fromPreMul_isNaNC,
input io_fromPreMul_isInfC,
input io_fromPreMul_isZeroC,
input [12:0] io_fromPreMul_sExpSum,
input io_fromPreMul_doSubMags,
input io_fromPreMul_CIsDominant,
input [5:0] io_fromPreMul_CDom_CAlignDist,
input [54:0] io_fromPreMul_highAlignedSigC,
input io_fromPreMul_bit0AlignedSigC,
input [106:0] io_mulAddResult,
input [2:0] io_roundingMode,
output io_invalidExc,
output io_rawOut_isNaN,
output io_rawOut_isInf,
output io_rawOut_isZero,
output io_rawOut_sign,
output [12:0] io_rawOut_sExp,
output [55:0] io_rawOut_sig
);
wire roundingMode_min = io_roundingMode == 3'h2;
wire opSignC = io_fromPreMul_signProd ^ io_fromPreMul_doSubMags;
wire [54:0] _sigSum_T_3 = io_mulAddResult[106] ? io_fromPreMul_highAlignedSigC + 55'h1 : io_fromPreMul_highAlignedSigC;
wire [107:0] CDom_absSigSum = io_fromPreMul_doSubMags ? ~{_sigSum_T_3, io_mulAddResult[105:53]} : {1'h0, io_fromPreMul_highAlignedSigC[54:53], _sigSum_T_3[52:0], io_mulAddResult[105:54]};
wire [170:0] _CDom_mainSig_T = {63'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist;
wire [16:0] CDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> ~(io_fromPreMul_CDom_CAlignDist[5:2]));
wire [108:0] notCDom_absSigSum = _sigSum_T_3[2] ? ~{_sigSum_T_3[1:0], io_mulAddResult[105:0], io_fromPreMul_bit0AlignedSigC} : {_sigSum_T_3[1:0], io_mulAddResult[105:0], io_fromPreMul_bit0AlignedSigC} + {108'h0, io_fromPreMul_doSubMags};
wire [5:0] notCDom_normDistReduced2 =
notCDom_absSigSum[108]
? 6'h0
: (|(notCDom_absSigSum[107:106]))
? 6'h1
: (|(notCDom_absSigSum[105:104]))
? 6'h2
: (|(notCDom_absSigSum[103:102])) ? 6'h3 : (|(notCDom_absSigSum[101:100])) ? 6'h4 : (|(notCDom_absSigSum[99:98])) ? 6'h5 : (|(notCDom_absSigSum[97:96])) ? 6'h6 : (|(notCDom_absSigSum[95:94])) ? 6'h7 : (|(notCDom_absSigSum[93:92])) ? 6'h8 : (|(notCDom_absSigSum[91:90])) ? 6'h9 : (|(notCDom_absSigSum[89:88])) ? 6'hA : (|(notCDom_absSigSum[87:86])) ? 6'hB : (|(notCDom_absSigSum[85:84])) ? 6'hC : (|(notCDom_absSigSum[83:82])) ? 6'hD : (|(notCDom_absSigSum[81:80])) ? 6'hE : (|(notCDom_absSigSum[79:78])) ? 6'hF : (|(notCDom_absSigSum[77:76])) ? 6'h10 : (|(notCDom_absSigSum[75:74])) ? 6'h11 : (|(notCDom_absSigSum[73:72])) ? 6'h12 : (|(notCDom_absSigSum[71:70])) ? 6'h13 : (|(notCDom_absSigSum[69:68])) ? 6'h14 : (|(notCDom_absSigSum[67:66])) ? 6'h15 : (|(notCDom_absSigSum[65:64])) ? 6'h16 : (|(notCDom_absSigSum[63:62])) ? 6'h17 : (|(notCDom_absSigSum[61:60])) ? 6'h18 : (|(notCDom_absSigSum[59:58])) ? 6'h19 : (|(notCDom_absSigSum[57:56])) ? 6'h1A : (|(notCDom_absSigSum[55:54])) ? 6'h1B : (|(notCDom_absSigSum[53:52])) ? 6'h1C : (|(notCDom_absSigSum[51:50])) ? 6'h1D : (|(notCDom_absSigSum[49:48])) ? 6'h1E : (|(notCDom_absSigSum[47:46])) ? 6'h1F : (|(notCDom_absSigSum[45:44])) ? 6'h20 : (|(notCDom_absSigSum[43:42])) ? 6'h21 : (|(notCDom_absSigSum[41:40])) ? 6'h22 : (|(notCDom_absSigSum[39:38])) ? 6'h23 : (|(notCDom_absSigSum[37:36])) ? 6'h24 : (|(notCDom_absSigSum[35:34])) ? 6'h25 : (|(notCDom_absSigSum[33:32])) ? 6'h26 : (|(notCDom_absSigSum[31:30])) ? 6'h27 : (|(notCDom_absSigSum[29:28])) ? 6'h28 : (|(notCDom_absSigSum[27:26])) ? 6'h29 : (|(notCDom_absSigSum[25:24])) ? 6'h2A : (|(notCDom_absSigSum[23:22])) ? 6'h2B : (|(notCDom_absSigSum[21:20])) ? 6'h2C : (|(notCDom_absSigSum[19:18])) ? 6'h2D : (|(notCDom_absSigSum[17:16])) ? 6'h2E : (|(notCDom_absSigSum[15:14])) ? 6'h2F : (|(notCDom_absSigSum[13:12])) ? 6'h30 : (|(notCDom_absSigSum[11:10])) ? 6'h31 : (|(notCDom_absSigSum[9:8])) ? 6'h32 : (|(notCDom_absSigSum[7:6])) ? 6'h33 : (|(notCDom_absSigSum[5:4])) ? 6'h34 : (|(notCDom_absSigSum[3:2])) ? 6'h35 : 6'h36;
wire [235:0] _notCDom_mainSig_T = {127'h0, notCDom_absSigSum} << {229'h0, notCDom_normDistReduced2, 1'h0};
wire [32:0] notCDom_reduced4SigExtra_shift = $signed(33'sh100000000 >>> ~(notCDom_normDistReduced2[5:1]));
wire notCDom_completeCancellation = _notCDom_mainSig_T[109:108] == 2'h0;
wire notNaN_isInfProd = io_fromPreMul_isInfA | io_fromPreMul_isInfB;
wire notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC;
wire notNaN_addZeros = (io_fromPreMul_isZeroA | io_fromPreMul_isZeroB) & io_fromPreMul_isZeroC;
assign io_invalidExc = io_fromPreMul_isSigNaNAny | io_fromPreMul_isInfA & io_fromPreMul_isZeroB | io_fromPreMul_isZeroA & io_fromPreMul_isInfB | ~io_fromPreMul_isNaNAOrB & notNaN_isInfProd & io_fromPreMul_isInfC & io_fromPreMul_doSubMags;
assign io_rawOut_isNaN = io_fromPreMul_isNaNAOrB | io_fromPreMul_isNaNC;
assign io_rawOut_isInf = notNaN_isInfOut;
assign io_rawOut_isZero = notNaN_addZeros | ~io_fromPreMul_CIsDominant & notCDom_completeCancellation;
assign io_rawOut_sign = notNaN_isInfProd & io_fromPreMul_signProd | io_fromPreMul_isInfC & opSignC | notNaN_addZeros & io_roundingMode != 3'h2 & io_fromPreMul_signProd & opSignC | notNaN_addZeros & roundingMode_min & (io_fromPreMul_signProd | opSignC) | ~notNaN_isInfOut & ~notNaN_addZeros & (io_fromPreMul_CIsDominant ? opSignC : notCDom_completeCancellation ? roundingMode_min : io_fromPreMul_signProd ^ _sigSum_T_3[2]);
assign io_rawOut_sExp = io_fromPreMul_CIsDominant ? io_fromPreMul_sExpSum - {12'h0, io_fromPreMul_doSubMags} : io_fromPreMul_sExpSum - {6'h0, notCDom_normDistReduced2, 1'h0};
assign io_rawOut_sig =
io_fromPreMul_CIsDominant
? {_CDom_mainSig_T[107:53], (|{_CDom_mainSig_T[52:50], {|(CDom_absSigSum[49:46]), |(CDom_absSigSum[45:42]), |(CDom_absSigSum[41:38]), |(CDom_absSigSum[37:34]), |(CDom_absSigSum[33:30]), |(CDom_absSigSum[29:26]), |(CDom_absSigSum[25:22]), |(CDom_absSigSum[21:18]), |(CDom_absSigSum[17:14]), |(CDom_absSigSum[13:10]), |(CDom_absSigSum[9:6]), |(CDom_absSigSum[5:2]), |(CDom_absSigSum[1:0])} & {CDom_reduced4SigExtra_shift[1], CDom_reduced4SigExtra_shift[2], CDom_reduced4SigExtra_shift[3], CDom_reduced4SigExtra_shift[4], CDom_reduced4SigExtra_shift[5], CDom_reduced4SigExtra_shift[6], CDom_reduced4SigExtra_shift[7], CDom_reduced4SigExtra_shift[8], CDom_reduced4SigExtra_shift[9], CDom_reduced4SigExtra_shift[10], CDom_reduced4SigExtra_shift[11], CDom_reduced4SigExtra_shift[12], CDom_reduced4SigExtra_shift[13]}}) | (io_fromPreMul_doSubMags ? io_mulAddResult[52:0] != 53'h1FFFFFFFFFFFFF : (|(io_mulAddResult[53:0])))}
: {_notCDom_mainSig_T[109:55], |{_notCDom_mainSig_T[54:52], {|{|(notCDom_absSigSum[51:50]), |(notCDom_absSigSum[49:48])}, |{|(notCDom_absSigSum[47:46]), |(notCDom_absSigSum[45:44])}, |{|(notCDom_absSigSum[43:42]), |(notCDom_absSigSum[41:40])}, |{|(notCDom_absSigSum[39:38]), |(notCDom_absSigSum[37:36])}, |{|(notCDom_absSigSum[35:34]), |(notCDom_absSigSum[33:32])}, |{|(notCDom_absSigSum[31:30]), |(notCDom_absSigSum[29:28])}, |{|(notCDom_absSigSum[27:26]), |(notCDom_absSigSum[25:24])}, |{|(notCDom_absSigSum[23:22]), |(notCDom_absSigSum[21:20])}, |{|(notCDom_absSigSum[19:18]), |(notCDom_absSigSum[17:16])}, |{|(notCDom_absSigSum[15:14]), |(notCDom_absSigSum[13:12])}, |{|(notCDom_absSigSum[11:10]), |(notCDom_absSigSum[9:8])}, |{|(notCDom_absSigSum[7:6]), |(notCDom_absSigSum[5:4])}, |{|(notCDom_absSigSum[3:2]), |(notCDom_absSigSum[1:0])}} & {notCDom_reduced4SigExtra_shift[1], notCDom_reduced4SigExtra_shift[2], notCDom_reduced4SigExtra_shift[3], notCDom_reduced4SigExtra_shift[4], notCDom_reduced4SigExtra_shift[5], notCDom_reduced4SigExtra_shift[6], notCDom_reduced4SigExtra_shift[7], notCDom_reduced4SigExtra_shift[8], notCDom_reduced4SigExtra_shift[9], notCDom_reduced4SigExtra_shift[10], notCDom_reduced4SigExtra_shift[11], notCDom_reduced4SigExtra_shift[12], notCDom_reduced4SigExtra_shift[13]}}};
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
case class FPUParams(
minFLen: Int = 32,
fLen: Int = 64,
divSqrt: Boolean = true,
sfmaLatency: Int = 3,
dfmaLatency: Int = 4,
fpmuLatency: Int = 2,
ifpuLatency: Int = 2
)
object FPConstants
{
val RM_SZ = 3
val FLAGS_SZ = 5
}
trait HasFPUCtrlSigs {
val ldst = Bool()
val wen = Bool()
val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val swap12 = Bool()
val swap23 = Bool()
val typeTagIn = UInt(2.W)
val typeTagOut = UInt(2.W)
val fromint = Bool()
val toint = Bool()
val fastpipe = Bool()
val fma = Bool()
val div = Bool()
val sqrt = Bool()
val wflags = Bool()
val vec = Bool()
}
class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val inst = Input(Bits(32.W))
val sigs = Output(new FPUCtrlSigs())
})
private val X2 = BitPat.dontCare(2)
val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)
val h: Array[(BitPat, List[BitPat])] =
Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),
FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),
FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),
FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),
FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),
FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),
FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),
FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))
val f: Array[(BitPat, List[BitPat])] =
Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),
FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),
FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),
FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),
FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),
FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))
val d: Array[(BitPat, List[BitPat])] =
Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),
FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),
FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),
FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),
FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),
FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),
FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),
FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))
val fcvt_hd: Array[(BitPat, List[BitPat])] =
Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),
FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))
val vfmv_f_s: Array[(BitPat, List[BitPat])] =
Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))
val insns = ((minFLen, fLen) match {
case (32, 32) => f
case (16, 32) => h ++ f
case (32, 64) => f ++ d
case (16, 64) => h ++ f ++ d ++ fcvt_hd
case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration")
}) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())
val decoder = DecodeLogic(io.inst, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,
s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)
sigs zip decoder map {case(s,d) => s := d}
}
class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val time = Input(UInt(xLen.W))
val inst = Input(Bits(32.W))
val fromint_data = Input(Bits(xLen.W))
val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))
val v_sew = Input(UInt(3.W))
val store_data = Output(Bits(fLen.W))
val toint_data = Output(Bits(xLen.W))
val ll_resp_val = Input(Bool())
val ll_resp_type = Input(Bits(3.W))
val ll_resp_tag = Input(UInt(5.W))
val ll_resp_data = Input(Bits(fLen.W))
val valid = Input(Bool())
val fcsr_rdy = Output(Bool())
val nack_mem = Output(Bool())
val illegal_rm = Output(Bool())
val killx = Input(Bool())
val killm = Input(Bool())
val dec = Output(new FPUCtrlSigs())
val sboard_set = Output(Bool())
val sboard_clr = Output(Bool())
val sboard_clra = Output(UInt(5.W))
val keep_clock_enabled = Input(Bool())
}
class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs
val cp_resp = Decoupled(new FPResult())
}
class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
val data = Bits((fLen+1).W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val typ = Bits(2.W)
val in1 = Bits(xLen.W)
}
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val fmaCmd = Bits(2.W)
val typ = Bits(2.W)
val fmt = Bits(2.W)
val in1 = Bits((fLen+1).W)
val in2 = Bits((fLen+1).W)
val in3 = Bits((fLen+1).W)
}
case class FType(exp: Int, sig: Int) {
def ieeeWidth = exp + sig
def recodedWidth = ieeeWidth + 1
def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)
def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)
def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR
def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)
def classify(x: UInt) = {
val sign = x(sig + exp)
val code = x(exp + sig - 1, exp + sig - 3)
val codeHi = code(2, 1)
val isSpecial = codeHi === 3.U
val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U
val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn
val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U
val isZero = code === 0.U
val isInf = isSpecial && !code(0)
val isNaN = code.andR
val isSNaN = isNaN && !x(sig-2)
val isQNaN = isNaN && x(sig-2)
Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,
isSubnormal && !sign, isZero && !sign, isZero && sign,
isSubnormal && sign, isNormal && sign, isInf && sign)
}
// convert between formats, ignoring rounding, range, NaN
def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {
val sign = x(sig + exp)
val fractIn = x(sig - 2, 0)
val expIn = x(sig + exp - 1, sig - 1)
val fractOut = fractIn << to.sig >> sig
val expOut = {
val expCode = expIn(exp, exp - 2)
val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U
Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))
}
Cat(sign, expOut, fractOut)
}
private def ieeeBundle = {
val expWidth = exp
class IEEEBundle extends Bundle {
val sign = Bool()
val exp = UInt(expWidth.W)
val sig = UInt((ieeeWidth-expWidth-1).W)
}
new IEEEBundle
}
def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)
def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)
def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)
}
object FType {
val H = new FType(5, 11)
val S = new FType(8, 24)
val D = new FType(11, 53)
val all = List(H, S, D)
}
trait HasFPUParameters {
require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))
val minFLen: Int
val fLen: Int
def xLen: Int
val minXLen = 32
val nIntTypes = log2Ceil(xLen/minXLen) + 1
def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)
def minType = floatTypes.head
def maxType = floatTypes.last
def prevType(t: FType) = floatTypes(typeTag(t) - 1)
def maxExpWidth = maxType.exp
def maxSigWidth = maxType.sig
def typeTag(t: FType) = floatTypes.indexOf(t)
def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U
def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U
// typeTag
def H = typeTagGroup(FType.H)
def S = typeTagGroup(FType.S)
def D = typeTagGroup(FType.D)
def I = typeTag(maxType).U
private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR
private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {
require(xt.ieeeWidth == 2 * yt.ieeeWidth)
val swizzledNaN = Cat(
x(xt.sig + xt.exp, xt.sig + xt.exp - 3),
x(xt.sig - 2, yt.recodedWidth - 1).andR,
x(xt.sig + xt.exp - 5, xt.sig),
y(yt.recodedWidth - 2),
x(xt.sig - 2, yt.recodedWidth - 1),
y(yt.recodedWidth - 1),
y(yt.recodedWidth - 3, 0))
Mux(xt.isNaN(x), swizzledNaN, x)
}
// implement NaN unboxing for FU inputs
def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {
val outType = exactType.getOrElse(maxType)
def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {
val prev =
if (t == minType) {
Seq()
} else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prev = helper(unswizzled, prevT)
val isbox = isBox(x, t)
prev.map(p => (isbox && p._1, p._2))
}
prev :+ (true.B, t.unsafeConvert(x, outType))
}
val (oks, floats) = helper(x, maxType).unzip
if (exactType.isEmpty || floatTypes.size == 1) {
Mux(oks(tag), floats(tag), maxType.qNaN)
} else {
val t = exactType.get
floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)
}
}
// make sure that the redundant bits in the NaN-boxed encoding are consistent
def consistent(x: UInt): Bool = {
def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prevOK = !isBox(x, t) || helper(unswizzled, prevT)
val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR
prevOK && curOK
}
helper(x, maxType)
}
// generate a NaN box from an FU result
def box(x: UInt, t: FType): UInt = {
if (t == maxType) {
x
} else {
val nt = floatTypes(typeTag(t) + 1)
val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)
bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U
}
}
// generate a NaN box from an FU result
def box(x: UInt, tag: UInt): UInt = {
val opts = floatTypes.map(t => box(x, t))
opts(tag)
}
// zap bits that hardfloat thinks are don't-cares, but we do care about
def sanitizeNaN(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
x
} else {
val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)
Mux(t.isNaN(x), maskedNaN, x)
}
}
// implement NaN boxing and recoding for FL*/fmv.*.x
def recode(x: UInt, tag: UInt): UInt = {
def helper(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
t.recode(x)
} else {
val prevT = prevType(t)
box(t.recode(x), t, helper(x, prevT), prevT)
}
}
// fill MSBs of subword loads to emulate a wider load of a NaN-boxed value
val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)
helper(boxes(tag) | x, maxType)
}
// implement NaN unboxing and un-recoding for FS*/fmv.x.*
def ieee(x: UInt, t: FType = maxType): UInt = {
if (typeTag(t) == 0) {
t.ieee(x)
} else {
val unrecoded = t.ieee(x)
val prevT = prevType(t)
val prevRecoded = Cat(
x(prevT.recodedWidth-2),
x(t.sig-1),
x(prevT.recodedWidth-3, 0))
val prevUnrecoded = ieee(prevRecoded, prevT)
Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))
}
}
}
abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
class Output extends Bundle {
val in = new FPInput
val lt = Bool()
val store = Bits(fLen.W)
val toint = Bits(xLen.W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new Output)
})
val in = RegEnable(io.in.bits, io.in.valid)
val valid = RegNext(io.in.valid)
val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
dcmp.io.a := in.in1
dcmp.io.b := in.in2
dcmp.io.signaling := !in.rm(1)
val tag = in.typeTagOut
val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))
else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
val toint = WireDefault(toint_ieee)
val intType = WireDefault(in.fmt(0))
io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
io.out.bits.exc := 0.U
when (in.rm(0)) {
val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)
toint := classify_out | (toint_ieee >> minXLen << minXLen)
intType := false.B
}
when (in.wflags) { // feq/flt/fle, fcvt
toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)
io.out.bits.exc := dcmp.io.exceptionFlags
intType := false.B
when (!in.ren2) { // fcvt
val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
intType := cvtType
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
conv.io.in := in.in1
conv.io.roundingMode := in.rm
conv.io.signedOut := ~in.typ(0)
toint := conv.io.out
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))
for (i <- 0 until nIntTypes-1) {
val w = minXLen << i
when (cvtType === i.U) {
val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))
narrow.io.in := in.in1
narrow.io.roundingMode := in.rm
narrow.io.signedOut := ~in.typ(0)
val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)
val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))
val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)
when (invalid) { toint := Cat(conv.io.out >> w, excOut) }
io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))
}
}
}
}
io.out.valid := valid
io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)
io.out.bits.in := in
}
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new IntToFPInput))
val out = Valid(new FPResult)
})
val in = Pipe(io.in)
val tag = in.bits.typeTagIn
val mux = Wire(new FPResult)
mux.exc := 0.U
mux.data := recode(in.bits.in1, tag)
val intValue = {
val res = WireDefault(in.bits.in1.asSInt)
for (i <- 0 until nIntTypes-1) {
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
}
}
res.asUInt
}
when (in.bits.wflags) { // fcvt
// could be improved for RVD/RVQ with a single variable-position rounding
// unit, rather than N fixed-position ones
val i2fResults = for (t <- floatTypes) yield {
val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
i2f.io.signedIn := ~in.bits.typ(0)
i2f.io.in := intValue
i2f.io.roundingMode := in.bits.rm
i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding
(sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)
}
val (data, exc) = i2fResults.unzip
val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
mux.data := dataPadded(tag)
mux.exc := exc(tag)
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
val lt = Input(Bool()) // from FPToInt
})
val in = Pipe(io.in)
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
val fsgnjMux = Wire(new FPResult)
fsgnjMux.exc := 0.U
fsgnjMux.data := fsgnj
when (in.bits.wflags) { // fmin/fmax
val isnan1 = maxType.isNaN(in.bits.in1)
val isnan2 = maxType.isNaN(in.bits.in2)
val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)
val isNaNOut = isnan1 && isnan2
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
fsgnjMux.exc := isInvalid << 4
fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
}
val inTag = in.bits.typeTagIn
val outTag = in.bits.typeTagOut
val mux = WireDefault(fsgnjMux)
for (t <- floatTypes.init) {
when (outTag === typeTag(t).U) {
mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))
}
}
when (in.bits.wflags && !in.bits.ren2) { // fcvt
if (floatTypes.size > 1) {
// widening conversions simply canonicalize NaN operands
val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)
fsgnjMux.data := widened
fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4
// narrowing conversions require rounding (for RVQ, this could be
// optimized to use a single variable-position rounding unit, rather
// than two fixed-position ones)
for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {
val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
narrower.io.in := in.bits.in1
narrower.io.roundingMode := in.bits.rm
narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding
val narrowed = sanitizeNaN(narrower.io.out, outType)
mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)
mux.exc := narrower.io.exceptionFlags
}
}
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
{
override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}"
require(latency<=2)
val io = IO(new Bundle {
val validin = Input(Bool())
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
val validout = Output(Bool())
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
val valid_stage0 = Wire(Bool())
val roundingMode_stage0 = Wire(UInt(3.W))
val detectTininess_stage0 = Wire(UInt(1.W))
val postmul_regs = if(latency>0) 1 else 0
mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits
detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits
valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
val round_regs = if(latency==2) 1 else 0
roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
io.validout := Pipe(valid_stage0, false.B, round_regs).valid
roundRawFNToRecFN.io.infiniteExc := false.B
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
class FPUFMAPipe(val latency: Int, val t: FType)
(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
require(latency>0)
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
})
val valid = RegNext(io.in.valid)
val in = Reg(new FPInput)
when (io.in.valid) {
val one = 1.U << (t.sig + t.exp - 1)
val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))
val cmd_fma = io.in.bits.ren3
val cmd_addsub = io.in.bits.swap23
in := io.in.bits
when (cmd_addsub) { in.in2 := one }
when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
}
val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
fma.io.validin := valid
fma.io.op := in.fmaCmd
fma.io.roundingMode := in.rm
fma.io.detectTininess := hardfloat.consts.tininess_afterRounding
fma.io.a := in.in1
fma.io.b := in.in2
fma.io.c := in.in3
val res = Wire(new FPResult)
res.data := sanitizeNaN(fma.io.out, t)
res.exc := fma.io.exceptionFlags
io.out := Pipe(fma.io.validout, res, (latency-3) max 0)
}
class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new FPUIO)
val (useClockGating, useDebugROB) = coreParams match {
case r: RocketCoreParams =>
val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1
(r.clockGate, sz < 1)
case _ => (false, false)
}
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cp_req.valid
val gated_clock =
if (!useClockGating) clock
else ClockGate(clock, clock_en, "fpu_clock_gate")
val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.inst
val id_ctrl = WireInit(fp_decoder.io.sigs)
coreParams match { case r: RocketCoreParams => r.vector.map(v => {
val v_decode = v.decoder(p) // Only need to get ren1
v_decode.io.inst := io.inst
v_decode.io.vconfig := DontCare // core deals with this
when (v_decode.io.legal && v_decode.io.read_frs1) {
id_ctrl.ren1 := true.B
id_ctrl.swap12 := false.B
id_ctrl.toint := true.B
id_ctrl.typeTagIn := I
id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)
}
when (v_decode.io.write_frd) { id_ctrl.wen := true.B }
})}
val ex_reg_valid = RegNext(io.valid, false.B)
val ex_reg_inst = RegEnable(io.inst, io.valid)
val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
val ex_ra = List.fill(3)(Reg(UInt()))
// load/vector response
val load_wb = RegNext(io.ll_resp_val)
val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)
val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)
val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)
class FPUImpl { // entering gated-clock domain
val req_valid = ex_reg_valid || io.cp_req.valid
val ex_cp_valid = io.cp_req.fire
val mem_cp_valid = RegNext(ex_cp_valid, false.B)
val wb_cp_valid = RegNext(mem_cp_valid, false.B)
val mem_reg_valid = RegInit(false.B)
val killm = (io.killm || io.nack_mem) && !mem_cp_valid
// Kill X-stage instruction if M-stage is killed. This prevents it from
// speculatively being sent to the div-sqrt unit, which can cause priority
// inversion for two back-to-back divides, the first of which is killed.
val killx = io.killx || mem_reg_valid && killm
mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid
val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
val cp_ctrl = Wire(new FPUCtrlSigs)
cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
io.cp_resp.valid := false.B
io.cp_resp.bits.data := 0.U
io.cp_resp.bits.exc := DontCare
val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)
val mem_ctrl = RegEnable(ex_ctrl, req_valid)
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
// CoreMonitorBundle to monitor fp register file writes
val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))
frfWriteBundle.foreach { i =>
i.clock := clock
i.reset := reset
i.hartid := io.hartid
i.timer := io.time(31,0)
i.valid := false.B
i.wrenx := false.B
i.wrenf := false.B
i.excpt := false.B
}
// regfile
val regfile = Mem(32, Bits((fLen+1).W))
when (load_wb) {
val wdata = recode(load_wb_data, load_wb_typeTag)
regfile(load_wb_tag) := wdata
assert(consistent(wdata))
if (enableCommitLog)
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))
if (useDebugROB)
DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))
frfWriteBundle(0).wrdst := load_wb_tag
frfWriteBundle(0).wrenf := true.B
frfWriteBundle(0).wrdata := ieee(wdata)
}
val ex_rs = ex_ra.map(a => regfile(a))
when (io.valid) {
when (id_ctrl.ren1) {
when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }
when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }
}
when (id_ctrl.ren2) {
when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }
when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }
when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }
}
when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }
}
val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))
def fuInput(minT: Option[FType]): FPInput = {
val req = Wire(new FPInput)
val tag = ex_ctrl.typeTagIn
req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
req.rm := ex_rm
req.in1 := unbox(ex_rs(0), tag, minT)
req.in2 := unbox(ex_rs(1), tag, minT)
req.in3 := unbox(ex_rs(2), tag, minT)
req.typ := ex_reg_inst(21,20)
req.fmt := ex_reg_inst(26,25)
req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))
when (ex_cp_valid) {
req := io.cp_req.bits
when (io.cp_req.bits.swap12) {
req.in1 := io.cp_req.bits.in2
req.in2 := io.cp_req.bits.in1
}
when (io.cp_req.bits.swap23) {
req.in2 := io.cp_req.bits.in3
req.in3 := io.cp_req.bits.in2
}
}
req
}
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new FPToInt)
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
io.store_data := fpiu.io.out.bits.store
io.toint_data := fpiu.io.out.bits.toint
when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){
io.cp_resp.bits.data := fpiu.io.out.bits.toint
io.cp_resp.valid := true.B
}
val ifpu = Module(new IntToFP(cfg.ifpuLatency))
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
ifpu.io.in.bits := fpiu.io.in.bits
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
val fpmu = Module(new FPToFP(cfg.fpmuLatency))
fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val divSqrt_wen = WireDefault(false.B)
val divSqrt_inFlight = WireDefault(false.B)
val divSqrt_waddr = Reg(UInt(5.W))
val divSqrt_cp = Reg(Bool())
val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
val divSqrt_wdata = Wire(UInt((fLen+1).W))
val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
divSqrt_typeTag := DontCare
divSqrt_wdata := DontCare
divSqrt_flags := DontCare
// writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++
(fLen > 32).option({
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D
dfma.io.in.bits := fuInput(Some(dfma.t))
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)
}) ++
(minFLen == 16).option({
val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))
hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H
hfma.io.in.bits := fuInput(Some(hfma.t))
Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)
})
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
require(pipes.forall(_.lat >= offset))
pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)
}
def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)
val maxLatency = pipes.map(_.lat).max
val memLatencyMask = latencyMask(mem_ctrl, 2)
class WBInfo extends Bundle {
val rd = UInt(5.W)
val typeTag = UInt(log2Up(floatTypes.size).W)
val cp = Bool()
val pipeid = UInt(log2Ceil(pipes.size).W)
}
val wen = RegInit(0.U((maxLatency-1).W))
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback")
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
}
wen := wen >> 1
when (mem_wen) {
when (!killm) {
wen := wen >> 1 | memLatencyMask
}
for (i <- 0 until maxLatency-1) {
when (!write_port_busy && memLatencyMask(i)) {
wbInfo(i).cp := mem_cp_valid
wbInfo(i).typeTag := mem_ctrl.typeTagOut
wbInfo(i).pipeid := pipeid(mem_ctrl)
wbInfo(i).rd := mem_reg_inst(11,7)
}
}
}
val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)
val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
assert(consistent(wdata))
regfile(waddr) := wdata
if (enableCommitLog) {
printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata))
}
frfWriteBundle(1).wrdst := waddr
frfWriteBundle(1).wrenf := true.B
frfWriteBundle(1).wrdata := ieee(wdata)
}
if (useDebugROB) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
}
when (wb_cp && (wen(0) || divSqrt_wen)) {
io.cp_resp.bits.data := wdata
io.cp_resp.valid := true.B
}
assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,
s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}")
// Avoid structural hazards and nacking of external requests
// toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs
io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)
io.fcsr_flags.bits :=
Mux(wb_toint_valid, wb_toint_exc, 0.U) |
Mux(divSqrt_wen, divSqrt_flags, 0.U) |
Mux(wen(0), wexc, 0.U)
val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid
io.dec <> id_ctrl
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)
io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))
io.sboard_clra := waddr
ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
// we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U
if (cfg.divSqrt) {
val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)
when (divSqrt_inValid) {
divSqrt_waddr := mem_reg_inst(11,7)
divSqrt_cp := mem_cp_valid
}
ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")
ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard")
ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback")
for (t <- floatTypes) {
val tag = mem_ctrl.typeTagOut
val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }
divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)
divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm
divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding
when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight
when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {
divSqrt_wen := !divSqrt_killed
divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)
divSqrt_flags := divSqrt.io.exceptionFlags
divSqrt_typeTag := typeTag(t).U
}
}
when (divSqrt_killed) { divSqrt_inFlight := false.B }
} else {
when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }
}
// gate the clock
clock_en_reg := !useClockGating.B ||
io.keep_clock_enabled || // chicken bit
io.valid || // ID stage
req_valid || // EX stage
mem_reg_valid || mem_cp_valid || // MEM stage
wb_reg_valid || wb_cp_valid || // WB stage
wen.orR || divSqrt_inFlight || // post-WB stage
io.ll_resp_val // load writeback
} // leaving gated-clock domain
val fpuImpl = withClock (gated_clock) { new FPUImpl }
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FPU_$label", "Core;;" + desc)
} | module MulAddRecFNPipe_l2_e11_s53(
input clock,
input reset,
input io_validin,
input [1:0] io_op,
input [64:0] io_a,
input [64:0] io_b,
input [64:0] io_c,
input [2:0] io_roundingMode,
output [64:0] io_out,
output [4:0] io_exceptionFlags,
output io_validout
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc;
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN;
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf;
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero;
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign;
wire [12:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp;
wire [55:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig;
wire [52:0] _mulAddRecFNToRaw_preMul_io_mulAddA;
wire [52:0] _mulAddRecFNToRaw_preMul_io_mulAddB;
wire [105:0] _mulAddRecFNToRaw_preMul_io_mulAddC;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC;
wire [12:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant;
wire [5:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist;
wire [54:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC;
reg [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant;
reg [5:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist;
reg [54:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC;
reg [106:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b;
reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b;
reg [2:0] roundingMode_stage0_pipe_b;
reg valid_stage0_pipe_v;
reg roundRawFNToRecFN_io_invalidExc_pipe_b;
reg roundRawFNToRecFN_io_in_pipe_b_isNaN;
reg roundRawFNToRecFN_io_in_pipe_b_isInf;
reg roundRawFNToRecFN_io_in_pipe_b_isZero;
reg roundRawFNToRecFN_io_in_pipe_b_sign;
reg [12:0] roundRawFNToRecFN_io_in_pipe_b_sExp;
reg [55:0] roundRawFNToRecFN_io_in_pipe_b_sig;
reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b;
reg io_validout_pipe_v;
always @(posedge clock) begin
if (io_validin) begin
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC;
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= {1'h0, {53'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {53'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC};
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode;
roundingMode_stage0_pipe_b <= io_roundingMode;
end
if (valid_stage0_pipe_v) begin
roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc;
roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN;
roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf;
roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero;
roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign;
roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp;
roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig;
roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0_pipe_b;
end
if (reset) begin
valid_stage0_pipe_v <= 1'h0;
io_validout_pipe_v <= 1'h0;
end
else begin
valid_stage0_pipe_v <= io_validin;
io_validout_pipe_v <= valid_stage0_pipe_v;
end
end
MulAddRecFNToRaw_preMul_e11_s53 mulAddRecFNToRaw_preMul (
.io_op (io_op),
.io_a (io_a),
.io_b (io_b),
.io_c (io_c),
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
);
MulAddRecFNToRaw_postMul_e11_s53 mulAddRecFNToRaw_postMul (
.io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny),
.io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB),
.io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA),
.io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA),
.io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB),
.io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB),
.io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd),
.io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC),
.io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC),
.io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC),
.io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum),
.io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags),
.io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant),
.io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist),
.io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC),
.io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC),
.io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b),
.io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b),
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
);
RoundRawFNToRecFN_e11_s53 roundRawFNToRecFN (
.io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_b),
.io_in_isNaN (roundRawFNToRecFN_io_in_pipe_b_isNaN),
.io_in_isInf (roundRawFNToRecFN_io_in_pipe_b_isInf),
.io_in_isZero (roundRawFNToRecFN_io_in_pipe_b_isZero),
.io_in_sign (roundRawFNToRecFN_io_in_pipe_b_sign),
.io_in_sExp (roundRawFNToRecFN_io_in_pipe_b_sExp),
.io_in_sig (roundRawFNToRecFN_io_in_pipe_b_sig),
.io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_b),
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
);
assign io_validout = io_validout_pipe_v;
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
} | module lo_us_3(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input [6:0] W0_addr,
input W0_clk,
input [3:0] W0_data,
input [3:0] W0_mask
);
hi_us_ext hi_us_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (1'h1),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)
{
val queueBits = log2Up(queues)
val entryBits = log2Up(entries)
}
class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle
{
val index = UInt(params.queueBits.W)
val data = Output(params.gen)
}
class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module
{
override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}"
val io = IO(new Bundle {
// push is visible on the same cycle; flow queues
val push = Flipped(Decoupled(new ListBufferPush(params)))
val valid = UInt(params.queues.W)
val pop = Flipped(Valid(UInt(params.queueBits.W)))
val data = Output(params.gen)
})
val valid = RegInit(0.U(params.queues.W))
val head = Mem(params.queues, UInt(params.entryBits.W))
val tail = Mem(params.queues, UInt(params.entryBits.W))
val used = RegInit(0.U(params.entries.W))
val next = Mem(params.entries, UInt(params.entryBits.W))
val data = Mem(params.entries, params.gen)
val freeOH = ~(leftOR(~used) << 1) & ~used
val freeIdx = OHToUInt(freeOH)
val valid_set = WireDefault(0.U(params.queues.W))
val valid_clr = WireDefault(0.U(params.queues.W))
val used_set = WireDefault(0.U(params.entries.W))
val used_clr = WireDefault(0.U(params.entries.W))
val push_tail = tail.read(io.push.bits.index)
val push_valid = valid(io.push.bits.index)
io.push.ready := !used.andR
when (io.push.fire) {
valid_set := UIntToOH(io.push.bits.index, params.queues)
used_set := freeOH
data.write(freeIdx, io.push.bits.data)
when (push_valid) {
next.write(push_tail, freeIdx)
} .otherwise {
head.write(io.push.bits.index, freeIdx)
}
tail.write(io.push.bits.index, freeIdx)
}
val pop_head = head.read(io.pop.bits)
val pop_valid = valid(io.pop.bits)
// Bypass push data to the peek port
io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))
io.valid := (if (!params.bypass) valid else (valid | valid_set))
// It is an error to pop something that is not valid
assert (!io.pop.fire || (io.valid)(io.pop.bits))
when (io.pop.fire) {
used_clr := UIntToOH(pop_head, params.entries)
when (pop_head === tail.read(io.pop.bits)) {
valid_clr := UIntToOH(io.pop.bits, params.queues)
}
head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))
}
// Empty bypass changes no state
when ((!params.bypass).B || !io.pop.valid || pop_valid) {
used := (used & ~used_clr) | used_set
valid := (valid & ~valid_clr) | valid_set
}
} | module next_33x6(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [5:0] R0_data,
input [5:0] W0_addr,
input W0_en,
input W0_clk,
input [5:0] W0_data
);
reg [5:0] Memory[0:32];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 6'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
trait TLFieldHelper {
def getBodyFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleC => Seq( b.data, b.corrupt)
case b: TLBundleD => Seq( b.data, b.corrupt)
case b: TLBundleE => Seq()
}
def getConstFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )
case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)
case b: TLBundleE => Seq( b.sink )
}
def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max
def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max
def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))
}
class TLBeat(val beatWidth: Int) extends Bundle {
val payload = UInt(beatWidth.W)
val head = Bool()
val tail = Bool()
}
abstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Flipped(Decoupled(gen))
val beat = Decoupled(new TLBeat(beatWidth))
})
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
// convert decoupled to irrevocable
val q = Module(new Queue(gen, 1, pipe=true, flow=true))
q.io.enq <> io.protocol
val protocol = q.io.deq
val has_body = Wire(Bool())
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val head = edge.first(protocol.bits, protocol.fire)
val tail = edge.last(protocol.bits, protocol.fire)
val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))
val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))
val is_body = RegInit(false.B)
io.beat.valid := protocol.valid
protocol.ready := io.beat.ready && (is_body || !has_body)
io.beat.bits.head := head && !is_body
io.beat.bits.tail := tail && (is_body || !has_body)
io.beat.bits.payload := Mux(is_body, body, const)
when (io.beat.fire && io.beat.bits.head) { is_body := true.B }
when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }
}
abstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Decoupled(gen)
val beat = Flipped(Decoupled(new TLBeat(beatWidth)))
})
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
val protocol = Wire(Decoupled(gen))
io.protocol <> protocol
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val is_const = RegInit(true.B)
val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))
val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)
io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready
protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid
def assign(i: UInt, sigs: Seq[Data]) = {
var t = i
for (s <- sigs.reverse) {
s := t.asTypeOf(s.cloneType)
t = t >> s.getWidth
}
}
assign(const, const_fields)
assign(io.beat.bits.payload, body_fields)
when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }
when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }
}
class TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)
class TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits)
}
class TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)
class TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p) | module TLCToBeat_SerialRAM_a64d64s8k8z8c(
input clock,
input reset,
output io_beat_bits_head
);
assign io_beat_bits_head = 1'h1;
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(t))
val out = Decoupled(new Flit(flitWidth))
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))
data(0) := DontCare // unused, DCE this
}
}
io.busy := io.out.valid
}
class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(t)
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits := (if (dataBeats == 1) {
io.in.bits.flit.asTypeOf(t)
} else {
Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)
})
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit
}
}
}
io.busy := beat =/= 0.U
}
class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Phit(phitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail
}
}
}
object FlitToPhit {
def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {
val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))
flit2phit.io.in <> flit
flit2phit.io.out
}
}
class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Decoupled(new Flit(flitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat) := io.in.bits.phit
}
}
}
}
object PhitToFlit {
def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in <> phit
phit2flit.io.out
}
def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in.valid := phit.valid
phit2flit.io.in.bits := phit.bits
when (phit.valid) { assert(phit2flit.io.in.ready) }
val out = Wire(Valid(new Flit(flitWidth)))
out.valid := phit2flit.io.out.valid
out.bits := phit2flit.io.out.bits
phit2flit.io.out.ready := true.B
out
}
}
class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))
val out = Decoupled(new Phit(phitWidth))
})
if (channels == 1) {
io.out <> io.in(0)
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val chosen_reg = Reg(UInt(headerWidth.W))
val chosen_prio = PriorityEncoder(io.in.map(_.valid))
val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.out.valid := VecInit(io.in.map(_.valid))(chosen)
io.out.bits.phit := Mux(beat < headerBeats.U,
chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),
VecInit(io.in.map(_.bits.phit))(chosen))
for (i <- 0 until channels) {
io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U
}
when (io.out.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) { chosen_reg := chosen_prio }
}
}
}
class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Vec(channels, Decoupled(new Phit(phitWidth)))
})
if (channels == 1) {
io.out(0) <> io.in
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))
val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)
for (c <- 0 until channels) {
io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U
io.out(c).bits.phit := io.in.bits.phit
}
when (io.in.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat < headerBeats.U) {
channel_vec(header_idx) := io.in.bits.phit
}
}
}
}
class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Flipped(Decoupled(new Flit(flitWidth)))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = io.out.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)
}
io.out.valid := io.in.valid && credits < bufferSz.U
io.out.bits.flit := io.in.bits.flit
io.in.ready := io.out.ready && credits < bufferSz.U
io.credit.ready := true.B
}
class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Decoupled(new Flit(flitWidth))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = buffer.io.deq.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credit_incr + Mux(credit_decr, 0.U, credits)
}
buffer.io.enq.valid := io.in.valid
buffer.io.enq.bits := io.in.bits
io.in.ready := true.B
when (io.in.valid) { assert(buffer.io.enq.ready) }
io.out <> buffer.io.deq
io.credit.valid := credits =/= 0.U
io.credit.bits.flit := credits - 1.U
} | module GenericSerializer_TLBeatw88_f32(
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [85:0] io_in_bits_payload,
input io_in_bits_head,
input io_in_bits_tail,
input io_out_ready,
output io_out_valid,
output [31:0] io_out_bits_flit
);
wire [0:0][31:0] _GEN = '{32'h0};
reg [31:0] data_1;
reg [31:0] data_2;
reg [1:0] beat;
wire _io_out_bits_flit_T = beat == 2'h0;
wire [2:0] _GEN_0 = {io_in_valid, beat};
wire [3:0][31:0] _GEN_1 = {_GEN, {{data_2}, {data_1}, {32'h0}}};
wire _GEN_2 = io_out_ready & (|_GEN_0);
always @(posedge clock) begin
if (_GEN_2 & _io_out_bits_flit_T) begin
data_1 <= io_in_bits_payload[61:30];
data_2 <= {8'h0, io_in_bits_payload[85:62]};
end
if (reset)
beat <= 2'h0;
else if (_GEN_2)
beat <= beat == 2'h2 ? 2'h0 : beat + 2'h1;
end
assign io_in_ready = io_out_ready & _io_out_bits_flit_T;
assign io_out_valid = |_GEN_0;
assign io_out_bits_flit = _io_out_bits_flit_T ? {io_in_bits_payload[29:0], io_in_bits_head, io_in_bits_tail} : _GEN_1[beat];
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Register File (Abstract class and Synthesizable RegFile)
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.exu
import scala.collection.mutable.ArrayBuffer
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix}
/**
* IO bundle for a register read port
*
* @param addrWidth size of register address in bits
* @param dataWidth size of register in bits
*/
class RegisterFileReadPortIO(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
{
val addr = Input(UInt(addrWidth.W))
val data = Output(UInt(dataWidth.W))
}
/**
* IO bundle for the register write port
*
* @param addrWidth size of register address in bits
* @param dataWidth size of register in bits
*/
class RegisterFileWritePort(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
{
val addr = UInt(addrWidth.W)
val data = UInt(dataWidth.W)
}
/**
* Utility function to turn ExeUnitResps to match the regfile's WritePort I/Os.
*/
object WritePort
{
def apply(enq: DecoupledIO[ExeUnitResp], addrWidth: Int, dataWidth: Int, rtype: UInt)
(implicit p: Parameters): Valid[RegisterFileWritePort] = {
val wport = Wire(Valid(new RegisterFileWritePort(addrWidth, dataWidth)))
wport.valid := enq.valid && enq.bits.uop.dst_rtype === rtype
wport.bits.addr := enq.bits.uop.pdst
wport.bits.data := enq.bits.data
enq.ready := true.B
wport
}
}
/**
* Register file abstract class
*
* @param numRegisters number of registers
* @param numReadPorts number of read ports
* @param numWritePorts number of write ports
* @param registerWidth size of registers in bits
* @param bypassableArray list of write ports from func units to the read port of the regfile
*/
abstract class RegisterFile(
numRegisters: Int,
numReadPorts: Int,
numWritePorts: Int,
registerWidth: Int,
bypassableArray: Seq[Boolean]) // which write ports can be bypassed to the read ports?
(implicit p: Parameters) extends BoomModule
{
val io = IO(new BoomBundle {
val read_ports = Vec(numReadPorts, new RegisterFileReadPortIO(maxPregSz, registerWidth))
val write_ports = Flipped(Vec(numWritePorts, Valid(new RegisterFileWritePort(maxPregSz, registerWidth))))
})
private val rf_cost = (numReadPorts + numWritePorts) * (numReadPorts + 2*numWritePorts)
private val type_str = if (registerWidth == fLen+1) "Floating Point" else "Integer"
override def toString: String = BoomCoreStringPrefix(
"==" + type_str + " Regfile==",
"Num RF Read Ports : " + numReadPorts,
"Num RF Write Ports : " + numWritePorts,
"RF Cost (R+W)*(R+2W) : " + rf_cost,
"Bypassable Units : " + bypassableArray)
}
/**
* A synthesizable model of a Register File. You will likely want to blackbox this for more than modest port counts.
*
* @param numRegisters number of registers
* @param numReadPorts number of read ports
* @param numWritePorts number of write ports
* @param registerWidth size of registers in bits
* @param bypassableArray list of write ports from func units to the read port of the regfile
*/
class RegisterFileSynthesizable(
numRegisters: Int,
numReadPorts: Int,
numWritePorts: Int,
registerWidth: Int,
bypassableArray: Seq[Boolean])
(implicit p: Parameters)
extends RegisterFile(numRegisters, numReadPorts, numWritePorts, registerWidth, bypassableArray)
{
// --------------------------------------------------------------
val regfile = Mem(numRegisters, UInt(registerWidth.W))
// --------------------------------------------------------------
// Read ports.
val read_data = Wire(Vec(numReadPorts, UInt(registerWidth.W)))
// Register the read port addresses to give a full cycle to the RegisterRead Stage (if desired).
val read_addrs = io.read_ports.map(p => RegNext(p.addr))
for (i <- 0 until numReadPorts) {
read_data(i) := regfile(read_addrs(i))
}
// --------------------------------------------------------------
// Bypass out of the ALU's write ports.
// We are assuming we cannot bypass a writer to a reader within the regfile memory
// for a write that occurs at the end of cycle S1 and a read that returns data on cycle S1.
// But since these bypasses are expensive, and not all write ports need to bypass their data,
// only perform the w->r bypass on a select number of write ports.
require (bypassableArray.length == io.write_ports.length)
if (bypassableArray.reduce(_||_)) {
val bypassable_wports = ArrayBuffer[Valid[RegisterFileWritePort]]()
io.write_ports zip bypassableArray map { case (wport, b) => if (b) { bypassable_wports += wport} }
for (i <- 0 until numReadPorts) {
val bypass_ens = bypassable_wports.map(x => x.valid &&
x.bits.addr === read_addrs(i))
val bypass_data = Mux1H(VecInit(bypass_ens.toSeq), VecInit(bypassable_wports.map(_.bits.data).toSeq))
io.read_ports(i).data := Mux(bypass_ens.reduce(_|_), bypass_data, read_data(i))
}
} else {
for (i <- 0 until numReadPorts) {
io.read_ports(i).data := read_data(i)
}
}
// --------------------------------------------------------------
// Write ports.
for (wport <- io.write_ports) {
when (wport.valid) {
regfile(wport.bits.addr) := wport.bits.data
}
}
// ensure there is only 1 writer per register (unless to preg0)
if (numWritePorts > 1) {
for (i <- 0 until (numWritePorts - 1)) {
for (j <- (i + 1) until numWritePorts) {
assert(!io.write_ports(i).valid ||
!io.write_ports(j).valid ||
(io.write_ports(i).bits.addr =/= io.write_ports(j).bits.addr) ||
(io.write_ports(i).bits.addr === 0.U), // note: you only have to check one here
"[regfile] too many writers a register")
}
}
}
} | module regfile_52x64(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [63:0] R0_data,
input [5:0] R1_addr,
input R1_en,
input R1_clk,
output [63:0] R1_data,
input [5:0] R2_addr,
input R2_en,
input R2_clk,
output [63:0] R2_data,
input [5:0] R3_addr,
input R3_en,
input R3_clk,
output [63:0] R3_data,
input [5:0] W0_addr,
input W0_en,
input W0_clk,
input [63:0] W0_data,
input [5:0] W1_addr,
input W1_en,
input W1_clk,
input [63:0] W1_data
);
reg [63:0] Memory[0:51];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
if (W1_en & 1'h1)
Memory[W1_addr] <= W1_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 64'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 64'bx;
assign R2_data = R2_en ? Memory[R2_addr] : 64'bx;
assign R3_data = R3_en ? Memory[R3_addr] : 64'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{Decoupled, DecoupledIO}
// A Repeater passes its input to its output, unless repeat is asserted.
// When repeat is asserted, the Repeater copies the input and repeats it next cycle.
class Repeater[T <: Data](gen: T) extends Module
{
override def desiredName = s"Repeater_${gen.typeName}"
val io = IO( new Bundle {
val repeat = Input(Bool())
val full = Output(Bool())
val enq = Flipped(Decoupled(gen.cloneType))
val deq = Decoupled(gen.cloneType)
} )
val full = RegInit(false.B)
val saved = Reg(gen.cloneType)
// When !full, a repeater is pass-through
io.deq.valid := io.enq.valid || full
io.enq.ready := io.deq.ready && !full
io.deq.bits := Mux(full, saved, io.enq.bits)
io.full := full
when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }
when (io.deq.fire && !io.repeat) { full := false.B }
}
object Repeater
{
def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {
val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))
repeater.io.repeat := repeat
repeater.io.enq <> enq
repeater.io.deq
}
} | module Repeater_TLBundleA_a28d64s3k1z3u(
input clock,
input reset,
input io_repeat,
output io_full,
output io_enq_ready,
input io_enq_valid,
input [2:0] io_enq_bits_opcode,
input [2:0] io_enq_bits_param,
input [2:0] io_enq_bits_size,
input [2:0] io_enq_bits_source,
input [27:0] io_enq_bits_address,
input [7:0] io_enq_bits_mask,
input io_enq_bits_corrupt,
input io_deq_ready,
output io_deq_valid,
output [2:0] io_deq_bits_opcode,
output [2:0] io_deq_bits_param,
output [2:0] io_deq_bits_size,
output [2:0] io_deq_bits_source,
output [27:0] io_deq_bits_address,
output [7:0] io_deq_bits_mask,
output io_deq_bits_corrupt
);
reg full;
reg [2:0] saved_opcode;
reg [2:0] saved_param;
reg [2:0] saved_size;
reg [2:0] saved_source;
reg [27:0] saved_address;
reg [7:0] saved_mask;
reg saved_corrupt;
wire io_deq_valid_0 = io_enq_valid | full;
wire io_enq_ready_0 = io_deq_ready & ~full;
wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat;
always @(posedge clock) begin
if (reset)
full <= 1'h0;
else
full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full);
if (_GEN) begin
saved_opcode <= io_enq_bits_opcode;
saved_param <= io_enq_bits_param;
saved_size <= io_enq_bits_size;
saved_source <= io_enq_bits_source;
saved_address <= io_enq_bits_address;
saved_mask <= io_enq_bits_mask;
saved_corrupt <= io_enq_bits_corrupt;
end
end
assign io_full = full;
assign io_enq_ready = io_enq_ready_0;
assign io_deq_valid = io_deq_valid_0;
assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode;
assign io_deq_bits_param = full ? saved_param : io_enq_bits_param;
assign io_deq_bits_size = full ? saved_size : io_enq_bits_size;
assign io_deq_bits_source = full ? saved_source : io_enq_bits_source;
assign io_deq_bits_address = full ? saved_address : io_enq_bits_address;
assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask;
assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)
{
val queueBits = log2Up(queues)
val entryBits = log2Up(entries)
}
class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle
{
val index = UInt(params.queueBits.W)
val data = Output(params.gen)
}
class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module
{
override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}"
val io = IO(new Bundle {
// push is visible on the same cycle; flow queues
val push = Flipped(Decoupled(new ListBufferPush(params)))
val valid = UInt(params.queues.W)
val pop = Flipped(Valid(UInt(params.queueBits.W)))
val data = Output(params.gen)
})
val valid = RegInit(0.U(params.queues.W))
val head = Mem(params.queues, UInt(params.entryBits.W))
val tail = Mem(params.queues, UInt(params.entryBits.W))
val used = RegInit(0.U(params.entries.W))
val next = Mem(params.entries, UInt(params.entryBits.W))
val data = Mem(params.entries, params.gen)
val freeOH = ~(leftOR(~used) << 1) & ~used
val freeIdx = OHToUInt(freeOH)
val valid_set = WireDefault(0.U(params.queues.W))
val valid_clr = WireDefault(0.U(params.queues.W))
val used_set = WireDefault(0.U(params.entries.W))
val used_clr = WireDefault(0.U(params.entries.W))
val push_tail = tail.read(io.push.bits.index)
val push_valid = valid(io.push.bits.index)
io.push.ready := !used.andR
when (io.push.fire) {
valid_set := UIntToOH(io.push.bits.index, params.queues)
used_set := freeOH
data.write(freeIdx, io.push.bits.data)
when (push_valid) {
next.write(push_tail, freeIdx)
} .otherwise {
head.write(io.push.bits.index, freeIdx)
}
tail.write(io.push.bits.index, freeIdx)
}
val pop_head = head.read(io.pop.bits)
val pop_valid = valid(io.pop.bits)
// Bypass push data to the peek port
io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))
io.valid := (if (!params.bypass) valid else (valid | valid_set))
// It is an error to pop something that is not valid
assert (!io.pop.fire || (io.valid)(io.pop.bits))
when (io.pop.fire) {
used_clr := UIntToOH(pop_head, params.entries)
when (pop_head === tail.read(io.pop.bits)) {
valid_clr := UIntToOH(io.pop.bits, params.queues)
}
head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))
}
// Empty bypass changes no state
when ((!params.bypass).B || !io.pop.valid || pop_valid) {
used := (used & ~used_clr) | used_set
valid := (valid & ~valid_clr) | valid_set
}
} | module ListBuffer_PutBufferAEntry_q40_e40(
input clock,
input reset,
output io_push_ready,
input io_push_valid,
input [5:0] io_push_bits_index,
input [31:0] io_push_bits_data_data,
input [3:0] io_push_bits_data_mask,
input io_push_bits_data_corrupt,
output [39:0] io_valid,
input io_pop_valid,
input [5:0] io_pop_bits,
output [31:0] io_data_data,
output [3:0] io_data_mask,
output io_data_corrupt
);
wire [36:0] _data_ext_R0_data;
wire [5:0] _next_ext_R0_data;
wire [5:0] _tail_ext_R0_data;
wire [5:0] _tail_ext_R1_data;
wire [5:0] _head_ext_R0_data;
reg [39:0] valid;
reg [39:0] used;
wire [39:0] _freeOH_T_22 = ~used;
wire [38:0] _freeOH_T_3 = _freeOH_T_22[38:0] | {_freeOH_T_22[37:0], 1'h0};
wire [38:0] _freeOH_T_6 = _freeOH_T_3 | {_freeOH_T_3[36:0], 2'h0};
wire [38:0] _freeOH_T_9 = _freeOH_T_6 | {_freeOH_T_6[34:0], 4'h0};
wire [38:0] _freeOH_T_12 = _freeOH_T_9 | {_freeOH_T_9[30:0], 8'h0};
wire [38:0] _freeOH_T_15 = _freeOH_T_12 | {_freeOH_T_12[22:0], 16'h0};
wire [39:0] _GEN = {~(_freeOH_T_15 | {_freeOH_T_15[6:0], 32'h0}), 1'h1} & _freeOH_T_22;
wire [30:0] _freeIdx_T_1 = {24'h0, _GEN[39:33]} | _GEN[31:1];
wire [14:0] _freeIdx_T_3 = _freeIdx_T_1[30:16] | _freeIdx_T_1[14:0];
wire [6:0] _freeIdx_T_5 = _freeIdx_T_3[14:8] | _freeIdx_T_3[6:0];
wire [2:0] _freeIdx_T_7 = _freeIdx_T_5[6:4] | _freeIdx_T_5[2:0];
wire [5:0] freeIdx = {|(_GEN[39:32]), |(_freeIdx_T_1[30:15]), |(_freeIdx_T_3[14:7]), |(_freeIdx_T_5[6:3]), |(_freeIdx_T_7[2:1]), _freeIdx_T_7[2] | _freeIdx_T_7[0]};
wire [39:0] _push_valid_T = valid >> io_push_bits_index;
wire io_push_ready_0 = used != 40'hFFFFFFFFFF;
wire data_MPORT_en = io_push_ready_0 & io_push_valid;
wire [63:0] _valid_clr_T = 64'h1 << io_pop_bits;
wire [63:0] _valid_set_T = 64'h1 << io_push_bits_index;
wire [63:0] _used_clr_T = 64'h1 << _head_ext_R0_data;
always @(posedge clock) begin
if (reset) begin
valid <= 40'h0;
used <= 40'h0;
end
else begin
valid <= valid & ~(io_pop_valid & _head_ext_R0_data == _tail_ext_R1_data ? _valid_clr_T[39:0] : 40'h0) | (data_MPORT_en ? _valid_set_T[39:0] : 40'h0);
used <= used & ~(io_pop_valid ? _used_clr_T[39:0] : 40'h0) | (data_MPORT_en ? _GEN : 40'h0);
end
end
head_40x6 head_ext (
.R0_addr (io_pop_bits),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_head_ext_R0_data),
.W0_addr (io_pop_bits),
.W0_en (io_pop_valid),
.W0_clk (clock),
.W0_data (data_MPORT_en & _push_valid_T[0] & _tail_ext_R0_data == _head_ext_R0_data ? freeIdx : _next_ext_R0_data),
.W1_addr (io_push_bits_index),
.W1_en (data_MPORT_en & ~(_push_valid_T[0])),
.W1_clk (clock),
.W1_data (freeIdx)
);
tail_40x6 tail_ext (
.R0_addr (io_push_bits_index),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_tail_ext_R0_data),
.R1_addr (io_pop_bits),
.R1_en (io_pop_valid),
.R1_clk (clock),
.R1_data (_tail_ext_R1_data),
.W0_addr (io_push_bits_index),
.W0_en (data_MPORT_en),
.W0_clk (clock),
.W0_data (freeIdx)
);
next_40x6 next_ext (
.R0_addr (_head_ext_R0_data),
.R0_en (io_pop_valid),
.R0_clk (clock),
.R0_data (_next_ext_R0_data),
.W0_addr (_tail_ext_R0_data),
.W0_en (data_MPORT_en & _push_valid_T[0]),
.W0_clk (clock),
.W0_data (freeIdx)
);
data_40x37 data_ext (
.R0_addr (_head_ext_R0_data),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_data_ext_R0_data),
.W0_addr (freeIdx),
.W0_en (data_MPORT_en),
.W0_clk (clock),
.W0_data ({io_push_bits_data_corrupt, io_push_bits_data_mask, io_push_bits_data_data})
);
assign io_push_ready = io_push_ready_0;
assign io_valid = valid;
assign io_data_data = _data_ext_R0_data[31:0];
assign io_data_mask = _data_ext_R0_data[35:32];
assign io_data_corrupt = _data_ext_R0_data[36];
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
} | module table_0(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [43:0] R0_data,
input [6:0] W0_addr,
input W0_clk,
input [43:0] W0_data,
input [3:0] W0_mask
);
table_ext table_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (1'h1),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(t))
val out = Decoupled(new Flit(flitWidth))
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))
data(0) := DontCare // unused, DCE this
}
}
io.busy := io.out.valid
}
class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(t)
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits := (if (dataBeats == 1) {
io.in.bits.flit.asTypeOf(t)
} else {
Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)
})
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit
}
}
}
io.busy := beat =/= 0.U
}
class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Phit(phitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail
}
}
}
object FlitToPhit {
def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {
val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))
flit2phit.io.in <> flit
flit2phit.io.out
}
}
class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Decoupled(new Flit(flitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat) := io.in.bits.phit
}
}
}
}
object PhitToFlit {
def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in <> phit
phit2flit.io.out
}
def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in.valid := phit.valid
phit2flit.io.in.bits := phit.bits
when (phit.valid) { assert(phit2flit.io.in.ready) }
val out = Wire(Valid(new Flit(flitWidth)))
out.valid := phit2flit.io.out.valid
out.bits := phit2flit.io.out.bits
phit2flit.io.out.ready := true.B
out
}
}
class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))
val out = Decoupled(new Phit(phitWidth))
})
if (channels == 1) {
io.out <> io.in(0)
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val chosen_reg = Reg(UInt(headerWidth.W))
val chosen_prio = PriorityEncoder(io.in.map(_.valid))
val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.out.valid := VecInit(io.in.map(_.valid))(chosen)
io.out.bits.phit := Mux(beat < headerBeats.U,
chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),
VecInit(io.in.map(_.bits.phit))(chosen))
for (i <- 0 until channels) {
io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U
}
when (io.out.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) { chosen_reg := chosen_prio }
}
}
}
class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Vec(channels, Decoupled(new Phit(phitWidth)))
})
if (channels == 1) {
io.out(0) <> io.in
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))
val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)
for (c <- 0 until channels) {
io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U
io.out(c).bits.phit := io.in.bits.phit
}
when (io.in.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat < headerBeats.U) {
channel_vec(header_idx) := io.in.bits.phit
}
}
}
}
class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Flipped(Decoupled(new Flit(flitWidth)))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = io.out.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)
}
io.out.valid := io.in.valid && credits < bufferSz.U
io.out.bits.flit := io.in.bits.flit
io.in.ready := io.out.ready && credits < bufferSz.U
io.credit.ready := true.B
}
class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Decoupled(new Flit(flitWidth))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = buffer.io.deq.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credit_incr + Mux(credit_decr, 0.U, credits)
}
buffer.io.enq.valid := io.in.valid
buffer.io.enq.bits := io.in.bits
io.in.ready := true.B
when (io.in.valid) { assert(buffer.io.enq.ready) }
io.out <> buffer.io.deq
io.credit.valid := credits =/= 0.U
io.credit.bits.flit := credits - 1.U
} | module GenericDeserializer_TLBeatw88_f32(
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits_flit,
input io_out_ready,
output io_out_valid,
output [85:0] io_out_bits_payload,
output io_out_bits_head,
output io_out_bits_tail
);
reg [31:0] data_0;
reg [31:0] data_1;
reg [1:0] beat;
wire io_in_ready_0 = io_out_ready | beat != 2'h2;
wire _beat_T = beat == 2'h2;
wire _GEN = io_in_ready_0 & io_in_valid;
wire _GEN_0 = beat == 2'h2;
always @(posedge clock) begin
if (~_GEN | _GEN_0 | beat[0]) begin
end
else
data_0 <= io_in_bits_flit;
if (~_GEN | _GEN_0 | ~(beat[0])) begin
end
else
data_1 <= io_in_bits_flit;
if (reset)
beat <= 2'h0;
else if (_GEN)
beat <= _beat_T ? 2'h0 : beat + 2'h1;
end
assign io_in_ready = io_in_ready_0;
assign io_out_valid = io_in_valid & _beat_T;
assign io_out_bits_payload = {io_in_bits_flit[23:0], data_1, data_0[31:2]};
assign io_out_bits_head = data_0[1];
assign io_out_bits_tail = data_0[0];
endmodule |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)
{
val queueBits = log2Up(queues)
val entryBits = log2Up(entries)
}
class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle
{
val index = UInt(params.queueBits.W)
val data = Output(params.gen)
}
class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module
{
override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}"
val io = IO(new Bundle {
// push is visible on the same cycle; flow queues
val push = Flipped(Decoupled(new ListBufferPush(params)))
val valid = UInt(params.queues.W)
val pop = Flipped(Valid(UInt(params.queueBits.W)))
val data = Output(params.gen)
})
val valid = RegInit(0.U(params.queues.W))
val head = Mem(params.queues, UInt(params.entryBits.W))
val tail = Mem(params.queues, UInt(params.entryBits.W))
val used = RegInit(0.U(params.entries.W))
val next = Mem(params.entries, UInt(params.entryBits.W))
val data = Mem(params.entries, params.gen)
val freeOH = ~(leftOR(~used) << 1) & ~used
val freeIdx = OHToUInt(freeOH)
val valid_set = WireDefault(0.U(params.queues.W))
val valid_clr = WireDefault(0.U(params.queues.W))
val used_set = WireDefault(0.U(params.entries.W))
val used_clr = WireDefault(0.U(params.entries.W))
val push_tail = tail.read(io.push.bits.index)
val push_valid = valid(io.push.bits.index)
io.push.ready := !used.andR
when (io.push.fire) {
valid_set := UIntToOH(io.push.bits.index, params.queues)
used_set := freeOH
data.write(freeIdx, io.push.bits.data)
when (push_valid) {
next.write(push_tail, freeIdx)
} .otherwise {
head.write(io.push.bits.index, freeIdx)
}
tail.write(io.push.bits.index, freeIdx)
}
val pop_head = head.read(io.pop.bits)
val pop_valid = valid(io.pop.bits)
// Bypass push data to the peek port
io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))
io.valid := (if (!params.bypass) valid else (valid | valid_set))
// It is an error to pop something that is not valid
assert (!io.pop.fire || (io.valid)(io.pop.bits))
when (io.pop.fire) {
used_clr := UIntToOH(pop_head, params.entries)
when (pop_head === tail.read(io.pop.bits)) {
valid_clr := UIntToOH(io.pop.bits, params.queues)
}
head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))
}
// Empty bypass changes no state
when ((!params.bypass).B || !io.pop.valid || pop_valid) {
used := (used & ~used_clr) | used_set
valid := (valid & ~valid_clr) | valid_set
}
} | module head_15x6(
input [3:0] R0_addr,
input R0_en,
input R0_clk,
output [5:0] R0_data,
input [3:0] W0_addr,
input W0_en,
input W0_clk,
input [5:0] W0_data,
input [3:0] W1_addr,
input W1_en,
input W1_clk,
input [5:0] W1_data
);
reg [5:0] Memory[0:14];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
if (W1_en & 1'h1)
Memory[W1_addr] <= W1_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 6'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)
{
val queueBits = log2Up(queues)
val entryBits = log2Up(entries)
}
class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle
{
val index = UInt(params.queueBits.W)
val data = Output(params.gen)
}
class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module
{
override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}"
val io = IO(new Bundle {
// push is visible on the same cycle; flow queues
val push = Flipped(Decoupled(new ListBufferPush(params)))
val valid = UInt(params.queues.W)
val pop = Flipped(Valid(UInt(params.queueBits.W)))
val data = Output(params.gen)
})
val valid = RegInit(0.U(params.queues.W))
val head = Mem(params.queues, UInt(params.entryBits.W))
val tail = Mem(params.queues, UInt(params.entryBits.W))
val used = RegInit(0.U(params.entries.W))
val next = Mem(params.entries, UInt(params.entryBits.W))
val data = Mem(params.entries, params.gen)
val freeOH = ~(leftOR(~used) << 1) & ~used
val freeIdx = OHToUInt(freeOH)
val valid_set = WireDefault(0.U(params.queues.W))
val valid_clr = WireDefault(0.U(params.queues.W))
val used_set = WireDefault(0.U(params.entries.W))
val used_clr = WireDefault(0.U(params.entries.W))
val push_tail = tail.read(io.push.bits.index)
val push_valid = valid(io.push.bits.index)
io.push.ready := !used.andR
when (io.push.fire) {
valid_set := UIntToOH(io.push.bits.index, params.queues)
used_set := freeOH
data.write(freeIdx, io.push.bits.data)
when (push_valid) {
next.write(push_tail, freeIdx)
} .otherwise {
head.write(io.push.bits.index, freeIdx)
}
tail.write(io.push.bits.index, freeIdx)
}
val pop_head = head.read(io.pop.bits)
val pop_valid = valid(io.pop.bits)
// Bypass push data to the peek port
io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))
io.valid := (if (!params.bypass) valid else (valid | valid_set))
// It is an error to pop something that is not valid
assert (!io.pop.fire || (io.valid)(io.pop.bits))
when (io.pop.fire) {
used_clr := UIntToOH(pop_head, params.entries)
when (pop_head === tail.read(io.pop.bits)) {
valid_clr := UIntToOH(io.pop.bits, params.queues)
}
head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))
}
// Empty bypass changes no state
when ((!params.bypass).B || !io.pop.valid || pop_valid) {
used := (used & ~used_clr) | used_set
valid := (valid & ~valid_clr) | valid_set
}
} | module ListBuffer_QueuedRequest_q21_e33(
input clock,
input reset,
output io_push_ready,
input io_push_valid,
input [4:0] io_push_bits_index,
input io_push_bits_data_prio_0,
input io_push_bits_data_prio_2,
input io_push_bits_data_control,
input [2:0] io_push_bits_data_opcode,
input [2:0] io_push_bits_data_param,
input [2:0] io_push_bits_data_size,
input [5:0] io_push_bits_data_source,
input [12:0] io_push_bits_data_tag,
input [5:0] io_push_bits_data_offset,
input [5:0] io_push_bits_data_put,
output [20:0] io_valid,
input io_pop_valid,
input [4:0] io_pop_bits,
output io_data_prio_0,
output io_data_prio_1,
output io_data_prio_2,
output io_data_control,
output [2:0] io_data_opcode,
output [2:0] io_data_param,
output [2:0] io_data_size,
output [5:0] io_data_source,
output [12:0] io_data_tag,
output [5:0] io_data_offset,
output [5:0] io_data_put
);
wire [43:0] _data_ext_R0_data;
wire [5:0] _next_ext_R0_data;
wire [5:0] _tail_ext_R0_data;
wire [5:0] _tail_ext_R1_data;
wire [5:0] _head_ext_R0_data;
reg [20:0] valid;
reg [32:0] used;
wire [32:0] _freeOH_T_22 = ~used;
wire [31:0] _freeOH_T_3 = _freeOH_T_22[31:0] | {_freeOH_T_22[30:0], 1'h0};
wire [31:0] _freeOH_T_6 = _freeOH_T_3 | {_freeOH_T_3[29:0], 2'h0};
wire [31:0] _freeOH_T_9 = _freeOH_T_6 | {_freeOH_T_6[27:0], 4'h0};
wire [31:0] _freeOH_T_12 = _freeOH_T_9 | {_freeOH_T_9[23:0], 8'h0};
wire [32:0] _GEN = {~(_freeOH_T_12 | {_freeOH_T_12[15:0], 16'h0}), 1'h1} & _freeOH_T_22;
wire [14:0] _freeIdx_T_3 = _GEN[31:17] | _GEN[15:1];
wire [6:0] _freeIdx_T_5 = _freeIdx_T_3[14:8] | _freeIdx_T_3[6:0];
wire [2:0] _freeIdx_T_7 = _freeIdx_T_5[6:4] | _freeIdx_T_5[2:0];
wire [5:0] freeIdx = {_GEN[32], |(_GEN[31:16]), |(_freeIdx_T_3[14:7]), |(_freeIdx_T_5[6:3]), |(_freeIdx_T_7[2:1]), _freeIdx_T_7[2] | _freeIdx_T_7[0]};
wire [20:0] _push_valid_T = valid >> io_push_bits_index;
wire io_push_ready_0 = used != 33'h1FFFFFFFF;
wire data_MPORT_en = io_push_ready_0 & io_push_valid;
wire [31:0] _valid_clr_T = 32'h1 << io_pop_bits;
wire [31:0] _valid_set_T = 32'h1 << io_push_bits_index;
wire [63:0] _used_clr_T = 64'h1 << _head_ext_R0_data;
always @(posedge clock) begin
if (reset) begin
valid <= 21'h0;
used <= 33'h0;
end
else begin
valid <= valid & ~(io_pop_valid & _head_ext_R0_data == _tail_ext_R1_data ? _valid_clr_T[20:0] : 21'h0) | (data_MPORT_en ? _valid_set_T[20:0] : 21'h0);
used <= used & ~(io_pop_valid ? _used_clr_T[32:0] : 33'h0) | (data_MPORT_en ? _GEN : 33'h0);
end
end
head_21x6 head_ext (
.R0_addr (io_pop_bits),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_head_ext_R0_data),
.W0_addr (io_pop_bits),
.W0_en (io_pop_valid),
.W0_clk (clock),
.W0_data (data_MPORT_en & _push_valid_T[0] & _tail_ext_R0_data == _head_ext_R0_data ? freeIdx : _next_ext_R0_data),
.W1_addr (io_push_bits_index),
.W1_en (data_MPORT_en & ~(_push_valid_T[0])),
.W1_clk (clock),
.W1_data (freeIdx)
);
tail_21x6 tail_ext (
.R0_addr (io_push_bits_index),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_tail_ext_R0_data),
.R1_addr (io_pop_bits),
.R1_en (io_pop_valid),
.R1_clk (clock),
.R1_data (_tail_ext_R1_data),
.W0_addr (io_push_bits_index),
.W0_en (data_MPORT_en),
.W0_clk (clock),
.W0_data (freeIdx)
);
next_33x6 next_ext (
.R0_addr (_head_ext_R0_data),
.R0_en (io_pop_valid),
.R0_clk (clock),
.R0_data (_next_ext_R0_data),
.W0_addr (_tail_ext_R0_data),
.W0_en (data_MPORT_en & _push_valid_T[0]),
.W0_clk (clock),
.W0_data (freeIdx)
);
data_33x44 data_ext (
.R0_addr (_head_ext_R0_data),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_data_ext_R0_data),
.W0_addr (freeIdx),
.W0_en (data_MPORT_en),
.W0_clk (clock),
.W0_data ({io_push_bits_data_put, io_push_bits_data_offset, io_push_bits_data_tag, io_push_bits_data_source, io_push_bits_data_size, io_push_bits_data_param, io_push_bits_data_opcode, io_push_bits_data_control, io_push_bits_data_prio_2, 1'h0, io_push_bits_data_prio_0})
);
assign io_push_ready = io_push_ready_0;
assign io_valid = valid;
assign io_data_prio_0 = _data_ext_R0_data[0];
assign io_data_prio_1 = _data_ext_R0_data[1];
assign io_data_prio_2 = _data_ext_R0_data[2];
assign io_data_control = _data_ext_R0_data[3];
assign io_data_opcode = _data_ext_R0_data[6:4];
assign io_data_param = _data_ext_R0_data[9:7];
assign io_data_size = _data_ext_R0_data[12:10];
assign io_data_source = _data_ext_R0_data[18:13];
assign io_data_tag = _data_ext_R0_data[31:19];
assign io_data_offset = _data_ext_R0_data[37:32];
assign io_data_put = _data_ext_R0_data[43:38];
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Ported from Rocket-Chip
// See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.lsu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.rocket._
import boom.v3.common._
import boom.v3.exu.BrUpdateInfo
import boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc, Transpose}
class BoomWritebackUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) {
val io = IO(new Bundle {
val req = Flipped(Decoupled(new WritebackReq(edge.bundle)))
val meta_read = Decoupled(new L1MetaReadReq)
val resp = Output(Bool())
val idx = Output(Valid(UInt()))
val data_req = Decoupled(new L1DataReadReq)
val data_resp = Input(UInt(encRowBits.W))
val mem_grant = Input(Bool())
val release = Decoupled(new TLBundleC(edge.bundle))
val lsu_release = Decoupled(new TLBundleC(edge.bundle))
})
val req = Reg(new WritebackReq(edge.bundle))
val s_invalid :: s_fill_buffer :: s_lsu_release :: s_active :: s_grant :: Nil = Enum(5)
val state = RegInit(s_invalid)
val r1_data_req_fired = RegInit(false.B)
val r2_data_req_fired = RegInit(false.B)
val r1_data_req_cnt = Reg(UInt(log2Up(refillCycles+1).W))
val r2_data_req_cnt = Reg(UInt(log2Up(refillCycles+1).W))
val data_req_cnt = RegInit(0.U(log2Up(refillCycles+1).W))
val (_, last_beat, all_beats_done, beat_count) = edge.count(io.release)
val wb_buffer = Reg(Vec(refillCycles, UInt(encRowBits.W)))
val acked = RegInit(false.B)
io.idx.valid := state =/= s_invalid
io.idx.bits := req.idx
io.release.valid := false.B
io.release.bits := DontCare
io.req.ready := false.B
io.meta_read.valid := false.B
io.meta_read.bits := DontCare
io.data_req.valid := false.B
io.data_req.bits := DontCare
io.resp := false.B
io.lsu_release.valid := false.B
io.lsu_release.bits := DontCare
val r_address = Cat(req.tag, req.idx) << blockOffBits
val id = cfg.nMSHRs
val probeResponse = edge.ProbeAck(
fromSource = id.U,
toAddress = r_address,
lgSize = lgCacheBlockBytes.U,
reportPermissions = req.param,
data = wb_buffer(data_req_cnt))
val voluntaryRelease = edge.Release(
fromSource = id.U,
toAddress = r_address,
lgSize = lgCacheBlockBytes.U,
shrinkPermissions = req.param,
data = wb_buffer(data_req_cnt))._2
when (state === s_invalid) {
io.req.ready := true.B
when (io.req.fire) {
state := s_fill_buffer
data_req_cnt := 0.U
req := io.req.bits
acked := false.B
}
} .elsewhen (state === s_fill_buffer) {
io.meta_read.valid := data_req_cnt < refillCycles.U
io.meta_read.bits.idx := req.idx
io.meta_read.bits.tag := req.tag
io.data_req.valid := data_req_cnt < refillCycles.U
io.data_req.bits.way_en := req.way_en
io.data_req.bits.addr := (if(refillCycles > 1)
Cat(req.idx, data_req_cnt(log2Up(refillCycles)-1,0))
else req.idx) << rowOffBits
r1_data_req_fired := false.B
r1_data_req_cnt := 0.U
r2_data_req_fired := r1_data_req_fired
r2_data_req_cnt := r1_data_req_cnt
when (io.data_req.fire && io.meta_read.fire) {
r1_data_req_fired := true.B
r1_data_req_cnt := data_req_cnt
data_req_cnt := data_req_cnt + 1.U
}
when (r2_data_req_fired) {
wb_buffer(r2_data_req_cnt) := io.data_resp
when (r2_data_req_cnt === (refillCycles-1).U) {
io.resp := true.B
state := s_lsu_release
data_req_cnt := 0.U
}
}
} .elsewhen (state === s_lsu_release) {
io.lsu_release.valid := true.B
io.lsu_release.bits := probeResponse
when (io.lsu_release.fire) {
state := s_active
}
} .elsewhen (state === s_active) {
io.release.valid := data_req_cnt < refillCycles.U
io.release.bits := Mux(req.voluntary, voluntaryRelease, probeResponse)
when (io.mem_grant) {
acked := true.B
}
when (io.release.fire) {
data_req_cnt := data_req_cnt + 1.U
}
when ((data_req_cnt === (refillCycles-1).U) && io.release.fire) {
state := Mux(req.voluntary, s_grant, s_invalid)
}
} .elsewhen (state === s_grant) {
when (io.mem_grant) {
acked := true.B
}
when (acked) {
state := s_invalid
}
}
}
class BoomProbeUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) {
val io = IO(new Bundle {
val req = Flipped(Decoupled(new TLBundleB(edge.bundle)))
val rep = Decoupled(new TLBundleC(edge.bundle))
val meta_read = Decoupled(new L1MetaReadReq)
val meta_write = Decoupled(new L1MetaWriteReq)
val wb_req = Decoupled(new WritebackReq(edge.bundle))
val way_en = Input(UInt(nWays.W))
val wb_rdy = Input(Bool()) // Is writeback unit currently busy? If so need to retry meta read when its done
val mshr_rdy = Input(Bool()) // Is MSHR ready for this request to proceed?
val mshr_wb_rdy = Output(Bool()) // Should we block MSHR writebacks while we finish our own?
val block_state = Input(new ClientMetadata())
val lsu_release = Decoupled(new TLBundleC(edge.bundle))
val state = Output(Valid(UInt(coreMaxAddrBits.W)))
})
val (s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req ::
s_mshr_resp :: s_lsu_release :: s_release :: s_writeback_req :: s_writeback_resp ::
s_meta_write :: s_meta_write_resp :: Nil) = Enum(11)
val state = RegInit(s_invalid)
val req = Reg(new TLBundleB(edge.bundle))
val req_idx = req.address(idxMSB, idxLSB)
val req_tag = req.address >> untagBits
val way_en = Reg(UInt())
val tag_matches = way_en.orR
val old_coh = Reg(new ClientMetadata)
val miss_coh = ClientMetadata.onReset
val reply_coh = Mux(tag_matches, old_coh, miss_coh)
val (is_dirty, report_param, new_coh) = reply_coh.onProbe(req.param)
io.state.valid := state =/= s_invalid
io.state.bits := req.address
io.req.ready := state === s_invalid
io.rep.valid := state === s_release
io.rep.bits := edge.ProbeAck(req, report_param)
assert(!io.rep.valid || !edge.hasData(io.rep.bits),
"ProbeUnit should not send ProbeAcks with data, WritebackUnit should handle it")
io.meta_read.valid := state === s_meta_read
io.meta_read.bits.idx := req_idx
io.meta_read.bits.tag := req_tag
io.meta_read.bits.way_en := ~(0.U(nWays.W))
io.meta_write.valid := state === s_meta_write
io.meta_write.bits.way_en := way_en
io.meta_write.bits.idx := req_idx
io.meta_write.bits.tag := req_tag
io.meta_write.bits.data.tag := req_tag
io.meta_write.bits.data.coh := new_coh
io.wb_req.valid := state === s_writeback_req
io.wb_req.bits.source := req.source
io.wb_req.bits.idx := req_idx
io.wb_req.bits.tag := req_tag
io.wb_req.bits.param := report_param
io.wb_req.bits.way_en := way_en
io.wb_req.bits.voluntary := false.B
io.mshr_wb_rdy := !state.isOneOf(s_release, s_writeback_req, s_writeback_resp, s_meta_write, s_meta_write_resp)
io.lsu_release.valid := state === s_lsu_release
io.lsu_release.bits := edge.ProbeAck(req, report_param)
// state === s_invalid
when (state === s_invalid) {
when (io.req.fire) {
state := s_meta_read
req := io.req.bits
}
} .elsewhen (state === s_meta_read) {
when (io.meta_read.fire) {
state := s_meta_resp
}
} .elsewhen (state === s_meta_resp) {
// we need to wait one cycle for the metadata to be read from the array
state := s_mshr_req
} .elsewhen (state === s_mshr_req) {
old_coh := io.block_state
way_en := io.way_en
// if the read didn't go through, we need to retry
state := Mux(io.mshr_rdy && io.wb_rdy, s_mshr_resp, s_meta_read)
} .elsewhen (state === s_mshr_resp) {
state := Mux(tag_matches && is_dirty, s_writeback_req, s_lsu_release)
} .elsewhen (state === s_lsu_release) {
when (io.lsu_release.fire) {
state := s_release
}
} .elsewhen (state === s_release) {
when (io.rep.ready) {
state := Mux(tag_matches, s_meta_write, s_invalid)
}
} .elsewhen (state === s_writeback_req) {
when (io.wb_req.fire) {
state := s_writeback_resp
}
} .elsewhen (state === s_writeback_resp) {
// wait for the writeback request to finish before updating the metadata
when (io.wb_req.ready) {
state := s_meta_write
}
} .elsewhen (state === s_meta_write) {
when (io.meta_write.fire) {
state := s_meta_write_resp
}
} .elsewhen (state === s_meta_write_resp) {
state := s_invalid
}
}
class BoomL1MetaReadReq(implicit p: Parameters) extends BoomBundle()(p) {
val req = Vec(memWidth, new L1MetaReadReq)
}
class BoomL1DataReadReq(implicit p: Parameters) extends BoomBundle()(p) {
val req = Vec(memWidth, new L1DataReadReq)
val valid = Vec(memWidth, Bool())
}
abstract class AbstractBoomDataArray(implicit p: Parameters) extends BoomModule with HasL1HellaCacheParameters {
val io = IO(new BoomBundle {
val read = Input(Vec(memWidth, Valid(new L1DataReadReq)))
val write = Input(Valid(new L1DataWriteReq))
val resp = Output(Vec(memWidth, Vec(nWays, Bits(encRowBits.W))))
val nacks = Output(Vec(memWidth, Bool()))
})
def pipeMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f))
}
class BoomDuplicatedDataArray(implicit p: Parameters) extends AbstractBoomDataArray
{
val waddr = io.write.bits.addr >> rowOffBits
for (j <- 0 until memWidth) {
val raddr = io.read(j).bits.addr >> rowOffBits
for (w <- 0 until nWays) {
val array = DescribedSRAM(
name = s"array_${w}_${j}",
desc = "Non-blocking DCache Data Array",
size = nSets * refillCycles,
data = Vec(rowWords, Bits(encDataBits.W))
)
when (io.write.bits.way_en(w) && io.write.valid) {
val data = VecInit((0 until rowWords) map (i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i)))
array.write(waddr, data, io.write.bits.wmask.asBools)
}
io.resp(j)(w) := RegNext(array.read(raddr, io.read(j).bits.way_en(w) && io.read(j).valid).asUInt)
}
io.nacks(j) := false.B
}
}
class BoomBankedDataArray(implicit p: Parameters) extends AbstractBoomDataArray {
val nBanks = boomParams.numDCacheBanks
val bankSize = nSets * refillCycles / nBanks
require (nBanks >= memWidth)
require (bankSize > 0)
val bankBits = log2Ceil(nBanks)
val bankOffBits = log2Ceil(rowWords) + log2Ceil(wordBytes)
val bidxBits = log2Ceil(bankSize)
val bidxOffBits = bankOffBits + bankBits
//----------------------------------------------------------------------------------------------------
val s0_rbanks = if (nBanks > 1) VecInit(io.read.map(r => (r.bits.addr >> bankOffBits)(bankBits-1,0))) else VecInit(0.U)
val s0_wbank = if (nBanks > 1) (io.write.bits.addr >> bankOffBits)(bankBits-1,0) else 0.U
val s0_ridxs = VecInit(io.read.map(r => (r.bits.addr >> bidxOffBits)(bidxBits-1,0)))
val s0_widx = (io.write.bits.addr >> bidxOffBits)(bidxBits-1,0)
val s0_read_valids = VecInit(io.read.map(_.valid))
val s0_bank_conflicts = pipeMap(w => (0 until w).foldLeft(false.B)((c,i) => c || io.read(i).valid && s0_rbanks(i) === s0_rbanks(w)))
val s0_do_bank_read = s0_read_valids zip s0_bank_conflicts map {case (v,c) => v && !c}
val s0_bank_read_gnts = Transpose(VecInit(s0_rbanks zip s0_do_bank_read map {case (b,d) => VecInit((UIntToOH(b) & Fill(nBanks,d)).asBools)}))
val s0_bank_write_gnt = (UIntToOH(s0_wbank) & Fill(nBanks, io.write.valid)).asBools
//----------------------------------------------------------------------------------------------------
val s1_rbanks = RegNext(s0_rbanks)
val s1_ridxs = RegNext(s0_ridxs)
val s1_read_valids = RegNext(s0_read_valids)
val s1_pipe_selection = pipeMap(i => VecInit(PriorityEncoderOH(pipeMap(j =>
if (j < i) s1_read_valids(j) && s1_rbanks(j) === s1_rbanks(i)
else if (j == i) true.B else false.B))))
val s1_ridx_match = pipeMap(i => pipeMap(j => if (j < i) s1_ridxs(j) === s1_ridxs(i)
else if (j == i) true.B else false.B))
val s1_nacks = pipeMap(w => s1_read_valids(w) && (s1_pipe_selection(w).asUInt & ~s1_ridx_match(w).asUInt).orR)
val s1_bank_selection = pipeMap(w => Mux1H(s1_pipe_selection(w), s1_rbanks))
//----------------------------------------------------------------------------------------------------
val s2_bank_selection = RegNext(s1_bank_selection)
val s2_nacks = RegNext(s1_nacks)
for (w <- 0 until nWays) {
val s2_bank_reads = Reg(Vec(nBanks, Bits(encRowBits.W)))
for (b <- 0 until nBanks) {
val array = DescribedSRAM(
name = s"array_${w}_${b}",
desc = "Non-blocking DCache Data Array",
size = bankSize,
data = Vec(rowWords, Bits(encDataBits.W))
)
val ridx = Mux1H(s0_bank_read_gnts(b), s0_ridxs)
val way_en = Mux1H(s0_bank_read_gnts(b), io.read.map(_.bits.way_en))
s2_bank_reads(b) := array.read(ridx, way_en(w) && s0_bank_read_gnts(b).reduce(_||_)).asUInt
when (io.write.bits.way_en(w) && s0_bank_write_gnt(b)) {
val data = VecInit((0 until rowWords) map (i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i)))
array.write(s0_widx, data, io.write.bits.wmask.asBools)
}
}
for (i <- 0 until memWidth) {
io.resp(i)(w) := s2_bank_reads(s2_bank_selection(i))
}
}
io.nacks := s2_nacks
}
/**
* Top level class wrapping a non-blocking dcache.
*
* @param hartid hardware thread for the cache
*/
class BoomNonBlockingDCache(staticIdForMetadataUseOnly: Int)(implicit p: Parameters) extends LazyModule
{
private val tileParams = p(TileKey)
protected val cfg = tileParams.dcache.get
protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1(
name = s"Core ${staticIdForMetadataUseOnly} DCache",
sourceId = IdRange(0, 1 max (cfg.nMSHRs + 1)),
supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes))))
protected def mmioClientParameters = Seq(TLMasterParameters.v1(
name = s"Core ${staticIdForMetadataUseOnly} DCache MMIO",
sourceId = IdRange(cfg.nMSHRs + 1, cfg.nMSHRs + 1 + cfg.nMMIOs),
requestFifo = true))
val node = TLClientNode(Seq(TLMasterPortParameters.v1(
cacheClientParameters ++ mmioClientParameters,
minLatency = 1)))
lazy val module = new BoomNonBlockingDCacheModule(this)
def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireT || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT)
require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$")
}
class BoomDCacheBundle(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) {
val lsu = Flipped(new LSUDMemIO)
}
class BoomNonBlockingDCacheModule(outer: BoomNonBlockingDCache) extends LazyModuleImp(outer)
with HasL1HellaCacheParameters
with HasBoomCoreParameters
{
implicit val edge = outer.node.edges.out(0)
val (tl_out, _) = outer.node.out(0)
val io = IO(new BoomDCacheBundle)
private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile)
fifoManagers.foreach { m =>
require (m.fifoId == fifoManagers.head.fifoId,
s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees ${m.nodePath.map(_.name)}")
}
def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f))
val t_replay :: t_probe :: t_wb :: t_mshr_meta_read :: t_lsu :: t_prefetch :: Nil = Enum(6)
val wb = Module(new BoomWritebackUnit)
val prober = Module(new BoomProbeUnit)
val mshrs = Module(new BoomMSHRFile)
mshrs.io.clear_all := io.lsu.force_order
mshrs.io.brupdate := io.lsu.brupdate
mshrs.io.exception := io.lsu.exception
mshrs.io.rob_pnr_idx := io.lsu.rob_pnr_idx
mshrs.io.rob_head_idx := io.lsu.rob_head_idx
// tags
def onReset = L1Metadata(0.U, ClientMetadata.onReset)
val meta = Seq.fill(memWidth) { Module(new L1MetadataArray(onReset _)) }
val metaWriteArb = Module(new Arbiter(new L1MetaWriteReq, 2))
// 0 goes to MSHR refills, 1 goes to prober
val metaReadArb = Module(new Arbiter(new BoomL1MetaReadReq, 6))
// 0 goes to MSHR replays, 1 goes to prober, 2 goes to wb, 3 goes to MSHR meta read,
// 4 goes to pipeline, 5 goes to prefetcher
metaReadArb.io.in := DontCare
for (w <- 0 until memWidth) {
meta(w).io.write.valid := metaWriteArb.io.out.fire
meta(w).io.write.bits := metaWriteArb.io.out.bits
meta(w).io.read.valid := metaReadArb.io.out.valid
meta(w).io.read.bits := metaReadArb.io.out.bits.req(w)
}
metaReadArb.io.out.ready := meta.map(_.io.read.ready).reduce(_||_)
metaWriteArb.io.out.ready := meta.map(_.io.write.ready).reduce(_||_)
// data
val data = Module(if (boomParams.numDCacheBanks == 1) new BoomDuplicatedDataArray else new BoomBankedDataArray)
val dataWriteArb = Module(new Arbiter(new L1DataWriteReq, 2))
// 0 goes to pipeline, 1 goes to MSHR refills
val dataReadArb = Module(new Arbiter(new BoomL1DataReadReq, 3))
// 0 goes to MSHR replays, 1 goes to wb, 2 goes to pipeline
dataReadArb.io.in := DontCare
for (w <- 0 until memWidth) {
data.io.read(w).valid := dataReadArb.io.out.bits.valid(w) && dataReadArb.io.out.valid
data.io.read(w).bits := dataReadArb.io.out.bits.req(w)
}
dataReadArb.io.out.ready := true.B
data.io.write.valid := dataWriteArb.io.out.fire
data.io.write.bits := dataWriteArb.io.out.bits
dataWriteArb.io.out.ready := true.B
// ------------
// New requests
io.lsu.req.ready := metaReadArb.io.in(4).ready && dataReadArb.io.in(2).ready
metaReadArb.io.in(4).valid := io.lsu.req.valid
dataReadArb.io.in(2).valid := io.lsu.req.valid
for (w <- 0 until memWidth) {
// Tag read for new requests
metaReadArb.io.in(4).bits.req(w).idx := io.lsu.req.bits(w).bits.addr >> blockOffBits
metaReadArb.io.in(4).bits.req(w).way_en := DontCare
metaReadArb.io.in(4).bits.req(w).tag := DontCare
// Data read for new requests
dataReadArb.io.in(2).bits.valid(w) := io.lsu.req.bits(w).valid
dataReadArb.io.in(2).bits.req(w).addr := io.lsu.req.bits(w).bits.addr
dataReadArb.io.in(2).bits.req(w).way_en := ~0.U(nWays.W)
}
// ------------
// MSHR Replays
val replay_req = Wire(Vec(memWidth, new BoomDCacheReq))
replay_req := DontCare
replay_req(0).uop := mshrs.io.replay.bits.uop
replay_req(0).addr := mshrs.io.replay.bits.addr
replay_req(0).data := mshrs.io.replay.bits.data
replay_req(0).is_hella := mshrs.io.replay.bits.is_hella
mshrs.io.replay.ready := metaReadArb.io.in(0).ready && dataReadArb.io.in(0).ready
// Tag read for MSHR replays
// We don't actually need to read the metadata, for replays we already know our way
metaReadArb.io.in(0).valid := mshrs.io.replay.valid
metaReadArb.io.in(0).bits.req(0).idx := mshrs.io.replay.bits.addr >> blockOffBits
metaReadArb.io.in(0).bits.req(0).way_en := DontCare
metaReadArb.io.in(0).bits.req(0).tag := DontCare
// Data read for MSHR replays
dataReadArb.io.in(0).valid := mshrs.io.replay.valid
dataReadArb.io.in(0).bits.req(0).addr := mshrs.io.replay.bits.addr
dataReadArb.io.in(0).bits.req(0).way_en := mshrs.io.replay.bits.way_en
dataReadArb.io.in(0).bits.valid := widthMap(w => (w == 0).B)
// -----------
// MSHR Meta read
val mshr_read_req = Wire(Vec(memWidth, new BoomDCacheReq))
mshr_read_req := DontCare
mshr_read_req(0).uop := NullMicroOp
mshr_read_req(0).addr := Cat(mshrs.io.meta_read.bits.tag, mshrs.io.meta_read.bits.idx) << blockOffBits
mshr_read_req(0).data := DontCare
mshr_read_req(0).is_hella := false.B
metaReadArb.io.in(3).valid := mshrs.io.meta_read.valid
metaReadArb.io.in(3).bits.req(0) := mshrs.io.meta_read.bits
mshrs.io.meta_read.ready := metaReadArb.io.in(3).ready
// -----------
// Write-backs
val wb_fire = wb.io.meta_read.fire && wb.io.data_req.fire
val wb_req = Wire(Vec(memWidth, new BoomDCacheReq))
wb_req := DontCare
wb_req(0).uop := NullMicroOp
wb_req(0).addr := Cat(wb.io.meta_read.bits.tag, wb.io.data_req.bits.addr)
wb_req(0).data := DontCare
wb_req(0).is_hella := false.B
// Couple the two decoupled interfaces of the WBUnit's meta_read and data_read
// Tag read for write-back
metaReadArb.io.in(2).valid := wb.io.meta_read.valid
metaReadArb.io.in(2).bits.req(0) := wb.io.meta_read.bits
wb.io.meta_read.ready := metaReadArb.io.in(2).ready && dataReadArb.io.in(1).ready
// Data read for write-back
dataReadArb.io.in(1).valid := wb.io.data_req.valid
dataReadArb.io.in(1).bits.req(0) := wb.io.data_req.bits
dataReadArb.io.in(1).bits.valid := widthMap(w => (w == 0).B)
wb.io.data_req.ready := metaReadArb.io.in(2).ready && dataReadArb.io.in(1).ready
assert(!(wb.io.meta_read.fire ^ wb.io.data_req.fire))
// -------
// Prober
val prober_fire = prober.io.meta_read.fire
val prober_req = Wire(Vec(memWidth, new BoomDCacheReq))
prober_req := DontCare
prober_req(0).uop := NullMicroOp
prober_req(0).addr := Cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx) << blockOffBits
prober_req(0).data := DontCare
prober_req(0).is_hella := false.B
// Tag read for prober
metaReadArb.io.in(1).valid := prober.io.meta_read.valid
metaReadArb.io.in(1).bits.req(0) := prober.io.meta_read.bits
prober.io.meta_read.ready := metaReadArb.io.in(1).ready
// Prober does not need to read data array
// -------
// Prefetcher
val prefetch_fire = mshrs.io.prefetch.fire
val prefetch_req = Wire(Vec(memWidth, new BoomDCacheReq))
prefetch_req := DontCare
prefetch_req(0) := mshrs.io.prefetch.bits
// Tag read for prefetch
metaReadArb.io.in(5).valid := mshrs.io.prefetch.valid
metaReadArb.io.in(5).bits.req(0).idx := mshrs.io.prefetch.bits.addr >> blockOffBits
metaReadArb.io.in(5).bits.req(0).way_en := DontCare
metaReadArb.io.in(5).bits.req(0).tag := DontCare
mshrs.io.prefetch.ready := metaReadArb.io.in(5).ready
// Prefetch does not need to read data array
val s0_valid = Mux(io.lsu.req.fire, VecInit(io.lsu.req.bits.map(_.valid)),
Mux(mshrs.io.replay.fire || wb_fire || prober_fire || prefetch_fire || mshrs.io.meta_read.fire,
VecInit(1.U(memWidth.W).asBools), VecInit(0.U(memWidth.W).asBools)))
val s0_req = Mux(io.lsu.req.fire , VecInit(io.lsu.req.bits.map(_.bits)),
Mux(wb_fire , wb_req,
Mux(prober_fire , prober_req,
Mux(prefetch_fire , prefetch_req,
Mux(mshrs.io.meta_read.fire, mshr_read_req
, replay_req)))))
val s0_type = Mux(io.lsu.req.fire , t_lsu,
Mux(wb_fire , t_wb,
Mux(prober_fire , t_probe,
Mux(prefetch_fire , t_prefetch,
Mux(mshrs.io.meta_read.fire, t_mshr_meta_read
, t_replay)))))
// Does this request need to send a response or nack
val s0_send_resp_or_nack = Mux(io.lsu.req.fire, s0_valid,
VecInit(Mux(mshrs.io.replay.fire && isRead(mshrs.io.replay.bits.uop.mem_cmd), 1.U(memWidth.W), 0.U(memWidth.W)).asBools))
val s1_req = RegNext(s0_req)
for (w <- 0 until memWidth)
s1_req(w).uop.br_mask := GetNewBrMask(io.lsu.brupdate, s0_req(w).uop)
val s2_store_failed = Wire(Bool())
val s1_valid = widthMap(w =>
RegNext(s0_valid(w) &&
!IsKilledByBranch(io.lsu.brupdate, s0_req(w).uop) &&
!(io.lsu.exception && s0_req(w).uop.uses_ldq) &&
!(s2_store_failed && io.lsu.req.fire && s0_req(w).uop.uses_stq),
init=false.B))
for (w <- 0 until memWidth)
assert(!(io.lsu.s1_kill(w) && !RegNext(io.lsu.req.fire) && !RegNext(io.lsu.req.bits(w).valid)))
val s1_addr = s1_req.map(_.addr)
val s1_nack = s1_addr.map(a => a(idxMSB,idxLSB) === prober.io.meta_write.bits.idx && !prober.io.req.ready)
val s1_send_resp_or_nack = RegNext(s0_send_resp_or_nack)
val s1_type = RegNext(s0_type)
val s1_mshr_meta_read_way_en = RegNext(mshrs.io.meta_read.bits.way_en)
val s1_replay_way_en = RegNext(mshrs.io.replay.bits.way_en) // For replays, the metadata isn't written yet
val s1_wb_way_en = RegNext(wb.io.data_req.bits.way_en)
// tag check
def wayMap[T <: Data](f: Int => T) = VecInit((0 until nWays).map(f))
val s1_tag_eq_way = widthMap(i => wayMap((w: Int) => meta(i).io.resp(w).tag === (s1_addr(i) >> untagBits)).asUInt)
val s1_tag_match_way = widthMap(i =>
Mux(s1_type === t_replay, s1_replay_way_en,
Mux(s1_type === t_wb, s1_wb_way_en,
Mux(s1_type === t_mshr_meta_read, s1_mshr_meta_read_way_en,
wayMap((w: Int) => s1_tag_eq_way(i)(w) && meta(i).io.resp(w).coh.isValid()).asUInt))))
val s1_wb_idx_matches = widthMap(i => (s1_addr(i)(untagBits-1,blockOffBits) === wb.io.idx.bits) && wb.io.idx.valid)
val s2_req = RegNext(s1_req)
val s2_type = RegNext(s1_type)
val s2_valid = widthMap(w =>
RegNext(s1_valid(w) &&
!io.lsu.s1_kill(w) &&
!IsKilledByBranch(io.lsu.brupdate, s1_req(w).uop) &&
!(io.lsu.exception && s1_req(w).uop.uses_ldq) &&
!(s2_store_failed && (s1_type === t_lsu) && s1_req(w).uop.uses_stq)))
for (w <- 0 until memWidth)
s2_req(w).uop.br_mask := GetNewBrMask(io.lsu.brupdate, s1_req(w).uop)
val s2_tag_match_way = RegNext(s1_tag_match_way)
val s2_tag_match = s2_tag_match_way.map(_.orR)
val s2_hit_state = widthMap(i => Mux1H(s2_tag_match_way(i), wayMap((w: Int) => RegNext(meta(i).io.resp(w).coh))))
val s2_has_permission = widthMap(w => s2_hit_state(w).onAccess(s2_req(w).uop.mem_cmd)._1)
val s2_new_hit_state = widthMap(w => s2_hit_state(w).onAccess(s2_req(w).uop.mem_cmd)._3)
val s2_hit = widthMap(w => (s2_tag_match(w) && s2_has_permission(w) && s2_hit_state(w) === s2_new_hit_state(w) && !mshrs.io.block_hit(w)) || s2_type.isOneOf(t_replay, t_wb))
val s2_nack = Wire(Vec(memWidth, Bool()))
assert(!(s2_type === t_replay && !s2_hit(0)), "Replays should always hit")
assert(!(s2_type === t_wb && !s2_hit(0)), "Writeback should always see data hit")
val s2_wb_idx_matches = RegNext(s1_wb_idx_matches)
// lr/sc
val debug_sc_fail_addr = RegInit(0.U)
val debug_sc_fail_cnt = RegInit(0.U(8.W))
val lrsc_count = RegInit(0.U(log2Ceil(lrscCycles).W))
val lrsc_valid = lrsc_count > lrscBackoff.U
val lrsc_addr = Reg(UInt())
val s2_lr = s2_req(0).uop.mem_cmd === M_XLR && (!RegNext(s1_nack(0)) || s2_type === t_replay)
val s2_sc = s2_req(0).uop.mem_cmd === M_XSC && (!RegNext(s1_nack(0)) || s2_type === t_replay)
val s2_lrsc_addr_match = widthMap(w => lrsc_valid && lrsc_addr === (s2_req(w).addr >> blockOffBits))
val s2_sc_fail = s2_sc && !s2_lrsc_addr_match(0)
when (lrsc_count > 0.U) { lrsc_count := lrsc_count - 1.U }
when (s2_valid(0) && ((s2_type === t_lsu && s2_hit(0) && !s2_nack(0)) ||
(s2_type === t_replay && s2_req(0).uop.mem_cmd =/= M_FLUSH_ALL))) {
when (s2_lr) {
lrsc_count := (lrscCycles - 1).U
lrsc_addr := s2_req(0).addr >> blockOffBits
}
when (lrsc_count > 0.U) {
lrsc_count := 0.U
}
}
for (w <- 0 until memWidth) {
when (s2_valid(w) &&
s2_type === t_lsu &&
!s2_hit(w) &&
!(s2_has_permission(w) && s2_tag_match(w)) &&
s2_lrsc_addr_match(w) &&
!s2_nack(w)) {
lrsc_count := 0.U
}
}
when (s2_valid(0)) {
when (s2_req(0).addr === debug_sc_fail_addr) {
when (s2_sc_fail) {
debug_sc_fail_cnt := debug_sc_fail_cnt + 1.U
} .elsewhen (s2_sc) {
debug_sc_fail_cnt := 0.U
}
} .otherwise {
when (s2_sc_fail) {
debug_sc_fail_addr := s2_req(0).addr
debug_sc_fail_cnt := 1.U
}
}
}
assert(debug_sc_fail_cnt < 100.U, "L1DCache failed too many SCs in a row")
val s2_data = Wire(Vec(memWidth, Vec(nWays, UInt(encRowBits.W))))
for (i <- 0 until memWidth) {
for (w <- 0 until nWays) {
s2_data(i)(w) := data.io.resp(i)(w)
}
}
val s2_data_muxed = widthMap(w => Mux1H(s2_tag_match_way(w), s2_data(w)))
val s2_word_idx = widthMap(w => if (rowWords == 1) 0.U else s2_req(w).addr(log2Up(rowWords*wordBytes)-1, log2Up(wordBytes)))
// replacement policy
val replacer = cacheParams.replacement
val s1_replaced_way_en = UIntToOH(replacer.way)
val s2_replaced_way_en = UIntToOH(RegNext(replacer.way))
val s2_repl_meta = widthMap(i => Mux1H(s2_replaced_way_en, wayMap((w: Int) => RegNext(meta(i).io.resp(w))).toSeq))
// nack because of incoming probe
val s2_nack_hit = RegNext(VecInit(s1_nack))
// Nack when we hit something currently being evicted
val s2_nack_victim = widthMap(w => s2_valid(w) && s2_hit(w) && mshrs.io.secondary_miss(w))
// MSHRs not ready for request
val s2_nack_miss = widthMap(w => s2_valid(w) && !s2_hit(w) && !mshrs.io.req(w).ready)
// Bank conflict on data arrays
val s2_nack_data = widthMap(w => data.io.nacks(w))
// Can't allocate MSHR for same set currently being written back
val s2_nack_wb = widthMap(w => s2_valid(w) && !s2_hit(w) && s2_wb_idx_matches(w))
s2_nack := widthMap(w => (s2_nack_miss(w) || s2_nack_hit(w) || s2_nack_victim(w) || s2_nack_data(w) || s2_nack_wb(w)) && s2_type =/= t_replay)
val s2_send_resp = widthMap(w => (RegNext(s1_send_resp_or_nack(w)) && !s2_nack(w) &&
(s2_hit(w) || (mshrs.io.req(w).fire && isWrite(s2_req(w).uop.mem_cmd) && !isRead(s2_req(w).uop.mem_cmd)))))
val s2_send_nack = widthMap(w => (RegNext(s1_send_resp_or_nack(w)) && s2_nack(w)))
for (w <- 0 until memWidth)
assert(!(s2_send_resp(w) && s2_send_nack(w)))
// hits always send a response
// If MSHR is not available, LSU has to replay this request later
// If MSHR is available and this is only a store(not a amo), we don't need to wait for resp later
s2_store_failed := s2_valid(0) && s2_nack(0) && s2_send_nack(0) && s2_req(0).uop.uses_stq
// Miss handling
for (w <- 0 until memWidth) {
mshrs.io.req(w).valid := s2_valid(w) &&
!s2_hit(w) &&
!s2_nack_hit(w) &&
!s2_nack_victim(w) &&
!s2_nack_data(w) &&
!s2_nack_wb(w) &&
s2_type.isOneOf(t_lsu, t_prefetch) &&
!IsKilledByBranch(io.lsu.brupdate, s2_req(w).uop) &&
!(io.lsu.exception && s2_req(w).uop.uses_ldq) &&
(isPrefetch(s2_req(w).uop.mem_cmd) ||
isRead(s2_req(w).uop.mem_cmd) ||
isWrite(s2_req(w).uop.mem_cmd))
assert(!(mshrs.io.req(w).valid && s2_type === t_replay), "Replays should not need to go back into MSHRs")
mshrs.io.req(w).bits := DontCare
mshrs.io.req(w).bits.uop := s2_req(w).uop
mshrs.io.req(w).bits.uop.br_mask := GetNewBrMask(io.lsu.brupdate, s2_req(w).uop)
mshrs.io.req(w).bits.addr := s2_req(w).addr
mshrs.io.req(w).bits.tag_match := s2_tag_match(w)
mshrs.io.req(w).bits.old_meta := Mux(s2_tag_match(w), L1Metadata(s2_repl_meta(w).tag, s2_hit_state(w)), s2_repl_meta(w))
mshrs.io.req(w).bits.way_en := Mux(s2_tag_match(w), s2_tag_match_way(w), s2_replaced_way_en)
mshrs.io.req(w).bits.data := s2_req(w).data
mshrs.io.req(w).bits.is_hella := s2_req(w).is_hella
mshrs.io.req_is_probe(w) := s2_type === t_probe && s2_valid(w)
}
mshrs.io.meta_resp.valid := !s2_nack_hit(0) || prober.io.mshr_wb_rdy
mshrs.io.meta_resp.bits := Mux1H(s2_tag_match_way(0), RegNext(meta(0).io.resp))
when (mshrs.io.req.map(_.fire).reduce(_||_)) { replacer.miss }
tl_out.a <> mshrs.io.mem_acquire
// probes and releases
prober.io.req.valid := tl_out.b.valid && !lrsc_valid
tl_out.b.ready := prober.io.req.ready && !lrsc_valid
prober.io.req.bits := tl_out.b.bits
prober.io.way_en := s2_tag_match_way(0)
prober.io.block_state := s2_hit_state(0)
metaWriteArb.io.in(1) <> prober.io.meta_write
prober.io.mshr_rdy := mshrs.io.probe_rdy
prober.io.wb_rdy := (prober.io.meta_write.bits.idx =/= wb.io.idx.bits) || !wb.io.idx.valid
mshrs.io.prober_state := prober.io.state
// refills
when (tl_out.d.bits.source === cfg.nMSHRs.U) {
// This should be ReleaseAck
tl_out.d.ready := true.B
mshrs.io.mem_grant.valid := false.B
mshrs.io.mem_grant.bits := DontCare
} .otherwise {
// This should be GrantData
mshrs.io.mem_grant <> tl_out.d
}
dataWriteArb.io.in(1) <> mshrs.io.refill
metaWriteArb.io.in(0) <> mshrs.io.meta_write
tl_out.e <> mshrs.io.mem_finish
// writebacks
val wbArb = Module(new Arbiter(new WritebackReq(edge.bundle), 2))
// 0 goes to prober, 1 goes to MSHR evictions
wbArb.io.in(0) <> prober.io.wb_req
wbArb.io.in(1) <> mshrs.io.wb_req
wb.io.req <> wbArb.io.out
wb.io.data_resp := s2_data_muxed(0)
mshrs.io.wb_resp := wb.io.resp
wb.io.mem_grant := tl_out.d.fire && tl_out.d.bits.source === cfg.nMSHRs.U
val lsu_release_arb = Module(new Arbiter(new TLBundleC(edge.bundle), 2))
io.lsu.release <> lsu_release_arb.io.out
lsu_release_arb.io.in(0) <> wb.io.lsu_release
lsu_release_arb.io.in(1) <> prober.io.lsu_release
TLArbiter.lowest(edge, tl_out.c, wb.io.release, prober.io.rep)
io.lsu.perf.release := edge.done(tl_out.c)
io.lsu.perf.acquire := edge.done(tl_out.a)
// load data gen
val s2_data_word_prebypass = widthMap(w => s2_data_muxed(w) >> Cat(s2_word_idx(w), 0.U(log2Ceil(coreDataBits).W)))
val s2_data_word = Wire(Vec(memWidth, UInt()))
val loadgen = (0 until memWidth).map { w =>
new LoadGen(s2_req(w).uop.mem_size, s2_req(w).uop.mem_signed, s2_req(w).addr,
s2_data_word(w), s2_sc && (w == 0).B, wordBytes)
}
// Mux between cache responses and uncache responses
val cache_resp = Wire(Vec(memWidth, Valid(new BoomDCacheResp)))
for (w <- 0 until memWidth) {
cache_resp(w).valid := s2_valid(w) && s2_send_resp(w)
cache_resp(w).bits.uop := s2_req(w).uop
cache_resp(w).bits.data := loadgen(w).data | s2_sc_fail
cache_resp(w).bits.is_hella := s2_req(w).is_hella
}
val uncache_resp = Wire(Valid(new BoomDCacheResp))
uncache_resp.bits := mshrs.io.resp.bits
uncache_resp.valid := mshrs.io.resp.valid
mshrs.io.resp.ready := !(cache_resp.map(_.valid).reduce(_&&_)) // We can backpressure the MSHRs, but not cache hits
val resp = WireInit(cache_resp)
var uncache_responding = false.B
for (w <- 0 until memWidth) {
val uncache_respond = !cache_resp(w).valid && !uncache_responding
when (uncache_respond) {
resp(w) := uncache_resp
}
uncache_responding = uncache_responding || uncache_respond
}
for (w <- 0 until memWidth) {
io.lsu.resp(w).valid := resp(w).valid &&
!(io.lsu.exception && resp(w).bits.uop.uses_ldq) &&
!IsKilledByBranch(io.lsu.brupdate, resp(w).bits.uop)
io.lsu.resp(w).bits := UpdateBrMask(io.lsu.brupdate, resp(w).bits)
io.lsu.nack(w).valid := s2_valid(w) && s2_send_nack(w) &&
!(io.lsu.exception && s2_req(w).uop.uses_ldq) &&
!IsKilledByBranch(io.lsu.brupdate, s2_req(w).uop)
io.lsu.nack(w).bits := UpdateBrMask(io.lsu.brupdate, s2_req(w))
assert(!(io.lsu.nack(w).valid && s2_type =/= t_lsu))
}
// Store/amo hits
val s3_req = RegNext(s2_req(0))
val s3_valid = RegNext(s2_valid(0) && s2_hit(0) && isWrite(s2_req(0).uop.mem_cmd) &&
!s2_sc_fail && !(s2_send_nack(0) && s2_nack(0)))
for (w <- 1 until memWidth) {
assert(!(s2_valid(w) && s2_hit(w) && isWrite(s2_req(w).uop.mem_cmd) &&
!s2_sc_fail && !(s2_send_nack(w) && s2_nack(w))),
"Store must go through 0th pipe in L1D")
}
// For bypassing
val s4_req = RegNext(s3_req)
val s4_valid = RegNext(s3_valid)
val s5_req = RegNext(s4_req)
val s5_valid = RegNext(s4_valid)
val s3_bypass = widthMap(w => s3_valid && ((s2_req(w).addr >> wordOffBits) === (s3_req.addr >> wordOffBits)))
val s4_bypass = widthMap(w => s4_valid && ((s2_req(w).addr >> wordOffBits) === (s4_req.addr >> wordOffBits)))
val s5_bypass = widthMap(w => s5_valid && ((s2_req(w).addr >> wordOffBits) === (s5_req.addr >> wordOffBits)))
// Store -> Load bypassing
for (w <- 0 until memWidth) {
s2_data_word(w) := Mux(s3_bypass(w), s3_req.data,
Mux(s4_bypass(w), s4_req.data,
Mux(s5_bypass(w), s5_req.data,
s2_data_word_prebypass(w))))
}
val amoalu = Module(new AMOALU(xLen))
amoalu.io.mask := new StoreGen(s2_req(0).uop.mem_size, s2_req(0).addr, 0.U, xLen/8).mask
amoalu.io.cmd := s2_req(0).uop.mem_cmd
amoalu.io.lhs := s2_data_word(0)
amoalu.io.rhs := s2_req(0).data
s3_req.data := amoalu.io.out
val s3_way = RegNext(s2_tag_match_way(0))
dataWriteArb.io.in(0).valid := s3_valid
dataWriteArb.io.in(0).bits.addr := s3_req.addr
dataWriteArb.io.in(0).bits.wmask := UIntToOH(s3_req.addr.extract(rowOffBits-1,offsetlsb))
dataWriteArb.io.in(0).bits.data := Fill(rowWords, s3_req.data)
dataWriteArb.io.in(0).bits.way_en := s3_way
io.lsu.ordered := mshrs.io.fence_rdy && !s1_valid.reduce(_||_) && !s2_valid.reduce(_||_)
} | module BoomProbeUnit(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [1:0] io_req_bits_param,
input [3:0] io_req_bits_size,
input [1:0] io_req_bits_source,
input [31:0] io_req_bits_address,
input io_rep_ready,
output io_rep_valid,
output [2:0] io_rep_bits_param,
output [3:0] io_rep_bits_size,
output [1:0] io_rep_bits_source,
output [31:0] io_rep_bits_address,
input io_meta_read_ready,
output io_meta_read_valid,
output [5:0] io_meta_read_bits_idx,
output [19:0] io_meta_read_bits_tag,
input io_meta_write_ready,
output io_meta_write_valid,
output [5:0] io_meta_write_bits_idx,
output [3:0] io_meta_write_bits_way_en,
output [1:0] io_meta_write_bits_data_coh_state,
output [19:0] io_meta_write_bits_data_tag,
input io_wb_req_ready,
output io_wb_req_valid,
output [19:0] io_wb_req_bits_tag,
output [5:0] io_wb_req_bits_idx,
output [2:0] io_wb_req_bits_param,
output [3:0] io_wb_req_bits_way_en,
input [3:0] io_way_en,
input io_wb_rdy,
input io_mshr_rdy,
output io_mshr_wb_rdy,
input [1:0] io_block_state_state,
input io_lsu_release_ready,
output io_lsu_release_valid,
output [31:0] io_lsu_release_bits_address,
output io_state_valid,
output [39:0] io_state_bits
);
reg [3:0] state;
reg [1:0] req_param;
reg [3:0] req_size;
reg [1:0] req_source;
reg [31:0] req_address;
reg [3:0] way_en;
reg [1:0] old_coh_state;
wire [3:0] _r_T = {req_param, (|way_en) ? old_coh_state : 2'h0};
wire _r_T_26 = _r_T == 4'hB;
wire _r_T_29 = _r_T == 4'h4;
wire _r_T_33 = _r_T == 4'h5;
wire _r_T_37 = _r_T == 4'h6;
wire _r_T_41 = _r_T == 4'h7;
wire _r_T_45 = _r_T == 4'h0;
wire _r_T_49 = _r_T == 4'h1;
wire _r_T_53 = _r_T == 4'h2;
wire _r_T_57 = _r_T == 4'h3;
wire _GEN = _r_T_57 | _r_T_53;
wire [2:0] report_param = _GEN ? 3'h3 : _r_T_49 ? 3'h4 : _r_T_45 ? 3'h5 : _r_T_41 | _r_T_37 ? 3'h0 : _r_T_33 ? 3'h4 : _r_T_29 ? 3'h5 : _r_T_26 | _r_T == 4'hA ? 3'h1 : _r_T == 4'h9 ? 3'h2 : _r_T == 4'h8 ? 3'h5 : 3'h0;
wire io_req_ready_0 = state == 4'h0;
wire io_rep_valid_0 = state == 4'h6;
wire io_meta_read_valid_0 = state == 4'h1;
wire io_meta_write_valid_0 = state == 4'h9;
wire io_wb_req_valid_0 = state == 4'h7;
wire io_lsu_release_valid_0 = state == 4'h5;
wire _GEN_0 = io_req_ready_0 & io_req_valid;
wire [15:0][3:0] _GEN_1 = {{state}, {state}, {state}, {state}, {state}, {4'h0}, {io_meta_write_ready & io_meta_write_valid_0 ? 4'hA : state}, {io_wb_req_ready ? 4'h9 : state}, {io_wb_req_ready & io_wb_req_valid_0 ? 4'h8 : state}, {io_rep_ready ? ((|way_en) ? 4'h9 : 4'h0) : state}, {io_lsu_release_ready & io_lsu_release_valid_0 ? 4'h6 : state}, {{2'h1, (|way_en) & (_r_T_57 | ~(_r_T_53 | _r_T_49 | _r_T_45) & (_r_T_41 | ~(_r_T_37 | _r_T_33 | _r_T_29) & _r_T_26)), 1'h1}}, {io_mshr_rdy & io_wb_rdy ? 4'h4 : 4'h1}, {4'h3}, {io_meta_read_ready & io_meta_read_valid_0 ? 4'h2 : state}, {_GEN_0 ? 4'h1 : state}};
always @(posedge clock) begin
if (reset)
state <= 4'h0;
else
state <= _GEN_1[state];
if (_GEN_0) begin
req_param <= io_req_bits_param;
req_size <= io_req_bits_size;
req_source <= io_req_bits_source;
req_address <= io_req_bits_address;
end
if (io_req_ready_0 | io_meta_read_valid_0 | state == 4'h2 | state != 4'h3) begin
end
else begin
way_en <= io_way_en;
old_coh_state <= io_block_state_state;
end
end
assign io_req_ready = io_req_ready_0;
assign io_rep_valid = io_rep_valid_0;
assign io_rep_bits_param = report_param;
assign io_rep_bits_size = req_size;
assign io_rep_bits_source = req_source;
assign io_rep_bits_address = req_address;
assign io_meta_read_valid = io_meta_read_valid_0;
assign io_meta_read_bits_idx = req_address[11:6];
assign io_meta_read_bits_tag = req_address[31:12];
assign io_meta_write_valid = io_meta_write_valid_0;
assign io_meta_write_bits_idx = req_address[11:6];
assign io_meta_write_bits_way_en = way_en;
assign io_meta_write_bits_data_coh_state = _GEN ? 2'h2 : _r_T_49 ? 2'h1 : _r_T_45 ? 2'h0 : {1'h0, _r_T_41 | _r_T_37 | _r_T_33};
assign io_meta_write_bits_data_tag = req_address[31:12];
assign io_wb_req_valid = io_wb_req_valid_0;
assign io_wb_req_bits_tag = req_address[31:12];
assign io_wb_req_bits_idx = req_address[11:6];
assign io_wb_req_bits_param = report_param;
assign io_wb_req_bits_way_en = way_en;
assign io_mshr_wb_rdy = ~(io_rep_valid_0 | io_wb_req_valid_0 | state == 4'h8 | io_meta_write_valid_0 | state == 4'hA);
assign io_lsu_release_valid = io_lsu_release_valid_0;
assign io_lsu_release_bits_address = req_address;
assign io_state_valid = |state;
assign io_state_bits = {8'h0, req_address};
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(t))
val out = Decoupled(new Flit(flitWidth))
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))
data(0) := DontCare // unused, DCE this
}
}
io.busy := io.out.valid
}
class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(t)
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits := (if (dataBeats == 1) {
io.in.bits.flit.asTypeOf(t)
} else {
Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)
})
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit
}
}
}
io.busy := beat =/= 0.U
}
class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Phit(phitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail
}
}
}
object FlitToPhit {
def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {
val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))
flit2phit.io.in <> flit
flit2phit.io.out
}
}
class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Decoupled(new Flit(flitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat) := io.in.bits.phit
}
}
}
}
object PhitToFlit {
def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in <> phit
phit2flit.io.out
}
def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in.valid := phit.valid
phit2flit.io.in.bits := phit.bits
when (phit.valid) { assert(phit2flit.io.in.ready) }
val out = Wire(Valid(new Flit(flitWidth)))
out.valid := phit2flit.io.out.valid
out.bits := phit2flit.io.out.bits
phit2flit.io.out.ready := true.B
out
}
}
class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))
val out = Decoupled(new Phit(phitWidth))
})
if (channels == 1) {
io.out <> io.in(0)
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val chosen_reg = Reg(UInt(headerWidth.W))
val chosen_prio = PriorityEncoder(io.in.map(_.valid))
val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.out.valid := VecInit(io.in.map(_.valid))(chosen)
io.out.bits.phit := Mux(beat < headerBeats.U,
chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),
VecInit(io.in.map(_.bits.phit))(chosen))
for (i <- 0 until channels) {
io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U
}
when (io.out.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) { chosen_reg := chosen_prio }
}
}
}
class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Vec(channels, Decoupled(new Phit(phitWidth)))
})
if (channels == 1) {
io.out(0) <> io.in
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))
val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)
for (c <- 0 until channels) {
io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U
io.out(c).bits.phit := io.in.bits.phit
}
when (io.in.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat < headerBeats.U) {
channel_vec(header_idx) := io.in.bits.phit
}
}
}
}
class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Flipped(Decoupled(new Flit(flitWidth)))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = io.out.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)
}
io.out.valid := io.in.valid && credits < bufferSz.U
io.out.bits.flit := io.in.bits.flit
io.in.ready := io.out.ready && credits < bufferSz.U
io.credit.ready := true.B
}
class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Decoupled(new Flit(flitWidth))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = buffer.io.deq.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credit_incr + Mux(credit_decr, 0.U, credits)
}
buffer.io.enq.valid := io.in.valid
buffer.io.enq.bits := io.in.bits
io.in.ready := true.B
when (io.in.valid) { assert(buffer.io.enq.ready) }
io.out <> buffer.io.deq
io.credit.valid := credits =/= 0.U
io.credit.bits.flit := credits - 1.U
} | module GenericDeserializer_TLBeatw10_f32(
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits_flit,
input io_out_ready,
output io_out_valid,
output io_out_bits_head,
output io_out_bits_tail
);
assign io_in_ready = io_out_ready;
assign io_out_valid = io_in_valid;
assign io_out_bits_head = io_in_bits_flit[1];
assign io_out_bits_tail = io_in_bits_flit[0];
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Fetch Target Queue (FTQ)
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Each entry in the FTQ holds the fetch address and branch prediction snapshot state.
//
// TODO:
// * reduce port counts.
package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.util.{Str}
import boom.v3.common._
import boom.v3.exu._
import boom.v3.util._
/**
* FTQ Parameters used in configurations
*
* @param nEntries # of entries in the FTQ
*/
case class FtqParameters(
nEntries: Int = 16
)
/**
* Bundle to add to the FTQ RAM and to be used as the pass in IO
*/
class FTQBundle(implicit p: Parameters) extends BoomBundle
with HasBoomFrontendParameters
{
// // TODO compress out high-order bits
// val fetch_pc = UInt(vaddrBitsExtended.W)
// IDX of instruction that was predicted taken, if any
val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W))
// Was the CFI in this bundle found to be taken? or not
val cfi_taken = Bool()
// Was this CFI mispredicted by the branch prediction pipeline?
val cfi_mispredicted = Bool()
// What type of CFI was taken out of this bundle
val cfi_type = UInt(CFI_SZ.W)
// mask of branches which were visible in this fetch bundle
val br_mask = UInt(fetchWidth.W)
// This CFI is likely a CALL
val cfi_is_call = Bool()
// This CFI is likely a RET
val cfi_is_ret = Bool()
// Is the NPC after the CFI +4 or +2
val cfi_npc_plus4 = Bool()
// What was the top of the RAS that this bundle saw?
val ras_top = UInt(vaddrBitsExtended.W)
val ras_idx = UInt(log2Ceil(nRasEntries).W)
// Which bank did this start from?
val start_bank = UInt(1.W)
// // Metadata for the branch predictor
// val bpd_meta = Vec(nBanks, UInt(bpdMaxMetaLength.W))
}
/**
* IO to provide a port for a FunctionalUnit to get the PC of an instruction.
* And for JALRs, the PC of the next instruction.
*/
class GetPCFromFtqIO(implicit p: Parameters) extends BoomBundle
{
val ftq_idx = Input(UInt(log2Ceil(ftqSz).W))
val entry = Output(new FTQBundle)
val ghist = Output(new GlobalHistory)
val pc = Output(UInt(vaddrBitsExtended.W))
val com_pc = Output(UInt(vaddrBitsExtended.W))
// the next_pc may not be valid (stalled or still being fetched)
val next_val = Output(Bool())
val next_pc = Output(UInt(vaddrBitsExtended.W))
}
/**
* Queue to store the fetch PC and other relevant branch predictor signals that are inflight in the
* processor.
*
* @param num_entries # of entries in the FTQ
*/
class FetchTargetQueue(implicit p: Parameters) extends BoomModule
with HasBoomCoreParameters
with HasBoomFrontendParameters
{
val num_entries = ftqSz
private val idx_sz = log2Ceil(num_entries)
val io = IO(new BoomBundle {
// Enqueue one entry for every fetch cycle.
val enq = Flipped(Decoupled(new FetchBundle()))
// Pass to FetchBuffer (newly fetched instructions).
val enq_idx = Output(UInt(idx_sz.W))
// ROB tells us the youngest committed ftq_idx to remove from FTQ.
val deq = Flipped(Valid(UInt(idx_sz.W)))
// Give PC info to BranchUnit.
val get_ftq_pc = Vec(2, new GetPCFromFtqIO())
// Used to regenerate PC for trace port stuff in FireSim
// Don't tape this out, this blows up the FTQ
val debug_ftq_idx = Input(Vec(coreWidth, UInt(log2Ceil(ftqSz).W)))
val debug_fetch_pc = Output(Vec(coreWidth, UInt(vaddrBitsExtended.W)))
val redirect = Input(Valid(UInt(idx_sz.W)))
val brupdate = Input(new BrUpdateInfo)
val bpdupdate = Output(Valid(new BranchPredictionUpdate))
val ras_update = Output(Bool())
val ras_update_idx = Output(UInt(log2Ceil(nRasEntries).W))
val ras_update_pc = Output(UInt(vaddrBitsExtended.W))
})
val bpd_ptr = RegInit(0.U(idx_sz.W))
val deq_ptr = RegInit(0.U(idx_sz.W))
val enq_ptr = RegInit(1.U(idx_sz.W))
val full = ((WrapInc(WrapInc(enq_ptr, num_entries), num_entries) === bpd_ptr) ||
(WrapInc(enq_ptr, num_entries) === bpd_ptr))
val pcs = Reg(Vec(num_entries, UInt(vaddrBitsExtended.W)))
val meta = SyncReadMem(num_entries, Vec(nBanks, UInt(bpdMaxMetaLength.W)))
val ram = Reg(Vec(num_entries, new FTQBundle))
val ghist = Seq.fill(2) { SyncReadMem(num_entries, new GlobalHistory) }
val lhist = if (useLHist) {
Some(SyncReadMem(num_entries, Vec(nBanks, UInt(localHistoryLength.W))))
} else {
None
}
val do_enq = io.enq.fire
// This register lets us initialize the ghist to 0
val prev_ghist = RegInit((0.U).asTypeOf(new GlobalHistory))
val prev_entry = RegInit((0.U).asTypeOf(new FTQBundle))
val prev_pc = RegInit(0.U(vaddrBitsExtended.W))
when (do_enq) {
pcs(enq_ptr) := io.enq.bits.pc
val new_entry = Wire(new FTQBundle)
new_entry.cfi_idx := io.enq.bits.cfi_idx
// Initially, if we see a CFI, it is assumed to be taken.
// Branch resolutions may change this
new_entry.cfi_taken := io.enq.bits.cfi_idx.valid
new_entry.cfi_mispredicted := false.B
new_entry.cfi_type := io.enq.bits.cfi_type
new_entry.cfi_is_call := io.enq.bits.cfi_is_call
new_entry.cfi_is_ret := io.enq.bits.cfi_is_ret
new_entry.cfi_npc_plus4 := io.enq.bits.cfi_npc_plus4
new_entry.ras_top := io.enq.bits.ras_top
new_entry.ras_idx := io.enq.bits.ghist.ras_idx
new_entry.br_mask := io.enq.bits.br_mask & io.enq.bits.mask
new_entry.start_bank := bank(io.enq.bits.pc)
val new_ghist = Mux(io.enq.bits.ghist.current_saw_branch_not_taken,
io.enq.bits.ghist,
prev_ghist.update(
prev_entry.br_mask,
prev_entry.cfi_taken,
prev_entry.br_mask(prev_entry.cfi_idx.bits),
prev_entry.cfi_idx.bits,
prev_entry.cfi_idx.valid,
prev_pc,
prev_entry.cfi_is_call,
prev_entry.cfi_is_ret
)
)
lhist.map( l => l.write(enq_ptr, io.enq.bits.lhist))
ghist.map( g => g.write(enq_ptr, new_ghist))
meta.write(enq_ptr, io.enq.bits.bpd_meta)
ram(enq_ptr) := new_entry
prev_pc := io.enq.bits.pc
prev_entry := new_entry
prev_ghist := new_ghist
enq_ptr := WrapInc(enq_ptr, num_entries)
}
io.enq_idx := enq_ptr
io.bpdupdate.valid := false.B
io.bpdupdate.bits := DontCare
when (io.deq.valid) {
deq_ptr := io.deq.bits
}
// This register avoids a spurious bpd update on the first fetch packet
val first_empty = RegInit(true.B)
// We can update the branch predictors when we know the target of the
// CFI in this fetch bundle
val ras_update = WireInit(false.B)
val ras_update_pc = WireInit(0.U(vaddrBitsExtended.W))
val ras_update_idx = WireInit(0.U(log2Ceil(nRasEntries).W))
io.ras_update := RegNext(ras_update)
io.ras_update_pc := RegNext(ras_update_pc)
io.ras_update_idx := RegNext(ras_update_idx)
val bpd_update_mispredict = RegInit(false.B)
val bpd_update_repair = RegInit(false.B)
val bpd_repair_idx = Reg(UInt(log2Ceil(ftqSz).W))
val bpd_end_idx = Reg(UInt(log2Ceil(ftqSz).W))
val bpd_repair_pc = Reg(UInt(vaddrBitsExtended.W))
val bpd_idx = Mux(io.redirect.valid, io.redirect.bits,
Mux(bpd_update_repair || bpd_update_mispredict, bpd_repair_idx, bpd_ptr))
val bpd_entry = RegNext(ram(bpd_idx))
val bpd_ghist = ghist(0).read(bpd_idx, true.B)
val bpd_lhist = if (useLHist) {
lhist.get.read(bpd_idx, true.B)
} else {
VecInit(Seq.fill(nBanks) { 0.U })
}
val bpd_meta = meta.read(bpd_idx, true.B) // TODO fix these SRAMs
val bpd_pc = RegNext(pcs(bpd_idx))
val bpd_target = RegNext(pcs(WrapInc(bpd_idx, num_entries)))
when (io.redirect.valid) {
bpd_update_mispredict := false.B
bpd_update_repair := false.B
} .elsewhen (RegNext(io.brupdate.b2.mispredict)) {
bpd_update_mispredict := true.B
bpd_repair_idx := RegNext(io.brupdate.b2.uop.ftq_idx)
bpd_end_idx := RegNext(enq_ptr)
} .elsewhen (bpd_update_mispredict) {
bpd_update_mispredict := false.B
bpd_update_repair := true.B
bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)
} .elsewhen (bpd_update_repair && RegNext(bpd_update_mispredict)) {
bpd_repair_pc := bpd_pc
bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)
} .elsewhen (bpd_update_repair) {
bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)
when (WrapInc(bpd_repair_idx, num_entries) === bpd_end_idx ||
bpd_pc === bpd_repair_pc) {
bpd_update_repair := false.B
}
}
val do_commit_update = (!bpd_update_mispredict &&
!bpd_update_repair &&
bpd_ptr =/= deq_ptr &&
enq_ptr =/= WrapInc(bpd_ptr, num_entries) &&
!io.brupdate.b2.mispredict &&
!io.redirect.valid && !RegNext(io.redirect.valid))
val do_mispredict_update = bpd_update_mispredict
val do_repair_update = bpd_update_repair
when (RegNext(do_commit_update || do_repair_update || do_mispredict_update)) {
val cfi_idx = bpd_entry.cfi_idx.bits
val valid_repair = bpd_pc =/= bpd_repair_pc
io.bpdupdate.valid := (!first_empty &&
(bpd_entry.cfi_idx.valid || bpd_entry.br_mask =/= 0.U) &&
!(RegNext(do_repair_update) && !valid_repair))
io.bpdupdate.bits.is_mispredict_update := RegNext(do_mispredict_update)
io.bpdupdate.bits.is_repair_update := RegNext(do_repair_update)
io.bpdupdate.bits.pc := bpd_pc
io.bpdupdate.bits.btb_mispredicts := 0.U
io.bpdupdate.bits.br_mask := Mux(bpd_entry.cfi_idx.valid,
MaskLower(UIntToOH(cfi_idx)) & bpd_entry.br_mask, bpd_entry.br_mask)
io.bpdupdate.bits.cfi_idx := bpd_entry.cfi_idx
io.bpdupdate.bits.cfi_mispredicted := bpd_entry.cfi_mispredicted
io.bpdupdate.bits.cfi_taken := bpd_entry.cfi_taken
io.bpdupdate.bits.target := bpd_target
io.bpdupdate.bits.cfi_is_br := bpd_entry.br_mask(cfi_idx)
io.bpdupdate.bits.cfi_is_jal := bpd_entry.cfi_type === CFI_JAL || bpd_entry.cfi_type === CFI_JALR
io.bpdupdate.bits.ghist := bpd_ghist
io.bpdupdate.bits.lhist := bpd_lhist
io.bpdupdate.bits.meta := bpd_meta
first_empty := false.B
}
when (do_commit_update) {
bpd_ptr := WrapInc(bpd_ptr, num_entries)
}
io.enq.ready := RegNext(!full || do_commit_update)
val redirect_idx = io.redirect.bits
val redirect_entry = ram(redirect_idx)
val redirect_new_entry = WireInit(redirect_entry)
when (io.redirect.valid) {
enq_ptr := WrapInc(io.redirect.bits, num_entries)
when (io.brupdate.b2.mispredict) {
val new_cfi_idx = (io.brupdate.b2.uop.pc_lob ^
Mux(redirect_entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U))(log2Ceil(fetchWidth), 1)
redirect_new_entry.cfi_idx.valid := true.B
redirect_new_entry.cfi_idx.bits := new_cfi_idx
redirect_new_entry.cfi_mispredicted := true.B
redirect_new_entry.cfi_taken := io.brupdate.b2.taken
redirect_new_entry.cfi_is_call := redirect_entry.cfi_is_call && redirect_entry.cfi_idx.bits === new_cfi_idx
redirect_new_entry.cfi_is_ret := redirect_entry.cfi_is_ret && redirect_entry.cfi_idx.bits === new_cfi_idx
}
ras_update := true.B
ras_update_pc := redirect_entry.ras_top
ras_update_idx := redirect_entry.ras_idx
} .elsewhen (RegNext(io.redirect.valid)) {
prev_entry := RegNext(redirect_new_entry)
prev_ghist := bpd_ghist
prev_pc := bpd_pc
ram(RegNext(io.redirect.bits)) := RegNext(redirect_new_entry)
}
//-------------------------------------------------------------
// **** Core Read PCs ****
//-------------------------------------------------------------
for (i <- 0 until 2) {
val idx = io.get_ftq_pc(i).ftq_idx
val next_idx = WrapInc(idx, num_entries)
val next_is_enq = (next_idx === enq_ptr) && io.enq.fire
val next_pc = Mux(next_is_enq, io.enq.bits.pc, pcs(next_idx))
val get_entry = ram(idx)
val next_entry = ram(next_idx)
io.get_ftq_pc(i).entry := RegNext(get_entry)
if (i == 1)
io.get_ftq_pc(i).ghist := ghist(1).read(idx, true.B)
else
io.get_ftq_pc(i).ghist := DontCare
io.get_ftq_pc(i).pc := RegNext(pcs(idx))
io.get_ftq_pc(i).next_pc := RegNext(next_pc)
io.get_ftq_pc(i).next_val := RegNext(next_idx =/= enq_ptr || next_is_enq)
io.get_ftq_pc(i).com_pc := RegNext(pcs(Mux(io.deq.valid, io.deq.bits, deq_ptr)))
}
for (w <- 0 until coreWidth) {
io.debug_fetch_pc(w) := RegNext(pcs(io.debug_ftq_idx(w)))
}
} | module meta_0_0(
input [3:0] R0_addr,
input R0_clk,
output [119:0] R0_data,
input [3:0] W0_addr,
input W0_en,
input W0_clk,
input [119:0] W0_data
);
meta_0_0_ext meta_0_0_ext (
.R0_addr (R0_addr),
.R0_en (1'h1),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Ported from Rocket-Chip
// See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.lsu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.rocket._
import boom.v3.common._
import boom.v3.exu.BrUpdateInfo
import boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc}
class BoomDCacheReqInternal(implicit p: Parameters) extends BoomDCacheReq()(p)
with HasL1HellaCacheParameters
{
// miss info
val tag_match = Bool()
val old_meta = new L1Metadata
val way_en = UInt(nWays.W)
// Used in the MSHRs
val sdq_id = UInt(log2Ceil(cfg.nSDQ).W)
}
class BoomMSHR(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)
with HasL1HellaCacheParameters
{
val io = IO(new Bundle {
val id = Input(UInt())
val req_pri_val = Input(Bool())
val req_pri_rdy = Output(Bool())
val req_sec_val = Input(Bool())
val req_sec_rdy = Output(Bool())
val clear_prefetch = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val exception = Input(Bool())
val rob_pnr_idx = Input(UInt(robAddrSz.W))
val rob_head_idx = Input(UInt(robAddrSz.W))
val req = Input(new BoomDCacheReqInternal)
val req_is_probe = Input(Bool())
val idx = Output(Valid(UInt()))
val way = Output(Valid(UInt()))
val tag = Output(Valid(UInt()))
val mem_acquire = Decoupled(new TLBundleA(edge.bundle))
val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle)))
val mem_finish = Decoupled(new TLBundleE(edge.bundle))
val prober_state = Input(Valid(UInt(coreMaxAddrBits.W)))
val refill = Decoupled(new L1DataWriteReq)
val meta_write = Decoupled(new L1MetaWriteReq)
val meta_read = Decoupled(new L1MetaReadReq)
val meta_resp = Input(Valid(new L1Metadata))
val wb_req = Decoupled(new WritebackReq(edge.bundle))
// To inform the prefetcher when we are commiting the fetch of this line
val commit_val = Output(Bool())
val commit_addr = Output(UInt(coreMaxAddrBits.W))
val commit_coh = Output(new ClientMetadata)
// Reading from the line buffer
val lb_read = Decoupled(new LineBufferReadReq)
val lb_resp = Input(UInt(encRowBits.W))
val lb_write = Decoupled(new LineBufferWriteReq)
// Replays go through the cache pipeline again
val replay = Decoupled(new BoomDCacheReqInternal)
// Resp go straight out to the core
val resp = Decoupled(new BoomDCacheResp)
// Writeback unit tells us when it is done processing our wb
val wb_resp = Input(Bool())
val probe_rdy = Output(Bool())
})
// TODO: Optimize this. We don't want to mess with cache during speculation
// s_refill_req : Make a request for a new cache line
// s_refill_resp : Store the refill response into our buffer
// s_drain_rpq_loads : Drain out loads from the rpq
// : If miss was misspeculated, go to s_invalid
// s_wb_req : Write back the evicted cache line
// s_wb_resp : Finish writing back the evicted cache line
// s_meta_write_req : Write the metadata for new cache lne
// s_meta_write_resp :
val s_invalid :: s_refill_req :: s_refill_resp :: s_drain_rpq_loads :: s_meta_read :: s_meta_resp_1 :: s_meta_resp_2 :: s_meta_clear :: s_wb_meta_read :: s_wb_req :: s_wb_resp :: s_commit_line :: s_drain_rpq :: s_meta_write_req :: s_mem_finish_1 :: s_mem_finish_2 :: s_prefetched :: s_prefetch :: Nil = Enum(18)
val state = RegInit(s_invalid)
val req = Reg(new BoomDCacheReqInternal)
val req_idx = req.addr(untagBits-1, blockOffBits)
val req_tag = req.addr >> untagBits
val req_block_addr = (req.addr >> blockOffBits) << blockOffBits
val req_needs_wb = RegInit(false.B)
val new_coh = RegInit(ClientMetadata.onReset)
val (_, shrink_param, coh_on_clear) = req.old_meta.coh.onCacheControl(M_FLUSH)
val grow_param = new_coh.onAccess(req.uop.mem_cmd)._2
val coh_on_grant = new_coh.onGrant(req.uop.mem_cmd, io.mem_grant.bits.param)
// We only accept secondary misses if the original request had sufficient permissions
val (cmd_requires_second_acquire, is_hit_again, _, dirtier_coh, dirtier_cmd) =
new_coh.onSecondaryAccess(req.uop.mem_cmd, io.req.uop.mem_cmd)
val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant)
val sec_rdy = (!cmd_requires_second_acquire && !io.req_is_probe &&
!state.isOneOf(s_invalid, s_meta_write_req, s_mem_finish_1, s_mem_finish_2))// Always accept secondary misses
val rpq = Module(new BranchKillableQueue(new BoomDCacheReqInternal, cfg.nRPQ, u => u.uses_ldq, false))
rpq.io.brupdate := io.brupdate
rpq.io.flush := io.exception
assert(!(state === s_invalid && !rpq.io.empty))
rpq.io.enq.valid := ((io.req_pri_val && io.req_pri_rdy) || (io.req_sec_val && io.req_sec_rdy)) && !isPrefetch(io.req.uop.mem_cmd)
rpq.io.enq.bits := io.req
rpq.io.deq.ready := false.B
val grantack = Reg(Valid(new TLBundleE(edge.bundle)))
val refill_ctr = Reg(UInt(log2Ceil(cacheDataBeats).W))
val commit_line = Reg(Bool())
val grant_had_data = Reg(Bool())
val finish_to_prefetch = Reg(Bool())
// Block probes if a tag write we started is still in the pipeline
val meta_hazard = RegInit(0.U(2.W))
when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U }
when (io.meta_write.fire) { meta_hazard := 1.U }
io.probe_rdy := (meta_hazard === 0.U && (state.isOneOf(s_invalid, s_refill_req, s_refill_resp, s_drain_rpq_loads) || (state === s_meta_read && grantack.valid)))
io.idx.valid := state =/= s_invalid
io.tag.valid := state =/= s_invalid
io.way.valid := !state.isOneOf(s_invalid, s_prefetch)
io.idx.bits := req_idx
io.tag.bits := req_tag
io.way.bits := req.way_en
io.meta_write.valid := false.B
io.meta_write.bits := DontCare
io.req_pri_rdy := false.B
io.req_sec_rdy := sec_rdy && rpq.io.enq.ready
io.mem_acquire.valid := false.B
io.mem_acquire.bits := DontCare
io.refill.valid := false.B
io.refill.bits := DontCare
io.replay.valid := false.B
io.replay.bits := DontCare
io.wb_req.valid := false.B
io.wb_req.bits := DontCare
io.resp.valid := false.B
io.resp.bits := DontCare
io.commit_val := false.B
io.commit_addr := req.addr
io.commit_coh := coh_on_grant
io.meta_read.valid := false.B
io.meta_read.bits := DontCare
io.mem_finish.valid := false.B
io.mem_finish.bits := DontCare
io.lb_write.valid := false.B
io.lb_write.bits := DontCare
io.lb_read.valid := false.B
io.lb_read.bits := DontCare
io.mem_grant.ready := false.B
when (io.req_sec_val && io.req_sec_rdy) {
req.uop.mem_cmd := dirtier_cmd
when (is_hit_again) {
new_coh := dirtier_coh
}
}
def handle_pri_req(old_state: UInt): UInt = {
val new_state = WireInit(old_state)
grantack.valid := false.B
refill_ctr := 0.U
assert(rpq.io.enq.ready)
req := io.req
val old_coh = io.req.old_meta.coh
req_needs_wb := old_coh.onCacheControl(M_FLUSH)._1 // does the line we are evicting need to be written back
when (io.req.tag_match) {
val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req.uop.mem_cmd)
when (is_hit) { // set dirty bit
assert(isWrite(io.req.uop.mem_cmd))
new_coh := coh_on_hit
new_state := s_drain_rpq
} .otherwise { // upgrade permissions
new_coh := old_coh
new_state := s_refill_req
}
} .otherwise { // refill and writeback if necessary
new_coh := ClientMetadata.onReset
new_state := s_refill_req
}
new_state
}
when (state === s_invalid) {
io.req_pri_rdy := true.B
grant_had_data := false.B
when (io.req_pri_val && io.req_pri_rdy) {
state := handle_pri_req(state)
}
} .elsewhen (state === s_refill_req) {
io.mem_acquire.valid := true.B
// TODO: Use AcquirePerm if just doing permissions acquire
io.mem_acquire.bits := edge.AcquireBlock(
fromSource = io.id,
toAddress = Cat(req_tag, req_idx) << blockOffBits,
lgSize = lgCacheBlockBytes.U,
growPermissions = grow_param)._2
when (io.mem_acquire.fire) {
state := s_refill_resp
}
} .elsewhen (state === s_refill_resp) {
when (edge.hasData(io.mem_grant.bits)) {
io.mem_grant.ready := io.lb_write.ready
io.lb_write.valid := io.mem_grant.valid
io.lb_write.bits.id := io.id
io.lb_write.bits.offset := refill_address_inc >> rowOffBits
io.lb_write.bits.data := io.mem_grant.bits.data
} .otherwise {
io.mem_grant.ready := true.B
}
when (io.mem_grant.fire) {
grant_had_data := edge.hasData(io.mem_grant.bits)
}
when (refill_done) {
grantack.valid := edge.isRequest(io.mem_grant.bits)
grantack.bits := edge.GrantAck(io.mem_grant.bits)
state := Mux(grant_had_data, s_drain_rpq_loads, s_drain_rpq)
assert(!(!grant_had_data && req_needs_wb))
commit_line := false.B
new_coh := coh_on_grant
}
} .elsewhen (state === s_drain_rpq_loads) {
val drain_load = (isRead(rpq.io.deq.bits.uop.mem_cmd) &&
!isWrite(rpq.io.deq.bits.uop.mem_cmd) &&
(rpq.io.deq.bits.uop.mem_cmd =/= M_XLR)) // LR should go through replay
// drain all loads for now
val rp_addr = Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0))
val word_idx = if (rowWords == 1) 0.U else rp_addr(log2Up(rowWords*coreDataBytes)-1, log2Up(wordBytes))
val data = io.lb_resp
val data_word = data >> Cat(word_idx, 0.U(log2Up(coreDataBits).W))
val loadgen = new LoadGen(rpq.io.deq.bits.uop.mem_size, rpq.io.deq.bits.uop.mem_signed,
Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)),
data_word, false.B, wordBytes)
rpq.io.deq.ready := io.resp.ready && io.lb_read.ready && drain_load
io.lb_read.valid := rpq.io.deq.valid && drain_load
io.lb_read.bits.id := io.id
io.lb_read.bits.offset := rpq.io.deq.bits.addr >> rowOffBits
io.resp.valid := rpq.io.deq.valid && io.lb_read.fire && drain_load
io.resp.bits.uop := rpq.io.deq.bits.uop
io.resp.bits.data := loadgen.data
io.resp.bits.is_hella := rpq.io.deq.bits.is_hella
when (rpq.io.deq.fire) {
commit_line := true.B
}
.elsewhen (rpq.io.empty && !commit_line)
{
when (!rpq.io.enq.fire) {
state := s_mem_finish_1
finish_to_prefetch := enablePrefetching.B
}
} .elsewhen (rpq.io.empty || (rpq.io.deq.valid && !drain_load)) {
// io.commit_val is for the prefetcher. it tells the prefetcher that this line was correctly acquired
// The prefetcher should consider fetching the next line
io.commit_val := true.B
state := s_meta_read
}
} .elsewhen (state === s_meta_read) {
io.meta_read.valid := !io.prober_state.valid || !grantack.valid || (io.prober_state.bits(untagBits-1,blockOffBits) =/= req_idx)
io.meta_read.bits.idx := req_idx
io.meta_read.bits.tag := req_tag
io.meta_read.bits.way_en := req.way_en
when (io.meta_read.fire) {
state := s_meta_resp_1
}
} .elsewhen (state === s_meta_resp_1) {
state := s_meta_resp_2
} .elsewhen (state === s_meta_resp_2) {
val needs_wb = io.meta_resp.bits.coh.onCacheControl(M_FLUSH)._1
state := Mux(!io.meta_resp.valid, s_meta_read, // Prober could have nack'd this read
Mux(needs_wb, s_meta_clear, s_commit_line))
} .elsewhen (state === s_meta_clear) {
io.meta_write.valid := true.B
io.meta_write.bits.idx := req_idx
io.meta_write.bits.data.coh := coh_on_clear
io.meta_write.bits.data.tag := req_tag
io.meta_write.bits.way_en := req.way_en
when (io.meta_write.fire) {
state := s_wb_req
}
} .elsewhen (state === s_wb_req) {
io.wb_req.valid := true.B
io.wb_req.bits.tag := req.old_meta.tag
io.wb_req.bits.idx := req_idx
io.wb_req.bits.param := shrink_param
io.wb_req.bits.way_en := req.way_en
io.wb_req.bits.source := io.id
io.wb_req.bits.voluntary := true.B
when (io.wb_req.fire) {
state := s_wb_resp
}
} .elsewhen (state === s_wb_resp) {
when (io.wb_resp) {
state := s_commit_line
}
} .elsewhen (state === s_commit_line) {
io.lb_read.valid := true.B
io.lb_read.bits.id := io.id
io.lb_read.bits.offset := refill_ctr
io.refill.valid := io.lb_read.fire
io.refill.bits.addr := req_block_addr | (refill_ctr << rowOffBits)
io.refill.bits.way_en := req.way_en
io.refill.bits.wmask := ~(0.U(rowWords.W))
io.refill.bits.data := io.lb_resp
when (io.refill.fire) {
refill_ctr := refill_ctr + 1.U
when (refill_ctr === (cacheDataBeats - 1).U) {
state := s_drain_rpq
}
}
} .elsewhen (state === s_drain_rpq) {
io.replay <> rpq.io.deq
io.replay.bits.way_en := req.way_en
io.replay.bits.addr := Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0))
when (io.replay.fire && isWrite(rpq.io.deq.bits.uop.mem_cmd)) {
// Set dirty bit
val (is_hit, _, coh_on_hit) = new_coh.onAccess(rpq.io.deq.bits.uop.mem_cmd)
assert(is_hit, "We still don't have permissions for this store")
new_coh := coh_on_hit
}
when (rpq.io.empty && !rpq.io.enq.valid) {
state := s_meta_write_req
}
} .elsewhen (state === s_meta_write_req) {
io.meta_write.valid := true.B
io.meta_write.bits.idx := req_idx
io.meta_write.bits.data.coh := new_coh
io.meta_write.bits.data.tag := req_tag
io.meta_write.bits.way_en := req.way_en
when (io.meta_write.fire) {
state := s_mem_finish_1
finish_to_prefetch := false.B
}
} .elsewhen (state === s_mem_finish_1) {
io.mem_finish.valid := grantack.valid
io.mem_finish.bits := grantack.bits
when (io.mem_finish.fire || !grantack.valid) {
grantack.valid := false.B
state := s_mem_finish_2
}
} .elsewhen (state === s_mem_finish_2) {
state := Mux(finish_to_prefetch, s_prefetch, s_invalid)
} .elsewhen (state === s_prefetch) {
io.req_pri_rdy := true.B
when ((io.req_sec_val && !io.req_sec_rdy) || io.clear_prefetch) {
state := s_invalid
} .elsewhen (io.req_sec_val && io.req_sec_rdy) {
val (is_hit, _, coh_on_hit) = new_coh.onAccess(io.req.uop.mem_cmd)
when (is_hit) { // Proceed with refill
new_coh := coh_on_hit
state := s_meta_read
} .otherwise { // Reacquire this line
new_coh := ClientMetadata.onReset
state := s_refill_req
}
} .elsewhen (io.req_pri_val && io.req_pri_rdy) {
grant_had_data := false.B
state := handle_pri_req(state)
}
}
}
class BoomIOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)
with HasL1HellaCacheParameters
{
val io = IO(new Bundle {
val req = Flipped(Decoupled(new BoomDCacheReq))
val resp = Decoupled(new BoomDCacheResp)
val mem_access = Decoupled(new TLBundleA(edge.bundle))
val mem_ack = Flipped(Valid(new TLBundleD(edge.bundle)))
// We don't need brupdate in here because uncacheable operations are guaranteed non-speculative
})
def beatOffset(addr: UInt) = addr.extract(beatOffBits-1, wordOffBits)
def wordFromBeat(addr: UInt, dat: UInt) = {
val shift = Cat(beatOffset(addr), 0.U((wordOffBits+log2Ceil(wordBytes)).W))
(dat >> shift)(wordBits-1, 0)
}
val req = Reg(new BoomDCacheReq)
val grant_word = Reg(UInt(wordBits.W))
val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(4)
val state = RegInit(s_idle)
io.req.ready := state === s_idle
val loadgen = new LoadGen(req.uop.mem_size, req.uop.mem_signed, req.addr, grant_word, false.B, wordBytes)
val a_source = id.U
val a_address = req.addr
val a_size = req.uop.mem_size
val a_data = Fill(beatWords, req.data)
val get = edge.Get(a_source, a_address, a_size)._2
val put = edge.Put(a_source, a_address, a_size, a_data)._2
val atomics = if (edge.manager.anySupportLogical) {
MuxLookup(req.uop.mem_cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)))(Array(
M_XA_SWAP -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.SWAP)._2,
M_XA_XOR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.XOR) ._2,
M_XA_OR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.OR) ._2,
M_XA_AND -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.AND) ._2,
M_XA_ADD -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.ADD)._2,
M_XA_MIN -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MIN)._2,
M_XA_MAX -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAX)._2,
M_XA_MINU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MINU)._2,
M_XA_MAXU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAXU)._2))
} else {
// If no managers support atomics, assert fail if processor asks for them
assert(state === s_idle || !isAMO(req.uop.mem_cmd))
(0.U).asTypeOf(new TLBundleA(edge.bundle))
}
assert(state === s_idle || req.uop.mem_cmd =/= M_XSC)
io.mem_access.valid := state === s_mem_access
io.mem_access.bits := Mux(isAMO(req.uop.mem_cmd), atomics, Mux(isRead(req.uop.mem_cmd), get, put))
val send_resp = isRead(req.uop.mem_cmd)
io.resp.valid := (state === s_resp) && send_resp
io.resp.bits.is_hella := req.is_hella
io.resp.bits.uop := req.uop
io.resp.bits.data := loadgen.data
when (io.req.fire) {
req := io.req.bits
state := s_mem_access
}
when (io.mem_access.fire) {
state := s_mem_ack
}
when (state === s_mem_ack && io.mem_ack.valid) {
state := s_resp
when (isRead(req.uop.mem_cmd)) {
grant_word := wordFromBeat(req.addr, io.mem_ack.bits.data)
}
}
when (state === s_resp) {
when (!send_resp || io.resp.fire) {
state := s_idle
}
}
}
class LineBufferReadReq(implicit p: Parameters) extends BoomBundle()(p)
with HasL1HellaCacheParameters
{
val id = UInt(log2Ceil(nLBEntries).W)
val offset = UInt(log2Ceil(cacheDataBeats).W)
def lb_addr = Cat(id, offset)
}
class LineBufferWriteReq(implicit p: Parameters) extends LineBufferReadReq()(p)
{
val data = UInt(encRowBits.W)
}
class LineBufferMetaWriteReq(implicit p: Parameters) extends BoomBundle()(p)
{
val id = UInt(log2Ceil(nLBEntries).W)
val coh = new ClientMetadata
val addr = UInt(coreMaxAddrBits.W)
}
class LineBufferMeta(implicit p: Parameters) extends BoomBundle()(p)
with HasL1HellaCacheParameters
{
val coh = new ClientMetadata
val addr = UInt(coreMaxAddrBits.W)
}
class BoomMSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)
with HasL1HellaCacheParameters
{
val io = IO(new Bundle {
val req = Flipped(Vec(memWidth, Decoupled(new BoomDCacheReqInternal))) // Req from s2 of DCache pipe
val req_is_probe = Input(Vec(memWidth, Bool()))
val resp = Decoupled(new BoomDCacheResp)
val secondary_miss = Output(Vec(memWidth, Bool()))
val block_hit = Output(Vec(memWidth, Bool()))
val brupdate = Input(new BrUpdateInfo)
val exception = Input(Bool())
val rob_pnr_idx = Input(UInt(robAddrSz.W))
val rob_head_idx = Input(UInt(robAddrSz.W))
val mem_acquire = Decoupled(new TLBundleA(edge.bundle))
val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle)))
val mem_finish = Decoupled(new TLBundleE(edge.bundle))
val refill = Decoupled(new L1DataWriteReq)
val meta_write = Decoupled(new L1MetaWriteReq)
val meta_read = Decoupled(new L1MetaReadReq)
val meta_resp = Input(Valid(new L1Metadata))
val replay = Decoupled(new BoomDCacheReqInternal)
val prefetch = Decoupled(new BoomDCacheReq)
val wb_req = Decoupled(new WritebackReq(edge.bundle))
val prober_state = Input(Valid(UInt(coreMaxAddrBits.W)))
val clear_all = Input(Bool()) // Clears all uncommitted MSHRs to prepare for fence
val wb_resp = Input(Bool())
val fence_rdy = Output(Bool())
val probe_rdy = Output(Bool())
})
val req_idx = OHToUInt(io.req.map(_.valid))
val req = io.req(req_idx)
val req_is_probe = io.req_is_probe(0)
for (w <- 0 until memWidth)
io.req(w).ready := false.B
val prefetcher: DataPrefetcher = if (enablePrefetching) Module(new NLPrefetcher)
else Module(new NullPrefetcher)
io.prefetch <> prefetcher.io.prefetch
val cacheable = edge.manager.supportsAcquireBFast(req.bits.addr, lgCacheBlockBytes.U)
// --------------------
// The MSHR SDQ
val sdq_val = RegInit(0.U(cfg.nSDQ.W))
val sdq_alloc_id = PriorityEncoder(~sdq_val(cfg.nSDQ-1,0))
val sdq_rdy = !sdq_val.andR
val sdq_enq = req.fire && cacheable && isWrite(req.bits.uop.mem_cmd)
val sdq = Mem(cfg.nSDQ, UInt(coreDataBits.W))
when (sdq_enq) {
sdq(sdq_alloc_id) := req.bits.data
}
// --------------------
// The LineBuffer Data
// Holds refilling lines, prefetched lines
val lb = Mem(nLBEntries * cacheDataBeats, UInt(encRowBits.W))
val lb_read_arb = Module(new Arbiter(new LineBufferReadReq, cfg.nMSHRs))
val lb_write_arb = Module(new Arbiter(new LineBufferWriteReq, cfg.nMSHRs))
lb_read_arb.io.out.ready := false.B
lb_write_arb.io.out.ready := true.B
val lb_read_data = WireInit(0.U(encRowBits.W))
when (lb_write_arb.io.out.fire) {
lb.write(lb_write_arb.io.out.bits.lb_addr, lb_write_arb.io.out.bits.data)
} .otherwise {
lb_read_arb.io.out.ready := true.B
when (lb_read_arb.io.out.fire) {
lb_read_data := lb.read(lb_read_arb.io.out.bits.lb_addr)
}
}
def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f))
val idx_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool())))
val tag_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool())))
val way_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool())))
val tag_match = widthMap(w => Mux1H(idx_matches(w), tag_matches(w)))
val idx_match = widthMap(w => idx_matches(w).reduce(_||_))
val way_match = widthMap(w => Mux1H(idx_matches(w), way_matches(w)))
val wb_tag_list = Wire(Vec(cfg.nMSHRs, UInt(tagBits.W)))
val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq , cfg.nMSHRs))
val meta_read_arb = Module(new Arbiter(new L1MetaReadReq , cfg.nMSHRs))
val wb_req_arb = Module(new Arbiter(new WritebackReq(edge.bundle), cfg.nMSHRs))
val replay_arb = Module(new Arbiter(new BoomDCacheReqInternal , cfg.nMSHRs))
val resp_arb = Module(new Arbiter(new BoomDCacheResp , cfg.nMSHRs + nIOMSHRs))
val refill_arb = Module(new Arbiter(new L1DataWriteReq , cfg.nMSHRs))
val commit_vals = Wire(Vec(cfg.nMSHRs, Bool()))
val commit_addrs = Wire(Vec(cfg.nMSHRs, UInt(coreMaxAddrBits.W)))
val commit_cohs = Wire(Vec(cfg.nMSHRs, new ClientMetadata))
var sec_rdy = false.B
io.fence_rdy := true.B
io.probe_rdy := true.B
io.mem_grant.ready := false.B
val mshr_alloc_idx = Wire(UInt())
val pri_rdy = WireInit(false.B)
val pri_val = req.valid && sdq_rdy && cacheable && !idx_match(req_idx)
val mshrs = (0 until cfg.nMSHRs) map { i =>
val mshr = Module(new BoomMSHR)
mshr.io.id := i.U(log2Ceil(cfg.nMSHRs).W)
for (w <- 0 until memWidth) {
idx_matches(w)(i) := mshr.io.idx.valid && mshr.io.idx.bits === io.req(w).bits.addr(untagBits-1,blockOffBits)
tag_matches(w)(i) := mshr.io.tag.valid && mshr.io.tag.bits === io.req(w).bits.addr >> untagBits
way_matches(w)(i) := mshr.io.way.valid && mshr.io.way.bits === io.req(w).bits.way_en
}
wb_tag_list(i) := mshr.io.wb_req.bits.tag
mshr.io.req_pri_val := (i.U === mshr_alloc_idx) && pri_val
when (i.U === mshr_alloc_idx) {
pri_rdy := mshr.io.req_pri_rdy
}
mshr.io.req_sec_val := req.valid && sdq_rdy && tag_match(req_idx) && idx_matches(req_idx)(i) && cacheable
mshr.io.req := req.bits
mshr.io.req_is_probe := req_is_probe
mshr.io.req.sdq_id := sdq_alloc_id
// Clear because of a FENCE, a request to the same idx as a prefetched line,
// a probe to that prefetched line, all mshrs are in use
mshr.io.clear_prefetch := ((io.clear_all && !req.valid)||
(req.valid && idx_matches(req_idx)(i) && cacheable && !tag_match(req_idx)) ||
(req_is_probe && idx_matches(req_idx)(i)))
mshr.io.brupdate := io.brupdate
mshr.io.exception := io.exception
mshr.io.rob_pnr_idx := io.rob_pnr_idx
mshr.io.rob_head_idx := io.rob_head_idx
mshr.io.prober_state := io.prober_state
mshr.io.wb_resp := io.wb_resp
meta_write_arb.io.in(i) <> mshr.io.meta_write
meta_read_arb.io.in(i) <> mshr.io.meta_read
mshr.io.meta_resp := io.meta_resp
wb_req_arb.io.in(i) <> mshr.io.wb_req
replay_arb.io.in(i) <> mshr.io.replay
refill_arb.io.in(i) <> mshr.io.refill
lb_read_arb.io.in(i) <> mshr.io.lb_read
mshr.io.lb_resp := lb_read_data
lb_write_arb.io.in(i) <> mshr.io.lb_write
commit_vals(i) := mshr.io.commit_val
commit_addrs(i) := mshr.io.commit_addr
commit_cohs(i) := mshr.io.commit_coh
mshr.io.mem_grant.valid := false.B
mshr.io.mem_grant.bits := DontCare
when (io.mem_grant.bits.source === i.U) {
mshr.io.mem_grant <> io.mem_grant
}
sec_rdy = sec_rdy || (mshr.io.req_sec_rdy && mshr.io.req_sec_val)
resp_arb.io.in(i) <> mshr.io.resp
when (!mshr.io.req_pri_rdy) {
io.fence_rdy := false.B
}
for (w <- 0 until memWidth) {
when (!mshr.io.probe_rdy && idx_matches(w)(i) && io.req_is_probe(w)) {
io.probe_rdy := false.B
}
}
mshr
}
// Try to round-robin the MSHRs
val mshr_head = RegInit(0.U(log2Ceil(cfg.nMSHRs).W))
mshr_alloc_idx := RegNext(AgePriorityEncoder(mshrs.map(m=>m.io.req_pri_rdy), mshr_head))
when (pri_rdy && pri_val) { mshr_head := WrapInc(mshr_head, cfg.nMSHRs) }
io.meta_write <> meta_write_arb.io.out
io.meta_read <> meta_read_arb.io.out
io.wb_req <> wb_req_arb.io.out
val mmio_alloc_arb = Module(new Arbiter(Bool(), nIOMSHRs))
var mmio_rdy = false.B
val mmios = (0 until nIOMSHRs) map { i =>
val id = cfg.nMSHRs + 1 + i // +1 for wb unit
val mshr = Module(new BoomIOMSHR(id))
mmio_alloc_arb.io.in(i).valid := mshr.io.req.ready
mmio_alloc_arb.io.in(i).bits := DontCare
mshr.io.req.valid := mmio_alloc_arb.io.in(i).ready
mshr.io.req.bits := req.bits
mmio_rdy = mmio_rdy || mshr.io.req.ready
mshr.io.mem_ack.bits := io.mem_grant.bits
mshr.io.mem_ack.valid := io.mem_grant.valid && io.mem_grant.bits.source === id.U
when (io.mem_grant.bits.source === id.U) {
io.mem_grant.ready := true.B
}
resp_arb.io.in(cfg.nMSHRs + i) <> mshr.io.resp
when (!mshr.io.req.ready) {
io.fence_rdy := false.B
}
mshr
}
mmio_alloc_arb.io.out.ready := req.valid && !cacheable
TLArbiter.lowestFromSeq(edge, io.mem_acquire, mshrs.map(_.io.mem_acquire) ++ mmios.map(_.io.mem_access))
TLArbiter.lowestFromSeq(edge, io.mem_finish, mshrs.map(_.io.mem_finish))
val respq = Module(new BranchKillableQueue(new BoomDCacheResp, 4, u => u.uses_ldq, flow = false))
respq.io.brupdate := io.brupdate
respq.io.flush := io.exception
respq.io.enq <> resp_arb.io.out
io.resp <> respq.io.deq
for (w <- 0 until memWidth) {
io.req(w).ready := (w.U === req_idx) &&
Mux(!cacheable, mmio_rdy, sdq_rdy && Mux(idx_match(w), tag_match(w) && sec_rdy, pri_rdy))
io.secondary_miss(w) := idx_match(w) && way_match(w) && !tag_match(w)
io.block_hit(w) := idx_match(w) && tag_match(w)
}
io.refill <> refill_arb.io.out
val free_sdq = io.replay.fire && isWrite(io.replay.bits.uop.mem_cmd)
io.replay <> replay_arb.io.out
io.replay.bits.data := sdq(replay_arb.io.out.bits.sdq_id)
when (io.replay.valid || sdq_enq) {
sdq_val := sdq_val & ~(UIntToOH(replay_arb.io.out.bits.sdq_id) & Fill(cfg.nSDQ, free_sdq)) |
PriorityEncoderOH(~sdq_val(cfg.nSDQ-1,0)) & Fill(cfg.nSDQ, sdq_enq)
}
prefetcher.io.mshr_avail := RegNext(pri_rdy)
prefetcher.io.req_val := RegNext(commit_vals.reduce(_||_))
prefetcher.io.req_addr := RegNext(Mux1H(commit_vals, commit_addrs))
prefetcher.io.req_coh := RegNext(Mux1H(commit_vals, commit_cohs))
} | module BoomIOMSHR(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [6:0] io_req_bits_uop_uopc,
input [31:0] io_req_bits_uop_inst,
input [31:0] io_req_bits_uop_debug_inst,
input io_req_bits_uop_is_rvc,
input [39:0] io_req_bits_uop_debug_pc,
input [2:0] io_req_bits_uop_iq_type,
input [9:0] io_req_bits_uop_fu_code,
input [3:0] io_req_bits_uop_ctrl_br_type,
input [1:0] io_req_bits_uop_ctrl_op1_sel,
input [2:0] io_req_bits_uop_ctrl_op2_sel,
input [2:0] io_req_bits_uop_ctrl_imm_sel,
input [4:0] io_req_bits_uop_ctrl_op_fcn,
input io_req_bits_uop_ctrl_fcn_dw,
input [2:0] io_req_bits_uop_ctrl_csr_cmd,
input io_req_bits_uop_ctrl_is_load,
input io_req_bits_uop_ctrl_is_sta,
input io_req_bits_uop_ctrl_is_std,
input [1:0] io_req_bits_uop_iw_state,
input io_req_bits_uop_iw_p1_poisoned,
input io_req_bits_uop_iw_p2_poisoned,
input io_req_bits_uop_is_br,
input io_req_bits_uop_is_jalr,
input io_req_bits_uop_is_jal,
input io_req_bits_uop_is_sfb,
input [7:0] io_req_bits_uop_br_mask,
input [2:0] io_req_bits_uop_br_tag,
input [3:0] io_req_bits_uop_ftq_idx,
input io_req_bits_uop_edge_inst,
input [5:0] io_req_bits_uop_pc_lob,
input io_req_bits_uop_taken,
input [19:0] io_req_bits_uop_imm_packed,
input [11:0] io_req_bits_uop_csr_addr,
input [4:0] io_req_bits_uop_rob_idx,
input [2:0] io_req_bits_uop_ldq_idx,
input [2:0] io_req_bits_uop_stq_idx,
input [1:0] io_req_bits_uop_rxq_idx,
input [5:0] io_req_bits_uop_pdst,
input [5:0] io_req_bits_uop_prs1,
input [5:0] io_req_bits_uop_prs2,
input [5:0] io_req_bits_uop_prs3,
input [3:0] io_req_bits_uop_ppred,
input io_req_bits_uop_prs1_busy,
input io_req_bits_uop_prs2_busy,
input io_req_bits_uop_prs3_busy,
input io_req_bits_uop_ppred_busy,
input [5:0] io_req_bits_uop_stale_pdst,
input io_req_bits_uop_exception,
input [63:0] io_req_bits_uop_exc_cause,
input io_req_bits_uop_bypassable,
input [4:0] io_req_bits_uop_mem_cmd,
input [1:0] io_req_bits_uop_mem_size,
input io_req_bits_uop_mem_signed,
input io_req_bits_uop_is_fence,
input io_req_bits_uop_is_fencei,
input io_req_bits_uop_is_amo,
input io_req_bits_uop_uses_ldq,
input io_req_bits_uop_uses_stq,
input io_req_bits_uop_is_sys_pc2epc,
input io_req_bits_uop_is_unique,
input io_req_bits_uop_flush_on_commit,
input io_req_bits_uop_ldst_is_rs1,
input [5:0] io_req_bits_uop_ldst,
input [5:0] io_req_bits_uop_lrs1,
input [5:0] io_req_bits_uop_lrs2,
input [5:0] io_req_bits_uop_lrs3,
input io_req_bits_uop_ldst_val,
input [1:0] io_req_bits_uop_dst_rtype,
input [1:0] io_req_bits_uop_lrs1_rtype,
input [1:0] io_req_bits_uop_lrs2_rtype,
input io_req_bits_uop_frs3_en,
input io_req_bits_uop_fp_val,
input io_req_bits_uop_fp_single,
input io_req_bits_uop_xcpt_pf_if,
input io_req_bits_uop_xcpt_ae_if,
input io_req_bits_uop_xcpt_ma_if,
input io_req_bits_uop_bp_debug_if,
input io_req_bits_uop_bp_xcpt_if,
input [1:0] io_req_bits_uop_debug_fsrc,
input [1:0] io_req_bits_uop_debug_tsrc,
input [39:0] io_req_bits_addr,
input [63:0] io_req_bits_data,
input io_req_bits_is_hella,
input io_resp_ready,
output io_resp_valid,
output [6:0] io_resp_bits_uop_uopc,
output [31:0] io_resp_bits_uop_inst,
output [31:0] io_resp_bits_uop_debug_inst,
output io_resp_bits_uop_is_rvc,
output [39:0] io_resp_bits_uop_debug_pc,
output [2:0] io_resp_bits_uop_iq_type,
output [9:0] io_resp_bits_uop_fu_code,
output [3:0] io_resp_bits_uop_ctrl_br_type,
output [1:0] io_resp_bits_uop_ctrl_op1_sel,
output [2:0] io_resp_bits_uop_ctrl_op2_sel,
output [2:0] io_resp_bits_uop_ctrl_imm_sel,
output [4:0] io_resp_bits_uop_ctrl_op_fcn,
output io_resp_bits_uop_ctrl_fcn_dw,
output [2:0] io_resp_bits_uop_ctrl_csr_cmd,
output io_resp_bits_uop_ctrl_is_load,
output io_resp_bits_uop_ctrl_is_sta,
output io_resp_bits_uop_ctrl_is_std,
output [1:0] io_resp_bits_uop_iw_state,
output io_resp_bits_uop_iw_p1_poisoned,
output io_resp_bits_uop_iw_p2_poisoned,
output io_resp_bits_uop_is_br,
output io_resp_bits_uop_is_jalr,
output io_resp_bits_uop_is_jal,
output io_resp_bits_uop_is_sfb,
output [7:0] io_resp_bits_uop_br_mask,
output [2:0] io_resp_bits_uop_br_tag,
output [3:0] io_resp_bits_uop_ftq_idx,
output io_resp_bits_uop_edge_inst,
output [5:0] io_resp_bits_uop_pc_lob,
output io_resp_bits_uop_taken,
output [19:0] io_resp_bits_uop_imm_packed,
output [11:0] io_resp_bits_uop_csr_addr,
output [4:0] io_resp_bits_uop_rob_idx,
output [2:0] io_resp_bits_uop_ldq_idx,
output [2:0] io_resp_bits_uop_stq_idx,
output [1:0] io_resp_bits_uop_rxq_idx,
output [5:0] io_resp_bits_uop_pdst,
output [5:0] io_resp_bits_uop_prs1,
output [5:0] io_resp_bits_uop_prs2,
output [5:0] io_resp_bits_uop_prs3,
output [3:0] io_resp_bits_uop_ppred,
output io_resp_bits_uop_prs1_busy,
output io_resp_bits_uop_prs2_busy,
output io_resp_bits_uop_prs3_busy,
output io_resp_bits_uop_ppred_busy,
output [5:0] io_resp_bits_uop_stale_pdst,
output io_resp_bits_uop_exception,
output [63:0] io_resp_bits_uop_exc_cause,
output io_resp_bits_uop_bypassable,
output [4:0] io_resp_bits_uop_mem_cmd,
output [1:0] io_resp_bits_uop_mem_size,
output io_resp_bits_uop_mem_signed,
output io_resp_bits_uop_is_fence,
output io_resp_bits_uop_is_fencei,
output io_resp_bits_uop_is_amo,
output io_resp_bits_uop_uses_ldq,
output io_resp_bits_uop_uses_stq,
output io_resp_bits_uop_is_sys_pc2epc,
output io_resp_bits_uop_is_unique,
output io_resp_bits_uop_flush_on_commit,
output io_resp_bits_uop_ldst_is_rs1,
output [5:0] io_resp_bits_uop_ldst,
output [5:0] io_resp_bits_uop_lrs1,
output [5:0] io_resp_bits_uop_lrs2,
output [5:0] io_resp_bits_uop_lrs3,
output io_resp_bits_uop_ldst_val,
output [1:0] io_resp_bits_uop_dst_rtype,
output [1:0] io_resp_bits_uop_lrs1_rtype,
output [1:0] io_resp_bits_uop_lrs2_rtype,
output io_resp_bits_uop_frs3_en,
output io_resp_bits_uop_fp_val,
output io_resp_bits_uop_fp_single,
output io_resp_bits_uop_xcpt_pf_if,
output io_resp_bits_uop_xcpt_ae_if,
output io_resp_bits_uop_xcpt_ma_if,
output io_resp_bits_uop_bp_debug_if,
output io_resp_bits_uop_bp_xcpt_if,
output [1:0] io_resp_bits_uop_debug_fsrc,
output [1:0] io_resp_bits_uop_debug_tsrc,
output [63:0] io_resp_bits_data,
output io_resp_bits_is_hella,
input io_mem_access_ready,
output io_mem_access_valid,
output [2:0] io_mem_access_bits_opcode,
output [2:0] io_mem_access_bits_param,
output [3:0] io_mem_access_bits_size,
output [1:0] io_mem_access_bits_source,
output [31:0] io_mem_access_bits_address,
output [7:0] io_mem_access_bits_mask,
output [63:0] io_mem_access_bits_data,
input io_mem_ack_valid,
input [63:0] io_mem_ack_bits_data
);
reg [6:0] req_uop_uopc;
reg [31:0] req_uop_inst;
reg [31:0] req_uop_debug_inst;
reg req_uop_is_rvc;
reg [39:0] req_uop_debug_pc;
reg [2:0] req_uop_iq_type;
reg [9:0] req_uop_fu_code;
reg [3:0] req_uop_ctrl_br_type;
reg [1:0] req_uop_ctrl_op1_sel;
reg [2:0] req_uop_ctrl_op2_sel;
reg [2:0] req_uop_ctrl_imm_sel;
reg [4:0] req_uop_ctrl_op_fcn;
reg req_uop_ctrl_fcn_dw;
reg [2:0] req_uop_ctrl_csr_cmd;
reg req_uop_ctrl_is_load;
reg req_uop_ctrl_is_sta;
reg req_uop_ctrl_is_std;
reg [1:0] req_uop_iw_state;
reg req_uop_iw_p1_poisoned;
reg req_uop_iw_p2_poisoned;
reg req_uop_is_br;
reg req_uop_is_jalr;
reg req_uop_is_jal;
reg req_uop_is_sfb;
reg [7:0] req_uop_br_mask;
reg [2:0] req_uop_br_tag;
reg [3:0] req_uop_ftq_idx;
reg req_uop_edge_inst;
reg [5:0] req_uop_pc_lob;
reg req_uop_taken;
reg [19:0] req_uop_imm_packed;
reg [11:0] req_uop_csr_addr;
reg [4:0] req_uop_rob_idx;
reg [2:0] req_uop_ldq_idx;
reg [2:0] req_uop_stq_idx;
reg [1:0] req_uop_rxq_idx;
reg [5:0] req_uop_pdst;
reg [5:0] req_uop_prs1;
reg [5:0] req_uop_prs2;
reg [5:0] req_uop_prs3;
reg [3:0] req_uop_ppred;
reg req_uop_prs1_busy;
reg req_uop_prs2_busy;
reg req_uop_prs3_busy;
reg req_uop_ppred_busy;
reg [5:0] req_uop_stale_pdst;
reg req_uop_exception;
reg [63:0] req_uop_exc_cause;
reg req_uop_bypassable;
reg [4:0] req_uop_mem_cmd;
reg [1:0] req_uop_mem_size;
reg req_uop_mem_signed;
reg req_uop_is_fence;
reg req_uop_is_fencei;
reg req_uop_is_amo;
reg req_uop_uses_ldq;
reg req_uop_uses_stq;
reg req_uop_is_sys_pc2epc;
reg req_uop_is_unique;
reg req_uop_flush_on_commit;
reg req_uop_ldst_is_rs1;
reg [5:0] req_uop_ldst;
reg [5:0] req_uop_lrs1;
reg [5:0] req_uop_lrs2;
reg [5:0] req_uop_lrs3;
reg req_uop_ldst_val;
reg [1:0] req_uop_dst_rtype;
reg [1:0] req_uop_lrs1_rtype;
reg [1:0] req_uop_lrs2_rtype;
reg req_uop_frs3_en;
reg req_uop_fp_val;
reg req_uop_fp_single;
reg req_uop_xcpt_pf_if;
reg req_uop_xcpt_ae_if;
reg req_uop_xcpt_ma_if;
reg req_uop_bp_debug_if;
reg req_uop_bp_xcpt_if;
reg [1:0] req_uop_debug_fsrc;
reg [1:0] req_uop_debug_tsrc;
reg [39:0] req_addr;
reg [63:0] req_data;
reg req_is_hella;
reg [63:0] grant_word;
reg [1:0] state;
wire io_req_ready_0 = state == 2'h0;
wire get_a_mask_sub_sub_size = req_uop_mem_size == 2'h2;
wire get_a_mask_sub_sub_0_1 = (&req_uop_mem_size) | get_a_mask_sub_sub_size & ~(req_addr[2]);
wire get_a_mask_sub_sub_1_1 = (&req_uop_mem_size) | get_a_mask_sub_sub_size & req_addr[2];
wire get_a_mask_sub_size = req_uop_mem_size == 2'h1;
wire get_a_mask_sub_0_2 = ~(req_addr[2]) & ~(req_addr[1]);
wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 | get_a_mask_sub_size & get_a_mask_sub_0_2;
wire get_a_mask_sub_1_2 = ~(req_addr[2]) & req_addr[1];
wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 | get_a_mask_sub_size & get_a_mask_sub_1_2;
wire get_a_mask_sub_2_2 = req_addr[2] & ~(req_addr[1]);
wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 | get_a_mask_sub_size & get_a_mask_sub_2_2;
wire get_a_mask_sub_3_2 = req_addr[2] & req_addr[1];
wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 | get_a_mask_sub_size & get_a_mask_sub_3_2;
wire put_a_mask_sub_sub_size = req_uop_mem_size == 2'h2;
wire put_a_mask_sub_sub_0_1 = (&req_uop_mem_size) | put_a_mask_sub_sub_size & ~(req_addr[2]);
wire put_a_mask_sub_sub_1_1 = (&req_uop_mem_size) | put_a_mask_sub_sub_size & req_addr[2];
wire put_a_mask_sub_size = req_uop_mem_size == 2'h1;
wire put_a_mask_sub_0_2 = ~(req_addr[2]) & ~(req_addr[1]);
wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 | put_a_mask_sub_size & put_a_mask_sub_0_2;
wire put_a_mask_sub_1_2 = ~(req_addr[2]) & req_addr[1];
wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 | put_a_mask_sub_size & put_a_mask_sub_1_2;
wire put_a_mask_sub_2_2 = req_addr[2] & ~(req_addr[1]);
wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 | put_a_mask_sub_size & put_a_mask_sub_2_2;
wire put_a_mask_sub_3_2 = req_addr[2] & req_addr[1];
wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 | put_a_mask_sub_size & put_a_mask_sub_3_2;
wire atomics_a_mask_sub_sub_size = req_uop_mem_size == 2'h2;
wire atomics_a_mask_sub_sub_0_1 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size & ~(req_addr[2]);
wire atomics_a_mask_sub_sub_1_1 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size & req_addr[2];
wire atomics_a_mask_sub_size = req_uop_mem_size == 2'h1;
wire atomics_a_mask_sub_0_2 = ~(req_addr[2]) & ~(req_addr[1]);
wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 | atomics_a_mask_sub_size & atomics_a_mask_sub_0_2;
wire atomics_a_mask_sub_1_2 = ~(req_addr[2]) & req_addr[1];
wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 | atomics_a_mask_sub_size & atomics_a_mask_sub_1_2;
wire atomics_a_mask_sub_2_2 = req_addr[2] & ~(req_addr[1]);
wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 | atomics_a_mask_sub_size & atomics_a_mask_sub_2_2;
wire atomics_a_mask_sub_3_2 = req_addr[2] & req_addr[1];
wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 | atomics_a_mask_sub_size & atomics_a_mask_sub_3_2;
wire atomics_a_mask_sub_sub_size_1 = req_uop_mem_size == 2'h2;
wire atomics_a_mask_sub_sub_0_1_1 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_1 & ~(req_addr[2]);
wire atomics_a_mask_sub_sub_1_1_1 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_1 & req_addr[2];
wire atomics_a_mask_sub_size_1 = req_uop_mem_size == 2'h1;
wire atomics_a_mask_sub_0_2_1 = ~(req_addr[2]) & ~(req_addr[1]);
wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 | atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1;
wire atomics_a_mask_sub_1_2_1 = ~(req_addr[2]) & req_addr[1];
wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 | atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1;
wire atomics_a_mask_sub_2_2_1 = req_addr[2] & ~(req_addr[1]);
wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 | atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1;
wire atomics_a_mask_sub_3_2_1 = req_addr[2] & req_addr[1];
wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 | atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1;
wire atomics_a_mask_sub_sub_size_2 = req_uop_mem_size == 2'h2;
wire atomics_a_mask_sub_sub_0_1_2 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_2 & ~(req_addr[2]);
wire atomics_a_mask_sub_sub_1_1_2 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_2 & req_addr[2];
wire atomics_a_mask_sub_size_2 = req_uop_mem_size == 2'h1;
wire atomics_a_mask_sub_0_2_2 = ~(req_addr[2]) & ~(req_addr[1]);
wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 | atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2;
wire atomics_a_mask_sub_1_2_2 = ~(req_addr[2]) & req_addr[1];
wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 | atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2;
wire atomics_a_mask_sub_2_2_2 = req_addr[2] & ~(req_addr[1]);
wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 | atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2;
wire atomics_a_mask_sub_3_2_2 = req_addr[2] & req_addr[1];
wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 | atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2;
wire atomics_a_mask_sub_sub_size_3 = req_uop_mem_size == 2'h2;
wire atomics_a_mask_sub_sub_0_1_3 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_3 & ~(req_addr[2]);
wire atomics_a_mask_sub_sub_1_1_3 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_3 & req_addr[2];
wire atomics_a_mask_sub_size_3 = req_uop_mem_size == 2'h1;
wire atomics_a_mask_sub_0_2_3 = ~(req_addr[2]) & ~(req_addr[1]);
wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 | atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3;
wire atomics_a_mask_sub_1_2_3 = ~(req_addr[2]) & req_addr[1];
wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 | atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3;
wire atomics_a_mask_sub_2_2_3 = req_addr[2] & ~(req_addr[1]);
wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 | atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3;
wire atomics_a_mask_sub_3_2_3 = req_addr[2] & req_addr[1];
wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 | atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3;
wire atomics_a_mask_sub_sub_size_4 = req_uop_mem_size == 2'h2;
wire atomics_a_mask_sub_sub_0_1_4 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_4 & ~(req_addr[2]);
wire atomics_a_mask_sub_sub_1_1_4 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_4 & req_addr[2];
wire atomics_a_mask_sub_size_4 = req_uop_mem_size == 2'h1;
wire atomics_a_mask_sub_0_2_4 = ~(req_addr[2]) & ~(req_addr[1]);
wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 | atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4;
wire atomics_a_mask_sub_1_2_4 = ~(req_addr[2]) & req_addr[1];
wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 | atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4;
wire atomics_a_mask_sub_2_2_4 = req_addr[2] & ~(req_addr[1]);
wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 | atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4;
wire atomics_a_mask_sub_3_2_4 = req_addr[2] & req_addr[1];
wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 | atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4;
wire atomics_a_mask_sub_sub_size_5 = req_uop_mem_size == 2'h2;
wire atomics_a_mask_sub_sub_0_1_5 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_5 & ~(req_addr[2]);
wire atomics_a_mask_sub_sub_1_1_5 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_5 & req_addr[2];
wire atomics_a_mask_sub_size_5 = req_uop_mem_size == 2'h1;
wire atomics_a_mask_sub_0_2_5 = ~(req_addr[2]) & ~(req_addr[1]);
wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 | atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5;
wire atomics_a_mask_sub_1_2_5 = ~(req_addr[2]) & req_addr[1];
wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 | atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5;
wire atomics_a_mask_sub_2_2_5 = req_addr[2] & ~(req_addr[1]);
wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 | atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5;
wire atomics_a_mask_sub_3_2_5 = req_addr[2] & req_addr[1];
wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 | atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5;
wire atomics_a_mask_sub_sub_size_6 = req_uop_mem_size == 2'h2;
wire atomics_a_mask_sub_sub_0_1_6 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_6 & ~(req_addr[2]);
wire atomics_a_mask_sub_sub_1_1_6 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_6 & req_addr[2];
wire atomics_a_mask_sub_size_6 = req_uop_mem_size == 2'h1;
wire atomics_a_mask_sub_0_2_6 = ~(req_addr[2]) & ~(req_addr[1]);
wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 | atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6;
wire atomics_a_mask_sub_1_2_6 = ~(req_addr[2]) & req_addr[1];
wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 | atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6;
wire atomics_a_mask_sub_2_2_6 = req_addr[2] & ~(req_addr[1]);
wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 | atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6;
wire atomics_a_mask_sub_3_2_6 = req_addr[2] & req_addr[1];
wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 | atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6;
wire atomics_a_mask_sub_sub_size_7 = req_uop_mem_size == 2'h2;
wire atomics_a_mask_sub_sub_0_1_7 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_7 & ~(req_addr[2]);
wire atomics_a_mask_sub_sub_1_1_7 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_7 & req_addr[2];
wire atomics_a_mask_sub_size_7 = req_uop_mem_size == 2'h1;
wire atomics_a_mask_sub_0_2_7 = ~(req_addr[2]) & ~(req_addr[1]);
wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 | atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7;
wire atomics_a_mask_sub_1_2_7 = ~(req_addr[2]) & req_addr[1];
wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 | atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7;
wire atomics_a_mask_sub_2_2_7 = req_addr[2] & ~(req_addr[1]);
wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 | atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7;
wire atomics_a_mask_sub_3_2_7 = req_addr[2] & req_addr[1];
wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 | atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7;
wire atomics_a_mask_sub_sub_size_8 = req_uop_mem_size == 2'h2;
wire atomics_a_mask_sub_sub_0_1_8 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_8 & ~(req_addr[2]);
wire atomics_a_mask_sub_sub_1_1_8 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_8 & req_addr[2];
wire atomics_a_mask_sub_size_8 = req_uop_mem_size == 2'h1;
wire atomics_a_mask_sub_0_2_8 = ~(req_addr[2]) & ~(req_addr[1]);
wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 | atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8;
wire atomics_a_mask_sub_1_2_8 = ~(req_addr[2]) & req_addr[1];
wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 | atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8;
wire atomics_a_mask_sub_2_2_8 = req_addr[2] & ~(req_addr[1]);
wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 | atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8;
wire atomics_a_mask_sub_3_2_8 = req_addr[2] & req_addr[1];
wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 | atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8;
wire _send_resp_T_7 = req_uop_mem_cmd == 5'h4;
wire _send_resp_T_8 = req_uop_mem_cmd == 5'h9;
wire _send_resp_T_9 = req_uop_mem_cmd == 5'hA;
wire _send_resp_T_10 = req_uop_mem_cmd == 5'hB;
wire _GEN = _send_resp_T_10 | _send_resp_T_9 | _send_resp_T_8 | _send_resp_T_7;
wire _send_resp_T_14 = req_uop_mem_cmd == 5'h8;
wire _send_resp_T_15 = req_uop_mem_cmd == 5'hC;
wire _send_resp_T_16 = req_uop_mem_cmd == 5'hD;
wire _send_resp_T_17 = req_uop_mem_cmd == 5'hE;
wire _send_resp_T_18 = req_uop_mem_cmd == 5'hF;
wire _GEN_0 = _send_resp_T_18 | _send_resp_T_17 | _send_resp_T_16 | _send_resp_T_15 | _send_resp_T_14;
wire [7:0] atomics_mask =
_send_resp_T_18
? {atomics_a_mask_sub_3_1_8 | atomics_a_mask_sub_3_2_8 & req_addr[0], atomics_a_mask_sub_3_1_8 | atomics_a_mask_sub_3_2_8 & ~(req_addr[0]), atomics_a_mask_sub_2_1_8 | atomics_a_mask_sub_2_2_8 & req_addr[0], atomics_a_mask_sub_2_1_8 | atomics_a_mask_sub_2_2_8 & ~(req_addr[0]), atomics_a_mask_sub_1_1_8 | atomics_a_mask_sub_1_2_8 & req_addr[0], atomics_a_mask_sub_1_1_8 | atomics_a_mask_sub_1_2_8 & ~(req_addr[0]), atomics_a_mask_sub_0_1_8 | atomics_a_mask_sub_0_2_8 & req_addr[0], atomics_a_mask_sub_0_1_8 | atomics_a_mask_sub_0_2_8 & ~(req_addr[0])}
: _send_resp_T_17
? {atomics_a_mask_sub_3_1_7 | atomics_a_mask_sub_3_2_7 & req_addr[0], atomics_a_mask_sub_3_1_7 | atomics_a_mask_sub_3_2_7 & ~(req_addr[0]), atomics_a_mask_sub_2_1_7 | atomics_a_mask_sub_2_2_7 & req_addr[0], atomics_a_mask_sub_2_1_7 | atomics_a_mask_sub_2_2_7 & ~(req_addr[0]), atomics_a_mask_sub_1_1_7 | atomics_a_mask_sub_1_2_7 & req_addr[0], atomics_a_mask_sub_1_1_7 | atomics_a_mask_sub_1_2_7 & ~(req_addr[0]), atomics_a_mask_sub_0_1_7 | atomics_a_mask_sub_0_2_7 & req_addr[0], atomics_a_mask_sub_0_1_7 | atomics_a_mask_sub_0_2_7 & ~(req_addr[0])}
: _send_resp_T_16
? {atomics_a_mask_sub_3_1_6 | atomics_a_mask_sub_3_2_6 & req_addr[0], atomics_a_mask_sub_3_1_6 | atomics_a_mask_sub_3_2_6 & ~(req_addr[0]), atomics_a_mask_sub_2_1_6 | atomics_a_mask_sub_2_2_6 & req_addr[0], atomics_a_mask_sub_2_1_6 | atomics_a_mask_sub_2_2_6 & ~(req_addr[0]), atomics_a_mask_sub_1_1_6 | atomics_a_mask_sub_1_2_6 & req_addr[0], atomics_a_mask_sub_1_1_6 | atomics_a_mask_sub_1_2_6 & ~(req_addr[0]), atomics_a_mask_sub_0_1_6 | atomics_a_mask_sub_0_2_6 & req_addr[0], atomics_a_mask_sub_0_1_6 | atomics_a_mask_sub_0_2_6 & ~(req_addr[0])}
: _send_resp_T_15
? {atomics_a_mask_sub_3_1_5 | atomics_a_mask_sub_3_2_5 & req_addr[0], atomics_a_mask_sub_3_1_5 | atomics_a_mask_sub_3_2_5 & ~(req_addr[0]), atomics_a_mask_sub_2_1_5 | atomics_a_mask_sub_2_2_5 & req_addr[0], atomics_a_mask_sub_2_1_5 | atomics_a_mask_sub_2_2_5 & ~(req_addr[0]), atomics_a_mask_sub_1_1_5 | atomics_a_mask_sub_1_2_5 & req_addr[0], atomics_a_mask_sub_1_1_5 | atomics_a_mask_sub_1_2_5 & ~(req_addr[0]), atomics_a_mask_sub_0_1_5 | atomics_a_mask_sub_0_2_5 & req_addr[0], atomics_a_mask_sub_0_1_5 | atomics_a_mask_sub_0_2_5 & ~(req_addr[0])}
: _send_resp_T_14
? {atomics_a_mask_sub_3_1_4 | atomics_a_mask_sub_3_2_4 & req_addr[0], atomics_a_mask_sub_3_1_4 | atomics_a_mask_sub_3_2_4 & ~(req_addr[0]), atomics_a_mask_sub_2_1_4 | atomics_a_mask_sub_2_2_4 & req_addr[0], atomics_a_mask_sub_2_1_4 | atomics_a_mask_sub_2_2_4 & ~(req_addr[0]), atomics_a_mask_sub_1_1_4 | atomics_a_mask_sub_1_2_4 & req_addr[0], atomics_a_mask_sub_1_1_4 | atomics_a_mask_sub_1_2_4 & ~(req_addr[0]), atomics_a_mask_sub_0_1_4 | atomics_a_mask_sub_0_2_4 & req_addr[0], atomics_a_mask_sub_0_1_4 | atomics_a_mask_sub_0_2_4 & ~(req_addr[0])}
: _send_resp_T_10
? {atomics_a_mask_sub_3_1_3 | atomics_a_mask_sub_3_2_3 & req_addr[0], atomics_a_mask_sub_3_1_3 | atomics_a_mask_sub_3_2_3 & ~(req_addr[0]), atomics_a_mask_sub_2_1_3 | atomics_a_mask_sub_2_2_3 & req_addr[0], atomics_a_mask_sub_2_1_3 | atomics_a_mask_sub_2_2_3 & ~(req_addr[0]), atomics_a_mask_sub_1_1_3 | atomics_a_mask_sub_1_2_3 & req_addr[0], atomics_a_mask_sub_1_1_3 | atomics_a_mask_sub_1_2_3 & ~(req_addr[0]), atomics_a_mask_sub_0_1_3 | atomics_a_mask_sub_0_2_3 & req_addr[0], atomics_a_mask_sub_0_1_3 | atomics_a_mask_sub_0_2_3 & ~(req_addr[0])}
: _send_resp_T_9 ? {atomics_a_mask_sub_3_1_2 | atomics_a_mask_sub_3_2_2 & req_addr[0], atomics_a_mask_sub_3_1_2 | atomics_a_mask_sub_3_2_2 & ~(req_addr[0]), atomics_a_mask_sub_2_1_2 | atomics_a_mask_sub_2_2_2 & req_addr[0], atomics_a_mask_sub_2_1_2 | atomics_a_mask_sub_2_2_2 & ~(req_addr[0]), atomics_a_mask_sub_1_1_2 | atomics_a_mask_sub_1_2_2 & req_addr[0], atomics_a_mask_sub_1_1_2 | atomics_a_mask_sub_1_2_2 & ~(req_addr[0]), atomics_a_mask_sub_0_1_2 | atomics_a_mask_sub_0_2_2 & req_addr[0], atomics_a_mask_sub_0_1_2 | atomics_a_mask_sub_0_2_2 & ~(req_addr[0])} : _send_resp_T_8 ? {atomics_a_mask_sub_3_1_1 | atomics_a_mask_sub_3_2_1 & req_addr[0], atomics_a_mask_sub_3_1_1 | atomics_a_mask_sub_3_2_1 & ~(req_addr[0]), atomics_a_mask_sub_2_1_1 | atomics_a_mask_sub_2_2_1 & req_addr[0], atomics_a_mask_sub_2_1_1 | atomics_a_mask_sub_2_2_1 & ~(req_addr[0]), atomics_a_mask_sub_1_1_1 | atomics_a_mask_sub_1_2_1 & req_addr[0], atomics_a_mask_sub_1_1_1 | atomics_a_mask_sub_1_2_1 & ~(req_addr[0]), atomics_a_mask_sub_0_1_1 | atomics_a_mask_sub_0_2_1 & req_addr[0], atomics_a_mask_sub_0_1_1 | atomics_a_mask_sub_0_2_1 & ~(req_addr[0])} : _send_resp_T_7 ? {atomics_a_mask_sub_3_1 | atomics_a_mask_sub_3_2 & req_addr[0], atomics_a_mask_sub_3_1 | atomics_a_mask_sub_3_2 & ~(req_addr[0]), atomics_a_mask_sub_2_1 | atomics_a_mask_sub_2_2 & req_addr[0], atomics_a_mask_sub_2_1 | atomics_a_mask_sub_2_2 & ~(req_addr[0]), atomics_a_mask_sub_1_1 | atomics_a_mask_sub_1_2 & req_addr[0], atomics_a_mask_sub_1_1 | atomics_a_mask_sub_1_2 & ~(req_addr[0]), atomics_a_mask_sub_0_1 | atomics_a_mask_sub_0_2 & req_addr[0], atomics_a_mask_sub_0_1 | atomics_a_mask_sub_0_2 & ~(req_addr[0])} : 8'h0;
wire io_mem_access_valid_0 = state == 2'h1;
wire _io_mem_access_bits_T_16 = _send_resp_T_7 | _send_resp_T_8 | _send_resp_T_9 | _send_resp_T_10 | _send_resp_T_14 | _send_resp_T_15 | _send_resp_T_16 | _send_resp_T_17 | _send_resp_T_18;
wire _send_resp_T = req_uop_mem_cmd == 5'h0;
wire _send_resp_T_1 = req_uop_mem_cmd == 5'h10;
wire _send_resp_T_2 = req_uop_mem_cmd == 5'h6;
wire _send_resp_T_3 = req_uop_mem_cmd == 5'h7;
wire _io_mem_access_bits_T_41 = _send_resp_T | _send_resp_T_1 | _send_resp_T_2 | _send_resp_T_3 | _send_resp_T_7 | _send_resp_T_8 | _send_resp_T_9 | _send_resp_T_10 | _send_resp_T_14 | _send_resp_T_15 | _send_resp_T_16 | _send_resp_T_17 | _send_resp_T_18;
wire _GEN_1 = ~_io_mem_access_bits_T_16 | _send_resp_T_18 | _send_resp_T_17 | _send_resp_T_16 | _send_resp_T_15 | _send_resp_T_14 | _send_resp_T_10 | _send_resp_T_9 | _send_resp_T_8 | _send_resp_T_7;
wire send_resp = _send_resp_T | _send_resp_T_1 | _send_resp_T_2 | _send_resp_T_3 | _send_resp_T_7 | _send_resp_T_8 | _send_resp_T_9 | _send_resp_T_10 | _send_resp_T_14 | _send_resp_T_15 | _send_resp_T_16 | _send_resp_T_17 | _send_resp_T_18;
wire io_resp_valid_0 = (&state) & send_resp;
wire [31:0] io_resp_bits_data_zeroed = req_addr[2] ? grant_word[63:32] : grant_word[31:0];
wire [15:0] io_resp_bits_data_zeroed_1 = req_addr[1] ? io_resp_bits_data_zeroed[31:16] : io_resp_bits_data_zeroed[15:0];
wire [7:0] io_resp_bits_data_zeroed_2 = req_addr[0] ? io_resp_bits_data_zeroed_1[15:8] : io_resp_bits_data_zeroed_1[7:0];
wire _GEN_2 = io_req_ready_0 & io_req_valid;
wire _GEN_3 = state == 2'h2 & io_mem_ack_valid;
always @(posedge clock) begin
if (_GEN_2) begin
req_uop_uopc <= io_req_bits_uop_uopc;
req_uop_inst <= io_req_bits_uop_inst;
req_uop_debug_inst <= io_req_bits_uop_debug_inst;
req_uop_is_rvc <= io_req_bits_uop_is_rvc;
req_uop_debug_pc <= io_req_bits_uop_debug_pc;
req_uop_iq_type <= io_req_bits_uop_iq_type;
req_uop_fu_code <= io_req_bits_uop_fu_code;
req_uop_ctrl_br_type <= io_req_bits_uop_ctrl_br_type;
req_uop_ctrl_op1_sel <= io_req_bits_uop_ctrl_op1_sel;
req_uop_ctrl_op2_sel <= io_req_bits_uop_ctrl_op2_sel;
req_uop_ctrl_imm_sel <= io_req_bits_uop_ctrl_imm_sel;
req_uop_ctrl_op_fcn <= io_req_bits_uop_ctrl_op_fcn;
req_uop_ctrl_fcn_dw <= io_req_bits_uop_ctrl_fcn_dw;
req_uop_ctrl_csr_cmd <= io_req_bits_uop_ctrl_csr_cmd;
req_uop_ctrl_is_load <= io_req_bits_uop_ctrl_is_load;
req_uop_ctrl_is_sta <= io_req_bits_uop_ctrl_is_sta;
req_uop_ctrl_is_std <= io_req_bits_uop_ctrl_is_std;
req_uop_iw_state <= io_req_bits_uop_iw_state;
req_uop_iw_p1_poisoned <= io_req_bits_uop_iw_p1_poisoned;
req_uop_iw_p2_poisoned <= io_req_bits_uop_iw_p2_poisoned;
req_uop_is_br <= io_req_bits_uop_is_br;
req_uop_is_jalr <= io_req_bits_uop_is_jalr;
req_uop_is_jal <= io_req_bits_uop_is_jal;
req_uop_is_sfb <= io_req_bits_uop_is_sfb;
req_uop_br_mask <= io_req_bits_uop_br_mask;
req_uop_br_tag <= io_req_bits_uop_br_tag;
req_uop_ftq_idx <= io_req_bits_uop_ftq_idx;
req_uop_edge_inst <= io_req_bits_uop_edge_inst;
req_uop_pc_lob <= io_req_bits_uop_pc_lob;
req_uop_taken <= io_req_bits_uop_taken;
req_uop_imm_packed <= io_req_bits_uop_imm_packed;
req_uop_csr_addr <= io_req_bits_uop_csr_addr;
req_uop_rob_idx <= io_req_bits_uop_rob_idx;
req_uop_ldq_idx <= io_req_bits_uop_ldq_idx;
req_uop_stq_idx <= io_req_bits_uop_stq_idx;
req_uop_rxq_idx <= io_req_bits_uop_rxq_idx;
req_uop_pdst <= io_req_bits_uop_pdst;
req_uop_prs1 <= io_req_bits_uop_prs1;
req_uop_prs2 <= io_req_bits_uop_prs2;
req_uop_prs3 <= io_req_bits_uop_prs3;
req_uop_ppred <= io_req_bits_uop_ppred;
req_uop_prs1_busy <= io_req_bits_uop_prs1_busy;
req_uop_prs2_busy <= io_req_bits_uop_prs2_busy;
req_uop_prs3_busy <= io_req_bits_uop_prs3_busy;
req_uop_ppred_busy <= io_req_bits_uop_ppred_busy;
req_uop_stale_pdst <= io_req_bits_uop_stale_pdst;
req_uop_exception <= io_req_bits_uop_exception;
req_uop_exc_cause <= io_req_bits_uop_exc_cause;
req_uop_bypassable <= io_req_bits_uop_bypassable;
req_uop_mem_cmd <= io_req_bits_uop_mem_cmd;
req_uop_mem_size <= io_req_bits_uop_mem_size;
req_uop_mem_signed <= io_req_bits_uop_mem_signed;
req_uop_is_fence <= io_req_bits_uop_is_fence;
req_uop_is_fencei <= io_req_bits_uop_is_fencei;
req_uop_is_amo <= io_req_bits_uop_is_amo;
req_uop_uses_ldq <= io_req_bits_uop_uses_ldq;
req_uop_uses_stq <= io_req_bits_uop_uses_stq;
req_uop_is_sys_pc2epc <= io_req_bits_uop_is_sys_pc2epc;
req_uop_is_unique <= io_req_bits_uop_is_unique;
req_uop_flush_on_commit <= io_req_bits_uop_flush_on_commit;
req_uop_ldst_is_rs1 <= io_req_bits_uop_ldst_is_rs1;
req_uop_ldst <= io_req_bits_uop_ldst;
req_uop_lrs1 <= io_req_bits_uop_lrs1;
req_uop_lrs2 <= io_req_bits_uop_lrs2;
req_uop_lrs3 <= io_req_bits_uop_lrs3;
req_uop_ldst_val <= io_req_bits_uop_ldst_val;
req_uop_dst_rtype <= io_req_bits_uop_dst_rtype;
req_uop_lrs1_rtype <= io_req_bits_uop_lrs1_rtype;
req_uop_lrs2_rtype <= io_req_bits_uop_lrs2_rtype;
req_uop_frs3_en <= io_req_bits_uop_frs3_en;
req_uop_fp_val <= io_req_bits_uop_fp_val;
req_uop_fp_single <= io_req_bits_uop_fp_single;
req_uop_xcpt_pf_if <= io_req_bits_uop_xcpt_pf_if;
req_uop_xcpt_ae_if <= io_req_bits_uop_xcpt_ae_if;
req_uop_xcpt_ma_if <= io_req_bits_uop_xcpt_ma_if;
req_uop_bp_debug_if <= io_req_bits_uop_bp_debug_if;
req_uop_bp_xcpt_if <= io_req_bits_uop_bp_xcpt_if;
req_uop_debug_fsrc <= io_req_bits_uop_debug_fsrc;
req_uop_debug_tsrc <= io_req_bits_uop_debug_tsrc;
req_addr <= io_req_bits_addr;
req_data <= io_req_bits_data;
req_is_hella <= io_req_bits_is_hella;
end
if (_GEN_3 & (_send_resp_T | _send_resp_T_1 | _send_resp_T_2 | _send_resp_T_3 | _GEN | _GEN_0))
grant_word <= io_mem_ack_bits_data;
if (reset)
state <= 2'h0;
else if ((&state) & (~send_resp | io_resp_ready & io_resp_valid_0))
state <= 2'h0;
else if (_GEN_3)
state <= 2'h3;
else if (io_mem_access_ready & io_mem_access_valid_0)
state <= 2'h2;
else if (_GEN_2)
state <= 2'h1;
end
assign io_req_ready = io_req_ready_0;
assign io_resp_valid = io_resp_valid_0;
assign io_resp_bits_uop_uopc = req_uop_uopc;
assign io_resp_bits_uop_inst = req_uop_inst;
assign io_resp_bits_uop_debug_inst = req_uop_debug_inst;
assign io_resp_bits_uop_is_rvc = req_uop_is_rvc;
assign io_resp_bits_uop_debug_pc = req_uop_debug_pc;
assign io_resp_bits_uop_iq_type = req_uop_iq_type;
assign io_resp_bits_uop_fu_code = req_uop_fu_code;
assign io_resp_bits_uop_ctrl_br_type = req_uop_ctrl_br_type;
assign io_resp_bits_uop_ctrl_op1_sel = req_uop_ctrl_op1_sel;
assign io_resp_bits_uop_ctrl_op2_sel = req_uop_ctrl_op2_sel;
assign io_resp_bits_uop_ctrl_imm_sel = req_uop_ctrl_imm_sel;
assign io_resp_bits_uop_ctrl_op_fcn = req_uop_ctrl_op_fcn;
assign io_resp_bits_uop_ctrl_fcn_dw = req_uop_ctrl_fcn_dw;
assign io_resp_bits_uop_ctrl_csr_cmd = req_uop_ctrl_csr_cmd;
assign io_resp_bits_uop_ctrl_is_load = req_uop_ctrl_is_load;
assign io_resp_bits_uop_ctrl_is_sta = req_uop_ctrl_is_sta;
assign io_resp_bits_uop_ctrl_is_std = req_uop_ctrl_is_std;
assign io_resp_bits_uop_iw_state = req_uop_iw_state;
assign io_resp_bits_uop_iw_p1_poisoned = req_uop_iw_p1_poisoned;
assign io_resp_bits_uop_iw_p2_poisoned = req_uop_iw_p2_poisoned;
assign io_resp_bits_uop_is_br = req_uop_is_br;
assign io_resp_bits_uop_is_jalr = req_uop_is_jalr;
assign io_resp_bits_uop_is_jal = req_uop_is_jal;
assign io_resp_bits_uop_is_sfb = req_uop_is_sfb;
assign io_resp_bits_uop_br_mask = req_uop_br_mask;
assign io_resp_bits_uop_br_tag = req_uop_br_tag;
assign io_resp_bits_uop_ftq_idx = req_uop_ftq_idx;
assign io_resp_bits_uop_edge_inst = req_uop_edge_inst;
assign io_resp_bits_uop_pc_lob = req_uop_pc_lob;
assign io_resp_bits_uop_taken = req_uop_taken;
assign io_resp_bits_uop_imm_packed = req_uop_imm_packed;
assign io_resp_bits_uop_csr_addr = req_uop_csr_addr;
assign io_resp_bits_uop_rob_idx = req_uop_rob_idx;
assign io_resp_bits_uop_ldq_idx = req_uop_ldq_idx;
assign io_resp_bits_uop_stq_idx = req_uop_stq_idx;
assign io_resp_bits_uop_rxq_idx = req_uop_rxq_idx;
assign io_resp_bits_uop_pdst = req_uop_pdst;
assign io_resp_bits_uop_prs1 = req_uop_prs1;
assign io_resp_bits_uop_prs2 = req_uop_prs2;
assign io_resp_bits_uop_prs3 = req_uop_prs3;
assign io_resp_bits_uop_ppred = req_uop_ppred;
assign io_resp_bits_uop_prs1_busy = req_uop_prs1_busy;
assign io_resp_bits_uop_prs2_busy = req_uop_prs2_busy;
assign io_resp_bits_uop_prs3_busy = req_uop_prs3_busy;
assign io_resp_bits_uop_ppred_busy = req_uop_ppred_busy;
assign io_resp_bits_uop_stale_pdst = req_uop_stale_pdst;
assign io_resp_bits_uop_exception = req_uop_exception;
assign io_resp_bits_uop_exc_cause = req_uop_exc_cause;
assign io_resp_bits_uop_bypassable = req_uop_bypassable;
assign io_resp_bits_uop_mem_cmd = req_uop_mem_cmd;
assign io_resp_bits_uop_mem_size = req_uop_mem_size;
assign io_resp_bits_uop_mem_signed = req_uop_mem_signed;
assign io_resp_bits_uop_is_fence = req_uop_is_fence;
assign io_resp_bits_uop_is_fencei = req_uop_is_fencei;
assign io_resp_bits_uop_is_amo = req_uop_is_amo;
assign io_resp_bits_uop_uses_ldq = req_uop_uses_ldq;
assign io_resp_bits_uop_uses_stq = req_uop_uses_stq;
assign io_resp_bits_uop_is_sys_pc2epc = req_uop_is_sys_pc2epc;
assign io_resp_bits_uop_is_unique = req_uop_is_unique;
assign io_resp_bits_uop_flush_on_commit = req_uop_flush_on_commit;
assign io_resp_bits_uop_ldst_is_rs1 = req_uop_ldst_is_rs1;
assign io_resp_bits_uop_ldst = req_uop_ldst;
assign io_resp_bits_uop_lrs1 = req_uop_lrs1;
assign io_resp_bits_uop_lrs2 = req_uop_lrs2;
assign io_resp_bits_uop_lrs3 = req_uop_lrs3;
assign io_resp_bits_uop_ldst_val = req_uop_ldst_val;
assign io_resp_bits_uop_dst_rtype = req_uop_dst_rtype;
assign io_resp_bits_uop_lrs1_rtype = req_uop_lrs1_rtype;
assign io_resp_bits_uop_lrs2_rtype = req_uop_lrs2_rtype;
assign io_resp_bits_uop_frs3_en = req_uop_frs3_en;
assign io_resp_bits_uop_fp_val = req_uop_fp_val;
assign io_resp_bits_uop_fp_single = req_uop_fp_single;
assign io_resp_bits_uop_xcpt_pf_if = req_uop_xcpt_pf_if;
assign io_resp_bits_uop_xcpt_ae_if = req_uop_xcpt_ae_if;
assign io_resp_bits_uop_xcpt_ma_if = req_uop_xcpt_ma_if;
assign io_resp_bits_uop_bp_debug_if = req_uop_bp_debug_if;
assign io_resp_bits_uop_bp_xcpt_if = req_uop_bp_xcpt_if;
assign io_resp_bits_uop_debug_fsrc = req_uop_debug_fsrc;
assign io_resp_bits_uop_debug_tsrc = req_uop_debug_tsrc;
assign io_resp_bits_data = {req_uop_mem_size == 2'h0 ? {56{req_uop_mem_signed & io_resp_bits_data_zeroed_2[7]}} : {req_uop_mem_size == 2'h1 ? {48{req_uop_mem_signed & io_resp_bits_data_zeroed_1[15]}} : {req_uop_mem_size == 2'h2 ? {32{req_uop_mem_signed & io_resp_bits_data_zeroed[31]}} : grant_word[63:32], io_resp_bits_data_zeroed[31:16]}, io_resp_bits_data_zeroed_1[15:8]}, io_resp_bits_data_zeroed_2};
assign io_resp_bits_is_hella = req_is_hella;
assign io_mem_access_valid = io_mem_access_valid_0;
assign io_mem_access_bits_opcode = _io_mem_access_bits_T_16 ? (_GEN_0 ? 3'h2 : _GEN ? 3'h3 : 3'h0) : {_io_mem_access_bits_T_41, 2'h0};
assign io_mem_access_bits_param = _io_mem_access_bits_T_16 ? (_send_resp_T_18 ? 3'h3 : _send_resp_T_17 ? 3'h2 : _send_resp_T_16 ? 3'h1 : _send_resp_T_15 ? 3'h0 : _send_resp_T_14 ? 3'h4 : _send_resp_T_10 ? 3'h2 : _send_resp_T_9 ? 3'h1 : _send_resp_T_8 | ~_send_resp_T_7 ? 3'h0 : 3'h3) : 3'h0;
assign io_mem_access_bits_size = _GEN_1 ? {2'h0, req_uop_mem_size} : 4'h0;
assign io_mem_access_bits_source = _io_mem_access_bits_T_16 ? {2{_send_resp_T_18 | _send_resp_T_17 | _send_resp_T_16 | _send_resp_T_15 | _send_resp_T_14 | _GEN}} : 2'h3;
assign io_mem_access_bits_address = _GEN_1 ? req_addr[31:0] : 32'h0;
assign io_mem_access_bits_mask = _io_mem_access_bits_T_16 ? atomics_mask : _io_mem_access_bits_T_41 ? {get_a_mask_sub_3_1 | get_a_mask_sub_3_2 & req_addr[0], get_a_mask_sub_3_1 | get_a_mask_sub_3_2 & ~(req_addr[0]), get_a_mask_sub_2_1 | get_a_mask_sub_2_2 & req_addr[0], get_a_mask_sub_2_1 | get_a_mask_sub_2_2 & ~(req_addr[0]), get_a_mask_sub_1_1 | get_a_mask_sub_1_2 & req_addr[0], get_a_mask_sub_1_1 | get_a_mask_sub_1_2 & ~(req_addr[0]), get_a_mask_sub_0_1 | get_a_mask_sub_0_2 & req_addr[0], get_a_mask_sub_0_1 | get_a_mask_sub_0_2 & ~(req_addr[0])} : {put_a_mask_sub_3_1 | put_a_mask_sub_3_2 & req_addr[0], put_a_mask_sub_3_1 | put_a_mask_sub_3_2 & ~(req_addr[0]), put_a_mask_sub_2_1 | put_a_mask_sub_2_2 & req_addr[0], put_a_mask_sub_2_1 | put_a_mask_sub_2_2 & ~(req_addr[0]), put_a_mask_sub_1_1 | put_a_mask_sub_1_2 & req_addr[0], put_a_mask_sub_1_1 | put_a_mask_sub_1_2 & ~(req_addr[0]), put_a_mask_sub_0_1 | put_a_mask_sub_0_2 & req_addr[0], put_a_mask_sub_0_1 | put_a_mask_sub_0_2 & ~(req_addr[0])};
assign io_mem_access_bits_data = _io_mem_access_bits_T_16 ? (_send_resp_T_18 | _send_resp_T_17 | _send_resp_T_16 | _send_resp_T_15 | _send_resp_T_14 | _send_resp_T_10 | _send_resp_T_9 | _send_resp_T_8 | _send_resp_T_7 ? req_data : 64'h0) : _io_mem_access_bits_T_41 ? 64'h0 : req_data;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
} | module rockettile_icache_data_arrays_1(
input [8:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [255:0] RW0_wdata,
output [255:0] RW0_rdata,
input [7:0] RW0_wmask
);
rockettile_icache_data_arrays_0_ext rockettile_icache_data_arrays_0_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class SourceBRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val param = UInt(3.W)
val tag = UInt(params.tagBits.W)
val set = UInt(params.setBits.W)
val clients = UInt(params.clientBits.W)
}
class SourceB(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val req = Flipped(Decoupled(new SourceBRequest(params)))
val b = Decoupled(new TLBundleB(params.inner.bundle))
})
if (params.firstLevel) {
// Tie off unused ports
io.req.ready := true.B
io.b.valid := false.B
io.b.bits := DontCare
} else {
val remain = RegInit(0.U(params.clientBits.W))
val remain_set = WireInit(init = 0.U(params.clientBits.W))
val remain_clr = WireInit(init = 0.U(params.clientBits.W))
remain := (remain | remain_set) & ~remain_clr
val busy = remain.orR
val todo = Mux(busy, remain, io.req.bits.clients)
val next = ~(leftOR(todo) << 1) & todo
if (params.clientBits > 1) {
params.ccover(PopCount(remain) > 1.U, "SOURCEB_MULTI_PROBE", "Had to probe more than one client")
}
assert (!io.req.valid || io.req.bits.clients =/= 0.U)
io.req.ready := !busy
when (io.req.fire) { remain_set := io.req.bits.clients }
// No restrictions on the type of buffer used here
val b = Wire(chiselTypeOf(io.b))
io.b <> params.micro.innerBuf.b(b)
b.valid := busy || io.req.valid
when (b.fire) { remain_clr := next }
params.ccover(b.valid && !b.ready, "SOURCEB_STALL", "Backpressured when issuing a probe")
val tag = Mux(!busy, io.req.bits.tag, RegEnable(io.req.bits.tag, io.req.fire))
val set = Mux(!busy, io.req.bits.set, RegEnable(io.req.bits.set, io.req.fire))
val param = Mux(!busy, io.req.bits.param, RegEnable(io.req.bits.param, io.req.fire))
b.bits.opcode := TLMessages.Probe
b.bits.param := param
b.bits.size := params.offsetBits .U
b.bits.source := params.clientSource(next)
b.bits.address := params.expandAddress(tag, set, 0.U)
b.bits.mask := ~0.U(params.inner.manager.beatBytes.W)
b.bits.data := 0.U
b.bits.corrupt := false.B
}
} | module SourceB(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [2:0] io_req_bits_param,
input [12:0] io_req_bits_tag,
input [9:0] io_req_bits_set,
input io_req_bits_clients,
input io_b_ready,
output io_b_valid,
output [1:0] io_b_bits_param,
output [31:0] io_b_bits_address
);
reg busy;
wire _param_T_1 = ~busy & io_req_valid;
wire b_valid = busy | io_req_valid;
reg [12:0] tag_r;
wire [12:0] tag = busy ? tag_r : io_req_bits_tag;
reg [9:0] set_r;
reg [2:0] param_r;
always @(posedge clock) begin
if (reset)
busy <= 1'h0;
else
busy <= (busy | _param_T_1 & io_req_bits_clients) & ~(io_b_ready & b_valid & (busy ? busy : io_req_bits_clients));
if (_param_T_1) begin
tag_r <= io_req_bits_tag;
set_r <= io_req_bits_set;
param_r <= io_req_bits_param;
end
end
assign io_req_ready = ~busy;
assign io_b_valid = b_valid;
assign io_b_bits_param = busy ? param_r[1:0] : io_req_bits_param[1:0];
assign io_b_bits_address = {tag[12], 3'h0, tag[11:0], busy ? set_r : io_req_bits_set, 6'h0};
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
class CompareRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
val io = IO(new Bundle {
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val signaling = Input(Bool())
val lt = Output(Bool())
val eq = Output(Bool())
val gt = Output(Bool())
val exceptionFlags = Output(Bits(5.W))
})
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val ordered = ! rawA.isNaN && ! rawB.isNaN
val bothInfs = rawA.isInf && rawB.isInf
val bothZeros = rawA.isZero && rawB.isZero
val eqExps = (rawA.sExp === rawB.sExp)
val common_ltMags =
(rawA.sExp < rawB.sExp) || (eqExps && (rawA.sig < rawB.sig))
val common_eqMags = eqExps && (rawA.sig === rawB.sig)
val ordered_lt =
! bothZeros &&
((rawA.sign && ! rawB.sign) ||
(! bothInfs &&
((rawA.sign && ! common_ltMags && ! common_eqMags) ||
(! rawB.sign && common_ltMags))))
val ordered_eq =
bothZeros || ((rawA.sign === rawB.sign) && (bothInfs || common_eqMags))
val invalid =
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
(io.signaling && ! ordered)
io.lt := ordered && ordered_lt
io.eq := ordered && ordered_eq
io.gt := ordered && ! ordered_lt && ! ordered_eq
io.exceptionFlags := invalid ## 0.U(4.W)
} | module CompareRecFN(
input [64:0] io_a,
input [64:0] io_b,
input io_signaling,
output io_lt,
output io_eq,
output [4:0] io_exceptionFlags
);
wire rawA_isNaN = (&(io_a[63:62])) & io_a[61];
wire rawB_isNaN = (&(io_b[63:62])) & io_b[61];
wire ordered = ~rawA_isNaN & ~rawB_isNaN;
wire bothInfs = (&(io_a[63:62])) & ~(io_a[61]) & (&(io_b[63:62])) & ~(io_b[61]);
wire bothZeros = ~(|(io_a[63:61])) & ~(|(io_b[63:61]));
wire eqExps = io_a[63:52] == io_b[63:52];
wire [52:0] _GEN = {|(io_a[63:61]), io_a[51:0]};
wire [52:0] _GEN_0 = {|(io_b[63:61]), io_b[51:0]};
wire common_ltMags = $signed({1'h0, io_a[63:52]}) < $signed({1'h0, io_b[63:52]}) | eqExps & _GEN < _GEN_0;
wire common_eqMags = eqExps & _GEN == _GEN_0;
assign io_lt = ordered & ~bothZeros & (io_a[64] & ~(io_b[64]) | ~bothInfs & (io_a[64] & ~common_ltMags & ~common_eqMags | ~(io_b[64]) & common_ltMags));
assign io_eq = ordered & (bothZeros | io_a[64] == io_b[64] & (bothInfs | common_eqMags));
assign io_exceptionFlags = {rawA_isNaN & ~(io_a[51]) | rawB_isNaN & ~(io_b[51]) | io_signaling & ~ordered, 4'h0};
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
class ExpandedInstruction extends Bundle {
val bits = UInt(32.W)
val rd = UInt(5.W)
val rs1 = UInt(5.W)
val rs2 = UInt(5.W)
val rs3 = UInt(5.W)
}
class RVCDecoder(x: UInt, xLen: Int, fLen: Int, useAddiForMv: Boolean = false) {
def inst(bits: UInt, rd: UInt = x(11,7), rs1: UInt = x(19,15), rs2: UInt = x(24,20), rs3: UInt = x(31,27)) = {
val res = Wire(new ExpandedInstruction)
res.bits := bits
res.rd := rd
res.rs1 := rs1
res.rs2 := rs2
res.rs3 := rs3
res
}
def rs1p = Cat(1.U(2.W), x(9,7))
def rs2p = Cat(1.U(2.W), x(4,2))
def rs2 = x(6,2)
def rd = x(11,7)
def addi4spnImm = Cat(x(10,7), x(12,11), x(5), x(6), 0.U(2.W))
def lwImm = Cat(x(5), x(12,10), x(6), 0.U(2.W))
def ldImm = Cat(x(6,5), x(12,10), 0.U(3.W))
def lwspImm = Cat(x(3,2), x(12), x(6,4), 0.U(2.W))
def ldspImm = Cat(x(4,2), x(12), x(6,5), 0.U(3.W))
def swspImm = Cat(x(8,7), x(12,9), 0.U(2.W))
def sdspImm = Cat(x(9,7), x(12,10), 0.U(3.W))
def luiImm = Cat(Fill(15, x(12)), x(6,2), 0.U(12.W))
def addi16spImm = Cat(Fill(3, x(12)), x(4,3), x(5), x(2), x(6), 0.U(4.W))
def addiImm = Cat(Fill(7, x(12)), x(6,2))
def jImm = Cat(Fill(10, x(12)), x(8), x(10,9), x(6), x(7), x(2), x(11), x(5,3), 0.U(1.W))
def bImm = Cat(Fill(5, x(12)), x(6,5), x(2), x(11,10), x(4,3), 0.U(1.W))
def shamt = Cat(x(12), x(6,2))
def x0 = 0.U(5.W)
def ra = 1.U(5.W)
def sp = 2.U(5.W)
def q0 = {
def addi4spn = {
val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W))
inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p)
}
def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
def flw = {
if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
else ld
}
def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p)
def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
def fsw = {
if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
else sd
}
Seq(addi4spn, fld, lw, flw, unimp, fsd, sw, fsw)
}
def q1 = {
def addi = inst(Cat(addiImm, rd, 0.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2p)
def addiw = {
val opc = Mux(rd.orR, 0x1B.U(7.W), 0x1F.U(7.W))
inst(Cat(addiImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p)
}
def jal = {
if (xLen == 32) inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), ra, 0x6F.U(7.W)), ra, rd, rs2p)
else addiw
}
def li = inst(Cat(addiImm, x0, 0.U(3.W), rd, 0x13.U(7.W)), rd, x0, rs2p)
def addi16sp = {
val opc = Mux(addiImm.orR, 0x13.U(7.W), 0x1F.U(7.W))
inst(Cat(addi16spImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p)
}
def lui = {
val opc = Mux(addiImm.orR, 0x37.U(7.W), 0x3F.U(7.W))
val me = inst(Cat(luiImm(31,12), rd, opc), rd, rd, rs2p)
Mux(rd === x0 || rd === sp, addi16sp, me)
}
def j = inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), x0, 0x6F.U(7.W)), x0, rs1p, rs2p)
def beqz = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 0.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), rs1p, rs1p, x0)
def bnez = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 1.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), x0, rs1p, x0)
def arith = {
def srli = Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W))
def srai = srli | (1 << 30).U
def andi = Cat(addiImm, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W))
def rtype = {
val funct = Seq(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 2.U, 3.U)(Cat(x(12), x(6,5)))
val sub = Mux(x(6,5) === 0.U, (1 << 30).U, 0.U)
val opc = Mux(x(12), 0x3B.U(7.W), 0x33.U(7.W))
Cat(rs2p, rs1p, funct, rs1p, opc) | sub
}
inst(Seq(srli, srai, andi, rtype)(x(11,10)), rs1p, rs1p, rs2p)
}
Seq(addi, jal, li, lui, arith, j, beqz, bnez)
}
def q2 = {
val load_opc = Mux(rd.orR, 0x03.U(7.W), 0x1F.U(7.W))
def slli = inst(Cat(shamt, rd, 1.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2)
def ldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, load_opc), rd, sp, rs2)
def lwsp = inst(Cat(lwspImm, sp, 2.U(3.W), rd, load_opc), rd, sp, rs2)
def fldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2)
def flwsp = {
if (xLen == 32) inst(Cat(lwspImm, sp, 2.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2)
else ldsp
}
def sdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x23.U(7.W)), rd, sp, rs2)
def swsp = inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x23.U(7.W)), rd, sp, rs2)
def fsdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x27.U(7.W)), rd, sp, rs2)
def fswsp = {
if (xLen == 32) inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x27.U(7.W)), rd, sp, rs2)
else sdsp
}
def jalr = {
val mv = {
if (useAddiForMv) inst(Cat(rs2, 0.U(3.W), rd, 0x13.U(7.W)), rd, rs2, x0)
else inst(Cat(rs2, x0, 0.U(3.W), rd, 0x33.U(7.W)), rd, x0, rs2)
}
val add = inst(Cat(rs2, rd, 0.U(3.W), rd, 0x33.U(7.W)), rd, rd, rs2)
val jr = Cat(rs2, rd, 0.U(3.W), x0, 0x67.U(7.W))
val reserved = Cat(jr >> 7, 0x1F.U(7.W))
val jr_reserved = inst(Mux(rd.orR, jr, reserved), x0, rd, rs2)
val jr_mv = Mux(rs2.orR, mv, jr_reserved)
val jalr = Cat(rs2, rd, 0.U(3.W), ra, 0x67.U(7.W))
val ebreak = Cat(jr >> 7, 0x73.U(7.W)) | (1 << 20).U
val jalr_ebreak = inst(Mux(rd.orR, jalr, ebreak), ra, rd, rs2)
val jalr_add = Mux(rs2.orR, add, jalr_ebreak)
Mux(x(12), jalr_add, jr_mv)
}
Seq(slli, fldsp, lwsp, flwsp, jalr, fsdsp, swsp, fswsp)
}
def q3 = Seq.fill(8)(passthrough)
def passthrough = inst(x)
def decode = {
val s = q0 ++ q1 ++ q2 ++ q3
s(Cat(x(1,0), x(15,13)))
}
def q0_ill = {
def allz = !(x(12, 2).orR)
def fld = if (fLen >= 64) false.B else true.B
def flw32 = if (xLen == 64 || fLen >= 32) false.B else true.B
def fsd = if (fLen >= 64) false.B else true.B
def fsw32 = if (xLen == 64 || fLen >= 32) false.B else true.B
Seq(allz, fld, false.B, flw32, true.B, fsd, false.B, fsw32)
}
def q1_ill = {
def rd0 = if (xLen == 32) false.B else rd === 0.U
def immz = !(x(12) | x(6, 2).orR)
def arith_res = x(12, 10).andR && (if (xLen == 32) true.B else x(6) === 1.U)
Seq(false.B, rd0, false.B, immz, arith_res, false.B, false.B, false.B)
}
def q2_ill = {
def fldsp = if (fLen >= 64) false.B else true.B
def rd0 = rd === 0.U
def flwsp = if (xLen == 64) rd0 else if (fLen >= 32) false.B else true.B
def jr_res = !(x(12 ,2).orR)
def fsdsp = if (fLen >= 64) false.B else true.B
def fswsp32 = if (xLen == 64) false.B else if (fLen >= 32) false.B else true.B
Seq(false.B, fldsp, rd0, flwsp, jr_res, fsdsp, false.B, fswsp32)
}
def q3_ill = Seq.fill(8)(false.B)
def ill = {
val s = q0_ill ++ q1_ill ++ q2_ill ++ q3_ill
s(Cat(x(1,0), x(15,13)))
}
}
class RVCExpander(useAddiForMv: Boolean = false)(implicit val p: Parameters) extends Module with HasCoreParameters {
val io = IO(new Bundle {
val in = Input(UInt(32.W))
val out = Output(new ExpandedInstruction)
val rvc = Output(Bool())
val ill = Output(Bool())
})
if (usingCompressed) {
io.rvc := io.in(1,0) =/= 3.U
val decoder = new RVCDecoder(io.in, xLen, fLen, useAddiForMv)
io.out := decoder.decode
io.ill := decoder.ill
} else {
io.rvc := false.B
io.out := new RVCDecoder(io.in, xLen, fLen, useAddiForMv).passthrough
io.ill := false.B // only used for RVC
}
} | module RVCExpander(
input [31:0] io_in,
output [31:0] io_out_bits,
output io_rvc
);
wire [2:0] _io_out_s_funct_T_2 = {io_in[12], io_in[6:5]};
wire [2:0] _io_out_s_funct_T_4 = {_io_out_s_funct_T_2 == 3'h1, 2'h0};
wire [7:0][2:0] _GEN = {{3'h3}, {3'h2}, {3'h0}, {3'h0}, {3'h7}, {3'h6}, {_io_out_s_funct_T_4}, {_io_out_s_funct_T_4}};
wire [3:0] _GEN_0 = {4{io_in[12]}};
wire [6:0] io_out_s_load_opc = (|(io_in[11:7])) ? 7'h3 : 7'h1F;
wire [4:0] _io_out_T_2 = {io_in[1:0], io_in[15:13]};
wire [31:0] _io_out_T_42_bits =
_io_out_T_2 == 5'h14
? {7'h0, io_in[12] ? ((|(io_in[6:2])) ? {io_in[6:2], io_in[11:7], 3'h0, io_in[11:7], 7'h33} : (|(io_in[11:7])) ? {io_in[6:2], io_in[11:7], 15'hE7} : {io_in[6:3], 1'h1, io_in[11:7], 15'h73}) : {io_in[6:2], (|(io_in[6:2])) ? {8'h0, io_in[11:7], 7'h33} : {io_in[11:7], (|(io_in[11:7])) ? 15'h67 : 15'h1F}}}
: _io_out_T_2 == 5'h13
? {3'h0, io_in[4:2], io_in[12], io_in[6:5], 11'h13, io_in[11:7], io_out_s_load_opc}
: _io_out_T_2 == 5'h12
? {4'h0, io_in[3:2], io_in[12], io_in[6:4], 10'h12, io_in[11:7], io_out_s_load_opc}
: _io_out_T_2 == 5'h11
? {3'h0, io_in[4:2], io_in[12], io_in[6:5], 11'h13, io_in[11:7], 7'h7}
: _io_out_T_2 == 5'h10
? {6'h0, io_in[12], io_in[6:2], io_in[11:7], 3'h1, io_in[11:7], 7'h13}
: _io_out_T_2 == 5'hF
? {_GEN_0, io_in[6:5], io_in[2], 7'h1, io_in[9:7], 3'h1, io_in[11:10], io_in[4:3], io_in[12], 7'h63}
: _io_out_T_2 == 5'hE
? {_GEN_0, io_in[6:5], io_in[2], 7'h1, io_in[9:7], 3'h0, io_in[11:10], io_in[4:3], io_in[12], 7'h63}
: _io_out_T_2 == 5'hD ? {io_in[12], io_in[8], io_in[10:9], io_in[6], io_in[7], io_in[2], io_in[11], io_in[5:3], {9{io_in[12]}}, 12'h6F} : _io_out_T_2 == 5'hC ? ((&(io_in[11:10])) ? {1'h0, io_in[6:5] == 2'h0, 7'h1, io_in[4:2], 2'h1, io_in[9:7], _GEN[_io_out_s_funct_T_2], 2'h1, io_in[9:7], 3'h3, io_in[12], 3'h3} : {io_in[11:10] == 2'h2 ? {{7{io_in[12]}}, io_in[6:2], 2'h1, io_in[9:7], 5'h1D} : {1'h0, io_in[11:10] == 2'h1, 4'h0, io_in[12], io_in[6:2], 2'h1, io_in[9:7], 5'h15}, io_in[9:7], 7'h13}) : _io_out_T_2 == 5'hB ? {{3{io_in[12]}}, io_in[11:7] == 5'h0 | io_in[11:7] == 5'h2 ? {io_in[4:3], io_in[5], io_in[2], io_in[6], 4'h0, io_in[11:7], 3'h0, io_in[11:7], (|{{7{io_in[12]}}, io_in[6:2]}) ? 7'h13 : 7'h1F} : {{12{io_in[12]}}, io_in[6:2], io_in[11:7], 3'h3, {{7{io_in[12]}}, io_in[6:2]} == 12'h0, 3'h7}} : _io_out_T_2 == 5'hA ? {{7{io_in[12]}}, io_in[6:2], 8'h0, io_in[11:7], 7'h13} : _io_out_T_2 == 5'h9 ? {{7{io_in[12]}}, io_in[6:2], io_in[11:7], 3'h0, io_in[11:7], 4'h3, io_in[11:7] == 5'h0, 2'h3} : _io_out_T_2 == 5'h8 ? {{7{io_in[12]}}, io_in[6:2], io_in[11:7], 3'h0, io_in[11:7], 7'h13} : _io_out_T_2 == 5'h7 ? {4'h0, io_in[6:5], io_in[12], 2'h1, io_in[4:2], 2'h1, io_in[9:7], 3'h3, io_in[11:10], 10'h23} : _io_out_T_2 == 5'h6 ? {5'h0, io_in[5], io_in[12], 2'h1, io_in[4:2], 2'h1, io_in[9:7], 3'h2, io_in[11:10], io_in[6], 9'h23} : _io_out_T_2 == 5'h5 ? {4'h0, io_in[6:5], io_in[12], 2'h1, io_in[4:2], 2'h1, io_in[9:7], 3'h3, io_in[11:10], 10'h27} : _io_out_T_2 == 5'h4 ? {5'h0, io_in[5], io_in[12], 2'h1, io_in[4:2], 2'h1, io_in[9:7], 3'h2, io_in[11:10], io_in[6], 9'h3F} : _io_out_T_2 == 5'h3 ? {4'h0, io_in[6:5], io_in[12:10], 5'h1, io_in[9:7], 5'hD, io_in[4:2], 7'h3} : _io_out_T_2 == 5'h2 ? {5'h0, io_in[5], io_in[12:10], io_in[6], 4'h1, io_in[9:7], 5'h9, io_in[4:2], 7'h3} : _io_out_T_2 == 5'h1 ? {4'h0, io_in[6:5], io_in[12:10], 5'h1, io_in[9:7], 5'hD, io_in[4:2], 7'h7} : {2'h0, io_in[10:7], io_in[12:11], io_in[5], io_in[6], 12'h41, io_in[4:2], (|(io_in[12:5])) ? 7'h13 : 7'h1F};
assign io_out_bits = (&_io_out_T_2) | _io_out_T_2 == 5'h1E | _io_out_T_2 == 5'h1D | _io_out_T_2 == 5'h1C | _io_out_T_2 == 5'h1B | _io_out_T_2 == 5'h1A | _io_out_T_2 == 5'h19 | _io_out_T_2 == 5'h18 ? io_in : _io_out_T_2 == 5'h17 ? {3'h0, io_in[9:7], io_in[12], io_in[6:2], 8'h13, io_in[11:10], 10'h23} : _io_out_T_2 == 5'h16 ? {4'h0, io_in[8:7], io_in[12], io_in[6:2], 8'h12, io_in[11:9], 9'h23} : _io_out_T_2 == 5'h15 ? {3'h0, io_in[9:7], io_in[12], io_in[6:2], 8'h13, io_in[11:10], 10'h27} : _io_out_T_42_bits;
assign io_rvc = io_in[1:0] != 2'h3;
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.uart
import chisel3._
import chisel3.util._
import chisel3.experimental.{IntParam}
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import sifive.blocks.devices.uart._
import testchipip.serdes.{SerialIO}
object UARTAdapterConsts {
val DATA_WIDTH = 8
}
import UARTAdapterConsts._
/**
* Module to connect with a DUT UART and converts the UART signal to/from DATA_WIDTH
* packets.
*
* @param uartno the uart number
* @param div the divisor (equal to the clock frequency divided by the baud rate)
*/
class UARTAdapter(uartno: Int, div: Int, forcePty: Boolean) extends Module
{
val io = IO(new Bundle {
val uart = Flipped(new UARTPortIO(UARTParams(address = 0))) // We do not support the four wire variant
})
val sim = Module(new SimUART(uartno, forcePty))
val uartParams = UARTParams(0)
val txm = Module(new UARTRx(uartParams))
val txq = Module(new Queue(UInt(uartParams.dataBits.W), uartParams.nTxEntries))
val rxm = Module(new UARTTx(uartParams))
val rxq = Module(new Queue(UInt(uartParams.dataBits.W), uartParams.nRxEntries))
sim.io.clock := clock
sim.io.reset := reset.asBool
txm.io.en := true.B
txm.io.in := io.uart.txd
txm.io.div := div.U
txq.io.enq.valid := txm.io.out.valid
txq.io.enq.bits := txm.io.out.bits
when (txq.io.enq.valid) { assert(txq.io.enq.ready) }
rxm.io.en := true.B
rxm.io.in <> rxq.io.deq
rxm.io.div := div.U
rxm.io.nstop := 0.U
io.uart.rxd := rxm.io.out
sim.io.serial.out.bits := txq.io.deq.bits
sim.io.serial.out.valid := txq.io.deq.valid
txq.io.deq.ready := sim.io.serial.out.ready
rxq.io.enq.bits := sim.io.serial.in.bits
rxq.io.enq.valid := sim.io.serial.in.valid
sim.io.serial.in.ready := rxq.io.enq.ready && rxq.io.count < (uartParams.nRxEntries - 1).U
}
object UARTAdapter {
var uartno = 0
def connect(uart: Seq[UARTPortIO], baudrate: BigInt = 115200, forcePty: Boolean = false)(implicit p: Parameters) {
UARTAdapter.connect(uart, baudrate, p(PeripheryBusKey).dtsFrequency.get, forcePty)
}
def connect(uart: Seq[UARTPortIO], baudrate: BigInt, clockFrequency: BigInt, forcePty: Boolean) {
val div = (clockFrequency / baudrate).toInt
UARTAdapter.connect(uart, div, forcePty)
}
def connect(uart: Seq[UARTPortIO], div: Int, forcePty: Boolean) {
uart.zipWithIndex.foreach { case (dut_io, i) =>
val uart_sim = Module(new UARTAdapter(uartno, div, forcePty))
uart_sim.suggestName(s"uart_sim_${i}_uartno${uartno}")
uart_sim.io.uart.txd := dut_io.txd
dut_io.rxd := uart_sim.io.uart.rxd
uartno += 1
}
}
}
/**
* Module to connect to a *.v blackbox that uses DPI calls to interact with the DUT UART.
*
* @param uartno the uart number
*/
class SimUART(uartno: Int, forcePty: Boolean) extends BlackBox(Map(
"UARTNO" -> IntParam(uartno),
"FORCEPTY" -> IntParam(if (forcePty) 1 else 0)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val clock = Input(Clock())
val reset = Input(Bool())
val serial = Flipped(new SerialIO(DATA_WIDTH))
})
addResource("/testchipip/vsrc/SimUART.v")
addResource("/testchipip/csrc/SimUART.cc")
addResource("/testchipip/csrc/uart.cc")
addResource("/testchipip/csrc/uart.h")
} | module UARTAdapter(
input clock,
input reset,
input io_uart_txd,
output io_uart_rxd
);
wire _rxq_io_enq_ready;
wire _rxq_io_deq_valid;
wire [7:0] _rxq_io_deq_bits;
wire [3:0] _rxq_io_count;
wire _rxm_io_in_ready;
wire _txq_io_enq_ready;
wire _txq_io_deq_valid;
wire [7:0] _txq_io_deq_bits;
wire _txm_io_out_valid;
wire [7:0] _txm_io_out_bits;
wire _sim_serial_in_valid;
wire [7:0] _sim_serial_in_bits;
wire _sim_serial_out_ready;
SimUART #(
.FORCEPTY(0),
.UARTNO(0)
) sim (
.clock (clock),
.reset (reset),
.serial_in_ready (_rxq_io_enq_ready & _rxq_io_count < 4'h7),
.serial_in_valid (_sim_serial_in_valid),
.serial_in_bits (_sim_serial_in_bits),
.serial_out_ready (_sim_serial_out_ready),
.serial_out_valid (_txq_io_deq_valid),
.serial_out_bits (_txq_io_deq_bits)
);
UARTRx txm (
.clock (clock),
.reset (reset),
.io_en (1'h1),
.io_in (io_uart_txd),
.io_out_valid (_txm_io_out_valid),
.io_out_bits (_txm_io_out_bits),
.io_div (16'h364)
);
Queue8_UInt8 txq (
.clock (clock),
.reset (reset),
.io_enq_ready (_txq_io_enq_ready),
.io_enq_valid (_txm_io_out_valid),
.io_enq_bits (_txm_io_out_bits),
.io_deq_ready (_sim_serial_out_ready),
.io_deq_valid (_txq_io_deq_valid),
.io_deq_bits (_txq_io_deq_bits),
.io_count (/* unused */)
);
UARTTx rxm (
.clock (clock),
.reset (reset),
.io_en (1'h1),
.io_in_ready (_rxm_io_in_ready),
.io_in_valid (_rxq_io_deq_valid),
.io_in_bits (_rxq_io_deq_bits),
.io_out (io_uart_rxd),
.io_div (16'h364),
.io_nstop (1'h0)
);
Queue8_UInt8 rxq (
.clock (clock),
.reset (reset),
.io_enq_ready (_rxq_io_enq_ready),
.io_enq_valid (_sim_serial_in_valid),
.io_enq_bits (_sim_serial_in_bits),
.io_deq_ready (_rxm_io_in_ready),
.io_deq_valid (_rxq_io_deq_valid),
.io_deq_bits (_rxq_io_deq_bits),
.io_count (_rxq_io_count)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Ported from Rocket-Chip
// See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.lsu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.rocket._
import boom.v3.common._
import boom.v3.exu.BrUpdateInfo
import boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc, Transpose}
class BoomWritebackUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) {
val io = IO(new Bundle {
val req = Flipped(Decoupled(new WritebackReq(edge.bundle)))
val meta_read = Decoupled(new L1MetaReadReq)
val resp = Output(Bool())
val idx = Output(Valid(UInt()))
val data_req = Decoupled(new L1DataReadReq)
val data_resp = Input(UInt(encRowBits.W))
val mem_grant = Input(Bool())
val release = Decoupled(new TLBundleC(edge.bundle))
val lsu_release = Decoupled(new TLBundleC(edge.bundle))
})
val req = Reg(new WritebackReq(edge.bundle))
val s_invalid :: s_fill_buffer :: s_lsu_release :: s_active :: s_grant :: Nil = Enum(5)
val state = RegInit(s_invalid)
val r1_data_req_fired = RegInit(false.B)
val r2_data_req_fired = RegInit(false.B)
val r1_data_req_cnt = Reg(UInt(log2Up(refillCycles+1).W))
val r2_data_req_cnt = Reg(UInt(log2Up(refillCycles+1).W))
val data_req_cnt = RegInit(0.U(log2Up(refillCycles+1).W))
val (_, last_beat, all_beats_done, beat_count) = edge.count(io.release)
val wb_buffer = Reg(Vec(refillCycles, UInt(encRowBits.W)))
val acked = RegInit(false.B)
io.idx.valid := state =/= s_invalid
io.idx.bits := req.idx
io.release.valid := false.B
io.release.bits := DontCare
io.req.ready := false.B
io.meta_read.valid := false.B
io.meta_read.bits := DontCare
io.data_req.valid := false.B
io.data_req.bits := DontCare
io.resp := false.B
io.lsu_release.valid := false.B
io.lsu_release.bits := DontCare
val r_address = Cat(req.tag, req.idx) << blockOffBits
val id = cfg.nMSHRs
val probeResponse = edge.ProbeAck(
fromSource = id.U,
toAddress = r_address,
lgSize = lgCacheBlockBytes.U,
reportPermissions = req.param,
data = wb_buffer(data_req_cnt))
val voluntaryRelease = edge.Release(
fromSource = id.U,
toAddress = r_address,
lgSize = lgCacheBlockBytes.U,
shrinkPermissions = req.param,
data = wb_buffer(data_req_cnt))._2
when (state === s_invalid) {
io.req.ready := true.B
when (io.req.fire) {
state := s_fill_buffer
data_req_cnt := 0.U
req := io.req.bits
acked := false.B
}
} .elsewhen (state === s_fill_buffer) {
io.meta_read.valid := data_req_cnt < refillCycles.U
io.meta_read.bits.idx := req.idx
io.meta_read.bits.tag := req.tag
io.data_req.valid := data_req_cnt < refillCycles.U
io.data_req.bits.way_en := req.way_en
io.data_req.bits.addr := (if(refillCycles > 1)
Cat(req.idx, data_req_cnt(log2Up(refillCycles)-1,0))
else req.idx) << rowOffBits
r1_data_req_fired := false.B
r1_data_req_cnt := 0.U
r2_data_req_fired := r1_data_req_fired
r2_data_req_cnt := r1_data_req_cnt
when (io.data_req.fire && io.meta_read.fire) {
r1_data_req_fired := true.B
r1_data_req_cnt := data_req_cnt
data_req_cnt := data_req_cnt + 1.U
}
when (r2_data_req_fired) {
wb_buffer(r2_data_req_cnt) := io.data_resp
when (r2_data_req_cnt === (refillCycles-1).U) {
io.resp := true.B
state := s_lsu_release
data_req_cnt := 0.U
}
}
} .elsewhen (state === s_lsu_release) {
io.lsu_release.valid := true.B
io.lsu_release.bits := probeResponse
when (io.lsu_release.fire) {
state := s_active
}
} .elsewhen (state === s_active) {
io.release.valid := data_req_cnt < refillCycles.U
io.release.bits := Mux(req.voluntary, voluntaryRelease, probeResponse)
when (io.mem_grant) {
acked := true.B
}
when (io.release.fire) {
data_req_cnt := data_req_cnt + 1.U
}
when ((data_req_cnt === (refillCycles-1).U) && io.release.fire) {
state := Mux(req.voluntary, s_grant, s_invalid)
}
} .elsewhen (state === s_grant) {
when (io.mem_grant) {
acked := true.B
}
when (acked) {
state := s_invalid
}
}
}
class BoomProbeUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) {
val io = IO(new Bundle {
val req = Flipped(Decoupled(new TLBundleB(edge.bundle)))
val rep = Decoupled(new TLBundleC(edge.bundle))
val meta_read = Decoupled(new L1MetaReadReq)
val meta_write = Decoupled(new L1MetaWriteReq)
val wb_req = Decoupled(new WritebackReq(edge.bundle))
val way_en = Input(UInt(nWays.W))
val wb_rdy = Input(Bool()) // Is writeback unit currently busy? If so need to retry meta read when its done
val mshr_rdy = Input(Bool()) // Is MSHR ready for this request to proceed?
val mshr_wb_rdy = Output(Bool()) // Should we block MSHR writebacks while we finish our own?
val block_state = Input(new ClientMetadata())
val lsu_release = Decoupled(new TLBundleC(edge.bundle))
val state = Output(Valid(UInt(coreMaxAddrBits.W)))
})
val (s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req ::
s_mshr_resp :: s_lsu_release :: s_release :: s_writeback_req :: s_writeback_resp ::
s_meta_write :: s_meta_write_resp :: Nil) = Enum(11)
val state = RegInit(s_invalid)
val req = Reg(new TLBundleB(edge.bundle))
val req_idx = req.address(idxMSB, idxLSB)
val req_tag = req.address >> untagBits
val way_en = Reg(UInt())
val tag_matches = way_en.orR
val old_coh = Reg(new ClientMetadata)
val miss_coh = ClientMetadata.onReset
val reply_coh = Mux(tag_matches, old_coh, miss_coh)
val (is_dirty, report_param, new_coh) = reply_coh.onProbe(req.param)
io.state.valid := state =/= s_invalid
io.state.bits := req.address
io.req.ready := state === s_invalid
io.rep.valid := state === s_release
io.rep.bits := edge.ProbeAck(req, report_param)
assert(!io.rep.valid || !edge.hasData(io.rep.bits),
"ProbeUnit should not send ProbeAcks with data, WritebackUnit should handle it")
io.meta_read.valid := state === s_meta_read
io.meta_read.bits.idx := req_idx
io.meta_read.bits.tag := req_tag
io.meta_read.bits.way_en := ~(0.U(nWays.W))
io.meta_write.valid := state === s_meta_write
io.meta_write.bits.way_en := way_en
io.meta_write.bits.idx := req_idx
io.meta_write.bits.tag := req_tag
io.meta_write.bits.data.tag := req_tag
io.meta_write.bits.data.coh := new_coh
io.wb_req.valid := state === s_writeback_req
io.wb_req.bits.source := req.source
io.wb_req.bits.idx := req_idx
io.wb_req.bits.tag := req_tag
io.wb_req.bits.param := report_param
io.wb_req.bits.way_en := way_en
io.wb_req.bits.voluntary := false.B
io.mshr_wb_rdy := !state.isOneOf(s_release, s_writeback_req, s_writeback_resp, s_meta_write, s_meta_write_resp)
io.lsu_release.valid := state === s_lsu_release
io.lsu_release.bits := edge.ProbeAck(req, report_param)
// state === s_invalid
when (state === s_invalid) {
when (io.req.fire) {
state := s_meta_read
req := io.req.bits
}
} .elsewhen (state === s_meta_read) {
when (io.meta_read.fire) {
state := s_meta_resp
}
} .elsewhen (state === s_meta_resp) {
// we need to wait one cycle for the metadata to be read from the array
state := s_mshr_req
} .elsewhen (state === s_mshr_req) {
old_coh := io.block_state
way_en := io.way_en
// if the read didn't go through, we need to retry
state := Mux(io.mshr_rdy && io.wb_rdy, s_mshr_resp, s_meta_read)
} .elsewhen (state === s_mshr_resp) {
state := Mux(tag_matches && is_dirty, s_writeback_req, s_lsu_release)
} .elsewhen (state === s_lsu_release) {
when (io.lsu_release.fire) {
state := s_release
}
} .elsewhen (state === s_release) {
when (io.rep.ready) {
state := Mux(tag_matches, s_meta_write, s_invalid)
}
} .elsewhen (state === s_writeback_req) {
when (io.wb_req.fire) {
state := s_writeback_resp
}
} .elsewhen (state === s_writeback_resp) {
// wait for the writeback request to finish before updating the metadata
when (io.wb_req.ready) {
state := s_meta_write
}
} .elsewhen (state === s_meta_write) {
when (io.meta_write.fire) {
state := s_meta_write_resp
}
} .elsewhen (state === s_meta_write_resp) {
state := s_invalid
}
}
class BoomL1MetaReadReq(implicit p: Parameters) extends BoomBundle()(p) {
val req = Vec(memWidth, new L1MetaReadReq)
}
class BoomL1DataReadReq(implicit p: Parameters) extends BoomBundle()(p) {
val req = Vec(memWidth, new L1DataReadReq)
val valid = Vec(memWidth, Bool())
}
abstract class AbstractBoomDataArray(implicit p: Parameters) extends BoomModule with HasL1HellaCacheParameters {
val io = IO(new BoomBundle {
val read = Input(Vec(memWidth, Valid(new L1DataReadReq)))
val write = Input(Valid(new L1DataWriteReq))
val resp = Output(Vec(memWidth, Vec(nWays, Bits(encRowBits.W))))
val nacks = Output(Vec(memWidth, Bool()))
})
def pipeMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f))
}
class BoomDuplicatedDataArray(implicit p: Parameters) extends AbstractBoomDataArray
{
val waddr = io.write.bits.addr >> rowOffBits
for (j <- 0 until memWidth) {
val raddr = io.read(j).bits.addr >> rowOffBits
for (w <- 0 until nWays) {
val array = DescribedSRAM(
name = s"array_${w}_${j}",
desc = "Non-blocking DCache Data Array",
size = nSets * refillCycles,
data = Vec(rowWords, Bits(encDataBits.W))
)
when (io.write.bits.way_en(w) && io.write.valid) {
val data = VecInit((0 until rowWords) map (i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i)))
array.write(waddr, data, io.write.bits.wmask.asBools)
}
io.resp(j)(w) := RegNext(array.read(raddr, io.read(j).bits.way_en(w) && io.read(j).valid).asUInt)
}
io.nacks(j) := false.B
}
}
class BoomBankedDataArray(implicit p: Parameters) extends AbstractBoomDataArray {
val nBanks = boomParams.numDCacheBanks
val bankSize = nSets * refillCycles / nBanks
require (nBanks >= memWidth)
require (bankSize > 0)
val bankBits = log2Ceil(nBanks)
val bankOffBits = log2Ceil(rowWords) + log2Ceil(wordBytes)
val bidxBits = log2Ceil(bankSize)
val bidxOffBits = bankOffBits + bankBits
//----------------------------------------------------------------------------------------------------
val s0_rbanks = if (nBanks > 1) VecInit(io.read.map(r => (r.bits.addr >> bankOffBits)(bankBits-1,0))) else VecInit(0.U)
val s0_wbank = if (nBanks > 1) (io.write.bits.addr >> bankOffBits)(bankBits-1,0) else 0.U
val s0_ridxs = VecInit(io.read.map(r => (r.bits.addr >> bidxOffBits)(bidxBits-1,0)))
val s0_widx = (io.write.bits.addr >> bidxOffBits)(bidxBits-1,0)
val s0_read_valids = VecInit(io.read.map(_.valid))
val s0_bank_conflicts = pipeMap(w => (0 until w).foldLeft(false.B)((c,i) => c || io.read(i).valid && s0_rbanks(i) === s0_rbanks(w)))
val s0_do_bank_read = s0_read_valids zip s0_bank_conflicts map {case (v,c) => v && !c}
val s0_bank_read_gnts = Transpose(VecInit(s0_rbanks zip s0_do_bank_read map {case (b,d) => VecInit((UIntToOH(b) & Fill(nBanks,d)).asBools)}))
val s0_bank_write_gnt = (UIntToOH(s0_wbank) & Fill(nBanks, io.write.valid)).asBools
//----------------------------------------------------------------------------------------------------
val s1_rbanks = RegNext(s0_rbanks)
val s1_ridxs = RegNext(s0_ridxs)
val s1_read_valids = RegNext(s0_read_valids)
val s1_pipe_selection = pipeMap(i => VecInit(PriorityEncoderOH(pipeMap(j =>
if (j < i) s1_read_valids(j) && s1_rbanks(j) === s1_rbanks(i)
else if (j == i) true.B else false.B))))
val s1_ridx_match = pipeMap(i => pipeMap(j => if (j < i) s1_ridxs(j) === s1_ridxs(i)
else if (j == i) true.B else false.B))
val s1_nacks = pipeMap(w => s1_read_valids(w) && (s1_pipe_selection(w).asUInt & ~s1_ridx_match(w).asUInt).orR)
val s1_bank_selection = pipeMap(w => Mux1H(s1_pipe_selection(w), s1_rbanks))
//----------------------------------------------------------------------------------------------------
val s2_bank_selection = RegNext(s1_bank_selection)
val s2_nacks = RegNext(s1_nacks)
for (w <- 0 until nWays) {
val s2_bank_reads = Reg(Vec(nBanks, Bits(encRowBits.W)))
for (b <- 0 until nBanks) {
val array = DescribedSRAM(
name = s"array_${w}_${b}",
desc = "Non-blocking DCache Data Array",
size = bankSize,
data = Vec(rowWords, Bits(encDataBits.W))
)
val ridx = Mux1H(s0_bank_read_gnts(b), s0_ridxs)
val way_en = Mux1H(s0_bank_read_gnts(b), io.read.map(_.bits.way_en))
s2_bank_reads(b) := array.read(ridx, way_en(w) && s0_bank_read_gnts(b).reduce(_||_)).asUInt
when (io.write.bits.way_en(w) && s0_bank_write_gnt(b)) {
val data = VecInit((0 until rowWords) map (i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i)))
array.write(s0_widx, data, io.write.bits.wmask.asBools)
}
}
for (i <- 0 until memWidth) {
io.resp(i)(w) := s2_bank_reads(s2_bank_selection(i))
}
}
io.nacks := s2_nacks
}
/**
* Top level class wrapping a non-blocking dcache.
*
* @param hartid hardware thread for the cache
*/
class BoomNonBlockingDCache(staticIdForMetadataUseOnly: Int)(implicit p: Parameters) extends LazyModule
{
private val tileParams = p(TileKey)
protected val cfg = tileParams.dcache.get
protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1(
name = s"Core ${staticIdForMetadataUseOnly} DCache",
sourceId = IdRange(0, 1 max (cfg.nMSHRs + 1)),
supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes))))
protected def mmioClientParameters = Seq(TLMasterParameters.v1(
name = s"Core ${staticIdForMetadataUseOnly} DCache MMIO",
sourceId = IdRange(cfg.nMSHRs + 1, cfg.nMSHRs + 1 + cfg.nMMIOs),
requestFifo = true))
val node = TLClientNode(Seq(TLMasterPortParameters.v1(
cacheClientParameters ++ mmioClientParameters,
minLatency = 1)))
lazy val module = new BoomNonBlockingDCacheModule(this)
def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireT || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT)
require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$")
}
class BoomDCacheBundle(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) {
val lsu = Flipped(new LSUDMemIO)
}
class BoomNonBlockingDCacheModule(outer: BoomNonBlockingDCache) extends LazyModuleImp(outer)
with HasL1HellaCacheParameters
with HasBoomCoreParameters
{
implicit val edge = outer.node.edges.out(0)
val (tl_out, _) = outer.node.out(0)
val io = IO(new BoomDCacheBundle)
private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile)
fifoManagers.foreach { m =>
require (m.fifoId == fifoManagers.head.fifoId,
s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees ${m.nodePath.map(_.name)}")
}
def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f))
val t_replay :: t_probe :: t_wb :: t_mshr_meta_read :: t_lsu :: t_prefetch :: Nil = Enum(6)
val wb = Module(new BoomWritebackUnit)
val prober = Module(new BoomProbeUnit)
val mshrs = Module(new BoomMSHRFile)
mshrs.io.clear_all := io.lsu.force_order
mshrs.io.brupdate := io.lsu.brupdate
mshrs.io.exception := io.lsu.exception
mshrs.io.rob_pnr_idx := io.lsu.rob_pnr_idx
mshrs.io.rob_head_idx := io.lsu.rob_head_idx
// tags
def onReset = L1Metadata(0.U, ClientMetadata.onReset)
val meta = Seq.fill(memWidth) { Module(new L1MetadataArray(onReset _)) }
val metaWriteArb = Module(new Arbiter(new L1MetaWriteReq, 2))
// 0 goes to MSHR refills, 1 goes to prober
val metaReadArb = Module(new Arbiter(new BoomL1MetaReadReq, 6))
// 0 goes to MSHR replays, 1 goes to prober, 2 goes to wb, 3 goes to MSHR meta read,
// 4 goes to pipeline, 5 goes to prefetcher
metaReadArb.io.in := DontCare
for (w <- 0 until memWidth) {
meta(w).io.write.valid := metaWriteArb.io.out.fire
meta(w).io.write.bits := metaWriteArb.io.out.bits
meta(w).io.read.valid := metaReadArb.io.out.valid
meta(w).io.read.bits := metaReadArb.io.out.bits.req(w)
}
metaReadArb.io.out.ready := meta.map(_.io.read.ready).reduce(_||_)
metaWriteArb.io.out.ready := meta.map(_.io.write.ready).reduce(_||_)
// data
val data = Module(if (boomParams.numDCacheBanks == 1) new BoomDuplicatedDataArray else new BoomBankedDataArray)
val dataWriteArb = Module(new Arbiter(new L1DataWriteReq, 2))
// 0 goes to pipeline, 1 goes to MSHR refills
val dataReadArb = Module(new Arbiter(new BoomL1DataReadReq, 3))
// 0 goes to MSHR replays, 1 goes to wb, 2 goes to pipeline
dataReadArb.io.in := DontCare
for (w <- 0 until memWidth) {
data.io.read(w).valid := dataReadArb.io.out.bits.valid(w) && dataReadArb.io.out.valid
data.io.read(w).bits := dataReadArb.io.out.bits.req(w)
}
dataReadArb.io.out.ready := true.B
data.io.write.valid := dataWriteArb.io.out.fire
data.io.write.bits := dataWriteArb.io.out.bits
dataWriteArb.io.out.ready := true.B
// ------------
// New requests
io.lsu.req.ready := metaReadArb.io.in(4).ready && dataReadArb.io.in(2).ready
metaReadArb.io.in(4).valid := io.lsu.req.valid
dataReadArb.io.in(2).valid := io.lsu.req.valid
for (w <- 0 until memWidth) {
// Tag read for new requests
metaReadArb.io.in(4).bits.req(w).idx := io.lsu.req.bits(w).bits.addr >> blockOffBits
metaReadArb.io.in(4).bits.req(w).way_en := DontCare
metaReadArb.io.in(4).bits.req(w).tag := DontCare
// Data read for new requests
dataReadArb.io.in(2).bits.valid(w) := io.lsu.req.bits(w).valid
dataReadArb.io.in(2).bits.req(w).addr := io.lsu.req.bits(w).bits.addr
dataReadArb.io.in(2).bits.req(w).way_en := ~0.U(nWays.W)
}
// ------------
// MSHR Replays
val replay_req = Wire(Vec(memWidth, new BoomDCacheReq))
replay_req := DontCare
replay_req(0).uop := mshrs.io.replay.bits.uop
replay_req(0).addr := mshrs.io.replay.bits.addr
replay_req(0).data := mshrs.io.replay.bits.data
replay_req(0).is_hella := mshrs.io.replay.bits.is_hella
mshrs.io.replay.ready := metaReadArb.io.in(0).ready && dataReadArb.io.in(0).ready
// Tag read for MSHR replays
// We don't actually need to read the metadata, for replays we already know our way
metaReadArb.io.in(0).valid := mshrs.io.replay.valid
metaReadArb.io.in(0).bits.req(0).idx := mshrs.io.replay.bits.addr >> blockOffBits
metaReadArb.io.in(0).bits.req(0).way_en := DontCare
metaReadArb.io.in(0).bits.req(0).tag := DontCare
// Data read for MSHR replays
dataReadArb.io.in(0).valid := mshrs.io.replay.valid
dataReadArb.io.in(0).bits.req(0).addr := mshrs.io.replay.bits.addr
dataReadArb.io.in(0).bits.req(0).way_en := mshrs.io.replay.bits.way_en
dataReadArb.io.in(0).bits.valid := widthMap(w => (w == 0).B)
// -----------
// MSHR Meta read
val mshr_read_req = Wire(Vec(memWidth, new BoomDCacheReq))
mshr_read_req := DontCare
mshr_read_req(0).uop := NullMicroOp
mshr_read_req(0).addr := Cat(mshrs.io.meta_read.bits.tag, mshrs.io.meta_read.bits.idx) << blockOffBits
mshr_read_req(0).data := DontCare
mshr_read_req(0).is_hella := false.B
metaReadArb.io.in(3).valid := mshrs.io.meta_read.valid
metaReadArb.io.in(3).bits.req(0) := mshrs.io.meta_read.bits
mshrs.io.meta_read.ready := metaReadArb.io.in(3).ready
// -----------
// Write-backs
val wb_fire = wb.io.meta_read.fire && wb.io.data_req.fire
val wb_req = Wire(Vec(memWidth, new BoomDCacheReq))
wb_req := DontCare
wb_req(0).uop := NullMicroOp
wb_req(0).addr := Cat(wb.io.meta_read.bits.tag, wb.io.data_req.bits.addr)
wb_req(0).data := DontCare
wb_req(0).is_hella := false.B
// Couple the two decoupled interfaces of the WBUnit's meta_read and data_read
// Tag read for write-back
metaReadArb.io.in(2).valid := wb.io.meta_read.valid
metaReadArb.io.in(2).bits.req(0) := wb.io.meta_read.bits
wb.io.meta_read.ready := metaReadArb.io.in(2).ready && dataReadArb.io.in(1).ready
// Data read for write-back
dataReadArb.io.in(1).valid := wb.io.data_req.valid
dataReadArb.io.in(1).bits.req(0) := wb.io.data_req.bits
dataReadArb.io.in(1).bits.valid := widthMap(w => (w == 0).B)
wb.io.data_req.ready := metaReadArb.io.in(2).ready && dataReadArb.io.in(1).ready
assert(!(wb.io.meta_read.fire ^ wb.io.data_req.fire))
// -------
// Prober
val prober_fire = prober.io.meta_read.fire
val prober_req = Wire(Vec(memWidth, new BoomDCacheReq))
prober_req := DontCare
prober_req(0).uop := NullMicroOp
prober_req(0).addr := Cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx) << blockOffBits
prober_req(0).data := DontCare
prober_req(0).is_hella := false.B
// Tag read for prober
metaReadArb.io.in(1).valid := prober.io.meta_read.valid
metaReadArb.io.in(1).bits.req(0) := prober.io.meta_read.bits
prober.io.meta_read.ready := metaReadArb.io.in(1).ready
// Prober does not need to read data array
// -------
// Prefetcher
val prefetch_fire = mshrs.io.prefetch.fire
val prefetch_req = Wire(Vec(memWidth, new BoomDCacheReq))
prefetch_req := DontCare
prefetch_req(0) := mshrs.io.prefetch.bits
// Tag read for prefetch
metaReadArb.io.in(5).valid := mshrs.io.prefetch.valid
metaReadArb.io.in(5).bits.req(0).idx := mshrs.io.prefetch.bits.addr >> blockOffBits
metaReadArb.io.in(5).bits.req(0).way_en := DontCare
metaReadArb.io.in(5).bits.req(0).tag := DontCare
mshrs.io.prefetch.ready := metaReadArb.io.in(5).ready
// Prefetch does not need to read data array
val s0_valid = Mux(io.lsu.req.fire, VecInit(io.lsu.req.bits.map(_.valid)),
Mux(mshrs.io.replay.fire || wb_fire || prober_fire || prefetch_fire || mshrs.io.meta_read.fire,
VecInit(1.U(memWidth.W).asBools), VecInit(0.U(memWidth.W).asBools)))
val s0_req = Mux(io.lsu.req.fire , VecInit(io.lsu.req.bits.map(_.bits)),
Mux(wb_fire , wb_req,
Mux(prober_fire , prober_req,
Mux(prefetch_fire , prefetch_req,
Mux(mshrs.io.meta_read.fire, mshr_read_req
, replay_req)))))
val s0_type = Mux(io.lsu.req.fire , t_lsu,
Mux(wb_fire , t_wb,
Mux(prober_fire , t_probe,
Mux(prefetch_fire , t_prefetch,
Mux(mshrs.io.meta_read.fire, t_mshr_meta_read
, t_replay)))))
// Does this request need to send a response or nack
val s0_send_resp_or_nack = Mux(io.lsu.req.fire, s0_valid,
VecInit(Mux(mshrs.io.replay.fire && isRead(mshrs.io.replay.bits.uop.mem_cmd), 1.U(memWidth.W), 0.U(memWidth.W)).asBools))
val s1_req = RegNext(s0_req)
for (w <- 0 until memWidth)
s1_req(w).uop.br_mask := GetNewBrMask(io.lsu.brupdate, s0_req(w).uop)
val s2_store_failed = Wire(Bool())
val s1_valid = widthMap(w =>
RegNext(s0_valid(w) &&
!IsKilledByBranch(io.lsu.brupdate, s0_req(w).uop) &&
!(io.lsu.exception && s0_req(w).uop.uses_ldq) &&
!(s2_store_failed && io.lsu.req.fire && s0_req(w).uop.uses_stq),
init=false.B))
for (w <- 0 until memWidth)
assert(!(io.lsu.s1_kill(w) && !RegNext(io.lsu.req.fire) && !RegNext(io.lsu.req.bits(w).valid)))
val s1_addr = s1_req.map(_.addr)
val s1_nack = s1_addr.map(a => a(idxMSB,idxLSB) === prober.io.meta_write.bits.idx && !prober.io.req.ready)
val s1_send_resp_or_nack = RegNext(s0_send_resp_or_nack)
val s1_type = RegNext(s0_type)
val s1_mshr_meta_read_way_en = RegNext(mshrs.io.meta_read.bits.way_en)
val s1_replay_way_en = RegNext(mshrs.io.replay.bits.way_en) // For replays, the metadata isn't written yet
val s1_wb_way_en = RegNext(wb.io.data_req.bits.way_en)
// tag check
def wayMap[T <: Data](f: Int => T) = VecInit((0 until nWays).map(f))
val s1_tag_eq_way = widthMap(i => wayMap((w: Int) => meta(i).io.resp(w).tag === (s1_addr(i) >> untagBits)).asUInt)
val s1_tag_match_way = widthMap(i =>
Mux(s1_type === t_replay, s1_replay_way_en,
Mux(s1_type === t_wb, s1_wb_way_en,
Mux(s1_type === t_mshr_meta_read, s1_mshr_meta_read_way_en,
wayMap((w: Int) => s1_tag_eq_way(i)(w) && meta(i).io.resp(w).coh.isValid()).asUInt))))
val s1_wb_idx_matches = widthMap(i => (s1_addr(i)(untagBits-1,blockOffBits) === wb.io.idx.bits) && wb.io.idx.valid)
val s2_req = RegNext(s1_req)
val s2_type = RegNext(s1_type)
val s2_valid = widthMap(w =>
RegNext(s1_valid(w) &&
!io.lsu.s1_kill(w) &&
!IsKilledByBranch(io.lsu.brupdate, s1_req(w).uop) &&
!(io.lsu.exception && s1_req(w).uop.uses_ldq) &&
!(s2_store_failed && (s1_type === t_lsu) && s1_req(w).uop.uses_stq)))
for (w <- 0 until memWidth)
s2_req(w).uop.br_mask := GetNewBrMask(io.lsu.brupdate, s1_req(w).uop)
val s2_tag_match_way = RegNext(s1_tag_match_way)
val s2_tag_match = s2_tag_match_way.map(_.orR)
val s2_hit_state = widthMap(i => Mux1H(s2_tag_match_way(i), wayMap((w: Int) => RegNext(meta(i).io.resp(w).coh))))
val s2_has_permission = widthMap(w => s2_hit_state(w).onAccess(s2_req(w).uop.mem_cmd)._1)
val s2_new_hit_state = widthMap(w => s2_hit_state(w).onAccess(s2_req(w).uop.mem_cmd)._3)
val s2_hit = widthMap(w => (s2_tag_match(w) && s2_has_permission(w) && s2_hit_state(w) === s2_new_hit_state(w) && !mshrs.io.block_hit(w)) || s2_type.isOneOf(t_replay, t_wb))
val s2_nack = Wire(Vec(memWidth, Bool()))
assert(!(s2_type === t_replay && !s2_hit(0)), "Replays should always hit")
assert(!(s2_type === t_wb && !s2_hit(0)), "Writeback should always see data hit")
val s2_wb_idx_matches = RegNext(s1_wb_idx_matches)
// lr/sc
val debug_sc_fail_addr = RegInit(0.U)
val debug_sc_fail_cnt = RegInit(0.U(8.W))
val lrsc_count = RegInit(0.U(log2Ceil(lrscCycles).W))
val lrsc_valid = lrsc_count > lrscBackoff.U
val lrsc_addr = Reg(UInt())
val s2_lr = s2_req(0).uop.mem_cmd === M_XLR && (!RegNext(s1_nack(0)) || s2_type === t_replay)
val s2_sc = s2_req(0).uop.mem_cmd === M_XSC && (!RegNext(s1_nack(0)) || s2_type === t_replay)
val s2_lrsc_addr_match = widthMap(w => lrsc_valid && lrsc_addr === (s2_req(w).addr >> blockOffBits))
val s2_sc_fail = s2_sc && !s2_lrsc_addr_match(0)
when (lrsc_count > 0.U) { lrsc_count := lrsc_count - 1.U }
when (s2_valid(0) && ((s2_type === t_lsu && s2_hit(0) && !s2_nack(0)) ||
(s2_type === t_replay && s2_req(0).uop.mem_cmd =/= M_FLUSH_ALL))) {
when (s2_lr) {
lrsc_count := (lrscCycles - 1).U
lrsc_addr := s2_req(0).addr >> blockOffBits
}
when (lrsc_count > 0.U) {
lrsc_count := 0.U
}
}
for (w <- 0 until memWidth) {
when (s2_valid(w) &&
s2_type === t_lsu &&
!s2_hit(w) &&
!(s2_has_permission(w) && s2_tag_match(w)) &&
s2_lrsc_addr_match(w) &&
!s2_nack(w)) {
lrsc_count := 0.U
}
}
when (s2_valid(0)) {
when (s2_req(0).addr === debug_sc_fail_addr) {
when (s2_sc_fail) {
debug_sc_fail_cnt := debug_sc_fail_cnt + 1.U
} .elsewhen (s2_sc) {
debug_sc_fail_cnt := 0.U
}
} .otherwise {
when (s2_sc_fail) {
debug_sc_fail_addr := s2_req(0).addr
debug_sc_fail_cnt := 1.U
}
}
}
assert(debug_sc_fail_cnt < 100.U, "L1DCache failed too many SCs in a row")
val s2_data = Wire(Vec(memWidth, Vec(nWays, UInt(encRowBits.W))))
for (i <- 0 until memWidth) {
for (w <- 0 until nWays) {
s2_data(i)(w) := data.io.resp(i)(w)
}
}
val s2_data_muxed = widthMap(w => Mux1H(s2_tag_match_way(w), s2_data(w)))
val s2_word_idx = widthMap(w => if (rowWords == 1) 0.U else s2_req(w).addr(log2Up(rowWords*wordBytes)-1, log2Up(wordBytes)))
// replacement policy
val replacer = cacheParams.replacement
val s1_replaced_way_en = UIntToOH(replacer.way)
val s2_replaced_way_en = UIntToOH(RegNext(replacer.way))
val s2_repl_meta = widthMap(i => Mux1H(s2_replaced_way_en, wayMap((w: Int) => RegNext(meta(i).io.resp(w))).toSeq))
// nack because of incoming probe
val s2_nack_hit = RegNext(VecInit(s1_nack))
// Nack when we hit something currently being evicted
val s2_nack_victim = widthMap(w => s2_valid(w) && s2_hit(w) && mshrs.io.secondary_miss(w))
// MSHRs not ready for request
val s2_nack_miss = widthMap(w => s2_valid(w) && !s2_hit(w) && !mshrs.io.req(w).ready)
// Bank conflict on data arrays
val s2_nack_data = widthMap(w => data.io.nacks(w))
// Can't allocate MSHR for same set currently being written back
val s2_nack_wb = widthMap(w => s2_valid(w) && !s2_hit(w) && s2_wb_idx_matches(w))
s2_nack := widthMap(w => (s2_nack_miss(w) || s2_nack_hit(w) || s2_nack_victim(w) || s2_nack_data(w) || s2_nack_wb(w)) && s2_type =/= t_replay)
val s2_send_resp = widthMap(w => (RegNext(s1_send_resp_or_nack(w)) && !s2_nack(w) &&
(s2_hit(w) || (mshrs.io.req(w).fire && isWrite(s2_req(w).uop.mem_cmd) && !isRead(s2_req(w).uop.mem_cmd)))))
val s2_send_nack = widthMap(w => (RegNext(s1_send_resp_or_nack(w)) && s2_nack(w)))
for (w <- 0 until memWidth)
assert(!(s2_send_resp(w) && s2_send_nack(w)))
// hits always send a response
// If MSHR is not available, LSU has to replay this request later
// If MSHR is available and this is only a store(not a amo), we don't need to wait for resp later
s2_store_failed := s2_valid(0) && s2_nack(0) && s2_send_nack(0) && s2_req(0).uop.uses_stq
// Miss handling
for (w <- 0 until memWidth) {
mshrs.io.req(w).valid := s2_valid(w) &&
!s2_hit(w) &&
!s2_nack_hit(w) &&
!s2_nack_victim(w) &&
!s2_nack_data(w) &&
!s2_nack_wb(w) &&
s2_type.isOneOf(t_lsu, t_prefetch) &&
!IsKilledByBranch(io.lsu.brupdate, s2_req(w).uop) &&
!(io.lsu.exception && s2_req(w).uop.uses_ldq) &&
(isPrefetch(s2_req(w).uop.mem_cmd) ||
isRead(s2_req(w).uop.mem_cmd) ||
isWrite(s2_req(w).uop.mem_cmd))
assert(!(mshrs.io.req(w).valid && s2_type === t_replay), "Replays should not need to go back into MSHRs")
mshrs.io.req(w).bits := DontCare
mshrs.io.req(w).bits.uop := s2_req(w).uop
mshrs.io.req(w).bits.uop.br_mask := GetNewBrMask(io.lsu.brupdate, s2_req(w).uop)
mshrs.io.req(w).bits.addr := s2_req(w).addr
mshrs.io.req(w).bits.tag_match := s2_tag_match(w)
mshrs.io.req(w).bits.old_meta := Mux(s2_tag_match(w), L1Metadata(s2_repl_meta(w).tag, s2_hit_state(w)), s2_repl_meta(w))
mshrs.io.req(w).bits.way_en := Mux(s2_tag_match(w), s2_tag_match_way(w), s2_replaced_way_en)
mshrs.io.req(w).bits.data := s2_req(w).data
mshrs.io.req(w).bits.is_hella := s2_req(w).is_hella
mshrs.io.req_is_probe(w) := s2_type === t_probe && s2_valid(w)
}
mshrs.io.meta_resp.valid := !s2_nack_hit(0) || prober.io.mshr_wb_rdy
mshrs.io.meta_resp.bits := Mux1H(s2_tag_match_way(0), RegNext(meta(0).io.resp))
when (mshrs.io.req.map(_.fire).reduce(_||_)) { replacer.miss }
tl_out.a <> mshrs.io.mem_acquire
// probes and releases
prober.io.req.valid := tl_out.b.valid && !lrsc_valid
tl_out.b.ready := prober.io.req.ready && !lrsc_valid
prober.io.req.bits := tl_out.b.bits
prober.io.way_en := s2_tag_match_way(0)
prober.io.block_state := s2_hit_state(0)
metaWriteArb.io.in(1) <> prober.io.meta_write
prober.io.mshr_rdy := mshrs.io.probe_rdy
prober.io.wb_rdy := (prober.io.meta_write.bits.idx =/= wb.io.idx.bits) || !wb.io.idx.valid
mshrs.io.prober_state := prober.io.state
// refills
when (tl_out.d.bits.source === cfg.nMSHRs.U) {
// This should be ReleaseAck
tl_out.d.ready := true.B
mshrs.io.mem_grant.valid := false.B
mshrs.io.mem_grant.bits := DontCare
} .otherwise {
// This should be GrantData
mshrs.io.mem_grant <> tl_out.d
}
dataWriteArb.io.in(1) <> mshrs.io.refill
metaWriteArb.io.in(0) <> mshrs.io.meta_write
tl_out.e <> mshrs.io.mem_finish
// writebacks
val wbArb = Module(new Arbiter(new WritebackReq(edge.bundle), 2))
// 0 goes to prober, 1 goes to MSHR evictions
wbArb.io.in(0) <> prober.io.wb_req
wbArb.io.in(1) <> mshrs.io.wb_req
wb.io.req <> wbArb.io.out
wb.io.data_resp := s2_data_muxed(0)
mshrs.io.wb_resp := wb.io.resp
wb.io.mem_grant := tl_out.d.fire && tl_out.d.bits.source === cfg.nMSHRs.U
val lsu_release_arb = Module(new Arbiter(new TLBundleC(edge.bundle), 2))
io.lsu.release <> lsu_release_arb.io.out
lsu_release_arb.io.in(0) <> wb.io.lsu_release
lsu_release_arb.io.in(1) <> prober.io.lsu_release
TLArbiter.lowest(edge, tl_out.c, wb.io.release, prober.io.rep)
io.lsu.perf.release := edge.done(tl_out.c)
io.lsu.perf.acquire := edge.done(tl_out.a)
// load data gen
val s2_data_word_prebypass = widthMap(w => s2_data_muxed(w) >> Cat(s2_word_idx(w), 0.U(log2Ceil(coreDataBits).W)))
val s2_data_word = Wire(Vec(memWidth, UInt()))
val loadgen = (0 until memWidth).map { w =>
new LoadGen(s2_req(w).uop.mem_size, s2_req(w).uop.mem_signed, s2_req(w).addr,
s2_data_word(w), s2_sc && (w == 0).B, wordBytes)
}
// Mux between cache responses and uncache responses
val cache_resp = Wire(Vec(memWidth, Valid(new BoomDCacheResp)))
for (w <- 0 until memWidth) {
cache_resp(w).valid := s2_valid(w) && s2_send_resp(w)
cache_resp(w).bits.uop := s2_req(w).uop
cache_resp(w).bits.data := loadgen(w).data | s2_sc_fail
cache_resp(w).bits.is_hella := s2_req(w).is_hella
}
val uncache_resp = Wire(Valid(new BoomDCacheResp))
uncache_resp.bits := mshrs.io.resp.bits
uncache_resp.valid := mshrs.io.resp.valid
mshrs.io.resp.ready := !(cache_resp.map(_.valid).reduce(_&&_)) // We can backpressure the MSHRs, but not cache hits
val resp = WireInit(cache_resp)
var uncache_responding = false.B
for (w <- 0 until memWidth) {
val uncache_respond = !cache_resp(w).valid && !uncache_responding
when (uncache_respond) {
resp(w) := uncache_resp
}
uncache_responding = uncache_responding || uncache_respond
}
for (w <- 0 until memWidth) {
io.lsu.resp(w).valid := resp(w).valid &&
!(io.lsu.exception && resp(w).bits.uop.uses_ldq) &&
!IsKilledByBranch(io.lsu.brupdate, resp(w).bits.uop)
io.lsu.resp(w).bits := UpdateBrMask(io.lsu.brupdate, resp(w).bits)
io.lsu.nack(w).valid := s2_valid(w) && s2_send_nack(w) &&
!(io.lsu.exception && s2_req(w).uop.uses_ldq) &&
!IsKilledByBranch(io.lsu.brupdate, s2_req(w).uop)
io.lsu.nack(w).bits := UpdateBrMask(io.lsu.brupdate, s2_req(w))
assert(!(io.lsu.nack(w).valid && s2_type =/= t_lsu))
}
// Store/amo hits
val s3_req = RegNext(s2_req(0))
val s3_valid = RegNext(s2_valid(0) && s2_hit(0) && isWrite(s2_req(0).uop.mem_cmd) &&
!s2_sc_fail && !(s2_send_nack(0) && s2_nack(0)))
for (w <- 1 until memWidth) {
assert(!(s2_valid(w) && s2_hit(w) && isWrite(s2_req(w).uop.mem_cmd) &&
!s2_sc_fail && !(s2_send_nack(w) && s2_nack(w))),
"Store must go through 0th pipe in L1D")
}
// For bypassing
val s4_req = RegNext(s3_req)
val s4_valid = RegNext(s3_valid)
val s5_req = RegNext(s4_req)
val s5_valid = RegNext(s4_valid)
val s3_bypass = widthMap(w => s3_valid && ((s2_req(w).addr >> wordOffBits) === (s3_req.addr >> wordOffBits)))
val s4_bypass = widthMap(w => s4_valid && ((s2_req(w).addr >> wordOffBits) === (s4_req.addr >> wordOffBits)))
val s5_bypass = widthMap(w => s5_valid && ((s2_req(w).addr >> wordOffBits) === (s5_req.addr >> wordOffBits)))
// Store -> Load bypassing
for (w <- 0 until memWidth) {
s2_data_word(w) := Mux(s3_bypass(w), s3_req.data,
Mux(s4_bypass(w), s4_req.data,
Mux(s5_bypass(w), s5_req.data,
s2_data_word_prebypass(w))))
}
val amoalu = Module(new AMOALU(xLen))
amoalu.io.mask := new StoreGen(s2_req(0).uop.mem_size, s2_req(0).addr, 0.U, xLen/8).mask
amoalu.io.cmd := s2_req(0).uop.mem_cmd
amoalu.io.lhs := s2_data_word(0)
amoalu.io.rhs := s2_req(0).data
s3_req.data := amoalu.io.out
val s3_way = RegNext(s2_tag_match_way(0))
dataWriteArb.io.in(0).valid := s3_valid
dataWriteArb.io.in(0).bits.addr := s3_req.addr
dataWriteArb.io.in(0).bits.wmask := UIntToOH(s3_req.addr.extract(rowOffBits-1,offsetlsb))
dataWriteArb.io.in(0).bits.data := Fill(rowWords, s3_req.data)
dataWriteArb.io.in(0).bits.way_en := s3_way
io.lsu.ordered := mshrs.io.fence_rdy && !s1_valid.reduce(_||_) && !s2_valid.reduce(_||_)
} | module BoomWritebackUnit(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [19:0] io_req_bits_tag,
input [5:0] io_req_bits_idx,
input [2:0] io_req_bits_param,
input [3:0] io_req_bits_way_en,
input io_req_bits_voluntary,
input io_meta_read_ready,
output io_meta_read_valid,
output [5:0] io_meta_read_bits_idx,
output [19:0] io_meta_read_bits_tag,
output io_resp,
output io_idx_valid,
output [5:0] io_idx_bits,
input io_data_req_ready,
output io_data_req_valid,
output [3:0] io_data_req_bits_way_en,
output [11:0] io_data_req_bits_addr,
input [63:0] io_data_resp,
input io_mem_grant,
input io_release_ready,
output io_release_valid,
output [2:0] io_release_bits_opcode,
output [2:0] io_release_bits_param,
output [31:0] io_release_bits_address,
output [63:0] io_release_bits_data,
input io_lsu_release_ready,
output io_lsu_release_valid,
output [31:0] io_lsu_release_bits_address
);
reg [19:0] req_tag;
reg [5:0] req_idx;
reg [2:0] req_param;
reg [3:0] req_way_en;
reg req_voluntary;
reg [2:0] state;
reg r1_data_req_fired;
reg r2_data_req_fired;
reg [3:0] r1_data_req_cnt;
reg [3:0] r2_data_req_cnt;
reg [3:0] data_req_cnt;
reg [63:0] wb_buffer_0;
reg [63:0] wb_buffer_1;
reg [63:0] wb_buffer_2;
reg [63:0] wb_buffer_3;
reg [63:0] wb_buffer_4;
reg [63:0] wb_buffer_5;
reg [63:0] wb_buffer_6;
reg [63:0] wb_buffer_7;
reg acked;
wire [31:0] r_address = {req_tag, req_idx, 6'h0};
wire [7:0][63:0] _GEN = {{wb_buffer_7}, {wb_buffer_6}, {wb_buffer_5}, {wb_buffer_4}, {wb_buffer_3}, {wb_buffer_2}, {wb_buffer_1}, {wb_buffer_0}};
wire io_req_ready_0 = state == 3'h0;
wire _GEN_0 = state == 3'h1;
wire io_data_req_valid_0 = ~io_req_ready_0 & _GEN_0 & ~(data_req_cnt[3]);
wire _GEN_1 = r2_data_req_cnt == 4'h7;
wire _GEN_2 = state == 3'h2;
wire io_lsu_release_valid_0 = ~(io_req_ready_0 | _GEN_0) & _GEN_2;
wire _GEN_3 = state == 3'h3;
wire _GEN_4 = _GEN_0 | _GEN_2;
wire io_release_valid_0 = ~(io_req_ready_0 | _GEN_4) & _GEN_3 & ~(data_req_cnt[3]);
wire _GEN_5 = io_release_ready & io_release_valid_0;
wire _GEN_6 = state == 3'h4;
wire _GEN_7 = io_req_ready_0 & io_req_valid;
wire _GEN_8 = io_req_ready_0 | ~_GEN_0;
wire _GEN_9 = io_data_req_ready & io_data_req_valid_0 & io_meta_read_ready;
always @(posedge clock) begin
if (_GEN_7) begin
req_tag <= io_req_bits_tag;
req_idx <= io_req_bits_idx;
req_param <= io_req_bits_param;
req_way_en <= io_req_bits_way_en;
req_voluntary <= io_req_bits_voluntary;
end
if (_GEN_8) begin
end
else begin
r1_data_req_cnt <= _GEN_9 ? data_req_cnt : 4'h0;
r2_data_req_cnt <= r1_data_req_cnt;
end
if (io_req_ready_0 | ~(_GEN_0 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h0)) begin
end
else
wb_buffer_0 <= io_data_resp;
if (io_req_ready_0 | ~(_GEN_0 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h1)) begin
end
else
wb_buffer_1 <= io_data_resp;
if (io_req_ready_0 | ~(_GEN_0 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h2)) begin
end
else
wb_buffer_2 <= io_data_resp;
if (io_req_ready_0 | ~(_GEN_0 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h3)) begin
end
else
wb_buffer_3 <= io_data_resp;
if (io_req_ready_0 | ~(_GEN_0 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h4)) begin
end
else
wb_buffer_4 <= io_data_resp;
if (io_req_ready_0 | ~(_GEN_0 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h5)) begin
end
else
wb_buffer_5 <= io_data_resp;
if (io_req_ready_0 | ~(_GEN_0 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h6)) begin
end
else
wb_buffer_6 <= io_data_resp;
if (io_req_ready_0 | ~(_GEN_0 & r2_data_req_fired & (&(r2_data_req_cnt[2:0])))) begin
end
else
wb_buffer_7 <= io_data_resp;
if (reset) begin
state <= 3'h0;
r1_data_req_fired <= 1'h0;
r2_data_req_fired <= 1'h0;
data_req_cnt <= 4'h0;
acked <= 1'h0;
end
else begin
if (io_req_ready_0) begin
if (_GEN_7) begin
state <= 3'h1;
data_req_cnt <= 4'h0;
end
acked <= ~_GEN_7 & acked;
end
else begin
if (_GEN_0) begin
if (r2_data_req_fired & _GEN_1) begin
state <= 3'h2;
data_req_cnt <= 4'h0;
end
else if (_GEN_9)
data_req_cnt <= data_req_cnt + 4'h1;
end
else begin
if (_GEN_2) begin
if (io_lsu_release_ready & io_lsu_release_valid_0)
state <= 3'h3;
end
else if (_GEN_3) begin
if (data_req_cnt == 4'h7 & _GEN_5)
state <= {req_voluntary, 2'h0};
end
else if (_GEN_6 & acked)
state <= 3'h0;
if (_GEN_2 | ~_GEN_5) begin
end
else
data_req_cnt <= data_req_cnt + 4'h1;
end
if (~_GEN_4)
acked <= _GEN_3 ? io_mem_grant | acked : _GEN_6 & io_mem_grant | acked;
end
if (_GEN_8) begin
end
else begin
r1_data_req_fired <= _GEN_9;
r2_data_req_fired <= r1_data_req_fired;
end
end
end
assign io_req_ready = io_req_ready_0;
assign io_meta_read_valid = io_data_req_valid_0;
assign io_meta_read_bits_idx = req_idx;
assign io_meta_read_bits_tag = req_tag;
assign io_resp = ~io_req_ready_0 & _GEN_0 & r2_data_req_fired & _GEN_1;
assign io_idx_valid = |state;
assign io_idx_bits = req_idx;
assign io_data_req_valid = io_data_req_valid_0;
assign io_data_req_bits_way_en = req_way_en;
assign io_data_req_bits_addr = {req_idx, data_req_cnt[2:0], 3'h0};
assign io_release_valid = io_release_valid_0;
assign io_release_bits_opcode = {1'h1, req_voluntary, 1'h1};
assign io_release_bits_param = req_param;
assign io_release_bits_address = r_address;
assign io_release_bits_data = _GEN[data_req_cnt[2:0]];
assign io_lsu_release_valid = io_lsu_release_valid_0;
assign io_lsu_release_bits_address = r_address;
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket.Instructions32
import freechips.rocketchip.rocket.CustomInstructions._
import freechips.rocketchip.rocket.RVCExpander
import freechips.rocketchip.rocket.{CSR,Causes}
import freechips.rocketchip.util.{uintToBitPat,UIntIsOneOf}
import FUConstants._
import boom.v3.common._
import boom.v3.util._
// scalastyle:off
/**
* Abstract trait giving defaults and other relevant values to different Decode constants/
*/
abstract trait DecodeConstants
extends freechips.rocketchip.rocket.constants.ScalarOpConstants
with freechips.rocketchip.rocket.constants.MemoryOpConstants
{
val xpr64 = Y // TODO inform this from xLen
val DC2 = BitPat.dontCare(2) // Makes the listing below more readable
def decode_default: List[BitPat] =
// frs3_en wakeup_delay
// is val inst? | imm sel | bypassable (aka, known/fixed latency)
// | is fp inst? | | uses_ldq | | is_br
// | | is single-prec? rs1 regtype | | | uses_stq | | |
// | | | micro-code | rs2 type| | | | is_amo | | |
// | | | | iq-type func unit | | | | | | | is_fence | | |
// | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?
// | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
// | | | | | | | | | | | | | | | | | | | | | | | |
List(N, N, X, uopX , IQT_INT, FU_X , RT_X , DC2 ,DC2 ,X, IS_X, X, X, X, X, N, M_X, DC2, X, X, N, N, X, CSR.X)
val table: Array[(BitPat, List[BitPat])]
}
// scalastyle:on
/**
* Decoded control signals
*/
class CtrlSigs extends Bundle
{
val legal = Bool()
val fp_val = Bool()
val fp_single = Bool()
val uopc = UInt(UOPC_SZ.W)
val iq_type = UInt(IQT_SZ.W)
val fu_code = UInt(FUC_SZ.W)
val dst_type = UInt(2.W)
val rs1_type = UInt(2.W)
val rs2_type = UInt(2.W)
val frs3_en = Bool()
val imm_sel = UInt(IS_X.getWidth.W)
val uses_ldq = Bool()
val uses_stq = Bool()
val is_amo = Bool()
val is_fence = Bool()
val is_fencei = Bool()
val mem_cmd = UInt(freechips.rocketchip.rocket.M_SZ.W)
val wakeup_delay = UInt(2.W)
val bypassable = Bool()
val is_br = Bool()
val is_sys_pc2epc = Bool()
val inst_unique = Bool()
val flush_on_commit = Bool()
val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W)
val rocc = Bool()
def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = {
val decoder = freechips.rocketchip.rocket.DecodeLogic(inst, XDecode.decode_default, table)
val sigs =
Seq(legal, fp_val, fp_single, uopc, iq_type, fu_code, dst_type, rs1_type,
rs2_type, frs3_en, imm_sel, uses_ldq, uses_stq, is_amo,
is_fence, is_fencei, mem_cmd, wakeup_delay, bypassable,
is_br, is_sys_pc2epc, inst_unique, flush_on_commit, csr_cmd)
sigs zip decoder map {case(s,d) => s := d}
rocc := false.B
this
}
}
// scalastyle:off
/**
* Decode constants for RV32
*/
object X32Decode extends DecodeConstants
{
// frs3_en wakeup_delay
// is val inst? | imm sel | bypassable (aka, known/fixed latency)
// | is fp inst? | | uses_ldq | | is_br
// | | is single-prec? rs1 regtype | | | uses_stq | | |
// | | | micro-code | rs2 type| | | | is_amo | | |
// | | | | iq-type func unit | | | | | | | is_fence | | |
// | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?
// | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | |
Instructions32.SLLI ->
List(Y, N, X, uopSLLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
Instructions32.SRLI ->
List(Y, N, X, uopSRLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
Instructions32.SRAI ->
List(Y, N, X, uopSRAI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N)
)
}
/**
* Decode constants for RV64
*/
object X64Decode extends DecodeConstants
{
// frs3_en wakeup_delay
// is val inst? | imm sel | bypassable (aka, known/fixed latency)
// | is fp inst? | | uses_ldq | | is_br
// | | is single-prec? rs1 regtype | | | uses_stq | | |
// | | | micro-code | rs2 type| | | | is_amo | | |
// | | | | iq-type func unit | | | | | | | is_fence | | |
// | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?
// | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | |
LD -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),
LWU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),
SD -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),
SLLI -> List(Y, N, X, uopSLLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRLI -> List(Y, N, X, uopSRLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRAI -> List(Y, N, X, uopSRAI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
ADDIW -> List(Y, N, X, uopADDIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SLLIW -> List(Y, N, X, uopSLLIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRAIW -> List(Y, N, X, uopSRAIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRLIW -> List(Y, N, X, uopSRLIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
ADDW -> List(Y, N, X, uopADDW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SUBW -> List(Y, N, X, uopSUBW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SLLW -> List(Y, N, X, uopSLLW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRAW -> List(Y, N, X, uopSRAW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRLW -> List(Y, N, X, uopSRLW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N)
)
}
/**
* Overall Decode constants
*/
object XDecode extends DecodeConstants
{
// frs3_en wakeup_delay
// is val inst? | imm sel | bypassable (aka, known/fixed latency)
// | is fp inst? | | uses_ldq | | is_br
// | | is single-prec? rs1 regtype | | | uses_stq | | |
// | | | micro-code | rs2 type| | | | is_amo | | |
// | | | | iq-type func unit | | | | | | | is_fence | | |
// | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?
// | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | |
LW -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),
LH -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),
LHU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),
LB -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),
LBU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),
SW -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),
SH -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),
SB -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),
LUI -> List(Y, N, X, uopLUI , IQT_INT, FU_ALU , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
ADDI -> List(Y, N, X, uopADDI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
ANDI -> List(Y, N, X, uopANDI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
ORI -> List(Y, N, X, uopORI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
XORI -> List(Y, N, X, uopXORI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SLTI -> List(Y, N, X, uopSLTI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SLTIU -> List(Y, N, X, uopSLTIU, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SLL -> List(Y, N, X, uopSLL , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
ADD -> List(Y, N, X, uopADD , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SUB -> List(Y, N, X, uopSUB , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SLT -> List(Y, N, X, uopSLT , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SLTU -> List(Y, N, X, uopSLTU , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
AND -> List(Y, N, X, uopAND , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
OR -> List(Y, N, X, uopOR , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
XOR -> List(Y, N, X, uopXOR , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRA -> List(Y, N, X, uopSRA , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRL -> List(Y, N, X, uopSRL , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
MUL -> List(Y, N, X, uopMUL , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
MULH -> List(Y, N, X, uopMULH , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
MULHU -> List(Y, N, X, uopMULHU, IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
MULHSU -> List(Y, N, X, uopMULHSU,IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
MULW -> List(Y, N, X, uopMULW , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
DIV -> List(Y, N, X, uopDIV , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
DIVU -> List(Y, N, X, uopDIVU , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
REM -> List(Y, N, X, uopREM , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
REMU -> List(Y, N, X, uopREMU , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
DIVW -> List(Y, N, X, uopDIVW , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
DIVUW -> List(Y, N, X, uopDIVUW, IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
REMW -> List(Y, N, X, uopREMW , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
REMUW -> List(Y, N, X, uopREMUW, IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
AUIPC -> List(Y, N, X, uopAUIPC, IQT_INT, FU_JMP , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N), // use BRU for the PC read
JAL -> List(Y, N, X, uopJAL , IQT_INT, FU_JMP , RT_FIX, RT_X , RT_X , N, IS_J, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N),
JALR -> List(Y, N, X, uopJALR , IQT_INT, FU_JMP , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N),
BEQ -> List(Y, N, X, uopBEQ , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),
BNE -> List(Y, N, X, uopBNE , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),
BGE -> List(Y, N, X, uopBGE , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),
BGEU -> List(Y, N, X, uopBGEU , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),
BLT -> List(Y, N, X, uopBLT , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),
BLTU -> List(Y, N, X, uopBLTU , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),
// I-type, the immediate12 holds the CSR register.
CSRRW -> List(Y, N, X, uopCSRRW, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.W),
CSRRS -> List(Y, N, X, uopCSRRS, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.S),
CSRRC -> List(Y, N, X, uopCSRRC, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.C),
CSRRWI -> List(Y, N, X, uopCSRRWI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.W),
CSRRSI -> List(Y, N, X, uopCSRRSI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.S),
CSRRCI -> List(Y, N, X, uopCSRRCI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.C),
SFENCE_VMA->List(Y,N, X, uopSFENCE,IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N,M_SFENCE,0.U,N, N, N, Y, Y, CSR.N),
ECALL -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, Y, Y, Y, CSR.I),
EBREAK -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, Y, Y, Y, CSR.I),
SRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),
MRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),
DRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),
WFI -> List(Y, N, X, uopWFI ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),
FENCE_I -> List(Y, N, X, uopNOP , IQT_INT, FU_X , RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, Y, M_X , 0.U, N, N, N, Y, Y, CSR.N),
FENCE -> List(Y, N, X, uopFENCE, IQT_INT, FU_MEM , RT_X , RT_X , RT_X , N, IS_X, N, Y, N, Y, N, M_X , 0.U, N, N, N, Y, Y, CSR.N), // TODO PERF make fence higher performance
// currently serializes pipeline
// frs3_en wakeup_delay
// is val inst? | imm sel | bypassable (aka, known/fixed latency)
// | is fp inst? | | uses_ldq | | is_br
// | | is single-prec? rs1 regtype | | | uses_stq | | |
// | | | micro-code | rs2 type| | | | is_amo | | |
// | | | | iq-type func unit | | | | | | | is_fence | | |
// | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?
// | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
// A-type | | | | | | | | | | | | | | | | | | | | | | | |
AMOADD_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_ADD, 0.U,N, N, N, Y, Y, CSR.N), // TODO make AMOs higherperformance
AMOXOR_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_XOR, 0.U,N, N, N, Y, Y, CSR.N),
AMOSWAP_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_SWAP,0.U,N, N, N, Y, Y, CSR.N),
AMOAND_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_AND, 0.U,N, N, N, Y, Y, CSR.N),
AMOOR_W -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_OR, 0.U,N, N, N, Y, Y, CSR.N),
AMOMIN_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MIN, 0.U,N, N, N, Y, Y, CSR.N),
AMOMINU_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MINU,0.U,N, N, N, Y, Y, CSR.N),
AMOMAX_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAX, 0.U,N, N, N, Y, Y, CSR.N),
AMOMAXU_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAXU,0.U,N, N, N, Y, Y, CSR.N),
AMOADD_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_ADD, 0.U,N, N, N, Y, Y, CSR.N),
AMOXOR_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_XOR, 0.U,N, N, N, Y, Y, CSR.N),
AMOSWAP_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_SWAP,0.U,N, N, N, Y, Y, CSR.N),
AMOAND_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_AND, 0.U,N, N, N, Y, Y, CSR.N),
AMOOR_D -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_OR, 0.U,N, N, N, Y, Y, CSR.N),
AMOMIN_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MIN, 0.U,N, N, N, Y, Y, CSR.N),
AMOMINU_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MINU,0.U,N, N, N, Y, Y, CSR.N),
AMOMAX_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAX, 0.U,N, N, N, Y, Y, CSR.N),
AMOMAXU_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAXU,0.U,N, N, N, Y, Y, CSR.N),
LR_W -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_X , N, IS_X, Y, N, N, N, N, M_XLR , 0.U,N, N, N, Y, Y, CSR.N),
LR_D -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_X , N, IS_X, Y, N, N, N, N, M_XLR , 0.U,N, N, N, Y, Y, CSR.N),
SC_W -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XSC , 0.U,N, N, N, Y, Y, CSR.N),
SC_D -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XSC , 0.U,N, N, N, Y, Y, CSR.N)
)
}
/**
* FP Decode constants
*/
object FDecode extends DecodeConstants
{
val table: Array[(BitPat, List[BitPat])] = Array(
// frs3_en wakeup_delay
// | imm sel | bypassable (aka, known/fixed latency)
// | | uses_ldq | | is_br
// is val inst? rs1 regtype | | | uses_stq | | |
// | is fp inst? | rs2 type| | | | is_amo | | |
// | | is dst single-prec? | | | | | | | is_fence | | |
// | | | micro-opcode | | | | | | | | is_fencei | | | is breakpoint or ecall
// | | | | iq_type func dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | unit regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
FLW -> List(Y, Y, Y, uopLD , IQT_MEM, FU_MEM, RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 0.U, N, N, N, N, N, CSR.N),
FLD -> List(Y, Y, N, uopLD , IQT_MEM, FU_MEM, RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 0.U, N, N, N, N, N, CSR.N),
FSW -> List(Y, Y, Y, uopSTA , IQT_MFP,FU_F2IMEM,RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), // sort of a lie; broken into two micro-ops
FSD -> List(Y, Y, N, uopSTA , IQT_MFP,FU_F2IMEM,RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),
FCLASS_S-> List(Y, Y, Y, uopFCLASS_S,IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCLASS_D-> List(Y, Y, N, uopFCLASS_D,IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMV_W_X -> List(Y, Y, Y, uopFMV_W_X, IQT_INT, FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMV_D_X -> List(Y, Y, N, uopFMV_D_X, IQT_INT, FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMV_X_W -> List(Y, Y, Y, uopFMV_X_W, IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMV_X_D -> List(Y, Y, N, uopFMV_X_D, IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSGNJ_S -> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSGNJ_D -> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSGNJX_S-> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSGNJX_D-> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSGNJN_S-> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSGNJN_D-> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
// FP to FP
FCVT_S_D-> List(Y, Y, Y, uopFCVT_S_D,IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_D_S-> List(Y, Y, N, uopFCVT_D_S,IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
// Int to FP
FCVT_S_W-> List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_S_WU->List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_S_L-> List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_S_LU->List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_D_W-> List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_D_WU->List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_D_L-> List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_D_LU->List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
// FP to Int
FCVT_W_S-> List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_WU_S->List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_L_S-> List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_LU_S->List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_W_D-> List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_WU_D->List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_L_D-> List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_LU_D->List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
// "fp_single" is used for wb_data formatting (and debugging)
FEQ_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FLT_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FLE_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FEQ_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FLT_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FLE_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMIN_S ->List(Y, Y, Y,uopFMINMAX_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMAX_S ->List(Y, Y, Y,uopFMINMAX_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMIN_D ->List(Y, Y, N,uopFMINMAX_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMAX_D ->List(Y, Y, N,uopFMINMAX_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FADD_S ->List(Y, Y, Y, uopFADD_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSUB_S ->List(Y, Y, Y, uopFSUB_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMUL_S ->List(Y, Y, Y, uopFMUL_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FADD_D ->List(Y, Y, N, uopFADD_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSUB_D ->List(Y, Y, N, uopFSUB_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMUL_D ->List(Y, Y, N, uopFMUL_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMADD_S ->List(Y, Y, Y, uopFMADD_S, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMSUB_S ->List(Y, Y, Y, uopFMSUB_S, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FNMADD_S ->List(Y, Y, Y, uopFNMADD_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FNMSUB_S ->List(Y, Y, Y, uopFNMSUB_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMADD_D ->List(Y, Y, N, uopFMADD_D, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMSUB_D ->List(Y, Y, N, uopFMSUB_D, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FNMADD_D ->List(Y, Y, N, uopFNMADD_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FNMSUB_D ->List(Y, Y, N, uopFNMSUB_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N)
)
}
/**
* FP Divide SquareRoot Constants
*/
object FDivSqrtDecode extends DecodeConstants
{
val table: Array[(BitPat, List[BitPat])] = Array(
// frs3_en wakeup_delay
// | imm sel | bypassable (aka, known/fixed latency)
// | | uses_ldq | | is_br
// is val inst? rs1 regtype | | | uses_stq | | |
// | is fp inst? | rs2 type| | | | is_amo | | |
// | | is dst single-prec? | | | | | | | is_fence | | |
// | | | micro-opcode | | | | | | | | is_fencei | | | is breakpoint or ecall
// | | | | iq-type func dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | unit regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
FDIV_S ->List(Y, Y, Y, uopFDIV_S , IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FDIV_D ->List(Y, Y, N, uopFDIV_D , IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSQRT_S ->List(Y, Y, Y, uopFSQRT_S, IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSQRT_D ->List(Y, Y, N, uopFSQRT_D, IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N)
)
}
//scalastyle:on
/**
* RoCC initial decode
*/
object RoCCDecode extends DecodeConstants
{
// Note: We use FU_CSR since CSR instructions cannot co-execute with RoCC instructions
// frs3_en wakeup_delay
// is val inst? | imm sel | bypassable (aka, known/fixed latency)
// | is fp inst? | | uses_ldq | | is_br
// | | is single-prec rs1 regtype | | | uses_stq | | |
// | | | | rs2 type| | | | is_amo | | |
// | | | micro-code func unit | | | | | | | is_fence | | |
// | | | | iq-type | | | | | | | | | is_fencei | | | is breakpoint or ecall?
// | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
// | | | | | | | | | | | | | | | | | | | | | | | |
val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | | |
CUSTOM0 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM0_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM0_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM0_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM0_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM0_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM1_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM1_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM1_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM1_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM1_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM2_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM2_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM2_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM2_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM2_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM3 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM3_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM3_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM3_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM3_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM3_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N)
)
}
/**
* IO bundle for the Decode unit
*/
class DecodeUnitIo(implicit p: Parameters) extends BoomBundle
{
val enq = new Bundle { val uop = Input(new MicroOp()) }
val deq = new Bundle { val uop = Output(new MicroOp()) }
// from CSRFile
val status = Input(new freechips.rocketchip.rocket.MStatus())
val csr_decode = Flipped(new freechips.rocketchip.rocket.CSRDecodeIO)
val interrupt = Input(Bool())
val interrupt_cause = Input(UInt(xLen.W))
}
/**
* Decode unit that takes in a single instruction and generates a MicroOp.
*/
class DecodeUnit(implicit p: Parameters) extends BoomModule
with freechips.rocketchip.rocket.constants.MemoryOpConstants
{
val io = IO(new DecodeUnitIo)
val uop = Wire(new MicroOp())
uop := io.enq.uop
var decode_table = XDecode.table
if (usingFPU) decode_table ++= FDecode.table
if (usingFPU && usingFDivSqrt) decode_table ++= FDivSqrtDecode.table
if (usingRoCC) decode_table ++= RoCCDecode.table
decode_table ++= (if (xLen == 64) X64Decode.table else X32Decode.table)
val inst = uop.inst
val cs = Wire(new CtrlSigs()).decode(inst, decode_table)
// Exception Handling
io.csr_decode.inst := inst
val csr_en = cs.csr_cmd.isOneOf(CSR.S, CSR.C, CSR.W)
val csr_ren = cs.csr_cmd.isOneOf(CSR.S, CSR.C) && uop.lrs1 === 0.U
val system_insn = cs.csr_cmd === CSR.I
val sfence = cs.uopc === uopSFENCE
val cs_legal = cs.legal
// dontTouch(cs_legal)
val id_illegal_insn = !cs_legal ||
cs.fp_val && io.csr_decode.fp_illegal || // TODO check for illegal rm mode: (io.fpu.illegal_rm)
cs.rocc && io.csr_decode.rocc_illegal ||
cs.is_amo && !io.status.isa('a'-'a') ||
(cs.fp_val && !cs.fp_single) && !io.status.isa('d'-'a') ||
csr_en && (io.csr_decode.read_illegal || !csr_ren && io.csr_decode.write_illegal) ||
((sfence || system_insn) && io.csr_decode.system_illegal)
// cs.div && !csr.io.status.isa('m'-'a') || TODO check for illegal div instructions
def checkExceptions(x: Seq[(Bool, UInt)]) =
(x.map(_._1).reduce(_||_), PriorityMux(x))
val (xcpt_valid, xcpt_cause) = checkExceptions(List(
(io.interrupt && !io.enq.uop.is_sfb, io.interrupt_cause), // Disallow interrupts while we are handling a SFB
(uop.bp_debug_if, (CSR.debugTriggerCause).U),
(uop.bp_xcpt_if, (Causes.breakpoint).U),
(uop.xcpt_pf_if, (Causes.fetch_page_fault).U),
(uop.xcpt_ae_if, (Causes.fetch_access).U),
(id_illegal_insn, (Causes.illegal_instruction).U)))
uop.exception := xcpt_valid
uop.exc_cause := xcpt_cause
//-------------------------------------------------------------
uop.uopc := cs.uopc
uop.iq_type := cs.iq_type
uop.fu_code := cs.fu_code
// x-registers placed in 0-31, f-registers placed in 32-63.
// This allows us to straight-up compare register specifiers and not need to
// verify the rtypes (e.g., bypassing in rename).
uop.ldst := inst(RD_MSB,RD_LSB)
uop.lrs1 := inst(RS1_MSB,RS1_LSB)
uop.lrs2 := inst(RS2_MSB,RS2_LSB)
uop.lrs3 := inst(RS3_MSB,RS3_LSB)
uop.ldst_val := cs.dst_type =/= RT_X && !(uop.ldst === 0.U && uop.dst_rtype === RT_FIX)
uop.dst_rtype := cs.dst_type
uop.lrs1_rtype := cs.rs1_type
uop.lrs2_rtype := cs.rs2_type
uop.frs3_en := cs.frs3_en
uop.ldst_is_rs1 := uop.is_sfb_shadow
// SFB optimization
when (uop.is_sfb_shadow && cs.rs2_type === RT_X) {
uop.lrs2_rtype := RT_FIX
uop.lrs2 := inst(RD_MSB,RD_LSB)
uop.ldst_is_rs1 := false.B
} .elsewhen (uop.is_sfb_shadow && cs.uopc === uopADD && inst(RS1_MSB,RS1_LSB) === 0.U) {
uop.uopc := uopMOV
uop.lrs1 := inst(RD_MSB, RD_LSB)
uop.ldst_is_rs1 := true.B
}
when (uop.is_sfb_br) {
uop.fu_code := FU_JMP
}
uop.fp_val := cs.fp_val
uop.fp_single := cs.fp_single // TODO use this signal instead of the FPU decode's table signal?
uop.mem_cmd := cs.mem_cmd
uop.mem_size := Mux(cs.mem_cmd.isOneOf(M_SFENCE, M_FLUSH_ALL), Cat(uop.lrs2 =/= 0.U, uop.lrs1 =/= 0.U), inst(13,12))
uop.mem_signed := !inst(14)
uop.uses_ldq := cs.uses_ldq
uop.uses_stq := cs.uses_stq
uop.is_amo := cs.is_amo
uop.is_fence := cs.is_fence
uop.is_fencei := cs.is_fencei
uop.is_sys_pc2epc := cs.is_sys_pc2epc
uop.is_unique := cs.inst_unique
uop.flush_on_commit := cs.flush_on_commit || (csr_en && !csr_ren && io.csr_decode.write_flush)
uop.bypassable := cs.bypassable
//-------------------------------------------------------------
// immediates
// repackage the immediate, and then pass the fewest number of bits around
val di24_20 = Mux(cs.imm_sel === IS_B || cs.imm_sel === IS_S, inst(11,7), inst(24,20))
uop.imm_packed := Cat(inst(31,25), di24_20, inst(19,12))
//-------------------------------------------------------------
uop.is_br := cs.is_br
uop.is_jal := (uop.uopc === uopJAL)
uop.is_jalr := (uop.uopc === uopJALR)
// uop.is_jump := cs.is_jal || (uop.uopc === uopJALR)
// uop.is_ret := (uop.uopc === uopJALR) &&
// (uop.ldst === X0) &&
// (uop.lrs1 === RA)
// uop.is_call := (uop.uopc === uopJALR || uop.uopc === uopJAL) &&
// (uop.ldst === RA)
//-------------------------------------------------------------
io.deq.uop := uop
}
/**
* Smaller Decode unit for the Frontend to decode different
* branches.
* Accepts EXPANDED RVC instructions
*/
class BranchDecodeSignals(implicit p: Parameters) extends BoomBundle
{
val is_ret = Bool()
val is_call = Bool()
val target = UInt(vaddrBitsExtended.W)
val cfi_type = UInt(CFI_SZ.W)
// Is this branch a short forwards jump?
val sfb_offset = Valid(UInt(log2Ceil(icBlockBytes).W))
// Is this instruction allowed to be inside a sfb?
val shadowable = Bool()
}
class BranchDecode(implicit p: Parameters) extends BoomModule
{
val io = IO(new Bundle {
val inst = Input(UInt(32.W))
val pc = Input(UInt(vaddrBitsExtended.W))
val out = Output(new BranchDecodeSignals)
})
val bpd_csignals =
freechips.rocketchip.rocket.DecodeLogic(io.inst,
List[BitPat](N, N, N, N, X),
//// is br?
//// | is jal?
//// | | is jalr?
//// | | |
//// | | | shadowable
//// | | | | has_rs2
//// | | | | |
Array[(BitPat, List[BitPat])](
JAL -> List(N, Y, N, N, X),
JALR -> List(N, N, Y, N, X),
BEQ -> List(Y, N, N, N, X),
BNE -> List(Y, N, N, N, X),
BGE -> List(Y, N, N, N, X),
BGEU -> List(Y, N, N, N, X),
BLT -> List(Y, N, N, N, X),
BLTU -> List(Y, N, N, N, X),
SLLI -> List(N, N, N, Y, N),
SRLI -> List(N, N, N, Y, N),
SRAI -> List(N, N, N, Y, N),
ADDIW -> List(N, N, N, Y, N),
SLLIW -> List(N, N, N, Y, N),
SRAIW -> List(N, N, N, Y, N),
SRLIW -> List(N, N, N, Y, N),
ADDW -> List(N, N, N, Y, Y),
SUBW -> List(N, N, N, Y, Y),
SLLW -> List(N, N, N, Y, Y),
SRAW -> List(N, N, N, Y, Y),
SRLW -> List(N, N, N, Y, Y),
LUI -> List(N, N, N, Y, N),
ADDI -> List(N, N, N, Y, N),
ANDI -> List(N, N, N, Y, N),
ORI -> List(N, N, N, Y, N),
XORI -> List(N, N, N, Y, N),
SLTI -> List(N, N, N, Y, N),
SLTIU -> List(N, N, N, Y, N),
SLL -> List(N, N, N, Y, Y),
ADD -> List(N, N, N, Y, Y),
SUB -> List(N, N, N, Y, Y),
SLT -> List(N, N, N, Y, Y),
SLTU -> List(N, N, N, Y, Y),
AND -> List(N, N, N, Y, Y),
OR -> List(N, N, N, Y, Y),
XOR -> List(N, N, N, Y, Y),
SRA -> List(N, N, N, Y, Y),
SRL -> List(N, N, N, Y, Y)
))
val cs_is_br = bpd_csignals(0)(0)
val cs_is_jal = bpd_csignals(1)(0)
val cs_is_jalr = bpd_csignals(2)(0)
val cs_is_shadowable = bpd_csignals(3)(0)
val cs_has_rs2 = bpd_csignals(4)(0)
io.out.is_call := (cs_is_jal || cs_is_jalr) && GetRd(io.inst) === RA
io.out.is_ret := cs_is_jalr && GetRs1(io.inst) === BitPat("b00?01") && GetRd(io.inst) === X0
io.out.target := Mux(cs_is_br, ComputeBranchTarget(io.pc, io.inst, xLen),
ComputeJALTarget(io.pc, io.inst, xLen))
io.out.cfi_type :=
Mux(cs_is_jalr,
CFI_JALR,
Mux(cs_is_jal,
CFI_JAL,
Mux(cs_is_br,
CFI_BR,
CFI_X)))
val br_offset = Cat(io.inst(7), io.inst(30,25), io.inst(11,8), 0.U(1.W))
// Is a sfb if it points forwards (offset is positive)
io.out.sfb_offset.valid := cs_is_br && !io.inst(31) && br_offset =/= 0.U && (br_offset >> log2Ceil(icBlockBytes)) === 0.U
io.out.sfb_offset.bits := br_offset
io.out.shadowable := cs_is_shadowable && (
!cs_has_rs2 ||
(GetRs1(io.inst) === GetRd(io.inst)) ||
(io.inst === ADD && GetRs1(io.inst) === X0)
)
}
/**
* Track the current "branch mask", and give out the branch mask to each micro-op in Decode
* (each micro-op in the machine has a branch mask which says which branches it
* is being speculated under).
*
* @param pl_width pipeline width for the processor
*/
class BranchMaskGenerationLogic(val pl_width: Int)(implicit p: Parameters) extends BoomModule
{
val io = IO(new Bundle {
// guess if the uop is a branch (we'll catch this later)
val is_branch = Input(Vec(pl_width, Bool()))
// lock in that it's actually a branch and will fire, so we update
// the branch_masks.
val will_fire = Input(Vec(pl_width, Bool()))
// give out tag immediately (needed in rename)
// mask can come later in the cycle
val br_tag = Output(Vec(pl_width, UInt(brTagSz.W)))
val br_mask = Output(Vec(pl_width, UInt(maxBrCount.W)))
// tell decoders the branch mask has filled up, but on the granularity
// of an individual micro-op (so some micro-ops can go through)
val is_full = Output(Vec(pl_width, Bool()))
val brupdate = Input(new BrUpdateInfo())
val flush_pipeline = Input(Bool())
val debug_branch_mask = Output(UInt(maxBrCount.W))
})
val branch_mask = RegInit(0.U(maxBrCount.W))
//-------------------------------------------------------------
// Give out the branch tag to each branch micro-op
var allocate_mask = branch_mask
val tag_masks = Wire(Vec(pl_width, UInt(maxBrCount.W)))
for (w <- 0 until pl_width) {
// TODO this is a loss of performance as we're blocking branches based on potentially fake branches
io.is_full(w) := (allocate_mask === ~(0.U(maxBrCount.W))) && io.is_branch(w)
// find br_tag and compute next br_mask
val new_br_tag = Wire(UInt(brTagSz.W))
new_br_tag := 0.U
tag_masks(w) := 0.U
for (i <- maxBrCount-1 to 0 by -1) {
when (~allocate_mask(i)) {
new_br_tag := i.U
tag_masks(w) := (1.U << i.U)
}
}
io.br_tag(w) := new_br_tag
allocate_mask = Mux(io.is_branch(w), tag_masks(w) | allocate_mask, allocate_mask)
}
//-------------------------------------------------------------
// Give out the branch mask to each micro-op
// (kill off the bits that corresponded to branches that aren't going to fire)
var curr_mask = branch_mask
for (w <- 0 until pl_width) {
io.br_mask(w) := GetNewBrMask(io.brupdate, curr_mask)
curr_mask = Mux(io.will_fire(w), tag_masks(w) | curr_mask, curr_mask)
}
//-------------------------------------------------------------
// Update the current branch_mask
when (io.flush_pipeline) {
branch_mask := 0.U
} .otherwise {
val mask = Mux(io.brupdate.b2.mispredict,
io.brupdate.b2.uop.br_mask,
~(0.U(maxBrCount.W)))
branch_mask := GetNewBrMask(io.brupdate, curr_mask) & mask
}
io.debug_branch_mask := branch_mask
} | module BranchMaskGenerationLogic(
input clock,
input reset,
input io_is_branch_0,
input io_will_fire_0,
output [2:0] io_br_tag_0,
output [7:0] io_br_mask_0,
output io_is_full_0,
input [7:0] io_brupdate_b1_resolve_mask,
input [7:0] io_brupdate_b2_uop_br_mask,
input io_brupdate_b2_mispredict,
input io_flush_pipeline
);
reg [7:0] branch_mask;
always @(posedge clock) begin
if (reset)
branch_mask <= 8'h0;
else
branch_mask <= io_flush_pipeline ? 8'h0 : ({8{io_will_fire_0}} & (branch_mask[0] ? (branch_mask[1] ? (branch_mask[2] ? (branch_mask[3] ? (branch_mask[4] ? (branch_mask[5] ? (branch_mask[6] ? {~(branch_mask[7]), 7'h0} : 8'h40) : 8'h20) : 8'h10) : 8'h8) : 8'h4) : 8'h2) : 8'h1) | branch_mask) & ~io_brupdate_b1_resolve_mask & (io_brupdate_b2_mispredict ? io_brupdate_b2_uop_br_mask : 8'hFF);
end
assign io_br_tag_0 = branch_mask[0] ? (branch_mask[1] ? (branch_mask[2] ? (branch_mask[3] ? (branch_mask[4] ? (branch_mask[5] ? (branch_mask[6] ? {3{~(branch_mask[7])}} : 3'h6) : 3'h5) : 3'h4) : 3'h3) : 3'h2) : 3'h1) : 3'h0;
assign io_br_mask_0 = branch_mask & ~io_brupdate_b1_resolve_mask;
assign io_is_full_0 = (&branch_mask) & io_is_branch_0;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
} | module MulAddRecFNToRaw_preMul_e5_s11(
input [1:0] io_op,
input [16:0] io_a,
input [16:0] io_b,
input [16:0] io_c,
output [10:0] io_mulAddA,
output [10:0] io_mulAddB,
output [21:0] io_mulAddC,
output io_toPostMul_isSigNaNAny,
output io_toPostMul_isNaNAOrB,
output io_toPostMul_isInfA,
output io_toPostMul_isZeroA,
output io_toPostMul_isInfB,
output io_toPostMul_isZeroB,
output io_toPostMul_signProd,
output io_toPostMul_isNaNC,
output io_toPostMul_isInfC,
output io_toPostMul_isZeroC,
output [6:0] io_toPostMul_sExpSum,
output io_toPostMul_doSubMags,
output io_toPostMul_CIsDominant,
output [3:0] io_toPostMul_CDom_CAlignDist,
output [12:0] io_toPostMul_highAlignedSigC,
output io_toPostMul_bit0AlignedSigC
);
wire rawA_isNaN = (&(io_a[15:14])) & io_a[13];
wire rawB_isNaN = (&(io_b[15:14])) & io_b[13];
wire rawC_isNaN = (&(io_c[15:14])) & io_c[13];
wire signProd = io_a[16] ^ io_b[16] ^ io_op[1];
wire [7:0] _sExpAlignedProd_T_1 = {2'h0, io_a[15:10]} + {2'h0, io_b[15:10]} - 8'h12;
wire doSubMags = signProd ^ io_c[16] ^ io_op[0];
wire [7:0] _sNatCAlignDist_T = _sExpAlignedProd_T_1 - {2'h0, io_c[15:10]};
wire isMinCAlign = ~(|(io_a[15:13])) | ~(|(io_b[15:13])) | $signed(_sNatCAlignDist_T) < 8'sh0;
wire CIsDominant = (|(io_c[15:13])) & (isMinCAlign | _sNatCAlignDist_T[6:0] < 7'hC);
wire [5:0] CAlignDist = isMinCAlign ? 6'h0 : _sNatCAlignDist_T[6:0] < 7'h23 ? _sNatCAlignDist_T[5:0] : 6'h23;
wire [38:0] mainAlignedSigC = $signed($signed({doSubMags ? {1'h1, ~(|(io_c[15:13])), ~(io_c[9:0])} : {1'h0, |(io_c[15:13]), io_c[9:0]}, {27{doSubMags}}}) >>> CAlignDist);
wire [16:0] reduced4CExtra_shift = $signed(17'sh10000 >>> CAlignDist[5:2]);
wire [1:0] _GEN = {|(io_c[7:4]), |(io_c[3:0])} & {reduced4CExtra_shift[8], reduced4CExtra_shift[9]};
assign io_mulAddA = {|(io_a[15:13]), io_a[9:0]};
assign io_mulAddB = {|(io_b[15:13]), io_b[9:0]};
assign io_mulAddC = mainAlignedSigC[24:3];
assign io_toPostMul_isSigNaNAny = rawA_isNaN & ~(io_a[9]) | rawB_isNaN & ~(io_b[9]) | rawC_isNaN & ~(io_c[9]);
assign io_toPostMul_isNaNAOrB = rawA_isNaN | rawB_isNaN;
assign io_toPostMul_isInfA = (&(io_a[15:14])) & ~(io_a[13]);
assign io_toPostMul_isZeroA = ~(|(io_a[15:13]));
assign io_toPostMul_isInfB = (&(io_b[15:14])) & ~(io_b[13]);
assign io_toPostMul_isZeroB = ~(|(io_b[15:13]));
assign io_toPostMul_signProd = signProd;
assign io_toPostMul_isNaNC = rawC_isNaN;
assign io_toPostMul_isInfC = (&(io_c[15:14])) & ~(io_c[13]);
assign io_toPostMul_isZeroC = ~(|(io_c[15:13]));
assign io_toPostMul_sExpSum = CIsDominant ? {1'h0, io_c[15:10]} : _sExpAlignedProd_T_1[6:0] - 7'hB;
assign io_toPostMul_doSubMags = doSubMags;
assign io_toPostMul_CIsDominant = CIsDominant;
assign io_toPostMul_CDom_CAlignDist = CAlignDist[3:0];
assign io_toPostMul_highAlignedSigC = mainAlignedSigC[37:25];
assign io_toPostMul_bit0AlignedSigC = doSubMags ? (&(mainAlignedSigC[2:0])) & _GEN == 2'h0 : (|{mainAlignedSigC[2:0], _GEN});
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Functional Unit Decode
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Generate the functional unit control signals from the micro-op opcodes.
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.uintToBitPat
import freechips.rocketchip.rocket.CSR
import freechips.rocketchip.rocket.ALU._
import boom.v3.common._
/**
* Control signal bundle for register renaming
*/
class RRdCtrlSigs(implicit p: Parameters) extends BoomBundle
{
val br_type = UInt(BR_N.getWidth.W)
val use_alupipe = Bool()
val use_muldivpipe = Bool()
val use_mempipe = Bool()
val op_fcn = Bits(SZ_ALU_FN.W)
val fcn_dw = Bool()
val op1_sel = UInt(OP1_X.getWidth.W)
val op2_sel = UInt(OP2_X.getWidth.W)
val imm_sel = UInt(IS_X.getWidth.W)
val rf_wen = Bool()
val csr_cmd = Bits(CSR.SZ.W)
def decode(uopc: UInt, table: Iterable[(BitPat, List[BitPat])]) = {
val decoder = freechips.rocketchip.rocket.DecodeLogic(uopc, AluRRdDecode.default, table)
val sigs = Seq(br_type, use_alupipe, use_muldivpipe, use_mempipe, op_fcn,
fcn_dw, op1_sel, op2_sel, imm_sel, rf_wen, csr_cmd)
sigs zip decoder map {case(s,d) => s := d}
this
}
}
/**
* Default register read constants
*/
abstract trait RRdDecodeConstants
{
val default: List[BitPat] =
List[BitPat](BR_N , Y, N, N, FN_ADD , DW_X , OP1_X , OP2_X , IS_X, REN_0, CSR.N)
val table: Array[(BitPat, List[BitPat])]
}
/**
* ALU register read constants
*/
object AluRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopLUI) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMM , IS_U, REN_1, CSR.N),
BitPat(uopADDI) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopANDI) -> List(BR_N , Y, N, N, FN_AND , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopORI) -> List(BR_N , Y, N, N, FN_OR , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopXORI) -> List(BR_N , Y, N, N, FN_XOR , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSLTI) -> List(BR_N , Y, N, N, FN_SLT , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSLTIU) -> List(BR_N , Y, N, N, FN_SLTU, DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSLLI) -> List(BR_N , Y, N, N, FN_SL , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSRAI) -> List(BR_N , Y, N, N, FN_SRA , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSRLI) -> List(BR_N , Y, N, N, FN_SR , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopADDIW) -> List(BR_N , Y, N, N, FN_ADD , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSLLIW) -> List(BR_N , Y, N, N, FN_SL , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSRAIW) -> List(BR_N , Y, N, N, FN_SRA , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSRLIW) -> List(BR_N , Y, N, N, FN_SR , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopADD) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSLL) -> List(BR_N , Y, N, N, FN_SL , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSUB) -> List(BR_N , Y, N, N, FN_SUB , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSLT) -> List(BR_N , Y, N, N, FN_SLT , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSLTU) -> List(BR_N , Y, N, N, FN_SLTU, DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopAND) -> List(BR_N , Y, N, N, FN_AND , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopOR) -> List(BR_N , Y, N, N, FN_OR , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopXOR) -> List(BR_N , Y, N, N, FN_XOR , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSRA) -> List(BR_N , Y, N, N, FN_SRA , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSRL) -> List(BR_N , Y, N, N, FN_SR , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopADDW) -> List(BR_N , Y, N, N, FN_ADD , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSUBW) -> List(BR_N , Y, N, N, FN_SUB , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSLLW) -> List(BR_N , Y, N, N, FN_SL , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSRAW) -> List(BR_N , Y, N, N, FN_SRA , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSRLW) -> List(BR_N , Y, N, N, FN_SR , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopBEQ) -> List(BR_EQ ,Y, N, N, FN_SUB , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),
BitPat(uopBNE) -> List(BR_NE ,Y, N, N, FN_SUB , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),
BitPat(uopBGE) -> List(BR_GE ,Y, N, N, FN_SLT , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),
BitPat(uopBGEU) -> List(BR_GEU,Y, N, N, FN_SLTU, DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),
BitPat(uopBLT) -> List(BR_LT ,Y, N, N, FN_SLT , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),
BitPat(uopBLTU) -> List(BR_LTU,Y, N, N, FN_SLTU, DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N))
}
object JmpRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopJAL) -> List(BR_J , Y, N, N, FN_ADD , DW_XPR, OP1_PC , OP2_NEXT, IS_J, REN_1, CSR.N),
BitPat(uopJALR) -> List(BR_JR, Y, N, N, FN_ADD , DW_XPR, OP1_PC , OP2_NEXT, IS_I, REN_1, CSR.N),
BitPat(uopAUIPC) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_PC , OP2_IMM , IS_U, REN_1, CSR.N))
}
/**
* Multiply divider register read constants
*/
object MulDivRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopMUL) -> List(BR_N , N, Y, N, FN_MUL, DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),
BitPat(uopMULH) -> List(BR_N , N, Y, N, FN_MULH, DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),
BitPat(uopMULHU) -> List(BR_N , N, Y, N, FN_MULHU, DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),
BitPat(uopMULHSU)-> List(BR_N , N, Y, N, FN_MULHSU,DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),
BitPat(uopMULW) -> List(BR_N , N, Y, N, FN_MUL, DW_32 ,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),
BitPat(uopDIV) -> List(BR_N , N, Y, N, FN_DIV , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopDIVU) -> List(BR_N , N, Y, N, FN_DIVU, DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopREM) -> List(BR_N , N, Y, N, FN_REM , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopREMU) -> List(BR_N , N, Y, N, FN_REMU, DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopDIVW) -> List(BR_N , N, Y, N, FN_DIV , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopDIVUW) -> List(BR_N , N, Y, N, FN_DIVU, DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopREMW) -> List(BR_N , N, Y, N, FN_REM , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopREMUW) -> List(BR_N , N, Y, N, FN_REMU, DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N))
}
/**
* Memory unit register read constants
*/
object MemRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopLD) -> List(BR_N , N, N, Y, FN_ADD , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_0, CSR.N),
BitPat(uopSTA) -> List(BR_N , N, N, Y, FN_ADD , DW_XPR, OP1_RS1 , OP2_IMM , IS_S, REN_0, CSR.N),
BitPat(uopSTD) -> List(BR_N , N, N, Y, FN_X , DW_X , OP1_RS1 , OP2_RS2 , IS_X, REN_0, CSR.N),
BitPat(uopSFENCE)-> List(BR_N , N, N, Y, FN_X , DW_X , OP1_RS1 , OP2_RS2 , IS_X, REN_0, CSR.N),
BitPat(uopAMO_AG)-> List(BR_N , N, N, Y, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_X, REN_0, CSR.N))
}
/**
* CSR register read constants
*/
object CsrRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopCSRRW) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_I, REN_1, CSR.W),
BitPat(uopCSRRS) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_I, REN_1, CSR.S),
BitPat(uopCSRRC) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_I, REN_1, CSR.C),
BitPat(uopCSRRWI)-> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_1, CSR.W),
BitPat(uopCSRRSI)-> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_1, CSR.S),
BitPat(uopCSRRCI)-> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_1, CSR.C),
BitPat(uopWFI) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_0, CSR.I),
BitPat(uopERET) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_0, CSR.I))
}
/**
* FPU register read constants
*/
object FpuRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopFCLASS_S)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCLASS_D)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
// BitPat(uopFMV_W_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
// BitPat(uopFMV_D_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMV_X_W)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMV_X_D)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFSGNJ_S)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFSGNJ_D)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCVT_S_D) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCVT_D_S) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
// TODO comment out I2F instructions.
BitPat(uopFCVT_S_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCVT_D_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCVT_X_S) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCVT_X_D) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopCMPR_S) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopCMPR_D) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMINMAX_S)->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMINMAX_D)->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFADD_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFSUB_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMUL_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFADD_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFSUB_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMUL_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMADD_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMSUB_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFNMADD_S)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFNMSUB_S)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMADD_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMSUB_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFNMADD_D)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFNMSUB_D)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N))
}
/**
* Fused multiple add register read constants
*/
object IfmvRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopFMV_W_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMV_D_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCVT_S_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCVT_D_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N))
}
/**
* Floating point divide and square root register read constants
*/
object FDivRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopFDIV_S) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFDIV_D) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFSQRT_S) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFSQRT_D) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N))
}
/**
* Register read decoder
*
* @param supportedUnits indicate what functional units are being used
*/
class RegisterReadDecode(supportedUnits: SupportedFuncUnits)(implicit p: Parameters) extends BoomModule
with freechips.rocketchip.rocket.constants.MemoryOpConstants
{
val io = IO(new BoomBundle {
val iss_valid = Input(Bool())
val iss_uop = Input(new MicroOp())
val rrd_valid = Output(Bool())
val rrd_uop = Output(new MicroOp())
})
// Issued Instruction
val rrd_valid = io.iss_valid
io.rrd_uop := io.iss_uop
var dec_table = AluRRdDecode.table
if (supportedUnits.jmp) dec_table ++= JmpRRdDecode.table
if (supportedUnits.mem) dec_table ++= MemRRdDecode.table
if (supportedUnits.muld) dec_table ++= MulDivRRdDecode.table
if (supportedUnits.csr) dec_table ++= CsrRRdDecode.table
if (supportedUnits.fpu) dec_table ++= FpuRRdDecode.table
if (supportedUnits.fdiv) dec_table ++= FDivRRdDecode.table
if (supportedUnits.ifpu) dec_table ++= IfmvRRdDecode.table
val rrd_cs = Wire(new RRdCtrlSigs()).decode(io.rrd_uop.uopc, dec_table)
// rrd_use_alupipe is unused
io.rrd_uop.ctrl.br_type := rrd_cs.br_type
io.rrd_uop.ctrl.op1_sel := rrd_cs.op1_sel
io.rrd_uop.ctrl.op2_sel := rrd_cs.op2_sel
io.rrd_uop.ctrl.imm_sel := rrd_cs.imm_sel
io.rrd_uop.ctrl.op_fcn := rrd_cs.op_fcn.asUInt
io.rrd_uop.ctrl.fcn_dw := rrd_cs.fcn_dw.asBool
io.rrd_uop.ctrl.is_load := io.rrd_uop.uopc === uopLD
io.rrd_uop.ctrl.is_sta := io.rrd_uop.uopc === uopSTA || io.rrd_uop.uopc === uopAMO_AG
io.rrd_uop.ctrl.is_std := io.rrd_uop.uopc === uopSTD || (io.rrd_uop.ctrl.is_sta && io.rrd_uop.lrs2_rtype === RT_FIX)
when (io.rrd_uop.uopc === uopAMO_AG || (io.rrd_uop.uopc === uopLD && io.rrd_uop.mem_cmd === M_XLR)) {
io.rrd_uop.imm_packed := 0.U
}
val raddr1 = io.rrd_uop.prs1 // although renamed, it'll stay 0 if lrs1 = 0
val csr_ren = (rrd_cs.csr_cmd === CSR.S || rrd_cs.csr_cmd === CSR.C) && raddr1 === 0.U
io.rrd_uop.ctrl.csr_cmd := Mux(csr_ren, CSR.R, rrd_cs.csr_cmd)
//-------------------------------------------------------------
// set outputs
io.rrd_valid := rrd_valid
} | module RegisterReadDecode(
input io_iss_valid,
input [6:0] io_iss_uop_uopc,
input [31:0] io_iss_uop_inst,
input [31:0] io_iss_uop_debug_inst,
input io_iss_uop_is_rvc,
input [39:0] io_iss_uop_debug_pc,
input [2:0] io_iss_uop_iq_type,
input [9:0] io_iss_uop_fu_code,
input [1:0] io_iss_uop_iw_state,
input io_iss_uop_is_br,
input io_iss_uop_is_jalr,
input io_iss_uop_is_jal,
input io_iss_uop_is_sfb,
input [7:0] io_iss_uop_br_mask,
input [2:0] io_iss_uop_br_tag,
input [3:0] io_iss_uop_ftq_idx,
input io_iss_uop_edge_inst,
input [5:0] io_iss_uop_pc_lob,
input io_iss_uop_taken,
input [19:0] io_iss_uop_imm_packed,
input [11:0] io_iss_uop_csr_addr,
input [4:0] io_iss_uop_rob_idx,
input [2:0] io_iss_uop_ldq_idx,
input [2:0] io_iss_uop_stq_idx,
input [1:0] io_iss_uop_rxq_idx,
input [5:0] io_iss_uop_pdst,
input [5:0] io_iss_uop_prs1,
input [5:0] io_iss_uop_prs2,
input [5:0] io_iss_uop_prs3,
input [3:0] io_iss_uop_ppred,
input io_iss_uop_prs1_busy,
input io_iss_uop_prs2_busy,
input io_iss_uop_prs3_busy,
input io_iss_uop_ppred_busy,
input [5:0] io_iss_uop_stale_pdst,
input io_iss_uop_exception,
input [63:0] io_iss_uop_exc_cause,
input io_iss_uop_bypassable,
input [4:0] io_iss_uop_mem_cmd,
input [1:0] io_iss_uop_mem_size,
input io_iss_uop_mem_signed,
input io_iss_uop_is_fence,
input io_iss_uop_is_fencei,
input io_iss_uop_is_amo,
input io_iss_uop_uses_ldq,
input io_iss_uop_uses_stq,
input io_iss_uop_is_sys_pc2epc,
input io_iss_uop_is_unique,
input io_iss_uop_flush_on_commit,
input io_iss_uop_ldst_is_rs1,
input [5:0] io_iss_uop_ldst,
input [5:0] io_iss_uop_lrs1,
input [5:0] io_iss_uop_lrs2,
input [5:0] io_iss_uop_lrs3,
input io_iss_uop_ldst_val,
input [1:0] io_iss_uop_dst_rtype,
input [1:0] io_iss_uop_lrs1_rtype,
input [1:0] io_iss_uop_lrs2_rtype,
input io_iss_uop_frs3_en,
input io_iss_uop_fp_val,
input io_iss_uop_fp_single,
input io_iss_uop_xcpt_pf_if,
input io_iss_uop_xcpt_ae_if,
input io_iss_uop_xcpt_ma_if,
input io_iss_uop_bp_debug_if,
input io_iss_uop_bp_xcpt_if,
input [1:0] io_iss_uop_debug_fsrc,
input [1:0] io_iss_uop_debug_tsrc,
output io_rrd_valid,
output [6:0] io_rrd_uop_uopc,
output [31:0] io_rrd_uop_inst,
output [31:0] io_rrd_uop_debug_inst,
output io_rrd_uop_is_rvc,
output [39:0] io_rrd_uop_debug_pc,
output [2:0] io_rrd_uop_iq_type,
output [9:0] io_rrd_uop_fu_code,
output [3:0] io_rrd_uop_ctrl_br_type,
output [1:0] io_rrd_uop_ctrl_op1_sel,
output [2:0] io_rrd_uop_ctrl_op2_sel,
output [2:0] io_rrd_uop_ctrl_imm_sel,
output [4:0] io_rrd_uop_ctrl_op_fcn,
output io_rrd_uop_ctrl_fcn_dw,
output [2:0] io_rrd_uop_ctrl_csr_cmd,
output io_rrd_uop_ctrl_is_load,
output io_rrd_uop_ctrl_is_sta,
output io_rrd_uop_ctrl_is_std,
output [1:0] io_rrd_uop_iw_state,
output io_rrd_uop_is_br,
output io_rrd_uop_is_jalr,
output io_rrd_uop_is_jal,
output io_rrd_uop_is_sfb,
output [7:0] io_rrd_uop_br_mask,
output [2:0] io_rrd_uop_br_tag,
output [3:0] io_rrd_uop_ftq_idx,
output io_rrd_uop_edge_inst,
output [5:0] io_rrd_uop_pc_lob,
output io_rrd_uop_taken,
output [19:0] io_rrd_uop_imm_packed,
output [11:0] io_rrd_uop_csr_addr,
output [4:0] io_rrd_uop_rob_idx,
output [2:0] io_rrd_uop_ldq_idx,
output [2:0] io_rrd_uop_stq_idx,
output [1:0] io_rrd_uop_rxq_idx,
output [5:0] io_rrd_uop_pdst,
output [5:0] io_rrd_uop_prs1,
output [5:0] io_rrd_uop_prs2,
output [5:0] io_rrd_uop_prs3,
output [3:0] io_rrd_uop_ppred,
output io_rrd_uop_prs1_busy,
output io_rrd_uop_prs2_busy,
output io_rrd_uop_prs3_busy,
output io_rrd_uop_ppred_busy,
output [5:0] io_rrd_uop_stale_pdst,
output io_rrd_uop_exception,
output [63:0] io_rrd_uop_exc_cause,
output io_rrd_uop_bypassable,
output [4:0] io_rrd_uop_mem_cmd,
output [1:0] io_rrd_uop_mem_size,
output io_rrd_uop_mem_signed,
output io_rrd_uop_is_fence,
output io_rrd_uop_is_fencei,
output io_rrd_uop_is_amo,
output io_rrd_uop_uses_ldq,
output io_rrd_uop_uses_stq,
output io_rrd_uop_is_sys_pc2epc,
output io_rrd_uop_is_unique,
output io_rrd_uop_flush_on_commit,
output io_rrd_uop_ldst_is_rs1,
output [5:0] io_rrd_uop_ldst,
output [5:0] io_rrd_uop_lrs1,
output [5:0] io_rrd_uop_lrs2,
output [5:0] io_rrd_uop_lrs3,
output io_rrd_uop_ldst_val,
output [1:0] io_rrd_uop_dst_rtype,
output [1:0] io_rrd_uop_lrs1_rtype,
output [1:0] io_rrd_uop_lrs2_rtype,
output io_rrd_uop_frs3_en,
output io_rrd_uop_fp_val,
output io_rrd_uop_fp_single,
output io_rrd_uop_xcpt_pf_if,
output io_rrd_uop_xcpt_ae_if,
output io_rrd_uop_xcpt_ma_if,
output io_rrd_uop_bp_debug_if,
output io_rrd_uop_bp_xcpt_if,
output [1:0] io_rrd_uop_debug_fsrc,
output [1:0] io_rrd_uop_debug_tsrc
);
wire [6:0] rrd_cs_decoder_decoded_invInputs = ~io_iss_uop_uopc;
wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_3 = {rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]};
wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_6 = {io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5]};
wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_49 = {io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};
wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_52 = {rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};
wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_55 = {io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], io_iss_uop_uopc[6]};
wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_57 = {rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[6]};
wire [2:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_58 = {io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[5], io_iss_uop_uopc[6]};
wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_59 = {rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], io_iss_uop_uopc[6]};
wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_60 = {rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], io_iss_uop_uopc[6]};
wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_61 = {io_iss_uop_uopc[0], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], io_iss_uop_uopc[6]};
wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_62 = {rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], io_iss_uop_uopc[6]};
wire io_rrd_uop_ctrl_is_load_0 = io_iss_uop_uopc == 7'h1;
wire _io_rrd_uop_ctrl_is_sta_T_1 = io_iss_uop_uopc == 7'h43;
wire io_rrd_uop_ctrl_is_sta_0 = io_iss_uop_uopc == 7'h2 | _io_rrd_uop_ctrl_is_sta_T_1;
assign io_rrd_valid = io_iss_valid;
assign io_rrd_uop_uopc = io_iss_uop_uopc;
assign io_rrd_uop_inst = io_iss_uop_inst;
assign io_rrd_uop_debug_inst = io_iss_uop_debug_inst;
assign io_rrd_uop_is_rvc = io_iss_uop_is_rvc;
assign io_rrd_uop_debug_pc = io_iss_uop_debug_pc;
assign io_rrd_uop_iq_type = io_iss_uop_iq_type;
assign io_rrd_uop_fu_code = io_iss_uop_fu_code;
assign io_rrd_uop_ctrl_br_type = {1'h0, |{&{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}}, |{&{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}}, |{&{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}}};
assign io_rrd_uop_ctrl_op1_sel = {1'h0, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_3};
assign io_rrd_uop_ctrl_op2_sel = {2'h0, |{&{rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}}};
assign io_rrd_uop_ctrl_imm_sel = {1'h0, |{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_3, &{io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_3};
assign io_rrd_uop_ctrl_op_fcn =
{|{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_55, &{io_iss_uop_uopc[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[5], io_iss_uop_uopc[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_59, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_60, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_62},
|{&{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_49, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_55, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_59, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_61, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_62},
|{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_6, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5]}, &{io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5]}, &{io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_60, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_62},
|{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_6, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_49, &{rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_59, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_60, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_61, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_62},
|{&{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5]}, &{io_iss_uop_uopc[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_52, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_55, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_59, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_60, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_62}};
assign io_rrd_uop_ctrl_fcn_dw = {&{io_iss_uop_uopc[0], io_iss_uop_uopc[1], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_52} == 3'h0;
assign io_rrd_uop_ctrl_csr_cmd = 3'h0;
assign io_rrd_uop_ctrl_is_load = io_rrd_uop_ctrl_is_load_0;
assign io_rrd_uop_ctrl_is_sta = io_rrd_uop_ctrl_is_sta_0;
assign io_rrd_uop_ctrl_is_std = io_iss_uop_uopc == 7'h3 | io_rrd_uop_ctrl_is_sta_0 & io_iss_uop_lrs2_rtype == 2'h0;
assign io_rrd_uop_iw_state = io_iss_uop_iw_state;
assign io_rrd_uop_is_br = io_iss_uop_is_br;
assign io_rrd_uop_is_jalr = io_iss_uop_is_jalr;
assign io_rrd_uop_is_jal = io_iss_uop_is_jal;
assign io_rrd_uop_is_sfb = io_iss_uop_is_sfb;
assign io_rrd_uop_br_mask = io_iss_uop_br_mask;
assign io_rrd_uop_br_tag = io_iss_uop_br_tag;
assign io_rrd_uop_ftq_idx = io_iss_uop_ftq_idx;
assign io_rrd_uop_edge_inst = io_iss_uop_edge_inst;
assign io_rrd_uop_pc_lob = io_iss_uop_pc_lob;
assign io_rrd_uop_taken = io_iss_uop_taken;
assign io_rrd_uop_imm_packed = _io_rrd_uop_ctrl_is_sta_T_1 | io_rrd_uop_ctrl_is_load_0 & io_iss_uop_mem_cmd == 5'h6 ? 20'h0 : io_iss_uop_imm_packed;
assign io_rrd_uop_csr_addr = io_iss_uop_csr_addr;
assign io_rrd_uop_rob_idx = io_iss_uop_rob_idx;
assign io_rrd_uop_ldq_idx = io_iss_uop_ldq_idx;
assign io_rrd_uop_stq_idx = io_iss_uop_stq_idx;
assign io_rrd_uop_rxq_idx = io_iss_uop_rxq_idx;
assign io_rrd_uop_pdst = io_iss_uop_pdst;
assign io_rrd_uop_prs1 = io_iss_uop_prs1;
assign io_rrd_uop_prs2 = io_iss_uop_prs2;
assign io_rrd_uop_prs3 = io_iss_uop_prs3;
assign io_rrd_uop_ppred = io_iss_uop_ppred;
assign io_rrd_uop_prs1_busy = io_iss_uop_prs1_busy;
assign io_rrd_uop_prs2_busy = io_iss_uop_prs2_busy;
assign io_rrd_uop_prs3_busy = io_iss_uop_prs3_busy;
assign io_rrd_uop_ppred_busy = io_iss_uop_ppred_busy;
assign io_rrd_uop_stale_pdst = io_iss_uop_stale_pdst;
assign io_rrd_uop_exception = io_iss_uop_exception;
assign io_rrd_uop_exc_cause = io_iss_uop_exc_cause;
assign io_rrd_uop_bypassable = io_iss_uop_bypassable;
assign io_rrd_uop_mem_cmd = io_iss_uop_mem_cmd;
assign io_rrd_uop_mem_size = io_iss_uop_mem_size;
assign io_rrd_uop_mem_signed = io_iss_uop_mem_signed;
assign io_rrd_uop_is_fence = io_iss_uop_is_fence;
assign io_rrd_uop_is_fencei = io_iss_uop_is_fencei;
assign io_rrd_uop_is_amo = io_iss_uop_is_amo;
assign io_rrd_uop_uses_ldq = io_iss_uop_uses_ldq;
assign io_rrd_uop_uses_stq = io_iss_uop_uses_stq;
assign io_rrd_uop_is_sys_pc2epc = io_iss_uop_is_sys_pc2epc;
assign io_rrd_uop_is_unique = io_iss_uop_is_unique;
assign io_rrd_uop_flush_on_commit = io_iss_uop_flush_on_commit;
assign io_rrd_uop_ldst_is_rs1 = io_iss_uop_ldst_is_rs1;
assign io_rrd_uop_ldst = io_iss_uop_ldst;
assign io_rrd_uop_lrs1 = io_iss_uop_lrs1;
assign io_rrd_uop_lrs2 = io_iss_uop_lrs2;
assign io_rrd_uop_lrs3 = io_iss_uop_lrs3;
assign io_rrd_uop_ldst_val = io_iss_uop_ldst_val;
assign io_rrd_uop_dst_rtype = io_iss_uop_dst_rtype;
assign io_rrd_uop_lrs1_rtype = io_iss_uop_lrs1_rtype;
assign io_rrd_uop_lrs2_rtype = io_iss_uop_lrs2_rtype;
assign io_rrd_uop_frs3_en = io_iss_uop_frs3_en;
assign io_rrd_uop_fp_val = io_iss_uop_fp_val;
assign io_rrd_uop_fp_single = io_iss_uop_fp_single;
assign io_rrd_uop_xcpt_pf_if = io_iss_uop_xcpt_pf_if;
assign io_rrd_uop_xcpt_ae_if = io_iss_uop_xcpt_ae_if;
assign io_rrd_uop_xcpt_ma_if = io_iss_uop_xcpt_ma_if;
assign io_rrd_uop_bp_debug_if = io_iss_uop_bp_debug_if;
assign io_rrd_uop_bp_xcpt_if = io_iss_uop_bp_xcpt_if;
assign io_rrd_uop_debug_fsrc = io_iss_uop_debug_fsrc;
assign io_rrd_uop_debug_tsrc = io_iss_uop_debug_tsrc;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{Decoupled, DecoupledIO}
// A Repeater passes its input to its output, unless repeat is asserted.
// When repeat is asserted, the Repeater copies the input and repeats it next cycle.
class Repeater[T <: Data](gen: T) extends Module
{
override def desiredName = s"Repeater_${gen.typeName}"
val io = IO( new Bundle {
val repeat = Input(Bool())
val full = Output(Bool())
val enq = Flipped(Decoupled(gen.cloneType))
val deq = Decoupled(gen.cloneType)
} )
val full = RegInit(false.B)
val saved = Reg(gen.cloneType)
// When !full, a repeater is pass-through
io.deq.valid := io.enq.valid || full
io.enq.ready := io.deq.ready && !full
io.deq.bits := Mux(full, saved, io.enq.bits)
io.full := full
when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }
when (io.deq.fire && !io.repeat) { full := false.B }
}
object Repeater
{
def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {
val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))
repeater.io.repeat := repeat
repeater.io.enq <> enq
repeater.io.deq
}
} | module Repeater_TLBundleA_a12d64s7k1z3u(
input clock,
input reset,
input io_repeat,
output io_full,
output io_enq_ready,
input io_enq_valid,
input [2:0] io_enq_bits_opcode,
input [2:0] io_enq_bits_param,
input [2:0] io_enq_bits_size,
input [6:0] io_enq_bits_source,
input [11:0] io_enq_bits_address,
input [7:0] io_enq_bits_mask,
input io_enq_bits_corrupt,
input io_deq_ready,
output io_deq_valid,
output [2:0] io_deq_bits_opcode,
output [2:0] io_deq_bits_param,
output [2:0] io_deq_bits_size,
output [6:0] io_deq_bits_source,
output [11:0] io_deq_bits_address,
output [7:0] io_deq_bits_mask,
output io_deq_bits_corrupt
);
reg full;
reg [2:0] saved_opcode;
reg [2:0] saved_param;
reg [2:0] saved_size;
reg [6:0] saved_source;
reg [11:0] saved_address;
reg [7:0] saved_mask;
reg saved_corrupt;
wire io_deq_valid_0 = io_enq_valid | full;
wire io_enq_ready_0 = io_deq_ready & ~full;
wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat;
always @(posedge clock) begin
if (reset)
full <= 1'h0;
else
full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full);
if (_GEN) begin
saved_opcode <= io_enq_bits_opcode;
saved_param <= io_enq_bits_param;
saved_size <= io_enq_bits_size;
saved_source <= io_enq_bits_source;
saved_address <= io_enq_bits_address;
saved_mask <= io_enq_bits_mask;
saved_corrupt <= io_enq_bits_corrupt;
end
end
assign io_full = full;
assign io_enq_ready = io_enq_ready_0;
assign io_deq_valid = io_deq_valid_0;
assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode;
assign io_deq_bits_param = full ? saved_param : io_enq_bits_param;
assign io_deq_bits_size = full ? saved_size : io_enq_bits_size;
assign io_deq_bits_source = full ? saved_source : io_enq_bits_source;
assign io_deq_bits_address = full ? saved_address : io_enq_bits_address;
assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask;
assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)
{
val queueBits = log2Up(queues)
val entryBits = log2Up(entries)
}
class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle
{
val index = UInt(params.queueBits.W)
val data = Output(params.gen)
}
class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module
{
override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}"
val io = IO(new Bundle {
// push is visible on the same cycle; flow queues
val push = Flipped(Decoupled(new ListBufferPush(params)))
val valid = UInt(params.queues.W)
val pop = Flipped(Valid(UInt(params.queueBits.W)))
val data = Output(params.gen)
})
val valid = RegInit(0.U(params.queues.W))
val head = Mem(params.queues, UInt(params.entryBits.W))
val tail = Mem(params.queues, UInt(params.entryBits.W))
val used = RegInit(0.U(params.entries.W))
val next = Mem(params.entries, UInt(params.entryBits.W))
val data = Mem(params.entries, params.gen)
val freeOH = ~(leftOR(~used) << 1) & ~used
val freeIdx = OHToUInt(freeOH)
val valid_set = WireDefault(0.U(params.queues.W))
val valid_clr = WireDefault(0.U(params.queues.W))
val used_set = WireDefault(0.U(params.entries.W))
val used_clr = WireDefault(0.U(params.entries.W))
val push_tail = tail.read(io.push.bits.index)
val push_valid = valid(io.push.bits.index)
io.push.ready := !used.andR
when (io.push.fire) {
valid_set := UIntToOH(io.push.bits.index, params.queues)
used_set := freeOH
data.write(freeIdx, io.push.bits.data)
when (push_valid) {
next.write(push_tail, freeIdx)
} .otherwise {
head.write(io.push.bits.index, freeIdx)
}
tail.write(io.push.bits.index, freeIdx)
}
val pop_head = head.read(io.pop.bits)
val pop_valid = valid(io.pop.bits)
// Bypass push data to the peek port
io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))
io.valid := (if (!params.bypass) valid else (valid | valid_set))
// It is an error to pop something that is not valid
assert (!io.pop.fire || (io.valid)(io.pop.bits))
when (io.pop.fire) {
used_clr := UIntToOH(pop_head, params.entries)
when (pop_head === tail.read(io.pop.bits)) {
valid_clr := UIntToOH(io.pop.bits, params.queues)
}
head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))
}
// Empty bypass changes no state
when ((!params.bypass).B || !io.pop.valid || pop_valid) {
used := (used & ~used_clr) | used_set
valid := (valid & ~valid_clr) | valid_set
}
} | module next_40x6(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [5:0] R0_data,
input [5:0] W0_addr,
input W0_en,
input W0_clk,
input [5:0] W0_data
);
reg [5:0] Memory[0:39];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 6'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(t))
val out = Decoupled(new Flit(flitWidth))
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))
data(0) := DontCare // unused, DCE this
}
}
io.busy := io.out.valid
}
class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(t)
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits := (if (dataBeats == 1) {
io.in.bits.flit.asTypeOf(t)
} else {
Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)
})
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit
}
}
}
io.busy := beat =/= 0.U
}
class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Phit(phitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail
}
}
}
object FlitToPhit {
def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {
val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))
flit2phit.io.in <> flit
flit2phit.io.out
}
}
class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Decoupled(new Flit(flitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat) := io.in.bits.phit
}
}
}
}
object PhitToFlit {
def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in <> phit
phit2flit.io.out
}
def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in.valid := phit.valid
phit2flit.io.in.bits := phit.bits
when (phit.valid) { assert(phit2flit.io.in.ready) }
val out = Wire(Valid(new Flit(flitWidth)))
out.valid := phit2flit.io.out.valid
out.bits := phit2flit.io.out.bits
phit2flit.io.out.ready := true.B
out
}
}
class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))
val out = Decoupled(new Phit(phitWidth))
})
if (channels == 1) {
io.out <> io.in(0)
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val chosen_reg = Reg(UInt(headerWidth.W))
val chosen_prio = PriorityEncoder(io.in.map(_.valid))
val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.out.valid := VecInit(io.in.map(_.valid))(chosen)
io.out.bits.phit := Mux(beat < headerBeats.U,
chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),
VecInit(io.in.map(_.bits.phit))(chosen))
for (i <- 0 until channels) {
io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U
}
when (io.out.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) { chosen_reg := chosen_prio }
}
}
}
class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Vec(channels, Decoupled(new Phit(phitWidth)))
})
if (channels == 1) {
io.out(0) <> io.in
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))
val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)
for (c <- 0 until channels) {
io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U
io.out(c).bits.phit := io.in.bits.phit
}
when (io.in.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat < headerBeats.U) {
channel_vec(header_idx) := io.in.bits.phit
}
}
}
}
class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Flipped(Decoupled(new Flit(flitWidth)))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = io.out.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)
}
io.out.valid := io.in.valid && credits < bufferSz.U
io.out.bits.flit := io.in.bits.flit
io.in.ready := io.out.ready && credits < bufferSz.U
io.credit.ready := true.B
}
class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Decoupled(new Flit(flitWidth))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = buffer.io.deq.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credit_incr + Mux(credit_decr, 0.U, credits)
}
buffer.io.enq.valid := io.in.valid
buffer.io.enq.bits := io.in.bits
io.in.ready := true.B
when (io.in.valid) { assert(buffer.io.enq.ready) }
io.out <> buffer.io.deq
io.credit.valid := credits =/= 0.U
io.credit.bits.flit := credits - 1.U
} | module GenericDeserializer_TLBeatw67_f32_TestHarness_UNIQUIFIED(
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits_flit,
input io_out_ready,
output io_out_valid,
output [64:0] io_out_bits_payload,
output io_out_bits_head,
output io_out_bits_tail
);
reg [31:0] data_0;
reg [31:0] data_1;
reg [1:0] beat;
wire io_in_ready_0 = io_out_ready | beat != 2'h2;
wire _beat_T = beat == 2'h2;
wire _GEN = io_in_ready_0 & io_in_valid;
wire _GEN_0 = beat == 2'h2;
always @(posedge clock) begin
if (~_GEN | _GEN_0 | beat[0]) begin
end
else
data_0 <= io_in_bits_flit;
if (~_GEN | _GEN_0 | ~(beat[0])) begin
end
else
data_1 <= io_in_bits_flit;
if (reset)
beat <= 2'h0;
else if (_GEN)
beat <= _beat_T ? 2'h0 : beat + 2'h1;
end
assign io_in_ready = io_in_ready_0;
assign io_out_valid = io_in_valid & _beat_T;
assign io_out_bits_payload = {io_in_bits_flit[2:0], data_1, data_0[31:2]};
assign io_out_bits_head = data_0[1];
assign io_out_bits_tail = data_0[0];
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
} | module MulAddRecFNToRaw_postMul_e5_s11(
input io_fromPreMul_isSigNaNAny,
input io_fromPreMul_isNaNAOrB,
input io_fromPreMul_isInfA,
input io_fromPreMul_isZeroA,
input io_fromPreMul_isInfB,
input io_fromPreMul_isZeroB,
input io_fromPreMul_signProd,
input io_fromPreMul_isNaNC,
input io_fromPreMul_isInfC,
input io_fromPreMul_isZeroC,
input [6:0] io_fromPreMul_sExpSum,
input io_fromPreMul_doSubMags,
input io_fromPreMul_CIsDominant,
input [3:0] io_fromPreMul_CDom_CAlignDist,
input [12:0] io_fromPreMul_highAlignedSigC,
input io_fromPreMul_bit0AlignedSigC,
input [22:0] io_mulAddResult,
input [2:0] io_roundingMode,
output io_invalidExc,
output io_rawOut_isNaN,
output io_rawOut_isInf,
output io_rawOut_isZero,
output io_rawOut_sign,
output [6:0] io_rawOut_sExp,
output [13:0] io_rawOut_sig
);
wire roundingMode_min = io_roundingMode == 3'h2;
wire opSignC = io_fromPreMul_signProd ^ io_fromPreMul_doSubMags;
wire [12:0] _sigSum_T_3 = io_mulAddResult[22] ? io_fromPreMul_highAlignedSigC + 13'h1 : io_fromPreMul_highAlignedSigC;
wire [23:0] CDom_absSigSum = io_fromPreMul_doSubMags ? ~{_sigSum_T_3, io_mulAddResult[21:11]} : {1'h0, io_fromPreMul_highAlignedSigC[12:11], _sigSum_T_3[10:0], io_mulAddResult[21:12]};
wire [38:0] _CDom_mainSig_T = {15'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist;
wire [4:0] CDom_reduced4SigExtra_shift = $signed(5'sh10 >>> ~(io_fromPreMul_CDom_CAlignDist[3:2]));
wire [24:0] notCDom_absSigSum = _sigSum_T_3[2] ? ~{_sigSum_T_3[1:0], io_mulAddResult[21:0], io_fromPreMul_bit0AlignedSigC} : {_sigSum_T_3[1:0], io_mulAddResult[21:0], io_fromPreMul_bit0AlignedSigC} + {24'h0, io_fromPreMul_doSubMags};
wire [3:0] notCDom_normDistReduced2 = notCDom_absSigSum[24] ? 4'h0 : (|(notCDom_absSigSum[23:22])) ? 4'h1 : (|(notCDom_absSigSum[21:20])) ? 4'h2 : (|(notCDom_absSigSum[19:18])) ? 4'h3 : (|(notCDom_absSigSum[17:16])) ? 4'h4 : (|(notCDom_absSigSum[15:14])) ? 4'h5 : (|(notCDom_absSigSum[13:12])) ? 4'h6 : (|(notCDom_absSigSum[11:10])) ? 4'h7 : (|(notCDom_absSigSum[9:8])) ? 4'h8 : (|(notCDom_absSigSum[7:6])) ? 4'h9 : (|(notCDom_absSigSum[5:4])) ? 4'hA : (|(notCDom_absSigSum[3:2])) ? 4'hB : 4'hC;
wire [55:0] _notCDom_mainSig_T = {31'h0, notCDom_absSigSum} << {51'h0, notCDom_normDistReduced2, 1'h0};
wire [8:0] notCDom_reduced4SigExtra_shift = $signed(9'sh100 >>> ~(notCDom_normDistReduced2[3:1]));
wire notCDom_completeCancellation = _notCDom_mainSig_T[25:24] == 2'h0;
wire notNaN_isInfProd = io_fromPreMul_isInfA | io_fromPreMul_isInfB;
wire notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC;
wire notNaN_addZeros = (io_fromPreMul_isZeroA | io_fromPreMul_isZeroB) & io_fromPreMul_isZeroC;
assign io_invalidExc = io_fromPreMul_isSigNaNAny | io_fromPreMul_isInfA & io_fromPreMul_isZeroB | io_fromPreMul_isZeroA & io_fromPreMul_isInfB | ~io_fromPreMul_isNaNAOrB & notNaN_isInfProd & io_fromPreMul_isInfC & io_fromPreMul_doSubMags;
assign io_rawOut_isNaN = io_fromPreMul_isNaNAOrB | io_fromPreMul_isNaNC;
assign io_rawOut_isInf = notNaN_isInfOut;
assign io_rawOut_isZero = notNaN_addZeros | ~io_fromPreMul_CIsDominant & notCDom_completeCancellation;
assign io_rawOut_sign = notNaN_isInfProd & io_fromPreMul_signProd | io_fromPreMul_isInfC & opSignC | notNaN_addZeros & io_roundingMode != 3'h2 & io_fromPreMul_signProd & opSignC | notNaN_addZeros & roundingMode_min & (io_fromPreMul_signProd | opSignC) | ~notNaN_isInfOut & ~notNaN_addZeros & (io_fromPreMul_CIsDominant ? opSignC : notCDom_completeCancellation ? roundingMode_min : io_fromPreMul_signProd ^ _sigSum_T_3[2]);
assign io_rawOut_sExp = io_fromPreMul_CIsDominant ? io_fromPreMul_sExpSum - {6'h0, io_fromPreMul_doSubMags} : io_fromPreMul_sExpSum - {2'h0, notCDom_normDistReduced2, 1'h0};
assign io_rawOut_sig = io_fromPreMul_CIsDominant ? {_CDom_mainSig_T[23:11], (|{_CDom_mainSig_T[10:8], {|(CDom_absSigSum[7:4]), |(CDom_absSigSum[3:0])} & {CDom_reduced4SigExtra_shift[1], CDom_reduced4SigExtra_shift[2]}}) | (io_fromPreMul_doSubMags ? io_mulAddResult[10:0] != 11'h7FF : (|(io_mulAddResult[11:0])))} : {_notCDom_mainSig_T[25:13], |{_notCDom_mainSig_T[12:10], {|{|(notCDom_absSigSum[9:8]), |(notCDom_absSigSum[7:6])}, |{|(notCDom_absSigSum[5:4]), |(notCDom_absSigSum[3:2])}, |(notCDom_absSigSum[1:0])} & {notCDom_reduced4SigExtra_shift[1], notCDom_reduced4SigExtra_shift[2], notCDom_reduced4SigExtra_shift[3]}}};
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
} | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11(
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [6:0] io_in_sExp,
input [13:0] io_in_sig,
input [2:0] io_roundingMode,
output [16:0] io_out,
output [4:0] io_exceptionFlags
);
wire roundingMode_near_even = io_roundingMode == 3'h0;
wire roundingMode_odd = io_roundingMode == 3'h6;
wire roundMagUp = io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign;
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> ~(io_in_sExp[5:0]));
wire _common_underflow_T_4 = roundMask_shift[18] | io_in_sig[13];
wire [12:0] _GEN = {1'h1, ~(roundMask_shift[7]), ~(roundMask_shift[8]), ~(roundMask_shift[9]), ~(roundMask_shift[10]), ~(roundMask_shift[11]), ~(roundMask_shift[12]), ~(roundMask_shift[13]), ~(roundMask_shift[14]), ~(roundMask_shift[15]), ~(roundMask_shift[16]), ~(roundMask_shift[17]), ~_common_underflow_T_4};
wire [12:0] _GEN_0 = {roundMask_shift[7], roundMask_shift[8], roundMask_shift[9], roundMask_shift[10], roundMask_shift[11], roundMask_shift[12], roundMask_shift[13], roundMask_shift[14], roundMask_shift[15], roundMask_shift[16], roundMask_shift[17], _common_underflow_T_4, 1'h1};
wire [12:0] _roundPosBit_T = io_in_sig[13:1] & _GEN & _GEN_0;
wire [12:0] _anyRoundExtra_T = io_in_sig[12:0] & _GEN_0;
wire [25:0] _GEN_1 = {_roundPosBit_T, _anyRoundExtra_T};
wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4;
wire [12:0] roundedSig = _overflow_roundMagUp_T & (|_roundPosBit_T) | roundMagUp & (|_GEN_1) ? {1'h0, io_in_sig[13:2] | {roundMask_shift[7], roundMask_shift[8], roundMask_shift[9], roundMask_shift[10], roundMask_shift[11], roundMask_shift[12], roundMask_shift[13], roundMask_shift[14], roundMask_shift[15], roundMask_shift[16], roundMask_shift[17], _common_underflow_T_4}} + 13'h1 & ~(roundingMode_near_even & (|_roundPosBit_T) & _anyRoundExtra_T == 13'h0 ? {roundMask_shift[7], roundMask_shift[8], roundMask_shift[9], roundMask_shift[10], roundMask_shift[11], roundMask_shift[12], roundMask_shift[13], roundMask_shift[14], roundMask_shift[15], roundMask_shift[16], roundMask_shift[17], _common_underflow_T_4, 1'h1} : 13'h0) : {1'h0, io_in_sig[13:2] & {~(roundMask_shift[7]), ~(roundMask_shift[8]), ~(roundMask_shift[9]), ~(roundMask_shift[10]), ~(roundMask_shift[11]), ~(roundMask_shift[12]), ~(roundMask_shift[13]), ~(roundMask_shift[14]), ~(roundMask_shift[15]), ~(roundMask_shift[16]), ~(roundMask_shift[17]), ~_common_underflow_T_4}} | (roundingMode_odd & (|_GEN_1) ? _GEN & _GEN_0 : 13'h0);
wire [7:0] sRoundedExp = {io_in_sExp[6], io_in_sExp} + {6'h0, roundedSig[12:11]};
wire common_totalUnderflow = $signed(sRoundedExp) < 8'sh8;
wire isNaNOut = io_invalidExc | io_in_isNaN;
wire notNaN_isSpecialInfOut = io_infiniteExc | io_in_isInf;
wire commonCase = ~isNaNOut & ~notNaN_isSpecialInfOut & ~io_in_isZero;
wire overflow = commonCase & $signed(sRoundedExp[7:4]) > 4'sh2;
wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp;
wire pegMinNonzeroMagOut = commonCase & common_totalUnderflow & (roundMagUp | roundingMode_odd);
wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp;
wire notNaN_isInfOut = notNaN_isSpecialInfOut | overflow & overflow_roundMagUp;
assign io_out = {~isNaNOut & io_in_sign, sRoundedExp[5:0] & ~(io_in_isZero | common_totalUnderflow ? 6'h38 : 6'h0) & ~(pegMinNonzeroMagOut ? 6'h37 : 6'h0) & {1'h1, ~pegMaxFiniteMagOut, 4'hF} & {2'h3, ~notNaN_isInfOut, 3'h7} | {2'h0, pegMinNonzeroMagOut, 3'h0} | (pegMaxFiniteMagOut ? 6'h2F : 6'h0) | (notNaN_isInfOut ? 6'h30 : 6'h0) | (isNaNOut ? 6'h38 : 6'h0), (isNaNOut | io_in_isZero | common_totalUnderflow ? {isNaNOut, 9'h0} : io_in_sig[13] ? roundedSig[10:1] : roundedSig[9:0]) | {10{pegMaxFiniteMagOut}}};
assign io_exceptionFlags = {io_invalidExc, io_infiniteExc, overflow, commonCase & (common_totalUnderflow | (|_GEN_1) & io_in_sExp[6:5] != 2'h1 & (io_in_sig[13] ? roundMask_shift[17] : _common_underflow_T_4) & ~(~(io_in_sig[13] ? roundMask_shift[16] : roundMask_shift[17]) & (io_in_sig[13] ? roundedSig[12] : roundedSig[11]) & (|_roundPosBit_T) & (_overflow_roundMagUp_T & (io_in_sig[13] ? io_in_sig[2] : io_in_sig[1]) | roundMagUp & (|{io_in_sig[13] & io_in_sig[2], io_in_sig[1:0]})))), overflow | commonCase & (|{common_totalUnderflow, _roundPosBit_T, _anyRoundExtra_T})};
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Execution Units
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// The issue window schedules micro-ops onto a specific execution pipeline
// A given execution pipeline may contain multiple functional units; one or more
// read ports, and one or more writeports.
package boom.v3.exu
import scala.collection.mutable.{ArrayBuffer}
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.rocket.{BP}
import freechips.rocketchip.tile
import FUConstants._
import boom.v3.common._
import boom.v3.ifu.{GetPCFromFtqIO}
import boom.v3.util.{ImmGen, IsKilledByBranch, BranchKillableQueue, BoomCoreStringPrefix}
/**
* Response from Execution Unit. Bundles a MicroOp with data
*
* @param dataWidth width of the data coming from the execution unit
*/
class ExeUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
with HasBoomUOP
{
val data = Bits(dataWidth.W)
val predicated = Bool() // Was this predicated off?
val fflags = new ValidIO(new FFlagsResp) // write fflags to ROB // TODO: Do this better
}
/**
* Floating Point flag response
*/
class FFlagsResp(implicit p: Parameters) extends BoomBundle
{
val uop = new MicroOp()
val flags = Bits(tile.FPConstants.FLAGS_SZ.W)
}
/**
* Abstract Top level Execution Unit that wraps lower level functional units to make a
* multi function execution unit.
*
* @param readsIrf does this exe unit need a integer regfile port
* @param writesIrf does this exe unit need a integer regfile port
* @param readsFrf does this exe unit need a integer regfile port
* @param writesFrf does this exe unit need a integer regfile port
* @param writesLlIrf does this exe unit need a integer regfile port
* @param writesLlFrf does this exe unit need a integer regfile port
* @param numBypassStages number of bypass ports for the exe unit
* @param dataWidth width of the data coming out of the exe unit
* @param bypassable is the exe unit able to be bypassed
* @param hasMem does the exe unit have a MemAddrCalcUnit
* @param hasCSR does the exe unit write to the CSRFile
* @param hasBrUnit does the exe unit have a branch unit
* @param hasAlu does the exe unit have a alu
* @param hasFpu does the exe unit have a fpu
* @param hasMul does the exe unit have a multiplier
* @param hasDiv does the exe unit have a divider
* @param hasFdiv does the exe unit have a FP divider
* @param hasIfpu does the exe unit have a int to FP unit
* @param hasFpiu does the exe unit have a FP to int unit
*/
abstract class ExecutionUnit(
val readsIrf : Boolean = false,
val writesIrf : Boolean = false,
val readsFrf : Boolean = false,
val writesFrf : Boolean = false,
val writesLlIrf : Boolean = false,
val writesLlFrf : Boolean = false,
val numBypassStages : Int,
val dataWidth : Int,
val bypassable : Boolean = false, // TODO make override def for code clarity
val alwaysBypassable : Boolean = false,
val hasMem : Boolean = false,
val hasCSR : Boolean = false,
val hasJmpUnit : Boolean = false,
val hasAlu : Boolean = false,
val hasFpu : Boolean = false,
val hasMul : Boolean = false,
val hasDiv : Boolean = false,
val hasFdiv : Boolean = false,
val hasIfpu : Boolean = false,
val hasFpiu : Boolean = false,
val hasRocc : Boolean = false
)(implicit p: Parameters) extends BoomModule
{
val io = IO(new Bundle {
val fu_types = Output(Bits(FUC_SZ.W))
val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth)))
val iresp = if (writesIrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null
val fresp = if (writesFrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null
val ll_iresp = if (writesLlIrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null
val ll_fresp = if (writesLlFrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null
val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth))))
val brupdate = Input(new BrUpdateInfo())
// only used by the rocc unit
val rocc = if (hasRocc) new RoCCShimCoreIO else null
// only used by the branch unit
val brinfo = if (hasAlu) Output(new BrResolutionInfo()) else null
val get_ftq_pc = if (hasJmpUnit) Flipped(new GetPCFromFtqIO()) else null
val status = Input(new freechips.rocketchip.rocket.MStatus())
// only used by the fpu unit
val fcsr_rm = if (hasFcsr) Input(Bits(tile.FPConstants.RM_SZ.W)) else null
// only used by the mem unit
val lsu_io = if (hasMem) Flipped(new boom.v3.lsu.LSUExeIO) else null
val bp = if (hasMem) Input(Vec(nBreakpoints, new BP)) else null
val mcontext = if (hasMem) Input(UInt(coreParams.mcontextWidth.W)) else null
val scontext = if (hasMem) Input(UInt(coreParams.scontextWidth.W)) else null
// TODO move this out of ExecutionUnit
val com_exception = if (hasMem || hasRocc) Input(Bool()) else null
})
io.req.ready := false.B
if (writesIrf) {
io.iresp.valid := false.B
io.iresp.bits := DontCare
io.iresp.bits.fflags.valid := false.B
io.iresp.bits.predicated := false.B
assert(io.iresp.ready)
}
if (writesLlIrf) {
io.ll_iresp.valid := false.B
io.ll_iresp.bits := DontCare
io.ll_iresp.bits.fflags.valid := false.B
io.ll_iresp.bits.predicated := false.B
}
if (writesFrf) {
io.fresp.valid := false.B
io.fresp.bits := DontCare
io.fresp.bits.fflags.valid := false.B
io.fresp.bits.predicated := false.B
assert(io.fresp.ready)
}
if (writesLlFrf) {
io.ll_fresp.valid := false.B
io.ll_fresp.bits := DontCare
io.ll_fresp.bits.fflags.valid := false.B
io.ll_fresp.bits.predicated := false.B
}
// TODO add "number of fflag ports", so we can properly account for FPU+Mem combinations
def hasFFlags : Boolean = hasFpu || hasFdiv
require ((hasFpu || hasFdiv) ^ (hasAlu || hasMul || hasMem || hasIfpu),
"[execute] we no longer support mixing FP and Integer functional units in the same exe unit.")
def hasFcsr = hasIfpu || hasFpu || hasFdiv
require (bypassable || !alwaysBypassable,
"[execute] an execution unit must be bypassable if it is always bypassable")
def supportedFuncUnits = {
new SupportedFuncUnits(
alu = hasAlu,
jmp = hasJmpUnit,
mem = hasMem,
muld = hasMul || hasDiv,
fpu = hasFpu,
csr = hasCSR,
fdiv = hasFdiv,
ifpu = hasIfpu)
}
}
/**
* ALU execution unit that can have a branch, alu, mul, div, int to FP,
* and memory unit.
*
* @param hasBrUnit does the exe unit have a branch unit
* @param hasCSR does the exe unit write to the CSRFile
* @param hasAlu does the exe unit have a alu
* @param hasMul does the exe unit have a multiplier
* @param hasDiv does the exe unit have a divider
* @param hasIfpu does the exe unit have a int to FP unit
* @param hasMem does the exe unit have a MemAddrCalcUnit
*/
class ALUExeUnit(
hasJmpUnit : Boolean = false,
hasCSR : Boolean = false,
hasAlu : Boolean = true,
hasMul : Boolean = false,
hasDiv : Boolean = false,
hasIfpu : Boolean = false,
hasMem : Boolean = false,
hasRocc : Boolean = false)
(implicit p: Parameters)
extends ExecutionUnit(
readsIrf = true,
writesIrf = hasAlu || hasMul || hasDiv,
writesLlIrf = hasMem || hasRocc,
writesLlFrf = (hasIfpu || hasMem) && p(tile.TileKey).core.fpu != None,
numBypassStages =
if (hasAlu && hasMul) 3 //TODO XXX p(tile.TileKey).core.imulLatency
else if (hasAlu) 1 else 0,
dataWidth = 64 + 1,
bypassable = hasAlu,
alwaysBypassable = hasAlu && !(hasMem || hasJmpUnit || hasMul || hasDiv || hasCSR || hasIfpu || hasRocc),
hasCSR = hasCSR,
hasJmpUnit = hasJmpUnit,
hasAlu = hasAlu,
hasMul = hasMul,
hasDiv = hasDiv,
hasIfpu = hasIfpu,
hasMem = hasMem,
hasRocc = hasRocc)
with freechips.rocketchip.rocket.constants.MemoryOpConstants
{
require(!(hasRocc && !hasCSR),
"RoCC needs to be shared with CSR unit")
require(!(hasMem && hasRocc),
"We do not support execution unit with both Mem and Rocc writebacks")
require(!(hasMem && hasIfpu),
"TODO. Currently do not support AluMemExeUnit with FP")
val out_str =
BoomCoreStringPrefix("==ExeUnit==") +
(if (hasAlu) BoomCoreStringPrefix(" - ALU") else "") +
(if (hasMul) BoomCoreStringPrefix(" - Mul") else "") +
(if (hasDiv) BoomCoreStringPrefix(" - Div") else "") +
(if (hasIfpu) BoomCoreStringPrefix(" - IFPU") else "") +
(if (hasMem) BoomCoreStringPrefix(" - Mem") else "") +
(if (hasRocc) BoomCoreStringPrefix(" - RoCC") else "")
override def toString: String = out_str.toString
val div_busy = WireInit(false.B)
val ifpu_busy = WireInit(false.B)
// The Functional Units --------------------
// Specifically the functional units with fast writeback to IRF
val iresp_fu_units = ArrayBuffer[FunctionalUnit]()
io.fu_types := Mux(hasAlu.B, FU_ALU, 0.U) |
Mux(hasMul.B, FU_MUL, 0.U) |
Mux(!div_busy && hasDiv.B, FU_DIV, 0.U) |
Mux(hasCSR.B, FU_CSR, 0.U) |
Mux(hasJmpUnit.B, FU_JMP, 0.U) |
Mux(!ifpu_busy && hasIfpu.B, FU_I2F, 0.U) |
Mux(hasMem.B, FU_MEM, 0.U)
// ALU Unit -------------------------------
var alu: ALUUnit = null
if (hasAlu) {
alu = Module(new ALUUnit(isJmpUnit = hasJmpUnit,
numStages = numBypassStages,
dataWidth = xLen))
alu.io.req.valid := (
io.req.valid &&
(io.req.bits.uop.fu_code === FU_ALU ||
io.req.bits.uop.fu_code === FU_JMP ||
(io.req.bits.uop.fu_code === FU_CSR && io.req.bits.uop.uopc =/= uopROCC)))
//ROCC Rocc Commands are taken by the RoCC unit
alu.io.req.bits.uop := io.req.bits.uop
alu.io.req.bits.kill := io.req.bits.kill
alu.io.req.bits.rs1_data := io.req.bits.rs1_data
alu.io.req.bits.rs2_data := io.req.bits.rs2_data
alu.io.req.bits.rs3_data := DontCare
alu.io.req.bits.pred_data := io.req.bits.pred_data
alu.io.resp.ready := DontCare
alu.io.brupdate := io.brupdate
iresp_fu_units += alu
// Bypassing only applies to ALU
io.bypass := alu.io.bypass
// branch unit is embedded inside the ALU
io.brinfo := alu.io.brinfo
if (hasJmpUnit) {
alu.io.get_ftq_pc <> io.get_ftq_pc
}
}
var rocc: RoCCShim = null
if (hasRocc) {
rocc = Module(new RoCCShim)
rocc.io.req.valid := io.req.valid && io.req.bits.uop.uopc === uopROCC
rocc.io.req.bits := DontCare
rocc.io.req.bits.uop := io.req.bits.uop
rocc.io.req.bits.kill := io.req.bits.kill
rocc.io.req.bits.rs1_data := io.req.bits.rs1_data
rocc.io.req.bits.rs2_data := io.req.bits.rs2_data
rocc.io.brupdate := io.brupdate // We should assert on this somewhere
rocc.io.status := io.status
rocc.io.exception := io.com_exception
io.rocc <> rocc.io.core
rocc.io.resp.ready := io.ll_iresp.ready
io.ll_iresp.valid := rocc.io.resp.valid
io.ll_iresp.bits.uop := rocc.io.resp.bits.uop
io.ll_iresp.bits.data := rocc.io.resp.bits.data
}
// Pipelined, IMul Unit ------------------
var imul: PipelinedMulUnit = null
if (hasMul) {
imul = Module(new PipelinedMulUnit(imulLatency, xLen))
imul.io <> DontCare
imul.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_MUL)
imul.io.req.bits.uop := io.req.bits.uop
imul.io.req.bits.rs1_data := io.req.bits.rs1_data
imul.io.req.bits.rs2_data := io.req.bits.rs2_data
imul.io.req.bits.kill := io.req.bits.kill
imul.io.brupdate := io.brupdate
iresp_fu_units += imul
}
var ifpu: IntToFPUnit = null
if (hasIfpu) {
ifpu = Module(new IntToFPUnit(latency=intToFpLatency))
ifpu.io.req <> io.req
ifpu.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_I2F)
ifpu.io.fcsr_rm := io.fcsr_rm
ifpu.io.brupdate <> io.brupdate
ifpu.io.resp.ready := DontCare
// buffer up results since we share write-port on integer regfile.
val queue = Module(new BranchKillableQueue(new ExeUnitResp(dataWidth),
entries = intToFpLatency + 3)) // TODO being overly conservative
queue.io.enq.valid := ifpu.io.resp.valid
queue.io.enq.bits.uop := ifpu.io.resp.bits.uop
queue.io.enq.bits.data := ifpu.io.resp.bits.data
queue.io.enq.bits.predicated := ifpu.io.resp.bits.predicated
queue.io.enq.bits.fflags := ifpu.io.resp.bits.fflags
queue.io.brupdate := io.brupdate
queue.io.flush := io.req.bits.kill
io.ll_fresp <> queue.io.deq
ifpu_busy := !(queue.io.empty)
assert (queue.io.enq.ready)
}
// Div/Rem Unit -----------------------
var div: DivUnit = null
val div_resp_val = WireInit(false.B)
if (hasDiv) {
div = Module(new DivUnit(xLen))
div.io <> DontCare
div.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_DIV) && hasDiv.B
div.io.req.bits.uop := io.req.bits.uop
div.io.req.bits.rs1_data := io.req.bits.rs1_data
div.io.req.bits.rs2_data := io.req.bits.rs2_data
div.io.brupdate := io.brupdate
div.io.req.bits.kill := io.req.bits.kill
// share write port with the pipelined units
div.io.resp.ready := !(iresp_fu_units.map(_.io.resp.valid).reduce(_|_))
div_resp_val := div.io.resp.valid
div_busy := !div.io.req.ready ||
(io.req.valid && io.req.bits.uop.fu_code_is(FU_DIV))
iresp_fu_units += div
}
// Mem Unit --------------------------
if (hasMem) {
require(!hasAlu)
val maddrcalc = Module(new MemAddrCalcUnit)
maddrcalc.io.req <> io.req
maddrcalc.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_MEM)
maddrcalc.io.brupdate <> io.brupdate
maddrcalc.io.status := io.status
maddrcalc.io.bp := io.bp
maddrcalc.io.mcontext := io.mcontext
maddrcalc.io.scontext := io.scontext
maddrcalc.io.resp.ready := DontCare
require(numBypassStages == 0)
io.lsu_io.req := maddrcalc.io.resp
io.ll_iresp <> io.lsu_io.iresp
if (usingFPU) {
io.ll_fresp <> io.lsu_io.fresp
}
}
// Outputs (Write Port #0) ---------------
if (writesIrf) {
io.iresp.valid := iresp_fu_units.map(_.io.resp.valid).reduce(_|_)
io.iresp.bits.uop := PriorityMux(iresp_fu_units.map(f =>
(f.io.resp.valid, f.io.resp.bits.uop)).toSeq)
io.iresp.bits.data := PriorityMux(iresp_fu_units.map(f =>
(f.io.resp.valid, f.io.resp.bits.data)).toSeq)
io.iresp.bits.predicated := PriorityMux(iresp_fu_units.map(f =>
(f.io.resp.valid, f.io.resp.bits.predicated)).toSeq)
// pulled out for critical path reasons
// TODO: Does this make sense as part of the iresp bundle?
if (hasAlu) {
io.iresp.bits.uop.csr_addr := ImmGen(alu.io.resp.bits.uop.imm_packed, IS_I).asUInt
io.iresp.bits.uop.ctrl.csr_cmd := alu.io.resp.bits.uop.ctrl.csr_cmd
}
}
assert ((PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 1.U && !div_resp_val) ||
(PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 2.U && (div_resp_val)),
"Multiple functional units are fighting over the write port.")
}
/**
* FPU-only unit, with optional second write-port for ToInt micro-ops.
*
* @param hasFpu does the exe unit have a fpu
* @param hasFdiv does the exe unit have a FP divider
* @param hasFpiu does the exe unit have a FP to int unit
*/
class FPUExeUnit(
hasFpu : Boolean = true,
hasFdiv : Boolean = false,
hasFpiu : Boolean = false
)
(implicit p: Parameters)
extends ExecutionUnit(
readsFrf = true,
writesFrf = true,
writesLlIrf = hasFpiu,
writesIrf = false,
numBypassStages = 0,
dataWidth = p(tile.TileKey).core.fpu.get.fLen + 1,
bypassable = false,
hasFpu = hasFpu,
hasFdiv = hasFdiv,
hasFpiu = hasFpiu) with tile.HasFPUParameters
{
val out_str =
BoomCoreStringPrefix("==ExeUnit==")
(if (hasFpu) BoomCoreStringPrefix("- FPU (Latency: " + dfmaLatency + ")") else "") +
(if (hasFdiv) BoomCoreStringPrefix("- FDiv/FSqrt") else "") +
(if (hasFpiu) BoomCoreStringPrefix("- FPIU (writes to Integer RF)") else "")
val fdiv_busy = WireInit(false.B)
val fpiu_busy = WireInit(false.B)
// The Functional Units --------------------
val fu_units = ArrayBuffer[FunctionalUnit]()
io.fu_types := Mux(hasFpu.B, FU_FPU, 0.U) |
Mux(!fdiv_busy && hasFdiv.B, FU_FDV, 0.U) |
Mux(!fpiu_busy && hasFpiu.B, FU_F2I, 0.U)
// FPU Unit -----------------------
var fpu: FPUUnit = null
val fpu_resp_val = WireInit(false.B)
val fpu_resp_fflags = Wire(new ValidIO(new FFlagsResp()))
fpu_resp_fflags.valid := false.B
if (hasFpu) {
fpu = Module(new FPUUnit())
fpu.io.req.valid := io.req.valid &&
(io.req.bits.uop.fu_code_is(FU_FPU) ||
io.req.bits.uop.fu_code_is(FU_F2I)) // TODO move to using a separate unit
fpu.io.req.bits.uop := io.req.bits.uop
fpu.io.req.bits.rs1_data := io.req.bits.rs1_data
fpu.io.req.bits.rs2_data := io.req.bits.rs2_data
fpu.io.req.bits.rs3_data := io.req.bits.rs3_data
fpu.io.req.bits.pred_data := false.B
fpu.io.req.bits.kill := io.req.bits.kill
fpu.io.fcsr_rm := io.fcsr_rm
fpu.io.brupdate := io.brupdate
fpu.io.resp.ready := DontCare
fpu_resp_val := fpu.io.resp.valid
fpu_resp_fflags := fpu.io.resp.bits.fflags
fu_units += fpu
}
// FDiv/FSqrt Unit -----------------------
var fdivsqrt: FDivSqrtUnit = null
val fdiv_resp_fflags = Wire(new ValidIO(new FFlagsResp()))
fdiv_resp_fflags := DontCare
fdiv_resp_fflags.valid := false.B
if (hasFdiv) {
fdivsqrt = Module(new FDivSqrtUnit())
fdivsqrt.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_FDV)
fdivsqrt.io.req.bits.uop := io.req.bits.uop
fdivsqrt.io.req.bits.rs1_data := io.req.bits.rs1_data
fdivsqrt.io.req.bits.rs2_data := io.req.bits.rs2_data
fdivsqrt.io.req.bits.rs3_data := DontCare
fdivsqrt.io.req.bits.pred_data := false.B
fdivsqrt.io.req.bits.kill := io.req.bits.kill
fdivsqrt.io.fcsr_rm := io.fcsr_rm
fdivsqrt.io.brupdate := io.brupdate
// share write port with the pipelined units
fdivsqrt.io.resp.ready := !(fu_units.map(_.io.resp.valid).reduce(_|_)) // TODO PERF will get blocked by fpiu.
fdiv_busy := !fdivsqrt.io.req.ready || (io.req.valid && io.req.bits.uop.fu_code_is(FU_FDV))
fdiv_resp_fflags := fdivsqrt.io.resp.bits.fflags
fu_units += fdivsqrt
}
// Outputs (Write Port #0) ---------------
io.fresp.valid := fu_units.map(_.io.resp.valid).reduce(_|_) &&
!(fpu.io.resp.valid && fpu.io.resp.bits.uop.fu_code_is(FU_F2I))
io.fresp.bits.uop := PriorityMux(fu_units.map(f => (f.io.resp.valid,
f.io.resp.bits.uop)).toSeq)
io.fresp.bits.data:= PriorityMux(fu_units.map(f => (f.io.resp.valid, f.io.resp.bits.data)).toSeq)
io.fresp.bits.fflags := Mux(fpu_resp_val, fpu_resp_fflags, fdiv_resp_fflags)
// Outputs (Write Port #1) -- FpToInt Queuing Unit -----------------------
if (hasFpiu) {
// TODO instantiate our own fpiu; and remove it from fpu.scala.
// buffer up results since we share write-port on integer regfile.
val queue = Module(new BranchKillableQueue(new ExeUnitResp(dataWidth),
entries = dfmaLatency + 3)) // TODO being overly conservative
queue.io.enq.valid := (fpu.io.resp.valid &&
fpu.io.resp.bits.uop.fu_code_is(FU_F2I) &&
fpu.io.resp.bits.uop.uopc =/= uopSTA) // STA means store data gen for floating point
queue.io.enq.bits.uop := fpu.io.resp.bits.uop
queue.io.enq.bits.data := fpu.io.resp.bits.data
queue.io.enq.bits.predicated := fpu.io.resp.bits.predicated
queue.io.enq.bits.fflags := fpu.io.resp.bits.fflags
queue.io.brupdate := io.brupdate
queue.io.flush := io.req.bits.kill
assert (queue.io.enq.ready) // If this backs up, we've miscalculated the size of the queue.
val fp_sdq = Module(new BranchKillableQueue(new ExeUnitResp(dataWidth),
entries = 3)) // Lets us backpressure floating point store data
fp_sdq.io.enq.valid := io.req.valid && io.req.bits.uop.uopc === uopSTA && !IsKilledByBranch(io.brupdate, io.req.bits.uop)
fp_sdq.io.enq.bits.uop := io.req.bits.uop
fp_sdq.io.enq.bits.data := ieee(io.req.bits.rs2_data)
fp_sdq.io.enq.bits.predicated := false.B
fp_sdq.io.enq.bits.fflags := DontCare
fp_sdq.io.brupdate := io.brupdate
fp_sdq.io.flush := io.req.bits.kill
assert(!(fp_sdq.io.enq.valid && !fp_sdq.io.enq.ready))
val resp_arb = Module(new Arbiter(new ExeUnitResp(dataWidth), 2))
resp_arb.io.in(0) <> queue.io.deq
resp_arb.io.in(1) <> fp_sdq.io.deq
io.ll_iresp <> resp_arb.io.out
fpiu_busy := !(queue.io.empty && fp_sdq.io.empty)
}
override def toString: String = out_str.toString
} | module ALUExeUnit(
input clock,
input reset,
input io_req_valid,
input [6:0] io_req_bits_uop_uopc,
input [31:0] io_req_bits_uop_inst,
input [31:0] io_req_bits_uop_debug_inst,
input io_req_bits_uop_is_rvc,
input [39:0] io_req_bits_uop_debug_pc,
input [2:0] io_req_bits_uop_iq_type,
input [9:0] io_req_bits_uop_fu_code,
input [3:0] io_req_bits_uop_ctrl_br_type,
input [1:0] io_req_bits_uop_ctrl_op1_sel,
input [2:0] io_req_bits_uop_ctrl_op2_sel,
input [2:0] io_req_bits_uop_ctrl_imm_sel,
input [4:0] io_req_bits_uop_ctrl_op_fcn,
input io_req_bits_uop_ctrl_fcn_dw,
input [2:0] io_req_bits_uop_ctrl_csr_cmd,
input io_req_bits_uop_ctrl_is_load,
input io_req_bits_uop_ctrl_is_sta,
input io_req_bits_uop_ctrl_is_std,
input [1:0] io_req_bits_uop_iw_state,
input io_req_bits_uop_is_br,
input io_req_bits_uop_is_jalr,
input io_req_bits_uop_is_jal,
input io_req_bits_uop_is_sfb,
input [7:0] io_req_bits_uop_br_mask,
input [2:0] io_req_bits_uop_br_tag,
input [3:0] io_req_bits_uop_ftq_idx,
input io_req_bits_uop_edge_inst,
input [5:0] io_req_bits_uop_pc_lob,
input io_req_bits_uop_taken,
input [19:0] io_req_bits_uop_imm_packed,
input [11:0] io_req_bits_uop_csr_addr,
input [4:0] io_req_bits_uop_rob_idx,
input [2:0] io_req_bits_uop_ldq_idx,
input [2:0] io_req_bits_uop_stq_idx,
input [1:0] io_req_bits_uop_rxq_idx,
input [5:0] io_req_bits_uop_pdst,
input [5:0] io_req_bits_uop_prs1,
input [5:0] io_req_bits_uop_prs2,
input [5:0] io_req_bits_uop_prs3,
input [3:0] io_req_bits_uop_ppred,
input io_req_bits_uop_prs1_busy,
input io_req_bits_uop_prs2_busy,
input io_req_bits_uop_prs3_busy,
input io_req_bits_uop_ppred_busy,
input [5:0] io_req_bits_uop_stale_pdst,
input io_req_bits_uop_exception,
input [63:0] io_req_bits_uop_exc_cause,
input io_req_bits_uop_bypassable,
input [4:0] io_req_bits_uop_mem_cmd,
input [1:0] io_req_bits_uop_mem_size,
input io_req_bits_uop_mem_signed,
input io_req_bits_uop_is_fence,
input io_req_bits_uop_is_fencei,
input io_req_bits_uop_is_amo,
input io_req_bits_uop_uses_ldq,
input io_req_bits_uop_uses_stq,
input io_req_bits_uop_is_sys_pc2epc,
input io_req_bits_uop_is_unique,
input io_req_bits_uop_flush_on_commit,
input io_req_bits_uop_ldst_is_rs1,
input [5:0] io_req_bits_uop_ldst,
input [5:0] io_req_bits_uop_lrs1,
input [5:0] io_req_bits_uop_lrs2,
input [5:0] io_req_bits_uop_lrs3,
input io_req_bits_uop_ldst_val,
input [1:0] io_req_bits_uop_dst_rtype,
input [1:0] io_req_bits_uop_lrs1_rtype,
input [1:0] io_req_bits_uop_lrs2_rtype,
input io_req_bits_uop_frs3_en,
input io_req_bits_uop_fp_val,
input io_req_bits_uop_fp_single,
input io_req_bits_uop_xcpt_pf_if,
input io_req_bits_uop_xcpt_ae_if,
input io_req_bits_uop_xcpt_ma_if,
input io_req_bits_uop_bp_debug_if,
input io_req_bits_uop_bp_xcpt_if,
input [1:0] io_req_bits_uop_debug_fsrc,
input [1:0] io_req_bits_uop_debug_tsrc,
input [64:0] io_req_bits_rs1_data,
input [64:0] io_req_bits_rs2_data,
output io_ll_iresp_valid,
output [4:0] io_ll_iresp_bits_uop_rob_idx,
output [5:0] io_ll_iresp_bits_uop_pdst,
output io_ll_iresp_bits_uop_is_amo,
output io_ll_iresp_bits_uop_uses_stq,
output [1:0] io_ll_iresp_bits_uop_dst_rtype,
output [64:0] io_ll_iresp_bits_data,
output io_ll_fresp_valid,
output [6:0] io_ll_fresp_bits_uop_uopc,
output [7:0] io_ll_fresp_bits_uop_br_mask,
output [4:0] io_ll_fresp_bits_uop_rob_idx,
output [2:0] io_ll_fresp_bits_uop_stq_idx,
output [5:0] io_ll_fresp_bits_uop_pdst,
output [1:0] io_ll_fresp_bits_uop_mem_size,
output io_ll_fresp_bits_uop_is_amo,
output io_ll_fresp_bits_uop_uses_stq,
output [1:0] io_ll_fresp_bits_uop_dst_rtype,
output io_ll_fresp_bits_uop_fp_val,
output [64:0] io_ll_fresp_bits_data,
input [7:0] io_brupdate_b1_resolve_mask,
input [7:0] io_brupdate_b1_mispredict_mask,
output io_lsu_io_req_valid,
output [6:0] io_lsu_io_req_bits_uop_uopc,
output [31:0] io_lsu_io_req_bits_uop_inst,
output [31:0] io_lsu_io_req_bits_uop_debug_inst,
output io_lsu_io_req_bits_uop_is_rvc,
output [39:0] io_lsu_io_req_bits_uop_debug_pc,
output [2:0] io_lsu_io_req_bits_uop_iq_type,
output [9:0] io_lsu_io_req_bits_uop_fu_code,
output [3:0] io_lsu_io_req_bits_uop_ctrl_br_type,
output [1:0] io_lsu_io_req_bits_uop_ctrl_op1_sel,
output [2:0] io_lsu_io_req_bits_uop_ctrl_op2_sel,
output [2:0] io_lsu_io_req_bits_uop_ctrl_imm_sel,
output [4:0] io_lsu_io_req_bits_uop_ctrl_op_fcn,
output io_lsu_io_req_bits_uop_ctrl_fcn_dw,
output [2:0] io_lsu_io_req_bits_uop_ctrl_csr_cmd,
output io_lsu_io_req_bits_uop_ctrl_is_load,
output io_lsu_io_req_bits_uop_ctrl_is_sta,
output io_lsu_io_req_bits_uop_ctrl_is_std,
output [1:0] io_lsu_io_req_bits_uop_iw_state,
output io_lsu_io_req_bits_uop_is_br,
output io_lsu_io_req_bits_uop_is_jalr,
output io_lsu_io_req_bits_uop_is_jal,
output io_lsu_io_req_bits_uop_is_sfb,
output [7:0] io_lsu_io_req_bits_uop_br_mask,
output [2:0] io_lsu_io_req_bits_uop_br_tag,
output [3:0] io_lsu_io_req_bits_uop_ftq_idx,
output io_lsu_io_req_bits_uop_edge_inst,
output [5:0] io_lsu_io_req_bits_uop_pc_lob,
output io_lsu_io_req_bits_uop_taken,
output [19:0] io_lsu_io_req_bits_uop_imm_packed,
output [11:0] io_lsu_io_req_bits_uop_csr_addr,
output [4:0] io_lsu_io_req_bits_uop_rob_idx,
output [2:0] io_lsu_io_req_bits_uop_ldq_idx,
output [2:0] io_lsu_io_req_bits_uop_stq_idx,
output [1:0] io_lsu_io_req_bits_uop_rxq_idx,
output [5:0] io_lsu_io_req_bits_uop_pdst,
output [5:0] io_lsu_io_req_bits_uop_prs1,
output [5:0] io_lsu_io_req_bits_uop_prs2,
output [5:0] io_lsu_io_req_bits_uop_prs3,
output [3:0] io_lsu_io_req_bits_uop_ppred,
output io_lsu_io_req_bits_uop_prs1_busy,
output io_lsu_io_req_bits_uop_prs2_busy,
output io_lsu_io_req_bits_uop_prs3_busy,
output io_lsu_io_req_bits_uop_ppred_busy,
output [5:0] io_lsu_io_req_bits_uop_stale_pdst,
output io_lsu_io_req_bits_uop_exception,
output [63:0] io_lsu_io_req_bits_uop_exc_cause,
output io_lsu_io_req_bits_uop_bypassable,
output [4:0] io_lsu_io_req_bits_uop_mem_cmd,
output [1:0] io_lsu_io_req_bits_uop_mem_size,
output io_lsu_io_req_bits_uop_mem_signed,
output io_lsu_io_req_bits_uop_is_fence,
output io_lsu_io_req_bits_uop_is_fencei,
output io_lsu_io_req_bits_uop_is_amo,
output io_lsu_io_req_bits_uop_uses_ldq,
output io_lsu_io_req_bits_uop_uses_stq,
output io_lsu_io_req_bits_uop_is_sys_pc2epc,
output io_lsu_io_req_bits_uop_is_unique,
output io_lsu_io_req_bits_uop_flush_on_commit,
output io_lsu_io_req_bits_uop_ldst_is_rs1,
output [5:0] io_lsu_io_req_bits_uop_ldst,
output [5:0] io_lsu_io_req_bits_uop_lrs1,
output [5:0] io_lsu_io_req_bits_uop_lrs2,
output [5:0] io_lsu_io_req_bits_uop_lrs3,
output io_lsu_io_req_bits_uop_ldst_val,
output [1:0] io_lsu_io_req_bits_uop_dst_rtype,
output [1:0] io_lsu_io_req_bits_uop_lrs1_rtype,
output [1:0] io_lsu_io_req_bits_uop_lrs2_rtype,
output io_lsu_io_req_bits_uop_frs3_en,
output io_lsu_io_req_bits_uop_fp_val,
output io_lsu_io_req_bits_uop_fp_single,
output io_lsu_io_req_bits_uop_xcpt_pf_if,
output io_lsu_io_req_bits_uop_xcpt_ae_if,
output io_lsu_io_req_bits_uop_xcpt_ma_if,
output io_lsu_io_req_bits_uop_bp_debug_if,
output io_lsu_io_req_bits_uop_bp_xcpt_if,
output [1:0] io_lsu_io_req_bits_uop_debug_fsrc,
output [1:0] io_lsu_io_req_bits_uop_debug_tsrc,
output [63:0] io_lsu_io_req_bits_data,
output [39:0] io_lsu_io_req_bits_addr,
output io_lsu_io_req_bits_mxcpt_valid,
output io_lsu_io_req_bits_sfence_valid,
output io_lsu_io_req_bits_sfence_bits_rs1,
output io_lsu_io_req_bits_sfence_bits_rs2,
output [38:0] io_lsu_io_req_bits_sfence_bits_addr,
input io_lsu_io_iresp_valid,
input [4:0] io_lsu_io_iresp_bits_uop_rob_idx,
input [5:0] io_lsu_io_iresp_bits_uop_pdst,
input io_lsu_io_iresp_bits_uop_is_amo,
input io_lsu_io_iresp_bits_uop_uses_stq,
input [1:0] io_lsu_io_iresp_bits_uop_dst_rtype,
input [63:0] io_lsu_io_iresp_bits_data,
input io_lsu_io_fresp_valid,
input [6:0] io_lsu_io_fresp_bits_uop_uopc,
input [7:0] io_lsu_io_fresp_bits_uop_br_mask,
input [4:0] io_lsu_io_fresp_bits_uop_rob_idx,
input [2:0] io_lsu_io_fresp_bits_uop_stq_idx,
input [5:0] io_lsu_io_fresp_bits_uop_pdst,
input [1:0] io_lsu_io_fresp_bits_uop_mem_size,
input io_lsu_io_fresp_bits_uop_is_amo,
input io_lsu_io_fresp_bits_uop_uses_stq,
input [1:0] io_lsu_io_fresp_bits_uop_dst_rtype,
input io_lsu_io_fresp_bits_uop_fp_val,
input [64:0] io_lsu_io_fresp_bits_data
);
wire [64:0] _maddrcalc_io_resp_bits_data;
MemAddrCalcUnit maddrcalc (
.clock (clock),
.reset (reset),
.io_req_valid (io_req_valid & io_req_bits_uop_fu_code[2]),
.io_req_bits_uop_uopc (io_req_bits_uop_uopc),
.io_req_bits_uop_inst (io_req_bits_uop_inst),
.io_req_bits_uop_debug_inst (io_req_bits_uop_debug_inst),
.io_req_bits_uop_is_rvc (io_req_bits_uop_is_rvc),
.io_req_bits_uop_debug_pc (io_req_bits_uop_debug_pc),
.io_req_bits_uop_iq_type (io_req_bits_uop_iq_type),
.io_req_bits_uop_fu_code (io_req_bits_uop_fu_code),
.io_req_bits_uop_ctrl_br_type (io_req_bits_uop_ctrl_br_type),
.io_req_bits_uop_ctrl_op1_sel (io_req_bits_uop_ctrl_op1_sel),
.io_req_bits_uop_ctrl_op2_sel (io_req_bits_uop_ctrl_op2_sel),
.io_req_bits_uop_ctrl_imm_sel (io_req_bits_uop_ctrl_imm_sel),
.io_req_bits_uop_ctrl_op_fcn (io_req_bits_uop_ctrl_op_fcn),
.io_req_bits_uop_ctrl_fcn_dw (io_req_bits_uop_ctrl_fcn_dw),
.io_req_bits_uop_ctrl_csr_cmd (io_req_bits_uop_ctrl_csr_cmd),
.io_req_bits_uop_ctrl_is_load (io_req_bits_uop_ctrl_is_load),
.io_req_bits_uop_ctrl_is_sta (io_req_bits_uop_ctrl_is_sta),
.io_req_bits_uop_ctrl_is_std (io_req_bits_uop_ctrl_is_std),
.io_req_bits_uop_iw_state (io_req_bits_uop_iw_state),
.io_req_bits_uop_is_br (io_req_bits_uop_is_br),
.io_req_bits_uop_is_jalr (io_req_bits_uop_is_jalr),
.io_req_bits_uop_is_jal (io_req_bits_uop_is_jal),
.io_req_bits_uop_is_sfb (io_req_bits_uop_is_sfb),
.io_req_bits_uop_br_mask (io_req_bits_uop_br_mask),
.io_req_bits_uop_br_tag (io_req_bits_uop_br_tag),
.io_req_bits_uop_ftq_idx (io_req_bits_uop_ftq_idx),
.io_req_bits_uop_edge_inst (io_req_bits_uop_edge_inst),
.io_req_bits_uop_pc_lob (io_req_bits_uop_pc_lob),
.io_req_bits_uop_taken (io_req_bits_uop_taken),
.io_req_bits_uop_imm_packed (io_req_bits_uop_imm_packed),
.io_req_bits_uop_csr_addr (io_req_bits_uop_csr_addr),
.io_req_bits_uop_rob_idx (io_req_bits_uop_rob_idx),
.io_req_bits_uop_ldq_idx (io_req_bits_uop_ldq_idx),
.io_req_bits_uop_stq_idx (io_req_bits_uop_stq_idx),
.io_req_bits_uop_rxq_idx (io_req_bits_uop_rxq_idx),
.io_req_bits_uop_pdst (io_req_bits_uop_pdst),
.io_req_bits_uop_prs1 (io_req_bits_uop_prs1),
.io_req_bits_uop_prs2 (io_req_bits_uop_prs2),
.io_req_bits_uop_prs3 (io_req_bits_uop_prs3),
.io_req_bits_uop_ppred (io_req_bits_uop_ppred),
.io_req_bits_uop_prs1_busy (io_req_bits_uop_prs1_busy),
.io_req_bits_uop_prs2_busy (io_req_bits_uop_prs2_busy),
.io_req_bits_uop_prs3_busy (io_req_bits_uop_prs3_busy),
.io_req_bits_uop_ppred_busy (io_req_bits_uop_ppred_busy),
.io_req_bits_uop_stale_pdst (io_req_bits_uop_stale_pdst),
.io_req_bits_uop_exception (io_req_bits_uop_exception),
.io_req_bits_uop_exc_cause (io_req_bits_uop_exc_cause),
.io_req_bits_uop_bypassable (io_req_bits_uop_bypassable),
.io_req_bits_uop_mem_cmd (io_req_bits_uop_mem_cmd),
.io_req_bits_uop_mem_size (io_req_bits_uop_mem_size),
.io_req_bits_uop_mem_signed (io_req_bits_uop_mem_signed),
.io_req_bits_uop_is_fence (io_req_bits_uop_is_fence),
.io_req_bits_uop_is_fencei (io_req_bits_uop_is_fencei),
.io_req_bits_uop_is_amo (io_req_bits_uop_is_amo),
.io_req_bits_uop_uses_ldq (io_req_bits_uop_uses_ldq),
.io_req_bits_uop_uses_stq (io_req_bits_uop_uses_stq),
.io_req_bits_uop_is_sys_pc2epc (io_req_bits_uop_is_sys_pc2epc),
.io_req_bits_uop_is_unique (io_req_bits_uop_is_unique),
.io_req_bits_uop_flush_on_commit (io_req_bits_uop_flush_on_commit),
.io_req_bits_uop_ldst_is_rs1 (io_req_bits_uop_ldst_is_rs1),
.io_req_bits_uop_ldst (io_req_bits_uop_ldst),
.io_req_bits_uop_lrs1 (io_req_bits_uop_lrs1),
.io_req_bits_uop_lrs2 (io_req_bits_uop_lrs2),
.io_req_bits_uop_lrs3 (io_req_bits_uop_lrs3),
.io_req_bits_uop_ldst_val (io_req_bits_uop_ldst_val),
.io_req_bits_uop_dst_rtype (io_req_bits_uop_dst_rtype),
.io_req_bits_uop_lrs1_rtype (io_req_bits_uop_lrs1_rtype),
.io_req_bits_uop_lrs2_rtype (io_req_bits_uop_lrs2_rtype),
.io_req_bits_uop_frs3_en (io_req_bits_uop_frs3_en),
.io_req_bits_uop_fp_val (io_req_bits_uop_fp_val),
.io_req_bits_uop_fp_single (io_req_bits_uop_fp_single),
.io_req_bits_uop_xcpt_pf_if (io_req_bits_uop_xcpt_pf_if),
.io_req_bits_uop_xcpt_ae_if (io_req_bits_uop_xcpt_ae_if),
.io_req_bits_uop_xcpt_ma_if (io_req_bits_uop_xcpt_ma_if),
.io_req_bits_uop_bp_debug_if (io_req_bits_uop_bp_debug_if),
.io_req_bits_uop_bp_xcpt_if (io_req_bits_uop_bp_xcpt_if),
.io_req_bits_uop_debug_fsrc (io_req_bits_uop_debug_fsrc),
.io_req_bits_uop_debug_tsrc (io_req_bits_uop_debug_tsrc),
.io_req_bits_rs1_data (io_req_bits_rs1_data),
.io_req_bits_rs2_data (io_req_bits_rs2_data),
.io_resp_valid (io_lsu_io_req_valid),
.io_resp_bits_uop_uopc (io_lsu_io_req_bits_uop_uopc),
.io_resp_bits_uop_inst (io_lsu_io_req_bits_uop_inst),
.io_resp_bits_uop_debug_inst (io_lsu_io_req_bits_uop_debug_inst),
.io_resp_bits_uop_is_rvc (io_lsu_io_req_bits_uop_is_rvc),
.io_resp_bits_uop_debug_pc (io_lsu_io_req_bits_uop_debug_pc),
.io_resp_bits_uop_iq_type (io_lsu_io_req_bits_uop_iq_type),
.io_resp_bits_uop_fu_code (io_lsu_io_req_bits_uop_fu_code),
.io_resp_bits_uop_ctrl_br_type (io_lsu_io_req_bits_uop_ctrl_br_type),
.io_resp_bits_uop_ctrl_op1_sel (io_lsu_io_req_bits_uop_ctrl_op1_sel),
.io_resp_bits_uop_ctrl_op2_sel (io_lsu_io_req_bits_uop_ctrl_op2_sel),
.io_resp_bits_uop_ctrl_imm_sel (io_lsu_io_req_bits_uop_ctrl_imm_sel),
.io_resp_bits_uop_ctrl_op_fcn (io_lsu_io_req_bits_uop_ctrl_op_fcn),
.io_resp_bits_uop_ctrl_fcn_dw (io_lsu_io_req_bits_uop_ctrl_fcn_dw),
.io_resp_bits_uop_ctrl_csr_cmd (io_lsu_io_req_bits_uop_ctrl_csr_cmd),
.io_resp_bits_uop_ctrl_is_load (io_lsu_io_req_bits_uop_ctrl_is_load),
.io_resp_bits_uop_ctrl_is_sta (io_lsu_io_req_bits_uop_ctrl_is_sta),
.io_resp_bits_uop_ctrl_is_std (io_lsu_io_req_bits_uop_ctrl_is_std),
.io_resp_bits_uop_iw_state (io_lsu_io_req_bits_uop_iw_state),
.io_resp_bits_uop_is_br (io_lsu_io_req_bits_uop_is_br),
.io_resp_bits_uop_is_jalr (io_lsu_io_req_bits_uop_is_jalr),
.io_resp_bits_uop_is_jal (io_lsu_io_req_bits_uop_is_jal),
.io_resp_bits_uop_is_sfb (io_lsu_io_req_bits_uop_is_sfb),
.io_resp_bits_uop_br_mask (io_lsu_io_req_bits_uop_br_mask),
.io_resp_bits_uop_br_tag (io_lsu_io_req_bits_uop_br_tag),
.io_resp_bits_uop_ftq_idx (io_lsu_io_req_bits_uop_ftq_idx),
.io_resp_bits_uop_edge_inst (io_lsu_io_req_bits_uop_edge_inst),
.io_resp_bits_uop_pc_lob (io_lsu_io_req_bits_uop_pc_lob),
.io_resp_bits_uop_taken (io_lsu_io_req_bits_uop_taken),
.io_resp_bits_uop_imm_packed (io_lsu_io_req_bits_uop_imm_packed),
.io_resp_bits_uop_csr_addr (io_lsu_io_req_bits_uop_csr_addr),
.io_resp_bits_uop_rob_idx (io_lsu_io_req_bits_uop_rob_idx),
.io_resp_bits_uop_ldq_idx (io_lsu_io_req_bits_uop_ldq_idx),
.io_resp_bits_uop_stq_idx (io_lsu_io_req_bits_uop_stq_idx),
.io_resp_bits_uop_rxq_idx (io_lsu_io_req_bits_uop_rxq_idx),
.io_resp_bits_uop_pdst (io_lsu_io_req_bits_uop_pdst),
.io_resp_bits_uop_prs1 (io_lsu_io_req_bits_uop_prs1),
.io_resp_bits_uop_prs2 (io_lsu_io_req_bits_uop_prs2),
.io_resp_bits_uop_prs3 (io_lsu_io_req_bits_uop_prs3),
.io_resp_bits_uop_ppred (io_lsu_io_req_bits_uop_ppred),
.io_resp_bits_uop_prs1_busy (io_lsu_io_req_bits_uop_prs1_busy),
.io_resp_bits_uop_prs2_busy (io_lsu_io_req_bits_uop_prs2_busy),
.io_resp_bits_uop_prs3_busy (io_lsu_io_req_bits_uop_prs3_busy),
.io_resp_bits_uop_ppred_busy (io_lsu_io_req_bits_uop_ppred_busy),
.io_resp_bits_uop_stale_pdst (io_lsu_io_req_bits_uop_stale_pdst),
.io_resp_bits_uop_exception (io_lsu_io_req_bits_uop_exception),
.io_resp_bits_uop_exc_cause (io_lsu_io_req_bits_uop_exc_cause),
.io_resp_bits_uop_bypassable (io_lsu_io_req_bits_uop_bypassable),
.io_resp_bits_uop_mem_cmd (io_lsu_io_req_bits_uop_mem_cmd),
.io_resp_bits_uop_mem_size (io_lsu_io_req_bits_uop_mem_size),
.io_resp_bits_uop_mem_signed (io_lsu_io_req_bits_uop_mem_signed),
.io_resp_bits_uop_is_fence (io_lsu_io_req_bits_uop_is_fence),
.io_resp_bits_uop_is_fencei (io_lsu_io_req_bits_uop_is_fencei),
.io_resp_bits_uop_is_amo (io_lsu_io_req_bits_uop_is_amo),
.io_resp_bits_uop_uses_ldq (io_lsu_io_req_bits_uop_uses_ldq),
.io_resp_bits_uop_uses_stq (io_lsu_io_req_bits_uop_uses_stq),
.io_resp_bits_uop_is_sys_pc2epc (io_lsu_io_req_bits_uop_is_sys_pc2epc),
.io_resp_bits_uop_is_unique (io_lsu_io_req_bits_uop_is_unique),
.io_resp_bits_uop_flush_on_commit (io_lsu_io_req_bits_uop_flush_on_commit),
.io_resp_bits_uop_ldst_is_rs1 (io_lsu_io_req_bits_uop_ldst_is_rs1),
.io_resp_bits_uop_ldst (io_lsu_io_req_bits_uop_ldst),
.io_resp_bits_uop_lrs1 (io_lsu_io_req_bits_uop_lrs1),
.io_resp_bits_uop_lrs2 (io_lsu_io_req_bits_uop_lrs2),
.io_resp_bits_uop_lrs3 (io_lsu_io_req_bits_uop_lrs3),
.io_resp_bits_uop_ldst_val (io_lsu_io_req_bits_uop_ldst_val),
.io_resp_bits_uop_dst_rtype (io_lsu_io_req_bits_uop_dst_rtype),
.io_resp_bits_uop_lrs1_rtype (io_lsu_io_req_bits_uop_lrs1_rtype),
.io_resp_bits_uop_lrs2_rtype (io_lsu_io_req_bits_uop_lrs2_rtype),
.io_resp_bits_uop_frs3_en (io_lsu_io_req_bits_uop_frs3_en),
.io_resp_bits_uop_fp_val (io_lsu_io_req_bits_uop_fp_val),
.io_resp_bits_uop_fp_single (io_lsu_io_req_bits_uop_fp_single),
.io_resp_bits_uop_xcpt_pf_if (io_lsu_io_req_bits_uop_xcpt_pf_if),
.io_resp_bits_uop_xcpt_ae_if (io_lsu_io_req_bits_uop_xcpt_ae_if),
.io_resp_bits_uop_xcpt_ma_if (io_lsu_io_req_bits_uop_xcpt_ma_if),
.io_resp_bits_uop_bp_debug_if (io_lsu_io_req_bits_uop_bp_debug_if),
.io_resp_bits_uop_bp_xcpt_if (io_lsu_io_req_bits_uop_bp_xcpt_if),
.io_resp_bits_uop_debug_fsrc (io_lsu_io_req_bits_uop_debug_fsrc),
.io_resp_bits_uop_debug_tsrc (io_lsu_io_req_bits_uop_debug_tsrc),
.io_resp_bits_data (_maddrcalc_io_resp_bits_data),
.io_resp_bits_addr (io_lsu_io_req_bits_addr),
.io_resp_bits_mxcpt_valid (io_lsu_io_req_bits_mxcpt_valid),
.io_resp_bits_sfence_valid (io_lsu_io_req_bits_sfence_valid),
.io_resp_bits_sfence_bits_rs1 (io_lsu_io_req_bits_sfence_bits_rs1),
.io_resp_bits_sfence_bits_rs2 (io_lsu_io_req_bits_sfence_bits_rs2),
.io_resp_bits_sfence_bits_addr (io_lsu_io_req_bits_sfence_bits_addr),
.io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask),
.io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask)
);
assign io_ll_iresp_valid = io_lsu_io_iresp_valid;
assign io_ll_iresp_bits_uop_rob_idx = io_lsu_io_iresp_bits_uop_rob_idx;
assign io_ll_iresp_bits_uop_pdst = io_lsu_io_iresp_bits_uop_pdst;
assign io_ll_iresp_bits_uop_is_amo = io_lsu_io_iresp_bits_uop_is_amo;
assign io_ll_iresp_bits_uop_uses_stq = io_lsu_io_iresp_bits_uop_uses_stq;
assign io_ll_iresp_bits_uop_dst_rtype = io_lsu_io_iresp_bits_uop_dst_rtype;
assign io_ll_iresp_bits_data = {1'h0, io_lsu_io_iresp_bits_data};
assign io_ll_fresp_valid = io_lsu_io_fresp_valid;
assign io_ll_fresp_bits_uop_uopc = io_lsu_io_fresp_bits_uop_uopc;
assign io_ll_fresp_bits_uop_br_mask = io_lsu_io_fresp_bits_uop_br_mask;
assign io_ll_fresp_bits_uop_rob_idx = io_lsu_io_fresp_bits_uop_rob_idx;
assign io_ll_fresp_bits_uop_stq_idx = io_lsu_io_fresp_bits_uop_stq_idx;
assign io_ll_fresp_bits_uop_pdst = io_lsu_io_fresp_bits_uop_pdst;
assign io_ll_fresp_bits_uop_mem_size = io_lsu_io_fresp_bits_uop_mem_size;
assign io_ll_fresp_bits_uop_is_amo = io_lsu_io_fresp_bits_uop_is_amo;
assign io_ll_fresp_bits_uop_uses_stq = io_lsu_io_fresp_bits_uop_uses_stq;
assign io_ll_fresp_bits_uop_dst_rtype = io_lsu_io_fresp_bits_uop_dst_rtype;
assign io_ll_fresp_bits_uop_fp_val = io_lsu_io_fresp_bits_uop_fp_val;
assign io_ll_fresp_bits_data = io_lsu_io_fresp_bits_data;
assign io_lsu_io_req_bits_data = _maddrcalc_io_resp_bits_data[63:0];
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
trait TLFieldHelper {
def getBodyFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleC => Seq( b.data, b.corrupt)
case b: TLBundleD => Seq( b.data, b.corrupt)
case b: TLBundleE => Seq()
}
def getConstFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )
case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)
case b: TLBundleE => Seq( b.sink )
}
def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max
def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max
def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))
}
class TLBeat(val beatWidth: Int) extends Bundle {
val payload = UInt(beatWidth.W)
val head = Bool()
val tail = Bool()
}
abstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Flipped(Decoupled(gen))
val beat = Decoupled(new TLBeat(beatWidth))
})
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
// convert decoupled to irrevocable
val q = Module(new Queue(gen, 1, pipe=true, flow=true))
q.io.enq <> io.protocol
val protocol = q.io.deq
val has_body = Wire(Bool())
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val head = edge.first(protocol.bits, protocol.fire)
val tail = edge.last(protocol.bits, protocol.fire)
val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))
val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))
val is_body = RegInit(false.B)
io.beat.valid := protocol.valid
protocol.ready := io.beat.ready && (is_body || !has_body)
io.beat.bits.head := head && !is_body
io.beat.bits.tail := tail && (is_body || !has_body)
io.beat.bits.payload := Mux(is_body, body, const)
when (io.beat.fire && io.beat.bits.head) { is_body := true.B }
when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }
}
abstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Decoupled(gen)
val beat = Flipped(Decoupled(new TLBeat(beatWidth)))
})
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
val protocol = Wire(Decoupled(gen))
io.protocol <> protocol
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val is_const = RegInit(true.B)
val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))
val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)
io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready
protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid
def assign(i: UInt, sigs: Seq[Data]) = {
var t = i
for (s <- sigs.reverse) {
s := t.asTypeOf(s.cloneType)
t = t >> s.getWidth
}
}
assign(const, const_fields)
assign(io.beat.bits.payload, body_fields)
when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }
when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }
}
class TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)
class TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits)
}
class TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)
class TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p) | module TLBFromBeat_serial_tl_0_a64d64s8k8z8c(
input clock,
input reset,
output io_beat_ready,
input io_beat_valid,
input io_beat_bits_head,
input io_beat_bits_tail
);
reg is_const;
wire io_beat_ready_0 = is_const & ~io_beat_bits_tail;
wire _GEN = io_beat_ready_0 & io_beat_valid;
always @(posedge clock) begin
if (reset)
is_const <= 1'h1;
else
is_const <= _GEN & io_beat_bits_tail | ~(_GEN & io_beat_bits_head) & is_const;
end
assign io_beat_ready = io_beat_ready_0;
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
} | module ram_3x77(
input [1:0] R0_addr,
input R0_en,
input R0_clk,
output [76:0] R0_data,
input [1:0] W0_addr,
input W0_en,
input W0_clk,
input [76:0] W0_data
);
reg [76:0] Memory[0:2];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 77'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
} | module RoundRawFNToRecFN_e11_s53_1(
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [2:0] io_roundingMode,
output [64:0] io_out,
output [4:0] io_exceptionFlags
);
RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_1 roundAnyRawFNToRecFN (
.io_invalidExc (io_invalidExc),
.io_infiniteExc (io_infiniteExc),
.io_in_isNaN (io_in_isNaN),
.io_in_isInf (io_in_isInf),
.io_in_isZero (io_in_isZero),
.io_in_sign (io_in_sign),
.io_in_sExp (io_in_sExp),
.io_in_sig (io_in_sig),
.io_roundingMode (io_roundingMode),
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Ported from Rocket-Chip
// See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.lsu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.rocket._
import boom.v3.common._
import boom.v3.exu.BrUpdateInfo
import boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc}
class BoomDCacheReqInternal(implicit p: Parameters) extends BoomDCacheReq()(p)
with HasL1HellaCacheParameters
{
// miss info
val tag_match = Bool()
val old_meta = new L1Metadata
val way_en = UInt(nWays.W)
// Used in the MSHRs
val sdq_id = UInt(log2Ceil(cfg.nSDQ).W)
}
class BoomMSHR(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)
with HasL1HellaCacheParameters
{
val io = IO(new Bundle {
val id = Input(UInt())
val req_pri_val = Input(Bool())
val req_pri_rdy = Output(Bool())
val req_sec_val = Input(Bool())
val req_sec_rdy = Output(Bool())
val clear_prefetch = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val exception = Input(Bool())
val rob_pnr_idx = Input(UInt(robAddrSz.W))
val rob_head_idx = Input(UInt(robAddrSz.W))
val req = Input(new BoomDCacheReqInternal)
val req_is_probe = Input(Bool())
val idx = Output(Valid(UInt()))
val way = Output(Valid(UInt()))
val tag = Output(Valid(UInt()))
val mem_acquire = Decoupled(new TLBundleA(edge.bundle))
val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle)))
val mem_finish = Decoupled(new TLBundleE(edge.bundle))
val prober_state = Input(Valid(UInt(coreMaxAddrBits.W)))
val refill = Decoupled(new L1DataWriteReq)
val meta_write = Decoupled(new L1MetaWriteReq)
val meta_read = Decoupled(new L1MetaReadReq)
val meta_resp = Input(Valid(new L1Metadata))
val wb_req = Decoupled(new WritebackReq(edge.bundle))
// To inform the prefetcher when we are commiting the fetch of this line
val commit_val = Output(Bool())
val commit_addr = Output(UInt(coreMaxAddrBits.W))
val commit_coh = Output(new ClientMetadata)
// Reading from the line buffer
val lb_read = Decoupled(new LineBufferReadReq)
val lb_resp = Input(UInt(encRowBits.W))
val lb_write = Decoupled(new LineBufferWriteReq)
// Replays go through the cache pipeline again
val replay = Decoupled(new BoomDCacheReqInternal)
// Resp go straight out to the core
val resp = Decoupled(new BoomDCacheResp)
// Writeback unit tells us when it is done processing our wb
val wb_resp = Input(Bool())
val probe_rdy = Output(Bool())
})
// TODO: Optimize this. We don't want to mess with cache during speculation
// s_refill_req : Make a request for a new cache line
// s_refill_resp : Store the refill response into our buffer
// s_drain_rpq_loads : Drain out loads from the rpq
// : If miss was misspeculated, go to s_invalid
// s_wb_req : Write back the evicted cache line
// s_wb_resp : Finish writing back the evicted cache line
// s_meta_write_req : Write the metadata for new cache lne
// s_meta_write_resp :
val s_invalid :: s_refill_req :: s_refill_resp :: s_drain_rpq_loads :: s_meta_read :: s_meta_resp_1 :: s_meta_resp_2 :: s_meta_clear :: s_wb_meta_read :: s_wb_req :: s_wb_resp :: s_commit_line :: s_drain_rpq :: s_meta_write_req :: s_mem_finish_1 :: s_mem_finish_2 :: s_prefetched :: s_prefetch :: Nil = Enum(18)
val state = RegInit(s_invalid)
val req = Reg(new BoomDCacheReqInternal)
val req_idx = req.addr(untagBits-1, blockOffBits)
val req_tag = req.addr >> untagBits
val req_block_addr = (req.addr >> blockOffBits) << blockOffBits
val req_needs_wb = RegInit(false.B)
val new_coh = RegInit(ClientMetadata.onReset)
val (_, shrink_param, coh_on_clear) = req.old_meta.coh.onCacheControl(M_FLUSH)
val grow_param = new_coh.onAccess(req.uop.mem_cmd)._2
val coh_on_grant = new_coh.onGrant(req.uop.mem_cmd, io.mem_grant.bits.param)
// We only accept secondary misses if the original request had sufficient permissions
val (cmd_requires_second_acquire, is_hit_again, _, dirtier_coh, dirtier_cmd) =
new_coh.onSecondaryAccess(req.uop.mem_cmd, io.req.uop.mem_cmd)
val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant)
val sec_rdy = (!cmd_requires_second_acquire && !io.req_is_probe &&
!state.isOneOf(s_invalid, s_meta_write_req, s_mem_finish_1, s_mem_finish_2))// Always accept secondary misses
val rpq = Module(new BranchKillableQueue(new BoomDCacheReqInternal, cfg.nRPQ, u => u.uses_ldq, false))
rpq.io.brupdate := io.brupdate
rpq.io.flush := io.exception
assert(!(state === s_invalid && !rpq.io.empty))
rpq.io.enq.valid := ((io.req_pri_val && io.req_pri_rdy) || (io.req_sec_val && io.req_sec_rdy)) && !isPrefetch(io.req.uop.mem_cmd)
rpq.io.enq.bits := io.req
rpq.io.deq.ready := false.B
val grantack = Reg(Valid(new TLBundleE(edge.bundle)))
val refill_ctr = Reg(UInt(log2Ceil(cacheDataBeats).W))
val commit_line = Reg(Bool())
val grant_had_data = Reg(Bool())
val finish_to_prefetch = Reg(Bool())
// Block probes if a tag write we started is still in the pipeline
val meta_hazard = RegInit(0.U(2.W))
when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U }
when (io.meta_write.fire) { meta_hazard := 1.U }
io.probe_rdy := (meta_hazard === 0.U && (state.isOneOf(s_invalid, s_refill_req, s_refill_resp, s_drain_rpq_loads) || (state === s_meta_read && grantack.valid)))
io.idx.valid := state =/= s_invalid
io.tag.valid := state =/= s_invalid
io.way.valid := !state.isOneOf(s_invalid, s_prefetch)
io.idx.bits := req_idx
io.tag.bits := req_tag
io.way.bits := req.way_en
io.meta_write.valid := false.B
io.meta_write.bits := DontCare
io.req_pri_rdy := false.B
io.req_sec_rdy := sec_rdy && rpq.io.enq.ready
io.mem_acquire.valid := false.B
io.mem_acquire.bits := DontCare
io.refill.valid := false.B
io.refill.bits := DontCare
io.replay.valid := false.B
io.replay.bits := DontCare
io.wb_req.valid := false.B
io.wb_req.bits := DontCare
io.resp.valid := false.B
io.resp.bits := DontCare
io.commit_val := false.B
io.commit_addr := req.addr
io.commit_coh := coh_on_grant
io.meta_read.valid := false.B
io.meta_read.bits := DontCare
io.mem_finish.valid := false.B
io.mem_finish.bits := DontCare
io.lb_write.valid := false.B
io.lb_write.bits := DontCare
io.lb_read.valid := false.B
io.lb_read.bits := DontCare
io.mem_grant.ready := false.B
when (io.req_sec_val && io.req_sec_rdy) {
req.uop.mem_cmd := dirtier_cmd
when (is_hit_again) {
new_coh := dirtier_coh
}
}
def handle_pri_req(old_state: UInt): UInt = {
val new_state = WireInit(old_state)
grantack.valid := false.B
refill_ctr := 0.U
assert(rpq.io.enq.ready)
req := io.req
val old_coh = io.req.old_meta.coh
req_needs_wb := old_coh.onCacheControl(M_FLUSH)._1 // does the line we are evicting need to be written back
when (io.req.tag_match) {
val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req.uop.mem_cmd)
when (is_hit) { // set dirty bit
assert(isWrite(io.req.uop.mem_cmd))
new_coh := coh_on_hit
new_state := s_drain_rpq
} .otherwise { // upgrade permissions
new_coh := old_coh
new_state := s_refill_req
}
} .otherwise { // refill and writeback if necessary
new_coh := ClientMetadata.onReset
new_state := s_refill_req
}
new_state
}
when (state === s_invalid) {
io.req_pri_rdy := true.B
grant_had_data := false.B
when (io.req_pri_val && io.req_pri_rdy) {
state := handle_pri_req(state)
}
} .elsewhen (state === s_refill_req) {
io.mem_acquire.valid := true.B
// TODO: Use AcquirePerm if just doing permissions acquire
io.mem_acquire.bits := edge.AcquireBlock(
fromSource = io.id,
toAddress = Cat(req_tag, req_idx) << blockOffBits,
lgSize = lgCacheBlockBytes.U,
growPermissions = grow_param)._2
when (io.mem_acquire.fire) {
state := s_refill_resp
}
} .elsewhen (state === s_refill_resp) {
when (edge.hasData(io.mem_grant.bits)) {
io.mem_grant.ready := io.lb_write.ready
io.lb_write.valid := io.mem_grant.valid
io.lb_write.bits.id := io.id
io.lb_write.bits.offset := refill_address_inc >> rowOffBits
io.lb_write.bits.data := io.mem_grant.bits.data
} .otherwise {
io.mem_grant.ready := true.B
}
when (io.mem_grant.fire) {
grant_had_data := edge.hasData(io.mem_grant.bits)
}
when (refill_done) {
grantack.valid := edge.isRequest(io.mem_grant.bits)
grantack.bits := edge.GrantAck(io.mem_grant.bits)
state := Mux(grant_had_data, s_drain_rpq_loads, s_drain_rpq)
assert(!(!grant_had_data && req_needs_wb))
commit_line := false.B
new_coh := coh_on_grant
}
} .elsewhen (state === s_drain_rpq_loads) {
val drain_load = (isRead(rpq.io.deq.bits.uop.mem_cmd) &&
!isWrite(rpq.io.deq.bits.uop.mem_cmd) &&
(rpq.io.deq.bits.uop.mem_cmd =/= M_XLR)) // LR should go through replay
// drain all loads for now
val rp_addr = Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0))
val word_idx = if (rowWords == 1) 0.U else rp_addr(log2Up(rowWords*coreDataBytes)-1, log2Up(wordBytes))
val data = io.lb_resp
val data_word = data >> Cat(word_idx, 0.U(log2Up(coreDataBits).W))
val loadgen = new LoadGen(rpq.io.deq.bits.uop.mem_size, rpq.io.deq.bits.uop.mem_signed,
Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)),
data_word, false.B, wordBytes)
rpq.io.deq.ready := io.resp.ready && io.lb_read.ready && drain_load
io.lb_read.valid := rpq.io.deq.valid && drain_load
io.lb_read.bits.id := io.id
io.lb_read.bits.offset := rpq.io.deq.bits.addr >> rowOffBits
io.resp.valid := rpq.io.deq.valid && io.lb_read.fire && drain_load
io.resp.bits.uop := rpq.io.deq.bits.uop
io.resp.bits.data := loadgen.data
io.resp.bits.is_hella := rpq.io.deq.bits.is_hella
when (rpq.io.deq.fire) {
commit_line := true.B
}
.elsewhen (rpq.io.empty && !commit_line)
{
when (!rpq.io.enq.fire) {
state := s_mem_finish_1
finish_to_prefetch := enablePrefetching.B
}
} .elsewhen (rpq.io.empty || (rpq.io.deq.valid && !drain_load)) {
// io.commit_val is for the prefetcher. it tells the prefetcher that this line was correctly acquired
// The prefetcher should consider fetching the next line
io.commit_val := true.B
state := s_meta_read
}
} .elsewhen (state === s_meta_read) {
io.meta_read.valid := !io.prober_state.valid || !grantack.valid || (io.prober_state.bits(untagBits-1,blockOffBits) =/= req_idx)
io.meta_read.bits.idx := req_idx
io.meta_read.bits.tag := req_tag
io.meta_read.bits.way_en := req.way_en
when (io.meta_read.fire) {
state := s_meta_resp_1
}
} .elsewhen (state === s_meta_resp_1) {
state := s_meta_resp_2
} .elsewhen (state === s_meta_resp_2) {
val needs_wb = io.meta_resp.bits.coh.onCacheControl(M_FLUSH)._1
state := Mux(!io.meta_resp.valid, s_meta_read, // Prober could have nack'd this read
Mux(needs_wb, s_meta_clear, s_commit_line))
} .elsewhen (state === s_meta_clear) {
io.meta_write.valid := true.B
io.meta_write.bits.idx := req_idx
io.meta_write.bits.data.coh := coh_on_clear
io.meta_write.bits.data.tag := req_tag
io.meta_write.bits.way_en := req.way_en
when (io.meta_write.fire) {
state := s_wb_req
}
} .elsewhen (state === s_wb_req) {
io.wb_req.valid := true.B
io.wb_req.bits.tag := req.old_meta.tag
io.wb_req.bits.idx := req_idx
io.wb_req.bits.param := shrink_param
io.wb_req.bits.way_en := req.way_en
io.wb_req.bits.source := io.id
io.wb_req.bits.voluntary := true.B
when (io.wb_req.fire) {
state := s_wb_resp
}
} .elsewhen (state === s_wb_resp) {
when (io.wb_resp) {
state := s_commit_line
}
} .elsewhen (state === s_commit_line) {
io.lb_read.valid := true.B
io.lb_read.bits.id := io.id
io.lb_read.bits.offset := refill_ctr
io.refill.valid := io.lb_read.fire
io.refill.bits.addr := req_block_addr | (refill_ctr << rowOffBits)
io.refill.bits.way_en := req.way_en
io.refill.bits.wmask := ~(0.U(rowWords.W))
io.refill.bits.data := io.lb_resp
when (io.refill.fire) {
refill_ctr := refill_ctr + 1.U
when (refill_ctr === (cacheDataBeats - 1).U) {
state := s_drain_rpq
}
}
} .elsewhen (state === s_drain_rpq) {
io.replay <> rpq.io.deq
io.replay.bits.way_en := req.way_en
io.replay.bits.addr := Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0))
when (io.replay.fire && isWrite(rpq.io.deq.bits.uop.mem_cmd)) {
// Set dirty bit
val (is_hit, _, coh_on_hit) = new_coh.onAccess(rpq.io.deq.bits.uop.mem_cmd)
assert(is_hit, "We still don't have permissions for this store")
new_coh := coh_on_hit
}
when (rpq.io.empty && !rpq.io.enq.valid) {
state := s_meta_write_req
}
} .elsewhen (state === s_meta_write_req) {
io.meta_write.valid := true.B
io.meta_write.bits.idx := req_idx
io.meta_write.bits.data.coh := new_coh
io.meta_write.bits.data.tag := req_tag
io.meta_write.bits.way_en := req.way_en
when (io.meta_write.fire) {
state := s_mem_finish_1
finish_to_prefetch := false.B
}
} .elsewhen (state === s_mem_finish_1) {
io.mem_finish.valid := grantack.valid
io.mem_finish.bits := grantack.bits
when (io.mem_finish.fire || !grantack.valid) {
grantack.valid := false.B
state := s_mem_finish_2
}
} .elsewhen (state === s_mem_finish_2) {
state := Mux(finish_to_prefetch, s_prefetch, s_invalid)
} .elsewhen (state === s_prefetch) {
io.req_pri_rdy := true.B
when ((io.req_sec_val && !io.req_sec_rdy) || io.clear_prefetch) {
state := s_invalid
} .elsewhen (io.req_sec_val && io.req_sec_rdy) {
val (is_hit, _, coh_on_hit) = new_coh.onAccess(io.req.uop.mem_cmd)
when (is_hit) { // Proceed with refill
new_coh := coh_on_hit
state := s_meta_read
} .otherwise { // Reacquire this line
new_coh := ClientMetadata.onReset
state := s_refill_req
}
} .elsewhen (io.req_pri_val && io.req_pri_rdy) {
grant_had_data := false.B
state := handle_pri_req(state)
}
}
}
class BoomIOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)
with HasL1HellaCacheParameters
{
val io = IO(new Bundle {
val req = Flipped(Decoupled(new BoomDCacheReq))
val resp = Decoupled(new BoomDCacheResp)
val mem_access = Decoupled(new TLBundleA(edge.bundle))
val mem_ack = Flipped(Valid(new TLBundleD(edge.bundle)))
// We don't need brupdate in here because uncacheable operations are guaranteed non-speculative
})
def beatOffset(addr: UInt) = addr.extract(beatOffBits-1, wordOffBits)
def wordFromBeat(addr: UInt, dat: UInt) = {
val shift = Cat(beatOffset(addr), 0.U((wordOffBits+log2Ceil(wordBytes)).W))
(dat >> shift)(wordBits-1, 0)
}
val req = Reg(new BoomDCacheReq)
val grant_word = Reg(UInt(wordBits.W))
val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(4)
val state = RegInit(s_idle)
io.req.ready := state === s_idle
val loadgen = new LoadGen(req.uop.mem_size, req.uop.mem_signed, req.addr, grant_word, false.B, wordBytes)
val a_source = id.U
val a_address = req.addr
val a_size = req.uop.mem_size
val a_data = Fill(beatWords, req.data)
val get = edge.Get(a_source, a_address, a_size)._2
val put = edge.Put(a_source, a_address, a_size, a_data)._2
val atomics = if (edge.manager.anySupportLogical) {
MuxLookup(req.uop.mem_cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)))(Array(
M_XA_SWAP -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.SWAP)._2,
M_XA_XOR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.XOR) ._2,
M_XA_OR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.OR) ._2,
M_XA_AND -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.AND) ._2,
M_XA_ADD -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.ADD)._2,
M_XA_MIN -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MIN)._2,
M_XA_MAX -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAX)._2,
M_XA_MINU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MINU)._2,
M_XA_MAXU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAXU)._2))
} else {
// If no managers support atomics, assert fail if processor asks for them
assert(state === s_idle || !isAMO(req.uop.mem_cmd))
(0.U).asTypeOf(new TLBundleA(edge.bundle))
}
assert(state === s_idle || req.uop.mem_cmd =/= M_XSC)
io.mem_access.valid := state === s_mem_access
io.mem_access.bits := Mux(isAMO(req.uop.mem_cmd), atomics, Mux(isRead(req.uop.mem_cmd), get, put))
val send_resp = isRead(req.uop.mem_cmd)
io.resp.valid := (state === s_resp) && send_resp
io.resp.bits.is_hella := req.is_hella
io.resp.bits.uop := req.uop
io.resp.bits.data := loadgen.data
when (io.req.fire) {
req := io.req.bits
state := s_mem_access
}
when (io.mem_access.fire) {
state := s_mem_ack
}
when (state === s_mem_ack && io.mem_ack.valid) {
state := s_resp
when (isRead(req.uop.mem_cmd)) {
grant_word := wordFromBeat(req.addr, io.mem_ack.bits.data)
}
}
when (state === s_resp) {
when (!send_resp || io.resp.fire) {
state := s_idle
}
}
}
class LineBufferReadReq(implicit p: Parameters) extends BoomBundle()(p)
with HasL1HellaCacheParameters
{
val id = UInt(log2Ceil(nLBEntries).W)
val offset = UInt(log2Ceil(cacheDataBeats).W)
def lb_addr = Cat(id, offset)
}
class LineBufferWriteReq(implicit p: Parameters) extends LineBufferReadReq()(p)
{
val data = UInt(encRowBits.W)
}
class LineBufferMetaWriteReq(implicit p: Parameters) extends BoomBundle()(p)
{
val id = UInt(log2Ceil(nLBEntries).W)
val coh = new ClientMetadata
val addr = UInt(coreMaxAddrBits.W)
}
class LineBufferMeta(implicit p: Parameters) extends BoomBundle()(p)
with HasL1HellaCacheParameters
{
val coh = new ClientMetadata
val addr = UInt(coreMaxAddrBits.W)
}
class BoomMSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)
with HasL1HellaCacheParameters
{
val io = IO(new Bundle {
val req = Flipped(Vec(memWidth, Decoupled(new BoomDCacheReqInternal))) // Req from s2 of DCache pipe
val req_is_probe = Input(Vec(memWidth, Bool()))
val resp = Decoupled(new BoomDCacheResp)
val secondary_miss = Output(Vec(memWidth, Bool()))
val block_hit = Output(Vec(memWidth, Bool()))
val brupdate = Input(new BrUpdateInfo)
val exception = Input(Bool())
val rob_pnr_idx = Input(UInt(robAddrSz.W))
val rob_head_idx = Input(UInt(robAddrSz.W))
val mem_acquire = Decoupled(new TLBundleA(edge.bundle))
val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle)))
val mem_finish = Decoupled(new TLBundleE(edge.bundle))
val refill = Decoupled(new L1DataWriteReq)
val meta_write = Decoupled(new L1MetaWriteReq)
val meta_read = Decoupled(new L1MetaReadReq)
val meta_resp = Input(Valid(new L1Metadata))
val replay = Decoupled(new BoomDCacheReqInternal)
val prefetch = Decoupled(new BoomDCacheReq)
val wb_req = Decoupled(new WritebackReq(edge.bundle))
val prober_state = Input(Valid(UInt(coreMaxAddrBits.W)))
val clear_all = Input(Bool()) // Clears all uncommitted MSHRs to prepare for fence
val wb_resp = Input(Bool())
val fence_rdy = Output(Bool())
val probe_rdy = Output(Bool())
})
val req_idx = OHToUInt(io.req.map(_.valid))
val req = io.req(req_idx)
val req_is_probe = io.req_is_probe(0)
for (w <- 0 until memWidth)
io.req(w).ready := false.B
val prefetcher: DataPrefetcher = if (enablePrefetching) Module(new NLPrefetcher)
else Module(new NullPrefetcher)
io.prefetch <> prefetcher.io.prefetch
val cacheable = edge.manager.supportsAcquireBFast(req.bits.addr, lgCacheBlockBytes.U)
// --------------------
// The MSHR SDQ
val sdq_val = RegInit(0.U(cfg.nSDQ.W))
val sdq_alloc_id = PriorityEncoder(~sdq_val(cfg.nSDQ-1,0))
val sdq_rdy = !sdq_val.andR
val sdq_enq = req.fire && cacheable && isWrite(req.bits.uop.mem_cmd)
val sdq = Mem(cfg.nSDQ, UInt(coreDataBits.W))
when (sdq_enq) {
sdq(sdq_alloc_id) := req.bits.data
}
// --------------------
// The LineBuffer Data
// Holds refilling lines, prefetched lines
val lb = Mem(nLBEntries * cacheDataBeats, UInt(encRowBits.W))
val lb_read_arb = Module(new Arbiter(new LineBufferReadReq, cfg.nMSHRs))
val lb_write_arb = Module(new Arbiter(new LineBufferWriteReq, cfg.nMSHRs))
lb_read_arb.io.out.ready := false.B
lb_write_arb.io.out.ready := true.B
val lb_read_data = WireInit(0.U(encRowBits.W))
when (lb_write_arb.io.out.fire) {
lb.write(lb_write_arb.io.out.bits.lb_addr, lb_write_arb.io.out.bits.data)
} .otherwise {
lb_read_arb.io.out.ready := true.B
when (lb_read_arb.io.out.fire) {
lb_read_data := lb.read(lb_read_arb.io.out.bits.lb_addr)
}
}
def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f))
val idx_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool())))
val tag_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool())))
val way_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool())))
val tag_match = widthMap(w => Mux1H(idx_matches(w), tag_matches(w)))
val idx_match = widthMap(w => idx_matches(w).reduce(_||_))
val way_match = widthMap(w => Mux1H(idx_matches(w), way_matches(w)))
val wb_tag_list = Wire(Vec(cfg.nMSHRs, UInt(tagBits.W)))
val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq , cfg.nMSHRs))
val meta_read_arb = Module(new Arbiter(new L1MetaReadReq , cfg.nMSHRs))
val wb_req_arb = Module(new Arbiter(new WritebackReq(edge.bundle), cfg.nMSHRs))
val replay_arb = Module(new Arbiter(new BoomDCacheReqInternal , cfg.nMSHRs))
val resp_arb = Module(new Arbiter(new BoomDCacheResp , cfg.nMSHRs + nIOMSHRs))
val refill_arb = Module(new Arbiter(new L1DataWriteReq , cfg.nMSHRs))
val commit_vals = Wire(Vec(cfg.nMSHRs, Bool()))
val commit_addrs = Wire(Vec(cfg.nMSHRs, UInt(coreMaxAddrBits.W)))
val commit_cohs = Wire(Vec(cfg.nMSHRs, new ClientMetadata))
var sec_rdy = false.B
io.fence_rdy := true.B
io.probe_rdy := true.B
io.mem_grant.ready := false.B
val mshr_alloc_idx = Wire(UInt())
val pri_rdy = WireInit(false.B)
val pri_val = req.valid && sdq_rdy && cacheable && !idx_match(req_idx)
val mshrs = (0 until cfg.nMSHRs) map { i =>
val mshr = Module(new BoomMSHR)
mshr.io.id := i.U(log2Ceil(cfg.nMSHRs).W)
for (w <- 0 until memWidth) {
idx_matches(w)(i) := mshr.io.idx.valid && mshr.io.idx.bits === io.req(w).bits.addr(untagBits-1,blockOffBits)
tag_matches(w)(i) := mshr.io.tag.valid && mshr.io.tag.bits === io.req(w).bits.addr >> untagBits
way_matches(w)(i) := mshr.io.way.valid && mshr.io.way.bits === io.req(w).bits.way_en
}
wb_tag_list(i) := mshr.io.wb_req.bits.tag
mshr.io.req_pri_val := (i.U === mshr_alloc_idx) && pri_val
when (i.U === mshr_alloc_idx) {
pri_rdy := mshr.io.req_pri_rdy
}
mshr.io.req_sec_val := req.valid && sdq_rdy && tag_match(req_idx) && idx_matches(req_idx)(i) && cacheable
mshr.io.req := req.bits
mshr.io.req_is_probe := req_is_probe
mshr.io.req.sdq_id := sdq_alloc_id
// Clear because of a FENCE, a request to the same idx as a prefetched line,
// a probe to that prefetched line, all mshrs are in use
mshr.io.clear_prefetch := ((io.clear_all && !req.valid)||
(req.valid && idx_matches(req_idx)(i) && cacheable && !tag_match(req_idx)) ||
(req_is_probe && idx_matches(req_idx)(i)))
mshr.io.brupdate := io.brupdate
mshr.io.exception := io.exception
mshr.io.rob_pnr_idx := io.rob_pnr_idx
mshr.io.rob_head_idx := io.rob_head_idx
mshr.io.prober_state := io.prober_state
mshr.io.wb_resp := io.wb_resp
meta_write_arb.io.in(i) <> mshr.io.meta_write
meta_read_arb.io.in(i) <> mshr.io.meta_read
mshr.io.meta_resp := io.meta_resp
wb_req_arb.io.in(i) <> mshr.io.wb_req
replay_arb.io.in(i) <> mshr.io.replay
refill_arb.io.in(i) <> mshr.io.refill
lb_read_arb.io.in(i) <> mshr.io.lb_read
mshr.io.lb_resp := lb_read_data
lb_write_arb.io.in(i) <> mshr.io.lb_write
commit_vals(i) := mshr.io.commit_val
commit_addrs(i) := mshr.io.commit_addr
commit_cohs(i) := mshr.io.commit_coh
mshr.io.mem_grant.valid := false.B
mshr.io.mem_grant.bits := DontCare
when (io.mem_grant.bits.source === i.U) {
mshr.io.mem_grant <> io.mem_grant
}
sec_rdy = sec_rdy || (mshr.io.req_sec_rdy && mshr.io.req_sec_val)
resp_arb.io.in(i) <> mshr.io.resp
when (!mshr.io.req_pri_rdy) {
io.fence_rdy := false.B
}
for (w <- 0 until memWidth) {
when (!mshr.io.probe_rdy && idx_matches(w)(i) && io.req_is_probe(w)) {
io.probe_rdy := false.B
}
}
mshr
}
// Try to round-robin the MSHRs
val mshr_head = RegInit(0.U(log2Ceil(cfg.nMSHRs).W))
mshr_alloc_idx := RegNext(AgePriorityEncoder(mshrs.map(m=>m.io.req_pri_rdy), mshr_head))
when (pri_rdy && pri_val) { mshr_head := WrapInc(mshr_head, cfg.nMSHRs) }
io.meta_write <> meta_write_arb.io.out
io.meta_read <> meta_read_arb.io.out
io.wb_req <> wb_req_arb.io.out
val mmio_alloc_arb = Module(new Arbiter(Bool(), nIOMSHRs))
var mmio_rdy = false.B
val mmios = (0 until nIOMSHRs) map { i =>
val id = cfg.nMSHRs + 1 + i // +1 for wb unit
val mshr = Module(new BoomIOMSHR(id))
mmio_alloc_arb.io.in(i).valid := mshr.io.req.ready
mmio_alloc_arb.io.in(i).bits := DontCare
mshr.io.req.valid := mmio_alloc_arb.io.in(i).ready
mshr.io.req.bits := req.bits
mmio_rdy = mmio_rdy || mshr.io.req.ready
mshr.io.mem_ack.bits := io.mem_grant.bits
mshr.io.mem_ack.valid := io.mem_grant.valid && io.mem_grant.bits.source === id.U
when (io.mem_grant.bits.source === id.U) {
io.mem_grant.ready := true.B
}
resp_arb.io.in(cfg.nMSHRs + i) <> mshr.io.resp
when (!mshr.io.req.ready) {
io.fence_rdy := false.B
}
mshr
}
mmio_alloc_arb.io.out.ready := req.valid && !cacheable
TLArbiter.lowestFromSeq(edge, io.mem_acquire, mshrs.map(_.io.mem_acquire) ++ mmios.map(_.io.mem_access))
TLArbiter.lowestFromSeq(edge, io.mem_finish, mshrs.map(_.io.mem_finish))
val respq = Module(new BranchKillableQueue(new BoomDCacheResp, 4, u => u.uses_ldq, flow = false))
respq.io.brupdate := io.brupdate
respq.io.flush := io.exception
respq.io.enq <> resp_arb.io.out
io.resp <> respq.io.deq
for (w <- 0 until memWidth) {
io.req(w).ready := (w.U === req_idx) &&
Mux(!cacheable, mmio_rdy, sdq_rdy && Mux(idx_match(w), tag_match(w) && sec_rdy, pri_rdy))
io.secondary_miss(w) := idx_match(w) && way_match(w) && !tag_match(w)
io.block_hit(w) := idx_match(w) && tag_match(w)
}
io.refill <> refill_arb.io.out
val free_sdq = io.replay.fire && isWrite(io.replay.bits.uop.mem_cmd)
io.replay <> replay_arb.io.out
io.replay.bits.data := sdq(replay_arb.io.out.bits.sdq_id)
when (io.replay.valid || sdq_enq) {
sdq_val := sdq_val & ~(UIntToOH(replay_arb.io.out.bits.sdq_id) & Fill(cfg.nSDQ, free_sdq)) |
PriorityEncoderOH(~sdq_val(cfg.nSDQ-1,0)) & Fill(cfg.nSDQ, sdq_enq)
}
prefetcher.io.mshr_avail := RegNext(pri_rdy)
prefetcher.io.req_val := RegNext(commit_vals.reduce(_||_))
prefetcher.io.req_addr := RegNext(Mux1H(commit_vals, commit_addrs))
prefetcher.io.req_coh := RegNext(Mux1H(commit_vals, commit_cohs))
} | module lb_16x64(
input [3:0] R0_addr,
input R0_en,
input R0_clk,
output [63:0] R0_data,
input [3:0] W0_addr,
input W0_en,
input W0_clk,
input [63:0] W0_data
);
reg [63:0] Memory[0:15];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 64'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)
{
val queueBits = log2Up(queues)
val entryBits = log2Up(entries)
}
class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle
{
val index = UInt(params.queueBits.W)
val data = Output(params.gen)
}
class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module
{
override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}"
val io = IO(new Bundle {
// push is visible on the same cycle; flow queues
val push = Flipped(Decoupled(new ListBufferPush(params)))
val valid = UInt(params.queues.W)
val pop = Flipped(Valid(UInt(params.queueBits.W)))
val data = Output(params.gen)
})
val valid = RegInit(0.U(params.queues.W))
val head = Mem(params.queues, UInt(params.entryBits.W))
val tail = Mem(params.queues, UInt(params.entryBits.W))
val used = RegInit(0.U(params.entries.W))
val next = Mem(params.entries, UInt(params.entryBits.W))
val data = Mem(params.entries, params.gen)
val freeOH = ~(leftOR(~used) << 1) & ~used
val freeIdx = OHToUInt(freeOH)
val valid_set = WireDefault(0.U(params.queues.W))
val valid_clr = WireDefault(0.U(params.queues.W))
val used_set = WireDefault(0.U(params.entries.W))
val used_clr = WireDefault(0.U(params.entries.W))
val push_tail = tail.read(io.push.bits.index)
val push_valid = valid(io.push.bits.index)
io.push.ready := !used.andR
when (io.push.fire) {
valid_set := UIntToOH(io.push.bits.index, params.queues)
used_set := freeOH
data.write(freeIdx, io.push.bits.data)
when (push_valid) {
next.write(push_tail, freeIdx)
} .otherwise {
head.write(io.push.bits.index, freeIdx)
}
tail.write(io.push.bits.index, freeIdx)
}
val pop_head = head.read(io.pop.bits)
val pop_valid = valid(io.pop.bits)
// Bypass push data to the peek port
io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))
io.valid := (if (!params.bypass) valid else (valid | valid_set))
// It is an error to pop something that is not valid
assert (!io.pop.fire || (io.valid)(io.pop.bits))
when (io.pop.fire) {
used_clr := UIntToOH(pop_head, params.entries)
when (pop_head === tail.read(io.pop.bits)) {
valid_clr := UIntToOH(io.pop.bits, params.queues)
}
head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))
}
// Empty bypass changes no state
when ((!params.bypass).B || !io.pop.valid || pop_valid) {
used := (used & ~used_clr) | used_set
valid := (valid & ~valid_clr) | valid_set
}
} | module tail_21x6(
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [5:0] R0_data,
input [4:0] R1_addr,
input R1_en,
input R1_clk,
output [5:0] R1_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [5:0] W0_data
);
reg [5:0] Memory[0:20];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 6'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 6'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, WrapInc}
import scala.math.min
class BIMMeta(implicit p: Parameters) extends BoomBundle()(p)
with HasBoomFrontendParameters
{
val bims = Vec(bankWidth, UInt(2.W))
}
case class BoomBIMParams(
nSets: Int = 2048
)
class BIMBranchPredictorBank(params: BoomBIMParams = BoomBIMParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
override val nSets = params.nSets
require(isPow2(nSets))
val nWrBypassEntries = 2
def bimWrite(v: UInt, taken: Bool): UInt = {
val old_bim_sat_taken = v === 3.U
val old_bim_sat_ntaken = v === 0.U
Mux(old_bim_sat_taken && taken, 3.U,
Mux(old_bim_sat_ntaken && !taken, 0.U,
Mux(taken, v + 1.U, v - 1.U)))
}
val s2_meta = Wire(new BIMMeta)
override val metaSz = s2_meta.asUInt.getWidth
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nSets).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nSets-1).U) { doing_reset := false.B }
val data = SyncReadMem(nSets, Vec(bankWidth, UInt(2.W)))
val mems = Seq(("bim", nSets, bankWidth * 2))
val s2_req_rdata = RegNext(data.read(s0_idx , s0_valid))
val s2_resp = Wire(Vec(bankWidth, Bool()))
for (w <- 0 until bankWidth) {
s2_resp(w) := s2_valid && s2_req_rdata(w)(1) && !doing_reset
s2_meta.bims(w) := s2_req_rdata(w)
}
val s1_update_wdata = Wire(Vec(bankWidth, UInt(2.W)))
val s1_update_wmask = Wire(Vec(bankWidth, Bool()))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new BIMMeta)
val s1_update_index = s1_update_idx
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nSets).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(2.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_idxs(i) === s1_update_index(log2Ceil(nSets)-1,0)
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
s1_update_wmask(w) := false.B
s1_update_wdata(w) := DontCare
val update_pc = s1_update.bits.pc + (w << 1).U
when (s1_update.bits.br_mask(w) ||
(s1_update.bits.cfi_idx.valid && s1_update.bits.cfi_idx.bits === w.U)) {
val was_taken = (
s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
(
(s1_update.bits.cfi_is_br && s1_update.bits.br_mask(w) && s1_update.bits.cfi_taken) ||
s1_update.bits.cfi_is_jal
)
)
val old_bim_value = Mux(wrbypass_hit, wrbypass(wrbypass_hit_idx)(w), s1_update_meta.bims(w))
s1_update_wmask(w) := true.B
s1_update_wdata(w) := bimWrite(old_bim_value, was_taken)
}
}
when (doing_reset || (s1_update.valid && s1_update.bits.is_commit_update)) {
data.write(
Mux(doing_reset, reset_idx, s1_update_index),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 2.U }), s1_update_wdata),
Mux(doing_reset, (~(0.U(bankWidth.W))), s1_update_wmask.asUInt).asBools
)
}
when (s1_update_wmask.reduce(_||_) && s1_update.valid && s1_update.bits.is_commit_update) {
when (wrbypass_hit) {
wrbypass(wrbypass_hit_idx) := s1_update_wdata
} .otherwise {
wrbypass(wrbypass_enq_idx) := s1_update_wdata
wrbypass_idxs(wrbypass_enq_idx) := s1_update_index
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
for (w <- 0 until bankWidth) {
io.resp.f2(w).taken := s2_resp(w)
io.resp.f3(w).taken := RegNext(io.resp.f2(w).taken)
}
io.f3_meta := RegNext(s2_meta.asUInt)
} | module data(
input [10:0] R0_addr,
input R0_en,
input R0_clk,
output [7:0] R0_data,
input [10:0] W0_addr,
input W0_en,
input W0_clk,
input [7:0] W0_data,
input [3:0] W0_mask
);
data_ext data_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
} | module MulAddRecFNToRaw_postMul_e8_s24(
input io_fromPreMul_isSigNaNAny,
input io_fromPreMul_isNaNAOrB,
input io_fromPreMul_isInfA,
input io_fromPreMul_isZeroA,
input io_fromPreMul_isInfB,
input io_fromPreMul_isZeroB,
input io_fromPreMul_signProd,
input io_fromPreMul_isNaNC,
input io_fromPreMul_isInfC,
input io_fromPreMul_isZeroC,
input [9:0] io_fromPreMul_sExpSum,
input io_fromPreMul_doSubMags,
input io_fromPreMul_CIsDominant,
input [4:0] io_fromPreMul_CDom_CAlignDist,
input [25:0] io_fromPreMul_highAlignedSigC,
input io_fromPreMul_bit0AlignedSigC,
input [48:0] io_mulAddResult,
input [2:0] io_roundingMode,
output io_invalidExc,
output io_rawOut_isNaN,
output io_rawOut_isInf,
output io_rawOut_isZero,
output io_rawOut_sign,
output [9:0] io_rawOut_sExp,
output [26:0] io_rawOut_sig
);
wire roundingMode_min = io_roundingMode == 3'h2;
wire opSignC = io_fromPreMul_signProd ^ io_fromPreMul_doSubMags;
wire [25:0] _sigSum_T_3 = io_mulAddResult[48] ? io_fromPreMul_highAlignedSigC + 26'h1 : io_fromPreMul_highAlignedSigC;
wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags ? ~{_sigSum_T_3, io_mulAddResult[47:24]} : {1'h0, io_fromPreMul_highAlignedSigC[25:24], _sigSum_T_3[23:0], io_mulAddResult[47:25]};
wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist;
wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> ~(io_fromPreMul_CDom_CAlignDist[4:2]));
wire [50:0] notCDom_absSigSum = _sigSum_T_3[2] ? ~{_sigSum_T_3[1:0], io_mulAddResult[47:0], io_fromPreMul_bit0AlignedSigC} : {_sigSum_T_3[1:0], io_mulAddResult[47:0], io_fromPreMul_bit0AlignedSigC} + {50'h0, io_fromPreMul_doSubMags};
wire [4:0] notCDom_normDistReduced2 = notCDom_absSigSum[50] ? 5'h0 : (|(notCDom_absSigSum[49:48])) ? 5'h1 : (|(notCDom_absSigSum[47:46])) ? 5'h2 : (|(notCDom_absSigSum[45:44])) ? 5'h3 : (|(notCDom_absSigSum[43:42])) ? 5'h4 : (|(notCDom_absSigSum[41:40])) ? 5'h5 : (|(notCDom_absSigSum[39:38])) ? 5'h6 : (|(notCDom_absSigSum[37:36])) ? 5'h7 : (|(notCDom_absSigSum[35:34])) ? 5'h8 : (|(notCDom_absSigSum[33:32])) ? 5'h9 : (|(notCDom_absSigSum[31:30])) ? 5'hA : (|(notCDom_absSigSum[29:28])) ? 5'hB : (|(notCDom_absSigSum[27:26])) ? 5'hC : (|(notCDom_absSigSum[25:24])) ? 5'hD : (|(notCDom_absSigSum[23:22])) ? 5'hE : (|(notCDom_absSigSum[21:20])) ? 5'hF : (|(notCDom_absSigSum[19:18])) ? 5'h10 : (|(notCDom_absSigSum[17:16])) ? 5'h11 : (|(notCDom_absSigSum[15:14])) ? 5'h12 : (|(notCDom_absSigSum[13:12])) ? 5'h13 : (|(notCDom_absSigSum[11:10])) ? 5'h14 : (|(notCDom_absSigSum[9:8])) ? 5'h15 : (|(notCDom_absSigSum[7:6])) ? 5'h16 : (|(notCDom_absSigSum[5:4])) ? 5'h17 : {4'hC, ~(|(notCDom_absSigSum[3:2]))};
wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << {108'h0, notCDom_normDistReduced2, 1'h0};
wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> ~(notCDom_normDistReduced2[4:1]));
wire notCDom_completeCancellation = _notCDom_mainSig_T[51:50] == 2'h0;
wire notNaN_isInfProd = io_fromPreMul_isInfA | io_fromPreMul_isInfB;
wire notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC;
wire notNaN_addZeros = (io_fromPreMul_isZeroA | io_fromPreMul_isZeroB) & io_fromPreMul_isZeroC;
assign io_invalidExc = io_fromPreMul_isSigNaNAny | io_fromPreMul_isInfA & io_fromPreMul_isZeroB | io_fromPreMul_isZeroA & io_fromPreMul_isInfB | ~io_fromPreMul_isNaNAOrB & notNaN_isInfProd & io_fromPreMul_isInfC & io_fromPreMul_doSubMags;
assign io_rawOut_isNaN = io_fromPreMul_isNaNAOrB | io_fromPreMul_isNaNC;
assign io_rawOut_isInf = notNaN_isInfOut;
assign io_rawOut_isZero = notNaN_addZeros | ~io_fromPreMul_CIsDominant & notCDom_completeCancellation;
assign io_rawOut_sign = notNaN_isInfProd & io_fromPreMul_signProd | io_fromPreMul_isInfC & opSignC | notNaN_addZeros & io_roundingMode != 3'h2 & io_fromPreMul_signProd & opSignC | notNaN_addZeros & roundingMode_min & (io_fromPreMul_signProd | opSignC) | ~notNaN_isInfOut & ~notNaN_addZeros & (io_fromPreMul_CIsDominant ? opSignC : notCDom_completeCancellation ? roundingMode_min : io_fromPreMul_signProd ^ _sigSum_T_3[2]);
assign io_rawOut_sExp = io_fromPreMul_CIsDominant ? io_fromPreMul_sExpSum - {9'h0, io_fromPreMul_doSubMags} : io_fromPreMul_sExpSum - {4'h0, notCDom_normDistReduced2, 1'h0};
assign io_rawOut_sig = io_fromPreMul_CIsDominant ? {_CDom_mainSig_T[49:24], (|{_CDom_mainSig_T[23:21], {|(CDom_absSigSum[20:17]), |(CDom_absSigSum[16:13]), |(CDom_absSigSum[12:9]), |(CDom_absSigSum[8:5]), |(CDom_absSigSum[4:1]), CDom_absSigSum[0]} & {CDom_reduced4SigExtra_shift[1], CDom_reduced4SigExtra_shift[2], CDom_reduced4SigExtra_shift[3], CDom_reduced4SigExtra_shift[4], CDom_reduced4SigExtra_shift[5], CDom_reduced4SigExtra_shift[6]}}) | (io_fromPreMul_doSubMags ? io_mulAddResult[23:0] != 24'hFFFFFF : (|(io_mulAddResult[24:0])))} : {_notCDom_mainSig_T[51:26], |{_notCDom_mainSig_T[25:23], {|{|(notCDom_absSigSum[23:22]), |(notCDom_absSigSum[21:20])}, |{|(notCDom_absSigSum[19:18]), |(notCDom_absSigSum[17:16])}, |{|(notCDom_absSigSum[15:14]), |(notCDom_absSigSum[13:12])}, |{|(notCDom_absSigSum[11:10]), |(notCDom_absSigSum[9:8])}, |{|(notCDom_absSigSum[7:6]), |(notCDom_absSigSum[5:4])}, |{|(notCDom_absSigSum[3:2]), |(notCDom_absSigSum[1:0])}} & {notCDom_reduced4SigExtra_shift[1], notCDom_reduced4SigExtra_shift[2], notCDom_reduced4SigExtra_shift[3], notCDom_reduced4SigExtra_shift[4], notCDom_reduced4SigExtra_shift[5], notCDom_reduced4SigExtra_shift[6]}}};
endmodule |
Generate the Verilog code corresponding to this Chisel code package sifive.blocks.devices.uart
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
/** UARTRx module recivies serial input from Rx port and transmits them to Rx fifo in parallel
*
* ==Datapass==
* Port(Rx) -> sample -> shifter -> Rx fifo -> TL bus
*
* ==Structure==
* - baud rate divisor counter:
* generate pulse, the enable signal for sample and data shift
* - sample counter:
* sample happens in middle
* - data counter
* control signals for data shift process
* - sample and data shift logic
*
* ==State Machine==
* s_idle: detect start bit, init data_count and sample count, start pulse counter
* s_data: data reciving
*
* @note Rx fifo transmits Rx data to TL bus
*/
class UARTRx(c: UARTParams) extends Module {
val io = IO(new Bundle {
/** enable signal from top */
val en = Input(Bool())
/** input data from rx port */
val in = Input(UInt(1.W))
/** output data to Rx fifo */
val out = Valid(UInt(c.dataBits.W))
/** divisor bits */
val div = Input(UInt(c.divisorBits.W))
/** parity enable */
val enparity = c.includeParity.option(Input(Bool()))
/** parity select
*
* 0 -> even parity
* 1 -> odd parity
*/
val parity = c.includeParity.option(Input(Bool()))
/** parity error bit */
val errorparity = c.includeParity.option(Output(Bool()))
/** databit select
*
* ture -> 8
* false -> 9
*/
val data8or9 = (c.dataBits == 9).option(Input(Bool()))
})
if (c.includeParity)
io.errorparity.get := false.B
val debounce = RegInit(0.U(2.W))
val debounce_max = (debounce === 3.U)
val debounce_min = (debounce === 0.U)
val prescaler = Reg(UInt((c.divisorBits - c.oversample + 1).W))
val start = WireDefault(false.B)
/** enable signal for sampling and data shifting */
val pulse = (prescaler === 0.U)
private val dataCountBits = log2Floor(c.dataBits+c.includeParity.toInt) + 1
/** init = data bits(8 or 9) + parity bit(0 or 1) + start bit(1) */
val data_count = Reg(UInt(dataCountBits.W))
val data_last = (data_count === 0.U)
val parity_bit = (data_count === 1.U) && io.enparity.getOrElse(false.B)
val sample_count = Reg(UInt(c.oversample.W))
val sample_mid = (sample_count === ((c.oversampleFactor - c.nSamples + 1) >> 1).U)
// todo unused
val sample_last = (sample_count === 0.U)
/** counter for data and sample
*
* {{{
* | data_count | sample_count |
* }}}
*/
val countdown = Cat(data_count, sample_count) - 1.U
// Compensate for the divisor not being a multiple of the oversampling period.
// Let remainder k = (io.div % c.oversampleFactor).
// For the last k samples, extend the sampling delay by 1 cycle.
val remainder = io.div(c.oversample-1, 0)
val extend = (sample_count < remainder) // Pad head: (sample_count > ~remainder)
/** prescaler reset signal
*
* conditions:
* {{{
* start : transmisson starts
* pulse : returns ture every pluse counter period
* }}}
*/
val restore = start || pulse
val prescaler_in = Mux(restore, io.div >> c.oversample, prescaler)
val prescaler_next = prescaler_in - Mux(restore && extend, 0.U, 1.U)
/** buffer for sample results */
val sample = Reg(UInt(c.nSamples.W))
// take the majority bit of sample buffer
val voter = Majority(sample.asBools.toSet)
// data buffer
val shifter = Reg(UInt(c.dataBits.W))
val valid = RegInit(false.B)
valid := false.B
io.out.valid := valid
io.out.bits := (if (c.dataBits == 8) shifter else Mux(io.data8or9.get, Cat(0.U, shifter(8,1)), shifter))
val (s_idle :: s_data :: Nil) = Enum(2)
val state = RegInit(s_idle)
switch (state) {
is (s_idle) {
// todo !(!io.in)?
when (!(!io.in) && !debounce_min) {
debounce := debounce - 1.U
}
when (!io.in) {
debounce := debounce + 1.U
when (debounce_max) {
state := s_data
start := true.B
prescaler := prescaler_next
// init data_count
data_count := (c.dataBits+1).U + (if (c.includeParity) io.enparity.get else 0.U) - io.data8or9.getOrElse(false.B).asUInt
// init sample_count = 15
sample_count := (c.oversampleFactor - 1).U
}
}
}
is (s_data) {
prescaler := prescaler_next
when (pulse) {
// sample scan in
sample := Cat(sample, io.in)
data_count := countdown >> c.oversample
sample_count := countdown(c.oversample-1, 0)
when (sample_mid) {
if (c.includeParity) {
// act according to frame bit stage at its respective sampling point
// check parity bit for error
when (parity_bit) {
io.errorparity.get := (shifter.asBools.reduce(_ ^ _) ^ voter ^ io.parity.get)
}
when (data_last) {
state := s_idle
valid := true.B
} .elsewhen (!parity_bit) {
// do not add parity bit to final rx data
shifter := Cat(voter, shifter >> 1)
}
} else {
when (data_last) {
state := s_idle
valid := true.B
} .otherwise {
shifter := Cat(voter, shifter >> 1)
}
}
}
}
}
}
when (!io.en) {
debounce := 0.U
}
}
/*
Copyright 2016 SiFive, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/ | module UARTRx_TestHarness_UNIQUIFIED(
input clock,
input reset,
input io_en,
input io_in,
output io_out_valid,
output [7:0] io_out_bits,
input [15:0] io_div
);
reg [1:0] debounce;
reg [12:0] prescaler;
reg [3:0] data_count;
reg [3:0] sample_count;
reg [2:0] sample;
reg [7:0] shifter;
reg valid;
reg state;
wire [7:0] _countdown_T_1 = {data_count, sample_count} - 8'h1;
wire pulse = prescaler == 13'h0;
wire data_last = data_count == 4'h0;
wire sample_mid = sample_count == 4'h7;
wire _GEN = ~io_in & (&debounce);
wire _GEN_0 = _GEN | state;
wire _GEN_1 = state & pulse;
wire _GEN_2 = state & pulse & sample_mid;
wire restore = ~state & ~io_in & (&debounce) | pulse;
always @(posedge clock) begin
if (reset) begin
debounce <= 2'h0;
valid <= 1'h0;
state <= 1'h0;
end
else begin
if (io_en) begin
if (state) begin
end
else if (io_in) begin
if (io_in & (|debounce))
debounce <= debounce - 2'h1;
end
else
debounce <= debounce + 2'h1;
end
else
debounce <= 2'h0;
valid <= _GEN_2 & data_last;
if (state)
state <= ~(state & pulse & sample_mid & data_last) & state;
else
state <= _GEN_0;
end
if (_GEN_0)
prescaler <= (restore ? {1'h0, io_div[15:4]} : prescaler) - {12'h0, ~(restore & sample_count < io_div[3:0])};
if (state) begin
if (_GEN_1) begin
data_count <= _countdown_T_1[7:4];
sample_count <= _countdown_T_1[3:0];
end
end
else if (_GEN) begin
data_count <= 4'h9;
sample_count <= 4'hF;
end
if (_GEN_1)
sample <= {sample[1:0], io_in};
if (~state | ~_GEN_2 | data_last) begin
end
else
shifter <= {sample[0] & sample[1] | sample[0] & sample[2] | sample[1] & sample[2], shifter[7:1]};
end
assign io_out_valid = valid;
assign io_out_bits = shifter;
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
trait TLFieldHelper {
def getBodyFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleC => Seq( b.data, b.corrupt)
case b: TLBundleD => Seq( b.data, b.corrupt)
case b: TLBundleE => Seq()
}
def getConstFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )
case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)
case b: TLBundleE => Seq( b.sink )
}
def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max
def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max
def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))
}
class TLBeat(val beatWidth: Int) extends Bundle {
val payload = UInt(beatWidth.W)
val head = Bool()
val tail = Bool()
}
abstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Flipped(Decoupled(gen))
val beat = Decoupled(new TLBeat(beatWidth))
})
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
// convert decoupled to irrevocable
val q = Module(new Queue(gen, 1, pipe=true, flow=true))
q.io.enq <> io.protocol
val protocol = q.io.deq
val has_body = Wire(Bool())
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val head = edge.first(protocol.bits, protocol.fire)
val tail = edge.last(protocol.bits, protocol.fire)
val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))
val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))
val is_body = RegInit(false.B)
io.beat.valid := protocol.valid
protocol.ready := io.beat.ready && (is_body || !has_body)
io.beat.bits.head := head && !is_body
io.beat.bits.tail := tail && (is_body || !has_body)
io.beat.bits.payload := Mux(is_body, body, const)
when (io.beat.fire && io.beat.bits.head) { is_body := true.B }
when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }
}
abstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Decoupled(gen)
val beat = Flipped(Decoupled(new TLBeat(beatWidth)))
})
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
val protocol = Wire(Decoupled(gen))
io.protocol <> protocol
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val is_const = RegInit(true.B)
val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))
val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)
io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready
protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid
def assign(i: UInt, sigs: Seq[Data]) = {
var t = i
for (s <- sigs.reverse) {
s := t.asTypeOf(s.cloneType)
t = t >> s.getWidth
}
}
assign(const, const_fields)
assign(io.beat.bits.payload, body_fields)
when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }
when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }
}
class TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)
class TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits)
}
class TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)
class TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p) | module TLAFromBeat_serial_tl_0_a64d64s8k8z8c(
input clock,
input reset,
input io_protocol_ready,
output io_protocol_valid,
output [2:0] io_protocol_bits_opcode,
output [2:0] io_protocol_bits_param,
output [7:0] io_protocol_bits_size,
output [7:0] io_protocol_bits_source,
output [63:0] io_protocol_bits_address,
output [7:0] io_protocol_bits_mask,
output [63:0] io_protocol_bits_data,
output io_protocol_bits_corrupt,
output io_beat_ready,
input io_beat_valid,
input [85:0] io_beat_bits_payload,
input io_beat_bits_head,
input io_beat_bits_tail
);
reg is_const;
reg [85:0] const_reg;
wire [85:0] const_0 = io_beat_bits_head ? io_beat_bits_payload : const_reg;
wire io_beat_ready_0 = is_const & ~io_beat_bits_tail | io_protocol_ready;
wire _GEN = io_beat_ready_0 & io_beat_valid;
wire _GEN_0 = _GEN & io_beat_bits_head;
always @(posedge clock) begin
if (reset)
is_const <= 1'h1;
else
is_const <= _GEN & io_beat_bits_tail | ~_GEN_0 & is_const;
if (_GEN_0)
const_reg <= io_beat_bits_payload;
end
assign io_protocol_valid = (~is_const | io_beat_bits_tail) & io_beat_valid;
assign io_protocol_bits_opcode = const_0[85:83];
assign io_protocol_bits_param = const_0[82:80];
assign io_protocol_bits_size = const_0[79:72];
assign io_protocol_bits_source = const_0[71:64];
assign io_protocol_bits_address = const_0[63:0];
assign io_protocol_bits_mask = io_beat_bits_head ? 8'hFF : io_beat_bits_payload[72:65];
assign io_protocol_bits_data = io_beat_bits_payload[64:1];
assign io_protocol_bits_corrupt = io_beat_bits_payload[0];
assign io_beat_ready = io_beat_ready_0;
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
trait TLFieldHelper {
def getBodyFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleC => Seq( b.data, b.corrupt)
case b: TLBundleD => Seq( b.data, b.corrupt)
case b: TLBundleE => Seq()
}
def getConstFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )
case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)
case b: TLBundleE => Seq( b.sink )
}
def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max
def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max
def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))
}
class TLBeat(val beatWidth: Int) extends Bundle {
val payload = UInt(beatWidth.W)
val head = Bool()
val tail = Bool()
}
abstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Flipped(Decoupled(gen))
val beat = Decoupled(new TLBeat(beatWidth))
})
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
// convert decoupled to irrevocable
val q = Module(new Queue(gen, 1, pipe=true, flow=true))
q.io.enq <> io.protocol
val protocol = q.io.deq
val has_body = Wire(Bool())
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val head = edge.first(protocol.bits, protocol.fire)
val tail = edge.last(protocol.bits, protocol.fire)
val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))
val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))
val is_body = RegInit(false.B)
io.beat.valid := protocol.valid
protocol.ready := io.beat.ready && (is_body || !has_body)
io.beat.bits.head := head && !is_body
io.beat.bits.tail := tail && (is_body || !has_body)
io.beat.bits.payload := Mux(is_body, body, const)
when (io.beat.fire && io.beat.bits.head) { is_body := true.B }
when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }
}
abstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Decoupled(gen)
val beat = Flipped(Decoupled(new TLBeat(beatWidth)))
})
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
val protocol = Wire(Decoupled(gen))
io.protocol <> protocol
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val is_const = RegInit(true.B)
val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))
val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)
io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready
protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid
def assign(i: UInt, sigs: Seq[Data]) = {
var t = i
for (s <- sigs.reverse) {
s := t.asTypeOf(s.cloneType)
t = t >> s.getWidth
}
}
assign(const, const_fields)
assign(io.beat.bits.payload, body_fields)
when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }
when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }
}
class TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)
class TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits)
}
class TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)
class TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p) | module TLDFromBeat_serial_tl_0_a64d64s8k8z8c(
input clock,
input reset,
output io_beat_ready,
input io_beat_valid,
input io_beat_bits_head,
input io_beat_bits_tail
);
reg is_const;
wire io_beat_ready_0 = is_const & ~io_beat_bits_tail;
wire _GEN = io_beat_ready_0 & io_beat_valid;
always @(posedge clock) begin
if (reset)
is_const <= 1'h1;
else
is_const <= _GEN & io_beat_bits_tail | ~(_GEN & io_beat_bits_head) & is_const;
end
assign io_beat_ready = io_beat_ready_0;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
} | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24(
input io_in_isZero,
input io_in_sign,
input [8:0] io_in_sExp,
input [64:0] io_in_sig,
input [2:0] io_roundingMode,
output [32:0] io_out,
output [4:0] io_exceptionFlags
);
wire roundingMode_near_even = io_roundingMode == 3'h0;
wire [1:0] _GEN = {io_in_sig[39], |(io_in_sig[38:0])};
wire [25:0] roundedSig = (roundingMode_near_even | io_roundingMode == 3'h4) & io_in_sig[39] | (io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign) & (|_GEN) ? {1'h0, io_in_sig[64:40]} + 26'h1 & {25'h1FFFFFF, ~(roundingMode_near_even & io_in_sig[39] & ~(|(io_in_sig[38:0])))} : {1'h0, io_in_sig[64:41], io_in_sig[40] | io_roundingMode == 3'h6 & (|_GEN)};
assign io_out = {io_in_sign, io_in_sExp + {7'h0, roundedSig[25:24]} + 9'h80 & ~(io_in_isZero ? 9'h1C0 : 9'h0), io_in_isZero ? 23'h0 : roundedSig[22:0]};
assign io_exceptionFlags = {4'h0, ~io_in_isZero & (|_GEN)};
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
case class FPUParams(
minFLen: Int = 32,
fLen: Int = 64,
divSqrt: Boolean = true,
sfmaLatency: Int = 3,
dfmaLatency: Int = 4,
fpmuLatency: Int = 2,
ifpuLatency: Int = 2
)
object FPConstants
{
val RM_SZ = 3
val FLAGS_SZ = 5
}
trait HasFPUCtrlSigs {
val ldst = Bool()
val wen = Bool()
val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val swap12 = Bool()
val swap23 = Bool()
val typeTagIn = UInt(2.W)
val typeTagOut = UInt(2.W)
val fromint = Bool()
val toint = Bool()
val fastpipe = Bool()
val fma = Bool()
val div = Bool()
val sqrt = Bool()
val wflags = Bool()
val vec = Bool()
}
class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val inst = Input(Bits(32.W))
val sigs = Output(new FPUCtrlSigs())
})
private val X2 = BitPat.dontCare(2)
val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)
val h: Array[(BitPat, List[BitPat])] =
Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),
FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),
FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),
FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),
FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),
FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),
FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),
FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))
val f: Array[(BitPat, List[BitPat])] =
Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),
FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),
FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),
FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),
FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),
FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))
val d: Array[(BitPat, List[BitPat])] =
Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),
FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),
FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),
FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),
FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),
FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),
FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),
FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))
val fcvt_hd: Array[(BitPat, List[BitPat])] =
Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),
FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))
val vfmv_f_s: Array[(BitPat, List[BitPat])] =
Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))
val insns = ((minFLen, fLen) match {
case (32, 32) => f
case (16, 32) => h ++ f
case (32, 64) => f ++ d
case (16, 64) => h ++ f ++ d ++ fcvt_hd
case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration")
}) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())
val decoder = DecodeLogic(io.inst, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,
s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)
sigs zip decoder map {case(s,d) => s := d}
}
class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val time = Input(UInt(xLen.W))
val inst = Input(Bits(32.W))
val fromint_data = Input(Bits(xLen.W))
val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))
val v_sew = Input(UInt(3.W))
val store_data = Output(Bits(fLen.W))
val toint_data = Output(Bits(xLen.W))
val ll_resp_val = Input(Bool())
val ll_resp_type = Input(Bits(3.W))
val ll_resp_tag = Input(UInt(5.W))
val ll_resp_data = Input(Bits(fLen.W))
val valid = Input(Bool())
val fcsr_rdy = Output(Bool())
val nack_mem = Output(Bool())
val illegal_rm = Output(Bool())
val killx = Input(Bool())
val killm = Input(Bool())
val dec = Output(new FPUCtrlSigs())
val sboard_set = Output(Bool())
val sboard_clr = Output(Bool())
val sboard_clra = Output(UInt(5.W))
val keep_clock_enabled = Input(Bool())
}
class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs
val cp_resp = Decoupled(new FPResult())
}
class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
val data = Bits((fLen+1).W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val typ = Bits(2.W)
val in1 = Bits(xLen.W)
}
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val fmaCmd = Bits(2.W)
val typ = Bits(2.W)
val fmt = Bits(2.W)
val in1 = Bits((fLen+1).W)
val in2 = Bits((fLen+1).W)
val in3 = Bits((fLen+1).W)
}
case class FType(exp: Int, sig: Int) {
def ieeeWidth = exp + sig
def recodedWidth = ieeeWidth + 1
def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)
def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)
def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR
def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)
def classify(x: UInt) = {
val sign = x(sig + exp)
val code = x(exp + sig - 1, exp + sig - 3)
val codeHi = code(2, 1)
val isSpecial = codeHi === 3.U
val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U
val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn
val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U
val isZero = code === 0.U
val isInf = isSpecial && !code(0)
val isNaN = code.andR
val isSNaN = isNaN && !x(sig-2)
val isQNaN = isNaN && x(sig-2)
Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,
isSubnormal && !sign, isZero && !sign, isZero && sign,
isSubnormal && sign, isNormal && sign, isInf && sign)
}
// convert between formats, ignoring rounding, range, NaN
def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {
val sign = x(sig + exp)
val fractIn = x(sig - 2, 0)
val expIn = x(sig + exp - 1, sig - 1)
val fractOut = fractIn << to.sig >> sig
val expOut = {
val expCode = expIn(exp, exp - 2)
val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U
Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))
}
Cat(sign, expOut, fractOut)
}
private def ieeeBundle = {
val expWidth = exp
class IEEEBundle extends Bundle {
val sign = Bool()
val exp = UInt(expWidth.W)
val sig = UInt((ieeeWidth-expWidth-1).W)
}
new IEEEBundle
}
def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)
def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)
def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)
}
object FType {
val H = new FType(5, 11)
val S = new FType(8, 24)
val D = new FType(11, 53)
val all = List(H, S, D)
}
trait HasFPUParameters {
require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))
val minFLen: Int
val fLen: Int
def xLen: Int
val minXLen = 32
val nIntTypes = log2Ceil(xLen/minXLen) + 1
def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)
def minType = floatTypes.head
def maxType = floatTypes.last
def prevType(t: FType) = floatTypes(typeTag(t) - 1)
def maxExpWidth = maxType.exp
def maxSigWidth = maxType.sig
def typeTag(t: FType) = floatTypes.indexOf(t)
def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U
def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U
// typeTag
def H = typeTagGroup(FType.H)
def S = typeTagGroup(FType.S)
def D = typeTagGroup(FType.D)
def I = typeTag(maxType).U
private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR
private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {
require(xt.ieeeWidth == 2 * yt.ieeeWidth)
val swizzledNaN = Cat(
x(xt.sig + xt.exp, xt.sig + xt.exp - 3),
x(xt.sig - 2, yt.recodedWidth - 1).andR,
x(xt.sig + xt.exp - 5, xt.sig),
y(yt.recodedWidth - 2),
x(xt.sig - 2, yt.recodedWidth - 1),
y(yt.recodedWidth - 1),
y(yt.recodedWidth - 3, 0))
Mux(xt.isNaN(x), swizzledNaN, x)
}
// implement NaN unboxing for FU inputs
def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {
val outType = exactType.getOrElse(maxType)
def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {
val prev =
if (t == minType) {
Seq()
} else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prev = helper(unswizzled, prevT)
val isbox = isBox(x, t)
prev.map(p => (isbox && p._1, p._2))
}
prev :+ (true.B, t.unsafeConvert(x, outType))
}
val (oks, floats) = helper(x, maxType).unzip
if (exactType.isEmpty || floatTypes.size == 1) {
Mux(oks(tag), floats(tag), maxType.qNaN)
} else {
val t = exactType.get
floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)
}
}
// make sure that the redundant bits in the NaN-boxed encoding are consistent
def consistent(x: UInt): Bool = {
def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prevOK = !isBox(x, t) || helper(unswizzled, prevT)
val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR
prevOK && curOK
}
helper(x, maxType)
}
// generate a NaN box from an FU result
def box(x: UInt, t: FType): UInt = {
if (t == maxType) {
x
} else {
val nt = floatTypes(typeTag(t) + 1)
val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)
bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U
}
}
// generate a NaN box from an FU result
def box(x: UInt, tag: UInt): UInt = {
val opts = floatTypes.map(t => box(x, t))
opts(tag)
}
// zap bits that hardfloat thinks are don't-cares, but we do care about
def sanitizeNaN(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
x
} else {
val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)
Mux(t.isNaN(x), maskedNaN, x)
}
}
// implement NaN boxing and recoding for FL*/fmv.*.x
def recode(x: UInt, tag: UInt): UInt = {
def helper(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
t.recode(x)
} else {
val prevT = prevType(t)
box(t.recode(x), t, helper(x, prevT), prevT)
}
}
// fill MSBs of subword loads to emulate a wider load of a NaN-boxed value
val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)
helper(boxes(tag) | x, maxType)
}
// implement NaN unboxing and un-recoding for FS*/fmv.x.*
def ieee(x: UInt, t: FType = maxType): UInt = {
if (typeTag(t) == 0) {
t.ieee(x)
} else {
val unrecoded = t.ieee(x)
val prevT = prevType(t)
val prevRecoded = Cat(
x(prevT.recodedWidth-2),
x(t.sig-1),
x(prevT.recodedWidth-3, 0))
val prevUnrecoded = ieee(prevRecoded, prevT)
Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))
}
}
}
abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
class Output extends Bundle {
val in = new FPInput
val lt = Bool()
val store = Bits(fLen.W)
val toint = Bits(xLen.W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new Output)
})
val in = RegEnable(io.in.bits, io.in.valid)
val valid = RegNext(io.in.valid)
val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
dcmp.io.a := in.in1
dcmp.io.b := in.in2
dcmp.io.signaling := !in.rm(1)
val tag = in.typeTagOut
val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))
else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
val toint = WireDefault(toint_ieee)
val intType = WireDefault(in.fmt(0))
io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
io.out.bits.exc := 0.U
when (in.rm(0)) {
val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)
toint := classify_out | (toint_ieee >> minXLen << minXLen)
intType := false.B
}
when (in.wflags) { // feq/flt/fle, fcvt
toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)
io.out.bits.exc := dcmp.io.exceptionFlags
intType := false.B
when (!in.ren2) { // fcvt
val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
intType := cvtType
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
conv.io.in := in.in1
conv.io.roundingMode := in.rm
conv.io.signedOut := ~in.typ(0)
toint := conv.io.out
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))
for (i <- 0 until nIntTypes-1) {
val w = minXLen << i
when (cvtType === i.U) {
val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))
narrow.io.in := in.in1
narrow.io.roundingMode := in.rm
narrow.io.signedOut := ~in.typ(0)
val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)
val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))
val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)
when (invalid) { toint := Cat(conv.io.out >> w, excOut) }
io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))
}
}
}
}
io.out.valid := valid
io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)
io.out.bits.in := in
}
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new IntToFPInput))
val out = Valid(new FPResult)
})
val in = Pipe(io.in)
val tag = in.bits.typeTagIn
val mux = Wire(new FPResult)
mux.exc := 0.U
mux.data := recode(in.bits.in1, tag)
val intValue = {
val res = WireDefault(in.bits.in1.asSInt)
for (i <- 0 until nIntTypes-1) {
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
}
}
res.asUInt
}
when (in.bits.wflags) { // fcvt
// could be improved for RVD/RVQ with a single variable-position rounding
// unit, rather than N fixed-position ones
val i2fResults = for (t <- floatTypes) yield {
val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
i2f.io.signedIn := ~in.bits.typ(0)
i2f.io.in := intValue
i2f.io.roundingMode := in.bits.rm
i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding
(sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)
}
val (data, exc) = i2fResults.unzip
val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
mux.data := dataPadded(tag)
mux.exc := exc(tag)
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
val lt = Input(Bool()) // from FPToInt
})
val in = Pipe(io.in)
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
val fsgnjMux = Wire(new FPResult)
fsgnjMux.exc := 0.U
fsgnjMux.data := fsgnj
when (in.bits.wflags) { // fmin/fmax
val isnan1 = maxType.isNaN(in.bits.in1)
val isnan2 = maxType.isNaN(in.bits.in2)
val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)
val isNaNOut = isnan1 && isnan2
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
fsgnjMux.exc := isInvalid << 4
fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
}
val inTag = in.bits.typeTagIn
val outTag = in.bits.typeTagOut
val mux = WireDefault(fsgnjMux)
for (t <- floatTypes.init) {
when (outTag === typeTag(t).U) {
mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))
}
}
when (in.bits.wflags && !in.bits.ren2) { // fcvt
if (floatTypes.size > 1) {
// widening conversions simply canonicalize NaN operands
val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)
fsgnjMux.data := widened
fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4
// narrowing conversions require rounding (for RVQ, this could be
// optimized to use a single variable-position rounding unit, rather
// than two fixed-position ones)
for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {
val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
narrower.io.in := in.bits.in1
narrower.io.roundingMode := in.bits.rm
narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding
val narrowed = sanitizeNaN(narrower.io.out, outType)
mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)
mux.exc := narrower.io.exceptionFlags
}
}
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
{
override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}"
require(latency<=2)
val io = IO(new Bundle {
val validin = Input(Bool())
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
val validout = Output(Bool())
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
val valid_stage0 = Wire(Bool())
val roundingMode_stage0 = Wire(UInt(3.W))
val detectTininess_stage0 = Wire(UInt(1.W))
val postmul_regs = if(latency>0) 1 else 0
mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits
detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits
valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
val round_regs = if(latency==2) 1 else 0
roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
io.validout := Pipe(valid_stage0, false.B, round_regs).valid
roundRawFNToRecFN.io.infiniteExc := false.B
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
class FPUFMAPipe(val latency: Int, val t: FType)
(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
require(latency>0)
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
})
val valid = RegNext(io.in.valid)
val in = Reg(new FPInput)
when (io.in.valid) {
val one = 1.U << (t.sig + t.exp - 1)
val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))
val cmd_fma = io.in.bits.ren3
val cmd_addsub = io.in.bits.swap23
in := io.in.bits
when (cmd_addsub) { in.in2 := one }
when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
}
val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
fma.io.validin := valid
fma.io.op := in.fmaCmd
fma.io.roundingMode := in.rm
fma.io.detectTininess := hardfloat.consts.tininess_afterRounding
fma.io.a := in.in1
fma.io.b := in.in2
fma.io.c := in.in3
val res = Wire(new FPResult)
res.data := sanitizeNaN(fma.io.out, t)
res.exc := fma.io.exceptionFlags
io.out := Pipe(fma.io.validout, res, (latency-3) max 0)
}
class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new FPUIO)
val (useClockGating, useDebugROB) = coreParams match {
case r: RocketCoreParams =>
val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1
(r.clockGate, sz < 1)
case _ => (false, false)
}
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cp_req.valid
val gated_clock =
if (!useClockGating) clock
else ClockGate(clock, clock_en, "fpu_clock_gate")
val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.inst
val id_ctrl = WireInit(fp_decoder.io.sigs)
coreParams match { case r: RocketCoreParams => r.vector.map(v => {
val v_decode = v.decoder(p) // Only need to get ren1
v_decode.io.inst := io.inst
v_decode.io.vconfig := DontCare // core deals with this
when (v_decode.io.legal && v_decode.io.read_frs1) {
id_ctrl.ren1 := true.B
id_ctrl.swap12 := false.B
id_ctrl.toint := true.B
id_ctrl.typeTagIn := I
id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)
}
when (v_decode.io.write_frd) { id_ctrl.wen := true.B }
})}
val ex_reg_valid = RegNext(io.valid, false.B)
val ex_reg_inst = RegEnable(io.inst, io.valid)
val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
val ex_ra = List.fill(3)(Reg(UInt()))
// load/vector response
val load_wb = RegNext(io.ll_resp_val)
val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)
val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)
val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)
class FPUImpl { // entering gated-clock domain
val req_valid = ex_reg_valid || io.cp_req.valid
val ex_cp_valid = io.cp_req.fire
val mem_cp_valid = RegNext(ex_cp_valid, false.B)
val wb_cp_valid = RegNext(mem_cp_valid, false.B)
val mem_reg_valid = RegInit(false.B)
val killm = (io.killm || io.nack_mem) && !mem_cp_valid
// Kill X-stage instruction if M-stage is killed. This prevents it from
// speculatively being sent to the div-sqrt unit, which can cause priority
// inversion for two back-to-back divides, the first of which is killed.
val killx = io.killx || mem_reg_valid && killm
mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid
val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
val cp_ctrl = Wire(new FPUCtrlSigs)
cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
io.cp_resp.valid := false.B
io.cp_resp.bits.data := 0.U
io.cp_resp.bits.exc := DontCare
val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)
val mem_ctrl = RegEnable(ex_ctrl, req_valid)
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
// CoreMonitorBundle to monitor fp register file writes
val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))
frfWriteBundle.foreach { i =>
i.clock := clock
i.reset := reset
i.hartid := io.hartid
i.timer := io.time(31,0)
i.valid := false.B
i.wrenx := false.B
i.wrenf := false.B
i.excpt := false.B
}
// regfile
val regfile = Mem(32, Bits((fLen+1).W))
when (load_wb) {
val wdata = recode(load_wb_data, load_wb_typeTag)
regfile(load_wb_tag) := wdata
assert(consistent(wdata))
if (enableCommitLog)
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))
if (useDebugROB)
DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))
frfWriteBundle(0).wrdst := load_wb_tag
frfWriteBundle(0).wrenf := true.B
frfWriteBundle(0).wrdata := ieee(wdata)
}
val ex_rs = ex_ra.map(a => regfile(a))
when (io.valid) {
when (id_ctrl.ren1) {
when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }
when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }
}
when (id_ctrl.ren2) {
when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }
when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }
when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }
}
when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }
}
val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))
def fuInput(minT: Option[FType]): FPInput = {
val req = Wire(new FPInput)
val tag = ex_ctrl.typeTagIn
req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
req.rm := ex_rm
req.in1 := unbox(ex_rs(0), tag, minT)
req.in2 := unbox(ex_rs(1), tag, minT)
req.in3 := unbox(ex_rs(2), tag, minT)
req.typ := ex_reg_inst(21,20)
req.fmt := ex_reg_inst(26,25)
req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))
when (ex_cp_valid) {
req := io.cp_req.bits
when (io.cp_req.bits.swap12) {
req.in1 := io.cp_req.bits.in2
req.in2 := io.cp_req.bits.in1
}
when (io.cp_req.bits.swap23) {
req.in2 := io.cp_req.bits.in3
req.in3 := io.cp_req.bits.in2
}
}
req
}
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new FPToInt)
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
io.store_data := fpiu.io.out.bits.store
io.toint_data := fpiu.io.out.bits.toint
when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){
io.cp_resp.bits.data := fpiu.io.out.bits.toint
io.cp_resp.valid := true.B
}
val ifpu = Module(new IntToFP(cfg.ifpuLatency))
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
ifpu.io.in.bits := fpiu.io.in.bits
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
val fpmu = Module(new FPToFP(cfg.fpmuLatency))
fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val divSqrt_wen = WireDefault(false.B)
val divSqrt_inFlight = WireDefault(false.B)
val divSqrt_waddr = Reg(UInt(5.W))
val divSqrt_cp = Reg(Bool())
val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
val divSqrt_wdata = Wire(UInt((fLen+1).W))
val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
divSqrt_typeTag := DontCare
divSqrt_wdata := DontCare
divSqrt_flags := DontCare
// writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++
(fLen > 32).option({
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D
dfma.io.in.bits := fuInput(Some(dfma.t))
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)
}) ++
(minFLen == 16).option({
val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))
hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H
hfma.io.in.bits := fuInput(Some(hfma.t))
Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)
})
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
require(pipes.forall(_.lat >= offset))
pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)
}
def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)
val maxLatency = pipes.map(_.lat).max
val memLatencyMask = latencyMask(mem_ctrl, 2)
class WBInfo extends Bundle {
val rd = UInt(5.W)
val typeTag = UInt(log2Up(floatTypes.size).W)
val cp = Bool()
val pipeid = UInt(log2Ceil(pipes.size).W)
}
val wen = RegInit(0.U((maxLatency-1).W))
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback")
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
}
wen := wen >> 1
when (mem_wen) {
when (!killm) {
wen := wen >> 1 | memLatencyMask
}
for (i <- 0 until maxLatency-1) {
when (!write_port_busy && memLatencyMask(i)) {
wbInfo(i).cp := mem_cp_valid
wbInfo(i).typeTag := mem_ctrl.typeTagOut
wbInfo(i).pipeid := pipeid(mem_ctrl)
wbInfo(i).rd := mem_reg_inst(11,7)
}
}
}
val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)
val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
assert(consistent(wdata))
regfile(waddr) := wdata
if (enableCommitLog) {
printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata))
}
frfWriteBundle(1).wrdst := waddr
frfWriteBundle(1).wrenf := true.B
frfWriteBundle(1).wrdata := ieee(wdata)
}
if (useDebugROB) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
}
when (wb_cp && (wen(0) || divSqrt_wen)) {
io.cp_resp.bits.data := wdata
io.cp_resp.valid := true.B
}
assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,
s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}")
// Avoid structural hazards and nacking of external requests
// toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs
io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)
io.fcsr_flags.bits :=
Mux(wb_toint_valid, wb_toint_exc, 0.U) |
Mux(divSqrt_wen, divSqrt_flags, 0.U) |
Mux(wen(0), wexc, 0.U)
val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid
io.dec <> id_ctrl
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)
io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))
io.sboard_clra := waddr
ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
// we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U
if (cfg.divSqrt) {
val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)
when (divSqrt_inValid) {
divSqrt_waddr := mem_reg_inst(11,7)
divSqrt_cp := mem_cp_valid
}
ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")
ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard")
ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback")
for (t <- floatTypes) {
val tag = mem_ctrl.typeTagOut
val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }
divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)
divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm
divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding
when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight
when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {
divSqrt_wen := !divSqrt_killed
divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)
divSqrt_flags := divSqrt.io.exceptionFlags
divSqrt_typeTag := typeTag(t).U
}
}
when (divSqrt_killed) { divSqrt_inFlight := false.B }
} else {
when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }
}
// gate the clock
clock_en_reg := !useClockGating.B ||
io.keep_clock_enabled || // chicken bit
io.valid || // ID stage
req_valid || // EX stage
mem_reg_valid || mem_cp_valid || // MEM stage
wb_reg_valid || wb_cp_valid || // WB stage
wen.orR || divSqrt_inFlight || // post-WB stage
io.ll_resp_val // load writeback
} // leaving gated-clock domain
val fpuImpl = withClock (gated_clock) { new FPUImpl }
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FPU_$label", "Core;;" + desc)
} | module FPUDecoder(
input [31:0] io_inst,
output io_sigs_wen,
output io_sigs_ren1,
output io_sigs_ren2,
output io_sigs_ren3,
output io_sigs_swap12,
output io_sigs_swap23,
output [1:0] io_sigs_typeTagIn,
output [1:0] io_sigs_typeTagOut,
output io_sigs_fromint,
output io_sigs_toint,
output io_sigs_fastpipe,
output io_sigs_fma,
output io_sigs_div,
output io_sigs_sqrt,
output io_sigs_wflags,
output io_sigs_vec
);
wire [29:0] decoder_decoded_invInputs = ~(io_inst[31:2]);
wire [4:0] _decoder_decoded_andMatrixOutputs_T = {io_inst[0], io_inst[1], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], io_inst[6]};
wire [6:0] _decoder_decoded_andMatrixOutputs_T_1 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24]};
wire [10:0] _decoder_decoded_andMatrixOutputs_T_2 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[23], decoder_decoded_invInputs[27], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};
wire [10:0] _decoder_decoded_andMatrixOutputs_T_3 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[24], decoder_decoded_invInputs[27], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};
wire [11:0] _decoder_decoded_andMatrixOutputs_T_4 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[27], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};
wire [11:0] _decoder_decoded_andMatrixOutputs_T_7 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[23], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};
wire [11:0] _decoder_decoded_andMatrixOutputs_T_8 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[24], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};
wire [8:0] _decoder_decoded_andMatrixOutputs_T_11 = {io_inst[0], io_inst[1], io_inst[2], decoder_decoded_invInputs[1], decoder_decoded_invInputs[2], io_inst[5], decoder_decoded_invInputs[4], io_inst[12], decoder_decoded_invInputs[12]};
wire [8:0] _decoder_decoded_andMatrixOutputs_T_14 = {io_inst[0], io_inst[1], io_inst[2], decoder_decoded_invInputs[1], decoder_decoded_invInputs[2], io_inst[5], decoder_decoded_invInputs[4], io_inst[13], decoder_decoded_invInputs[12]};
wire [6:0] _decoder_decoded_andMatrixOutputs_T_17 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], io_inst[6], io_inst[25], decoder_decoded_invInputs[24]};
wire [11:0] _decoder_decoded_andMatrixOutputs_T_18 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[27], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};
wire [13:0] _decoder_decoded_andMatrixOutputs_T_21 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[12], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28]};
wire [13:0] _decoder_decoded_andMatrixOutputs_T_22 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28]};
wire [13:0] _decoder_decoded_andMatrixOutputs_T_23 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[12], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28]};
wire [13:0] _decoder_decoded_andMatrixOutputs_T_24 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28]};
wire [14:0] _decoder_decoded_andMatrixOutputs_T_25 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[12], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28]};
wire [14:0] _decoder_decoded_andMatrixOutputs_T_26 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28]};
wire [13:0] _decoder_decoded_andMatrixOutputs_T_27 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[23], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};
wire [13:0] _decoder_decoded_andMatrixOutputs_T_28 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[24], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};
wire [14:0] _decoder_decoded_andMatrixOutputs_T_29 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};
wire [14:0] _decoder_decoded_andMatrixOutputs_T_30 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[12], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};
wire [14:0] _decoder_decoded_andMatrixOutputs_T_31 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[12], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};
wire [14:0] _decoder_decoded_andMatrixOutputs_T_32 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[12], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28]};
wire [14:0] _decoder_decoded_andMatrixOutputs_T_33 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28]};
wire [14:0] _decoder_decoded_andMatrixOutputs_T_34 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};
wire [16:0] _decoder_decoded_andMatrixOutputs_T_37 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], io_inst[20], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30]};
wire [17:0] _decoder_decoded_andMatrixOutputs_T_38 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], io_inst[20], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]};
wire [16:0] _decoder_decoded_andMatrixOutputs_T_40 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], io_inst[21], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30]};
wire [17:0] _decoder_decoded_andMatrixOutputs_T_41 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], io_inst[21], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]};
wire [16:0] _decoder_decoded_andMatrixOutputs_T_43 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30]};
wire [17:0] _decoder_decoded_andMatrixOutputs_T_44 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]};
wire [16:0] _decoder_decoded_andMatrixOutputs_T_46 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], io_inst[26], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30]};
wire [17:0] _decoder_decoded_andMatrixOutputs_T_47 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], io_inst[26], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]};
wire [17:0] _decoder_decoded_andMatrixOutputs_T_49 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], io_inst[27], io_inst[28], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]};
wire [17:0] _decoder_decoded_andMatrixOutputs_T_50 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[24], io_inst[27], io_inst[28], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]};
wire [18:0] _decoder_decoded_andMatrixOutputs_T_51 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], io_inst[27], io_inst[28], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]};
wire [18:0] _decoder_decoded_andMatrixOutputs_T_52 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], io_inst[25], decoder_decoded_invInputs[24], io_inst[27], io_inst[28], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]};
wire [14:0] _decoder_decoded_andMatrixOutputs_T_53 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[12], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], io_inst[31]};
wire [14:0] _decoder_decoded_andMatrixOutputs_T_54 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], io_inst[31]};
wire [14:0] _decoder_decoded_andMatrixOutputs_T_55 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[12], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], io_inst[31]};
wire [14:0] _decoder_decoded_andMatrixOutputs_T_56 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], io_inst[31]};
wire [15:0] _decoder_decoded_andMatrixOutputs_T_60 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30], io_inst[31]};
wire [15:0] _decoder_decoded_andMatrixOutputs_T_61 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30], io_inst[31]};
wire [15:0] _decoder_decoded_andMatrixOutputs_T_63 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], io_inst[28], decoder_decoded_invInputs[27], io_inst[30], io_inst[31]};
wire [15:0] _decoder_decoded_andMatrixOutputs_T_64 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], io_inst[28], decoder_decoded_invInputs[27], io_inst[30], io_inst[31]};
wire [19:0] _decoder_decoded_andMatrixOutputs_T_67 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], io_inst[30], io_inst[31]};
wire [19:0] _decoder_decoded_andMatrixOutputs_T_69 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], io_inst[30], io_inst[31]};
wire [20:0] _decoder_decoded_andMatrixOutputs_T_72 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], io_inst[29], io_inst[30], io_inst[31]};
wire [20:0] _decoder_decoded_andMatrixOutputs_T_73 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], io_inst[30], io_inst[31]};
wire [20:0] _decoder_decoded_andMatrixOutputs_T_74 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], io_inst[28], io_inst[29], io_inst[30], io_inst[31]};
wire [20:0] _decoder_decoded_andMatrixOutputs_T_75 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], io_inst[28], io_inst[29], io_inst[30], io_inst[31]};
assign io_sigs_wen = |{&_decoder_decoded_andMatrixOutputs_T, &_decoder_decoded_andMatrixOutputs_T_2, &_decoder_decoded_andMatrixOutputs_T_3, &{io_inst[0], io_inst[1], io_inst[2], decoder_decoded_invInputs[1], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_inst[12], decoder_decoded_invInputs[12]}, &{io_inst[0], io_inst[1], io_inst[2], decoder_decoded_invInputs[1], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_inst[13], decoder_decoded_invInputs[12]}, &_decoder_decoded_andMatrixOutputs_T_27, &_decoder_decoded_andMatrixOutputs_T_28, &_decoder_decoded_andMatrixOutputs_T_30, &_decoder_decoded_andMatrixOutputs_T_31, &_decoder_decoded_andMatrixOutputs_T_38, &_decoder_decoded_andMatrixOutputs_T_41, &_decoder_decoded_andMatrixOutputs_T_44, &_decoder_decoded_andMatrixOutputs_T_47, &_decoder_decoded_andMatrixOutputs_T_49, &_decoder_decoded_andMatrixOutputs_T_50, &_decoder_decoded_andMatrixOutputs_T_63, &_decoder_decoded_andMatrixOutputs_T_64, &_decoder_decoded_andMatrixOutputs_T_74, &_decoder_decoded_andMatrixOutputs_T_75};
assign io_sigs_ren1 = |{&_decoder_decoded_andMatrixOutputs_T, &_decoder_decoded_andMatrixOutputs_T_2, &_decoder_decoded_andMatrixOutputs_T_3, &_decoder_decoded_andMatrixOutputs_T_21, &_decoder_decoded_andMatrixOutputs_T_22, &_decoder_decoded_andMatrixOutputs_T_23, &_decoder_decoded_andMatrixOutputs_T_24, &_decoder_decoded_andMatrixOutputs_T_27, &_decoder_decoded_andMatrixOutputs_T_28, &_decoder_decoded_andMatrixOutputs_T_37, &_decoder_decoded_andMatrixOutputs_T_40, &_decoder_decoded_andMatrixOutputs_T_43, &_decoder_decoded_andMatrixOutputs_T_46, &_decoder_decoded_andMatrixOutputs_T_49, &_decoder_decoded_andMatrixOutputs_T_50, &_decoder_decoded_andMatrixOutputs_T_60, &_decoder_decoded_andMatrixOutputs_T_61, &_decoder_decoded_andMatrixOutputs_T_67, &_decoder_decoded_andMatrixOutputs_T_69};
assign io_sigs_ren2 = |{&_decoder_decoded_andMatrixOutputs_T, &_decoder_decoded_andMatrixOutputs_T_2, &_decoder_decoded_andMatrixOutputs_T_3, &_decoder_decoded_andMatrixOutputs_T_11, &_decoder_decoded_andMatrixOutputs_T_14, &_decoder_decoded_andMatrixOutputs_T_21, &_decoder_decoded_andMatrixOutputs_T_22, &_decoder_decoded_andMatrixOutputs_T_23, &_decoder_decoded_andMatrixOutputs_T_24, &_decoder_decoded_andMatrixOutputs_T_27, &_decoder_decoded_andMatrixOutputs_T_28};
assign io_sigs_ren3 = &_decoder_decoded_andMatrixOutputs_T;
assign io_sigs_swap12 = |{&_decoder_decoded_andMatrixOutputs_T_11, &_decoder_decoded_andMatrixOutputs_T_14};
assign io_sigs_swap23 = |{&_decoder_decoded_andMatrixOutputs_T_7, &_decoder_decoded_andMatrixOutputs_T_8};
assign io_sigs_typeTagIn =
{|{&_decoder_decoded_andMatrixOutputs_T_11, &_decoder_decoded_andMatrixOutputs_T_14, &_decoder_decoded_andMatrixOutputs_T_17, &_decoder_decoded_andMatrixOutputs_T_18, &_decoder_decoded_andMatrixOutputs_T_32, &_decoder_decoded_andMatrixOutputs_T_33, &_decoder_decoded_andMatrixOutputs_T_34, &_decoder_decoded_andMatrixOutputs_T_38, &_decoder_decoded_andMatrixOutputs_T_52, &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[27], io_inst[30], io_inst[31]}, &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], io_inst[30], io_inst[31]}, &_decoder_decoded_andMatrixOutputs_T_72, &_decoder_decoded_andMatrixOutputs_T_73},
|{&_decoder_decoded_andMatrixOutputs_T_1,
&_decoder_decoded_andMatrixOutputs_T_4,
&_decoder_decoded_andMatrixOutputs_T_25,
&_decoder_decoded_andMatrixOutputs_T_26,
&_decoder_decoded_andMatrixOutputs_T_29,
&{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]},
&{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], io_inst[26], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]},
&_decoder_decoded_andMatrixOutputs_T_51,
&{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[27], io_inst[30], io_inst[31]},
&{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], io_inst[12], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], io_inst[30], io_inst[31]},
&{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], io_inst[28], io_inst[29], io_inst[30], io_inst[31]}}};
assign io_sigs_typeTagOut =
{|{&{io_inst[0], io_inst[1], io_inst[2], decoder_decoded_invInputs[1], decoder_decoded_invInputs[2], io_inst[5], decoder_decoded_invInputs[4], io_inst[12], io_inst[13], decoder_decoded_invInputs[12]}, &_decoder_decoded_andMatrixOutputs_T_17, &_decoder_decoded_andMatrixOutputs_T_18, &_decoder_decoded_andMatrixOutputs_T_32, &_decoder_decoded_andMatrixOutputs_T_33, &_decoder_decoded_andMatrixOutputs_T_34, &_decoder_decoded_andMatrixOutputs_T_44, &_decoder_decoded_andMatrixOutputs_T_52, &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], io_inst[28], decoder_decoded_invInputs[27], io_inst[30], io_inst[31]}, &_decoder_decoded_andMatrixOutputs_T_72, &_decoder_decoded_andMatrixOutputs_T_73, &_decoder_decoded_andMatrixOutputs_T_74},
|{&_decoder_decoded_andMatrixOutputs_T_1,
&_decoder_decoded_andMatrixOutputs_T_4,
&{io_inst[0], io_inst[1], io_inst[2], decoder_decoded_invInputs[1], decoder_decoded_invInputs[2], io_inst[5], decoder_decoded_invInputs[4], decoder_decoded_invInputs[10], io_inst[13], decoder_decoded_invInputs[12]},
&_decoder_decoded_andMatrixOutputs_T_25,
&_decoder_decoded_andMatrixOutputs_T_26,
&_decoder_decoded_andMatrixOutputs_T_29,
&{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], io_inst[20], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]},
&{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], io_inst[21], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]},
&_decoder_decoded_andMatrixOutputs_T_51,
&{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], io_inst[28], decoder_decoded_invInputs[27], io_inst[30], io_inst[31]},
&{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], io_inst[30], io_inst[31]}}};
assign io_sigs_fromint = |{&_decoder_decoded_andMatrixOutputs_T_63, &_decoder_decoded_andMatrixOutputs_T_64, &_decoder_decoded_andMatrixOutputs_T_74, &_decoder_decoded_andMatrixOutputs_T_75};
assign io_sigs_toint = |{&_decoder_decoded_andMatrixOutputs_T_11, &_decoder_decoded_andMatrixOutputs_T_14, &_decoder_decoded_andMatrixOutputs_T_53, &_decoder_decoded_andMatrixOutputs_T_54, &_decoder_decoded_andMatrixOutputs_T_55, &_decoder_decoded_andMatrixOutputs_T_56, &_decoder_decoded_andMatrixOutputs_T_60, &_decoder_decoded_andMatrixOutputs_T_61, &_decoder_decoded_andMatrixOutputs_T_67, &_decoder_decoded_andMatrixOutputs_T_69};
assign io_sigs_fastpipe = |{&_decoder_decoded_andMatrixOutputs_T_27, &_decoder_decoded_andMatrixOutputs_T_28, &_decoder_decoded_andMatrixOutputs_T_30, &_decoder_decoded_andMatrixOutputs_T_31, &_decoder_decoded_andMatrixOutputs_T_38, &_decoder_decoded_andMatrixOutputs_T_41, &_decoder_decoded_andMatrixOutputs_T_44, &_decoder_decoded_andMatrixOutputs_T_47};
assign io_sigs_fma = |{&_decoder_decoded_andMatrixOutputs_T, &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[27], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]}, &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[27], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]}, &_decoder_decoded_andMatrixOutputs_T_7, &_decoder_decoded_andMatrixOutputs_T_8};
assign io_sigs_div = |{&{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[23], io_inst[27], io_inst[28], decoder_decoded_invInputs[27], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]}, &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[24], io_inst[27], io_inst[28], decoder_decoded_invInputs[27], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]}};
assign io_sigs_sqrt = |{&_decoder_decoded_andMatrixOutputs_T_49, &_decoder_decoded_andMatrixOutputs_T_50};
assign io_sigs_wflags = |{&_decoder_decoded_andMatrixOutputs_T, &_decoder_decoded_andMatrixOutputs_T_2, &_decoder_decoded_andMatrixOutputs_T_3, &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[23], io_inst[27], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]}, &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[24], io_inst[27], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]}, &_decoder_decoded_andMatrixOutputs_T_37, &_decoder_decoded_andMatrixOutputs_T_40, &_decoder_decoded_andMatrixOutputs_T_43, &_decoder_decoded_andMatrixOutputs_T_46, &_decoder_decoded_andMatrixOutputs_T_49, &_decoder_decoded_andMatrixOutputs_T_50, &_decoder_decoded_andMatrixOutputs_T_53, &_decoder_decoded_andMatrixOutputs_T_54, &_decoder_decoded_andMatrixOutputs_T_55, &_decoder_decoded_andMatrixOutputs_T_56, &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[27], io_inst[30], io_inst[31]}, &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[27], io_inst[30], io_inst[31]}};
assign io_sigs_vec = 1'h0;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
case class FPUParams(
minFLen: Int = 32,
fLen: Int = 64,
divSqrt: Boolean = true,
sfmaLatency: Int = 3,
dfmaLatency: Int = 4,
fpmuLatency: Int = 2,
ifpuLatency: Int = 2
)
object FPConstants
{
val RM_SZ = 3
val FLAGS_SZ = 5
}
trait HasFPUCtrlSigs {
val ldst = Bool()
val wen = Bool()
val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val swap12 = Bool()
val swap23 = Bool()
val typeTagIn = UInt(2.W)
val typeTagOut = UInt(2.W)
val fromint = Bool()
val toint = Bool()
val fastpipe = Bool()
val fma = Bool()
val div = Bool()
val sqrt = Bool()
val wflags = Bool()
val vec = Bool()
}
class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val inst = Input(Bits(32.W))
val sigs = Output(new FPUCtrlSigs())
})
private val X2 = BitPat.dontCare(2)
val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)
val h: Array[(BitPat, List[BitPat])] =
Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),
FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),
FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),
FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),
FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),
FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),
FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),
FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))
val f: Array[(BitPat, List[BitPat])] =
Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),
FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),
FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),
FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),
FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),
FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))
val d: Array[(BitPat, List[BitPat])] =
Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),
FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),
FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),
FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),
FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),
FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),
FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),
FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))
val fcvt_hd: Array[(BitPat, List[BitPat])] =
Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),
FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))
val vfmv_f_s: Array[(BitPat, List[BitPat])] =
Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))
val insns = ((minFLen, fLen) match {
case (32, 32) => f
case (16, 32) => h ++ f
case (32, 64) => f ++ d
case (16, 64) => h ++ f ++ d ++ fcvt_hd
case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration")
}) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())
val decoder = DecodeLogic(io.inst, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,
s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)
sigs zip decoder map {case(s,d) => s := d}
}
class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val time = Input(UInt(xLen.W))
val inst = Input(Bits(32.W))
val fromint_data = Input(Bits(xLen.W))
val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))
val v_sew = Input(UInt(3.W))
val store_data = Output(Bits(fLen.W))
val toint_data = Output(Bits(xLen.W))
val ll_resp_val = Input(Bool())
val ll_resp_type = Input(Bits(3.W))
val ll_resp_tag = Input(UInt(5.W))
val ll_resp_data = Input(Bits(fLen.W))
val valid = Input(Bool())
val fcsr_rdy = Output(Bool())
val nack_mem = Output(Bool())
val illegal_rm = Output(Bool())
val killx = Input(Bool())
val killm = Input(Bool())
val dec = Output(new FPUCtrlSigs())
val sboard_set = Output(Bool())
val sboard_clr = Output(Bool())
val sboard_clra = Output(UInt(5.W))
val keep_clock_enabled = Input(Bool())
}
class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs
val cp_resp = Decoupled(new FPResult())
}
class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
val data = Bits((fLen+1).W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val typ = Bits(2.W)
val in1 = Bits(xLen.W)
}
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val fmaCmd = Bits(2.W)
val typ = Bits(2.W)
val fmt = Bits(2.W)
val in1 = Bits((fLen+1).W)
val in2 = Bits((fLen+1).W)
val in3 = Bits((fLen+1).W)
}
case class FType(exp: Int, sig: Int) {
def ieeeWidth = exp + sig
def recodedWidth = ieeeWidth + 1
def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)
def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)
def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR
def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)
def classify(x: UInt) = {
val sign = x(sig + exp)
val code = x(exp + sig - 1, exp + sig - 3)
val codeHi = code(2, 1)
val isSpecial = codeHi === 3.U
val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U
val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn
val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U
val isZero = code === 0.U
val isInf = isSpecial && !code(0)
val isNaN = code.andR
val isSNaN = isNaN && !x(sig-2)
val isQNaN = isNaN && x(sig-2)
Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,
isSubnormal && !sign, isZero && !sign, isZero && sign,
isSubnormal && sign, isNormal && sign, isInf && sign)
}
// convert between formats, ignoring rounding, range, NaN
def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {
val sign = x(sig + exp)
val fractIn = x(sig - 2, 0)
val expIn = x(sig + exp - 1, sig - 1)
val fractOut = fractIn << to.sig >> sig
val expOut = {
val expCode = expIn(exp, exp - 2)
val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U
Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))
}
Cat(sign, expOut, fractOut)
}
private def ieeeBundle = {
val expWidth = exp
class IEEEBundle extends Bundle {
val sign = Bool()
val exp = UInt(expWidth.W)
val sig = UInt((ieeeWidth-expWidth-1).W)
}
new IEEEBundle
}
def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)
def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)
def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)
}
object FType {
val H = new FType(5, 11)
val S = new FType(8, 24)
val D = new FType(11, 53)
val all = List(H, S, D)
}
trait HasFPUParameters {
require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))
val minFLen: Int
val fLen: Int
def xLen: Int
val minXLen = 32
val nIntTypes = log2Ceil(xLen/minXLen) + 1
def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)
def minType = floatTypes.head
def maxType = floatTypes.last
def prevType(t: FType) = floatTypes(typeTag(t) - 1)
def maxExpWidth = maxType.exp
def maxSigWidth = maxType.sig
def typeTag(t: FType) = floatTypes.indexOf(t)
def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U
def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U
// typeTag
def H = typeTagGroup(FType.H)
def S = typeTagGroup(FType.S)
def D = typeTagGroup(FType.D)
def I = typeTag(maxType).U
private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR
private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {
require(xt.ieeeWidth == 2 * yt.ieeeWidth)
val swizzledNaN = Cat(
x(xt.sig + xt.exp, xt.sig + xt.exp - 3),
x(xt.sig - 2, yt.recodedWidth - 1).andR,
x(xt.sig + xt.exp - 5, xt.sig),
y(yt.recodedWidth - 2),
x(xt.sig - 2, yt.recodedWidth - 1),
y(yt.recodedWidth - 1),
y(yt.recodedWidth - 3, 0))
Mux(xt.isNaN(x), swizzledNaN, x)
}
// implement NaN unboxing for FU inputs
def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {
val outType = exactType.getOrElse(maxType)
def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {
val prev =
if (t == minType) {
Seq()
} else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prev = helper(unswizzled, prevT)
val isbox = isBox(x, t)
prev.map(p => (isbox && p._1, p._2))
}
prev :+ (true.B, t.unsafeConvert(x, outType))
}
val (oks, floats) = helper(x, maxType).unzip
if (exactType.isEmpty || floatTypes.size == 1) {
Mux(oks(tag), floats(tag), maxType.qNaN)
} else {
val t = exactType.get
floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)
}
}
// make sure that the redundant bits in the NaN-boxed encoding are consistent
def consistent(x: UInt): Bool = {
def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prevOK = !isBox(x, t) || helper(unswizzled, prevT)
val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR
prevOK && curOK
}
helper(x, maxType)
}
// generate a NaN box from an FU result
def box(x: UInt, t: FType): UInt = {
if (t == maxType) {
x
} else {
val nt = floatTypes(typeTag(t) + 1)
val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)
bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U
}
}
// generate a NaN box from an FU result
def box(x: UInt, tag: UInt): UInt = {
val opts = floatTypes.map(t => box(x, t))
opts(tag)
}
// zap bits that hardfloat thinks are don't-cares, but we do care about
def sanitizeNaN(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
x
} else {
val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)
Mux(t.isNaN(x), maskedNaN, x)
}
}
// implement NaN boxing and recoding for FL*/fmv.*.x
def recode(x: UInt, tag: UInt): UInt = {
def helper(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
t.recode(x)
} else {
val prevT = prevType(t)
box(t.recode(x), t, helper(x, prevT), prevT)
}
}
// fill MSBs of subword loads to emulate a wider load of a NaN-boxed value
val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)
helper(boxes(tag) | x, maxType)
}
// implement NaN unboxing and un-recoding for FS*/fmv.x.*
def ieee(x: UInt, t: FType = maxType): UInt = {
if (typeTag(t) == 0) {
t.ieee(x)
} else {
val unrecoded = t.ieee(x)
val prevT = prevType(t)
val prevRecoded = Cat(
x(prevT.recodedWidth-2),
x(t.sig-1),
x(prevT.recodedWidth-3, 0))
val prevUnrecoded = ieee(prevRecoded, prevT)
Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))
}
}
}
abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
class Output extends Bundle {
val in = new FPInput
val lt = Bool()
val store = Bits(fLen.W)
val toint = Bits(xLen.W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new Output)
})
val in = RegEnable(io.in.bits, io.in.valid)
val valid = RegNext(io.in.valid)
val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
dcmp.io.a := in.in1
dcmp.io.b := in.in2
dcmp.io.signaling := !in.rm(1)
val tag = in.typeTagOut
val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))
else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
val toint = WireDefault(toint_ieee)
val intType = WireDefault(in.fmt(0))
io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
io.out.bits.exc := 0.U
when (in.rm(0)) {
val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)
toint := classify_out | (toint_ieee >> minXLen << minXLen)
intType := false.B
}
when (in.wflags) { // feq/flt/fle, fcvt
toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)
io.out.bits.exc := dcmp.io.exceptionFlags
intType := false.B
when (!in.ren2) { // fcvt
val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
intType := cvtType
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
conv.io.in := in.in1
conv.io.roundingMode := in.rm
conv.io.signedOut := ~in.typ(0)
toint := conv.io.out
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))
for (i <- 0 until nIntTypes-1) {
val w = minXLen << i
when (cvtType === i.U) {
val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))
narrow.io.in := in.in1
narrow.io.roundingMode := in.rm
narrow.io.signedOut := ~in.typ(0)
val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)
val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))
val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)
when (invalid) { toint := Cat(conv.io.out >> w, excOut) }
io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))
}
}
}
}
io.out.valid := valid
io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)
io.out.bits.in := in
}
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new IntToFPInput))
val out = Valid(new FPResult)
})
val in = Pipe(io.in)
val tag = in.bits.typeTagIn
val mux = Wire(new FPResult)
mux.exc := 0.U
mux.data := recode(in.bits.in1, tag)
val intValue = {
val res = WireDefault(in.bits.in1.asSInt)
for (i <- 0 until nIntTypes-1) {
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
}
}
res.asUInt
}
when (in.bits.wflags) { // fcvt
// could be improved for RVD/RVQ with a single variable-position rounding
// unit, rather than N fixed-position ones
val i2fResults = for (t <- floatTypes) yield {
val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
i2f.io.signedIn := ~in.bits.typ(0)
i2f.io.in := intValue
i2f.io.roundingMode := in.bits.rm
i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding
(sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)
}
val (data, exc) = i2fResults.unzip
val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
mux.data := dataPadded(tag)
mux.exc := exc(tag)
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
val lt = Input(Bool()) // from FPToInt
})
val in = Pipe(io.in)
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
val fsgnjMux = Wire(new FPResult)
fsgnjMux.exc := 0.U
fsgnjMux.data := fsgnj
when (in.bits.wflags) { // fmin/fmax
val isnan1 = maxType.isNaN(in.bits.in1)
val isnan2 = maxType.isNaN(in.bits.in2)
val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)
val isNaNOut = isnan1 && isnan2
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
fsgnjMux.exc := isInvalid << 4
fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
}
val inTag = in.bits.typeTagIn
val outTag = in.bits.typeTagOut
val mux = WireDefault(fsgnjMux)
for (t <- floatTypes.init) {
when (outTag === typeTag(t).U) {
mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))
}
}
when (in.bits.wflags && !in.bits.ren2) { // fcvt
if (floatTypes.size > 1) {
// widening conversions simply canonicalize NaN operands
val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)
fsgnjMux.data := widened
fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4
// narrowing conversions require rounding (for RVQ, this could be
// optimized to use a single variable-position rounding unit, rather
// than two fixed-position ones)
for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {
val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
narrower.io.in := in.bits.in1
narrower.io.roundingMode := in.bits.rm
narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding
val narrowed = sanitizeNaN(narrower.io.out, outType)
mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)
mux.exc := narrower.io.exceptionFlags
}
}
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
{
override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}"
require(latency<=2)
val io = IO(new Bundle {
val validin = Input(Bool())
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
val validout = Output(Bool())
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
val valid_stage0 = Wire(Bool())
val roundingMode_stage0 = Wire(UInt(3.W))
val detectTininess_stage0 = Wire(UInt(1.W))
val postmul_regs = if(latency>0) 1 else 0
mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits
detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits
valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
val round_regs = if(latency==2) 1 else 0
roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
io.validout := Pipe(valid_stage0, false.B, round_regs).valid
roundRawFNToRecFN.io.infiniteExc := false.B
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
class FPUFMAPipe(val latency: Int, val t: FType)
(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
require(latency>0)
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
})
val valid = RegNext(io.in.valid)
val in = Reg(new FPInput)
when (io.in.valid) {
val one = 1.U << (t.sig + t.exp - 1)
val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))
val cmd_fma = io.in.bits.ren3
val cmd_addsub = io.in.bits.swap23
in := io.in.bits
when (cmd_addsub) { in.in2 := one }
when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
}
val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
fma.io.validin := valid
fma.io.op := in.fmaCmd
fma.io.roundingMode := in.rm
fma.io.detectTininess := hardfloat.consts.tininess_afterRounding
fma.io.a := in.in1
fma.io.b := in.in2
fma.io.c := in.in3
val res = Wire(new FPResult)
res.data := sanitizeNaN(fma.io.out, t)
res.exc := fma.io.exceptionFlags
io.out := Pipe(fma.io.validout, res, (latency-3) max 0)
}
class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new FPUIO)
val (useClockGating, useDebugROB) = coreParams match {
case r: RocketCoreParams =>
val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1
(r.clockGate, sz < 1)
case _ => (false, false)
}
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cp_req.valid
val gated_clock =
if (!useClockGating) clock
else ClockGate(clock, clock_en, "fpu_clock_gate")
val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.inst
val id_ctrl = WireInit(fp_decoder.io.sigs)
coreParams match { case r: RocketCoreParams => r.vector.map(v => {
val v_decode = v.decoder(p) // Only need to get ren1
v_decode.io.inst := io.inst
v_decode.io.vconfig := DontCare // core deals with this
when (v_decode.io.legal && v_decode.io.read_frs1) {
id_ctrl.ren1 := true.B
id_ctrl.swap12 := false.B
id_ctrl.toint := true.B
id_ctrl.typeTagIn := I
id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)
}
when (v_decode.io.write_frd) { id_ctrl.wen := true.B }
})}
val ex_reg_valid = RegNext(io.valid, false.B)
val ex_reg_inst = RegEnable(io.inst, io.valid)
val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
val ex_ra = List.fill(3)(Reg(UInt()))
// load/vector response
val load_wb = RegNext(io.ll_resp_val)
val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)
val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)
val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)
class FPUImpl { // entering gated-clock domain
val req_valid = ex_reg_valid || io.cp_req.valid
val ex_cp_valid = io.cp_req.fire
val mem_cp_valid = RegNext(ex_cp_valid, false.B)
val wb_cp_valid = RegNext(mem_cp_valid, false.B)
val mem_reg_valid = RegInit(false.B)
val killm = (io.killm || io.nack_mem) && !mem_cp_valid
// Kill X-stage instruction if M-stage is killed. This prevents it from
// speculatively being sent to the div-sqrt unit, which can cause priority
// inversion for two back-to-back divides, the first of which is killed.
val killx = io.killx || mem_reg_valid && killm
mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid
val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
val cp_ctrl = Wire(new FPUCtrlSigs)
cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
io.cp_resp.valid := false.B
io.cp_resp.bits.data := 0.U
io.cp_resp.bits.exc := DontCare
val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)
val mem_ctrl = RegEnable(ex_ctrl, req_valid)
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
// CoreMonitorBundle to monitor fp register file writes
val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))
frfWriteBundle.foreach { i =>
i.clock := clock
i.reset := reset
i.hartid := io.hartid
i.timer := io.time(31,0)
i.valid := false.B
i.wrenx := false.B
i.wrenf := false.B
i.excpt := false.B
}
// regfile
val regfile = Mem(32, Bits((fLen+1).W))
when (load_wb) {
val wdata = recode(load_wb_data, load_wb_typeTag)
regfile(load_wb_tag) := wdata
assert(consistent(wdata))
if (enableCommitLog)
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))
if (useDebugROB)
DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))
frfWriteBundle(0).wrdst := load_wb_tag
frfWriteBundle(0).wrenf := true.B
frfWriteBundle(0).wrdata := ieee(wdata)
}
val ex_rs = ex_ra.map(a => regfile(a))
when (io.valid) {
when (id_ctrl.ren1) {
when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }
when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }
}
when (id_ctrl.ren2) {
when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }
when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }
when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }
}
when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }
}
val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))
def fuInput(minT: Option[FType]): FPInput = {
val req = Wire(new FPInput)
val tag = ex_ctrl.typeTagIn
req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
req.rm := ex_rm
req.in1 := unbox(ex_rs(0), tag, minT)
req.in2 := unbox(ex_rs(1), tag, minT)
req.in3 := unbox(ex_rs(2), tag, minT)
req.typ := ex_reg_inst(21,20)
req.fmt := ex_reg_inst(26,25)
req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))
when (ex_cp_valid) {
req := io.cp_req.bits
when (io.cp_req.bits.swap12) {
req.in1 := io.cp_req.bits.in2
req.in2 := io.cp_req.bits.in1
}
when (io.cp_req.bits.swap23) {
req.in2 := io.cp_req.bits.in3
req.in3 := io.cp_req.bits.in2
}
}
req
}
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new FPToInt)
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
io.store_data := fpiu.io.out.bits.store
io.toint_data := fpiu.io.out.bits.toint
when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){
io.cp_resp.bits.data := fpiu.io.out.bits.toint
io.cp_resp.valid := true.B
}
val ifpu = Module(new IntToFP(cfg.ifpuLatency))
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
ifpu.io.in.bits := fpiu.io.in.bits
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
val fpmu = Module(new FPToFP(cfg.fpmuLatency))
fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val divSqrt_wen = WireDefault(false.B)
val divSqrt_inFlight = WireDefault(false.B)
val divSqrt_waddr = Reg(UInt(5.W))
val divSqrt_cp = Reg(Bool())
val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
val divSqrt_wdata = Wire(UInt((fLen+1).W))
val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
divSqrt_typeTag := DontCare
divSqrt_wdata := DontCare
divSqrt_flags := DontCare
// writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++
(fLen > 32).option({
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D
dfma.io.in.bits := fuInput(Some(dfma.t))
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)
}) ++
(minFLen == 16).option({
val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))
hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H
hfma.io.in.bits := fuInput(Some(hfma.t))
Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)
})
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
require(pipes.forall(_.lat >= offset))
pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)
}
def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)
val maxLatency = pipes.map(_.lat).max
val memLatencyMask = latencyMask(mem_ctrl, 2)
class WBInfo extends Bundle {
val rd = UInt(5.W)
val typeTag = UInt(log2Up(floatTypes.size).W)
val cp = Bool()
val pipeid = UInt(log2Ceil(pipes.size).W)
}
val wen = RegInit(0.U((maxLatency-1).W))
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback")
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
}
wen := wen >> 1
when (mem_wen) {
when (!killm) {
wen := wen >> 1 | memLatencyMask
}
for (i <- 0 until maxLatency-1) {
when (!write_port_busy && memLatencyMask(i)) {
wbInfo(i).cp := mem_cp_valid
wbInfo(i).typeTag := mem_ctrl.typeTagOut
wbInfo(i).pipeid := pipeid(mem_ctrl)
wbInfo(i).rd := mem_reg_inst(11,7)
}
}
}
val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)
val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
assert(consistent(wdata))
regfile(waddr) := wdata
if (enableCommitLog) {
printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata))
}
frfWriteBundle(1).wrdst := waddr
frfWriteBundle(1).wrenf := true.B
frfWriteBundle(1).wrdata := ieee(wdata)
}
if (useDebugROB) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
}
when (wb_cp && (wen(0) || divSqrt_wen)) {
io.cp_resp.bits.data := wdata
io.cp_resp.valid := true.B
}
assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,
s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}")
// Avoid structural hazards and nacking of external requests
// toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs
io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)
io.fcsr_flags.bits :=
Mux(wb_toint_valid, wb_toint_exc, 0.U) |
Mux(divSqrt_wen, divSqrt_flags, 0.U) |
Mux(wen(0), wexc, 0.U)
val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid
io.dec <> id_ctrl
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)
io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))
io.sboard_clra := waddr
ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
// we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U
if (cfg.divSqrt) {
val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)
when (divSqrt_inValid) {
divSqrt_waddr := mem_reg_inst(11,7)
divSqrt_cp := mem_cp_valid
}
ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")
ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard")
ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback")
for (t <- floatTypes) {
val tag = mem_ctrl.typeTagOut
val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }
divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)
divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm
divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding
when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight
when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {
divSqrt_wen := !divSqrt_killed
divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)
divSqrt_flags := divSqrt.io.exceptionFlags
divSqrt_typeTag := typeTag(t).U
}
}
when (divSqrt_killed) { divSqrt_inFlight := false.B }
} else {
when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }
}
// gate the clock
clock_en_reg := !useClockGating.B ||
io.keep_clock_enabled || // chicken bit
io.valid || // ID stage
req_valid || // EX stage
mem_reg_valid || mem_cp_valid || // MEM stage
wb_reg_valid || wb_cp_valid || // WB stage
wen.orR || divSqrt_inFlight || // post-WB stage
io.ll_resp_val // load writeback
} // leaving gated-clock domain
val fpuImpl = withClock (gated_clock) { new FPUImpl }
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FPU_$label", "Core;;" + desc)
} | module FPUFMAPipe_l3_f32(
input clock,
input reset,
input io_in_valid,
input io_in_bits_ren3,
input io_in_bits_swap23,
input [2:0] io_in_bits_rm,
input [1:0] io_in_bits_fmaCmd,
input [64:0] io_in_bits_in1,
input [64:0] io_in_bits_in2,
input [64:0] io_in_bits_in3,
output [64:0] io_out_bits_data,
output [4:0] io_out_bits_exc
);
wire [32:0] _fma_io_out;
reg valid;
reg [2:0] in_rm;
reg [1:0] in_fmaCmd;
reg [64:0] in_in1;
reg [64:0] in_in2;
reg [64:0] in_in3;
always @(posedge clock) begin
valid <= io_in_valid;
if (io_in_valid) begin
in_rm <= io_in_bits_rm;
in_fmaCmd <= io_in_bits_fmaCmd;
in_in1 <= io_in_bits_in1;
in_in2 <= io_in_bits_swap23 ? 65'h80000000 : io_in_bits_in2;
in_in3 <= io_in_bits_ren3 | io_in_bits_swap23 ? io_in_bits_in3 : {32'h0, (io_in_bits_in1[32:0] ^ io_in_bits_in2[32:0]) & 33'h100000000};
end
end
MulAddRecFNPipe_l2_e8_s24 fma (
.clock (clock),
.reset (reset),
.io_validin (valid),
.io_op (in_fmaCmd),
.io_a (in_in1[32:0]),
.io_b (in_in2[32:0]),
.io_c (in_in3[32:0]),
.io_roundingMode (in_rm),
.io_out (_fma_io_out),
.io_exceptionFlags (io_out_bits_exc)
);
assign io_out_bits_data = {32'h0, ({33{_fma_io_out[31:29] != 3'h7}} | 33'h1EF7FFFFF) & _fma_io_out};
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
} | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11(
input io_in_isZero,
input io_in_sign,
input [8:0] io_in_sExp,
input [64:0] io_in_sig,
input [2:0] io_roundingMode,
output [16:0] io_out,
output [4:0] io_exceptionFlags
);
wire roundingMode_near_even = io_roundingMode == 3'h0;
wire roundMagUp = io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign;
wire [9:0] sAdjustedExp = {io_in_sExp[8], io_in_sExp} - 10'h60;
wire [1:0] _GEN = {io_in_sig[52], |(io_in_sig[51:0])};
wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4;
wire [12:0] roundedSig = _overflow_roundMagUp_T & io_in_sig[52] | roundMagUp & (|_GEN) ? {1'h0, io_in_sig[64:53]} + 13'h1 & {12'hFFF, ~(roundingMode_near_even & io_in_sig[52] & ~(|(io_in_sig[51:0])))} : {1'h0, io_in_sig[64:54], io_in_sig[53] | io_roundingMode == 3'h6 & (|_GEN)};
wire [10:0] sRoundedExp = {sAdjustedExp[9], sAdjustedExp} + {9'h0, roundedSig[12:11]};
wire overflow = ~io_in_isZero & $signed(sRoundedExp[10:4]) > 7'sh2;
wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp;
wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp;
wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp;
assign io_out = {io_in_sign, sRoundedExp[5:0] & ~(io_in_isZero ? 6'h38 : 6'h0) & {1'h1, ~pegMaxFiniteMagOut, 4'hF} & {2'h3, ~_notNaN_isInfOut_T, 3'h7} | (pegMaxFiniteMagOut ? 6'h2F : 6'h0) | (_notNaN_isInfOut_T ? 6'h30 : 6'h0), (io_in_isZero ? 10'h0 : roundedSig[9:0]) | {10{pegMaxFiniteMagOut}}};
assign io_exceptionFlags = {2'h0, overflow, 1'h0, overflow | ~io_in_isZero & (|_GEN)};
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
} | module ram_7x77(
input [2:0] R0_addr,
input R0_en,
input R0_clk,
output [76:0] R0_data,
input [2:0] W0_addr,
input W0_en,
input W0_clk,
input [76:0] W0_data
);
reg [76:0] Memory[0:6];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 77'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Functional Unit Decode
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Generate the functional unit control signals from the micro-op opcodes.
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.uintToBitPat
import freechips.rocketchip.rocket.CSR
import freechips.rocketchip.rocket.ALU._
import boom.v3.common._
/**
* Control signal bundle for register renaming
*/
class RRdCtrlSigs(implicit p: Parameters) extends BoomBundle
{
val br_type = UInt(BR_N.getWidth.W)
val use_alupipe = Bool()
val use_muldivpipe = Bool()
val use_mempipe = Bool()
val op_fcn = Bits(SZ_ALU_FN.W)
val fcn_dw = Bool()
val op1_sel = UInt(OP1_X.getWidth.W)
val op2_sel = UInt(OP2_X.getWidth.W)
val imm_sel = UInt(IS_X.getWidth.W)
val rf_wen = Bool()
val csr_cmd = Bits(CSR.SZ.W)
def decode(uopc: UInt, table: Iterable[(BitPat, List[BitPat])]) = {
val decoder = freechips.rocketchip.rocket.DecodeLogic(uopc, AluRRdDecode.default, table)
val sigs = Seq(br_type, use_alupipe, use_muldivpipe, use_mempipe, op_fcn,
fcn_dw, op1_sel, op2_sel, imm_sel, rf_wen, csr_cmd)
sigs zip decoder map {case(s,d) => s := d}
this
}
}
/**
* Default register read constants
*/
abstract trait RRdDecodeConstants
{
val default: List[BitPat] =
List[BitPat](BR_N , Y, N, N, FN_ADD , DW_X , OP1_X , OP2_X , IS_X, REN_0, CSR.N)
val table: Array[(BitPat, List[BitPat])]
}
/**
* ALU register read constants
*/
object AluRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopLUI) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMM , IS_U, REN_1, CSR.N),
BitPat(uopADDI) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopANDI) -> List(BR_N , Y, N, N, FN_AND , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopORI) -> List(BR_N , Y, N, N, FN_OR , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopXORI) -> List(BR_N , Y, N, N, FN_XOR , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSLTI) -> List(BR_N , Y, N, N, FN_SLT , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSLTIU) -> List(BR_N , Y, N, N, FN_SLTU, DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSLLI) -> List(BR_N , Y, N, N, FN_SL , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSRAI) -> List(BR_N , Y, N, N, FN_SRA , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSRLI) -> List(BR_N , Y, N, N, FN_SR , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopADDIW) -> List(BR_N , Y, N, N, FN_ADD , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSLLIW) -> List(BR_N , Y, N, N, FN_SL , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSRAIW) -> List(BR_N , Y, N, N, FN_SRA , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopSRLIW) -> List(BR_N , Y, N, N, FN_SR , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),
BitPat(uopADD) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSLL) -> List(BR_N , Y, N, N, FN_SL , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSUB) -> List(BR_N , Y, N, N, FN_SUB , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSLT) -> List(BR_N , Y, N, N, FN_SLT , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSLTU) -> List(BR_N , Y, N, N, FN_SLTU, DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopAND) -> List(BR_N , Y, N, N, FN_AND , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopOR) -> List(BR_N , Y, N, N, FN_OR , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopXOR) -> List(BR_N , Y, N, N, FN_XOR , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSRA) -> List(BR_N , Y, N, N, FN_SRA , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSRL) -> List(BR_N , Y, N, N, FN_SR , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopADDW) -> List(BR_N , Y, N, N, FN_ADD , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSUBW) -> List(BR_N , Y, N, N, FN_SUB , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSLLW) -> List(BR_N , Y, N, N, FN_SL , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSRAW) -> List(BR_N , Y, N, N, FN_SRA , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopSRLW) -> List(BR_N , Y, N, N, FN_SR , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopBEQ) -> List(BR_EQ ,Y, N, N, FN_SUB , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),
BitPat(uopBNE) -> List(BR_NE ,Y, N, N, FN_SUB , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),
BitPat(uopBGE) -> List(BR_GE ,Y, N, N, FN_SLT , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),
BitPat(uopBGEU) -> List(BR_GEU,Y, N, N, FN_SLTU, DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),
BitPat(uopBLT) -> List(BR_LT ,Y, N, N, FN_SLT , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),
BitPat(uopBLTU) -> List(BR_LTU,Y, N, N, FN_SLTU, DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N))
}
object JmpRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopJAL) -> List(BR_J , Y, N, N, FN_ADD , DW_XPR, OP1_PC , OP2_NEXT, IS_J, REN_1, CSR.N),
BitPat(uopJALR) -> List(BR_JR, Y, N, N, FN_ADD , DW_XPR, OP1_PC , OP2_NEXT, IS_I, REN_1, CSR.N),
BitPat(uopAUIPC) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_PC , OP2_IMM , IS_U, REN_1, CSR.N))
}
/**
* Multiply divider register read constants
*/
object MulDivRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopMUL) -> List(BR_N , N, Y, N, FN_MUL, DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),
BitPat(uopMULH) -> List(BR_N , N, Y, N, FN_MULH, DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),
BitPat(uopMULHU) -> List(BR_N , N, Y, N, FN_MULHU, DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),
BitPat(uopMULHSU)-> List(BR_N , N, Y, N, FN_MULHSU,DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),
BitPat(uopMULW) -> List(BR_N , N, Y, N, FN_MUL, DW_32 ,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),
BitPat(uopDIV) -> List(BR_N , N, Y, N, FN_DIV , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopDIVU) -> List(BR_N , N, Y, N, FN_DIVU, DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopREM) -> List(BR_N , N, Y, N, FN_REM , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopREMU) -> List(BR_N , N, Y, N, FN_REMU, DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopDIVW) -> List(BR_N , N, Y, N, FN_DIV , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopDIVUW) -> List(BR_N , N, Y, N, FN_DIVU, DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopREMW) -> List(BR_N , N, Y, N, FN_REM , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),
BitPat(uopREMUW) -> List(BR_N , N, Y, N, FN_REMU, DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N))
}
/**
* Memory unit register read constants
*/
object MemRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopLD) -> List(BR_N , N, N, Y, FN_ADD , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_0, CSR.N),
BitPat(uopSTA) -> List(BR_N , N, N, Y, FN_ADD , DW_XPR, OP1_RS1 , OP2_IMM , IS_S, REN_0, CSR.N),
BitPat(uopSTD) -> List(BR_N , N, N, Y, FN_X , DW_X , OP1_RS1 , OP2_RS2 , IS_X, REN_0, CSR.N),
BitPat(uopSFENCE)-> List(BR_N , N, N, Y, FN_X , DW_X , OP1_RS1 , OP2_RS2 , IS_X, REN_0, CSR.N),
BitPat(uopAMO_AG)-> List(BR_N , N, N, Y, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_X, REN_0, CSR.N))
}
/**
* CSR register read constants
*/
object CsrRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopCSRRW) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_I, REN_1, CSR.W),
BitPat(uopCSRRS) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_I, REN_1, CSR.S),
BitPat(uopCSRRC) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_I, REN_1, CSR.C),
BitPat(uopCSRRWI)-> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_1, CSR.W),
BitPat(uopCSRRSI)-> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_1, CSR.S),
BitPat(uopCSRRCI)-> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_1, CSR.C),
BitPat(uopWFI) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_0, CSR.I),
BitPat(uopERET) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_0, CSR.I))
}
/**
* FPU register read constants
*/
object FpuRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopFCLASS_S)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCLASS_D)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
// BitPat(uopFMV_W_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
// BitPat(uopFMV_D_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMV_X_W)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMV_X_D)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFSGNJ_S)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFSGNJ_D)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCVT_S_D) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCVT_D_S) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
// TODO comment out I2F instructions.
BitPat(uopFCVT_S_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCVT_D_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCVT_X_S) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCVT_X_D) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopCMPR_S) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopCMPR_D) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMINMAX_S)->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMINMAX_D)->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFADD_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFSUB_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMUL_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFADD_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFSUB_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMUL_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMADD_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMSUB_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFNMADD_S)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFNMSUB_S)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMADD_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMSUB_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFNMADD_D)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFNMSUB_D)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N))
}
/**
* Fused multiple add register read constants
*/
object IfmvRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopFMV_W_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFMV_D_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCVT_S_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFCVT_D_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N))
}
/**
* Floating point divide and square root register read constants
*/
object FDivRRdDecode extends RRdDecodeConstants
{
val table: Array[(BitPat, List[BitPat])] =
Array[(BitPat, List[BitPat])](
// br type
// | use alu pipe op1 sel op2 sel
// | | use muldiv pipe | | immsel csr_cmd
// | | | use mem pipe | | | rf wen |
// | | | | alu fcn wd/word?| | | | |
// | | | | | | | | | | |
BitPat(uopFDIV_S) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFDIV_D) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFSQRT_S) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),
BitPat(uopFSQRT_D) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N))
}
/**
* Register read decoder
*
* @param supportedUnits indicate what functional units are being used
*/
class RegisterReadDecode(supportedUnits: SupportedFuncUnits)(implicit p: Parameters) extends BoomModule
with freechips.rocketchip.rocket.constants.MemoryOpConstants
{
val io = IO(new BoomBundle {
val iss_valid = Input(Bool())
val iss_uop = Input(new MicroOp())
val rrd_valid = Output(Bool())
val rrd_uop = Output(new MicroOp())
})
// Issued Instruction
val rrd_valid = io.iss_valid
io.rrd_uop := io.iss_uop
var dec_table = AluRRdDecode.table
if (supportedUnits.jmp) dec_table ++= JmpRRdDecode.table
if (supportedUnits.mem) dec_table ++= MemRRdDecode.table
if (supportedUnits.muld) dec_table ++= MulDivRRdDecode.table
if (supportedUnits.csr) dec_table ++= CsrRRdDecode.table
if (supportedUnits.fpu) dec_table ++= FpuRRdDecode.table
if (supportedUnits.fdiv) dec_table ++= FDivRRdDecode.table
if (supportedUnits.ifpu) dec_table ++= IfmvRRdDecode.table
val rrd_cs = Wire(new RRdCtrlSigs()).decode(io.rrd_uop.uopc, dec_table)
// rrd_use_alupipe is unused
io.rrd_uop.ctrl.br_type := rrd_cs.br_type
io.rrd_uop.ctrl.op1_sel := rrd_cs.op1_sel
io.rrd_uop.ctrl.op2_sel := rrd_cs.op2_sel
io.rrd_uop.ctrl.imm_sel := rrd_cs.imm_sel
io.rrd_uop.ctrl.op_fcn := rrd_cs.op_fcn.asUInt
io.rrd_uop.ctrl.fcn_dw := rrd_cs.fcn_dw.asBool
io.rrd_uop.ctrl.is_load := io.rrd_uop.uopc === uopLD
io.rrd_uop.ctrl.is_sta := io.rrd_uop.uopc === uopSTA || io.rrd_uop.uopc === uopAMO_AG
io.rrd_uop.ctrl.is_std := io.rrd_uop.uopc === uopSTD || (io.rrd_uop.ctrl.is_sta && io.rrd_uop.lrs2_rtype === RT_FIX)
when (io.rrd_uop.uopc === uopAMO_AG || (io.rrd_uop.uopc === uopLD && io.rrd_uop.mem_cmd === M_XLR)) {
io.rrd_uop.imm_packed := 0.U
}
val raddr1 = io.rrd_uop.prs1 // although renamed, it'll stay 0 if lrs1 = 0
val csr_ren = (rrd_cs.csr_cmd === CSR.S || rrd_cs.csr_cmd === CSR.C) && raddr1 === 0.U
io.rrd_uop.ctrl.csr_cmd := Mux(csr_ren, CSR.R, rrd_cs.csr_cmd)
//-------------------------------------------------------------
// set outputs
io.rrd_valid := rrd_valid
} | module RegisterReadDecode_2(
input io_iss_valid,
input [6:0] io_iss_uop_uopc,
input [31:0] io_iss_uop_inst,
input [31:0] io_iss_uop_debug_inst,
input io_iss_uop_is_rvc,
input [39:0] io_iss_uop_debug_pc,
input [2:0] io_iss_uop_iq_type,
input [9:0] io_iss_uop_fu_code,
input [1:0] io_iss_uop_iw_state,
input io_iss_uop_is_br,
input io_iss_uop_is_jalr,
input io_iss_uop_is_jal,
input io_iss_uop_is_sfb,
input [7:0] io_iss_uop_br_mask,
input [2:0] io_iss_uop_br_tag,
input [3:0] io_iss_uop_ftq_idx,
input io_iss_uop_edge_inst,
input [5:0] io_iss_uop_pc_lob,
input io_iss_uop_taken,
input [19:0] io_iss_uop_imm_packed,
input [11:0] io_iss_uop_csr_addr,
input [4:0] io_iss_uop_rob_idx,
input [2:0] io_iss_uop_ldq_idx,
input [2:0] io_iss_uop_stq_idx,
input [1:0] io_iss_uop_rxq_idx,
input [5:0] io_iss_uop_pdst,
input [5:0] io_iss_uop_prs1,
input [5:0] io_iss_uop_prs2,
input [5:0] io_iss_uop_prs3,
input [3:0] io_iss_uop_ppred,
input io_iss_uop_prs1_busy,
input io_iss_uop_prs2_busy,
input io_iss_uop_prs3_busy,
input io_iss_uop_ppred_busy,
input [5:0] io_iss_uop_stale_pdst,
input io_iss_uop_exception,
input [63:0] io_iss_uop_exc_cause,
input io_iss_uop_bypassable,
input [4:0] io_iss_uop_mem_cmd,
input [1:0] io_iss_uop_mem_size,
input io_iss_uop_mem_signed,
input io_iss_uop_is_fence,
input io_iss_uop_is_fencei,
input io_iss_uop_is_amo,
input io_iss_uop_uses_ldq,
input io_iss_uop_uses_stq,
input io_iss_uop_is_sys_pc2epc,
input io_iss_uop_is_unique,
input io_iss_uop_flush_on_commit,
input io_iss_uop_ldst_is_rs1,
input [5:0] io_iss_uop_ldst,
input [5:0] io_iss_uop_lrs1,
input [5:0] io_iss_uop_lrs2,
input [5:0] io_iss_uop_lrs3,
input io_iss_uop_ldst_val,
input [1:0] io_iss_uop_dst_rtype,
input [1:0] io_iss_uop_lrs1_rtype,
input [1:0] io_iss_uop_lrs2_rtype,
input io_iss_uop_frs3_en,
input io_iss_uop_fp_val,
input io_iss_uop_fp_single,
input io_iss_uop_xcpt_pf_if,
input io_iss_uop_xcpt_ae_if,
input io_iss_uop_xcpt_ma_if,
input io_iss_uop_bp_debug_if,
input io_iss_uop_bp_xcpt_if,
input [1:0] io_iss_uop_debug_fsrc,
input [1:0] io_iss_uop_debug_tsrc,
output io_rrd_valid,
output [6:0] io_rrd_uop_uopc,
output [31:0] io_rrd_uop_inst,
output [31:0] io_rrd_uop_debug_inst,
output io_rrd_uop_is_rvc,
output [39:0] io_rrd_uop_debug_pc,
output [2:0] io_rrd_uop_iq_type,
output [9:0] io_rrd_uop_fu_code,
output [3:0] io_rrd_uop_ctrl_br_type,
output [1:0] io_rrd_uop_ctrl_op1_sel,
output [2:0] io_rrd_uop_ctrl_op2_sel,
output [2:0] io_rrd_uop_ctrl_imm_sel,
output [4:0] io_rrd_uop_ctrl_op_fcn,
output io_rrd_uop_ctrl_fcn_dw,
output [2:0] io_rrd_uop_ctrl_csr_cmd,
output io_rrd_uop_ctrl_is_load,
output io_rrd_uop_ctrl_is_sta,
output io_rrd_uop_ctrl_is_std,
output [1:0] io_rrd_uop_iw_state,
output io_rrd_uop_is_br,
output io_rrd_uop_is_jalr,
output io_rrd_uop_is_jal,
output io_rrd_uop_is_sfb,
output [7:0] io_rrd_uop_br_mask,
output [2:0] io_rrd_uop_br_tag,
output [3:0] io_rrd_uop_ftq_idx,
output io_rrd_uop_edge_inst,
output [5:0] io_rrd_uop_pc_lob,
output io_rrd_uop_taken,
output [19:0] io_rrd_uop_imm_packed,
output [11:0] io_rrd_uop_csr_addr,
output [4:0] io_rrd_uop_rob_idx,
output [2:0] io_rrd_uop_ldq_idx,
output [2:0] io_rrd_uop_stq_idx,
output [1:0] io_rrd_uop_rxq_idx,
output [5:0] io_rrd_uop_pdst,
output [5:0] io_rrd_uop_prs1,
output [5:0] io_rrd_uop_prs2,
output [5:0] io_rrd_uop_prs3,
output [3:0] io_rrd_uop_ppred,
output io_rrd_uop_prs1_busy,
output io_rrd_uop_prs2_busy,
output io_rrd_uop_prs3_busy,
output io_rrd_uop_ppred_busy,
output [5:0] io_rrd_uop_stale_pdst,
output io_rrd_uop_exception,
output [63:0] io_rrd_uop_exc_cause,
output io_rrd_uop_bypassable,
output [4:0] io_rrd_uop_mem_cmd,
output [1:0] io_rrd_uop_mem_size,
output io_rrd_uop_mem_signed,
output io_rrd_uop_is_fence,
output io_rrd_uop_is_fencei,
output io_rrd_uop_is_amo,
output io_rrd_uop_uses_ldq,
output io_rrd_uop_uses_stq,
output io_rrd_uop_is_sys_pc2epc,
output io_rrd_uop_is_unique,
output io_rrd_uop_flush_on_commit,
output io_rrd_uop_ldst_is_rs1,
output [5:0] io_rrd_uop_ldst,
output [5:0] io_rrd_uop_lrs1,
output [5:0] io_rrd_uop_lrs2,
output [5:0] io_rrd_uop_lrs3,
output io_rrd_uop_ldst_val,
output [1:0] io_rrd_uop_dst_rtype,
output [1:0] io_rrd_uop_lrs1_rtype,
output [1:0] io_rrd_uop_lrs2_rtype,
output io_rrd_uop_frs3_en,
output io_rrd_uop_fp_val,
output io_rrd_uop_fp_single,
output io_rrd_uop_xcpt_pf_if,
output io_rrd_uop_xcpt_ae_if,
output io_rrd_uop_xcpt_ma_if,
output io_rrd_uop_bp_debug_if,
output io_rrd_uop_bp_xcpt_if,
output [1:0] io_rrd_uop_debug_fsrc,
output [1:0] io_rrd_uop_debug_tsrc
);
wire [6:0] rrd_cs_decoder_decoded_invInputs = ~io_iss_uop_uopc;
wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_3 = {rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]};
wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_9 = {io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]};
wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_34 = {rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]};
wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_35 = {rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]};
wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_52 = {io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};
wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_53 = {io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};
wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_56 = {rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};
wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_57 = {io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};
wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_59 = {rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};
wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_60 = {io_iss_uop_uopc[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};
wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_64 = {io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};
wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_69 = {rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};
wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_82 = {rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], io_iss_uop_uopc[6]};
wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_84 = {rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], io_iss_uop_uopc[6]};
wire [1:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_85 = {io_iss_uop_uopc[5], io_iss_uop_uopc[6]};
wire [2:0] rrd_cs_csr_cmd = {|{&{io_iss_uop_uopc[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], io_iss_uop_uopc[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], io_iss_uop_uopc[6]}}, |{&{io_iss_uop_uopc[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_53}, |{&{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_52}};
wire io_rrd_uop_ctrl_is_load_0 = io_iss_uop_uopc == 7'h1;
wire _io_rrd_uop_ctrl_is_sta_T_1 = io_iss_uop_uopc == 7'h43;
wire io_rrd_uop_ctrl_is_sta_0 = io_iss_uop_uopc == 7'h2 | _io_rrd_uop_ctrl_is_sta_T_1;
assign io_rrd_valid = io_iss_valid;
assign io_rrd_uop_uopc = io_iss_uop_uopc;
assign io_rrd_uop_inst = io_iss_uop_inst;
assign io_rrd_uop_debug_inst = io_iss_uop_debug_inst;
assign io_rrd_uop_is_rvc = io_iss_uop_is_rvc;
assign io_rrd_uop_debug_pc = io_iss_uop_debug_pc;
assign io_rrd_uop_iq_type = io_iss_uop_iq_type;
assign io_rrd_uop_fu_code = io_iss_uop_fu_code;
assign io_rrd_uop_ctrl_br_type = {&_rrd_cs_decoder_decoded_andMatrixOutputs_T_59, |{&{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57}, |{&{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57}, |{&{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57}};
assign io_rrd_uop_ctrl_op1_sel = {&{io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, |{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_3, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_52, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_53, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_85}};
assign io_rrd_uop_ctrl_op2_sel = {|{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_52, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_53, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_85}, |{&{io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_56, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_59}, |{&{rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}}};
assign io_rrd_uop_ctrl_imm_sel = {&_rrd_cs_decoder_decoded_andMatrixOutputs_T_56, |{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_3, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_34, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_35, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_60}, |{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_3, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_60}};
assign io_rrd_uop_ctrl_op_fcn =
{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_84,
|{&{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_34, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_35, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_64, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_84},
|{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_9, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_82, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_84},
|{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_9, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_64, &{rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[1], io_iss_uop_uopc[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_82, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_84},
|{&{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_69, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_82, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_84}};
assign io_rrd_uop_ctrl_fcn_dw = {&{io_iss_uop_uopc[0], io_iss_uop_uopc[1], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_69, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], io_iss_uop_uopc[6]}} == 7'h0;
assign io_rrd_uop_ctrl_csr_cmd = (rrd_cs_csr_cmd == 3'h6 | (&rrd_cs_csr_cmd)) & io_iss_uop_prs1 == 6'h0 ? 3'h2 : rrd_cs_csr_cmd;
assign io_rrd_uop_ctrl_is_load = io_rrd_uop_ctrl_is_load_0;
assign io_rrd_uop_ctrl_is_sta = io_rrd_uop_ctrl_is_sta_0;
assign io_rrd_uop_ctrl_is_std = io_iss_uop_uopc == 7'h3 | io_rrd_uop_ctrl_is_sta_0 & io_iss_uop_lrs2_rtype == 2'h0;
assign io_rrd_uop_iw_state = io_iss_uop_iw_state;
assign io_rrd_uop_is_br = io_iss_uop_is_br;
assign io_rrd_uop_is_jalr = io_iss_uop_is_jalr;
assign io_rrd_uop_is_jal = io_iss_uop_is_jal;
assign io_rrd_uop_is_sfb = io_iss_uop_is_sfb;
assign io_rrd_uop_br_mask = io_iss_uop_br_mask;
assign io_rrd_uop_br_tag = io_iss_uop_br_tag;
assign io_rrd_uop_ftq_idx = io_iss_uop_ftq_idx;
assign io_rrd_uop_edge_inst = io_iss_uop_edge_inst;
assign io_rrd_uop_pc_lob = io_iss_uop_pc_lob;
assign io_rrd_uop_taken = io_iss_uop_taken;
assign io_rrd_uop_imm_packed = _io_rrd_uop_ctrl_is_sta_T_1 | io_rrd_uop_ctrl_is_load_0 & io_iss_uop_mem_cmd == 5'h6 ? 20'h0 : io_iss_uop_imm_packed;
assign io_rrd_uop_csr_addr = io_iss_uop_csr_addr;
assign io_rrd_uop_rob_idx = io_iss_uop_rob_idx;
assign io_rrd_uop_ldq_idx = io_iss_uop_ldq_idx;
assign io_rrd_uop_stq_idx = io_iss_uop_stq_idx;
assign io_rrd_uop_rxq_idx = io_iss_uop_rxq_idx;
assign io_rrd_uop_pdst = io_iss_uop_pdst;
assign io_rrd_uop_prs1 = io_iss_uop_prs1;
assign io_rrd_uop_prs2 = io_iss_uop_prs2;
assign io_rrd_uop_prs3 = io_iss_uop_prs3;
assign io_rrd_uop_ppred = io_iss_uop_ppred;
assign io_rrd_uop_prs1_busy = io_iss_uop_prs1_busy;
assign io_rrd_uop_prs2_busy = io_iss_uop_prs2_busy;
assign io_rrd_uop_prs3_busy = io_iss_uop_prs3_busy;
assign io_rrd_uop_ppred_busy = io_iss_uop_ppred_busy;
assign io_rrd_uop_stale_pdst = io_iss_uop_stale_pdst;
assign io_rrd_uop_exception = io_iss_uop_exception;
assign io_rrd_uop_exc_cause = io_iss_uop_exc_cause;
assign io_rrd_uop_bypassable = io_iss_uop_bypassable;
assign io_rrd_uop_mem_cmd = io_iss_uop_mem_cmd;
assign io_rrd_uop_mem_size = io_iss_uop_mem_size;
assign io_rrd_uop_mem_signed = io_iss_uop_mem_signed;
assign io_rrd_uop_is_fence = io_iss_uop_is_fence;
assign io_rrd_uop_is_fencei = io_iss_uop_is_fencei;
assign io_rrd_uop_is_amo = io_iss_uop_is_amo;
assign io_rrd_uop_uses_ldq = io_iss_uop_uses_ldq;
assign io_rrd_uop_uses_stq = io_iss_uop_uses_stq;
assign io_rrd_uop_is_sys_pc2epc = io_iss_uop_is_sys_pc2epc;
assign io_rrd_uop_is_unique = io_iss_uop_is_unique;
assign io_rrd_uop_flush_on_commit = io_iss_uop_flush_on_commit;
assign io_rrd_uop_ldst_is_rs1 = io_iss_uop_ldst_is_rs1;
assign io_rrd_uop_ldst = io_iss_uop_ldst;
assign io_rrd_uop_lrs1 = io_iss_uop_lrs1;
assign io_rrd_uop_lrs2 = io_iss_uop_lrs2;
assign io_rrd_uop_lrs3 = io_iss_uop_lrs3;
assign io_rrd_uop_ldst_val = io_iss_uop_ldst_val;
assign io_rrd_uop_dst_rtype = io_iss_uop_dst_rtype;
assign io_rrd_uop_lrs1_rtype = io_iss_uop_lrs1_rtype;
assign io_rrd_uop_lrs2_rtype = io_iss_uop_lrs2_rtype;
assign io_rrd_uop_frs3_en = io_iss_uop_frs3_en;
assign io_rrd_uop_fp_val = io_iss_uop_fp_val;
assign io_rrd_uop_fp_single = io_iss_uop_fp_single;
assign io_rrd_uop_xcpt_pf_if = io_iss_uop_xcpt_pf_if;
assign io_rrd_uop_xcpt_ae_if = io_iss_uop_xcpt_ae_if;
assign io_rrd_uop_xcpt_ma_if = io_iss_uop_xcpt_ma_if;
assign io_rrd_uop_bp_debug_if = io_iss_uop_bp_debug_if;
assign io_rrd_uop_bp_xcpt_if = io_iss_uop_bp_xcpt_if;
assign io_rrd_uop_debug_fsrc = io_iss_uop_debug_fsrc;
assign io_rrd_uop_debug_tsrc = io_iss_uop_debug_tsrc;
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(t))
val out = Decoupled(new Flit(flitWidth))
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))
data(0) := DontCare // unused, DCE this
}
}
io.busy := io.out.valid
}
class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(t)
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits := (if (dataBeats == 1) {
io.in.bits.flit.asTypeOf(t)
} else {
Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)
})
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit
}
}
}
io.busy := beat =/= 0.U
}
class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Phit(phitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail
}
}
}
object FlitToPhit {
def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {
val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))
flit2phit.io.in <> flit
flit2phit.io.out
}
}
class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Decoupled(new Flit(flitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat) := io.in.bits.phit
}
}
}
}
object PhitToFlit {
def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in <> phit
phit2flit.io.out
}
def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in.valid := phit.valid
phit2flit.io.in.bits := phit.bits
when (phit.valid) { assert(phit2flit.io.in.ready) }
val out = Wire(Valid(new Flit(flitWidth)))
out.valid := phit2flit.io.out.valid
out.bits := phit2flit.io.out.bits
phit2flit.io.out.ready := true.B
out
}
}
class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))
val out = Decoupled(new Phit(phitWidth))
})
if (channels == 1) {
io.out <> io.in(0)
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val chosen_reg = Reg(UInt(headerWidth.W))
val chosen_prio = PriorityEncoder(io.in.map(_.valid))
val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.out.valid := VecInit(io.in.map(_.valid))(chosen)
io.out.bits.phit := Mux(beat < headerBeats.U,
chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),
VecInit(io.in.map(_.bits.phit))(chosen))
for (i <- 0 until channels) {
io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U
}
when (io.out.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) { chosen_reg := chosen_prio }
}
}
}
class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Vec(channels, Decoupled(new Phit(phitWidth)))
})
if (channels == 1) {
io.out(0) <> io.in
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))
val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)
for (c <- 0 until channels) {
io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U
io.out(c).bits.phit := io.in.bits.phit
}
when (io.in.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat < headerBeats.U) {
channel_vec(header_idx) := io.in.bits.phit
}
}
}
}
class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Flipped(Decoupled(new Flit(flitWidth)))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = io.out.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)
}
io.out.valid := io.in.valid && credits < bufferSz.U
io.out.bits.flit := io.in.bits.flit
io.in.ready := io.out.ready && credits < bufferSz.U
io.credit.ready := true.B
}
class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Decoupled(new Flit(flitWidth))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = buffer.io.deq.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credit_incr + Mux(credit_decr, 0.U, credits)
}
buffer.io.enq.valid := io.in.valid
buffer.io.enq.bits := io.in.bits
io.in.ready := true.B
when (io.in.valid) { assert(buffer.io.enq.ready) }
io.out <> buffer.io.deq
io.credit.valid := credits =/= 0.U
io.credit.bits.flit := credits - 1.U
} | module PhitToFlit_p32_f32(
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits_phit,
input io_out_ready,
output io_out_valid,
output [31:0] io_out_bits_flit
);
assign io_in_ready = io_out_ready;
assign io_out_valid = io_in_valid;
assign io_out_bits_flit = io_in_bits_phit;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.{Cat, Fill}
import consts._
/*----------------------------------------------------------------------------
| Computes a division or square root for standard 64-bit floating-point in
| recoded form, using a separate integer multiplier-adder. Multiple clock
| cycles are needed for each division or square-root operation. See
| "docs/DivSqrtRecF64_mulAddZ31.txt" for more details.
*----------------------------------------------------------------------------*/
class DivSqrtRecF64ToRaw_mulAddZ31 extends Module
{
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady_div = Output(Bool())
val inReady_sqrt = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(Bits(65.W))
val b = Input(Bits(65.W))
val roundingMode = Input(UInt(3.W))
//*** OPTIONALLY PROPAGATE:
// val detectTininess = Input(UInt(1.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val usingMulAdd = Output(Bits(4.W))
val latchMulAddA_0 = Output(Bool())
val mulAddA_0 = Output(UInt(54.W))
val latchMulAddB_0 = Output(Bool())
val mulAddB_0 = Output(UInt(54.W))
val mulAddC_2 = Output(UInt(105.W))
val mulAddResult_3 = Input(UInt(105.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val rawOutValid_div = Output(Bool())
val rawOutValid_sqrt = Output(Bool())
val roundingModeOut = Output(UInt(3.W))
val invalidExc = Output(Bool())
val infiniteExc = Output(Bool())
val rawOut = Output(new RawFloat(11, 55))
})
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val cycleNum_A = RegInit(0.U(3.W))
val cycleNum_B = RegInit(0.U(4.W))
val cycleNum_C = RegInit(0.U(3.W))
val cycleNum_E = RegInit(0.U(3.W))
val valid_PA = RegInit(false.B)
val sqrtOp_PA = Reg(Bool())
val majorExc_PA = Reg(Bool())
//*** REDUCE 3 BITS TO 2-BIT CODE:
val isNaN_PA = Reg(Bool())
val isInf_PA = Reg(Bool())
val isZero_PA = Reg(Bool())
val sign_PA = Reg(Bool())
val sExp_PA = Reg(SInt(13.W))
val fractB_PA = Reg(UInt(52.W))
val fractA_PA = Reg(UInt(52.W))
val roundingMode_PA = Reg(UInt(3.W))
val valid_PB = RegInit(false.B)
val sqrtOp_PB = Reg(Bool())
val majorExc_PB = Reg(Bool())
//*** REDUCE 3 BITS TO 2-BIT CODE:
val isNaN_PB = Reg(Bool())
val isInf_PB = Reg(Bool())
val isZero_PB = Reg(Bool())
val sign_PB = Reg(Bool())
val sExp_PB = Reg(SInt(13.W))
val bit0FractA_PB = Reg(UInt(1.W))
val fractB_PB = Reg(UInt(52.W))
val roundingMode_PB = Reg(UInt(3.W))
val valid_PC = RegInit(false.B)
val sqrtOp_PC = Reg(Bool())
val majorExc_PC = Reg(Bool())
//*** REDUCE 3 BITS TO 2-BIT CODE:
val isNaN_PC = Reg(Bool())
val isInf_PC = Reg(Bool())
val isZero_PC = Reg(Bool())
val sign_PC = Reg(Bool())
val sExp_PC = Reg(SInt(13.W))
val bit0FractA_PC = Reg(UInt(1.W))
val fractB_PC = Reg(UInt(52.W))
val roundingMode_PC = Reg(UInt(3.W))
val fractR0_A = Reg(UInt(9.W))
//*** COMBINE 'hiSqrR0_A_sqrt' AND 'partNegSigma0_A'?
val hiSqrR0_A_sqrt = Reg(UInt(10.W))
val partNegSigma0_A = Reg(UInt(21.W))
val nextMulAdd9A_A = Reg(UInt(9.W))
val nextMulAdd9B_A = Reg(UInt(9.W))
val ER1_B_sqrt = Reg(UInt(17.W))
val ESqrR1_B_sqrt = Reg(UInt(32.W))
val sigX1_B = Reg(UInt(58.W))
val sqrSigma1_C = Reg(UInt(33.W))
val sigXN_C = Reg(UInt(58.W))
val u_C_sqrt = Reg(UInt(31.W))
val E_E_div = Reg(Bool())
val sigT_E = Reg(UInt(54.W))
val isNegRemT_E = Reg(Bool())
val isZeroRemT_E = Reg(Bool())
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val ready_PA = Wire(Bool())
val ready_PB = Wire(Bool())
val ready_PC = Wire(Bool())
val leaving_PA = Wire(Bool())
val leaving_PB = Wire(Bool())
val leaving_PC = Wire(Bool())
val zSigma1_B4 = Wire(UInt())
val sigXNU_B3_CX = Wire(UInt())
val zComplSigT_C1_sqrt = Wire(UInt())
val zComplSigT_C1 = Wire(UInt())
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val cyc_S_div = io.inReady_div && io.inValid && ! io.sqrtOp
val cyc_S_sqrt = io.inReady_sqrt && io.inValid && io.sqrtOp
val cyc_S = cyc_S_div || cyc_S_sqrt
val rawA_S = rawFloatFromRecFN(11, 53, io.a)
val rawB_S = rawFloatFromRecFN(11, 53, io.b)
val notSigNaNIn_invalidExc_S_div =
(rawA_S.isZero && rawB_S.isZero) || (rawA_S.isInf && rawB_S.isInf)
val notSigNaNIn_invalidExc_S_sqrt =
! rawB_S.isNaN && ! rawB_S.isZero && rawB_S.sign
val majorExc_S =
Mux(io.sqrtOp,
isSigNaNRawFloat(rawB_S) || notSigNaNIn_invalidExc_S_sqrt,
isSigNaNRawFloat(rawA_S) || isSigNaNRawFloat(rawB_S) ||
notSigNaNIn_invalidExc_S_div ||
(! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero)
)
val isNaN_S =
Mux(io.sqrtOp,
rawB_S.isNaN || notSigNaNIn_invalidExc_S_sqrt,
rawA_S.isNaN || rawB_S.isNaN || notSigNaNIn_invalidExc_S_div
)
val isInf_S = Mux(io.sqrtOp, rawB_S.isInf, rawA_S.isInf || rawB_S.isZero)
val isZero_S = Mux(io.sqrtOp, rawB_S.isZero, rawA_S.isZero || rawB_S.isInf)
val sign_S = (! io.sqrtOp && rawA_S.sign) ^ rawB_S.sign
val specialCaseA_S = rawA_S.isNaN || rawA_S.isInf || rawA_S.isZero
val specialCaseB_S = rawB_S.isNaN || rawB_S.isInf || rawB_S.isZero
val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S
val normalCase_S_sqrt = ! specialCaseB_S && ! rawB_S.sign
val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)
val sExpQuot_S_div =
rawA_S.sExp +& (rawB_S.sExp(11) ## ~rawB_S.sExp(10, 0)).asSInt
//*** IS THIS OPTIMAL?:
val sSatExpQuot_S_div =
(Mux(((7<<9).S <= sExpQuot_S_div),
6.U,
sExpQuot_S_div(12, 9)
) ##
sExpQuot_S_div(8, 0)
).asSInt
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val entering_PA_normalCase_div = cyc_S_div && normalCase_S_div
val entering_PA_normalCase_sqrt = cyc_S_sqrt && normalCase_S_sqrt
val entering_PA_normalCase =
entering_PA_normalCase_div || entering_PA_normalCase_sqrt
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
when (entering_PA_normalCase || (cycleNum_A =/= 0.U)) {
cycleNum_A :=
Mux(entering_PA_normalCase_div, 3.U, 0.U) |
Mux(entering_PA_normalCase_sqrt, 6.U, 0.U) |
Mux(! entering_PA_normalCase, cycleNum_A - 1.U, 0.U)
}
val cyc_A7_sqrt = entering_PA_normalCase_sqrt
val cyc_A6_sqrt = (cycleNum_A === 6.U)
val cyc_A5_sqrt = (cycleNum_A === 5.U)
val cyc_A4_sqrt = (cycleNum_A === 4.U)
val cyc_A4_div = entering_PA_normalCase_div
val cyc_A4 = cyc_A4_sqrt || cyc_A4_div
val cyc_A3 = (cycleNum_A === 3.U)
val cyc_A2 = (cycleNum_A === 2.U)
val cyc_A1 = (cycleNum_A === 1.U)
val cyc_A3_div = cyc_A3 && ! sqrtOp_PA
val cyc_A2_div = cyc_A2 && ! sqrtOp_PA
val cyc_A1_div = cyc_A1 && ! sqrtOp_PA
val cyc_A3_sqrt = cyc_A3 && sqrtOp_PA
val cyc_A2_sqrt = cyc_A2 && sqrtOp_PA
val cyc_A1_sqrt = cyc_A1 && sqrtOp_PA
when (cyc_A1 || (cycleNum_B =/= 0.U)) {
cycleNum_B :=
Mux(cyc_A1,
Mux(sqrtOp_PA, 10.U, 6.U),
cycleNum_B - 1.U
)
}
val cyc_B10_sqrt = (cycleNum_B === 10.U)
val cyc_B9_sqrt = (cycleNum_B === 9.U)
val cyc_B8_sqrt = (cycleNum_B === 8.U)
val cyc_B7_sqrt = (cycleNum_B === 7.U)
val cyc_B6 = (cycleNum_B === 6.U)
val cyc_B5 = (cycleNum_B === 5.U)
val cyc_B4 = (cycleNum_B === 4.U)
val cyc_B3 = (cycleNum_B === 3.U)
val cyc_B2 = (cycleNum_B === 2.U)
val cyc_B1 = (cycleNum_B === 1.U)
val cyc_B6_div = cyc_B6 && valid_PA && ! sqrtOp_PA
val cyc_B5_div = cyc_B5 && valid_PA && ! sqrtOp_PA
val cyc_B4_div = cyc_B4 && valid_PA && ! sqrtOp_PA
val cyc_B3_div = cyc_B3 && ! sqrtOp_PB
val cyc_B2_div = cyc_B2 && ! sqrtOp_PB
val cyc_B1_div = cyc_B1 && ! sqrtOp_PB
val cyc_B6_sqrt = cyc_B6 && valid_PB && sqrtOp_PB
val cyc_B5_sqrt = cyc_B5 && valid_PB && sqrtOp_PB
val cyc_B4_sqrt = cyc_B4 && valid_PB && sqrtOp_PB
val cyc_B3_sqrt = cyc_B3 && sqrtOp_PB
val cyc_B2_sqrt = cyc_B2 && sqrtOp_PB
val cyc_B1_sqrt = cyc_B1 && sqrtOp_PB
when (cyc_B1 || (cycleNum_C =/= 0.U)) {
cycleNum_C :=
Mux(cyc_B1, Mux(sqrtOp_PB, 6.U, 5.U), cycleNum_C - 1.U)
}
val cyc_C6_sqrt = (cycleNum_C === 6.U)
val cyc_C5 = (cycleNum_C === 5.U)
val cyc_C4 = (cycleNum_C === 4.U)
val cyc_C3 = (cycleNum_C === 3.U)
val cyc_C2 = (cycleNum_C === 2.U)
val cyc_C1 = (cycleNum_C === 1.U)
val cyc_C5_div = cyc_C5 && ! sqrtOp_PB
val cyc_C4_div = cyc_C4 && ! sqrtOp_PB
val cyc_C3_div = cyc_C3 && ! sqrtOp_PB
val cyc_C2_div = cyc_C2 && ! sqrtOp_PC
val cyc_C1_div = cyc_C1 && ! sqrtOp_PC
val cyc_C5_sqrt = cyc_C5 && sqrtOp_PB
val cyc_C4_sqrt = cyc_C4 && sqrtOp_PB
val cyc_C3_sqrt = cyc_C3 && sqrtOp_PB
val cyc_C2_sqrt = cyc_C2 && sqrtOp_PC
val cyc_C1_sqrt = cyc_C1 && sqrtOp_PC
when (cyc_C1 || (cycleNum_E =/= 0.U)) {
cycleNum_E := Mux(cyc_C1, 4.U, cycleNum_E - 1.U)
}
val cyc_E4 = (cycleNum_E === 4.U)
val cyc_E3 = (cycleNum_E === 3.U)
val cyc_E2 = (cycleNum_E === 2.U)
val cyc_E1 = (cycleNum_E === 1.U)
val cyc_E4_div = cyc_E4 && ! sqrtOp_PC
val cyc_E3_div = cyc_E3 && ! sqrtOp_PC
val cyc_E2_div = cyc_E2 && ! sqrtOp_PC
val cyc_E1_div = cyc_E1 && ! sqrtOp_PC
val cyc_E4_sqrt = cyc_E4 && sqrtOp_PC
val cyc_E3_sqrt = cyc_E3 && sqrtOp_PC
val cyc_E2_sqrt = cyc_E2 && sqrtOp_PC
val cyc_E1_sqrt = cyc_E1 && sqrtOp_PC
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val entering_PA =
entering_PA_normalCase || (cyc_S && (valid_PA || ! ready_PB))
when (entering_PA || leaving_PA) {
valid_PA := entering_PA
}
when (entering_PA) {
sqrtOp_PA := io.sqrtOp
majorExc_PA := majorExc_S
isNaN_PA := isNaN_S
isInf_PA := isInf_S
isZero_PA := isZero_S
sign_PA := sign_S
}
when (entering_PA_normalCase) {
sExp_PA := Mux(io.sqrtOp, rawB_S.sExp, sSatExpQuot_S_div)
fractB_PA := rawB_S.sig(51, 0)
roundingMode_PA := io.roundingMode
}
when (entering_PA_normalCase_div) {
fractA_PA := rawA_S.sig(51, 0)
}
val normalCase_PA = ! isNaN_PA && ! isInf_PA && ! isZero_PA
val sigA_PA = 1.U(1.W) ## fractA_PA
val sigB_PA = 1.U(1.W) ## fractB_PA
val valid_normalCase_leaving_PA = cyc_B4_div || cyc_B7_sqrt
val valid_leaving_PA =
Mux(normalCase_PA, valid_normalCase_leaving_PA, ready_PB)
leaving_PA := valid_PA && valid_leaving_PA
ready_PA := ! valid_PA || valid_leaving_PA
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val entering_PB_S =
cyc_S && ! normalCase_S && ! valid_PA &&
(leaving_PB || (! valid_PB && ! ready_PC))
val entering_PB_normalCase =
valid_PA && normalCase_PA && valid_normalCase_leaving_PA
val entering_PB = entering_PB_S || leaving_PA
when (entering_PB || leaving_PB) {
valid_PB := entering_PB
}
when (entering_PB) {
sqrtOp_PB := Mux(valid_PA, sqrtOp_PA, io.sqrtOp )
majorExc_PB := Mux(valid_PA, majorExc_PA, majorExc_S)
isNaN_PB := Mux(valid_PA, isNaN_PA, isNaN_S )
isInf_PB := Mux(valid_PA, isInf_PA, isInf_S )
isZero_PB := Mux(valid_PA, isZero_PA, isZero_S )
sign_PB := Mux(valid_PA, sign_PA, sign_S )
}
when (entering_PB_normalCase) {
sExp_PB := sExp_PA
bit0FractA_PB := fractA_PA(0)
fractB_PB := fractB_PA
roundingMode_PB := Mux(valid_PA, roundingMode_PA, io.roundingMode)
}
val normalCase_PB = ! isNaN_PB && ! isInf_PB && ! isZero_PB
val valid_normalCase_leaving_PB = cyc_C3
val valid_leaving_PB =
Mux(normalCase_PB, valid_normalCase_leaving_PB, ready_PC)
leaving_PB := valid_PB && valid_leaving_PB
ready_PB := ! valid_PB || valid_leaving_PB
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val entering_PC_S =
cyc_S && ! normalCase_S && ! valid_PA && ! valid_PB && ready_PC
val entering_PC_normalCase =
valid_PB && normalCase_PB && valid_normalCase_leaving_PB
val entering_PC = entering_PC_S || leaving_PB
when (entering_PC || leaving_PC) {
valid_PC := entering_PC
}
when (entering_PC) {
sqrtOp_PC := Mux(valid_PB, sqrtOp_PB, io.sqrtOp )
majorExc_PC := Mux(valid_PB, majorExc_PB, majorExc_S)
isNaN_PC := Mux(valid_PB, isNaN_PB, isNaN_S )
isInf_PC := Mux(valid_PB, isInf_PB, isInf_S )
isZero_PC := Mux(valid_PB, isZero_PB, isZero_S )
sign_PC := Mux(valid_PB, sign_PB, sign_S )
}
when (entering_PC_normalCase) {
sExp_PC := sExp_PB
bit0FractA_PC := bit0FractA_PB
fractB_PC := fractB_PB
roundingMode_PC := Mux(valid_PB, roundingMode_PB, io.roundingMode)
}
val normalCase_PC = ! isNaN_PC && ! isInf_PC && ! isZero_PC
val sigB_PC = 1.U(1.W) ## fractB_PC
val valid_leaving_PC = ! normalCase_PC || cyc_E1
leaving_PC := valid_PC && valid_leaving_PC
ready_PC := ! valid_PC || valid_leaving_PC
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
//*** NEED TO COMPUTE AS MUCH AS POSSIBLE IN PREVIOUS CYCLE?:
io.inReady_div :=
//*** REPLACE ALL OF '! cyc_B*_sqrt' BY '! (valid_PB && sqrtOp_PB)'?:
ready_PA && ! cyc_B7_sqrt && ! cyc_B6_sqrt && ! cyc_B5_sqrt &&
! cyc_B4_sqrt && ! cyc_B3 && ! cyc_B2 && ! cyc_B1_sqrt &&
! cyc_C5 && ! cyc_C4
io.inReady_sqrt :=
ready_PA && ! cyc_B6_sqrt && ! cyc_B5_sqrt && ! cyc_B4_sqrt &&
! cyc_B2_div && ! cyc_B1_sqrt
/*------------------------------------------------------------------------
| Macrostage A, built around a 9x9-bit multiplier-adder.
*------------------------------------------------------------------------*/
val zFractB_A4_div = Mux(cyc_A4_div, rawB_S.sig(51, 0), 0.U)
val zLinPiece_0_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 0.U)
val zLinPiece_1_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 1.U)
val zLinPiece_2_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 2.U)
val zLinPiece_3_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 3.U)
val zLinPiece_4_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 4.U)
val zLinPiece_5_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 5.U)
val zLinPiece_6_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 6.U)
val zLinPiece_7_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 7.U)
val zK1_A4_div =
Mux(zLinPiece_0_A4_div, "h1C7".U, 0.U) |
Mux(zLinPiece_1_A4_div, "h16C".U, 0.U) |
Mux(zLinPiece_2_A4_div, "h12A".U, 0.U) |
Mux(zLinPiece_3_A4_div, "h0F8".U, 0.U) |
Mux(zLinPiece_4_A4_div, "h0D2".U, 0.U) |
Mux(zLinPiece_5_A4_div, "h0B4".U, 0.U) |
Mux(zLinPiece_6_A4_div, "h09C".U, 0.U) |
Mux(zLinPiece_7_A4_div, "h089".U, 0.U)
val zComplFractK0_A4_div =
Mux(zLinPiece_0_A4_div, ~"hFE3".U(12.W), 0.U) |
Mux(zLinPiece_1_A4_div, ~"hC5D".U(12.W), 0.U) |
Mux(zLinPiece_2_A4_div, ~"h98A".U(12.W), 0.U) |
Mux(zLinPiece_3_A4_div, ~"h739".U(12.W), 0.U) |
Mux(zLinPiece_4_A4_div, ~"h54B".U(12.W), 0.U) |
Mux(zLinPiece_5_A4_div, ~"h3A9".U(12.W), 0.U) |
Mux(zLinPiece_6_A4_div, ~"h242".U(12.W), 0.U) |
Mux(zLinPiece_7_A4_div, ~"h10B".U(12.W), 0.U)
val zFractB_A7_sqrt = Mux(cyc_A7_sqrt, rawB_S.sig(51, 0), 0.U)
val zQuadPiece_0_A7_sqrt =
cyc_A7_sqrt && ! rawB_S.sExp(0) && ! rawB_S.sig(51)
val zQuadPiece_1_A7_sqrt =
cyc_A7_sqrt && ! rawB_S.sExp(0) && rawB_S.sig(51)
val zQuadPiece_2_A7_sqrt =
cyc_A7_sqrt && rawB_S.sExp(0) && ! rawB_S.sig(51)
val zQuadPiece_3_A7_sqrt = cyc_A7_sqrt && rawB_S.sExp(0) && rawB_S.sig(51)
val zK2_A7_sqrt =
Mux(zQuadPiece_0_A7_sqrt, "h1C8".U, 0.U) |
Mux(zQuadPiece_1_A7_sqrt, "h0C1".U, 0.U) |
Mux(zQuadPiece_2_A7_sqrt, "h143".U, 0.U) |
Mux(zQuadPiece_3_A7_sqrt, "h089".U, 0.U)
val zComplK1_A7_sqrt =
Mux(zQuadPiece_0_A7_sqrt, ~"h3D0".U(10.W), 0.U) |
Mux(zQuadPiece_1_A7_sqrt, ~"h220".U(10.W), 0.U) |
Mux(zQuadPiece_2_A7_sqrt, ~"h2B2".U(10.W), 0.U) |
Mux(zQuadPiece_3_A7_sqrt, ~"h181".U(10.W), 0.U)
val zQuadPiece_0_A6_sqrt = cyc_A6_sqrt && ! sExp_PA(0) && ! sigB_PA(51)
val zQuadPiece_1_A6_sqrt = cyc_A6_sqrt && ! sExp_PA(0) && sigB_PA(51)
val zQuadPiece_2_A6_sqrt = cyc_A6_sqrt && sExp_PA(0) && ! sigB_PA(51)
val zQuadPiece_3_A6_sqrt = cyc_A6_sqrt && sExp_PA(0) && sigB_PA(51)
val zComplFractK0_A6_sqrt =
Mux(zQuadPiece_0_A6_sqrt, ~"h1FE5".U(13.W), 0.U) |
Mux(zQuadPiece_1_A6_sqrt, ~"h1435".U(13.W), 0.U) |
Mux(zQuadPiece_2_A6_sqrt, ~"h0D2C".U(13.W), 0.U) |
Mux(zQuadPiece_3_A6_sqrt, ~"h04E8".U(13.W), 0.U)
val mulAdd9A_A =
zFractB_A4_div(48, 40) | zK2_A7_sqrt |
Mux(! cyc_S, nextMulAdd9A_A, 0.U)
val mulAdd9B_A =
zK1_A4_div | zFractB_A7_sqrt(50, 42) |
Mux(! cyc_S, nextMulAdd9B_A, 0.U)
val mulAdd9C_A =
//*** ADJUST CONSTANTS SO 'Fill'S AREN'T NEEDED:
zComplK1_A7_sqrt ## Fill(10, cyc_A7_sqrt) |
Cat(cyc_A6_sqrt, zComplFractK0_A6_sqrt, Fill(6, cyc_A6_sqrt)) |
Cat(cyc_A4_div, zComplFractK0_A4_div, Fill(8, cyc_A4_div )) |
Mux(cyc_A5_sqrt, (1<<18).U +& (fractR0_A<<10), 0.U) |
Mux(cyc_A4_sqrt && ! hiSqrR0_A_sqrt(9), (1<<10).U, 0.U) |
Mux((cyc_A4_sqrt && hiSqrR0_A_sqrt(9)) || cyc_A3_div,
sigB_PA(46, 26) + (1<<10).U,
0.U
) |
Mux(cyc_A3_sqrt || cyc_A2, partNegSigma0_A, 0.U) |
Mux(cyc_A1_sqrt, fractR0_A<<16, 0.U) |
Mux(cyc_A1_div, fractR0_A<<15, 0.U)
val loMulAdd9Out_A = mulAdd9A_A * mulAdd9B_A +& mulAdd9C_A(17, 0)
val mulAdd9Out_A =
Cat(Mux(loMulAdd9Out_A(18),
mulAdd9C_A(24, 18) + 1.U,
mulAdd9C_A(24, 18)
),
loMulAdd9Out_A(17, 0)
)
val zFractR0_A6_sqrt =
Mux(cyc_A6_sqrt && mulAdd9Out_A(19), ~(mulAdd9Out_A>>10), 0.U)
/*------------------------------------------------------------------------
| ('sqrR0_A5_sqrt' is usually >= 1, but not always.)
*------------------------------------------------------------------------*/
val sqrR0_A5_sqrt = Mux(sExp_PA(0), mulAdd9Out_A<<1, mulAdd9Out_A)
val zFractR0_A4_div =
Mux(cyc_A4_div && mulAdd9Out_A(20), ~(mulAdd9Out_A>>11), 0.U)
val zSigma0_A2 =
Mux(cyc_A2 && mulAdd9Out_A(11), ~(mulAdd9Out_A>>2), 0.U)
val r1_A1 = (1<<15).U | Mux(sqrtOp_PA, mulAdd9Out_A>>10, mulAdd9Out_A>>9)
val ER1_A1_sqrt = Mux(sExp_PA(0), r1_A1<<1, r1_A1)
when (cyc_A6_sqrt || cyc_A4_div) {
fractR0_A := zFractR0_A6_sqrt | zFractR0_A4_div
}
when (cyc_A5_sqrt) {
hiSqrR0_A_sqrt := sqrR0_A5_sqrt>>10
}
when (cyc_A4_sqrt || cyc_A3) {
partNegSigma0_A := Mux(cyc_A4_sqrt, mulAdd9Out_A, mulAdd9Out_A>>9)
}
when (
cyc_A7_sqrt || cyc_A6_sqrt || cyc_A5_sqrt || cyc_A4 || cyc_A3 || cyc_A2
) {
nextMulAdd9A_A :=
Mux(cyc_A7_sqrt, ~mulAdd9Out_A>>11, 0.U) |
zFractR0_A6_sqrt |
Mux(cyc_A4_sqrt, sigB_PA(43, 35), 0.U) |
zFractB_A4_div(43, 35) |
Mux(cyc_A5_sqrt || cyc_A3, sigB_PA(52, 44), 0.U) |
zSigma0_A2
}
when (cyc_A7_sqrt || cyc_A6_sqrt || cyc_A5_sqrt || cyc_A4 || cyc_A2) {
nextMulAdd9B_A :=
zFractB_A7_sqrt(50, 42) |
zFractR0_A6_sqrt |
Mux(cyc_A5_sqrt, sqrR0_A5_sqrt(9, 1), 0.U) |
zFractR0_A4_div |
Mux(cyc_A4_sqrt, hiSqrR0_A_sqrt(8, 0), 0.U) |
Mux(cyc_A2, Cat(1.U(1.W), fractR0_A(8, 1)), 0.U)
}
when (cyc_A1_sqrt) {
ER1_B_sqrt := ER1_A1_sqrt
}
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
io.latchMulAddA_0 :=
cyc_A1 || cyc_B7_sqrt || cyc_B6_div || cyc_B4 || cyc_B3 ||
cyc_C6_sqrt || cyc_C4 || cyc_C1
io.mulAddA_0 :=
Mux(cyc_A1_sqrt, ER1_A1_sqrt<<36, 0.U) | // 52:36
Mux(cyc_B7_sqrt || cyc_A1_div, sigB_PA, 0.U) | // 52:0
Mux(cyc_B6_div, sigA_PA, 0.U) | // 52:0
zSigma1_B4(45, 12) | // 33:0
//*** ONLY 30 BITS NEEDED IN CYCLE C6:
Mux(cyc_B3 || cyc_C6_sqrt, sigXNU_B3_CX(57, 12), 0.U) | // 45:0
Mux(cyc_C4_div, sigXN_C(57, 25)<<13, 0.U) | // 45:13
Mux(cyc_C4_sqrt, u_C_sqrt<<15, 0.U) | // 45:15
Mux(cyc_C1_div, sigB_PC, 0.U) | // 52:0
zComplSigT_C1_sqrt // 53:0
io.latchMulAddB_0 :=
cyc_A1 || cyc_B7_sqrt || cyc_B6_sqrt || cyc_B4 ||
cyc_C6_sqrt || cyc_C4 || cyc_C1
io.mulAddB_0 :=
Mux(cyc_A1, r1_A1<<36, 0.U) | // 51:36
Mux(cyc_B7_sqrt, ESqrR1_B_sqrt<<19, 0.U) | // 50:19
Mux(cyc_B6_sqrt, ER1_B_sqrt<<36, 0.U) | // 52:36
zSigma1_B4 | // 45:0
Mux(cyc_C6_sqrt, sqrSigma1_C(30, 1), 0.U) | // 29:0
Mux(cyc_C4, sqrSigma1_C, 0.U) | // 32:0
zComplSigT_C1 // 53:0
io.usingMulAdd :=
Cat(cyc_A4 || cyc_A3_div || cyc_A1_div ||
cyc_B10_sqrt || cyc_B9_sqrt || cyc_B7_sqrt || cyc_B6 ||
cyc_B5_sqrt || cyc_B3_sqrt || cyc_B2_div || cyc_B1_sqrt ||
cyc_C4,
cyc_A3 || cyc_A2_div ||
cyc_B9_sqrt || cyc_B8_sqrt || cyc_B6 || cyc_B5 ||
cyc_B4_sqrt || cyc_B2_sqrt || cyc_B1_div || cyc_C6_sqrt ||
cyc_C3,
cyc_A2 || cyc_A1_div ||
cyc_B8_sqrt || cyc_B7_sqrt || cyc_B5 || cyc_B4 ||
cyc_B3_sqrt || cyc_B1_sqrt || cyc_C5 ||
cyc_C2,
io.latchMulAddA_0 || cyc_B6 || cyc_B2_sqrt
)
io.mulAddC_2 :=
Mux(cyc_B1, sigX1_B<<47, 0.U) |
Mux(cyc_C6_sqrt, sigX1_B<<46, 0.U) |
Mux(cyc_C4_sqrt || cyc_C2, sigXN_C<<47, 0.U) |
Mux(cyc_E3_div && ! E_E_div, bit0FractA_PC<<53, 0.U) |
Mux(cyc_E3_sqrt,
(Mux(sExp_PC(0),
sigB_PC(0)<<1,
(sigB_PC(1) ^ sigB_PC(0)) ## sigB_PC(0)
) ^ ((~ sigT_E(0))<<1)
)<<54,
0.U
)
val ESqrR1_B8_sqrt = io.mulAddResult_3(103, 72)
zSigma1_B4 := Mux(cyc_B4, ~io.mulAddResult_3(90, 45), 0.U)
val sqrSigma1_B1 = io.mulAddResult_3(79, 47)
sigXNU_B3_CX := io.mulAddResult_3(104, 47) // x1, x2, u (sqrt), xT'
val E_C1_div = ! io.mulAddResult_3(104)
zComplSigT_C1 :=
Mux((cyc_C1_div && ! E_C1_div) || cyc_C1_sqrt,
~io.mulAddResult_3(104, 51),
0.U
) |
Mux(cyc_C1_div && E_C1_div, ~io.mulAddResult_3(102, 50), 0.U)
zComplSigT_C1_sqrt :=
Mux(cyc_C1_sqrt, ~io.mulAddResult_3(104, 51), 0.U)
/*------------------------------------------------------------------------
| (For square root, 'sigT_C1' will usually be >= 1, but not always.)
*------------------------------------------------------------------------*/
val sigT_C1 = ~zComplSigT_C1
val remT_E2 = io.mulAddResult_3(55, 0)
when (cyc_B8_sqrt) {
ESqrR1_B_sqrt := ESqrR1_B8_sqrt
}
when (cyc_B3) {
sigX1_B := sigXNU_B3_CX
}
when (cyc_B1) {
sqrSigma1_C := sqrSigma1_B1
}
when (cyc_C6_sqrt || cyc_C5_div || cyc_C3_sqrt) {
sigXN_C := sigXNU_B3_CX
}
when (cyc_C5_sqrt) {
u_C_sqrt := sigXNU_B3_CX(56, 26)
}
when (cyc_C1) {
E_E_div := E_C1_div
sigT_E := sigT_C1
}
when (cyc_E2) {
isNegRemT_E := Mux(sqrtOp_PC, remT_E2(55), remT_E2(53))
isZeroRemT_E :=
(remT_E2(53, 0) === 0.U) &&
(! sqrtOp_PC || (remT_E2(55, 54) === 0.U))
}
/*------------------------------------------------------------------------
| T is the lower-bound "trial" result value, with 54 bits of precision.
| It is known that the true unrounded result is within the range of
| (T, T + (2 ulps of 54 bits)). X is defined as the best estimate,
| = T + (1 ulp), which is exactly in the middle of the possible range.
*------------------------------------------------------------------------*/
val trueLtX_E1 =
Mux(sqrtOp_PC, ! isNegRemT_E && ! isZeroRemT_E, isNegRemT_E)
val trueEqX_E1 = isZeroRemT_E
/*------------------------------------------------------------------------
| The inputs to these two values are stable for several clock cycles in
| advance, so the circuitry can be minimized at the expense of speed.
*** ANY WAY TO TELL THIS TO THE TOOLS?
*------------------------------------------------------------------------*/
val sExpP1_PC = sExp_PC + 1.S
val sigTP1_E = sigT_E +& 1.U
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
io.rawOutValid_div := leaving_PC && ! sqrtOp_PC
io.rawOutValid_sqrt := leaving_PC && sqrtOp_PC
io.roundingModeOut := roundingMode_PC
io.invalidExc := majorExc_PC && isNaN_PC
io.infiniteExc := majorExc_PC && ! isNaN_PC
io.rawOut.isNaN := isNaN_PC
io.rawOut.isInf := isInf_PC
io.rawOut.isZero := isZero_PC
io.rawOut.sign := sign_PC
io.rawOut.sExp :=
Mux(! sqrtOp_PC && E_E_div, sExp_PC, 0.S) |
Mux(! sqrtOp_PC && ! E_E_div, sExpP1_PC, 0.S) |
Mux( sqrtOp_PC, (sExp_PC>>1) +& 1024.S, 0.S)
io.rawOut.sig := Mux(trueLtX_E1, sigT_E, sigTP1_E) ## ! trueEqX_E1
}
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
class DivSqrtRecF64_mulAddZ31(options: Int) extends Module
{
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady_div = Output(Bool())
val inReady_sqrt = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(Bits(65.W))
val b = Input(Bits(65.W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val usingMulAdd = Output(Bits(4.W))
val latchMulAddA_0 = Output(Bool())
val mulAddA_0 = Output(UInt(54.W))
val latchMulAddB_0 = Output(Bool())
val mulAddB_0 = Output(UInt(54.W))
val mulAddC_2 = Output(UInt(105.W))
val mulAddResult_3 = Input(UInt(105.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val outValid_div = Output(Bool())
val outValid_sqrt = Output(Bool())
val out = Output(Bits(65.W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val divSqrtRecF64ToRaw = Module(new DivSqrtRecF64ToRaw_mulAddZ31)
io.inReady_div := divSqrtRecF64ToRaw.io.inReady_div
io.inReady_sqrt := divSqrtRecF64ToRaw.io.inReady_sqrt
divSqrtRecF64ToRaw.io.inValid := io.inValid
divSqrtRecF64ToRaw.io.sqrtOp := io.sqrtOp
divSqrtRecF64ToRaw.io.a := io.a
divSqrtRecF64ToRaw.io.b := io.b
divSqrtRecF64ToRaw.io.roundingMode := io.roundingMode
io.usingMulAdd := divSqrtRecF64ToRaw.io.usingMulAdd
io.latchMulAddA_0 := divSqrtRecF64ToRaw.io.latchMulAddA_0
io.mulAddA_0 := divSqrtRecF64ToRaw.io.mulAddA_0
io.latchMulAddB_0 := divSqrtRecF64ToRaw.io.latchMulAddB_0
io.mulAddB_0 := divSqrtRecF64ToRaw.io.mulAddB_0
io.mulAddC_2 := divSqrtRecF64ToRaw.io.mulAddC_2
divSqrtRecF64ToRaw.io.mulAddResult_3 := io.mulAddResult_3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.outValid_div := divSqrtRecF64ToRaw.io.rawOutValid_div
io.outValid_sqrt := divSqrtRecF64ToRaw.io.rawOutValid_sqrt
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(11, 53, flRoundOpt_sigMSBitAlwaysZero))
roundRawFNToRecFN.io.invalidExc := divSqrtRecF64ToRaw.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := divSqrtRecF64ToRaw.io.infiniteExc
roundRawFNToRecFN.io.in := divSqrtRecF64ToRaw.io.rawOut
roundRawFNToRecFN.io.roundingMode := divSqrtRecF64ToRaw.io.roundingModeOut
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
} | module DivSqrtRecF64_mulAddZ31(
input clock,
input reset,
output io_inReady_div,
output io_inReady_sqrt,
input io_inValid,
input io_sqrtOp,
input [64:0] io_a,
input [64:0] io_b,
input [2:0] io_roundingMode,
output [3:0] io_usingMulAdd,
output io_latchMulAddA_0,
output [53:0] io_mulAddA_0,
output io_latchMulAddB_0,
output [53:0] io_mulAddB_0,
output [104:0] io_mulAddC_2,
input [104:0] io_mulAddResult_3,
output io_outValid_div,
output io_outValid_sqrt,
output [64:0] io_out,
output [4:0] io_exceptionFlags
);
wire [2:0] _divSqrtRecF64ToRaw_io_roundingModeOut;
wire _divSqrtRecF64ToRaw_io_invalidExc;
wire _divSqrtRecF64ToRaw_io_infiniteExc;
wire _divSqrtRecF64ToRaw_io_rawOut_isNaN;
wire _divSqrtRecF64ToRaw_io_rawOut_isInf;
wire _divSqrtRecF64ToRaw_io_rawOut_isZero;
wire _divSqrtRecF64ToRaw_io_rawOut_sign;
wire [12:0] _divSqrtRecF64ToRaw_io_rawOut_sExp;
wire [55:0] _divSqrtRecF64ToRaw_io_rawOut_sig;
DivSqrtRecF64ToRaw_mulAddZ31 divSqrtRecF64ToRaw (
.clock (clock),
.reset (reset),
.io_inReady_div (io_inReady_div),
.io_inReady_sqrt (io_inReady_sqrt),
.io_inValid (io_inValid),
.io_sqrtOp (io_sqrtOp),
.io_a (io_a),
.io_b (io_b),
.io_roundingMode (io_roundingMode),
.io_usingMulAdd (io_usingMulAdd),
.io_latchMulAddA_0 (io_latchMulAddA_0),
.io_mulAddA_0 (io_mulAddA_0),
.io_latchMulAddB_0 (io_latchMulAddB_0),
.io_mulAddB_0 (io_mulAddB_0),
.io_mulAddC_2 (io_mulAddC_2),
.io_mulAddResult_3 (io_mulAddResult_3),
.io_rawOutValid_div (io_outValid_div),
.io_rawOutValid_sqrt (io_outValid_sqrt),
.io_roundingModeOut (_divSqrtRecF64ToRaw_io_roundingModeOut),
.io_invalidExc (_divSqrtRecF64ToRaw_io_invalidExc),
.io_infiniteExc (_divSqrtRecF64ToRaw_io_infiniteExc),
.io_rawOut_isNaN (_divSqrtRecF64ToRaw_io_rawOut_isNaN),
.io_rawOut_isInf (_divSqrtRecF64ToRaw_io_rawOut_isInf),
.io_rawOut_isZero (_divSqrtRecF64ToRaw_io_rawOut_isZero),
.io_rawOut_sign (_divSqrtRecF64ToRaw_io_rawOut_sign),
.io_rawOut_sExp (_divSqrtRecF64ToRaw_io_rawOut_sExp),
.io_rawOut_sig (_divSqrtRecF64ToRaw_io_rawOut_sig)
);
RoundRawFNToRecFN_e11_s53_1 roundRawFNToRecFN (
.io_invalidExc (_divSqrtRecF64ToRaw_io_invalidExc),
.io_infiniteExc (_divSqrtRecF64ToRaw_io_infiniteExc),
.io_in_isNaN (_divSqrtRecF64ToRaw_io_rawOut_isNaN),
.io_in_isInf (_divSqrtRecF64ToRaw_io_rawOut_isInf),
.io_in_isZero (_divSqrtRecF64ToRaw_io_rawOut_isZero),
.io_in_sign (_divSqrtRecF64ToRaw_io_rawOut_sign),
.io_in_sExp (_divSqrtRecF64ToRaw_io_rawOut_sExp),
.io_in_sig (_divSqrtRecF64ToRaw_io_rawOut_sig),
.io_roundingMode (_divSqrtRecF64ToRaw_io_roundingModeOut),
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
} | module hi_us_0(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input [6:0] W0_addr,
input W0_clk,
input [3:0] W0_data,
input [3:0] W0_mask
);
hi_us_ext hi_us_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (1'h1),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
case class FPUParams(
minFLen: Int = 32,
fLen: Int = 64,
divSqrt: Boolean = true,
sfmaLatency: Int = 3,
dfmaLatency: Int = 4,
fpmuLatency: Int = 2,
ifpuLatency: Int = 2
)
object FPConstants
{
val RM_SZ = 3
val FLAGS_SZ = 5
}
trait HasFPUCtrlSigs {
val ldst = Bool()
val wen = Bool()
val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val swap12 = Bool()
val swap23 = Bool()
val typeTagIn = UInt(2.W)
val typeTagOut = UInt(2.W)
val fromint = Bool()
val toint = Bool()
val fastpipe = Bool()
val fma = Bool()
val div = Bool()
val sqrt = Bool()
val wflags = Bool()
val vec = Bool()
}
class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val inst = Input(Bits(32.W))
val sigs = Output(new FPUCtrlSigs())
})
private val X2 = BitPat.dontCare(2)
val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)
val h: Array[(BitPat, List[BitPat])] =
Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),
FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),
FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),
FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),
FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),
FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),
FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),
FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))
val f: Array[(BitPat, List[BitPat])] =
Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),
FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),
FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),
FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),
FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),
FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))
val d: Array[(BitPat, List[BitPat])] =
Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),
FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),
FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),
FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),
FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),
FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),
FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),
FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))
val fcvt_hd: Array[(BitPat, List[BitPat])] =
Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),
FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))
val vfmv_f_s: Array[(BitPat, List[BitPat])] =
Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))
val insns = ((minFLen, fLen) match {
case (32, 32) => f
case (16, 32) => h ++ f
case (32, 64) => f ++ d
case (16, 64) => h ++ f ++ d ++ fcvt_hd
case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration")
}) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())
val decoder = DecodeLogic(io.inst, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,
s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)
sigs zip decoder map {case(s,d) => s := d}
}
class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val time = Input(UInt(xLen.W))
val inst = Input(Bits(32.W))
val fromint_data = Input(Bits(xLen.W))
val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))
val v_sew = Input(UInt(3.W))
val store_data = Output(Bits(fLen.W))
val toint_data = Output(Bits(xLen.W))
val ll_resp_val = Input(Bool())
val ll_resp_type = Input(Bits(3.W))
val ll_resp_tag = Input(UInt(5.W))
val ll_resp_data = Input(Bits(fLen.W))
val valid = Input(Bool())
val fcsr_rdy = Output(Bool())
val nack_mem = Output(Bool())
val illegal_rm = Output(Bool())
val killx = Input(Bool())
val killm = Input(Bool())
val dec = Output(new FPUCtrlSigs())
val sboard_set = Output(Bool())
val sboard_clr = Output(Bool())
val sboard_clra = Output(UInt(5.W))
val keep_clock_enabled = Input(Bool())
}
class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs
val cp_resp = Decoupled(new FPResult())
}
class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
val data = Bits((fLen+1).W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val typ = Bits(2.W)
val in1 = Bits(xLen.W)
}
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val fmaCmd = Bits(2.W)
val typ = Bits(2.W)
val fmt = Bits(2.W)
val in1 = Bits((fLen+1).W)
val in2 = Bits((fLen+1).W)
val in3 = Bits((fLen+1).W)
}
case class FType(exp: Int, sig: Int) {
def ieeeWidth = exp + sig
def recodedWidth = ieeeWidth + 1
def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)
def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)
def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR
def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)
def classify(x: UInt) = {
val sign = x(sig + exp)
val code = x(exp + sig - 1, exp + sig - 3)
val codeHi = code(2, 1)
val isSpecial = codeHi === 3.U
val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U
val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn
val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U
val isZero = code === 0.U
val isInf = isSpecial && !code(0)
val isNaN = code.andR
val isSNaN = isNaN && !x(sig-2)
val isQNaN = isNaN && x(sig-2)
Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,
isSubnormal && !sign, isZero && !sign, isZero && sign,
isSubnormal && sign, isNormal && sign, isInf && sign)
}
// convert between formats, ignoring rounding, range, NaN
def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {
val sign = x(sig + exp)
val fractIn = x(sig - 2, 0)
val expIn = x(sig + exp - 1, sig - 1)
val fractOut = fractIn << to.sig >> sig
val expOut = {
val expCode = expIn(exp, exp - 2)
val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U
Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))
}
Cat(sign, expOut, fractOut)
}
private def ieeeBundle = {
val expWidth = exp
class IEEEBundle extends Bundle {
val sign = Bool()
val exp = UInt(expWidth.W)
val sig = UInt((ieeeWidth-expWidth-1).W)
}
new IEEEBundle
}
def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)
def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)
def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)
}
object FType {
val H = new FType(5, 11)
val S = new FType(8, 24)
val D = new FType(11, 53)
val all = List(H, S, D)
}
trait HasFPUParameters {
require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))
val minFLen: Int
val fLen: Int
def xLen: Int
val minXLen = 32
val nIntTypes = log2Ceil(xLen/minXLen) + 1
def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)
def minType = floatTypes.head
def maxType = floatTypes.last
def prevType(t: FType) = floatTypes(typeTag(t) - 1)
def maxExpWidth = maxType.exp
def maxSigWidth = maxType.sig
def typeTag(t: FType) = floatTypes.indexOf(t)
def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U
def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U
// typeTag
def H = typeTagGroup(FType.H)
def S = typeTagGroup(FType.S)
def D = typeTagGroup(FType.D)
def I = typeTag(maxType).U
private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR
private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {
require(xt.ieeeWidth == 2 * yt.ieeeWidth)
val swizzledNaN = Cat(
x(xt.sig + xt.exp, xt.sig + xt.exp - 3),
x(xt.sig - 2, yt.recodedWidth - 1).andR,
x(xt.sig + xt.exp - 5, xt.sig),
y(yt.recodedWidth - 2),
x(xt.sig - 2, yt.recodedWidth - 1),
y(yt.recodedWidth - 1),
y(yt.recodedWidth - 3, 0))
Mux(xt.isNaN(x), swizzledNaN, x)
}
// implement NaN unboxing for FU inputs
def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {
val outType = exactType.getOrElse(maxType)
def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {
val prev =
if (t == minType) {
Seq()
} else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prev = helper(unswizzled, prevT)
val isbox = isBox(x, t)
prev.map(p => (isbox && p._1, p._2))
}
prev :+ (true.B, t.unsafeConvert(x, outType))
}
val (oks, floats) = helper(x, maxType).unzip
if (exactType.isEmpty || floatTypes.size == 1) {
Mux(oks(tag), floats(tag), maxType.qNaN)
} else {
val t = exactType.get
floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)
}
}
// make sure that the redundant bits in the NaN-boxed encoding are consistent
def consistent(x: UInt): Bool = {
def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prevOK = !isBox(x, t) || helper(unswizzled, prevT)
val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR
prevOK && curOK
}
helper(x, maxType)
}
// generate a NaN box from an FU result
def box(x: UInt, t: FType): UInt = {
if (t == maxType) {
x
} else {
val nt = floatTypes(typeTag(t) + 1)
val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)
bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U
}
}
// generate a NaN box from an FU result
def box(x: UInt, tag: UInt): UInt = {
val opts = floatTypes.map(t => box(x, t))
opts(tag)
}
// zap bits that hardfloat thinks are don't-cares, but we do care about
def sanitizeNaN(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
x
} else {
val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)
Mux(t.isNaN(x), maskedNaN, x)
}
}
// implement NaN boxing and recoding for FL*/fmv.*.x
def recode(x: UInt, tag: UInt): UInt = {
def helper(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
t.recode(x)
} else {
val prevT = prevType(t)
box(t.recode(x), t, helper(x, prevT), prevT)
}
}
// fill MSBs of subword loads to emulate a wider load of a NaN-boxed value
val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)
helper(boxes(tag) | x, maxType)
}
// implement NaN unboxing and un-recoding for FS*/fmv.x.*
def ieee(x: UInt, t: FType = maxType): UInt = {
if (typeTag(t) == 0) {
t.ieee(x)
} else {
val unrecoded = t.ieee(x)
val prevT = prevType(t)
val prevRecoded = Cat(
x(prevT.recodedWidth-2),
x(t.sig-1),
x(prevT.recodedWidth-3, 0))
val prevUnrecoded = ieee(prevRecoded, prevT)
Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))
}
}
}
abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
class Output extends Bundle {
val in = new FPInput
val lt = Bool()
val store = Bits(fLen.W)
val toint = Bits(xLen.W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new Output)
})
val in = RegEnable(io.in.bits, io.in.valid)
val valid = RegNext(io.in.valid)
val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
dcmp.io.a := in.in1
dcmp.io.b := in.in2
dcmp.io.signaling := !in.rm(1)
val tag = in.typeTagOut
val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))
else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
val toint = WireDefault(toint_ieee)
val intType = WireDefault(in.fmt(0))
io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
io.out.bits.exc := 0.U
when (in.rm(0)) {
val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)
toint := classify_out | (toint_ieee >> minXLen << minXLen)
intType := false.B
}
when (in.wflags) { // feq/flt/fle, fcvt
toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)
io.out.bits.exc := dcmp.io.exceptionFlags
intType := false.B
when (!in.ren2) { // fcvt
val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
intType := cvtType
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
conv.io.in := in.in1
conv.io.roundingMode := in.rm
conv.io.signedOut := ~in.typ(0)
toint := conv.io.out
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))
for (i <- 0 until nIntTypes-1) {
val w = minXLen << i
when (cvtType === i.U) {
val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))
narrow.io.in := in.in1
narrow.io.roundingMode := in.rm
narrow.io.signedOut := ~in.typ(0)
val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)
val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))
val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)
when (invalid) { toint := Cat(conv.io.out >> w, excOut) }
io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))
}
}
}
}
io.out.valid := valid
io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)
io.out.bits.in := in
}
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new IntToFPInput))
val out = Valid(new FPResult)
})
val in = Pipe(io.in)
val tag = in.bits.typeTagIn
val mux = Wire(new FPResult)
mux.exc := 0.U
mux.data := recode(in.bits.in1, tag)
val intValue = {
val res = WireDefault(in.bits.in1.asSInt)
for (i <- 0 until nIntTypes-1) {
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
}
}
res.asUInt
}
when (in.bits.wflags) { // fcvt
// could be improved for RVD/RVQ with a single variable-position rounding
// unit, rather than N fixed-position ones
val i2fResults = for (t <- floatTypes) yield {
val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
i2f.io.signedIn := ~in.bits.typ(0)
i2f.io.in := intValue
i2f.io.roundingMode := in.bits.rm
i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding
(sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)
}
val (data, exc) = i2fResults.unzip
val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
mux.data := dataPadded(tag)
mux.exc := exc(tag)
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
val lt = Input(Bool()) // from FPToInt
})
val in = Pipe(io.in)
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
val fsgnjMux = Wire(new FPResult)
fsgnjMux.exc := 0.U
fsgnjMux.data := fsgnj
when (in.bits.wflags) { // fmin/fmax
val isnan1 = maxType.isNaN(in.bits.in1)
val isnan2 = maxType.isNaN(in.bits.in2)
val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)
val isNaNOut = isnan1 && isnan2
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
fsgnjMux.exc := isInvalid << 4
fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
}
val inTag = in.bits.typeTagIn
val outTag = in.bits.typeTagOut
val mux = WireDefault(fsgnjMux)
for (t <- floatTypes.init) {
when (outTag === typeTag(t).U) {
mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))
}
}
when (in.bits.wflags && !in.bits.ren2) { // fcvt
if (floatTypes.size > 1) {
// widening conversions simply canonicalize NaN operands
val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)
fsgnjMux.data := widened
fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4
// narrowing conversions require rounding (for RVQ, this could be
// optimized to use a single variable-position rounding unit, rather
// than two fixed-position ones)
for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {
val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
narrower.io.in := in.bits.in1
narrower.io.roundingMode := in.bits.rm
narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding
val narrowed = sanitizeNaN(narrower.io.out, outType)
mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)
mux.exc := narrower.io.exceptionFlags
}
}
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
{
override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}"
require(latency<=2)
val io = IO(new Bundle {
val validin = Input(Bool())
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
val validout = Output(Bool())
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
val valid_stage0 = Wire(Bool())
val roundingMode_stage0 = Wire(UInt(3.W))
val detectTininess_stage0 = Wire(UInt(1.W))
val postmul_regs = if(latency>0) 1 else 0
mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits
detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits
valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
val round_regs = if(latency==2) 1 else 0
roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
io.validout := Pipe(valid_stage0, false.B, round_regs).valid
roundRawFNToRecFN.io.infiniteExc := false.B
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
class FPUFMAPipe(val latency: Int, val t: FType)
(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
require(latency>0)
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
})
val valid = RegNext(io.in.valid)
val in = Reg(new FPInput)
when (io.in.valid) {
val one = 1.U << (t.sig + t.exp - 1)
val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))
val cmd_fma = io.in.bits.ren3
val cmd_addsub = io.in.bits.swap23
in := io.in.bits
when (cmd_addsub) { in.in2 := one }
when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
}
val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
fma.io.validin := valid
fma.io.op := in.fmaCmd
fma.io.roundingMode := in.rm
fma.io.detectTininess := hardfloat.consts.tininess_afterRounding
fma.io.a := in.in1
fma.io.b := in.in2
fma.io.c := in.in3
val res = Wire(new FPResult)
res.data := sanitizeNaN(fma.io.out, t)
res.exc := fma.io.exceptionFlags
io.out := Pipe(fma.io.validout, res, (latency-3) max 0)
}
class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new FPUIO)
val (useClockGating, useDebugROB) = coreParams match {
case r: RocketCoreParams =>
val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1
(r.clockGate, sz < 1)
case _ => (false, false)
}
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cp_req.valid
val gated_clock =
if (!useClockGating) clock
else ClockGate(clock, clock_en, "fpu_clock_gate")
val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.inst
val id_ctrl = WireInit(fp_decoder.io.sigs)
coreParams match { case r: RocketCoreParams => r.vector.map(v => {
val v_decode = v.decoder(p) // Only need to get ren1
v_decode.io.inst := io.inst
v_decode.io.vconfig := DontCare // core deals with this
when (v_decode.io.legal && v_decode.io.read_frs1) {
id_ctrl.ren1 := true.B
id_ctrl.swap12 := false.B
id_ctrl.toint := true.B
id_ctrl.typeTagIn := I
id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)
}
when (v_decode.io.write_frd) { id_ctrl.wen := true.B }
})}
val ex_reg_valid = RegNext(io.valid, false.B)
val ex_reg_inst = RegEnable(io.inst, io.valid)
val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
val ex_ra = List.fill(3)(Reg(UInt()))
// load/vector response
val load_wb = RegNext(io.ll_resp_val)
val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)
val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)
val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)
class FPUImpl { // entering gated-clock domain
val req_valid = ex_reg_valid || io.cp_req.valid
val ex_cp_valid = io.cp_req.fire
val mem_cp_valid = RegNext(ex_cp_valid, false.B)
val wb_cp_valid = RegNext(mem_cp_valid, false.B)
val mem_reg_valid = RegInit(false.B)
val killm = (io.killm || io.nack_mem) && !mem_cp_valid
// Kill X-stage instruction if M-stage is killed. This prevents it from
// speculatively being sent to the div-sqrt unit, which can cause priority
// inversion for two back-to-back divides, the first of which is killed.
val killx = io.killx || mem_reg_valid && killm
mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid
val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
val cp_ctrl = Wire(new FPUCtrlSigs)
cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
io.cp_resp.valid := false.B
io.cp_resp.bits.data := 0.U
io.cp_resp.bits.exc := DontCare
val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)
val mem_ctrl = RegEnable(ex_ctrl, req_valid)
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
// CoreMonitorBundle to monitor fp register file writes
val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))
frfWriteBundle.foreach { i =>
i.clock := clock
i.reset := reset
i.hartid := io.hartid
i.timer := io.time(31,0)
i.valid := false.B
i.wrenx := false.B
i.wrenf := false.B
i.excpt := false.B
}
// regfile
val regfile = Mem(32, Bits((fLen+1).W))
when (load_wb) {
val wdata = recode(load_wb_data, load_wb_typeTag)
regfile(load_wb_tag) := wdata
assert(consistent(wdata))
if (enableCommitLog)
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))
if (useDebugROB)
DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))
frfWriteBundle(0).wrdst := load_wb_tag
frfWriteBundle(0).wrenf := true.B
frfWriteBundle(0).wrdata := ieee(wdata)
}
val ex_rs = ex_ra.map(a => regfile(a))
when (io.valid) {
when (id_ctrl.ren1) {
when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }
when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }
}
when (id_ctrl.ren2) {
when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }
when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }
when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }
}
when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }
}
val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))
def fuInput(minT: Option[FType]): FPInput = {
val req = Wire(new FPInput)
val tag = ex_ctrl.typeTagIn
req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
req.rm := ex_rm
req.in1 := unbox(ex_rs(0), tag, minT)
req.in2 := unbox(ex_rs(1), tag, minT)
req.in3 := unbox(ex_rs(2), tag, minT)
req.typ := ex_reg_inst(21,20)
req.fmt := ex_reg_inst(26,25)
req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))
when (ex_cp_valid) {
req := io.cp_req.bits
when (io.cp_req.bits.swap12) {
req.in1 := io.cp_req.bits.in2
req.in2 := io.cp_req.bits.in1
}
when (io.cp_req.bits.swap23) {
req.in2 := io.cp_req.bits.in3
req.in3 := io.cp_req.bits.in2
}
}
req
}
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new FPToInt)
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
io.store_data := fpiu.io.out.bits.store
io.toint_data := fpiu.io.out.bits.toint
when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){
io.cp_resp.bits.data := fpiu.io.out.bits.toint
io.cp_resp.valid := true.B
}
val ifpu = Module(new IntToFP(cfg.ifpuLatency))
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
ifpu.io.in.bits := fpiu.io.in.bits
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
val fpmu = Module(new FPToFP(cfg.fpmuLatency))
fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val divSqrt_wen = WireDefault(false.B)
val divSqrt_inFlight = WireDefault(false.B)
val divSqrt_waddr = Reg(UInt(5.W))
val divSqrt_cp = Reg(Bool())
val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
val divSqrt_wdata = Wire(UInt((fLen+1).W))
val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
divSqrt_typeTag := DontCare
divSqrt_wdata := DontCare
divSqrt_flags := DontCare
// writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++
(fLen > 32).option({
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D
dfma.io.in.bits := fuInput(Some(dfma.t))
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)
}) ++
(minFLen == 16).option({
val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))
hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H
hfma.io.in.bits := fuInput(Some(hfma.t))
Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)
})
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
require(pipes.forall(_.lat >= offset))
pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)
}
def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)
val maxLatency = pipes.map(_.lat).max
val memLatencyMask = latencyMask(mem_ctrl, 2)
class WBInfo extends Bundle {
val rd = UInt(5.W)
val typeTag = UInt(log2Up(floatTypes.size).W)
val cp = Bool()
val pipeid = UInt(log2Ceil(pipes.size).W)
}
val wen = RegInit(0.U((maxLatency-1).W))
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback")
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
}
wen := wen >> 1
when (mem_wen) {
when (!killm) {
wen := wen >> 1 | memLatencyMask
}
for (i <- 0 until maxLatency-1) {
when (!write_port_busy && memLatencyMask(i)) {
wbInfo(i).cp := mem_cp_valid
wbInfo(i).typeTag := mem_ctrl.typeTagOut
wbInfo(i).pipeid := pipeid(mem_ctrl)
wbInfo(i).rd := mem_reg_inst(11,7)
}
}
}
val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)
val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
assert(consistent(wdata))
regfile(waddr) := wdata
if (enableCommitLog) {
printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata))
}
frfWriteBundle(1).wrdst := waddr
frfWriteBundle(1).wrenf := true.B
frfWriteBundle(1).wrdata := ieee(wdata)
}
if (useDebugROB) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
}
when (wb_cp && (wen(0) || divSqrt_wen)) {
io.cp_resp.bits.data := wdata
io.cp_resp.valid := true.B
}
assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,
s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}")
// Avoid structural hazards and nacking of external requests
// toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs
io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)
io.fcsr_flags.bits :=
Mux(wb_toint_valid, wb_toint_exc, 0.U) |
Mux(divSqrt_wen, divSqrt_flags, 0.U) |
Mux(wen(0), wexc, 0.U)
val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid
io.dec <> id_ctrl
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)
io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))
io.sboard_clra := waddr
ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
// we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U
if (cfg.divSqrt) {
val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)
when (divSqrt_inValid) {
divSqrt_waddr := mem_reg_inst(11,7)
divSqrt_cp := mem_cp_valid
}
ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")
ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard")
ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback")
for (t <- floatTypes) {
val tag = mem_ctrl.typeTagOut
val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }
divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)
divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm
divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding
when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight
when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {
divSqrt_wen := !divSqrt_killed
divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)
divSqrt_flags := divSqrt.io.exceptionFlags
divSqrt_typeTag := typeTag(t).U
}
}
when (divSqrt_killed) { divSqrt_inFlight := false.B }
} else {
when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }
}
// gate the clock
clock_en_reg := !useClockGating.B ||
io.keep_clock_enabled || // chicken bit
io.valid || // ID stage
req_valid || // EX stage
mem_reg_valid || mem_cp_valid || // MEM stage
wb_reg_valid || wb_cp_valid || // WB stage
wen.orR || divSqrt_inFlight || // post-WB stage
io.ll_resp_val // load writeback
} // leaving gated-clock domain
val fpuImpl = withClock (gated_clock) { new FPUImpl }
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FPU_$label", "Core;;" + desc)
} | module FPToFP(
input clock,
input reset,
input io_in_valid,
input io_in_bits_ren2,
input [1:0] io_in_bits_typeTagOut,
input io_in_bits_wflags,
input [2:0] io_in_bits_rm,
input [64:0] io_in_bits_in1,
input [64:0] io_in_bits_in2,
output io_out_valid,
output [64:0] io_out_bits_data,
output [4:0] io_out_bits_exc,
input io_lt
);
wire [32:0] _narrower_io_out;
wire [4:0] _narrower_io_exceptionFlags;
reg in_pipe_v;
reg in_pipe_b_ren2;
reg [1:0] in_pipe_b_typeTagOut;
reg in_pipe_b_wflags;
reg [2:0] in_pipe_b_rm;
reg [64:0] in_pipe_b_in1;
reg [64:0] in_pipe_b_in2;
wire _GEN = in_pipe_b_wflags & ~in_pipe_b_ren2;
wire [64:0] fsgnjMux_data = _GEN ? ((&(in_pipe_b_in1[63:61])) ? 65'hE008000000000000 : in_pipe_b_in1) : in_pipe_b_wflags ? ((&(in_pipe_b_in1[63:61])) & (&(in_pipe_b_in2[63:61])) ? 65'hE008000000000000 : (&(in_pipe_b_in2[63:61])) | in_pipe_b_rm[0] != io_lt & ~(&(in_pipe_b_in1[63:61])) ? in_pipe_b_in1 : in_pipe_b_in2) : {in_pipe_b_rm[1] ? in_pipe_b_in1[64] ^ in_pipe_b_in2[64] : in_pipe_b_rm[0] ^ in_pipe_b_in2[64], in_pipe_b_in1[63:0]};
reg io_out_pipe_v;
reg [64:0] io_out_pipe_b_data;
reg [4:0] io_out_pipe_b_exc;
reg io_out_pipe_pipe_v;
reg [64:0] io_out_pipe_pipe_b_data;
reg [4:0] io_out_pipe_pipe_b_exc;
reg io_out_pipe_pipe_pipe_v;
reg [64:0] io_out_pipe_pipe_pipe_b_data;
reg [4:0] io_out_pipe_pipe_pipe_b_exc;
wire _GEN_0 = in_pipe_b_typeTagOut == 2'h0;
wire [8:0] _mux_data_expOut_commonCase_T = fsgnjMux_data[60:52] - 9'h100;
always @(posedge clock) begin
if (reset) begin
in_pipe_v <= 1'h0;
io_out_pipe_v <= 1'h0;
io_out_pipe_pipe_v <= 1'h0;
io_out_pipe_pipe_pipe_v <= 1'h0;
end
else begin
in_pipe_v <= io_in_valid;
io_out_pipe_v <= in_pipe_v;
io_out_pipe_pipe_v <= io_out_pipe_v;
io_out_pipe_pipe_pipe_v <= io_out_pipe_pipe_v;
end
if (io_in_valid) begin
in_pipe_b_ren2 <= io_in_bits_ren2;
in_pipe_b_typeTagOut <= io_in_bits_typeTagOut;
in_pipe_b_wflags <= io_in_bits_wflags;
in_pipe_b_rm <= io_in_bits_rm;
in_pipe_b_in1 <= io_in_bits_in1;
in_pipe_b_in2 <= io_in_bits_in2;
end
if (in_pipe_v) begin
io_out_pipe_b_data <= _GEN_0 ? (_GEN ? {fsgnjMux_data[64:33], _narrower_io_out} : {fsgnjMux_data[64:33], fsgnjMux_data[64], fsgnjMux_data[63:61] == 3'h0 | fsgnjMux_data[63:61] > 3'h5 ? {fsgnjMux_data[63:61], _mux_data_expOut_commonCase_T[5:0]} : _mux_data_expOut_commonCase_T, fsgnjMux_data[51:29]}) : fsgnjMux_data;
io_out_pipe_b_exc <= _GEN & _GEN_0 ? _narrower_io_exceptionFlags : _GEN ? {(&(in_pipe_b_in1[63:61])) & ~(in_pipe_b_in1[51]), 4'h0} : in_pipe_b_wflags ? {(&(in_pipe_b_in1[63:61])) & ~(in_pipe_b_in1[51]) | (&(in_pipe_b_in2[63:61])) & ~(in_pipe_b_in2[51]), 4'h0} : 5'h0;
end
if (io_out_pipe_v) begin
io_out_pipe_pipe_b_data <= io_out_pipe_b_data;
io_out_pipe_pipe_b_exc <= io_out_pipe_b_exc;
end
if (io_out_pipe_pipe_v) begin
io_out_pipe_pipe_pipe_b_data <= io_out_pipe_pipe_b_data;
io_out_pipe_pipe_pipe_b_exc <= io_out_pipe_pipe_b_exc;
end
end
RecFNToRecFN narrower (
.io_in (in_pipe_b_in1),
.io_roundingMode (in_pipe_b_rm),
.io_detectTininess (1'h1),
.io_out (_narrower_io_out),
.io_exceptionFlags (_narrower_io_exceptionFlags)
);
assign io_out_valid = io_out_pipe_pipe_pipe_v;
assign io_out_bits_data = io_out_pipe_pipe_pipe_b_data;
assign io_out_bits_exc = io_out_pipe_pipe_pipe_b_exc;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
} | module cc_banks_5(
input [13:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [31:0] RW0_wdata,
output [31:0] RW0_rdata
);
cc_banks_0_ext cc_banks_0_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.subsystem.CacheBlockBytes
import freechips.rocketchip.tile.HasCoreParameters
import freechips.rocketchip.util._
case class BHTParams(
nEntries: Int = 512,
counterLength: Int = 1,
historyLength: Int = 8,
historyBits: Int = 3)
case class BTBParams(
nEntries: Int = 28,
nMatchBits: Int = 14,
nPages: Int = 6,
nRAS: Int = 6,
bhtParams: Option[BHTParams] = Some(BHTParams()),
updatesOutOfOrder: Boolean = false)
trait HasBtbParameters extends HasCoreParameters { this: InstanceId =>
val btbParams = tileParams.btb.getOrElse(BTBParams(nEntries = 0))
val matchBits = btbParams.nMatchBits max log2Ceil(p(CacheBlockBytes) * tileParams.icache.get.nSets)
val entries = btbParams.nEntries
val updatesOutOfOrder = btbParams.updatesOutOfOrder
val nPages = (btbParams.nPages + 1) / 2 * 2 // control logic assumes 2 divides pages
}
abstract class BtbModule(implicit val p: Parameters) extends Module with HasBtbParameters {
Annotated.params(this, btbParams)
}
abstract class BtbBundle(implicit val p: Parameters) extends Bundle with HasBtbParameters
class RAS(nras: Int) {
def push(addr: UInt): Unit = {
when (count < nras.U) { count := count + 1.U }
val nextPos = Mux((isPow2(nras)).B || pos < (nras-1).U, pos+1.U, 0.U)
stack(nextPos) := addr
pos := nextPos
}
def peek: UInt = stack(pos)
def pop(): Unit = when (!isEmpty) {
count := count - 1.U
pos := Mux((isPow2(nras)).B || pos > 0.U, pos-1.U, (nras-1).U)
}
def clear(): Unit = count := 0.U
def isEmpty: Bool = count === 0.U
private val count = RegInit(0.U(log2Up(nras+1).W))
private val pos = RegInit(0.U(log2Up(nras).W))
private val stack = Reg(Vec(nras, UInt()))
}
class BHTResp(implicit p: Parameters) extends BtbBundle()(p) {
val history = UInt(btbParams.bhtParams.map(_.historyLength).getOrElse(1).W)
val value = UInt(btbParams.bhtParams.map(_.counterLength).getOrElse(1).W)
def taken = value(0)
def strongly_taken = value === 1.U
}
// BHT contains table of 2-bit counters and a global history register.
// The BHT only predicts and updates when there is a BTB hit.
// The global history:
// - updated speculatively in fetch (if there's a BTB hit).
// - on a mispredict, the history register is reset (again, only if BTB hit).
// The counter table:
// - each counter corresponds with the address of the fetch packet ("fetch pc").
// - updated when a branch resolves (and BTB was a hit for that branch).
// The updating branch must provide its "fetch pc".
class BHT(params: BHTParams)(implicit val p: Parameters) extends HasCoreParameters {
def index(addr: UInt, history: UInt) = {
def hashHistory(hist: UInt) = if (params.historyLength == params.historyBits) hist else {
val k = math.sqrt(3)/2
val i = BigDecimal(k * math.pow(2, params.historyLength)).toBigInt
(i.U * hist)(params.historyLength-1, params.historyLength-params.historyBits)
}
def hashAddr(addr: UInt) = {
val hi = addr >> log2Ceil(fetchBytes)
hi(log2Ceil(params.nEntries)-1, 0) ^ (hi >> log2Ceil(params.nEntries))(1, 0)
}
hashAddr(addr) ^ (hashHistory(history) << (log2Up(params.nEntries) - params.historyBits))
}
def get(addr: UInt): BHTResp = {
val res = Wire(new BHTResp)
res.value := Mux(resetting, 0.U, table(index(addr, history)))
res.history := history
res
}
def updateTable(addr: UInt, d: BHTResp, taken: Bool): Unit = {
wen := true.B
when (!resetting) {
waddr := index(addr, d.history)
wdata := (params.counterLength match {
case 1 => taken
case 2 => Cat(taken ^ d.value(0), d.value === 1.U || d.value(1) && taken)
})
}
}
def resetHistory(d: BHTResp): Unit = {
history := d.history
}
def updateHistory(addr: UInt, d: BHTResp, taken: Bool): Unit = {
history := Cat(taken, d.history >> 1)
}
def advanceHistory(taken: Bool): Unit = {
history := Cat(taken, history >> 1)
}
private val table = Mem(params.nEntries, UInt(params.counterLength.W))
val history = RegInit(0.U(params.historyLength.W))
private val reset_waddr = RegInit(0.U((params.nEntries.log2+1).W))
private val resetting = !reset_waddr(params.nEntries.log2)
private val wen = WireInit(resetting)
private val waddr = WireInit(reset_waddr)
private val wdata = WireInit(0.U)
when (resetting) { reset_waddr := reset_waddr + 1.U }
when (wen) { table(waddr) := wdata }
}
object CFIType {
def SZ = 2
def apply() = UInt(SZ.W)
def branch = 0.U
def jump = 1.U
def call = 2.U
def ret = 3.U
}
// BTB update occurs during branch resolution (and only on a mispredict).
// - "pc" is what future fetch PCs will tag match against.
// - "br_pc" is the PC of the branch instruction.
class BTBUpdate(implicit p: Parameters) extends BtbBundle()(p) {
val prediction = new BTBResp
val pc = UInt(vaddrBits.W)
val target = UInt(vaddrBits.W)
val taken = Bool()
val isValid = Bool()
val br_pc = UInt(vaddrBits.W)
val cfiType = CFIType()
}
// BHT update occurs during branch resolution on all conditional branches.
// - "pc" is what future fetch PCs will tag match against.
class BHTUpdate(implicit p: Parameters) extends BtbBundle()(p) {
val prediction = new BHTResp
val pc = UInt(vaddrBits.W)
val branch = Bool()
val taken = Bool()
val mispredict = Bool()
}
class RASUpdate(implicit p: Parameters) extends BtbBundle()(p) {
val cfiType = CFIType()
val returnAddr = UInt(vaddrBits.W)
}
// - "bridx" is the low-order PC bits of the predicted branch (after
// shifting off the lowest log(inst_bytes) bits off).
// - "mask" provides a mask of valid instructions (instructions are
// masked off by the predicted taken branch from the BTB).
class BTBResp(implicit p: Parameters) extends BtbBundle()(p) {
val cfiType = CFIType()
val taken = Bool()
val mask = Bits(fetchWidth.W)
val bridx = Bits(log2Up(fetchWidth).W)
val target = UInt(vaddrBits.W)
val entry = UInt(log2Up(entries + 1).W)
val bht = new BHTResp
}
class BTBReq(implicit p: Parameters) extends BtbBundle()(p) {
val addr = UInt(vaddrBits.W)
}
// fully-associative branch target buffer
// Higher-performance processors may cause BTB updates to occur out-of-order,
// which requires an extra CAM port for updates (to ensure no duplicates get
// placed in BTB).
class BTB(implicit p: Parameters) extends BtbModule {
val io = IO(new Bundle {
val req = Flipped(Valid(new BTBReq))
val resp = Valid(new BTBResp)
val btb_update = Flipped(Valid(new BTBUpdate))
val bht_update = Flipped(Valid(new BHTUpdate))
val bht_advance = Flipped(Valid(new BTBResp))
val ras_update = Flipped(Valid(new RASUpdate))
val ras_head = Valid(UInt(vaddrBits.W))
val flush = Input(Bool())
})
val idxs = Reg(Vec(entries, UInt((matchBits - log2Up(coreInstBytes)).W)))
val idxPages = Reg(Vec(entries, UInt(log2Up(nPages).W)))
val tgts = Reg(Vec(entries, UInt((matchBits - log2Up(coreInstBytes)).W)))
val tgtPages = Reg(Vec(entries, UInt(log2Up(nPages).W)))
val pages = Reg(Vec(nPages, UInt((vaddrBits - matchBits).W)))
val pageValid = RegInit(0.U(nPages.W))
val pagesMasked = (pageValid.asBools zip pages).map { case (v, p) => Mux(v, p, 0.U) }
val isValid = RegInit(0.U(entries.W))
val cfiType = Reg(Vec(entries, CFIType()))
val brIdx = Reg(Vec(entries, UInt(log2Up(fetchWidth).W)))
private def page(addr: UInt) = addr >> matchBits
private def pageMatch(addr: UInt) = {
val p = page(addr)
pageValid & pages.map(_ === p).asUInt
}
private def idxMatch(addr: UInt) = {
val idx = addr(matchBits-1, log2Up(coreInstBytes))
idxs.map(_ === idx).asUInt & isValid
}
val r_btb_update = Pipe(io.btb_update)
val update_target = io.req.bits.addr
val pageHit = pageMatch(io.req.bits.addr)
val idxHit = idxMatch(io.req.bits.addr)
val updatePageHit = pageMatch(r_btb_update.bits.pc)
val (updateHit, updateHitAddr) =
if (updatesOutOfOrder) {
val updateHits = (pageHit << 1)(Mux1H(idxMatch(r_btb_update.bits.pc), idxPages))
(updateHits.orR, OHToUInt(updateHits))
} else (r_btb_update.bits.prediction.entry < entries.U, r_btb_update.bits.prediction.entry)
val useUpdatePageHit = updatePageHit.orR
val usePageHit = pageHit.orR
val doIdxPageRepl = !useUpdatePageHit
val nextPageRepl = RegInit(0.U(log2Ceil(nPages).W))
val idxPageRepl = Cat(pageHit(nPages-2,0), pageHit(nPages-1)) | Mux(usePageHit, 0.U, UIntToOH(nextPageRepl))
val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)
val idxPageUpdate = OHToUInt(idxPageUpdateOH)
val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, 0.U)
val samePage = page(r_btb_update.bits.pc) === page(update_target)
val doTgtPageRepl = !samePage && !usePageHit
val tgtPageRepl = Mux(samePage, idxPageUpdateOH, Cat(idxPageUpdateOH(nPages-2,0), idxPageUpdateOH(nPages-1)))
val tgtPageUpdate = OHToUInt(pageHit | Mux(usePageHit, 0.U, tgtPageRepl))
val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, 0.U)
when (r_btb_update.valid && (doIdxPageRepl || doTgtPageRepl)) {
val both = doIdxPageRepl && doTgtPageRepl
val next = nextPageRepl + Mux[UInt](both, 2.U, 1.U)
nextPageRepl := Mux(next >= nPages.U, next(0), next)
}
val repl = new PseudoLRU(entries)
val waddr = Mux(updateHit, updateHitAddr, repl.way)
val r_resp = Pipe(io.resp)
when (r_resp.valid && r_resp.bits.taken || r_btb_update.valid) {
repl.access(Mux(r_btb_update.valid, waddr, r_resp.bits.entry))
}
when (r_btb_update.valid) {
val mask = UIntToOH(waddr)
idxs(waddr) := r_btb_update.bits.pc(matchBits-1, log2Up(coreInstBytes))
tgts(waddr) := update_target(matchBits-1, log2Up(coreInstBytes))
idxPages(waddr) := idxPageUpdate +& 1.U // the +1 corresponds to the <<1 on io.resp.valid
tgtPages(waddr) := tgtPageUpdate
cfiType(waddr) := r_btb_update.bits.cfiType
isValid := Mux(r_btb_update.bits.isValid, isValid | mask, isValid & ~mask)
if (fetchWidth > 1)
brIdx(waddr) := r_btb_update.bits.br_pc >> log2Up(coreInstBytes)
require(nPages % 2 == 0)
val idxWritesEven = !idxPageUpdate(0)
def writeBank(i: Int, mod: Int, en: UInt, data: UInt) =
for (i <- i until nPages by mod)
when (en(i)) { pages(i) := data }
writeBank(0, 2, Mux(idxWritesEven, idxPageReplEn, tgtPageReplEn),
Mux(idxWritesEven, page(r_btb_update.bits.pc), page(update_target)))
writeBank(1, 2, Mux(idxWritesEven, tgtPageReplEn, idxPageReplEn),
Mux(idxWritesEven, page(update_target), page(r_btb_update.bits.pc)))
pageValid := pageValid | tgtPageReplEn | idxPageReplEn
}
io.resp.valid := (pageHit << 1)(Mux1H(idxHit, idxPages))
io.resp.bits.taken := true.B
io.resp.bits.target := Cat(pagesMasked(Mux1H(idxHit, tgtPages)), Mux1H(idxHit, tgts) << log2Up(coreInstBytes))
io.resp.bits.entry := OHToUInt(idxHit)
io.resp.bits.bridx := (if (fetchWidth > 1) Mux1H(idxHit, brIdx) else 0.U)
io.resp.bits.mask := Cat((1.U << ~Mux(io.resp.bits.taken, ~io.resp.bits.bridx, 0.U))-1.U, 1.U)
io.resp.bits.cfiType := Mux1H(idxHit, cfiType)
// if multiple entries for same PC land in BTB, zap them
when (PopCountAtLeast(idxHit, 2)) {
isValid := isValid & ~idxHit
}
when (io.flush) {
isValid := 0.U
}
if (btbParams.bhtParams.nonEmpty) {
val bht = new BHT(Annotated.params(this, btbParams.bhtParams.get))
val isBranch = (idxHit & cfiType.map(_ === CFIType.branch).asUInt).orR
val res = bht.get(io.req.bits.addr)
when (io.bht_advance.valid) {
bht.advanceHistory(io.bht_advance.bits.bht.taken)
}
when (io.bht_update.valid) {
when (io.bht_update.bits.branch) {
bht.updateTable(io.bht_update.bits.pc, io.bht_update.bits.prediction, io.bht_update.bits.taken)
when (io.bht_update.bits.mispredict) {
bht.updateHistory(io.bht_update.bits.pc, io.bht_update.bits.prediction, io.bht_update.bits.taken)
}
}.elsewhen (io.bht_update.bits.mispredict) {
bht.resetHistory(io.bht_update.bits.prediction)
}
}
when (!res.taken && isBranch) { io.resp.bits.taken := false.B }
io.resp.bits.bht := res
}
if (btbParams.nRAS > 0) {
val ras = new RAS(btbParams.nRAS)
val doPeek = (idxHit & cfiType.map(_ === CFIType.ret).asUInt).orR
io.ras_head.valid := !ras.isEmpty
io.ras_head.bits := ras.peek
when (!ras.isEmpty && doPeek) {
io.resp.bits.target := ras.peek
}
when (io.ras_update.valid) {
when (io.ras_update.bits.cfiType === CFIType.call) {
ras.push(io.ras_update.bits.returnAddr)
}.elsewhen (io.ras_update.bits.cfiType === CFIType.ret) {
ras.pop()
}
}
}
} | module table_512x1(
input [8:0] R0_addr,
input R0_en,
input R0_clk,
output R0_data,
input [8:0] W0_addr,
input W0_en,
input W0_clk,
input W0_data
);
reg Memory[0:511];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end
assign R0_data = R0_en ? Memory[R0_addr] : 1'bx;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
} | module dataArrayWay_2(
input [8:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [63:0] RW0_wdata,
output [63:0] RW0_rdata
);
dataArrayWay_0_ext dataArrayWay_0_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata)
);
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
} | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53(
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [2:0] io_roundingMode,
output [64:0] io_out,
output [4:0] io_exceptionFlags
);
wire roundingMode_near_even = io_roundingMode == 3'h0;
wire roundingMode_odd = io_roundingMode == 3'h6;
wire roundMagUp = io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign;
wire [11:0] _roundMask_T_1 = ~(io_in_sExp[11:0]);
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> _roundMask_T_1[5:0]);
wire [18:0] _GEN = {roundMask_shift[18:17], roundMask_shift[20:19], roundMask_shift[22:21], roundMask_shift[24:23], roundMask_shift[26:25], roundMask_shift[28:27], roundMask_shift[30:29], roundMask_shift[32:31], roundMask_shift[34:33], roundMask_shift[36]} & 19'h55555;
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> _roundMask_T_1[5:0]);
wire [53:0] _roundMask_T_128 = _roundMask_T_1[11] ? (_roundMask_T_1[10] ? {~(_roundMask_T_1[9] | _roundMask_T_1[8] | _roundMask_T_1[7] | _roundMask_T_1[6] ? 51'h0 : ~{roundMask_shift[13], roundMask_shift[14], roundMask_shift[15], roundMask_shift[16], roundMask_shift[17], _GEN[18:15] | {roundMask_shift[20:19], roundMask_shift[22:21]} & 4'h5, roundMask_shift[22], _GEN[13] | roundMask_shift[23], roundMask_shift[24], roundMask_shift[25], _GEN[10:7] | {roundMask_shift[28:27], roundMask_shift[30:29]} & 4'h5, roundMask_shift[30], _GEN[5] | roundMask_shift[31], roundMask_shift[32], roundMask_shift[33], {_GEN[2:0], 1'h0} | {roundMask_shift[36:35], roundMask_shift[38:37]} & 4'h5, roundMask_shift[38], roundMask_shift[39], roundMask_shift[40], roundMask_shift[41], roundMask_shift[42], roundMask_shift[43], roundMask_shift[44], roundMask_shift[45], roundMask_shift[46], roundMask_shift[47], roundMask_shift[48], roundMask_shift[49], roundMask_shift[50], roundMask_shift[51], roundMask_shift[52], roundMask_shift[53], roundMask_shift[54], roundMask_shift[55], roundMask_shift[56], roundMask_shift[57], roundMask_shift[58], roundMask_shift[59], roundMask_shift[60], roundMask_shift[61], roundMask_shift[62], roundMask_shift[63]}), 3'h7} : {51'h0, _roundMask_T_1[9] & _roundMask_T_1[8] & _roundMask_T_1[7] & _roundMask_T_1[6] ? {roundMask_shift_1[0], roundMask_shift_1[1], roundMask_shift_1[2]} : 3'h0}) : 54'h0;
wire _common_underflow_T_4 = _roundMask_T_128[0] | io_in_sig[55];
wire [54:0] _GEN_0 = {1'h1, ~(_roundMask_T_128[53:1]), ~_common_underflow_T_4};
wire [54:0] _GEN_1 = {_roundMask_T_128[53:1], _common_underflow_T_4, 1'h1};
wire [54:0] _roundPosBit_T = io_in_sig[55:1] & _GEN_0 & _GEN_1;
wire [54:0] _anyRoundExtra_T = io_in_sig[54:0] & _GEN_1;
wire [109:0] _GEN_2 = {_roundPosBit_T, _anyRoundExtra_T};
wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4;
wire [54:0] roundedSig = _overflow_roundMagUp_T & (|_roundPosBit_T) | roundMagUp & (|_GEN_2) ? {1'h0, io_in_sig[55:2] | {_roundMask_T_128[53:1], _common_underflow_T_4}} + 55'h1 & ~(roundingMode_near_even & (|_roundPosBit_T) & _anyRoundExtra_T == 55'h0 ? {_roundMask_T_128[53:1], _common_underflow_T_4, 1'h1} : 55'h0) : {1'h0, io_in_sig[55:2] & {~(_roundMask_T_128[53:1]), ~_common_underflow_T_4}} | (roundingMode_odd & (|_GEN_2) ? _GEN_0 & _GEN_1 : 55'h0);
wire [13:0] sRoundedExp = {io_in_sExp[12], io_in_sExp} + {12'h0, roundedSig[54:53]};
wire common_totalUnderflow = $signed(sRoundedExp) < 14'sh3CE;
wire isNaNOut = io_invalidExc | io_in_isNaN;
wire commonCase = ~isNaNOut & ~io_in_isInf & ~io_in_isZero;
wire overflow = commonCase & $signed(sRoundedExp[13:10]) > 4'sh2;
wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp;
wire pegMinNonzeroMagOut = commonCase & common_totalUnderflow & (roundMagUp | roundingMode_odd);
wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp;
wire notNaN_isInfOut = io_in_isInf | overflow & overflow_roundMagUp;
assign io_out = {~isNaNOut & io_in_sign, sRoundedExp[11:0] & ~(io_in_isZero | common_totalUnderflow ? 12'hE00 : 12'h0) & ~(pegMinNonzeroMagOut ? 12'hC31 : 12'h0) & {1'h1, ~pegMaxFiniteMagOut, 10'h3FF} & {2'h3, ~notNaN_isInfOut, 9'h1FF} | (pegMinNonzeroMagOut ? 12'h3CE : 12'h0) | (pegMaxFiniteMagOut ? 12'hBFF : 12'h0) | (notNaN_isInfOut ? 12'hC00 : 12'h0) | (isNaNOut ? 12'hE00 : 12'h0), (isNaNOut | io_in_isZero | common_totalUnderflow ? {isNaNOut, 51'h0} : io_in_sig[55] ? roundedSig[52:1] : roundedSig[51:0]) | {52{pegMaxFiniteMagOut}}};
assign io_exceptionFlags = {io_invalidExc, 1'h0, overflow, commonCase & (common_totalUnderflow | (|_GEN_2) & io_in_sExp[12:11] != 2'h1 & (io_in_sig[55] ? _roundMask_T_128[1] : _common_underflow_T_4) & ~(~(io_in_sig[55] ? _roundMask_T_128[2] : _roundMask_T_128[1]) & (io_in_sig[55] ? roundedSig[54] : roundedSig[53]) & (|_roundPosBit_T) & (_overflow_roundMagUp_T & (io_in_sig[55] ? io_in_sig[2] : io_in_sig[1]) | roundMagUp & (|{io_in_sig[55] & io_in_sig[2], io_in_sig[1:0]})))), overflow | commonCase & (|{common_totalUnderflow, _roundPosBit_T, _anyRoundExtra_T})};
endmodule |
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