hasankursun/soc-builder-rtl-v1

SoC Builder RTL Dataset — v1 (Experiment Release)

A reproducible, machine-generated corpus of synthesizable System-on-Chip (SoC) RTL designs for machine learning on hardware: RTL representation learning today, and — as the corpus grows — netlist, timing, and placement prediction. Every design is a complete, hierarchical, lint-clean Verilog SoC assembled from real open-source IP — RISC-V CPU cores, network-on-chip (NoC) interconnects, accelerators, peripherals, memories and bridges — wired together by a seeded, deterministic generator and shipped with rich, machine-readable labels.

This is the experiment version (v1) — the beginning of a much larger effort to build an open, end-to-end RTL → netlist → timing → placement dataset for ML-for-EDA. The SoC builder, its IP library, and the dataset itself will grow many-fold from here (see Roadmap), and future releases will ship the synthesized netlists and physical-design labels alongside the RTL.

5,000 SoC designs, 100% Verilator-lint-clean, each a self-contained hierarchical Verilog tree + machine-readable label manifest. Generated from a v1 library of 65 reusable IP blocks — 10 RISC-V CPU cores (RV32E/I/IMC up to RV64GC), 20 NoC topologies + 3 classic interconnects, 14 accelerators, 12 peripherals, plus memories and bridges. This is a small slice of an effectively unbounded generator: the target library is 120–150+ IP blocks / 20–25+ cores, and the full dataset will scale to tens of thousands of designs enriched with netlists, post-synthesis timing, and placement data.

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Why this dataset

ML-for-EDA (machine learning for chip design — RTL quality, area/timing/power prediction, routability, design-space exploration) is data-starved at the open level: the datasets that matter are almost all proprietary, locked inside foundries and EDA vendors. This project bridges that gap with:

• Reproducibility — a deterministic generator, not a static scrape. A given (seed, library snapshot, generator version) regenerates a design bit-for-bit, so the corpus is auditable and infinitely extensible.
• Real, permissive IP — actual open-source RISC-V cores and hardware blocks (not toy RTL), packaged in an IP-XACT-lite scheme and assembled into coherent SoCs.
• Structural diversity by construction — every design independently draws a fabric/topology, CPU core(s), a slave mix, and per-IP microarchitectural knobs, so the corpus spans a wide, controllable distribution.
• Labels that go all the way down — today: full structural labels per design; on the roadmap: synthesized netlists, critical-path timing, and placement — the labels that turn this into a netlist/timing/placement-prediction benchmark.

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Subsets

Subset	Rows	Schema
designs (v1)	5,000	label row per SoC: {seed, name, path, fabric, topology, num_masters, num_slaves, num_bridges, categories, slaves, num_source_files, lint_ok}

Each row points at a soc_<seed>/ folder containing the full RTL and a per-design manifest.json (the complete label set). Future subsets (see Roadmap): netlists, timing, placement.

from datasets import load_dataset

# label index (one row per SoC design)
ds = load_dataset("hasankursun/soc-builder-rtl-v1", "designs", split="train")
print(ds[0])
# -> {'seed': 0, 'fabric': 'noc_dragonfly', 'num_masters': 1, 'num_slaves': 4,
#     'slaves': ['axil_ram', 'aes', 'timer', 'mailbox'], 'lint_ok': True, ...}

# the RTL itself lives in each design folder: soc_<seed>/rtl/soc_top.v,
# soc_<seed>/src/<mirror>/ (self-contained sources), soc_<seed>/manifest.json

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v1 composition

A v1 design independently draws an interconnect fabric, one or more CPU cores, a slave mix, and per-IP knobs. The realized v1 distribution:

CPU cores (masters)

Near-uniform across five microarchitectures (Wishbone core appears on Wishbone fabrics):

Core	ISA / style	Designs	License	Upstream
picorv32	RV32IMC, area-optimized	1,068	ISC	YosysHQ/picorv32
darkriscv	RV32E/I, 2–3 stage	1,041	BSD	darklife/darkriscv
ibex	RV32IMC, lowRISC (SV→sv2v)	1,037	Apache-2.0	lowRISC/ibex
serv	RV32I bit-serial (smallest)	1,034	ISC	olofk/serv
cv32e40p	RV32IMC, OpenHW (SV→sv2v)	1,024	SHL-2.1	openhwgroup/cv32e40p
picorv32_wb	RV32IMC, Wishbone	199	ISC	YosysHQ/picorv32

Larger cores are part of the library but kept out of the random pool so the corpus stays small/fast — scr1 (Syntacore) and XuanTie/T-Head openE902 / openE906 / openc906 (RV64GC, Apache-2.0) are reachable by pinning (--core <name>). They join the random distribution in later releases.

Interconnect fabrics — all 23 represented (4,330 NoC / 670 bus-class designs)

20 NoC topologies — ring, bidirectional-ring, line, mesh, torus, star, binary-tree, quad-tree, hypercube, concentrated-mesh, fully-connected, butterfly, spidergon, fat-tree (leaf-spine), dragonfly, flattened-butterfly, hierarchical-ring, king-mesh, chordal-ring, and a multi-master flow-controlled mesh (with valid/ready back-pressure + randomizable buffer depth) — plus AXI4-Lite shared-bus, AXI4-Lite crossbar, and Wishbone mux.

Slaves — 28 distinct IP, avg 3.86 slaves/design

Memories (axil_ram/wb_ram); crypto accelerators (aes, sha1/256/512, chacha, siphash, blake2s); compute accelerators (crc32, mac, popcount, fir, minmax, divider, isqrt); peripherals (uart, gpio, timer, pwm, watchdog, prng, sysctrl, mailbox, spi_master, i2c_master, intc, pulse_counter). regbus IP attaches to any fabric through an auto-inserted bridge.

Masters per design

1: 4,730 · 2: 180 · 3: 47 · 4: 43 (the multi-master flow-controlled mesh contributes the ≥2-master cases).

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Data fields

designs / index.jsonl (one row per SoC)

Field	Type	Description
seed	int	regeneration seed (deterministic)
name, path	string	design id and folder
fabric, topology	string	interconnect component + kind (e.g. noc_dragonfly)
num_masters, num_slaves, num_bridges	int	structural counts
categories	list[str]	IP categories present (core/memory/peripheral/accelerator/…)
slaves	list[str]	slave IP components
num_source_files	int	size proxy
lint_ok	bool	Verilator --lint-only quality gate (all true in v1)

soc_<seed>/manifest.json (full per-design labels)

The authoritative label set: the exact regeneration command, library snapshot, the fabric block (with randomized parameters, e.g. NoC buffer depth), every master/slave with its resolved parameters (counter widths, FIFO/buffer depths, FIR taps, …), the address map, clock/reset, and bridge insertions.

soc_<seed>/ files

rtl/soc_top.v (generated hierarchical top) · src/<mirror>/ (a copy of every source file — self-contained, never flattened) · filelist.f (portable) · manifest.json.

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How it's built

A four-layer, fully open pipeline:

1. IP-XACT-lite packaging — each block is described by a small YAML descriptor (bus interfaces, port maps, randomizable parameters). The generator reads only the descriptors, never parses RTL.
2. Seeded randomizer — a single ordered RNG stream picks the fabric, family-matched core(s), slave mix, and per-IP knobs; the master/memory protocol is matched to the fabric, and regbus IP rides any fabric through an auto-inserted bridge.
3. Assembler + emitter — builds the address map and emits a hierarchical, synthesizable Verilog top, bundling all sources self-contained.
4. Validation + corpus driver — every design is Verilator-lint-clean; the corpus driver is restartable and writes the JSONL label index incrementally.

SystemVerilog cores are converted to Verilog with sv2v. Determinism is enforced end-to-end (sorted iteration only), so the dataset is reproducible and trivially extensible by widening the seed range.

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Roadmap — from experiment to full dataset

This is v1. It is deliberately small and RTL-only. The plan:

• Library growth → 120–150+ IP blocks: more CPU cores toward 20–25+ (VexRiscv / NaxRiscv (SpinalHDL), Rocket / BOOM / Sodor (Chisel), CVA6, VeeR, more XuanTie incl. C910), more NoC topologies (→ ~26–28; mesh-of-trees, Clos/Benes, cube-connected-cycles, …), and many more accelerators (→ 30–45: CORDIC, FFT, more ciphers/hashes, ECC, matmul) and peripherals (→ 25–30: DMA, CAN, QSPI, Ethernet-lite, …). The big cores enter the random pool as the corpus scales.
• Scale → tens of thousands of designs (the generator already supports 10⁵–10⁶ structurally-distinct SoCs; the bound is compute, not the library).
• Netlists → each design synthesized (Yosys), shipping the gate-level netlist + cell counts as labels — the netlists subset.
• Timing studies → post-synthesis static timing (critical-path delay against open standard-cell libraries, e.g. Nangate45 / Sky130) — the timing subset, for netlist-timing prediction.
• Placement / physical-design studies → floorplan + placement data (and routability/congestion signals) from an open P&R flow — the placement subset.

The aim is a coherent, fully-open RTL → netlist → timing → placement dataset family with consistent provenance across releases.

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Intended use & limitations

Intended use: RTL representation learning; ML-for-EDA research (area/timing/power and — with later subsets — netlist/timing/placement prediction); design-space exploration; HDL tokenizer/model training; NoC and SoC-architecture studies.

Limitations to be aware of:

• v1 is RTL-only. No synthesized netlists, timing, or placement labels yet — those are the roadmap subsets. v1 is for RTL-representation work and as the seed corpus.
• Machine-generated, not human-authored. Designs are structurally valid and lint-clean, but they are assembled by a generator; they are not hand-optimized production SoCs and are not booted with firmware.
• Small, fast subset by design. v1 uses the 5 small/fast cores in the random pool; the large RV64GC cores and the heaviest accelerators are under-represented (pin-only) until later scaled releases.
• Quality gate is lint, not formal verification. Every design passes Verilator --lint-only; functional equivalence/verification is out of scope for v1.

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Licensing

Released under Apache-2.0. The generated top-level RTL and the generator/harness are original (MIT/Apache); the dataset aggregates open-source IP that retains its own permissive licenses (ISC / MIT / BSD / Apache-2.0 / Solderpad-SHL) — e.g. picorv32 (ISC), serv (ISC), darkriscv (BSD), ibex (Apache-2.0), cv32e40p / scr1 (SHL), XuanTie cores (Apache-2.0), secworks crypto (BSD-2). Each vendored block carries its upstream license in-tree. Users are responsible for verifying that their intended use complies with the terms of each upstream source.

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Citation

@misc{kursun_soc_builder_rtl_v1,
  title        = {SoC Builder RTL Dataset v1: A Reproducible Corpus of Synthesizable SoC RTL for ML-for-EDA},
  author       = {Kurşun, Hasan},
  year         = {2026},
  howpublished = {\url{https://huggingface.co/datasets/hasankursun/soc-builder-rtl-v1}},
  note         = {Experiment release; part of an ongoing RTL -> netlist -> timing -> placement dataset effort}
}

Please also cite the upstream IP (picorv32, serv, darkriscv, ibex, cv32e40p, scr1, XuanTie OpenC9xx, secworks crypto cores, Forencich verilog-axi/uart) where appropriate.

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Contact & custom work

Built and maintained by Hasan Kurşun.

I build hardware datasets and ML-for-EDA data pipelines — reproducible RTL/SoC corpora, synthesis and timing/placement label generation, IP packaging and design-space exploration, and end-to-end data engineering for chip-design ML. If you need a bespoke dataset (your IP, your PDK/flow, your target labels — netlist, timing, power, routability) or custom EDA-data / ML consulting, I'd be glad to help.

📧 hakursn@gmail.com

Available for freelance and contract work on EDA data engineering, RTL/netlist dataset construction, and applied ML for chip design.