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The dataset generation failed
Error code:   DatasetGenerationError
Exception:    CastError
Message:      Couldn't cast
base_design_id: string
benchmark_area: string
benchmark_source: string
catalog_case_id: string
expected: struct<security: string>
  child 0, security: string
family_id: string
id: string
lexical_stratum: string
mechanism_id: string
pair_id: string
policy_counterpart_id: string
policy_role: string
questions: struct<security: struct<criteria: list<item: string>, instructions: string, type: string>>
  child 0, security: struct<criteria: list<item: string>, instructions: string, type: string>
      child 0, criteria: list<item: string>
          child 0, item: string
      child 1, instructions: string
      child 2, type: string
rewrite_group_id: string
source: string
split: string
split_group_id: string
state: string
topic: string
validation: string
variant: int64
policy: string
property_origin: string
connected_template_id: string
label_basis: string
template_id: string
dataset_component: string
focused_temporal_domain: string
contract_version: string
assertion_sha256: string
behavior_group_id: string
parent_pair_id: string
parent_record_id: string
representation: string
requirement_kind: string
dependency_group_id: string
presentation_id: string
to
{'base_design_id': Value('string'), 'benchmark_area': Value('string'), 'benchmark_source': Value('string'), 'catalog_case_id': Value('string'), 'expected': {'security': Value('string')}, 'family_id': Value('string'), 'focused_temporal_domain': Value('string'), 'id': Value('string'), 'lexical_stratum': Value('string'), 'mechanism_id': Value('string'), 'pair_id': Value('string'), 'parent_pair_id': Value('string'), 'parent_record_id': Value('string'), 'policy_role': Value('string'), 'questions': {'security': {'criteria': List(Value('string')), 'instructions': Value('string'), 'type': Value('string')}}, 'rewrite_group_id': Value('string'), 'source': Json(decode=True), 'split': Value('string'), 'split_group_id': Value('string'), 'state': Value('string'), 'topic': Value('string'), 'validation': Json(decode=True), 'variant': Value('int64'), 'assertion_sha256': Value('string'), 'dataset_component': Value('string'), 'dependency_group_id': Value('string'), 'template_id': Value('string'), 'connected_template_id': Value('string'), 'behavior_group_id': Value('string'), 'contract_version': Value('string'), 'presentation_id': Value('string'), 'label_basis': Value('string'), 'representation': Value('string'), 'requirement_kind': Value('string'), 'policy_counterpart_id': Value('string')}
because column names don't match
Traceback:    Traceback (most recent call last):
                File "/usr/local/lib/python3.14/site-packages/datasets/builder.py", line 1835, in _prepare_split_single
                  for key, table in generator:
                                    ^^^^^^^^^
                File "/src/services/worker/src/worker/job_runners/config/parquet_and_info.py", line 621, in wrapped
                  for item in generator(*args, **kwargs):
                              ~~~~~~~~~^^^^^^^^^^^^^^^^^
                File "/usr/local/lib/python3.14/site-packages/datasets/packaged_modules/json/json.py", line 361, in _generate_tables
                  self._cast_table(pa_table, json_field_paths=json_field_paths),
                  ~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
                File "/usr/local/lib/python3.14/site-packages/datasets/packaged_modules/json/json.py", line 132, in _cast_table
                  pa_table = table_cast(pa_table, self.info.features.arrow_schema)
                File "/usr/local/lib/python3.14/site-packages/datasets/table.py", line 2381, in table_cast
                  return cast_table_to_schema(table, schema)
                File "/usr/local/lib/python3.14/site-packages/datasets/table.py", line 2309, in cast_table_to_schema
                  raise CastError(
                  ...<3 lines>...
                  )
              datasets.table.CastError: Couldn't cast
              base_design_id: string
              benchmark_area: string
              benchmark_source: string
              catalog_case_id: string
              expected: struct<security: string>
                child 0, security: string
              family_id: string
              id: string
              lexical_stratum: string
              mechanism_id: string
              pair_id: string
              policy_counterpart_id: string
              policy_role: string
              questions: struct<security: struct<criteria: list<item: string>, instructions: string, type: string>>
                child 0, security: struct<criteria: list<item: string>, instructions: string, type: string>
                    child 0, criteria: list<item: string>
                        child 0, item: string
                    child 1, instructions: string
                    child 2, type: string
              rewrite_group_id: string
              source: string
              split: string
              split_group_id: string
              state: string
              topic: string
              validation: string
              variant: int64
              policy: string
              property_origin: string
              connected_template_id: string
              label_basis: string
              template_id: string
              dataset_component: string
              focused_temporal_domain: string
              contract_version: string
              assertion_sha256: string
              behavior_group_id: string
              parent_pair_id: string
              parent_record_id: string
              representation: string
              requirement_kind: string
              dependency_group_id: string
              presentation_id: string
              to
              {'base_design_id': Value('string'), 'benchmark_area': Value('string'), 'benchmark_source': Value('string'), 'catalog_case_id': Value('string'), 'expected': {'security': Value('string')}, 'family_id': Value('string'), 'focused_temporal_domain': Value('string'), 'id': Value('string'), 'lexical_stratum': Value('string'), 'mechanism_id': Value('string'), 'pair_id': Value('string'), 'parent_pair_id': Value('string'), 'parent_record_id': Value('string'), 'policy_role': Value('string'), 'questions': {'security': {'criteria': List(Value('string')), 'instructions': Value('string'), 'type': Value('string')}}, 'rewrite_group_id': Value('string'), 'source': Json(decode=True), 'split': Value('string'), 'split_group_id': Value('string'), 'state': Value('string'), 'topic': Value('string'), 'validation': Json(decode=True), 'variant': Value('int64'), 'assertion_sha256': Value('string'), 'dataset_component': Value('string'), 'dependency_group_id': Value('string'), 'template_id': Value('string'), 'connected_template_id': Value('string'), 'behavior_group_id': Value('string'), 'contract_version': Value('string'), 'presentation_id': Value('string'), 'label_basis': Value('string'), 'representation': Value('string'), 'requirement_kind': Value('string'), 'policy_counterpart_id': Value('string')}
              because column names don't match
              
              The above exception was the direct cause of the following exception:
              
              Traceback (most recent call last):
                File "/src/services/worker/src/worker/job_runners/config/parquet_and_info.py", line 1379, in compute_config_parquet_and_info_response
                  parquet_operations, partial, estimated_dataset_info = stream_convert_to_parquet(
                                                                        ~~~~~~~~~~~~~~~~~~~~~~~~~^
                      builder, max_dataset_size_bytes=max_dataset_size_bytes
                      ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
                  )
                  ^
                File "/src/services/worker/src/worker/job_runners/config/parquet_and_info.py", line 956, in stream_convert_to_parquet
                  builder._prepare_split(split_generator=splits_generators[split], file_format="parquet")
                  ~~~~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
                File "/usr/local/lib/python3.14/site-packages/datasets/builder.py", line 1702, in _prepare_split
                  for job_id, done, content in self._prepare_split_single(
                                               ~~~~~~~~~~~~~~~~~~~~~~~~~~^
                      gen_kwargs=gen_kwargs, job_id=job_id, **_prepare_split_args
                      ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
                  ):
                  ^
                File "/usr/local/lib/python3.14/site-packages/datasets/builder.py", line 1887, in _prepare_split_single
                  raise DatasetGenerationError("An error occurred while generating the dataset") from e
              datasets.exceptions.DatasetGenerationError: An error occurred while generating the dataset

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base_design_id
string
benchmark_area
string
benchmark_source
string
catalog_case_id
string
expected
dict
family_id
string
focused_temporal_domain
string
id
string
lexical_stratum
string
mechanism_id
string
pair_id
string
parent_pair_id
string
parent_record_id
string
policy_role
string
questions
dict
rewrite_group_id
string
source
unknown
split
string
split_group_id
string
state
string
topic
string
validation
unknown
variant
int64
assertion_sha256
string
dataset_component
string
dependency_group_id
string
template_id
string
connected_template_id
string
behavior_group_id
string
contract_version
string
presentation_id
string
label_basis
string
representation
string
requirement_kind
string
policy_counterpart_id
string
35f7a1ad8ebf2bed430d
arbitration
focused-temporal-dev-234
61b87cd57361d221680e6e10
{ "security": "satisfies_requirement" }
OpenTitan-expanded:arbitration
arbitration
4d3a498ae5f709def62e28aa
and_to_or
arbiter-tree-acceptance
temporal-arb:16be47fd1de3621cacd2
61b87cd57361d221680e6e10:1
7727519faac777cc11c5a606
source_plain_english
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
61b87cd57361d221680e6e10
{ "anchors": [ { "line": 126, "sha256": "2ae14e977a1c29face6185df2521ca77b276f427e8cdb20a633d9bb5a050aa04", "text": "assign gnt_o[offset] = req_i[offset] & sel_tree[Pa] & ready_i;" } ], "case": "arbitration", "family": "OpenTitan-expanded:arbitration", "label_scope": "Source-de...
dev
temporal-focused:arbitration:14bbaf137073cca4
REQUIREMENT After combinational settling, gnt_o_offset_1 must be high exactly when request_1, selected_1, and ready_i_1 are all high. If any one of those three conditions is low, the grant must remain low. ASSUMPTIONS Two-state digital RTL with defined inputs. Combinational behavior is evaluated after settling. Only th...
arbiter-tree-acceptance
{ "accepted": true, "alpha_renaming": 1, "antecedent": "unconditional", "assertion_sha256": "97d2697b90f7e227f66bb38218c97c7565974391d8da222283c7e62e6236e05a", "basis": "temporal_induction", "bounded_command": "read_verilog -formal -sv checked.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; s...
1
null
null
null
null
null
null
null
null
null
null
null
null
35f7a1ad8ebf2bed430d
arbitration
focused-temporal-dev-234
61b87cd57361d221680e6e10
{ "security": "violates_requirement" }
OpenTitan-expanded:arbitration
arbitration
690f7f61147602093048098b
and_to_or
arbiter-tree-acceptance
temporal-arb:16be47fd1de3621cacd2
61b87cd57361d221680e6e10:1
6e6ada2aebc8d59aa1f24d09
source_plain_english
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
61b87cd57361d221680e6e10
{ "anchors": [ { "line": 126, "sha256": "2ae14e977a1c29face6185df2521ca77b276f427e8cdb20a633d9bb5a050aa04", "text": "assign gnt_o[offset] = req_i[offset] & sel_tree[Pa] & ready_i;" } ], "case": "arbitration", "family": "OpenTitan-expanded:arbitration", "label_scope": "Source-de...
dev
temporal-focused:arbitration:14bbaf137073cca4
REQUIREMENT After combinational settling, gnt_o_offset_1 must be high exactly when request_1, selected_1, and ready_i_1 are all high. If any one of those three conditions is low, the grant must remain low. ASSUMPTIONS Two-state digital RTL with defined inputs. Combinational behavior is evaluated after settling. Only th...
arbiter-tree-acceptance
{ "accepted": true, "alpha_renaming": 1, "assertion_sha256": "97d2697b90f7e227f66bb38218c97c7565974391d8da222283c7e62e6236e05a", "basis": "reachable_counterexample_6_cycles", "bounded_command": "read_verilog -formal -sv checked.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; sat -seq 6 -set-ini...
1
null
null
null
null
null
null
null
null
null
null
null
null
35f7a1ad8ebf2bed430d
arbitration
focused-temporal-dev-234
61b87cd57361d221680e6e10
{ "security": "insufficient_context" }
OpenTitan-expanded:arbitration
arbitration
6e2b98588f4eba44f79f55cf
and_to_or
arbiter-tree-acceptance
temporal-arb:16be47fd1de3621cacd2
61b87cd57361d221680e6e10:1
f8f26f04c2e5e24015278eab
source_plain_english
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
61b87cd57361d221680e6e10
{ "anchors": [ { "line": 126, "sha256": "2ae14e977a1c29face6185df2521ca77b276f427e8cdb20a633d9bb5a050aa04", "text": "assign gnt_o[offset] = req_i[offset] & sel_tree[Pa] & ready_i;" } ], "case": "arbitration", "family": "OpenTitan-expanded:arbitration", "label_scope": "Source-de...
dev
temporal-focused:arbitration:14bbaf137073cca4
REQUIREMENT After combinational settling, gnt_o_offset_1 must be high exactly when request_1, selected_1, and ready_i_1 are all high. If any one of those three conditions is low, the grant must remain low. ASSUMPTIONS Two-state digital RTL with defined inputs. Combinational behavior is evaluated after settling. Only th...
arbiter-tree-acceptance
{ "accepted": true, "alpha_renaming": 1, "bad_completion": "byte_exact", "bad_fill_sha256": "cb92a7145f96f664866484c26eecc1fe21262348b7eedfe8ede122af2893fe22", "basis": "exact_shared_hole_completions", "compile_evidence": "d522549a97b0bd7fb6bb1bda3b65943216ff9a4f150cafe6f0884ef2c4b4b1c8", "good_completion...
1
null
null
null
null
null
null
null
null
null
null
null
null
35f7a1ad8ebf2bed430d
arbitration
focused-temporal-dev-234
61b87cd57361d221680e6e10
{ "security": "insufficient_context" }
OpenTitan-expanded:arbitration
arbitration
9a55edd970d2b23348bc7e75
and_to_or
arbiter-tree-acceptance
temporal-arb:5d5de19bca30dd8827d1
61b87cd57361d221680e6e10:2
78a314cf5b23871eaf3c68b6
source_plain_english
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
61b87cd57361d221680e6e10
{ "anchors": [ { "line": 126, "sha256": "2ae14e977a1c29face6185df2521ca77b276f427e8cdb20a633d9bb5a050aa04", "text": "assign gnt_o[offset] = req_i[offset] & sel_tree[Pa] & ready_i;" } ], "case": "arbitration", "family": "OpenTitan-expanded:arbitration", "label_scope": "Source-de...
dev
temporal-focused:arbitration:14bbaf137073cca4
REQUIREMENT After combinational settling, gnt_o_offset_2 must be high exactly when request_2, selected_2, and ready_i_2 are all high. If any one of those three conditions is low, the grant must remain low. ASSUMPTIONS Two-state digital RTL with defined inputs. Combinational behavior is evaluated after settling. Only th...
arbiter-tree-acceptance
{ "accepted": true, "alpha_renaming": 2, "bad_completion": "byte_exact", "bad_fill_sha256": "2f8f01fb3989b6ca991cd62076b462d43026c4a29edbcb6e3d57e52f086c7692", "basis": "exact_shared_hole_completions", "compile_evidence": "70e12cb34b392880b68241f7c2920e23e74c819312aa00e766ecd2a2017358ce", "good_completion...
2
null
null
null
null
null
null
null
null
null
null
null
null
35f7a1ad8ebf2bed430d
arbitration
focused-temporal-dev-234
61b87cd57361d221680e6e10
{ "security": "violates_requirement" }
OpenTitan-expanded:arbitration
arbitration
d4969d592790c989cac250fa
and_to_or
arbiter-tree-acceptance
temporal-arb:5d5de19bca30dd8827d1
61b87cd57361d221680e6e10:2
6c88af53201b5b044d98984f
source_plain_english
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
61b87cd57361d221680e6e10
{ "anchors": [ { "line": 126, "sha256": "2ae14e977a1c29face6185df2521ca77b276f427e8cdb20a633d9bb5a050aa04", "text": "assign gnt_o[offset] = req_i[offset] & sel_tree[Pa] & ready_i;" } ], "case": "arbitration", "family": "OpenTitan-expanded:arbitration", "label_scope": "Source-de...
dev
temporal-focused:arbitration:14bbaf137073cca4
REQUIREMENT After combinational settling, gnt_o_offset_2 must be high exactly when request_2, selected_2, and ready_i_2 are all high. If any one of those three conditions is low, the grant must remain low. ASSUMPTIONS Two-state digital RTL with defined inputs. Combinational behavior is evaluated after settling. Only th...
arbiter-tree-acceptance
{ "accepted": true, "alpha_renaming": 2, "assertion_sha256": "7eee7f35dafbd6d2c6b6fbe10004126417822be2695f84a3fc3861f976b928d2", "basis": "reachable_counterexample_6_cycles", "bounded_command": "read_verilog -formal -sv checked.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; sat -seq 6 -set-ini...
2
null
null
null
null
null
null
null
null
null
null
null
null
35f7a1ad8ebf2bed430d
arbitration
focused-temporal-dev-234
61b87cd57361d221680e6e10
{ "security": "satisfies_requirement" }
OpenTitan-expanded:arbitration
arbitration
f30eaf42258fa5b60cce0c20
and_to_or
arbiter-tree-acceptance
temporal-arb:5d5de19bca30dd8827d1
61b87cd57361d221680e6e10:2
6df34bd144b199c9fd547369
source_plain_english
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
61b87cd57361d221680e6e10
{ "anchors": [ { "line": 126, "sha256": "2ae14e977a1c29face6185df2521ca77b276f427e8cdb20a633d9bb5a050aa04", "text": "assign gnt_o[offset] = req_i[offset] & sel_tree[Pa] & ready_i;" } ], "case": "arbitration", "family": "OpenTitan-expanded:arbitration", "label_scope": "Source-de...
dev
temporal-focused:arbitration:14bbaf137073cca4
REQUIREMENT After combinational settling, gnt_o_offset_2 must be high exactly when request_2, selected_2, and ready_i_2 are all high. If any one of those three conditions is low, the grant must remain low. ASSUMPTIONS Two-state digital RTL with defined inputs. Combinational behavior is evaluated after settling. Only th...
arbiter-tree-acceptance
{ "accepted": true, "alpha_renaming": 2, "antecedent": "unconditional", "assertion_sha256": "7eee7f35dafbd6d2c6b6fbe10004126417822be2695f84a3fc3861f976b928d2", "basis": "temporal_induction", "bounded_command": "read_verilog -formal -sv checked.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; s...
2
null
null
null
null
null
null
null
null
null
null
null
null
89ccfa5d63d75854cf1d
arbitration
focused-temporal-dev-234
4d36809042291692d8e83a10
{ "security": "insufficient_context" }
OpenTitan-expanded:arbitration
arbitration
0e7cd2bc46690722376fdc2f
output_mask_fault
arbiter-grant-handshake
temporal-arb:c4bd654aa3c3c84c8f63
4d36809042291692d8e83a10:1
ded75d504c76d40856476f3b
source_plain_english
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
4d36809042291692d8e83a10
{ "anchors": [ { "line": 85, "sha256": "fa773416ff4e7f9f550bbeea36b7a7c3e294bf2ea9da67ac297638d8077eb902", "text": "assign gnt_o = (ready_i) ? winner : '0;" } ], "case": "arbitration", "family": "OpenTitan-expanded:arbitration", "label_scope": "Source-derived local contract over ex...
dev
temporal-focused:arbitration:5162282e096f0803
REQUIREMENT After combinational settling, gnt_o_1 must be all zero while ready_i_1 is low. While ready_i_1 is high, gnt_o_1 must match winner_1 exactly. ASSUMPTIONS Two-state digital RTL with defined inputs. Combinational behavior is evaluated after settling. Only the stated property is assessed. An undriven wire denot...
arbiter-grant-handshake
{ "accepted": true, "alpha_renaming": 1, "bad_completion": "byte_exact", "bad_fill_sha256": "761e3cf69b2bdde44c491194da87dbd8a27a6f1c8586cc1dd894b55644fc9861", "basis": "exact_shared_hole_completions", "compile_evidence": "9c8fde73b72ecd3d71ad695a066c765c51889dd49c6e96f5162c605e18bbbb6b", "good_completion...
1
null
null
null
null
null
null
null
null
null
null
null
null
89ccfa5d63d75854cf1d
arbitration
focused-temporal-dev-234
4d36809042291692d8e83a10
{ "security": "violates_requirement" }
OpenTitan-expanded:arbitration
arbitration
c23dd35c492f8fae1c4b961a
output_mask_fault
arbiter-grant-handshake
temporal-arb:c4bd654aa3c3c84c8f63
4d36809042291692d8e83a10:1
8a16c8fb060619b63b1a8073
source_plain_english
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
4d36809042291692d8e83a10
{ "anchors": [ { "line": 85, "sha256": "fa773416ff4e7f9f550bbeea36b7a7c3e294bf2ea9da67ac297638d8077eb902", "text": "assign gnt_o = (ready_i) ? winner : '0;" } ], "case": "arbitration", "family": "OpenTitan-expanded:arbitration", "label_scope": "Source-derived local contract over ex...
dev
temporal-focused:arbitration:5162282e096f0803
REQUIREMENT After combinational settling, gnt_o_1 must be all zero while ready_i_1 is low. While ready_i_1 is high, gnt_o_1 must match winner_1 exactly. ASSUMPTIONS Two-state digital RTL with defined inputs. Combinational behavior is evaluated after settling. Only the stated property is assessed. An undriven wire denot...
arbiter-grant-handshake
{ "accepted": true, "alpha_renaming": 1, "assertion_sha256": "cf053e63fd438971f10a2eac1dc0469c7b3161674c7a198cae280fde03c67f5d", "basis": "reachable_counterexample_6_cycles", "bounded_command": "read_verilog -formal -sv checked.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; sat -seq 6 -set-ini...
1
null
null
null
null
null
null
null
null
null
null
null
null
89ccfa5d63d75854cf1d
arbitration
focused-temporal-dev-234
4d36809042291692d8e83a10
{ "security": "satisfies_requirement" }
OpenTitan-expanded:arbitration
arbitration
eb9955fbe0fca2b8a29bdaa5
output_mask_fault
arbiter-grant-handshake
temporal-arb:c4bd654aa3c3c84c8f63
4d36809042291692d8e83a10:1
c5699a327c2394cb7bac34a4
source_plain_english
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
4d36809042291692d8e83a10
{ "anchors": [ { "line": 85, "sha256": "fa773416ff4e7f9f550bbeea36b7a7c3e294bf2ea9da67ac297638d8077eb902", "text": "assign gnt_o = (ready_i) ? winner : '0;" } ], "case": "arbitration", "family": "OpenTitan-expanded:arbitration", "label_scope": "Source-derived local contract over ex...
dev
temporal-focused:arbitration:5162282e096f0803
REQUIREMENT After combinational settling, gnt_o_1 must be all zero while ready_i_1 is low. While ready_i_1 is high, gnt_o_1 must match winner_1 exactly. ASSUMPTIONS Two-state digital RTL with defined inputs. Combinational behavior is evaluated after settling. Only the stated property is assessed. An undriven wire denot...
arbiter-grant-handshake
{ "accepted": true, "alpha_renaming": 1, "antecedent": "unconditional", "assertion_sha256": "cf053e63fd438971f10a2eac1dc0469c7b3161674c7a198cae280fde03c67f5d", "basis": "temporal_induction", "bounded_command": "read_verilog -formal -sv checked.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; s...
1
null
null
null
null
null
null
null
null
null
null
null
null
35f7a1ad8ebf2bed430d
arbitration
focused-temporal-dev-234
61b87cd57361d221680e6e10
{ "security": "insufficient_context" }
OpenTitan-expanded:arbitration
arbitration
388995f15ad804eb6cab66b6
and_to_or
arbiter-tree-acceptance
temporal-arb:c80f308d332f91af6b6b
61b87cd57361d221680e6e10:0
0f00104c4cd476bd9e0aa658
source_plain_english
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
61b87cd57361d221680e6e10
{ "anchors": [ { "line": 126, "sha256": "2ae14e977a1c29face6185df2521ca77b276f427e8cdb20a633d9bb5a050aa04", "text": "assign gnt_o[offset] = req_i[offset] & sel_tree[Pa] & ready_i;" } ], "case": "arbitration", "family": "OpenTitan-expanded:arbitration", "label_scope": "Source-de...
dev
temporal-focused:arbitration:14bbaf137073cca4
REQUIREMENT After combinational settling, gnt_o_offset must be high exactly when request, selected, and ready_i are all high. If any one of those three conditions is low, the grant must remain low. ASSUMPTIONS Two-state digital RTL with defined inputs. Combinational behavior is evaluated after settling. Only the stated...
arbiter-tree-acceptance
{ "accepted": true, "alpha_renaming": 0, "bad_completion": "byte_exact", "bad_fill_sha256": "b0821ae34584f3c40eb028723d217ffa15da794971efa3eca942bfa91ff6f6b4", "basis": "exact_shared_hole_completions", "compile_evidence": "12958b336e147761271c0afefd87b35fbfd1f4e3ceee14be07c0ef84d066851a", "good_completion...
0
null
null
null
null
null
null
null
null
null
null
null
null
35f7a1ad8ebf2bed430d
arbitration
focused-temporal-dev-234
61b87cd57361d221680e6e10
{ "security": "violates_requirement" }
OpenTitan-expanded:arbitration
arbitration
4942723607a4e623b0488938
and_to_or
arbiter-tree-acceptance
temporal-arb:c80f308d332f91af6b6b
61b87cd57361d221680e6e10:0
8bb8dc3a3ce8cca7d8ab5b94
source_plain_english
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
61b87cd57361d221680e6e10
{ "anchors": [ { "line": 126, "sha256": "2ae14e977a1c29face6185df2521ca77b276f427e8cdb20a633d9bb5a050aa04", "text": "assign gnt_o[offset] = req_i[offset] & sel_tree[Pa] & ready_i;" } ], "case": "arbitration", "family": "OpenTitan-expanded:arbitration", "label_scope": "Source-de...
dev
temporal-focused:arbitration:14bbaf137073cca4
REQUIREMENT After combinational settling, gnt_o_offset must be high exactly when request, selected, and ready_i are all high. If any one of those three conditions is low, the grant must remain low. ASSUMPTIONS Two-state digital RTL with defined inputs. Combinational behavior is evaluated after settling. Only the stated...
arbiter-tree-acceptance
{ "accepted": true, "alpha_renaming": 0, "assertion_sha256": "9c9ef0e3f78f596701eccc7eb071ab70c88e6a0791e41f9e6748fbd9cd6cafbb", "basis": "reachable_counterexample_6_cycles", "bounded_command": "read_verilog -formal -sv checked.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; sat -seq 6 -set-ini...
0
null
null
null
null
null
null
null
null
null
null
null
null
35f7a1ad8ebf2bed430d
arbitration
focused-temporal-dev-234
61b87cd57361d221680e6e10
{ "security": "satisfies_requirement" }
OpenTitan-expanded:arbitration
arbitration
7dc7eb06dd5c0c0d9dd76642
and_to_or
arbiter-tree-acceptance
temporal-arb:c80f308d332f91af6b6b
61b87cd57361d221680e6e10:0
8bc132d0be3a1d3cba739915
source_plain_english
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
61b87cd57361d221680e6e10
{ "anchors": [ { "line": 126, "sha256": "2ae14e977a1c29face6185df2521ca77b276f427e8cdb20a633d9bb5a050aa04", "text": "assign gnt_o[offset] = req_i[offset] & sel_tree[Pa] & ready_i;" } ], "case": "arbitration", "family": "OpenTitan-expanded:arbitration", "label_scope": "Source-de...
dev
temporal-focused:arbitration:14bbaf137073cca4
REQUIREMENT After combinational settling, gnt_o_offset must be high exactly when request, selected, and ready_i are all high. If any one of those three conditions is low, the grant must remain low. ASSUMPTIONS Two-state digital RTL with defined inputs. Combinational behavior is evaluated after settling. Only the stated...
arbiter-tree-acceptance
{ "accepted": true, "alpha_renaming": 0, "antecedent": "unconditional", "assertion_sha256": "9c9ef0e3f78f596701eccc7eb071ab70c88e6a0791e41f9e6748fbd9cd6cafbb", "basis": "temporal_induction", "bounded_command": "read_verilog -formal -sv checked.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; s...
0
null
null
null
null
null
null
null
null
null
null
null
null
89ccfa5d63d75854cf1d
arbitration
focused-temporal-dev-234
4d36809042291692d8e83a10
{ "security": "satisfies_requirement" }
OpenTitan-expanded:arbitration
arbitration
1d11f7e1bc6bd2532a729882
output_mask_fault
arbiter-grant-handshake
temporal-arb:e3a7f00153fb4488d5b2
4d36809042291692d8e83a10:0
c257b2a04bdef95a1a8c6e47
source_plain_english
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
4d36809042291692d8e83a10
{ "anchors": [ { "line": 85, "sha256": "fa773416ff4e7f9f550bbeea36b7a7c3e294bf2ea9da67ac297638d8077eb902", "text": "assign gnt_o = (ready_i) ? winner : '0;" } ], "case": "arbitration", "family": "OpenTitan-expanded:arbitration", "label_scope": "Source-derived local contract over ex...
dev
temporal-focused:arbitration:5162282e096f0803
REQUIREMENT After combinational settling, gnt_o must be all zero while ready_i is low. While ready_i is high, gnt_o must match winner exactly. ASSUMPTIONS Two-state digital RTL with defined inputs. Combinational behavior is evaluated after settling. Only the stated property is assessed. An undriven wire denotes an omit...
arbiter-grant-handshake
{ "accepted": true, "alpha_renaming": 0, "antecedent": "unconditional", "assertion_sha256": "bd327f7c7b0b9d258c565353b47811aaf0f86c4a6f60251037a91b49b1669d3b", "basis": "temporal_induction", "bounded_command": "read_verilog -formal -sv checked.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; s...
0
null
null
null
null
null
null
null
null
null
null
null
null
89ccfa5d63d75854cf1d
arbitration
focused-temporal-dev-234
4d36809042291692d8e83a10
{ "security": "insufficient_context" }
OpenTitan-expanded:arbitration
arbitration
4089fae354ba21f75eeb3d28
output_mask_fault
arbiter-grant-handshake
temporal-arb:e3a7f00153fb4488d5b2
4d36809042291692d8e83a10:0
0cfeaef79dae630ac6914bcf
source_plain_english
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
4d36809042291692d8e83a10
{ "anchors": [ { "line": 85, "sha256": "fa773416ff4e7f9f550bbeea36b7a7c3e294bf2ea9da67ac297638d8077eb902", "text": "assign gnt_o = (ready_i) ? winner : '0;" } ], "case": "arbitration", "family": "OpenTitan-expanded:arbitration", "label_scope": "Source-derived local contract over ex...
dev
temporal-focused:arbitration:5162282e096f0803
REQUIREMENT After combinational settling, gnt_o must be all zero while ready_i is low. While ready_i is high, gnt_o must match winner exactly. ASSUMPTIONS Two-state digital RTL with defined inputs. Combinational behavior is evaluated after settling. Only the stated property is assessed. An undriven wire denotes an omit...
arbiter-grant-handshake
{ "accepted": true, "alpha_renaming": 0, "bad_completion": "byte_exact", "bad_fill_sha256": "9b2f9808122364a8fa38ab7a735fbdfe632a58bcfa5cbb208e3f20cc5d46006d", "basis": "exact_shared_hole_completions", "compile_evidence": "28d98f9a3b5e30239d5ce7af94ef650f836c475ed46915cd5ef82a17de38b173", "good_completion...
0
null
null
null
null
null
null
null
null
null
null
null
null
89ccfa5d63d75854cf1d
arbitration
focused-temporal-dev-234
4d36809042291692d8e83a10
{ "security": "violates_requirement" }
OpenTitan-expanded:arbitration
arbitration
53e0357ba6f9ed86fad9649c
output_mask_fault
arbiter-grant-handshake
temporal-arb:e3a7f00153fb4488d5b2
4d36809042291692d8e83a10:0
6b446560f3e53eac565c85d1
source_plain_english
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
4d36809042291692d8e83a10
{ "anchors": [ { "line": 85, "sha256": "fa773416ff4e7f9f550bbeea36b7a7c3e294bf2ea9da67ac297638d8077eb902", "text": "assign gnt_o = (ready_i) ? winner : '0;" } ], "case": "arbitration", "family": "OpenTitan-expanded:arbitration", "label_scope": "Source-derived local contract over ex...
dev
temporal-focused:arbitration:5162282e096f0803
REQUIREMENT After combinational settling, gnt_o must be all zero while ready_i is low. While ready_i is high, gnt_o must match winner exactly. ASSUMPTIONS Two-state digital RTL with defined inputs. Combinational behavior is evaluated after settling. Only the stated property is assessed. An undriven wire denotes an omit...
arbiter-grant-handshake
{ "accepted": true, "alpha_renaming": 0, "assertion_sha256": "bd327f7c7b0b9d258c565353b47811aaf0f86c4a6f60251037a91b49b1669d3b", "basis": "reachable_counterexample_6_cycles", "bounded_command": "read_verilog -formal -sv checked.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; sat -seq 6 -set-ini...
0
null
null
null
null
null
null
null
null
null
null
null
null
89ccfa5d63d75854cf1d
arbitration
focused-temporal-dev-234
4d36809042291692d8e83a10
{ "security": "insufficient_context" }
OpenTitan-expanded:arbitration
arbitration
0461ada57426bf6245de301b
output_mask_fault
arbiter-grant-handshake
temporal-arb:f1641637360409f02e11
4d36809042291692d8e83a10:2
30e462b5aab97f6462952553
source_plain_english
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
4d36809042291692d8e83a10
{ "anchors": [ { "line": 85, "sha256": "fa773416ff4e7f9f550bbeea36b7a7c3e294bf2ea9da67ac297638d8077eb902", "text": "assign gnt_o = (ready_i) ? winner : '0;" } ], "case": "arbitration", "family": "OpenTitan-expanded:arbitration", "label_scope": "Source-derived local contract over ex...
dev
temporal-focused:arbitration:5162282e096f0803
REQUIREMENT After combinational settling, gnt_o_2 must be all zero while ready_i_2 is low. While ready_i_2 is high, gnt_o_2 must match winner_2 exactly. ASSUMPTIONS Two-state digital RTL with defined inputs. Combinational behavior is evaluated after settling. Only the stated property is assessed. An undriven wire denot...
arbiter-grant-handshake
{ "accepted": true, "alpha_renaming": 2, "bad_completion": "byte_exact", "bad_fill_sha256": "306631c2852dc9a0b531182eef90d88cbcbe14aa96945a5dcb1c721417a6c110", "basis": "exact_shared_hole_completions", "compile_evidence": "a9d1f76939e0abf37dc345ee09d48256ba2a4378787cbc32e7ae514bf5628e08", "good_completion...
2
null
null
null
null
null
null
null
null
null
null
null
null
89ccfa5d63d75854cf1d
arbitration
focused-temporal-dev-234
4d36809042291692d8e83a10
{ "security": "satisfies_requirement" }
OpenTitan-expanded:arbitration
arbitration
1cdd79d21b4cdcfbec480c43
output_mask_fault
arbiter-grant-handshake
temporal-arb:f1641637360409f02e11
4d36809042291692d8e83a10:2
086e75937d98ada276625c88
source_plain_english
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
4d36809042291692d8e83a10
{ "anchors": [ { "line": 85, "sha256": "fa773416ff4e7f9f550bbeea36b7a7c3e294bf2ea9da67ac297638d8077eb902", "text": "assign gnt_o = (ready_i) ? winner : '0;" } ], "case": "arbitration", "family": "OpenTitan-expanded:arbitration", "label_scope": "Source-derived local contract over ex...
dev
temporal-focused:arbitration:5162282e096f0803
REQUIREMENT After combinational settling, gnt_o_2 must be all zero while ready_i_2 is low. While ready_i_2 is high, gnt_o_2 must match winner_2 exactly. ASSUMPTIONS Two-state digital RTL with defined inputs. Combinational behavior is evaluated after settling. Only the stated property is assessed. An undriven wire denot...
arbiter-grant-handshake
{ "accepted": true, "alpha_renaming": 2, "antecedent": "unconditional", "assertion_sha256": "198396580ae4f4fb6344b71701214fd64360d1cb0ee17288ae1ced3a3956cbef", "basis": "temporal_induction", "bounded_command": "read_verilog -formal -sv checked.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; s...
2
null
null
null
null
null
null
null
null
null
null
null
null
89ccfa5d63d75854cf1d
arbitration
focused-temporal-dev-234
4d36809042291692d8e83a10
{ "security": "violates_requirement" }
OpenTitan-expanded:arbitration
arbitration
75eaeb157d215f463fa6726b
output_mask_fault
arbiter-grant-handshake
temporal-arb:f1641637360409f02e11
4d36809042291692d8e83a10:2
d3f72a1004ae873e674abcf4
source_plain_english
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
4d36809042291692d8e83a10
{ "anchors": [ { "line": 85, "sha256": "fa773416ff4e7f9f550bbeea36b7a7c3e294bf2ea9da67ac297638d8077eb902", "text": "assign gnt_o = (ready_i) ? winner : '0;" } ], "case": "arbitration", "family": "OpenTitan-expanded:arbitration", "label_scope": "Source-derived local contract over ex...
dev
temporal-focused:arbitration:5162282e096f0803
REQUIREMENT After combinational settling, gnt_o_2 must be all zero while ready_i_2 is low. While ready_i_2 is high, gnt_o_2 must match winner_2 exactly. ASSUMPTIONS Two-state digital RTL with defined inputs. Combinational behavior is evaluated after settling. Only the stated property is assessed. An undriven wire denot...
arbiter-grant-handshake
{ "accepted": true, "alpha_renaming": 2, "assertion_sha256": "198396580ae4f4fb6344b71701214fd64360d1cb0ee17288ae1ced3a3956cbef", "basis": "reachable_counterexample_6_cycles", "bounded_command": "read_verilog -formal -sv checked.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; sat -seq 6 -set-ini...
2
null
null
null
null
null
null
null
null
null
null
null
null
814d42835dd0fb07ac33
counter
focused-temporal-dev-234
000cf0ec83f9d6470b81b31e
{ "security": "satisfies_requirement" }
OpenTitan-expanded:count
counter
4550502819f82bd33e241df2
connected_control_or_data_path
underflow-saturates:w5:reset1:style1
000cf0ec83f9d6470b81b31e:0
null
null
source
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
000cf0ec83f9d6470b81b31e
{ "anchors": [ { "line": 123, "sha256": "1e4f9bcf806522b7d4f653d8f02070c5696b825ef053af488201c44c8202b4f7", "text": "assign cnt_d_committed[k] = commit_i ? cnt_d[k] : cnt_q[k];" }, { "line": 114, "sha256": "ea5fed637c8f469101e37f035c0c692a521cdeb87387174aae9c266b01e808ed", ...
dev
temporal-focused:counter:8748f3a44a3d5231
REQUIREMENT A committed decrement larger than the current count must clamp count at zero, not wrap, when clear and load are inactive. ASSUMPTIONS Two-state sampled-clock RTL with defined inputs and arbitrary-but-defined initial state. Reset is asserted for the initial clock cycle and inactive thereafter. Reset takes pr...
underflow-saturates:w5:reset1:style1
{ "accepted": true, "alpha_renaming": 0, "antecedent": "reachable_bounded_12_cycles", "antecedent_command": "read_verilog -formal -sv antecedent.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; sat -seq 12 -set-init-def -set-def-inputs -set rst_n 1 -set-at 1 rst_n 0 -prove-asserts -show-ports -dum...
0
fafe7e7c4488596778bda83804fd01c6ca104566b56cc009642ccdc871f7790e
temporal_temporal_curriculum
temporal:814d42835dd0fb07ac33
tpl-d5d4a37bd7748b5ec93c9535
null
null
null
null
null
null
null
null
814d42835dd0fb07ac33
counter
focused-temporal-dev-234
000cf0ec83f9d6470b81b31e
{ "security": "insufficient_context" }
OpenTitan-expanded:count
counter
5d3ed0282df8a6f8386e7d6a
connected_control_or_data_path
underflow-saturates:w5:reset1:style1
000cf0ec83f9d6470b81b31e:0
null
null
source
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
000cf0ec83f9d6470b81b31e
{ "anchors": [ { "line": 123, "sha256": "1e4f9bcf806522b7d4f653d8f02070c5696b825ef053af488201c44c8202b4f7", "text": "assign cnt_d_committed[k] = commit_i ? cnt_d[k] : cnt_q[k];" }, { "line": 114, "sha256": "ea5fed637c8f469101e37f035c0c692a521cdeb87387174aae9c266b01e808ed", ...
dev
temporal-focused:counter:8748f3a44a3d5231
REQUIREMENT A committed decrement larger than the current count must clamp count at zero, not wrap, when clear and load are inactive. ASSUMPTIONS Two-state sampled-clock RTL with defined inputs and arbitrary-but-defined initial state. Reset is asserted for the initial clock cycle and inactive thereafter. Reset takes pr...
underflow-saturates:w5:reset1:style1
{ "accepted": true, "alpha_renaming": 0, "bad_completion": "byte_exact", "bad_fill_sha256": "6c5fda79f05c8499a3a85bb149e9994af4accaf4581151a489fd5c6e8239d654", "basis": "exact_shared_hole_completions", "good_completion": "byte_exact", "good_fill_sha256": "42a4ac20b32d3f56df346eb2be0dc711ec885df1a774e7309d...
0
fafe7e7c4488596778bda83804fd01c6ca104566b56cc009642ccdc871f7790e
temporal_temporal_curriculum
temporal:814d42835dd0fb07ac33
tpl-d5d4a37bd7748b5ec93c9535
null
null
null
null
null
null
null
null
814d42835dd0fb07ac33
counter
focused-temporal-dev-234
000cf0ec83f9d6470b81b31e
{ "security": "violates_requirement" }
OpenTitan-expanded:count
counter
aa42fef0139530add18c8abb
connected_control_or_data_path
underflow-saturates:w5:reset1:style1
000cf0ec83f9d6470b81b31e:0
null
null
source
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
000cf0ec83f9d6470b81b31e
{ "anchors": [ { "line": 123, "sha256": "1e4f9bcf806522b7d4f653d8f02070c5696b825ef053af488201c44c8202b4f7", "text": "assign cnt_d_committed[k] = commit_i ? cnt_d[k] : cnt_q[k];" }, { "line": 114, "sha256": "ea5fed637c8f469101e37f035c0c692a521cdeb87387174aae9c266b01e808ed", ...
dev
temporal-focused:counter:8748f3a44a3d5231
REQUIREMENT A committed decrement larger than the current count must clamp count at zero, not wrap, when clear and load are inactive. ASSUMPTIONS Two-state sampled-clock RTL with defined inputs and arbitrary-but-defined initial state. Reset is asserted for the initial clock cycle and inactive thereafter. Reset takes pr...
underflow-saturates:w5:reset1:style1
{ "accepted": true, "alpha_renaming": 0, "assertion_sha256": "f6f47e72e4d646951b9121b425fed1aa5d24a6ae35abbe6d51b87b019e9e254f", "basis": "reachable_counterexample_12_cycles", "bounded_command": "read_verilog -formal -sv checked.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; sat -seq 12 -set-i...
0
fafe7e7c4488596778bda83804fd01c6ca104566b56cc009642ccdc871f7790e
temporal_temporal_curriculum
temporal:814d42835dd0fb07ac33
tpl-d5d4a37bd7748b5ec93c9535
null
null
null
null
null
null
null
null
814d42835dd0fb07ac33
counter
focused-temporal-dev-234
000cf0ec83f9d6470b81b31e
{ "security": "violates_requirement" }
OpenTitan-expanded:count
counter
0e748f0b4146ffb85e02dcf1
connected_control_or_data_path
underflow-saturates:w5:reset1:style1
000cf0ec83f9d6470b81b31e:1
null
null
source
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
000cf0ec83f9d6470b81b31e
{ "anchors": [ { "line": 123, "sha256": "1e4f9bcf806522b7d4f653d8f02070c5696b825ef053af488201c44c8202b4f7", "text": "assign cnt_d_committed[k] = commit_i ? cnt_d[k] : cnt_q[k];" }, { "line": 114, "sha256": "ea5fed637c8f469101e37f035c0c692a521cdeb87387174aae9c266b01e808ed", ...
dev
temporal-focused:counter:8748f3a44a3d5231
REQUIREMENT A committed decrement_1 larger than the current count_1 must clamp count_1 at zero, not wrap, when clear_1 and load_1 are inactive. ASSUMPTIONS Two-state sampled-clock RTL with defined inputs and arbitrary-but-defined initial state. Reset is asserted for the initial clock cycle and inactive thereafter. Rese...
underflow-saturates:w5:reset1:style1
{ "accepted": true, "alpha_renaming": 1, "assertion_sha256": "19c0d219c1c783dfb43270d71041b09a492533c3ee5c0484b2033a80b1963683", "basis": "reachable_counterexample_12_cycles", "bounded_command": "read_verilog -formal -sv checked.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; sat -seq 12 -set-i...
1
afa1c9da74c552a6ee3fef5ed46257fbd48eda17a9eba0f59c9aebf401952636
temporal_temporal_curriculum
temporal:814d42835dd0fb07ac33
tpl-702d7853c19716aec300f0b3
null
null
null
null
null
null
null
null
814d42835dd0fb07ac33
counter
focused-temporal-dev-234
000cf0ec83f9d6470b81b31e
{ "security": "insufficient_context" }
OpenTitan-expanded:count
counter
e04e1d3d62819e8a70d1999a
connected_control_or_data_path
underflow-saturates:w5:reset1:style1
000cf0ec83f9d6470b81b31e:1
null
null
source
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
000cf0ec83f9d6470b81b31e
{ "anchors": [ { "line": 123, "sha256": "1e4f9bcf806522b7d4f653d8f02070c5696b825ef053af488201c44c8202b4f7", "text": "assign cnt_d_committed[k] = commit_i ? cnt_d[k] : cnt_q[k];" }, { "line": 114, "sha256": "ea5fed637c8f469101e37f035c0c692a521cdeb87387174aae9c266b01e808ed", ...
dev
temporal-focused:counter:8748f3a44a3d5231
REQUIREMENT A committed decrement_1 larger than the current count_1 must clamp count_1 at zero, not wrap, when clear_1 and load_1 are inactive. ASSUMPTIONS Two-state sampled-clock RTL with defined inputs and arbitrary-but-defined initial state. Reset is asserted for the initial clock cycle and inactive thereafter. Rese...
underflow-saturates:w5:reset1:style1
{ "accepted": true, "alpha_renaming": 1, "bad_completion": "byte_exact", "bad_fill_sha256": "8ffa2ef49af0d7a89281c3267b3cf3d05f68d7ee05a045af2b0ac5b7a5463f45", "basis": "exact_shared_hole_completions", "good_completion": "byte_exact", "good_fill_sha256": "bea390904085682f3a4997f4eef97e389f284057c37f6a28db...
1
afa1c9da74c552a6ee3fef5ed46257fbd48eda17a9eba0f59c9aebf401952636
temporal_temporal_curriculum
temporal:814d42835dd0fb07ac33
tpl-702d7853c19716aec300f0b3
null
null
null
null
null
null
null
null
814d42835dd0fb07ac33
counter
focused-temporal-dev-234
000cf0ec83f9d6470b81b31e
{ "security": "satisfies_requirement" }
OpenTitan-expanded:count
counter
e0ccb05d4d7388b03614ca2e
connected_control_or_data_path
underflow-saturates:w5:reset1:style1
000cf0ec83f9d6470b81b31e:1
null
null
source
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
000cf0ec83f9d6470b81b31e
{ "anchors": [ { "line": 123, "sha256": "1e4f9bcf806522b7d4f653d8f02070c5696b825ef053af488201c44c8202b4f7", "text": "assign cnt_d_committed[k] = commit_i ? cnt_d[k] : cnt_q[k];" }, { "line": 114, "sha256": "ea5fed637c8f469101e37f035c0c692a521cdeb87387174aae9c266b01e808ed", ...
dev
temporal-focused:counter:8748f3a44a3d5231
REQUIREMENT A committed decrement_1 larger than the current count_1 must clamp count_1 at zero, not wrap, when clear_1 and load_1 are inactive. ASSUMPTIONS Two-state sampled-clock RTL with defined inputs and arbitrary-but-defined initial state. Reset is asserted for the initial clock cycle and inactive thereafter. Rese...
underflow-saturates:w5:reset1:style1
{ "accepted": true, "alpha_renaming": 1, "antecedent": "reachable_bounded_12_cycles", "antecedent_command": "read_verilog -formal -sv antecedent.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; sat -seq 12 -set-init-def -set-def-inputs -set rst_n 1 -set-at 1 rst_n 0 -prove-asserts -show-ports -dum...
1
afa1c9da74c552a6ee3fef5ed46257fbd48eda17a9eba0f59c9aebf401952636
temporal_temporal_curriculum
temporal:814d42835dd0fb07ac33
tpl-702d7853c19716aec300f0b3
null
null
null
null
null
null
null
null
814d42835dd0fb07ac33
counter
focused-temporal-dev-234
000cf0ec83f9d6470b81b31e
{ "security": "satisfies_requirement" }
OpenTitan-expanded:count
counter
2a938f31736e0ddadef4b339
connected_control_or_data_path
underflow-saturates:w5:reset1:style1
000cf0ec83f9d6470b81b31e:2
null
null
source
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
000cf0ec83f9d6470b81b31e
{ "anchors": [ { "line": 123, "sha256": "1e4f9bcf806522b7d4f653d8f02070c5696b825ef053af488201c44c8202b4f7", "text": "assign cnt_d_committed[k] = commit_i ? cnt_d[k] : cnt_q[k];" }, { "line": 114, "sha256": "ea5fed637c8f469101e37f035c0c692a521cdeb87387174aae9c266b01e808ed", ...
dev
temporal-focused:counter:8748f3a44a3d5231
REQUIREMENT A committed decrement_2 larger than the current count_2 must clamp count_2 at zero, not wrap, when clear_2 and load_2 are inactive. ASSUMPTIONS Two-state sampled-clock RTL with defined inputs and arbitrary-but-defined initial state. Reset is asserted for the initial clock cycle and inactive thereafter. Rese...
underflow-saturates:w5:reset1:style1
{ "accepted": true, "alpha_renaming": 2, "antecedent": "reachable_bounded_12_cycles", "antecedent_command": "read_verilog -formal -sv antecedent.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; sat -seq 12 -set-init-def -set-def-inputs -set rst_n 1 -set-at 1 rst_n 0 -prove-asserts -show-ports -dum...
2
461324fb2eafdc6b4431b601d3b338f3cf6ee14fb7b195f91afb02e978e5d354
temporal_temporal_curriculum
temporal:814d42835dd0fb07ac33
tpl-3e3b6980940a03043a87e85a
null
null
null
null
null
null
null
null
814d42835dd0fb07ac33
counter
focused-temporal-dev-234
000cf0ec83f9d6470b81b31e
{ "security": "insufficient_context" }
OpenTitan-expanded:count
counter
ab87db8a84e4485f604a439e
connected_control_or_data_path
underflow-saturates:w5:reset1:style1
000cf0ec83f9d6470b81b31e:2
null
null
source
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
000cf0ec83f9d6470b81b31e
{ "anchors": [ { "line": 123, "sha256": "1e4f9bcf806522b7d4f653d8f02070c5696b825ef053af488201c44c8202b4f7", "text": "assign cnt_d_committed[k] = commit_i ? cnt_d[k] : cnt_q[k];" }, { "line": 114, "sha256": "ea5fed637c8f469101e37f035c0c692a521cdeb87387174aae9c266b01e808ed", ...
dev
temporal-focused:counter:8748f3a44a3d5231
REQUIREMENT A committed decrement_2 larger than the current count_2 must clamp count_2 at zero, not wrap, when clear_2 and load_2 are inactive. ASSUMPTIONS Two-state sampled-clock RTL with defined inputs and arbitrary-but-defined initial state. Reset is asserted for the initial clock cycle and inactive thereafter. Rese...
underflow-saturates:w5:reset1:style1
{ "accepted": true, "alpha_renaming": 2, "bad_completion": "byte_exact", "bad_fill_sha256": "17aa018d9ba40c4e233c5b39917a3ad8cab8f137272785d9921cd67f55764e2a", "basis": "exact_shared_hole_completions", "good_completion": "byte_exact", "good_fill_sha256": "4dd61786d76262fd89d98aaea437cbb4c9f53a28fc0f56dec7...
2
461324fb2eafdc6b4431b601d3b338f3cf6ee14fb7b195f91afb02e978e5d354
temporal_temporal_curriculum
temporal:814d42835dd0fb07ac33
tpl-3e3b6980940a03043a87e85a
null
null
null
null
null
null
null
null
814d42835dd0fb07ac33
counter
focused-temporal-dev-234
000cf0ec83f9d6470b81b31e
{ "security": "violates_requirement" }
OpenTitan-expanded:count
counter
e33566482b2fa4d144f6cc62
connected_control_or_data_path
underflow-saturates:w5:reset1:style1
000cf0ec83f9d6470b81b31e:2
null
null
source
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
000cf0ec83f9d6470b81b31e
{ "anchors": [ { "line": 123, "sha256": "1e4f9bcf806522b7d4f653d8f02070c5696b825ef053af488201c44c8202b4f7", "text": "assign cnt_d_committed[k] = commit_i ? cnt_d[k] : cnt_q[k];" }, { "line": 114, "sha256": "ea5fed637c8f469101e37f035c0c692a521cdeb87387174aae9c266b01e808ed", ...
dev
temporal-focused:counter:8748f3a44a3d5231
REQUIREMENT A committed decrement_2 larger than the current count_2 must clamp count_2 at zero, not wrap, when clear_2 and load_2 are inactive. ASSUMPTIONS Two-state sampled-clock RTL with defined inputs and arbitrary-but-defined initial state. Reset is asserted for the initial clock cycle and inactive thereafter. Rese...
underflow-saturates:w5:reset1:style1
{ "accepted": true, "alpha_renaming": 2, "assertion_sha256": "7784058b2d3eb17cb6fd7eb71c393f9ee33c3698985258a088ceace8f16f1a2e", "basis": "reachable_counterexample_12_cycles", "bounded_command": "read_verilog -formal -sv checked.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; sat -seq 12 -set-i...
2
461324fb2eafdc6b4431b601d3b338f3cf6ee14fb7b195f91afb02e978e5d354
temporal_temporal_curriculum
temporal:814d42835dd0fb07ac33
tpl-3e3b6980940a03043a87e85a
null
null
null
null
null
null
null
null
814d42835dd0fb07ac33
counter
focused-temporal-dev-234
01209b2386c2ab3dba056105
{ "security": "violates_requirement" }
OpenTitan-expanded:count
counter
94ca07ea341ada2b15b9b798
connected_control_or_data_path
underflow-saturates:w5:reset1:style1
01209b2386c2ab3dba056105:0
null
null
counterfactual
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
01209b2386c2ab3dba056105
{ "anchors": [ { "line": 123, "sha256": "1e4f9bcf806522b7d4f653d8f02070c5696b825ef053af488201c44c8202b4f7", "text": "assign cnt_d_committed[k] = commit_i ? cnt_d[k] : cnt_q[k];" }, { "line": 114, "sha256": "ea5fed637c8f469101e37f035c0c692a521cdeb87387174aae9c266b01e808ed", ...
dev
temporal-focused:counter:8748f3a44a3d5231
REQUIREMENT Modulo counting on underflow: a committed decrement below zero from a nonzero count must wrap to the low bits, not clamp at zero. ASSUMPTIONS Two-state sampled-clock RTL with defined inputs and arbitrary-but-defined initial state. Reset is asserted for the initial clock cycle and inactive thereafter. Reset ...
underflow-saturates:w5:reset1:style1
{ "accepted": true, "alpha_renaming": 0, "assertion_sha256": "9d7be1801098ac280c03c0345e9eeed6c58141ede0e3549d1d8f1f4927c3e5ef", "basis": "reachable_counterexample_12_cycles", "bounded_command": "read_verilog -formal -sv checked.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; sat -seq 12 -set-i...
0
88b63ce1aa21b4fb3811266d96942b3ef56657409653bad293d3471d29077bcc
temporal_counterfactual
temporal:814d42835dd0fb07ac33
tpl-cda2ad1c444f8acea3258aa4
null
null
null
null
null
null
null
null
814d42835dd0fb07ac33
counter
focused-temporal-dev-234
01209b2386c2ab3dba056105
{ "security": "satisfies_requirement" }
OpenTitan-expanded:count
counter
a72c0a0d6d55a1d24a827239
connected_control_or_data_path
underflow-saturates:w5:reset1:style1
01209b2386c2ab3dba056105:0
null
null
counterfactual
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
01209b2386c2ab3dba056105
{ "anchors": [ { "line": 123, "sha256": "1e4f9bcf806522b7d4f653d8f02070c5696b825ef053af488201c44c8202b4f7", "text": "assign cnt_d_committed[k] = commit_i ? cnt_d[k] : cnt_q[k];" }, { "line": 114, "sha256": "ea5fed637c8f469101e37f035c0c692a521cdeb87387174aae9c266b01e808ed", ...
dev
temporal-focused:counter:8748f3a44a3d5231
REQUIREMENT Modulo counting on underflow: a committed decrement below zero from a nonzero count must wrap to the low bits, not clamp at zero. ASSUMPTIONS Two-state sampled-clock RTL with defined inputs and arbitrary-but-defined initial state. Reset is asserted for the initial clock cycle and inactive thereafter. Reset ...
underflow-saturates:w5:reset1:style1
{ "accepted": true, "alpha_renaming": 0, "antecedent": "reachable_bounded_12_cycles", "antecedent_command": "read_verilog -formal -sv antecedent.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; sat -seq 12 -set-init-def -set-def-inputs -set rst_n 1 -set-at 1 rst_n 0 -prove-asserts -show-ports -dum...
0
88b63ce1aa21b4fb3811266d96942b3ef56657409653bad293d3471d29077bcc
temporal_counterfactual
temporal:814d42835dd0fb07ac33
tpl-cda2ad1c444f8acea3258aa4
null
null
null
null
null
null
null
null
814d42835dd0fb07ac33
counter
focused-temporal-dev-234
01209b2386c2ab3dba056105
{ "security": "insufficient_context" }
OpenTitan-expanded:count
counter
abd66969ec725bfd727f90b2
connected_control_or_data_path
underflow-saturates:w5:reset1:style1
01209b2386c2ab3dba056105:0
null
null
counterfactual
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
01209b2386c2ab3dba056105
{ "anchors": [ { "line": 123, "sha256": "1e4f9bcf806522b7d4f653d8f02070c5696b825ef053af488201c44c8202b4f7", "text": "assign cnt_d_committed[k] = commit_i ? cnt_d[k] : cnt_q[k];" }, { "line": 114, "sha256": "ea5fed637c8f469101e37f035c0c692a521cdeb87387174aae9c266b01e808ed", ...
dev
temporal-focused:counter:8748f3a44a3d5231
REQUIREMENT Modulo counting on underflow: a committed decrement below zero from a nonzero count must wrap to the low bits, not clamp at zero. ASSUMPTIONS Two-state sampled-clock RTL with defined inputs and arbitrary-but-defined initial state. Reset is asserted for the initial clock cycle and inactive thereafter. Reset ...
underflow-saturates:w5:reset1:style1
{ "accepted": true, "alpha_renaming": 0, "bad_completion": "byte_exact", "bad_fill_sha256": "42a4ac20b32d3f56df346eb2be0dc711ec885df1a774e7309d4d71a2605ffd49", "basis": "exact_shared_hole_completions", "good_completion": "byte_exact", "good_fill_sha256": "6c5fda79f05c8499a3a85bb149e9994af4accaf4581151a489...
0
88b63ce1aa21b4fb3811266d96942b3ef56657409653bad293d3471d29077bcc
temporal_counterfactual
temporal:814d42835dd0fb07ac33
tpl-cda2ad1c444f8acea3258aa4
null
null
null
null
null
null
null
null
814d42835dd0fb07ac33
counter
focused-temporal-dev-234
01209b2386c2ab3dba056105
{ "security": "insufficient_context" }
OpenTitan-expanded:count
counter
7d48e49b9d74dce91cd77b56
connected_control_or_data_path
underflow-saturates:w5:reset1:style1
01209b2386c2ab3dba056105:1
null
null
counterfactual
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
01209b2386c2ab3dba056105
{ "anchors": [ { "line": 123, "sha256": "1e4f9bcf806522b7d4f653d8f02070c5696b825ef053af488201c44c8202b4f7", "text": "assign cnt_d_committed[k] = commit_i ? cnt_d[k] : cnt_q[k];" }, { "line": 114, "sha256": "ea5fed637c8f469101e37f035c0c692a521cdeb87387174aae9c266b01e808ed", ...
dev
temporal-focused:counter:8748f3a44a3d5231
REQUIREMENT Modulo counting on underflow_1: a committed decrement_1 below zero from a nonzero count_1 must wrap to the low bits, not clamp at zero. ASSUMPTIONS Two-state sampled-clock RTL with defined inputs and arbitrary-but-defined initial state. Reset is asserted for the initial clock cycle and inactive thereafter. ...
underflow-saturates:w5:reset1:style1
{ "accepted": true, "alpha_renaming": 1, "bad_completion": "byte_exact", "bad_fill_sha256": "bea390904085682f3a4997f4eef97e389f284057c37f6a28dba8f557a81175a8", "basis": "exact_shared_hole_completions", "good_completion": "byte_exact", "good_fill_sha256": "8ffa2ef49af0d7a89281c3267b3cf3d05f68d7ee05a045af2b...
1
21ff24dcc42e3fca5682f15a7484df278c696a7d9cae6aed94a1a78e3104c2c0
temporal_counterfactual
temporal:814d42835dd0fb07ac33
tpl-141266d62cd9c7f98720e78c
null
null
null
null
null
null
null
null
814d42835dd0fb07ac33
counter
focused-temporal-dev-234
01209b2386c2ab3dba056105
{ "security": "violates_requirement" }
OpenTitan-expanded:count
counter
a54b98130ca1f7857ba21d69
connected_control_or_data_path
underflow-saturates:w5:reset1:style1
01209b2386c2ab3dba056105:1
null
null
counterfactual
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
01209b2386c2ab3dba056105
{ "anchors": [ { "line": 123, "sha256": "1e4f9bcf806522b7d4f653d8f02070c5696b825ef053af488201c44c8202b4f7", "text": "assign cnt_d_committed[k] = commit_i ? cnt_d[k] : cnt_q[k];" }, { "line": 114, "sha256": "ea5fed637c8f469101e37f035c0c692a521cdeb87387174aae9c266b01e808ed", ...
dev
temporal-focused:counter:8748f3a44a3d5231
REQUIREMENT Modulo counting on underflow_1: a committed decrement_1 below zero from a nonzero count_1 must wrap to the low bits, not clamp at zero. ASSUMPTIONS Two-state sampled-clock RTL with defined inputs and arbitrary-but-defined initial state. Reset is asserted for the initial clock cycle and inactive thereafter. ...
underflow-saturates:w5:reset1:style1
{ "accepted": true, "alpha_renaming": 1, "assertion_sha256": "c0f808fd7b3f3e5bb7371d9a3874d824d23995c5a9faddba91e04ea3013d7eeb", "basis": "reachable_counterexample_12_cycles", "bounded_command": "read_verilog -formal -sv checked.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; sat -seq 12 -set-i...
1
21ff24dcc42e3fca5682f15a7484df278c696a7d9cae6aed94a1a78e3104c2c0
temporal_counterfactual
temporal:814d42835dd0fb07ac33
tpl-141266d62cd9c7f98720e78c
null
null
null
null
null
null
null
null
814d42835dd0fb07ac33
counter
focused-temporal-dev-234
01209b2386c2ab3dba056105
{ "security": "satisfies_requirement" }
OpenTitan-expanded:count
counter
f4a4b7d873328e1a45c58a01
connected_control_or_data_path
underflow-saturates:w5:reset1:style1
01209b2386c2ab3dba056105:1
null
null
counterfactual
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
01209b2386c2ab3dba056105
{ "anchors": [ { "line": 123, "sha256": "1e4f9bcf806522b7d4f653d8f02070c5696b825ef053af488201c44c8202b4f7", "text": "assign cnt_d_committed[k] = commit_i ? cnt_d[k] : cnt_q[k];" }, { "line": 114, "sha256": "ea5fed637c8f469101e37f035c0c692a521cdeb87387174aae9c266b01e808ed", ...
dev
temporal-focused:counter:8748f3a44a3d5231
REQUIREMENT Modulo counting on underflow_1: a committed decrement_1 below zero from a nonzero count_1 must wrap to the low bits, not clamp at zero. ASSUMPTIONS Two-state sampled-clock RTL with defined inputs and arbitrary-but-defined initial state. Reset is asserted for the initial clock cycle and inactive thereafter. ...
underflow-saturates:w5:reset1:style1
{ "accepted": true, "alpha_renaming": 1, "antecedent": "reachable_bounded_12_cycles", "antecedent_command": "read_verilog -formal -sv antecedent.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; sat -seq 12 -set-init-def -set-def-inputs -set rst_n 1 -set-at 1 rst_n 0 -prove-asserts -show-ports -dum...
1
21ff24dcc42e3fca5682f15a7484df278c696a7d9cae6aed94a1a78e3104c2c0
temporal_counterfactual
temporal:814d42835dd0fb07ac33
tpl-141266d62cd9c7f98720e78c
null
null
null
null
null
null
null
null
814d42835dd0fb07ac33
counter
focused-temporal-dev-234
01209b2386c2ab3dba056105
{ "security": "violates_requirement" }
OpenTitan-expanded:count
counter
4869d188f33b7073d9bfc85b
connected_control_or_data_path
underflow-saturates:w5:reset1:style1
01209b2386c2ab3dba056105:2
null
null
counterfactual
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
01209b2386c2ab3dba056105
{ "anchors": [ { "line": 123, "sha256": "1e4f9bcf806522b7d4f653d8f02070c5696b825ef053af488201c44c8202b4f7", "text": "assign cnt_d_committed[k] = commit_i ? cnt_d[k] : cnt_q[k];" }, { "line": 114, "sha256": "ea5fed637c8f469101e37f035c0c692a521cdeb87387174aae9c266b01e808ed", ...
dev
temporal-focused:counter:8748f3a44a3d5231
REQUIREMENT Modulo counting on underflow_2: a committed decrement_2 below zero from a nonzero count_2 must wrap to the low bits, not clamp at zero. ASSUMPTIONS Two-state sampled-clock RTL with defined inputs and arbitrary-but-defined initial state. Reset is asserted for the initial clock cycle and inactive thereafter. ...
underflow-saturates:w5:reset1:style1
{ "accepted": true, "alpha_renaming": 2, "assertion_sha256": "78ff572daf41b093250fb65d808e4c3d4a6ac38c327470108eb9397beb65c4ce", "basis": "reachable_counterexample_12_cycles", "bounded_command": "read_verilog -formal -sv checked.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; sat -seq 12 -set-i...
2
bd1d00f0aa002b7b22b0ca5405f706a32789dfdd5dde03fcc5fdd4e2b3cfc5f5
temporal_counterfactual
temporal:814d42835dd0fb07ac33
tpl-3313e18c3330b149999b32f8
null
null
null
null
null
null
null
null
814d42835dd0fb07ac33
counter
focused-temporal-dev-234
01209b2386c2ab3dba056105
{ "security": "satisfies_requirement" }
OpenTitan-expanded:count
counter
5aff5e658280bfcede80bc1f
connected_control_or_data_path
underflow-saturates:w5:reset1:style1
01209b2386c2ab3dba056105:2
null
null
counterfactual
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
01209b2386c2ab3dba056105
{ "anchors": [ { "line": 123, "sha256": "1e4f9bcf806522b7d4f653d8f02070c5696b825ef053af488201c44c8202b4f7", "text": "assign cnt_d_committed[k] = commit_i ? cnt_d[k] : cnt_q[k];" }, { "line": 114, "sha256": "ea5fed637c8f469101e37f035c0c692a521cdeb87387174aae9c266b01e808ed", ...
dev
temporal-focused:counter:8748f3a44a3d5231
REQUIREMENT Modulo counting on underflow_2: a committed decrement_2 below zero from a nonzero count_2 must wrap to the low bits, not clamp at zero. ASSUMPTIONS Two-state sampled-clock RTL with defined inputs and arbitrary-but-defined initial state. Reset is asserted for the initial clock cycle and inactive thereafter. ...
underflow-saturates:w5:reset1:style1
{ "accepted": true, "alpha_renaming": 2, "antecedent": "reachable_bounded_12_cycles", "antecedent_command": "read_verilog -formal -sv antecedent.v; prep -top topmodule; async2sync; dffunmap; memory_map; opt; sat -seq 12 -set-init-def -set-def-inputs -set rst_n 1 -set-at 1 rst_n 0 -prove-asserts -show-ports -dum...
2
bd1d00f0aa002b7b22b0ca5405f706a32789dfdd5dde03fcc5fdd4e2b3cfc5f5
temporal_counterfactual
temporal:814d42835dd0fb07ac33
tpl-3313e18c3330b149999b32f8
null
null
null
null
null
null
null
null
814d42835dd0fb07ac33
counter
focused-temporal-dev-234
01209b2386c2ab3dba056105
{ "security": "insufficient_context" }
OpenTitan-expanded:count
counter
dea59d4286885e88ab19a734
connected_control_or_data_path
underflow-saturates:w5:reset1:style1
01209b2386c2ab3dba056105:2
null
null
counterfactual
{ "security": { "criteria": [ "satisfies_requirement", "violates_requirement", "insufficient_context" ], "instructions": "Assess the RTL against the requirement under the supplied assumptions. Use satisfies_requirement when the property holds and violates_requirement when a reachable cou...
01209b2386c2ab3dba056105
{ "anchors": [ { "line": 123, "sha256": "1e4f9bcf806522b7d4f653d8f02070c5696b825ef053af488201c44c8202b4f7", "text": "assign cnt_d_committed[k] = commit_i ? cnt_d[k] : cnt_q[k];" }, { "line": 114, "sha256": "ea5fed637c8f469101e37f035c0c692a521cdeb87387174aae9c266b01e808ed", ...
dev
temporal-focused:counter:8748f3a44a3d5231
REQUIREMENT Modulo counting on underflow_2: a committed decrement_2 below zero from a nonzero count_2 must wrap to the low bits, not clamp at zero. ASSUMPTIONS Two-state sampled-clock RTL with defined inputs and arbitrary-but-defined initial state. Reset is asserted for the initial clock cycle and inactive thereafter. ...
underflow-saturates:w5:reset1:style1
{ "accepted": true, "alpha_renaming": 2, "bad_completion": "byte_exact", "bad_fill_sha256": "4dd61786d76262fd89d98aaea437cbb4c9f53a28fc0f56dec7f25191bff33d62", "basis": "exact_shared_hole_completions", "good_completion": "byte_exact", "good_fill_sha256": "17aa018d9ba40c4e233c5b39917a3ad8cab8f137272785d992...
2
bd1d00f0aa002b7b22b0ca5405f706a32789dfdd5dde03fcc5fdd4e2b3cfc5f5
temporal_counterfactual
temporal:814d42835dd0fb07ac33
tpl-3313e18c3330b149999b32f8
null
null
null
null
null
null
null
null
End of preview.

SiliconShield RTL Security Benchmark v1

5,589 requirement-conditioned RTL security decisions across 11 design areas. Each row supplies RTL, a security requirement, execution assumptions, and one of three labels: satisfies_requirement, violates_requirement, or insufficient_context. Labels are solver-established (Yosys/Icarus/Verilator evidence); missing-context rows carry opposing completions. Every area is label-balanced.

Prompt contract: all rows use siliconshield-requirement-context-v1 (identical judging instructions; see manifest.json for the digest).

Areas and sizes

Area Rows Contents
local-safety-cwe 2610 Register hold/update safety, ~32 hardware CWEs
requirement-clarity 756 Same plain-English text, all 3 verdicts
transfer-pairs 621 Locks, privilege, clearing, windows, priority
write-paths 432 Multi-writer and debug-path authorization
guard-semantics 432 Authorization policy interpretation
interrupt-wake 234 Sticky/pending, masks, edge-vs-level, rearm
input-filter 162 Filter update, saturation, timed behavior
fifo 108 Occupancy, backpressure, capture, hold
counter 108 Saturation, sampled steps, commit/hold
ot-access-control 108 I2C address decode, ADC event binding
arbitration 18 Grant handshake, tree acceptance

What this benchmark covers

Peripheral and register access safety (locks, privilege, permissions, address windows, multi-writer and debug paths); FIFO/queue and counter behavior; interrupt and wake handling; reset and clearing properties; state hold-vs-update correctness; and requirement-ambiguity handling through explicit insufficient-context cases.

What it does NOT cover

FSM bugs (illegal states, deadlock); clock/reset-domain crossing; bus/protocol compliance (AXI/TileLink); cryptography and randomness; firmware/hardware interfaces; power management; DMA safety; secure boot and root-of-trust flows; multi-level privilege escalation; timing side channels. All rows are small bounded fragments with a single requirement -- no full IPs, SoC-level interactions, or multi-requirement analysis. Requirement wording style varies by source row (plain English in newer sets, equation-like in older ones).

Intended use

Score a checkpoint per area and report accuracy, per-class recall, false-safe count, and whole-triplet correctness. Do not train on these rows and report the result as independent evidence.

Circularity warning: siliconshield-rtl-contract-2 was selected on the fifo/counter/arbitration subset, so its scores there are an upper bound, not independent proof.

Files

  • data/benchmark.jsonl: 5,589 rows (sha256 46d96ce0…, see manifest).
  • manifest.json: sources, area audit, train-overlap audit (zero overlap with the Contract-2 training files), redaction record.

Row keys: id, state (RTL), questions (judging prompt), expected.security (label), mechanism_id, family_id, benchmark_area, benchmark_source, plus provenance/validation records. Tool paths in validation records are redacted to <tools>/<basename>.

Provenance and license

Pooled from development-grade SiliconShield populations; no sealed qualification, calibration, or test data included. OpenTitan-derived fragments retain their upstream Apache-2.0 terms; the compilation is offered under Apache-2.0.

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