SKLP-EDA-LAB/CircuitNet3.0

CircuitNet 3.0 Dataset

This is the public dataset release for CircuitNet 3.0: A Multi-Modal Dataset with Task-Oriented Augmentation for AI-Driven Circuit Design.

The code and documentation companion lives in sklp-eda-lab/iclr-circuitnet_3.0.

CircuitNet 3.0 is a multi-stage, multi-modal dataset for AI-driven circuit design. It is intended to support early-stage timing and power prediction, along with cross-stage representation learning over RTL, netlist, and layout-oriented artifacts.

Current release

At the time of writing, the public archive is packaged as circuitNetv3.zip. The archive currently exposes:

• dataset/RTL/ source RTL modules
• dataset/Netlist/ synthesized netlist artifacts
• dataset/Final/*/feature.json gate-level feature metadata
• dataset/Final/*/final_netlist.v final synthesized netlists
• dataset/Final/*/power_summary.txt power summaries

Layout artifacts are large and are being uploaded incrementally. If a layout subset you need is not yet available, or if you would like to request a specific large layout package, please contact wangmingjun000613@gmail.com.

Dataset summary

• 8,659 validated open-source RTL designs
• 15,863 total design instances after task-oriented augmentation
• Source-level train/validation/test partitioning, with augmented variants of test sources excluded from train/val to avoid leakage
• Timing labels: AT, WNS, and TNS
• Power labels: total power summaries

What is intentionally excluded

• Commercial PDK files, standard-cell libraries, and other restricted technology collateral
• Proprietary EDA binaries or license-dependent artifacts
• Redundant examples that do not improve downstream use or reproducibility

Update policy

This dataset card will be updated as new artifacts are uploaded. The Hugging Face hub is the source of truth for the latest available files.

Citation

If you use this dataset, please cite the paper above.