File size: 1,258 Bytes
f5dbfe6 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | from amaranth import *
from amaranth.sim import Simulator
from amaranth.lib.memory import Memory
from amaranth.back import verilog
from amaranth.lib.wiring import In, Out
from amaranth.lib import wiring
# minimal rtl block for testing, just some bram
class test_block(wiring.Component):
def __init__(self, size) -> None:
super().__init__({
"write_data": In(32),
"write_enable": In(1),
"address": In(16),
"read_data": Out(32)
})
self.size = size
def elaborate(self, platform):
m = Module()
m.submodules.memory = self.memory = Memory(shape=unsigned(32), depth=self.size, init=[]) # small memory for testing
self.externalReadPort = self.memory.read_port(domain="sync_100")
self.externalWritePort = self.memory.write_port(domain="sync_100")
# connect external memory interfaces
m.d.comb += self.externalReadPort.addr.eq(self.address)
m.d.comb += self.externalWritePort.addr.eq(self.address)
m.d.comb += self.externalWritePort.data.eq(self.write_data)
m.d.comb += self.externalWritePort.en.eq(self.write_enable)
m.d.comb += self.read_data.eq(self.externalReadPort.data)
return m
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