BinPrey/x86-instruction-test-vectors

x86-64 Instruction Test Vectors

Ground truth behavior of individual x86-64 instructions, captured by executing every encoding on real hardware and recording the resulting register and flag state. This is measured silicon behavior, not a model and not an emulator, so it also reflects implementation specific results such as the values an instruction leaves in flags that the architecture documents as undefined.

How it was generated

Each test case is produced by the x86Tester tool. For a single instruction encoding it sets a known input register and flag state, runs the instruction inside a debugger harness (the Windows debug API on Windows, ptrace on Linux), and reads back the resulting state. Inputs are swept so that every reachable output bit is exercised.

Instructions execute at a fixed code base address of 0x04000001. Any address dependent result, for example a RIP relative lea, already has its computed output recorded in the outputs.

Scope

Some instructions may be missing and coverage will be expanded over time.

Each CPU is stored as its own parquet file under data/ and exposed as a separate config, named by the processor brand string together with its family, model and stepping, so results from different silicon never collide. Select a config to view a single processor.

Columns

• mnemonic: instruction mnemonic.
• asm: full disassembly of the encoding.
• encoding: instruction bytes as uppercase hex.
• inputs: JSON object, stored as a string, mapping each register name or flags to its value before execution.
• outputs: JSON object, stored as a string, mapping each register name or flags to its value after execution. Empty when the instruction faulted.
• exception: the fault that was raised, if any, for example INT_DIVIDE_ERROR or INT_OVERFLOW, otherwise null.

Register and flag values are hex of the raw little endian bytes. For example a flags value of 01000000 is 0x00000001, the carry flag.

Source

Generated by x86Tester.