bitserial-modmul-v2

Submission for the SAIR Modular Arithmetic Challenge. 32-bit cell, tiers 1-4 (overall 0.412). Runs on CPU/Mac. Smaller/faster variant for testing.

One shared, p-conditioned recurrent cell in a fixed bit-serial Horner loop computes (a * b) mod p; the cell learns the per-step transition s' = (2s + d*x) mod p (including the modular wrap) and the loop only sequences bits. Randomising the weights collapses accuracy to 0 (the capability is in the trained parameters). entry_class model.BitSerialReducer, output_base 2.

Limitation (honest)

This model passes the random-operand benchmark but is not exact. On structured inputs (powers of two and other long doubling chains) the per-step reduction drifts for some primes beyond about 500 steps, reproducing the Neural GPU limitation (Price, Zaremba, Sutskever 2016). The benchmark tiers reflect average-case accuracy on the official scorer's random-operand distribution, not worst-case exactness of the underlying modular-multiplication operator.